clk: qcom: hfpll: Add MSM8976 PLL data
Add PLL configuration for MSM8976 SoC, this SoC offers 3 HFPLL. Small cluster offers two presets for 652-902Mhz range and 902Mhz-1.47Ghz. For simplicity only add second range as smaller frequencies can be obtained via apcs divider or safe parent this also saves us a hassle of reconfiguring VCO bit and config_val. A72 and CCI cluster only use single frequency range with their outputs/post_dividers/vco_bits being static. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230812112534.8610-6-a39.skl@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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@ -32,8 +32,62 @@ static const struct hfpll_data hdata = {
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.max_rate = 2900000000UL,
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};
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static const struct hfpll_data msm8976_a53 = {
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.mode_reg = 0x00,
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.l_reg = 0x04,
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.m_reg = 0x08,
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.n_reg = 0x0c,
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.user_reg = 0x10,
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.config_reg = 0x14,
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.config_val = 0x341600,
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.status_reg = 0x1c,
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.lock_bit = 16,
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.l_val = 0x35,
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.user_val = 0x109,
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.min_rate = 902400000UL,
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.max_rate = 1478400000UL,
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};
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static const struct hfpll_data msm8976_a72 = {
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.mode_reg = 0x00,
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.l_reg = 0x04,
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.m_reg = 0x08,
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.n_reg = 0x0c,
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.user_reg = 0x10,
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.config_reg = 0x14,
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.config_val = 0x4e0405d,
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.status_reg = 0x1c,
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.lock_bit = 16,
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.l_val = 0x3e,
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.user_val = 0x100109,
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.min_rate = 940800000UL,
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.max_rate = 2016000000UL,
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};
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static const struct hfpll_data msm8976_cci = {
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.mode_reg = 0x00,
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.l_reg = 0x04,
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.m_reg = 0x08,
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.n_reg = 0x0c,
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.user_reg = 0x10,
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.config_reg = 0x14,
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.config_val = 0x141400,
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.status_reg = 0x1c,
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.lock_bit = 16,
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.l_val = 0x20,
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.user_val = 0x100109,
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.min_rate = 556800000UL,
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.max_rate = 902400000UL,
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};
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static const struct of_device_id qcom_hfpll_match_table[] = {
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{ .compatible = "qcom,hfpll", .data = &hdata },
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{ .compatible = "qcom,msm8976-hfpll-a53", .data = &msm8976_a53 },
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{ .compatible = "qcom,msm8976-hfpll-a72", .data = &msm8976_a72 },
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{ .compatible = "qcom,msm8976-hfpll-cci", .data = &msm8976_cci },
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{ }
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};
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MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
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