iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

drm/xe: Don't hardcode GuC's MOCS index in register header

Browse Source 
Although PVC is currently the only platform that needs us to program a
GuC register with the index of an uncached MOCS entry, it's likely other
platforms will need this in the future.  Rather than hardcoding PVC's
index into the register header, we should just pull the appropriate
index from gt->mocs.uc_index to future-proof the code.

Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Link: https://lore.kernel.org/r/20230602235210.1314028-3-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Matt Roper 2023-06-02 16:52:10 -07:00 committed by Rodrigo Vivi
parent 17a6726c3d
commit 1fce9a6f69
2 changed files with 2 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/drm/xe/regs/xe_guc_regs.h
View File

@ -45,10 +45,7 @@
#define GUC_WOPCM_SIZE_LOCKED REG_BIT(0)
#define GUC_SHIM_CONTROL XE_REG(0xc064)
#define PVC_GUC_MOCS_INDEX_MASK REG_GENMASK(25, 24)
#define PVC_GUC_MOCS_UC_INDEX 1
#define PVC_GUC_MOCS_INDEX(index) REG_FIELD_PREP(PVC_GUC_MOCS_INDEX_MASK, \
index)
#define GUC_MOCS_INDEX_MASK REG_GENMASK(25, 24)
#define GUC_SHIM_WC_ENABLE REG_BIT(21)
#define GUC_ENABLE_MIA_CLOCK_GATING REG_BIT(15)
#define GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA REG_BIT(10)

2
drivers/gpu/drm/xe/xe_guc.c
View File

@ -328,7 +328,7 @@ static void guc_prepare_xfer(struct xe_guc *guc)
GUC_ENABLE_MIA_CACHING;
if (xe->info.platform == XE_PVC)
shim_flags |= PVC_GUC_MOCS_INDEX(PVC_GUC_MOCS_UC_INDEX);
shim_flags |= REG_FIELD_PREP(GUC_MOCS_INDEX_MASK, gt->mocs.uc_index);
/* Must program this register before loading the ucode with DMA */
xe_mmio_write32(gt, GUC_SHIM_CONTROL, shim_flags);