kaiser: x86_cr3_pcid_noflush and x86_cr3_pcid_user
Mostly this commit is just unshouting X86_CR3_PCID_KERN_VAR and X86_CR3_PCID_USER_VAR: we usually name variables in lower-case. But why does x86_cr3_pcid_noflush need to be __aligned(PAGE_SIZE)? Ah, it's a leftover from when kaiser_add_user_map() once complained about mapping the same page twice. Make it __read_mostly instead. (I'm a little uneasy about all the unrelated data which shares its page getting user-mapped too, but that was so before, and not a big deal: though we call it user-mapped, it's not mapped with _PAGE_USER.) And there is a little change around the two calls to do_nmi(). Previously they set the NOFLUSH bit (if PCID supported) when forcing to kernel context before do_nmi(); now they also have the NOFLUSH bit set (if PCID supported) when restoring context after: nothing done in do_nmi() should require a TLB to be flushed here. Signed-off-by: Hugh Dickins <hughd@google.com> Acked-by: Jiri Kosina <jkosina@suse.cz> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
3b4ce0e1a1
commit
20268a10ff
@ -1290,11 +1290,11 @@ ENTRY(nmi)
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/* Unconditionally use kernel CR3 for do_nmi() */
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/* Unconditionally use kernel CR3 for do_nmi() */
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/* %rax is saved above, so OK to clobber here */
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/* %rax is saved above, so OK to clobber here */
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movq %cr3, %rax
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movq %cr3, %rax
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/* If PCID enabled, NOFLUSH now and NOFLUSH on return */
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orq x86_cr3_pcid_noflush, %rax
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pushq %rax
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pushq %rax
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/* mask off "user" bit of pgd address and 12 PCID bits: */
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/* mask off "user" bit of pgd address and 12 PCID bits: */
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andq $(~(X86_CR3_PCID_ASID_MASK | KAISER_SHADOW_PGD_OFFSET)), %rax
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andq $(~(X86_CR3_PCID_ASID_MASK | KAISER_SHADOW_PGD_OFFSET)), %rax
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/* Add back kernel PCID and "no flush" bit */
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orq X86_CR3_PCID_KERN_VAR, %rax
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movq %rax, %cr3
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movq %rax, %cr3
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#endif
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#endif
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call do_nmi
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call do_nmi
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@ -1534,11 +1534,11 @@ end_repeat_nmi:
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/* Unconditionally use kernel CR3 for do_nmi() */
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/* Unconditionally use kernel CR3 for do_nmi() */
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/* %rax is saved above, so OK to clobber here */
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/* %rax is saved above, so OK to clobber here */
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movq %cr3, %rax
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movq %cr3, %rax
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/* If PCID enabled, NOFLUSH now and NOFLUSH on return */
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orq x86_cr3_pcid_noflush, %rax
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pushq %rax
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pushq %rax
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/* mask off "user" bit of pgd address and 12 PCID bits: */
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/* mask off "user" bit of pgd address and 12 PCID bits: */
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andq $(~(X86_CR3_PCID_ASID_MASK | KAISER_SHADOW_PGD_OFFSET)), %rax
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andq $(~(X86_CR3_PCID_ASID_MASK | KAISER_SHADOW_PGD_OFFSET)), %rax
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/* Add back kernel PCID and "no flush" bit */
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orq X86_CR3_PCID_KERN_VAR, %rax
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movq %rax, %cr3
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movq %rax, %cr3
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#endif
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#endif
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@ -25,7 +25,7 @@
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.macro _SWITCH_TO_KERNEL_CR3 reg
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.macro _SWITCH_TO_KERNEL_CR3 reg
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movq %cr3, \reg
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movq %cr3, \reg
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andq $(~(X86_CR3_PCID_ASID_MASK | KAISER_SHADOW_PGD_OFFSET)), \reg
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andq $(~(X86_CR3_PCID_ASID_MASK | KAISER_SHADOW_PGD_OFFSET)), \reg
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orq X86_CR3_PCID_KERN_VAR, \reg
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orq x86_cr3_pcid_noflush, \reg
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movq \reg, %cr3
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movq \reg, %cr3
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.endm
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.endm
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@ -37,11 +37,10 @@ movq \reg, %cr3
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* not enabled): so that the one register can update both memory and cr3.
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* not enabled): so that the one register can update both memory and cr3.
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*/
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*/
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movq %cr3, \reg
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movq %cr3, \reg
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andq $(~(X86_CR3_PCID_ASID_MASK | KAISER_SHADOW_PGD_OFFSET)), \reg
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orq PER_CPU_VAR(x86_cr3_pcid_user), \reg
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orq PER_CPU_VAR(X86_CR3_PCID_USER_VAR), \reg
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js 9f
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js 9f
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/* FLUSH this time, reset to NOFLUSH for next time (if PCID enabled) */
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/* FLUSH this time, reset to NOFLUSH for next time (if PCID enabled) */
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movb \regb, PER_CPU_VAR(X86_CR3_PCID_USER_VAR+7)
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movb \regb, PER_CPU_VAR(x86_cr3_pcid_user+7)
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9:
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9:
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movq \reg, %cr3
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movq \reg, %cr3
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.endm
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.endm
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@ -94,8 +93,8 @@ movq PER_CPU_VAR(unsafe_stack_register_backup), %rax
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*/
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*/
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DECLARE_PER_CPU_USER_MAPPED(unsigned long, unsafe_stack_register_backup);
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DECLARE_PER_CPU_USER_MAPPED(unsigned long, unsafe_stack_register_backup);
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extern unsigned long X86_CR3_PCID_KERN_VAR;
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extern unsigned long x86_cr3_pcid_noflush;
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DECLARE_PER_CPU(unsigned long, X86_CR3_PCID_USER_VAR);
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DECLARE_PER_CPU(unsigned long, x86_cr3_pcid_user);
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extern char __per_cpu_user_mapped_start[], __per_cpu_user_mapped_end[];
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extern char __per_cpu_user_mapped_start[], __per_cpu_user_mapped_end[];
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@ -29,8 +29,8 @@ DEFINE_PER_CPU_USER_MAPPED(unsigned long, unsafe_stack_register_backup);
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* This is also handy because systems that do not support PCIDs
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* This is also handy because systems that do not support PCIDs
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* just end up or'ing a 0 into their CR3, which does no harm.
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* just end up or'ing a 0 into their CR3, which does no harm.
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*/
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*/
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__aligned(PAGE_SIZE) unsigned long X86_CR3_PCID_KERN_VAR;
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unsigned long x86_cr3_pcid_noflush __read_mostly;
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DEFINE_PER_CPU(unsigned long, X86_CR3_PCID_USER_VAR);
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DEFINE_PER_CPU(unsigned long, x86_cr3_pcid_user);
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/*
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/*
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* At runtime, the only things we map are some things for CPU
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* At runtime, the only things we map are some things for CPU
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@ -304,7 +304,8 @@ void __init kaiser_init(void)
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sizeof(gate_desc) * NR_VECTORS,
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sizeof(gate_desc) * NR_VECTORS,
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__PAGE_KERNEL);
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__PAGE_KERNEL);
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kaiser_add_user_map_early(&X86_CR3_PCID_KERN_VAR, PAGE_SIZE,
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kaiser_add_user_map_early(&x86_cr3_pcid_noflush,
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sizeof(x86_cr3_pcid_noflush),
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__PAGE_KERNEL);
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__PAGE_KERNEL);
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}
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}
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@ -384,8 +385,8 @@ void kaiser_setup_pcid(void)
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* These variables are used by the entry/exit
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* These variables are used by the entry/exit
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* code to change PCID and pgd and TLB flushing.
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* code to change PCID and pgd and TLB flushing.
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*/
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*/
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X86_CR3_PCID_KERN_VAR = kern_cr3;
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x86_cr3_pcid_noflush = kern_cr3;
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this_cpu_write(X86_CR3_PCID_USER_VAR, user_cr3);
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this_cpu_write(x86_cr3_pcid_user, user_cr3);
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}
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}
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/*
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/*
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@ -395,7 +396,7 @@ void kaiser_setup_pcid(void)
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*/
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*/
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void kaiser_flush_tlb_on_return_to_user(void)
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void kaiser_flush_tlb_on_return_to_user(void)
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{
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{
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this_cpu_write(X86_CR3_PCID_USER_VAR,
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this_cpu_write(x86_cr3_pcid_user,
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X86_CR3_PCID_USER_FLUSH | KAISER_SHADOW_PGD_OFFSET);
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X86_CR3_PCID_USER_FLUSH | KAISER_SHADOW_PGD_OFFSET);
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}
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}
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EXPORT_SYMBOL(kaiser_flush_tlb_on_return_to_user);
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EXPORT_SYMBOL(kaiser_flush_tlb_on_return_to_user);
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