net/mlx5: Define interface bits for fencing UMR wqe
commit 1410a90ae449061b7e1ae19d275148f36948801b upstream. HW can implement UMR wqe re-transmission in various ways. Thus, add HCA cap to distinguish the needed fence for UMR to make sure that the wqe wouldn't fail on mkey checks. Signed-off-by: Max Gurtovoy <maxg@mellanox.com> Acked-by: Leon Romanovsky <leon@kernel.org> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Doug Ledford <dledford@redhat.com> Cc: Marta Rybczynska <mrybczyn@kalray.eu> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -737,6 +737,12 @@ enum {
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MLX5_CAP_PORT_TYPE_ETH = 0x1,
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};
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enum {
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MLX5_CAP_UMR_FENCE_STRONG = 0x0,
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MLX5_CAP_UMR_FENCE_SMALL = 0x1,
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MLX5_CAP_UMR_FENCE_NONE = 0x2,
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};
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struct mlx5_ifc_cmd_hca_cap_bits {
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u8 reserved_at_0[0x80];
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@ -838,7 +844,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
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u8 striding_rq[0x1];
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u8 reserved_at_201[0x2];
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u8 ipoib_basic_offloads[0x1];
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u8 reserved_at_205[0xa];
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u8 reserved_at_205[0x5];
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u8 umr_fence[0x2];
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u8 reserved_at_20c[0x3];
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u8 drain_sigerr[0x1];
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u8 cmdif_checksum[0x2];
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u8 sigerr_cqe[0x1];
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