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net/mlx5: Align mlx5_irq structure

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mlx5_irq structure have holes due to incorrect position of fields in it.
Make them naturally align.

pahole output after alignment:
struct mlx5_irq {
        struct atomic_notifier_head nh;                  /*     0    72 */
        /* --- cacheline 1 boundary (64 bytes) was 8 bytes ago --- */
        cpumask_var_t              mask;                 /*    72     8 */
        char                       name[32];             /*    80    32 */
        struct mlx5_irq_pool *     pool;                 /*   112     8 */
        struct kref                kref;                 /*   120     4 */
        u32                        index;                /*   124     4 */
        /* --- cacheline 2 boundary (128 bytes) --- */
        int                        irqn;                 /*   128     4 */

        /* size: 136, cachelines: 3, members: 7 */
        /* padding: 4 */
        /* last cacheline: 8 bytes */

};

Signed-off-by: Shay Drory <shayd@nvidia.com>
Reviewed-by: Parav Pandit <parav@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
This commit is contained in:
Shay Drory 2021-06-16 18:58:26 +03:00 committed by Saeed Mahameed
parent 8e792700b9
commit 211f4f99ed
1 changed files with 3 additions and 3 deletions
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6
drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c
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@ -28,13 +28,13 @@
#define MLX5_EQ_REFS_PER_IRQ (2) #define MLX5_EQ_REFS_PER_IRQ (2)
struct mlx5_irq { struct mlx5_irq {
u32 index;
struct atomic_notifier_head nh; struct atomic_notifier_head nh;
cpumask_var_t mask; cpumask_var_t mask;
char name[MLX5_MAX_IRQ_NAME]; char name[MLX5_MAX_IRQ_NAME];
struct kref kref;
int irqn;
struct mlx5_irq_pool *pool; struct mlx5_irq_pool *pool;
struct kref kref;
u32 index;
int irqn;
}; };
struct mlx5_irq_pool { struct mlx5_irq_pool {