iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

drm/amdgpu: replace reset_error_count with amdgpu_ras_reset_error_count

Browse Source 
Simplify the code.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tao Zhou 2023-10-18 17:57:25 +08:00 committed by Alex Deucher
parent 9d7a965e22
commit 21226f02d7
5 changed files with 10 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
View File

@ -3578,9 +3578,7 @@ static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
if (adev->asic_reset_res)
goto fail;
if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops &&
adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count)
adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev);
amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB);
} else {
task_barrier_full(&hive->tb);
@ -5201,9 +5199,7 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle,
if (!r && amdgpu_ras_intr_triggered()) {
list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
if (tmp_adev->mmhub.ras && tmp_adev->mmhub.ras->ras_block.hw_ops &&
tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count)
tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(tmp_adev);
amdgpu_ras_reset_error_count(tmp_adev, AMDGPU_RAS_BLOCK__MMHUB);
}
amdgpu_ras_intr_cleared();

4
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
View File

@ -908,7 +908,7 @@ static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, struct ras_comm
adev->gmc.xgmi.num_physical_nodes == 0)
return 0;
adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev);
amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL);
return amdgpu_ras_block_late_init(adev, ras_block);
}
@ -1075,7 +1075,7 @@ static void amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,
break;
}
adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev);
amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL);
err_data->ue_count += ue_cnt;
err_data->ce_count += ce_cnt;

9
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
View File

@ -1587,13 +1587,8 @@ static int gmc_v9_0_late_init(void *handle)
}
if (!amdgpu_persistent_edc_harvesting_supported(adev)) {
if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops &&
adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count)
adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev);
if (adev->hdp.ras && adev->hdp.ras->ras_block.hw_ops &&
adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count)
adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count(adev);
amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB);
amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__HDP);
}
r = amdgpu_gmc_ras_late_init(adev);

7
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
View File

@ -1749,11 +1749,8 @@ static int sdma_v4_0_late_init(void *handle)
sdma_v4_0_setup_ulv(adev);
if (!amdgpu_persistent_edc_harvesting_supported(adev)) {
if (adev->sdma.ras && adev->sdma.ras->ras_block.hw_ops &&
adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count)
adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count(adev);
}
if (!amdgpu_persistent_edc_harvesting_supported(adev))
amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__SDMA);
return 0;
}

7
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
View File

@ -1276,11 +1276,8 @@ static int sdma_v4_4_2_late_init(void *handle)
.cb = sdma_v4_4_2_process_ras_data_cb,
};
#endif
if (!amdgpu_persistent_edc_harvesting_supported(adev)) {
if (adev->sdma.ras && adev->sdma.ras->ras_block.hw_ops &&
adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count)
adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count(adev);
}
if (!amdgpu_persistent_edc_harvesting_supported(adev))
amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__SDMA);
return 0;
}