omap_hwmod: use a terminator record with omap_hwmod_mpu_irqs arrays
Previously, struct omap_hwmod_mpu_irqs arrays were unterminated; and users of these arrays used the ARRAY_SIZE() macro to determine the length of the array. However, ARRAY_SIZE() only works when the array is in the same scope as the macro user. So far this hasn't been a problem. However, to reduce duplicated data, a subsequent patch will move common data to a separate, shared file. When this is done, ARRAY_SIZE() will no longer be usable. This patch removes ARRAY_SIZE() usage for struct omap_hwmod_mpu_irqs arrays and uses a sentinel value (irq == -1) as the array terminator instead. Signed-off-by: Paul Walmsley <paul@pwsan.com>
This commit is contained in:
parent
ded11383fc
commit
212738a449
@ -678,6 +678,29 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
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}
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}
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/**
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* _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh
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* @oh: struct omap_hwmod *oh
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*
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* Count and return the number of MPU IRQs associated with the hwmod
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* @oh. Used to allocate struct resource data. Returns 0 if @oh is
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* NULL.
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*/
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static int _count_mpu_irqs(struct omap_hwmod *oh)
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{
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struct omap_hwmod_irq_info *ohii;
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int i = 0;
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if (!oh || !oh->mpu_irqs)
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return 0;
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do {
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ohii = &oh->mpu_irqs[i++];
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} while (ohii->irq != -1);
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return i;
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}
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/**
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* _count_ocp_if_addr_spaces - count the number of address space entries for @oh
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* @oh: struct omap_hwmod *oh
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@ -1964,7 +1987,7 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
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{
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int ret, i;
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ret = oh->mpu_irqs_cnt + oh->sdma_reqs_cnt;
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ret = _count_mpu_irqs(oh) + oh->sdma_reqs_cnt;
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for (i = 0; i < oh->slaves_cnt; i++)
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ret += _count_ocp_if_addr_spaces(oh->slaves[i]);
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@ -1984,12 +2007,13 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
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*/
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int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
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{
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int i, j;
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int i, j, mpu_irqs_cnt;
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int r = 0;
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/* For each IRQ, DMA, memory area, fill in array.*/
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for (i = 0; i < oh->mpu_irqs_cnt; i++) {
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mpu_irqs_cnt = _count_mpu_irqs(oh);
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for (i = 0; i < mpu_irqs_cnt; i++) {
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(res + r)->name = (oh->mpu_irqs + i)->name;
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(res + r)->start = (oh->mpu_irqs + i)->irq;
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(res + r)->end = (oh->mpu_irqs + i)->irq;
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@ -296,6 +296,7 @@ static struct omap_hwmod_class omap2420_timer_hwmod_class = {
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static struct omap_hwmod omap2420_timer1_hwmod;
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static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = {
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{ .irq = 37, },
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{ .irq = -1 }
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};
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static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
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@ -325,7 +326,6 @@ static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
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static struct omap_hwmod omap2420_timer1_hwmod = {
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.name = "timer1",
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.mpu_irqs = omap2420_timer1_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer1_mpu_irqs),
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.main_clk = "gpt1_fck",
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.prcm = {
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.omap2 = {
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@ -346,6 +346,7 @@ static struct omap_hwmod omap2420_timer1_hwmod = {
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static struct omap_hwmod omap2420_timer2_hwmod;
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static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = {
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{ .irq = 38, },
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{ .irq = -1 }
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};
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@ -367,7 +368,6 @@ static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
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static struct omap_hwmod omap2420_timer2_hwmod = {
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.name = "timer2",
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.mpu_irqs = omap2420_timer2_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer2_mpu_irqs),
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.main_clk = "gpt2_fck",
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.prcm = {
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.omap2 = {
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@ -388,6 +388,7 @@ static struct omap_hwmod omap2420_timer2_hwmod = {
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static struct omap_hwmod omap2420_timer3_hwmod;
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static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = {
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{ .irq = 39, },
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{ .irq = -1 }
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};
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/* l4_core -> timer3 */
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@ -408,7 +409,6 @@ static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
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static struct omap_hwmod omap2420_timer3_hwmod = {
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.name = "timer3",
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.mpu_irqs = omap2420_timer3_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer3_mpu_irqs),
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.main_clk = "gpt3_fck",
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.prcm = {
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.omap2 = {
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@ -429,6 +429,7 @@ static struct omap_hwmod omap2420_timer3_hwmod = {
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static struct omap_hwmod omap2420_timer4_hwmod;
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static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = {
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{ .irq = 40, },
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{ .irq = -1 }
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};
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/* l4_core -> timer4 */
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@ -449,7 +450,6 @@ static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
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static struct omap_hwmod omap2420_timer4_hwmod = {
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.name = "timer4",
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.mpu_irqs = omap2420_timer4_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer4_mpu_irqs),
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.main_clk = "gpt4_fck",
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.prcm = {
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.omap2 = {
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@ -470,6 +470,7 @@ static struct omap_hwmod omap2420_timer4_hwmod = {
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static struct omap_hwmod omap2420_timer5_hwmod;
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static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = {
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{ .irq = 41, },
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{ .irq = -1 }
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};
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/* l4_core -> timer5 */
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@ -490,7 +491,6 @@ static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
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static struct omap_hwmod omap2420_timer5_hwmod = {
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.name = "timer5",
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.mpu_irqs = omap2420_timer5_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer5_mpu_irqs),
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.main_clk = "gpt5_fck",
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.prcm = {
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.omap2 = {
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@ -512,6 +512,7 @@ static struct omap_hwmod omap2420_timer5_hwmod = {
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static struct omap_hwmod omap2420_timer6_hwmod;
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static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = {
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{ .irq = 42, },
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{ .irq = -1 }
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};
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/* l4_core -> timer6 */
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@ -532,7 +533,6 @@ static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
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static struct omap_hwmod omap2420_timer6_hwmod = {
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.name = "timer6",
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.mpu_irqs = omap2420_timer6_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer6_mpu_irqs),
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.main_clk = "gpt6_fck",
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.prcm = {
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.omap2 = {
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@ -553,6 +553,7 @@ static struct omap_hwmod omap2420_timer6_hwmod = {
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static struct omap_hwmod omap2420_timer7_hwmod;
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static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = {
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{ .irq = 43, },
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{ .irq = -1 }
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};
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/* l4_core -> timer7 */
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@ -573,7 +574,6 @@ static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
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static struct omap_hwmod omap2420_timer7_hwmod = {
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.name = "timer7",
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.mpu_irqs = omap2420_timer7_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer7_mpu_irqs),
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.main_clk = "gpt7_fck",
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.prcm = {
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.omap2 = {
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@ -594,6 +594,7 @@ static struct omap_hwmod omap2420_timer7_hwmod = {
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static struct omap_hwmod omap2420_timer8_hwmod;
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static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = {
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{ .irq = 44, },
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{ .irq = -1 }
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};
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/* l4_core -> timer8 */
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@ -614,7 +615,6 @@ static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
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static struct omap_hwmod omap2420_timer8_hwmod = {
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.name = "timer8",
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.mpu_irqs = omap2420_timer8_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer8_mpu_irqs),
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.main_clk = "gpt8_fck",
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.prcm = {
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.omap2 = {
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@ -635,6 +635,7 @@ static struct omap_hwmod omap2420_timer8_hwmod = {
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static struct omap_hwmod omap2420_timer9_hwmod;
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static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = {
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{ .irq = 45, },
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{ .irq = -1 }
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};
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/* l4_core -> timer9 */
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@ -655,7 +656,6 @@ static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
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static struct omap_hwmod omap2420_timer9_hwmod = {
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.name = "timer9",
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.mpu_irqs = omap2420_timer9_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer9_mpu_irqs),
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.main_clk = "gpt9_fck",
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.prcm = {
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.omap2 = {
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@ -676,6 +676,7 @@ static struct omap_hwmod omap2420_timer9_hwmod = {
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static struct omap_hwmod omap2420_timer10_hwmod;
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static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = {
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{ .irq = 46, },
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{ .irq = -1 }
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};
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/* l4_core -> timer10 */
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@ -696,7 +697,6 @@ static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
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static struct omap_hwmod omap2420_timer10_hwmod = {
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.name = "timer10",
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.mpu_irqs = omap2420_timer10_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer10_mpu_irqs),
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.main_clk = "gpt10_fck",
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.prcm = {
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.omap2 = {
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@ -717,6 +717,7 @@ static struct omap_hwmod omap2420_timer10_hwmod = {
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static struct omap_hwmod omap2420_timer11_hwmod;
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static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = {
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{ .irq = 47, },
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{ .irq = -1 }
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};
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/* l4_core -> timer11 */
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@ -737,7 +738,6 @@ static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
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static struct omap_hwmod omap2420_timer11_hwmod = {
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.name = "timer11",
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.mpu_irqs = omap2420_timer11_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer11_mpu_irqs),
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.main_clk = "gpt11_fck",
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.prcm = {
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.omap2 = {
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@ -758,6 +758,7 @@ static struct omap_hwmod omap2420_timer11_hwmod = {
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static struct omap_hwmod omap2420_timer12_hwmod;
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static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = {
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{ .irq = 48, },
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{ .irq = -1 }
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};
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/* l4_core -> timer12 */
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@ -778,7 +779,6 @@ static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
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static struct omap_hwmod omap2420_timer12_hwmod = {
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.name = "timer12",
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.mpu_irqs = omap2420_timer12_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer12_mpu_irqs),
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.main_clk = "gpt12_fck",
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.prcm = {
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.omap2 = {
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@ -879,6 +879,7 @@ static struct omap_hwmod_class uart_class = {
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static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
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{ .irq = INT_24XX_UART1_IRQ, },
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{ .irq = -1 }
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};
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static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
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@ -893,7 +894,6 @@ static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
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static struct omap_hwmod omap2420_uart1_hwmod = {
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.name = "uart1",
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.mpu_irqs = uart1_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
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.sdma_reqs = uart1_sdma_reqs,
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.sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
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.main_clk = "uart1_fck",
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@ -916,6 +916,7 @@ static struct omap_hwmod omap2420_uart1_hwmod = {
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static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
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{ .irq = INT_24XX_UART2_IRQ, },
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{ .irq = -1 }
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};
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static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
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@ -930,7 +931,6 @@ static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
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static struct omap_hwmod omap2420_uart2_hwmod = {
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.name = "uart2",
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.mpu_irqs = uart2_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
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.sdma_reqs = uart2_sdma_reqs,
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.sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
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.main_clk = "uart2_fck",
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@ -953,6 +953,7 @@ static struct omap_hwmod omap2420_uart2_hwmod = {
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static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
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{ .irq = INT_24XX_UART3_IRQ, },
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{ .irq = -1 }
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};
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static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
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@ -967,7 +968,6 @@ static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
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static struct omap_hwmod omap2420_uart3_hwmod = {
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.name = "uart3",
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.mpu_irqs = uart3_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
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.sdma_reqs = uart3_sdma_reqs,
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.sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
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.main_clk = "uart3_fck",
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@ -1087,6 +1087,7 @@ static struct omap_hwmod_class omap2420_dispc_hwmod_class = {
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static struct omap_hwmod_irq_info omap2420_dispc_irqs[] = {
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{ .irq = 25 },
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{ .irq = -1 }
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};
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/* l4_core -> dss_dispc */
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@ -1113,7 +1114,6 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = {
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.name = "dss_dispc",
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.class = &omap2420_dispc_hwmod_class,
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.mpu_irqs = omap2420_dispc_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap2420_dispc_irqs),
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.main_clk = "dss1_fck",
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.prcm = {
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.omap2 = {
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@ -1254,6 +1254,7 @@ static struct omap_i2c_dev_attr i2c_dev_attr;
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static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
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{ .irq = INT_24XX_I2C1_IRQ, },
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{ .irq = -1 }
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};
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static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
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@ -1268,7 +1269,6 @@ static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
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static struct omap_hwmod omap2420_i2c1_hwmod = {
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.name = "i2c1",
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.mpu_irqs = i2c1_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
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.sdma_reqs = i2c1_sdma_reqs,
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.sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
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.main_clk = "i2c1_fck",
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@ -1293,6 +1293,7 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
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static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
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{ .irq = INT_24XX_I2C2_IRQ, },
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{ .irq = -1 }
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};
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static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
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@ -1307,7 +1308,6 @@ static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
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static struct omap_hwmod omap2420_i2c2_hwmod = {
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.name = "i2c2",
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.mpu_irqs = i2c2_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
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.sdma_reqs = i2c2_sdma_reqs,
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.sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
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.main_clk = "i2c2_fck",
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@ -1430,6 +1430,7 @@ static struct omap_hwmod_class omap242x_gpio_hwmod_class = {
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||||
/* gpio1 */
|
||||
static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = {
|
||||
{ .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
|
||||
@ -1440,7 +1441,6 @@ static struct omap_hwmod omap2420_gpio1_hwmod = {
|
||||
.name = "gpio1",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap242x_gpio1_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs),
|
||||
.main_clk = "gpios_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -1461,6 +1461,7 @@ static struct omap_hwmod omap2420_gpio1_hwmod = {
|
||||
/* gpio2 */
|
||||
static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = {
|
||||
{ .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
|
||||
@ -1471,7 +1472,6 @@ static struct omap_hwmod omap2420_gpio2_hwmod = {
|
||||
.name = "gpio2",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap242x_gpio2_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs),
|
||||
.main_clk = "gpios_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -1492,6 +1492,7 @@ static struct omap_hwmod omap2420_gpio2_hwmod = {
|
||||
/* gpio3 */
|
||||
static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = {
|
||||
{ .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
|
||||
@ -1502,7 +1503,6 @@ static struct omap_hwmod omap2420_gpio3_hwmod = {
|
||||
.name = "gpio3",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap242x_gpio3_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs),
|
||||
.main_clk = "gpios_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -1523,6 +1523,7 @@ static struct omap_hwmod omap2420_gpio3_hwmod = {
|
||||
/* gpio4 */
|
||||
static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = {
|
||||
{ .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
|
||||
@ -1533,7 +1534,6 @@ static struct omap_hwmod omap2420_gpio4_hwmod = {
|
||||
.name = "gpio4",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap242x_gpio4_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs),
|
||||
.main_clk = "gpios_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -1580,6 +1580,7 @@ static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
|
||||
{ .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
|
||||
{ .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
|
||||
{ .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
/* dma_system -> L3 */
|
||||
@ -1613,7 +1614,6 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
|
||||
.name = "dma",
|
||||
.class = &omap2420_dma_hwmod_class,
|
||||
.mpu_irqs = omap2420_dma_system_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_dma_system_irqs),
|
||||
.main_clk = "core_l3_ck",
|
||||
.slaves = omap2420_dma_system_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves),
|
||||
@ -1650,6 +1650,7 @@ static struct omap_hwmod omap2420_mailbox_hwmod;
|
||||
static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
|
||||
{ .name = "dsp", .irq = 26 },
|
||||
{ .name = "iva", .irq = 34 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
/* l4_core -> mailbox */
|
||||
@ -1669,7 +1670,6 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
|
||||
.name = "mailbox",
|
||||
.class = &omap2420_mailbox_hwmod_class,
|
||||
.mpu_irqs = omap2420_mailbox_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_mailbox_irqs),
|
||||
.main_clk = "mailboxes_ick",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -1711,6 +1711,7 @@ static struct omap_hwmod_class omap2420_mcspi_class = {
|
||||
/* mcspi1 */
|
||||
static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = {
|
||||
{ .irq = 65 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = {
|
||||
@ -1735,7 +1736,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
|
||||
static struct omap_hwmod omap2420_mcspi1_hwmod = {
|
||||
.name = "mcspi1_hwmod",
|
||||
.mpu_irqs = omap2420_mcspi1_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi1_mpu_irqs),
|
||||
.sdma_reqs = omap2420_mcspi1_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs),
|
||||
.main_clk = "mcspi1_fck",
|
||||
@ -1758,6 +1758,7 @@ static struct omap_hwmod omap2420_mcspi1_hwmod = {
|
||||
/* mcspi2 */
|
||||
static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = {
|
||||
{ .irq = 66 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = {
|
||||
@ -1778,7 +1779,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
|
||||
static struct omap_hwmod omap2420_mcspi2_hwmod = {
|
||||
.name = "mcspi2_hwmod",
|
||||
.mpu_irqs = omap2420_mcspi2_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi2_mpu_irqs),
|
||||
.sdma_reqs = omap2420_mcspi2_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs),
|
||||
.main_clk = "mcspi2_fck",
|
||||
@ -1811,6 +1811,7 @@ static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
|
||||
static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
|
||||
{ .name = "tx", .irq = 59 },
|
||||
{ .name = "rx", .irq = 60 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = {
|
||||
@ -1836,7 +1837,6 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
|
||||
.name = "mcbsp1",
|
||||
.class = &omap2420_mcbsp_hwmod_class,
|
||||
.mpu_irqs = omap2420_mcbsp1_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_irqs),
|
||||
.sdma_reqs = omap2420_mcbsp1_sdma_chs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_sdma_chs),
|
||||
.main_clk = "mcbsp1_fck",
|
||||
@ -1858,6 +1858,7 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
|
||||
static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
|
||||
{ .name = "tx", .irq = 62 },
|
||||
{ .name = "rx", .irq = 63 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = {
|
||||
@ -1883,7 +1884,6 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = {
|
||||
.name = "mcbsp2",
|
||||
.class = &omap2420_mcbsp_hwmod_class,
|
||||
.mpu_irqs = omap2420_mcbsp2_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_irqs),
|
||||
.sdma_reqs = omap2420_mcbsp2_sdma_chs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_sdma_chs),
|
||||
.main_clk = "mcbsp2_fck",
|
||||
|
@ -369,6 +369,7 @@ static struct omap_hwmod_class omap2430_timer_hwmod_class = {
|
||||
static struct omap_hwmod omap2430_timer1_hwmod;
|
||||
static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
|
||||
{ .irq = 37, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
|
||||
@ -398,7 +399,6 @@ static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
|
||||
static struct omap_hwmod omap2430_timer1_hwmod = {
|
||||
.name = "timer1",
|
||||
.mpu_irqs = omap2430_timer1_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer1_mpu_irqs),
|
||||
.main_clk = "gpt1_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -419,6 +419,7 @@ static struct omap_hwmod omap2430_timer1_hwmod = {
|
||||
static struct omap_hwmod omap2430_timer2_hwmod;
|
||||
static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
|
||||
{ .irq = 38, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
/* l4_core -> timer2 */
|
||||
@ -439,7 +440,6 @@ static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
|
||||
static struct omap_hwmod omap2430_timer2_hwmod = {
|
||||
.name = "timer2",
|
||||
.mpu_irqs = omap2430_timer2_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer2_mpu_irqs),
|
||||
.main_clk = "gpt2_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -460,6 +460,7 @@ static struct omap_hwmod omap2430_timer2_hwmod = {
|
||||
static struct omap_hwmod omap2430_timer3_hwmod;
|
||||
static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
|
||||
{ .irq = 39, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
/* l4_core -> timer3 */
|
||||
@ -480,7 +481,6 @@ static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
|
||||
static struct omap_hwmod omap2430_timer3_hwmod = {
|
||||
.name = "timer3",
|
||||
.mpu_irqs = omap2430_timer3_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer3_mpu_irqs),
|
||||
.main_clk = "gpt3_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -501,6 +501,7 @@ static struct omap_hwmod omap2430_timer3_hwmod = {
|
||||
static struct omap_hwmod omap2430_timer4_hwmod;
|
||||
static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
|
||||
{ .irq = 40, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
/* l4_core -> timer4 */
|
||||
@ -521,7 +522,6 @@ static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
|
||||
static struct omap_hwmod omap2430_timer4_hwmod = {
|
||||
.name = "timer4",
|
||||
.mpu_irqs = omap2430_timer4_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer4_mpu_irqs),
|
||||
.main_clk = "gpt4_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -542,6 +542,7 @@ static struct omap_hwmod omap2430_timer4_hwmod = {
|
||||
static struct omap_hwmod omap2430_timer5_hwmod;
|
||||
static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
|
||||
{ .irq = 41, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
/* l4_core -> timer5 */
|
||||
@ -562,7 +563,6 @@ static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
|
||||
static struct omap_hwmod omap2430_timer5_hwmod = {
|
||||
.name = "timer5",
|
||||
.mpu_irqs = omap2430_timer5_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer5_mpu_irqs),
|
||||
.main_clk = "gpt5_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -583,6 +583,7 @@ static struct omap_hwmod omap2430_timer5_hwmod = {
|
||||
static struct omap_hwmod omap2430_timer6_hwmod;
|
||||
static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
|
||||
{ .irq = 42, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
/* l4_core -> timer6 */
|
||||
@ -603,7 +604,6 @@ static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
|
||||
static struct omap_hwmod omap2430_timer6_hwmod = {
|
||||
.name = "timer6",
|
||||
.mpu_irqs = omap2430_timer6_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer6_mpu_irqs),
|
||||
.main_clk = "gpt6_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -624,6 +624,7 @@ static struct omap_hwmod omap2430_timer6_hwmod = {
|
||||
static struct omap_hwmod omap2430_timer7_hwmod;
|
||||
static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
|
||||
{ .irq = 43, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
/* l4_core -> timer7 */
|
||||
@ -644,7 +645,6 @@ static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
|
||||
static struct omap_hwmod omap2430_timer7_hwmod = {
|
||||
.name = "timer7",
|
||||
.mpu_irqs = omap2430_timer7_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer7_mpu_irqs),
|
||||
.main_clk = "gpt7_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -665,6 +665,7 @@ static struct omap_hwmod omap2430_timer7_hwmod = {
|
||||
static struct omap_hwmod omap2430_timer8_hwmod;
|
||||
static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
|
||||
{ .irq = 44, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
/* l4_core -> timer8 */
|
||||
@ -685,7 +686,6 @@ static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
|
||||
static struct omap_hwmod omap2430_timer8_hwmod = {
|
||||
.name = "timer8",
|
||||
.mpu_irqs = omap2430_timer8_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer8_mpu_irqs),
|
||||
.main_clk = "gpt8_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -706,6 +706,7 @@ static struct omap_hwmod omap2430_timer8_hwmod = {
|
||||
static struct omap_hwmod omap2430_timer9_hwmod;
|
||||
static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
|
||||
{ .irq = 45, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
/* l4_core -> timer9 */
|
||||
@ -726,7 +727,6 @@ static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
|
||||
static struct omap_hwmod omap2430_timer9_hwmod = {
|
||||
.name = "timer9",
|
||||
.mpu_irqs = omap2430_timer9_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer9_mpu_irqs),
|
||||
.main_clk = "gpt9_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -747,6 +747,7 @@ static struct omap_hwmod omap2430_timer9_hwmod = {
|
||||
static struct omap_hwmod omap2430_timer10_hwmod;
|
||||
static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
|
||||
{ .irq = 46, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
/* l4_core -> timer10 */
|
||||
@ -767,7 +768,6 @@ static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
|
||||
static struct omap_hwmod omap2430_timer10_hwmod = {
|
||||
.name = "timer10",
|
||||
.mpu_irqs = omap2430_timer10_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer10_mpu_irqs),
|
||||
.main_clk = "gpt10_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -788,6 +788,7 @@ static struct omap_hwmod omap2430_timer10_hwmod = {
|
||||
static struct omap_hwmod omap2430_timer11_hwmod;
|
||||
static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
|
||||
{ .irq = 47, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
/* l4_core -> timer11 */
|
||||
@ -808,7 +809,6 @@ static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
|
||||
static struct omap_hwmod omap2430_timer11_hwmod = {
|
||||
.name = "timer11",
|
||||
.mpu_irqs = omap2430_timer11_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer11_mpu_irqs),
|
||||
.main_clk = "gpt11_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -829,6 +829,7 @@ static struct omap_hwmod omap2430_timer11_hwmod = {
|
||||
static struct omap_hwmod omap2430_timer12_hwmod;
|
||||
static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
|
||||
{ .irq = 48, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
/* l4_core -> timer12 */
|
||||
@ -849,7 +850,6 @@ static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
|
||||
static struct omap_hwmod omap2430_timer12_hwmod = {
|
||||
.name = "timer12",
|
||||
.mpu_irqs = omap2430_timer12_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer12_mpu_irqs),
|
||||
.main_clk = "gpt12_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -950,6 +950,7 @@ static struct omap_hwmod_class uart_class = {
|
||||
|
||||
static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
|
||||
{ .irq = INT_24XX_UART1_IRQ, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
|
||||
@ -964,7 +965,6 @@ static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
|
||||
static struct omap_hwmod omap2430_uart1_hwmod = {
|
||||
.name = "uart1",
|
||||
.mpu_irqs = uart1_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
|
||||
.sdma_reqs = uart1_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
|
||||
.main_clk = "uart1_fck",
|
||||
@ -987,6 +987,7 @@ static struct omap_hwmod omap2430_uart1_hwmod = {
|
||||
|
||||
static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
|
||||
{ .irq = INT_24XX_UART2_IRQ, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
|
||||
@ -1001,7 +1002,6 @@ static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
|
||||
static struct omap_hwmod omap2430_uart2_hwmod = {
|
||||
.name = "uart2",
|
||||
.mpu_irqs = uart2_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
|
||||
.sdma_reqs = uart2_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
|
||||
.main_clk = "uart2_fck",
|
||||
@ -1024,6 +1024,7 @@ static struct omap_hwmod omap2430_uart2_hwmod = {
|
||||
|
||||
static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
|
||||
{ .irq = INT_24XX_UART3_IRQ, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
|
||||
@ -1038,7 +1039,6 @@ static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
|
||||
static struct omap_hwmod omap2430_uart3_hwmod = {
|
||||
.name = "uart3",
|
||||
.mpu_irqs = uart3_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
|
||||
.sdma_reqs = uart3_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
|
||||
.main_clk = "uart3_fck",
|
||||
@ -1152,6 +1152,7 @@ static struct omap_hwmod_class omap2430_dispc_hwmod_class = {
|
||||
|
||||
static struct omap_hwmod_irq_info omap2430_dispc_irqs[] = {
|
||||
{ .irq = 25 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
/* l4_core -> dss_dispc */
|
||||
@ -1172,7 +1173,6 @@ static struct omap_hwmod omap2430_dss_dispc_hwmod = {
|
||||
.name = "dss_dispc",
|
||||
.class = &omap2430_dispc_hwmod_class,
|
||||
.mpu_irqs = omap2430_dispc_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_dispc_irqs),
|
||||
.main_clk = "dss1_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -1304,6 +1304,7 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
|
||||
|
||||
static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
|
||||
{ .irq = INT_24XX_I2C1_IRQ, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
|
||||
@ -1318,7 +1319,6 @@ static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
|
||||
static struct omap_hwmod omap2430_i2c1_hwmod = {
|
||||
.name = "i2c1",
|
||||
.mpu_irqs = i2c1_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
|
||||
.sdma_reqs = i2c1_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
|
||||
.main_clk = "i2chs1_fck",
|
||||
@ -1350,6 +1350,7 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
|
||||
|
||||
static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
|
||||
{ .irq = INT_24XX_I2C2_IRQ, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
|
||||
@ -1364,7 +1365,6 @@ static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
|
||||
static struct omap_hwmod omap2430_i2c2_hwmod = {
|
||||
.name = "i2c2",
|
||||
.mpu_irqs = i2c2_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
|
||||
.sdma_reqs = i2c2_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
|
||||
.main_clk = "i2chs2_fck",
|
||||
@ -1504,6 +1504,7 @@ static struct omap_hwmod_class omap243x_gpio_hwmod_class = {
|
||||
/* gpio1 */
|
||||
static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = {
|
||||
{ .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
|
||||
@ -1514,7 +1515,6 @@ static struct omap_hwmod omap2430_gpio1_hwmod = {
|
||||
.name = "gpio1",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap243x_gpio1_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs),
|
||||
.main_clk = "gpios_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -1535,6 +1535,7 @@ static struct omap_hwmod omap2430_gpio1_hwmod = {
|
||||
/* gpio2 */
|
||||
static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = {
|
||||
{ .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
|
||||
@ -1545,7 +1546,6 @@ static struct omap_hwmod omap2430_gpio2_hwmod = {
|
||||
.name = "gpio2",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap243x_gpio2_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs),
|
||||
.main_clk = "gpios_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -1566,6 +1566,7 @@ static struct omap_hwmod omap2430_gpio2_hwmod = {
|
||||
/* gpio3 */
|
||||
static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = {
|
||||
{ .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
|
||||
@ -1576,7 +1577,6 @@ static struct omap_hwmod omap2430_gpio3_hwmod = {
|
||||
.name = "gpio3",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap243x_gpio3_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs),
|
||||
.main_clk = "gpios_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -1597,6 +1597,7 @@ static struct omap_hwmod omap2430_gpio3_hwmod = {
|
||||
/* gpio4 */
|
||||
static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = {
|
||||
{ .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
|
||||
@ -1607,7 +1608,6 @@ static struct omap_hwmod omap2430_gpio4_hwmod = {
|
||||
.name = "gpio4",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap243x_gpio4_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs),
|
||||
.main_clk = "gpios_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -1628,6 +1628,7 @@ static struct omap_hwmod omap2430_gpio4_hwmod = {
|
||||
/* gpio5 */
|
||||
static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
|
||||
{ .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
|
||||
@ -1638,7 +1639,6 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
|
||||
.name = "gpio5",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap243x_gpio5_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs),
|
||||
.main_clk = "gpio5_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -1685,6 +1685,7 @@ static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
|
||||
{ .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
|
||||
{ .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
|
||||
{ .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
/* dma_system -> L3 */
|
||||
@ -1718,7 +1719,6 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
|
||||
.name = "dma",
|
||||
.class = &omap2430_dma_hwmod_class,
|
||||
.mpu_irqs = omap2430_dma_system_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs),
|
||||
.main_clk = "core_l3_ck",
|
||||
.slaves = omap2430_dma_system_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves),
|
||||
@ -1754,6 +1754,7 @@ static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
|
||||
static struct omap_hwmod omap2430_mailbox_hwmod;
|
||||
static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
|
||||
{ .irq = 26 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
/* l4_core -> mailbox */
|
||||
@ -1773,7 +1774,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
|
||||
.name = "mailbox",
|
||||
.class = &omap2430_mailbox_hwmod_class,
|
||||
.mpu_irqs = omap2430_mailbox_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mailbox_irqs),
|
||||
.main_clk = "mailboxes_ick",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -1815,6 +1815,7 @@ static struct omap_hwmod_class omap2430_mcspi_class = {
|
||||
/* mcspi1 */
|
||||
static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = {
|
||||
{ .irq = 65 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
|
||||
@ -1839,7 +1840,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
|
||||
static struct omap_hwmod omap2430_mcspi1_hwmod = {
|
||||
.name = "mcspi1_hwmod",
|
||||
.mpu_irqs = omap2430_mcspi1_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs),
|
||||
.sdma_reqs = omap2430_mcspi1_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
|
||||
.main_clk = "mcspi1_fck",
|
||||
@ -1862,6 +1862,7 @@ static struct omap_hwmod omap2430_mcspi1_hwmod = {
|
||||
/* mcspi2 */
|
||||
static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = {
|
||||
{ .irq = 66 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
|
||||
@ -1882,7 +1883,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
|
||||
static struct omap_hwmod omap2430_mcspi2_hwmod = {
|
||||
.name = "mcspi2_hwmod",
|
||||
.mpu_irqs = omap2430_mcspi2_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs),
|
||||
.sdma_reqs = omap2430_mcspi2_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
|
||||
.main_clk = "mcspi2_fck",
|
||||
@ -1905,6 +1905,7 @@ static struct omap_hwmod omap2430_mcspi2_hwmod = {
|
||||
/* mcspi3 */
|
||||
static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
|
||||
{ .irq = 91 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
|
||||
@ -1925,7 +1926,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
|
||||
static struct omap_hwmod omap2430_mcspi3_hwmod = {
|
||||
.name = "mcspi3_hwmod",
|
||||
.mpu_irqs = omap2430_mcspi3_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs),
|
||||
.sdma_reqs = omap2430_mcspi3_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs),
|
||||
.main_clk = "mcspi3_fck",
|
||||
@ -1970,12 +1970,12 @@ static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
|
||||
|
||||
{ .name = "mc", .irq = 92 },
|
||||
{ .name = "dma", .irq = 93 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap2430_usbhsotg_hwmod = {
|
||||
.name = "usb_otg_hs",
|
||||
.mpu_irqs = omap2430_usbhsotg_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs),
|
||||
.main_clk = "usbhs_ick",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -2025,6 +2025,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
|
||||
{ .name = "rx", .irq = 60 },
|
||||
{ .name = "ovr", .irq = 61 },
|
||||
{ .name = "common", .irq = 64 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = {
|
||||
@ -2050,7 +2051,6 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
|
||||
.name = "mcbsp1",
|
||||
.class = &omap2430_mcbsp_hwmod_class,
|
||||
.mpu_irqs = omap2430_mcbsp1_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_irqs),
|
||||
.sdma_reqs = omap2430_mcbsp1_sdma_chs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs),
|
||||
.main_clk = "mcbsp1_fck",
|
||||
@ -2073,6 +2073,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
|
||||
{ .name = "tx", .irq = 62 },
|
||||
{ .name = "rx", .irq = 63 },
|
||||
{ .name = "common", .irq = 16 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = {
|
||||
@ -2098,7 +2099,6 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
|
||||
.name = "mcbsp2",
|
||||
.class = &omap2430_mcbsp_hwmod_class,
|
||||
.mpu_irqs = omap2430_mcbsp2_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_irqs),
|
||||
.sdma_reqs = omap2430_mcbsp2_sdma_chs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs),
|
||||
.main_clk = "mcbsp2_fck",
|
||||
@ -2121,6 +2121,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
|
||||
{ .name = "tx", .irq = 89 },
|
||||
{ .name = "rx", .irq = 90 },
|
||||
{ .name = "common", .irq = 17 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = {
|
||||
@ -2156,7 +2157,6 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
|
||||
.name = "mcbsp3",
|
||||
.class = &omap2430_mcbsp_hwmod_class,
|
||||
.mpu_irqs = omap2430_mcbsp3_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_irqs),
|
||||
.sdma_reqs = omap2430_mcbsp3_sdma_chs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs),
|
||||
.main_clk = "mcbsp3_fck",
|
||||
@ -2179,6 +2179,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
|
||||
{ .name = "tx", .irq = 54 },
|
||||
{ .name = "rx", .irq = 55 },
|
||||
{ .name = "common", .irq = 18 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
|
||||
@ -2214,7 +2215,6 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
|
||||
.name = "mcbsp4",
|
||||
.class = &omap2430_mcbsp_hwmod_class,
|
||||
.mpu_irqs = omap2430_mcbsp4_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_irqs),
|
||||
.sdma_reqs = omap2430_mcbsp4_sdma_chs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs),
|
||||
.main_clk = "mcbsp4_fck",
|
||||
@ -2237,6 +2237,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
|
||||
{ .name = "tx", .irq = 81 },
|
||||
{ .name = "rx", .irq = 82 },
|
||||
{ .name = "common", .irq = 19 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
|
||||
@ -2272,7 +2273,6 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = {
|
||||
.name = "mcbsp5",
|
||||
.class = &omap2430_mcbsp_hwmod_class,
|
||||
.mpu_irqs = omap2430_mcbsp5_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_irqs),
|
||||
.sdma_reqs = omap2430_mcbsp5_sdma_chs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs),
|
||||
.main_clk = "mcbsp5_fck",
|
||||
@ -2312,6 +2312,7 @@ static struct omap_hwmod_class omap2430_mmc_class = {
|
||||
|
||||
static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
|
||||
{ .irq = 83 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
|
||||
@ -2335,7 +2336,6 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
|
||||
.name = "mmc1",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap2430_mmc1_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc1_mpu_irqs),
|
||||
.sdma_reqs = omap2430_mmc1_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc1_sdma_reqs),
|
||||
.opt_clks = omap2430_mmc1_opt_clks,
|
||||
@ -2361,6 +2361,7 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
|
||||
|
||||
static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
|
||||
{ .irq = 86 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
|
||||
@ -2380,7 +2381,6 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
|
||||
.name = "mmc2",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap2430_mmc2_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc2_mpu_irqs),
|
||||
.sdma_reqs = omap2430_mmc2_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc2_sdma_reqs),
|
||||
.opt_clks = omap2430_mmc2_opt_clks,
|
||||
|
@ -103,6 +103,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
|
||||
static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
|
||||
{ .irq = INT_34XX_L3_DBG_IRQ },
|
||||
{ .irq = INT_34XX_L3_APP_IRQ },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
|
||||
@ -151,7 +152,6 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod = {
|
||||
.name = "l3_main",
|
||||
.class = &l3_hwmod_class,
|
||||
.mpu_irqs = omap3xxx_l3_main_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_l3_main_irqs),
|
||||
.masters = omap3xxx_l3_main_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
|
||||
.slaves = omap3xxx_l3_main_slaves,
|
||||
@ -574,6 +574,7 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
|
||||
static struct omap_hwmod omap3xxx_timer1_hwmod;
|
||||
static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
|
||||
{ .irq = 37, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
|
||||
@ -603,7 +604,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
|
||||
static struct omap_hwmod omap3xxx_timer1_hwmod = {
|
||||
.name = "timer1",
|
||||
.mpu_irqs = omap3xxx_timer1_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
|
||||
.main_clk = "gpt1_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -624,6 +624,7 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
|
||||
static struct omap_hwmod omap3xxx_timer2_hwmod;
|
||||
static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
|
||||
{ .irq = 38, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
|
||||
@ -653,7 +654,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
|
||||
static struct omap_hwmod omap3xxx_timer2_hwmod = {
|
||||
.name = "timer2",
|
||||
.mpu_irqs = omap3xxx_timer2_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
|
||||
.main_clk = "gpt2_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -674,6 +674,7 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
|
||||
static struct omap_hwmod omap3xxx_timer3_hwmod;
|
||||
static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
|
||||
{ .irq = 39, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
|
||||
@ -703,7 +704,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
|
||||
static struct omap_hwmod omap3xxx_timer3_hwmod = {
|
||||
.name = "timer3",
|
||||
.mpu_irqs = omap3xxx_timer3_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
|
||||
.main_clk = "gpt3_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -724,6 +724,7 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
|
||||
static struct omap_hwmod omap3xxx_timer4_hwmod;
|
||||
static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
|
||||
{ .irq = 40, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
|
||||
@ -753,7 +754,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
|
||||
static struct omap_hwmod omap3xxx_timer4_hwmod = {
|
||||
.name = "timer4",
|
||||
.mpu_irqs = omap3xxx_timer4_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
|
||||
.main_clk = "gpt4_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -774,6 +774,7 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
|
||||
static struct omap_hwmod omap3xxx_timer5_hwmod;
|
||||
static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
|
||||
{ .irq = 41, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
|
||||
@ -803,7 +804,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
|
||||
static struct omap_hwmod omap3xxx_timer5_hwmod = {
|
||||
.name = "timer5",
|
||||
.mpu_irqs = omap3xxx_timer5_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
|
||||
.main_clk = "gpt5_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -824,6 +824,7 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
|
||||
static struct omap_hwmod omap3xxx_timer6_hwmod;
|
||||
static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
|
||||
{ .irq = 42, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
|
||||
@ -853,7 +854,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
|
||||
static struct omap_hwmod omap3xxx_timer6_hwmod = {
|
||||
.name = "timer6",
|
||||
.mpu_irqs = omap3xxx_timer6_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
|
||||
.main_clk = "gpt6_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -874,6 +874,7 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
|
||||
static struct omap_hwmod omap3xxx_timer7_hwmod;
|
||||
static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
|
||||
{ .irq = 43, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
|
||||
@ -903,7 +904,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
|
||||
static struct omap_hwmod omap3xxx_timer7_hwmod = {
|
||||
.name = "timer7",
|
||||
.mpu_irqs = omap3xxx_timer7_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
|
||||
.main_clk = "gpt7_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -924,6 +924,7 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
|
||||
static struct omap_hwmod omap3xxx_timer8_hwmod;
|
||||
static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
|
||||
{ .irq = 44, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
|
||||
@ -953,7 +954,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
|
||||
static struct omap_hwmod omap3xxx_timer8_hwmod = {
|
||||
.name = "timer8",
|
||||
.mpu_irqs = omap3xxx_timer8_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
|
||||
.main_clk = "gpt8_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -974,6 +974,7 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
|
||||
static struct omap_hwmod omap3xxx_timer9_hwmod;
|
||||
static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
|
||||
{ .irq = 45, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
|
||||
@ -1003,7 +1004,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
|
||||
static struct omap_hwmod omap3xxx_timer9_hwmod = {
|
||||
.name = "timer9",
|
||||
.mpu_irqs = omap3xxx_timer9_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
|
||||
.main_clk = "gpt9_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -1024,6 +1024,7 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
|
||||
static struct omap_hwmod omap3xxx_timer10_hwmod;
|
||||
static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
|
||||
{ .irq = 46, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
/* l4_core -> timer10 */
|
||||
@ -1044,7 +1045,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
|
||||
static struct omap_hwmod omap3xxx_timer10_hwmod = {
|
||||
.name = "timer10",
|
||||
.mpu_irqs = omap3xxx_timer10_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
|
||||
.main_clk = "gpt10_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -1065,6 +1065,7 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
|
||||
static struct omap_hwmod omap3xxx_timer11_hwmod;
|
||||
static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
|
||||
{ .irq = 47, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
/* l4_core -> timer11 */
|
||||
@ -1085,7 +1086,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
|
||||
static struct omap_hwmod omap3xxx_timer11_hwmod = {
|
||||
.name = "timer11",
|
||||
.mpu_irqs = omap3xxx_timer11_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
|
||||
.main_clk = "gpt11_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -1106,6 +1106,7 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
|
||||
static struct omap_hwmod omap3xxx_timer12_hwmod;
|
||||
static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
|
||||
{ .irq = 95, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
|
||||
@ -1135,7 +1136,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
|
||||
static struct omap_hwmod omap3xxx_timer12_hwmod = {
|
||||
.name = "timer12",
|
||||
.mpu_irqs = omap3xxx_timer12_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
|
||||
.main_clk = "gpt12_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -1256,6 +1256,7 @@ static struct omap_hwmod_class uart_class = {
|
||||
|
||||
static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
|
||||
{ .irq = INT_24XX_UART1_IRQ, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
|
||||
@ -1270,7 +1271,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
|
||||
static struct omap_hwmod omap3xxx_uart1_hwmod = {
|
||||
.name = "uart1",
|
||||
.mpu_irqs = uart1_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
|
||||
.sdma_reqs = uart1_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
|
||||
.main_clk = "uart1_fck",
|
||||
@ -1293,6 +1293,7 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
|
||||
|
||||
static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
|
||||
{ .irq = INT_24XX_UART2_IRQ, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
|
||||
@ -1307,7 +1308,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
|
||||
static struct omap_hwmod omap3xxx_uart2_hwmod = {
|
||||
.name = "uart2",
|
||||
.mpu_irqs = uart2_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
|
||||
.sdma_reqs = uart2_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
|
||||
.main_clk = "uart2_fck",
|
||||
@ -1330,6 +1330,7 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
|
||||
|
||||
static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
|
||||
{ .irq = INT_24XX_UART3_IRQ, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
|
||||
@ -1344,7 +1345,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
|
||||
static struct omap_hwmod omap3xxx_uart3_hwmod = {
|
||||
.name = "uart3",
|
||||
.mpu_irqs = uart3_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
|
||||
.sdma_reqs = uart3_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
|
||||
.main_clk = "uart3_fck",
|
||||
@ -1367,6 +1367,7 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
|
||||
|
||||
static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
|
||||
{ .irq = INT_36XX_UART4_IRQ, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
|
||||
@ -1381,7 +1382,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
|
||||
static struct omap_hwmod omap3xxx_uart4_hwmod = {
|
||||
.name = "uart4",
|
||||
.mpu_irqs = uart4_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs),
|
||||
.sdma_reqs = uart4_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
|
||||
.main_clk = "uart4_fck",
|
||||
@ -1557,6 +1557,7 @@ static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
|
||||
|
||||
static struct omap_hwmod_irq_info omap3xxx_dispc_irqs[] = {
|
||||
{ .irq = 25 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
/* l4_core -> dss_dispc */
|
||||
@ -1584,7 +1585,6 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
|
||||
.name = "dss_dispc",
|
||||
.class = &omap3xxx_dispc_hwmod_class,
|
||||
.mpu_irqs = omap3xxx_dispc_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dispc_irqs),
|
||||
.main_clk = "dss1_alwon_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -1612,6 +1612,7 @@ static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
|
||||
|
||||
static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
|
||||
{ .irq = 25 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
/* dss_dsi1 */
|
||||
@ -1648,7 +1649,6 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
|
||||
.name = "dss_dsi1",
|
||||
.class = &omap3xxx_dsi_hwmod_class,
|
||||
.mpu_irqs = omap3xxx_dsi1_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dsi1_irqs),
|
||||
.main_clk = "dss1_alwon_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -1783,6 +1783,7 @@ static struct omap_i2c_dev_attr i2c1_dev_attr = {
|
||||
|
||||
static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
|
||||
{ .irq = INT_24XX_I2C1_IRQ, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
|
||||
@ -1797,7 +1798,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
|
||||
static struct omap_hwmod omap3xxx_i2c1_hwmod = {
|
||||
.name = "i2c1",
|
||||
.mpu_irqs = i2c1_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
|
||||
.sdma_reqs = i2c1_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
|
||||
.main_clk = "i2c1_fck",
|
||||
@ -1825,6 +1825,7 @@ static struct omap_i2c_dev_attr i2c2_dev_attr = {
|
||||
|
||||
static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
|
||||
{ .irq = INT_24XX_I2C2_IRQ, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
|
||||
@ -1839,7 +1840,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
|
||||
static struct omap_hwmod omap3xxx_i2c2_hwmod = {
|
||||
.name = "i2c2",
|
||||
.mpu_irqs = i2c2_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
|
||||
.sdma_reqs = i2c2_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
|
||||
.main_clk = "i2c2_fck",
|
||||
@ -1867,6 +1867,7 @@ static struct omap_i2c_dev_attr i2c3_dev_attr = {
|
||||
|
||||
static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
|
||||
{ .irq = INT_34XX_I2C3_IRQ, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
|
||||
@ -1881,7 +1882,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
|
||||
static struct omap_hwmod omap3xxx_i2c3_hwmod = {
|
||||
.name = "i2c3",
|
||||
.mpu_irqs = i2c3_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs),
|
||||
.sdma_reqs = i2c3_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
|
||||
.main_clk = "i2c3_fck",
|
||||
@ -2034,6 +2034,7 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
|
||||
/* gpio1 */
|
||||
static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
|
||||
{ .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
|
||||
@ -2048,7 +2049,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
|
||||
.name = "gpio1",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap3xxx_gpio1_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs),
|
||||
.main_clk = "gpio1_ick",
|
||||
.opt_clks = gpio1_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
|
||||
@ -2071,6 +2071,7 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
|
||||
/* gpio2 */
|
||||
static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
|
||||
{ .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
|
||||
@ -2085,7 +2086,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
|
||||
.name = "gpio2",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap3xxx_gpio2_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs),
|
||||
.main_clk = "gpio2_ick",
|
||||
.opt_clks = gpio2_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
|
||||
@ -2108,6 +2108,7 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
|
||||
/* gpio3 */
|
||||
static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
|
||||
{ .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
|
||||
@ -2122,7 +2123,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
|
||||
.name = "gpio3",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap3xxx_gpio3_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs),
|
||||
.main_clk = "gpio3_ick",
|
||||
.opt_clks = gpio3_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
|
||||
@ -2145,6 +2145,7 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
|
||||
/* gpio4 */
|
||||
static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
|
||||
{ .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
|
||||
@ -2159,7 +2160,6 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
|
||||
.name = "gpio4",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap3xxx_gpio4_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs),
|
||||
.main_clk = "gpio4_ick",
|
||||
.opt_clks = gpio4_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
|
||||
@ -2182,6 +2182,7 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
|
||||
/* gpio5 */
|
||||
static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
|
||||
{ .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
|
||||
@ -2196,7 +2197,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
|
||||
.name = "gpio5",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap3xxx_gpio5_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs),
|
||||
.main_clk = "gpio5_ick",
|
||||
.opt_clks = gpio5_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
|
||||
@ -2219,6 +2219,7 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
|
||||
/* gpio6 */
|
||||
static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
|
||||
{ .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
|
||||
@ -2233,7 +2234,6 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
|
||||
.name = "gpio6",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap3xxx_gpio6_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs),
|
||||
.main_clk = "gpio6_ick",
|
||||
.opt_clks = gpio6_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
|
||||
@ -2292,6 +2292,7 @@ static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
|
||||
{ .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
|
||||
{ .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
|
||||
{ .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
|
||||
@ -2326,7 +2327,6 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = {
|
||||
.name = "dma",
|
||||
.class = &omap3xxx_dma_hwmod_class,
|
||||
.mpu_irqs = omap3xxx_dma_system_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs),
|
||||
.main_clk = "core_l3_ick",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -2371,6 +2371,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
|
||||
{ .name = "irq", .irq = 16 },
|
||||
{ .name = "tx", .irq = 59 },
|
||||
{ .name = "rx", .irq = 60 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
|
||||
@ -2406,7 +2407,6 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
|
||||
.name = "mcbsp1",
|
||||
.class = &omap3xxx_mcbsp_hwmod_class,
|
||||
.mpu_irqs = omap3xxx_mcbsp1_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_irqs),
|
||||
.sdma_reqs = omap3xxx_mcbsp1_sdma_chs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
|
||||
.main_clk = "mcbsp1_fck",
|
||||
@ -2429,6 +2429,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
|
||||
{ .name = "irq", .irq = 17 },
|
||||
{ .name = "tx", .irq = 62 },
|
||||
{ .name = "rx", .irq = 63 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
|
||||
@ -2469,7 +2470,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
|
||||
.name = "mcbsp2",
|
||||
.class = &omap3xxx_mcbsp_hwmod_class,
|
||||
.mpu_irqs = omap3xxx_mcbsp2_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_irqs),
|
||||
.sdma_reqs = omap3xxx_mcbsp2_sdma_chs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
|
||||
.main_clk = "mcbsp2_fck",
|
||||
@ -2493,6 +2493,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
|
||||
{ .name = "irq", .irq = 22 },
|
||||
{ .name = "tx", .irq = 89 },
|
||||
{ .name = "rx", .irq = 90 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
|
||||
@ -2532,7 +2533,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
|
||||
.name = "mcbsp3",
|
||||
.class = &omap3xxx_mcbsp_hwmod_class,
|
||||
.mpu_irqs = omap3xxx_mcbsp3_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_irqs),
|
||||
.sdma_reqs = omap3xxx_mcbsp3_sdma_chs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
|
||||
.main_clk = "mcbsp3_fck",
|
||||
@ -2556,6 +2556,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
|
||||
{ .name = "irq", .irq = 23 },
|
||||
{ .name = "tx", .irq = 54 },
|
||||
{ .name = "rx", .irq = 55 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
|
||||
@ -2591,7 +2592,6 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
|
||||
.name = "mcbsp4",
|
||||
.class = &omap3xxx_mcbsp_hwmod_class,
|
||||
.mpu_irqs = omap3xxx_mcbsp4_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_irqs),
|
||||
.sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
|
||||
.main_clk = "mcbsp4_fck",
|
||||
@ -2614,6 +2614,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
|
||||
{ .name = "irq", .irq = 27 },
|
||||
{ .name = "tx", .irq = 81 },
|
||||
{ .name = "rx", .irq = 82 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
|
||||
@ -2649,7 +2650,6 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
|
||||
.name = "mcbsp5",
|
||||
.class = &omap3xxx_mcbsp_hwmod_class,
|
||||
.mpu_irqs = omap3xxx_mcbsp5_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_irqs),
|
||||
.sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
|
||||
.main_clk = "mcbsp5_fck",
|
||||
@ -2682,6 +2682,7 @@ static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
|
||||
/* mcbsp2_sidetone */
|
||||
static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
|
||||
{ .name = "irq", .irq = 4 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
|
||||
@ -2712,7 +2713,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
|
||||
.name = "mcbsp2_sidetone",
|
||||
.class = &omap3xxx_mcbsp_sidetone_hwmod_class,
|
||||
.mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs),
|
||||
.main_clk = "mcbsp2_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -2731,6 +2731,7 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
|
||||
/* mcbsp3_sidetone */
|
||||
static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
|
||||
{ .name = "irq", .irq = 5 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
|
||||
@ -2761,7 +2762,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
|
||||
.name = "mcbsp3_sidetone",
|
||||
.class = &omap3xxx_mcbsp_sidetone_hwmod_class,
|
||||
.mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs),
|
||||
.main_clk = "mcbsp3_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -2931,6 +2931,7 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
|
||||
static struct omap_hwmod omap3xxx_mailbox_hwmod;
|
||||
static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
|
||||
{ .irq = 26 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
|
||||
@ -2959,7 +2960,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
|
||||
.name = "mailbox",
|
||||
.class = &omap3xxx_mailbox_hwmod_class,
|
||||
.mpu_irqs = omap3xxx_mailbox_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mailbox_irqs),
|
||||
.main_clk = "mailboxes_ick",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -3046,6 +3046,7 @@ static struct omap_hwmod_class omap34xx_mcspi_class = {
|
||||
/* mcspi1 */
|
||||
static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
|
||||
{ .name = "irq", .irq = 65 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
|
||||
@ -3070,7 +3071,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
|
||||
static struct omap_hwmod omap34xx_mcspi1 = {
|
||||
.name = "mcspi1",
|
||||
.mpu_irqs = omap34xx_mcspi1_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
|
||||
.sdma_reqs = omap34xx_mcspi1_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
|
||||
.main_clk = "mcspi1_fck",
|
||||
@ -3093,6 +3093,7 @@ static struct omap_hwmod omap34xx_mcspi1 = {
|
||||
/* mcspi2 */
|
||||
static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
|
||||
{ .name = "irq", .irq = 66 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
|
||||
@ -3113,7 +3114,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
|
||||
static struct omap_hwmod omap34xx_mcspi2 = {
|
||||
.name = "mcspi2",
|
||||
.mpu_irqs = omap34xx_mcspi2_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
|
||||
.sdma_reqs = omap34xx_mcspi2_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
|
||||
.main_clk = "mcspi2_fck",
|
||||
@ -3136,6 +3136,7 @@ static struct omap_hwmod omap34xx_mcspi2 = {
|
||||
/* mcspi3 */
|
||||
static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
|
||||
{ .name = "irq", .irq = 91 }, /* 91 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
|
||||
@ -3156,7 +3157,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
|
||||
static struct omap_hwmod omap34xx_mcspi3 = {
|
||||
.name = "mcspi3",
|
||||
.mpu_irqs = omap34xx_mcspi3_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
|
||||
.sdma_reqs = omap34xx_mcspi3_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
|
||||
.main_clk = "mcspi3_fck",
|
||||
@ -3179,6 +3179,7 @@ static struct omap_hwmod omap34xx_mcspi3 = {
|
||||
/* SPI4 */
|
||||
static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
|
||||
{ .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
|
||||
@ -3197,7 +3198,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
|
||||
static struct omap_hwmod omap34xx_mcspi4 = {
|
||||
.name = "mcspi4",
|
||||
.mpu_irqs = omap34xx_mcspi4_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
|
||||
.sdma_reqs = omap34xx_mcspi4_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
|
||||
.main_clk = "mcspi4_fck",
|
||||
@ -3241,12 +3241,12 @@ static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
|
||||
|
||||
{ .name = "mc", .irq = 92 },
|
||||
{ .name = "dma", .irq = 93 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
|
||||
.name = "usb_otg_hs",
|
||||
.mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
|
||||
.main_clk = "hsotgusb_ick",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -3278,6 +3278,7 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
|
||||
static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
|
||||
|
||||
{ .name = "mc", .irq = 71 },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class am35xx_usbotg_class = {
|
||||
@ -3288,7 +3289,6 @@ static struct omap_hwmod_class am35xx_usbotg_class = {
|
||||
static struct omap_hwmod am35xx_usbhsotg_hwmod = {
|
||||
.name = "am35x_otg_hs",
|
||||
.mpu_irqs = am35xx_usbhsotg_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
|
||||
.main_clk = NULL,
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
@ -3324,6 +3324,7 @@ static struct omap_hwmod_class omap34xx_mmc_class = {
|
||||
|
||||
static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
|
||||
{ .irq = 83, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
|
||||
@ -3346,7 +3347,6 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = {
|
||||
static struct omap_hwmod omap3xxx_mmc1_hwmod = {
|
||||
.name = "mmc1",
|
||||
.mpu_irqs = omap34xx_mmc1_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc1_mpu_irqs),
|
||||
.sdma_reqs = omap34xx_mmc1_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
|
||||
.opt_clks = omap34xx_mmc1_opt_clks,
|
||||
@ -3372,6 +3372,7 @@ static struct omap_hwmod omap3xxx_mmc1_hwmod = {
|
||||
|
||||
static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
|
||||
{ .irq = INT_24XX_MMC2_IRQ, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
|
||||
@ -3390,7 +3391,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
|
||||
static struct omap_hwmod omap3xxx_mmc2_hwmod = {
|
||||
.name = "mmc2",
|
||||
.mpu_irqs = omap34xx_mmc2_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc2_mpu_irqs),
|
||||
.sdma_reqs = omap34xx_mmc2_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
|
||||
.opt_clks = omap34xx_mmc2_opt_clks,
|
||||
@ -3415,6 +3415,7 @@ static struct omap_hwmod omap3xxx_mmc2_hwmod = {
|
||||
|
||||
static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
|
||||
{ .irq = 94, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
|
||||
@ -3433,7 +3434,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
|
||||
static struct omap_hwmod omap3xxx_mmc3_hwmod = {
|
||||
.name = "mmc3",
|
||||
.mpu_irqs = omap34xx_mmc3_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc3_mpu_irqs),
|
||||
.sdma_reqs = omap34xx_mmc3_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
|
||||
.opt_clks = omap34xx_mmc3_opt_clks,
|
||||
|
@ -115,6 +115,7 @@ static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
|
||||
|
||||
static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
|
||||
{ .irq = 113 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_dmm_hwmod = {
|
||||
@ -123,7 +124,6 @@ static struct omap_hwmod omap44xx_dmm_hwmod = {
|
||||
.slaves = omap44xx_dmm_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
|
||||
.mpu_irqs = omap44xx_dmm_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
@ -268,6 +268,7 @@ static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
|
||||
static struct omap_hwmod_irq_info omap44xx_l3_targ_irqs[] = {
|
||||
{ .irq = 9 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = 10 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
|
||||
@ -303,7 +304,6 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
|
||||
.name = "l3_main_1",
|
||||
.class = &omap44xx_l3_hwmod_class,
|
||||
.mpu_irqs = omap44xx_l3_targ_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_l3_targ_irqs),
|
||||
.slaves = omap44xx_l3_main_1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
@ -672,6 +672,7 @@ static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
|
||||
/* aess */
|
||||
static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
|
||||
{ .irq = 99 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
|
||||
@ -736,7 +737,6 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
|
||||
.name = "aess",
|
||||
.class = &omap44xx_aess_hwmod_class,
|
||||
.mpu_irqs = omap44xx_aess_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_aess_irqs),
|
||||
.sdma_reqs = omap44xx_aess_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_aess_sdma_reqs),
|
||||
.main_clk = "aess_fck",
|
||||
@ -875,6 +875,7 @@ static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
|
||||
{ .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
/* dma_system master ports */
|
||||
@ -909,7 +910,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
|
||||
.name = "dma_system",
|
||||
.class = &omap44xx_dma_hwmod_class,
|
||||
.mpu_irqs = omap44xx_dma_system_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs),
|
||||
.main_clk = "l3_div_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -948,6 +948,7 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
|
||||
static struct omap_hwmod omap44xx_dmic_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
|
||||
{ .irq = 114 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
|
||||
@ -1000,7 +1001,6 @@ static struct omap_hwmod omap44xx_dmic_hwmod = {
|
||||
.name = "dmic",
|
||||
.class = &omap44xx_dmic_hwmod_class,
|
||||
.mpu_irqs = omap44xx_dmic_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmic_irqs),
|
||||
.sdma_reqs = omap44xx_dmic_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dmic_sdma_reqs),
|
||||
.main_clk = "dmic_fck",
|
||||
@ -1026,6 +1026,7 @@ static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
|
||||
/* dsp */
|
||||
static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
|
||||
{ .irq = 28 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
|
||||
@ -1082,7 +1083,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
|
||||
.name = "dsp",
|
||||
.class = &omap44xx_dsp_hwmod_class,
|
||||
.mpu_irqs = omap44xx_dsp_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dsp_irqs),
|
||||
.rst_lines = omap44xx_dsp_resets,
|
||||
.rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
|
||||
.main_clk = "dsp_fck",
|
||||
@ -1215,6 +1215,7 @@ static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
|
||||
static struct omap_hwmod omap44xx_dss_dispc_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
|
||||
{ .irq = 25 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
|
||||
@ -1267,7 +1268,6 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
|
||||
.name = "dss_dispc",
|
||||
.class = &omap44xx_dispc_hwmod_class,
|
||||
.mpu_irqs = omap44xx_dss_dispc_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_irqs),
|
||||
.sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
|
||||
.main_clk = "dss_fck",
|
||||
@ -1306,6 +1306,7 @@ static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
|
||||
static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
|
||||
{ .irq = 53 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
|
||||
@ -1358,7 +1359,6 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
|
||||
.name = "dss_dsi1",
|
||||
.class = &omap44xx_dsi_hwmod_class,
|
||||
.mpu_irqs = omap44xx_dss_dsi1_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
|
||||
.sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
|
||||
.main_clk = "dss_fck",
|
||||
@ -1376,6 +1376,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
|
||||
static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
|
||||
{ .irq = 84 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
|
||||
@ -1428,7 +1429,6 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
|
||||
.name = "dss_dsi2",
|
||||
.class = &omap44xx_dsi_hwmod_class,
|
||||
.mpu_irqs = omap44xx_dss_dsi2_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
|
||||
.sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
|
||||
.main_clk = "dss_fck",
|
||||
@ -1466,6 +1466,7 @@ static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
|
||||
static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
|
||||
{ .irq = 101 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
|
||||
@ -1518,7 +1519,6 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
|
||||
.name = "dss_hdmi",
|
||||
.class = &omap44xx_hdmi_hwmod_class,
|
||||
.mpu_irqs = omap44xx_dss_hdmi_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_irqs),
|
||||
.sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
|
||||
.main_clk = "dss_fck",
|
||||
@ -1716,6 +1716,7 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
|
||||
static struct omap_hwmod omap44xx_gpio1_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
|
||||
{ .irq = 29 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
|
||||
@ -1749,7 +1750,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
|
||||
.name = "gpio1",
|
||||
.class = &omap44xx_gpio_hwmod_class,
|
||||
.mpu_irqs = omap44xx_gpio1_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs),
|
||||
.main_clk = "gpio1_ick",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -1768,6 +1768,7 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
|
||||
static struct omap_hwmod omap44xx_gpio2_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
|
||||
{ .irq = 30 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
|
||||
@ -1802,7 +1803,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
|
||||
.class = &omap44xx_gpio_hwmod_class,
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap44xx_gpio2_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs),
|
||||
.main_clk = "gpio2_ick",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -1821,6 +1821,7 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
|
||||
static struct omap_hwmod omap44xx_gpio3_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
|
||||
{ .irq = 31 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
|
||||
@ -1855,7 +1856,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
|
||||
.class = &omap44xx_gpio_hwmod_class,
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap44xx_gpio3_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs),
|
||||
.main_clk = "gpio3_ick",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -1874,6 +1874,7 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
|
||||
static struct omap_hwmod omap44xx_gpio4_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
|
||||
{ .irq = 32 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
|
||||
@ -1908,7 +1909,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
|
||||
.class = &omap44xx_gpio_hwmod_class,
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap44xx_gpio4_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs),
|
||||
.main_clk = "gpio4_ick",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -1927,6 +1927,7 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
|
||||
static struct omap_hwmod omap44xx_gpio5_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
|
||||
{ .irq = 33 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
|
||||
@ -1961,7 +1962,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
|
||||
.class = &omap44xx_gpio_hwmod_class,
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap44xx_gpio5_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs),
|
||||
.main_clk = "gpio5_ick",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -1980,6 +1980,7 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
|
||||
static struct omap_hwmod omap44xx_gpio6_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
|
||||
{ .irq = 34 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
|
||||
@ -2014,7 +2015,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
|
||||
.class = &omap44xx_gpio_hwmod_class,
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap44xx_gpio6_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs),
|
||||
.main_clk = "gpio6_ick",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -2058,6 +2058,7 @@ static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
|
||||
{ .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
/* hsi master ports */
|
||||
@ -2092,7 +2093,6 @@ static struct omap_hwmod omap44xx_hsi_hwmod = {
|
||||
.name = "hsi",
|
||||
.class = &omap44xx_hsi_hwmod_class,
|
||||
.mpu_irqs = omap44xx_hsi_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_hsi_irqs),
|
||||
.main_clk = "hsi_fck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -2131,6 +2131,7 @@ static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
|
||||
static struct omap_hwmod omap44xx_i2c1_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
|
||||
{ .irq = 56 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
|
||||
@ -2166,7 +2167,6 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
|
||||
.class = &omap44xx_i2c_hwmod_class,
|
||||
.flags = HWMOD_INIT_NO_RESET,
|
||||
.mpu_irqs = omap44xx_i2c1_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs),
|
||||
.sdma_reqs = omap44xx_i2c1_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
|
||||
.main_clk = "i2c1_fck",
|
||||
@ -2184,6 +2184,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
|
||||
static struct omap_hwmod omap44xx_i2c2_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
|
||||
{ .irq = 57 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
|
||||
@ -2219,7 +2220,6 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
|
||||
.class = &omap44xx_i2c_hwmod_class,
|
||||
.flags = HWMOD_INIT_NO_RESET,
|
||||
.mpu_irqs = omap44xx_i2c2_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs),
|
||||
.sdma_reqs = omap44xx_i2c2_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
|
||||
.main_clk = "i2c2_fck",
|
||||
@ -2237,6 +2237,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
|
||||
static struct omap_hwmod omap44xx_i2c3_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
|
||||
{ .irq = 61 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
|
||||
@ -2272,7 +2273,6 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
|
||||
.class = &omap44xx_i2c_hwmod_class,
|
||||
.flags = HWMOD_INIT_NO_RESET,
|
||||
.mpu_irqs = omap44xx_i2c3_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs),
|
||||
.sdma_reqs = omap44xx_i2c3_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
|
||||
.main_clk = "i2c3_fck",
|
||||
@ -2290,6 +2290,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
|
||||
static struct omap_hwmod omap44xx_i2c4_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
|
||||
{ .irq = 62 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
|
||||
@ -2325,7 +2326,6 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
|
||||
.class = &omap44xx_i2c_hwmod_class,
|
||||
.flags = HWMOD_INIT_NO_RESET,
|
||||
.mpu_irqs = omap44xx_i2c4_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs),
|
||||
.sdma_reqs = omap44xx_i2c4_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
|
||||
.main_clk = "i2c4_fck",
|
||||
@ -2351,6 +2351,7 @@ static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
|
||||
/* ipu */
|
||||
static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
|
||||
{ .irq = 100 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
|
||||
@ -2417,7 +2418,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
|
||||
.name = "ipu",
|
||||
.class = &omap44xx_ipu_hwmod_class,
|
||||
.mpu_irqs = omap44xx_ipu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_ipu_irqs),
|
||||
.rst_lines = omap44xx_ipu_resets,
|
||||
.rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
|
||||
.main_clk = "ipu_fck",
|
||||
@ -2458,6 +2458,7 @@ static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
|
||||
/* iss */
|
||||
static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
|
||||
{ .irq = 24 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
|
||||
@ -2503,7 +2504,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
|
||||
.name = "iss",
|
||||
.class = &omap44xx_iss_hwmod_class,
|
||||
.mpu_irqs = omap44xx_iss_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iss_irqs),
|
||||
.sdma_reqs = omap44xx_iss_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_iss_sdma_reqs),
|
||||
.main_clk = "iss_fck",
|
||||
@ -2535,6 +2535,7 @@ static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
|
||||
{ .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
|
||||
@ -2613,7 +2614,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
|
||||
.name = "iva",
|
||||
.class = &omap44xx_iva_hwmod_class,
|
||||
.mpu_irqs = omap44xx_iva_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iva_irqs),
|
||||
.rst_lines = omap44xx_iva_resets,
|
||||
.rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
|
||||
.main_clk = "iva_fck",
|
||||
@ -2656,6 +2656,7 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
|
||||
static struct omap_hwmod omap44xx_kbd_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
|
||||
{ .irq = 120 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
|
||||
@ -2685,7 +2686,6 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
|
||||
.name = "kbd",
|
||||
.class = &omap44xx_kbd_hwmod_class,
|
||||
.mpu_irqs = omap44xx_kbd_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_kbd_irqs),
|
||||
.main_clk = "kbd_fck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -2721,6 +2721,7 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
|
||||
static struct omap_hwmod omap44xx_mailbox_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
|
||||
{ .irq = 26 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
|
||||
@ -2750,7 +2751,6 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = {
|
||||
.name = "mailbox",
|
||||
.class = &omap44xx_mailbox_hwmod_class,
|
||||
.mpu_irqs = omap44xx_mailbox_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mailbox_irqs),
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
|
||||
@ -2784,6 +2784,7 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
|
||||
static struct omap_hwmod omap44xx_mcbsp1_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
|
||||
{ .irq = 17 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
|
||||
@ -2839,7 +2840,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
|
||||
.name = "mcbsp1",
|
||||
.class = &omap44xx_mcbsp_hwmod_class,
|
||||
.mpu_irqs = omap44xx_mcbsp1_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_irqs),
|
||||
.sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs),
|
||||
.main_clk = "mcbsp1_fck",
|
||||
@ -2857,6 +2857,7 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
|
||||
static struct omap_hwmod omap44xx_mcbsp2_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
|
||||
{ .irq = 22 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
|
||||
@ -2912,7 +2913,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
|
||||
.name = "mcbsp2",
|
||||
.class = &omap44xx_mcbsp_hwmod_class,
|
||||
.mpu_irqs = omap44xx_mcbsp2_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_irqs),
|
||||
.sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs),
|
||||
.main_clk = "mcbsp2_fck",
|
||||
@ -2930,6 +2930,7 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
|
||||
static struct omap_hwmod omap44xx_mcbsp3_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
|
||||
{ .irq = 23 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
|
||||
@ -2985,7 +2986,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
|
||||
.name = "mcbsp3",
|
||||
.class = &omap44xx_mcbsp_hwmod_class,
|
||||
.mpu_irqs = omap44xx_mcbsp3_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_irqs),
|
||||
.sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs),
|
||||
.main_clk = "mcbsp3_fck",
|
||||
@ -3003,6 +3003,7 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
|
||||
static struct omap_hwmod omap44xx_mcbsp4_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
|
||||
{ .irq = 16 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
|
||||
@ -3037,7 +3038,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
|
||||
.name = "mcbsp4",
|
||||
.class = &omap44xx_mcbsp_hwmod_class,
|
||||
.mpu_irqs = omap44xx_mcbsp4_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_irqs),
|
||||
.sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs),
|
||||
.main_clk = "mcbsp4_fck",
|
||||
@ -3076,6 +3076,7 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
|
||||
static struct omap_hwmod omap44xx_mcpdm_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
|
||||
{ .irq = 112 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
|
||||
@ -3129,7 +3130,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
|
||||
.name = "mcpdm",
|
||||
.class = &omap44xx_mcpdm_hwmod_class,
|
||||
.mpu_irqs = omap44xx_mcpdm_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_irqs),
|
||||
.sdma_reqs = omap44xx_mcpdm_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs),
|
||||
.main_clk = "mcpdm_fck",
|
||||
@ -3169,6 +3169,7 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
|
||||
static struct omap_hwmod omap44xx_mcspi1_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
|
||||
{ .irq = 65 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
|
||||
@ -3214,7 +3215,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
|
||||
.name = "mcspi1",
|
||||
.class = &omap44xx_mcspi_hwmod_class,
|
||||
.mpu_irqs = omap44xx_mcspi1_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_irqs),
|
||||
.sdma_reqs = omap44xx_mcspi1_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
|
||||
.main_clk = "mcspi1_fck",
|
||||
@ -3233,6 +3233,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
|
||||
static struct omap_hwmod omap44xx_mcspi2_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
|
||||
{ .irq = 66 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
|
||||
@ -3274,7 +3275,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
|
||||
.name = "mcspi2",
|
||||
.class = &omap44xx_mcspi_hwmod_class,
|
||||
.mpu_irqs = omap44xx_mcspi2_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_irqs),
|
||||
.sdma_reqs = omap44xx_mcspi2_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
|
||||
.main_clk = "mcspi2_fck",
|
||||
@ -3293,6 +3293,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
|
||||
static struct omap_hwmod omap44xx_mcspi3_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
|
||||
{ .irq = 91 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
|
||||
@ -3334,7 +3335,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
|
||||
.name = "mcspi3",
|
||||
.class = &omap44xx_mcspi_hwmod_class,
|
||||
.mpu_irqs = omap44xx_mcspi3_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_irqs),
|
||||
.sdma_reqs = omap44xx_mcspi3_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
|
||||
.main_clk = "mcspi3_fck",
|
||||
@ -3353,6 +3353,7 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
|
||||
static struct omap_hwmod omap44xx_mcspi4_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
|
||||
{ .irq = 48 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
|
||||
@ -3392,7 +3393,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
|
||||
.name = "mcspi4",
|
||||
.class = &omap44xx_mcspi_hwmod_class,
|
||||
.mpu_irqs = omap44xx_mcspi4_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_irqs),
|
||||
.sdma_reqs = omap44xx_mcspi4_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
|
||||
.main_clk = "mcspi4_fck",
|
||||
@ -3433,6 +3433,7 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
|
||||
|
||||
static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
|
||||
{ .irq = 83 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
|
||||
@ -3477,7 +3478,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
|
||||
.name = "mmc1",
|
||||
.class = &omap44xx_mmc_hwmod_class,
|
||||
.mpu_irqs = omap44xx_mmc1_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc1_irqs),
|
||||
.sdma_reqs = omap44xx_mmc1_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs),
|
||||
.main_clk = "mmc1_fck",
|
||||
@ -3497,6 +3497,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
|
||||
/* mmc2 */
|
||||
static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
|
||||
{ .irq = 86 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
|
||||
@ -3536,7 +3537,6 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
|
||||
.name = "mmc2",
|
||||
.class = &omap44xx_mmc_hwmod_class,
|
||||
.mpu_irqs = omap44xx_mmc2_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc2_irqs),
|
||||
.sdma_reqs = omap44xx_mmc2_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs),
|
||||
.main_clk = "mmc2_fck",
|
||||
@ -3556,6 +3556,7 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
|
||||
static struct omap_hwmod omap44xx_mmc3_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
|
||||
{ .irq = 94 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
|
||||
@ -3590,7 +3591,6 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
|
||||
.name = "mmc3",
|
||||
.class = &omap44xx_mmc_hwmod_class,
|
||||
.mpu_irqs = omap44xx_mmc3_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc3_irqs),
|
||||
.sdma_reqs = omap44xx_mmc3_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs),
|
||||
.main_clk = "mmc3_fck",
|
||||
@ -3608,6 +3608,7 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
|
||||
static struct omap_hwmod omap44xx_mmc4_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
|
||||
{ .irq = 96 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
|
||||
@ -3642,7 +3643,7 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
|
||||
.name = "mmc4",
|
||||
.class = &omap44xx_mmc_hwmod_class,
|
||||
.mpu_irqs = omap44xx_mmc4_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc4_irqs),
|
||||
|
||||
.sdma_reqs = omap44xx_mmc4_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs),
|
||||
.main_clk = "mmc4_fck",
|
||||
@ -3660,6 +3661,7 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
|
||||
static struct omap_hwmod omap44xx_mmc5_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
|
||||
{ .irq = 59 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
|
||||
@ -3694,7 +3696,6 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
|
||||
.name = "mmc5",
|
||||
.class = &omap44xx_mmc_hwmod_class,
|
||||
.mpu_irqs = omap44xx_mmc5_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc5_irqs),
|
||||
.sdma_reqs = omap44xx_mmc5_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs),
|
||||
.main_clk = "mmc5_fck",
|
||||
@ -3722,6 +3723,7 @@ static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
|
||||
{ .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
/* mpu master ports */
|
||||
@ -3736,7 +3738,6 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
|
||||
.class = &omap44xx_mpu_hwmod_class,
|
||||
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
|
||||
.mpu_irqs = omap44xx_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs),
|
||||
.main_clk = "dpll_mpu_m2_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -3778,6 +3779,7 @@ static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
|
||||
static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
|
||||
{ .irq = 19 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
|
||||
@ -3807,7 +3809,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
|
||||
.name = "smartreflex_core",
|
||||
.class = &omap44xx_smartreflex_hwmod_class,
|
||||
.mpu_irqs = omap44xx_smartreflex_core_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
|
||||
|
||||
.main_clk = "smartreflex_core_fck",
|
||||
.vdd_name = "core",
|
||||
.prcm = {
|
||||
@ -3824,6 +3826,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
|
||||
static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
|
||||
{ .irq = 102 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
|
||||
@ -3853,7 +3856,6 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
|
||||
.name = "smartreflex_iva",
|
||||
.class = &omap44xx_smartreflex_hwmod_class,
|
||||
.mpu_irqs = omap44xx_smartreflex_iva_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
|
||||
.main_clk = "smartreflex_iva_fck",
|
||||
.vdd_name = "iva",
|
||||
.prcm = {
|
||||
@ -3870,6 +3872,7 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
|
||||
static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
|
||||
{ .irq = 18 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
|
||||
@ -3899,7 +3902,6 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
|
||||
.name = "smartreflex_mpu",
|
||||
.class = &omap44xx_smartreflex_hwmod_class,
|
||||
.mpu_irqs = omap44xx_smartreflex_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
|
||||
.main_clk = "smartreflex_mpu_fck",
|
||||
.vdd_name = "mpu",
|
||||
.prcm = {
|
||||
@ -4015,6 +4017,7 @@ static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
|
||||
static struct omap_hwmod omap44xx_timer1_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
|
||||
{ .irq = 37 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
|
||||
@ -4044,7 +4047,6 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
|
||||
.name = "timer1",
|
||||
.class = &omap44xx_timer_1ms_hwmod_class,
|
||||
.mpu_irqs = omap44xx_timer1_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs),
|
||||
.main_clk = "timer1_fck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -4060,6 +4062,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
|
||||
static struct omap_hwmod omap44xx_timer2_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
|
||||
{ .irq = 38 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
|
||||
@ -4089,7 +4092,6 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
|
||||
.name = "timer2",
|
||||
.class = &omap44xx_timer_1ms_hwmod_class,
|
||||
.mpu_irqs = omap44xx_timer2_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer2_irqs),
|
||||
.main_clk = "timer2_fck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -4105,6 +4107,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
|
||||
static struct omap_hwmod omap44xx_timer3_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
|
||||
{ .irq = 39 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
|
||||
@ -4134,7 +4137,6 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
|
||||
.name = "timer3",
|
||||
.class = &omap44xx_timer_hwmod_class,
|
||||
.mpu_irqs = omap44xx_timer3_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer3_irqs),
|
||||
.main_clk = "timer3_fck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -4150,6 +4152,7 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
|
||||
static struct omap_hwmod omap44xx_timer4_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
|
||||
{ .irq = 40 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
|
||||
@ -4179,7 +4182,6 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
|
||||
.name = "timer4",
|
||||
.class = &omap44xx_timer_hwmod_class,
|
||||
.mpu_irqs = omap44xx_timer4_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer4_irqs),
|
||||
.main_clk = "timer4_fck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -4195,6 +4197,7 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
|
||||
static struct omap_hwmod omap44xx_timer5_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
|
||||
{ .irq = 41 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
|
||||
@ -4243,7 +4246,6 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
|
||||
.name = "timer5",
|
||||
.class = &omap44xx_timer_hwmod_class,
|
||||
.mpu_irqs = omap44xx_timer5_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer5_irqs),
|
||||
.main_clk = "timer5_fck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -4259,6 +4261,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
|
||||
static struct omap_hwmod omap44xx_timer6_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
|
||||
{ .irq = 42 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
|
||||
@ -4307,7 +4310,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
|
||||
.name = "timer6",
|
||||
.class = &omap44xx_timer_hwmod_class,
|
||||
.mpu_irqs = omap44xx_timer6_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer6_irqs),
|
||||
|
||||
.main_clk = "timer6_fck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -4323,6 +4326,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
|
||||
static struct omap_hwmod omap44xx_timer7_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
|
||||
{ .irq = 43 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
|
||||
@ -4371,7 +4375,6 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
|
||||
.name = "timer7",
|
||||
.class = &omap44xx_timer_hwmod_class,
|
||||
.mpu_irqs = omap44xx_timer7_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer7_irqs),
|
||||
.main_clk = "timer7_fck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -4387,6 +4390,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
|
||||
static struct omap_hwmod omap44xx_timer8_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
|
||||
{ .irq = 44 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
|
||||
@ -4435,7 +4439,6 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
|
||||
.name = "timer8",
|
||||
.class = &omap44xx_timer_hwmod_class,
|
||||
.mpu_irqs = omap44xx_timer8_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer8_irqs),
|
||||
.main_clk = "timer8_fck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -4451,6 +4454,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
|
||||
static struct omap_hwmod omap44xx_timer9_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
|
||||
{ .irq = 45 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
|
||||
@ -4480,7 +4484,6 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
|
||||
.name = "timer9",
|
||||
.class = &omap44xx_timer_hwmod_class,
|
||||
.mpu_irqs = omap44xx_timer9_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer9_irqs),
|
||||
.main_clk = "timer9_fck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -4496,6 +4499,7 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
|
||||
static struct omap_hwmod omap44xx_timer10_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
|
||||
{ .irq = 46 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
|
||||
@ -4525,7 +4529,6 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
|
||||
.name = "timer10",
|
||||
.class = &omap44xx_timer_1ms_hwmod_class,
|
||||
.mpu_irqs = omap44xx_timer10_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer10_irqs),
|
||||
.main_clk = "timer10_fck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -4541,6 +4544,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
|
||||
static struct omap_hwmod omap44xx_timer11_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
|
||||
{ .irq = 47 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
|
||||
@ -4570,7 +4574,6 @@ static struct omap_hwmod omap44xx_timer11_hwmod = {
|
||||
.name = "timer11",
|
||||
.class = &omap44xx_timer_hwmod_class,
|
||||
.mpu_irqs = omap44xx_timer11_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer11_irqs),
|
||||
.main_clk = "timer11_fck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -4608,6 +4611,7 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
|
||||
static struct omap_hwmod omap44xx_uart1_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
|
||||
{ .irq = 72 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
|
||||
@ -4642,7 +4646,6 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
|
||||
.name = "uart1",
|
||||
.class = &omap44xx_uart_hwmod_class,
|
||||
.mpu_irqs = omap44xx_uart1_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs),
|
||||
.sdma_reqs = omap44xx_uart1_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
|
||||
.main_clk = "uart1_fck",
|
||||
@ -4660,6 +4663,7 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
|
||||
static struct omap_hwmod omap44xx_uart2_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
|
||||
{ .irq = 73 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
|
||||
@ -4694,7 +4698,6 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
|
||||
.name = "uart2",
|
||||
.class = &omap44xx_uart_hwmod_class,
|
||||
.mpu_irqs = omap44xx_uart2_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs),
|
||||
.sdma_reqs = omap44xx_uart2_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
|
||||
.main_clk = "uart2_fck",
|
||||
@ -4712,6 +4715,7 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
|
||||
static struct omap_hwmod omap44xx_uart3_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
|
||||
{ .irq = 74 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
|
||||
@ -4747,7 +4751,6 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
|
||||
.class = &omap44xx_uart_hwmod_class,
|
||||
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
|
||||
.mpu_irqs = omap44xx_uart3_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs),
|
||||
.sdma_reqs = omap44xx_uart3_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
|
||||
.main_clk = "uart3_fck",
|
||||
@ -4765,6 +4768,7 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
|
||||
static struct omap_hwmod omap44xx_uart4_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
|
||||
{ .irq = 70 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
|
||||
@ -4799,7 +4803,6 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
|
||||
.name = "uart4",
|
||||
.class = &omap44xx_uart_hwmod_class,
|
||||
.mpu_irqs = omap44xx_uart4_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs),
|
||||
.sdma_reqs = omap44xx_uart4_sdma_reqs,
|
||||
.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
|
||||
.main_clk = "uart4_fck",
|
||||
@ -4840,6 +4843,7 @@ static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
|
||||
static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
|
||||
{ .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
/* usb_otg_hs master ports */
|
||||
@ -4879,7 +4883,6 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
|
||||
.class = &omap44xx_usb_otg_hs_hwmod_class,
|
||||
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
|
||||
.mpu_irqs = omap44xx_usb_otg_hs_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs),
|
||||
.main_clk = "usb_otg_hs_ick",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -4922,6 +4925,7 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
|
||||
static struct omap_hwmod omap44xx_wd_timer2_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
|
||||
{ .irq = 80 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
|
||||
@ -4951,7 +4955,6 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
|
||||
.name = "wd_timer2",
|
||||
.class = &omap44xx_wd_timer_hwmod_class,
|
||||
.mpu_irqs = omap44xx_wd_timer2_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
|
||||
.main_clk = "wd_timer2_fck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -4967,6 +4970,7 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
|
||||
static struct omap_hwmod omap44xx_wd_timer3_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
|
||||
{ .irq = 36 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
|
||||
@ -5015,7 +5019,6 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
|
||||
.name = "wd_timer3",
|
||||
.class = &omap44xx_wd_timer_hwmod_class,
|
||||
.mpu_irqs = omap44xx_wd_timer3_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
|
||||
.main_clk = "wd_timer3_fck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
|
@ -98,7 +98,7 @@ struct omap_hwmod_mux_info {
|
||||
/**
|
||||
* struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
|
||||
* @name: name of the IRQ channel (module local name)
|
||||
* @irq_ch: IRQ channel ID
|
||||
* @irq: IRQ channel ID (should be non-negative except -1 = terminator)
|
||||
*
|
||||
* @name should be something short, e.g., "tx" or "rx". It is for use
|
||||
* by platform_get_resource_byname(). It is defined locally to the
|
||||
@ -106,7 +106,7 @@ struct omap_hwmod_mux_info {
|
||||
*/
|
||||
struct omap_hwmod_irq_info {
|
||||
const char *name;
|
||||
u16 irq;
|
||||
s16 irq;
|
||||
};
|
||||
|
||||
/**
|
||||
@ -466,7 +466,7 @@ struct omap_hwmod_class {
|
||||
* @name: name of the hwmod
|
||||
* @class: struct omap_hwmod_class * to the class of this hwmod
|
||||
* @od: struct omap_device currently associated with this hwmod (internal use)
|
||||
* @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt)
|
||||
* @mpu_irqs: ptr to an array of MPU IRQs
|
||||
* @sdma_reqs: ptr to an array of System DMA request IDs (see sdma_reqs_cnt)
|
||||
* @prcm: PRCM data pertaining to this hwmod
|
||||
* @main_clk: main clock: OMAP clock name
|
||||
@ -480,7 +480,6 @@ struct omap_hwmod_class {
|
||||
* @_sysc_cache: internal-use hwmod flags
|
||||
* @_mpu_rt_va: cached register target start address (internal use)
|
||||
* @_mpu_port_index: cached MPU register target slave ID (internal use)
|
||||
* @mpu_irqs_cnt: number of @mpu_irqs
|
||||
* @sdma_reqs_cnt: number of @sdma_reqs
|
||||
* @opt_clks_cnt: number of @opt_clks
|
||||
* @master_cnt: number of @master entries
|
||||
@ -529,7 +528,6 @@ struct omap_hwmod {
|
||||
u16 flags;
|
||||
u8 _mpu_port_index;
|
||||
u8 response_lat;
|
||||
u8 mpu_irqs_cnt;
|
||||
u8 sdma_reqs_cnt;
|
||||
u8 rst_lines_cnt;
|
||||
u8 opt_clks_cnt;
|
||||
|
Loading…
Reference in New Issue
Block a user