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drm/nv40: Try to set up CRE_LCD even if it has unknown bits set.

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They don't seem to do anything useful, and we really want to program
CRE_LCD if we aren't lucky enough to find the right CRTC binding
already set.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Francisco Jerez 2010-08-30 19:55:52 +02:00 committed by Ben Skeggs
parent 7314dec95c
commit 217275d03d
3 changed files with 19 additions and 35 deletions
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8
drivers/gpu/drm/nouveau/nv04_dac.c
View File

@ -352,15 +352,9 @@ static void nv04_dac_prepare(struct drm_encoder *encoder)
helper->dpms(encoder, DRM_MODE_DPMS_OFF);
nv04_dfp_disable(dev, head);
/* Some NV4x have unknown values (0x3f, 0x50, 0x54, 0x6b, 0x79, 0x7f)
* at LCD__INDEX which we don't alter
*/
if (!(crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] & 0x44))
crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] = 0;
crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] = 0;
}
static void nv04_dac_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)

33
drivers/gpu/drm/nouveau/nv04_dfp.c
View File

@ -253,26 +253,21 @@ static void nv04_dfp_prepare(struct drm_encoder *encoder)
nv04_dfp_prepare_sel_clk(dev, nv_encoder, head);
/* Some NV4x have unknown values (0x3f, 0x50, 0x54, 0x6b, 0x79, 0x7f)
* at LCD__INDEX which we don't alter
*/
if (!(*cr_lcd & 0x44)) {
*cr_lcd = 0x3;
*cr_lcd = 0x3;
if (nv_two_heads(dev)) {
if (nv_encoder->dcb->location == DCB_LOC_ON_CHIP)
*cr_lcd |= head ? 0x0 : 0x8;
else {
*cr_lcd |= (nv_encoder->dcb->or << 4) & 0x30;
if (nv_encoder->dcb->type == OUTPUT_LVDS)
*cr_lcd |= 0x30;
if ((*cr_lcd & 0x30) == (*cr_lcd_oth & 0x30)) {
/* avoid being connected to both crtcs */
*cr_lcd_oth &= ~0x30;
NVWriteVgaCrtc(dev, head ^ 1,
NV_CIO_CRE_LCD__INDEX,
*cr_lcd_oth);
}
if (nv_two_heads(dev)) {
if (nv_encoder->dcb->location == DCB_LOC_ON_CHIP)
*cr_lcd |= head ? 0x0 : 0x8;
else {
*cr_lcd |= (nv_encoder->dcb->or << 4) & 0x30;
if (nv_encoder->dcb->type == OUTPUT_LVDS)
*cr_lcd |= 0x30;
if ((*cr_lcd & 0x30) == (*cr_lcd_oth & 0x30)) {
/* avoid being connected to both crtcs */
*cr_lcd_oth &= ~0x30;
NVWriteVgaCrtc(dev, head ^ 1,
NV_CIO_CRE_LCD__INDEX,
*cr_lcd_oth);
}
}
}

13
drivers/gpu/drm/nouveau/nv17_tv.c
View File

@ -408,15 +408,10 @@ static void nv17_tv_prepare(struct drm_encoder *encoder)
}
/* Some NV4x have unknown values (0x3f, 0x50, 0x54, 0x6b, 0x79, 0x7f)
* at LCD__INDEX which we don't alter
*/
if (!(*cr_lcd & 0x44)) {
if (tv_norm->kind == CTV_ENC_MODE)
*cr_lcd = 0x1 | (head ? 0x0 : 0x8);
else
*cr_lcd = 0;
}
if (tv_norm->kind == CTV_ENC_MODE)
*cr_lcd = 0x1 | (head ? 0x0 : 0x8);
else
*cr_lcd = 0;
/* Set the DACCLK register */
dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;