USB: host: Remove ehci-octeon and ohci-octeon drivers
Remove special-purpose octeon drivers and instead use ehci-platform and ohci-platform as suggested with http://marc.info/?l=linux-mips&m=140139694721623&w=2 [andreas.herrmann: fixed compile error] Cc: David Daney <david.daney@cavium.com> Cc: Alex Smith <alex.smith@imgtec.com> Signed-off-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
parent
f910b6cba2
commit
2193dda5ee
@ -7,22 +7,27 @@
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* Copyright (C) 2008 Wind River Systems
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/i2c.h>
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#include <linux/usb.h>
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#include <linux/dma-mapping.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/of_platform.h>
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#include <linux/of_fdt.h>
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#include <linux/libfdt.h>
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#include <linux/usb/ehci_pdriver.h>
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#include <linux/usb/ohci_pdriver.h>
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-rnm-defs.h>
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#include <asm/octeon/cvmx-helper.h>
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#include <asm/octeon/cvmx-helper-board.h>
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#include <asm/octeon/cvmx-uctlx-defs.h>
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/* Octeon Random Number Generator. */
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static int __init octeon_rng_device_init(void)
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@ -68,6 +73,229 @@ device_initcall(octeon_rng_device_init);
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#ifdef CONFIG_USB
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static DEFINE_MUTEX(octeon2_usb_clocks_mutex);
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static int octeon2_usb_clock_start_cnt;
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static void octeon2_usb_clocks_start(void)
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{
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u64 div;
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union cvmx_uctlx_if_ena if_ena;
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union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
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union cvmx_uctlx_uphy_ctl_status uphy_ctl_status;
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union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status;
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int i;
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unsigned long io_clk_64_to_ns;
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mutex_lock(&octeon2_usb_clocks_mutex);
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octeon2_usb_clock_start_cnt++;
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if (octeon2_usb_clock_start_cnt != 1)
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goto exit;
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io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate();
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/*
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* Step 1: Wait for voltages stable. That surely happened
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* before starting the kernel.
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*
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* Step 2: Enable SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1
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*/
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if_ena.u64 = 0;
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if_ena.s.en = 1;
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cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
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/* Step 3: Configure the reference clock, PHY, and HCLK */
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clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
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/*
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* If the UCTL looks like it has already been started, skip
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* the initialization, otherwise bus errors are obtained.
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*/
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if (clk_rst_ctl.s.hrst)
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goto end_clock;
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/* 3a */
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clk_rst_ctl.s.p_por = 1;
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clk_rst_ctl.s.hrst = 0;
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clk_rst_ctl.s.p_prst = 0;
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clk_rst_ctl.s.h_clkdiv_rst = 0;
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clk_rst_ctl.s.o_clkdiv_rst = 0;
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clk_rst_ctl.s.h_clkdiv_en = 0;
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clk_rst_ctl.s.o_clkdiv_en = 0;
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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/* 3b */
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/* 12MHz crystal. */
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clk_rst_ctl.s.p_refclk_sel = 0;
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clk_rst_ctl.s.p_refclk_div = 0;
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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/* 3c */
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div = octeon_get_io_clock_rate() / 130000000ull;
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switch (div) {
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case 0:
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div = 1;
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break;
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case 1:
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case 2:
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case 3:
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case 4:
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break;
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case 5:
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div = 4;
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break;
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case 6:
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case 7:
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div = 6;
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break;
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case 8:
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case 9:
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case 10:
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case 11:
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div = 8;
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break;
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default:
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div = 12;
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break;
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}
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clk_rst_ctl.s.h_div = div;
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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/* Read it back, */
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clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
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clk_rst_ctl.s.h_clkdiv_en = 1;
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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/* 3d */
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clk_rst_ctl.s.h_clkdiv_rst = 1;
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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/* 3e: delay 64 io clocks */
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ndelay(io_clk_64_to_ns);
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/*
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* Step 4: Program the power-on reset field in the UCTL
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* clock-reset-control register.
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*/
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clk_rst_ctl.s.p_por = 0;
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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/* Step 5: Wait 1 ms for the PHY clock to start. */
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mdelay(1);
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/*
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* Step 6: Program the reset input from automatic test
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* equipment field in the UPHY CSR
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*/
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uphy_ctl_status.u64 = cvmx_read_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0));
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uphy_ctl_status.s.ate_reset = 1;
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cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64);
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/* Step 7: Wait for at least 10ns. */
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ndelay(10);
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/* Step 8: Clear the ATE_RESET field in the UPHY CSR. */
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uphy_ctl_status.s.ate_reset = 0;
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cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64);
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/*
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* Step 9: Wait for at least 20ns for UPHY to output PHY clock
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* signals and OHCI_CLK48
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*/
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ndelay(20);
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/* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */
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/* 10a */
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clk_rst_ctl.s.o_clkdiv_rst = 1;
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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/* 10b */
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clk_rst_ctl.s.o_clkdiv_en = 1;
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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/* 10c */
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ndelay(io_clk_64_to_ns);
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/*
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* Step 11: Program the PHY reset field:
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* UCTL0_CLK_RST_CTL[P_PRST] = 1
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*/
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clk_rst_ctl.s.p_prst = 1;
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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/* Step 12: Wait 1 uS. */
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udelay(1);
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/* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */
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clk_rst_ctl.s.hrst = 1;
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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end_clock:
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/* Now we can set some other registers. */
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for (i = 0; i <= 1; i++) {
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port_ctl_status.u64 =
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cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0));
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/* Set txvreftune to 15 to obtain compliant 'eye' diagram. */
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port_ctl_status.s.txvreftune = 15;
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port_ctl_status.s.txrisetune = 1;
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port_ctl_status.s.txpreemphasistune = 1;
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cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0),
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port_ctl_status.u64);
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}
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/* Set uSOF cycle period to 60,000 bits. */
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cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull);
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exit:
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mutex_unlock(&octeon2_usb_clocks_mutex);
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}
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static void octeon2_usb_clocks_stop(void)
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{
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mutex_lock(&octeon2_usb_clocks_mutex);
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octeon2_usb_clock_start_cnt--;
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mutex_unlock(&octeon2_usb_clocks_mutex);
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}
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static int octeon_ehci_power_on(struct platform_device *pdev)
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{
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octeon2_usb_clocks_start();
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return 0;
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}
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static void octeon_ehci_power_off(struct platform_device *pdev)
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{
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octeon2_usb_clocks_stop();
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}
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static struct usb_ehci_pdata octeon_ehci_pdata = {
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/* Octeon EHCI matches CPU endianness. */
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#ifdef __BIG_ENDIAN
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.big_endian_mmio = 1,
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#endif
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.power_on = octeon_ehci_power_on,
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.power_off = octeon_ehci_power_off,
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};
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static void __init octeon_ehci_hw_start(void)
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{
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union cvmx_uctlx_ehci_ctl ehci_ctl;
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octeon2_usb_clocks_start();
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ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0));
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/* Use 64-bit addressing. */
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ehci_ctl.s.ehci_64b_addr_en = 1;
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ehci_ctl.s.l2c_addr_msb = 0;
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ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
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ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
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cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64);
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octeon2_usb_clocks_stop();
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}
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static u64 octeon_ehci_dma_mask = DMA_BIT_MASK(64);
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static int __init octeon_ehci_device_init(void)
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{
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struct platform_device *pd;
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@ -88,7 +316,7 @@ static int __init octeon_ehci_device_init(void)
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if (octeon_is_simulation() || usb_disabled())
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return 0; /* No USB in the simulator. */
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pd = platform_device_alloc("octeon-ehci", 0);
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pd = platform_device_alloc("ehci-platform", 0);
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if (!pd) {
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ret = -ENOMEM;
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goto out;
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@ -105,6 +333,10 @@ static int __init octeon_ehci_device_init(void)
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if (ret)
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goto fail;
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pd->dev.dma_mask = &octeon_ehci_dma_mask;
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pd->dev.platform_data = &octeon_ehci_pdata;
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octeon_ehci_hw_start();
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ret = platform_device_add(pd);
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if (ret)
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goto fail;
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@ -117,6 +349,41 @@ out:
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}
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device_initcall(octeon_ehci_device_init);
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static int octeon_ohci_power_on(struct platform_device *pdev)
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{
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octeon2_usb_clocks_start();
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return 0;
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}
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static void octeon_ohci_power_off(struct platform_device *pdev)
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{
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octeon2_usb_clocks_stop();
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}
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static struct usb_ohci_pdata octeon_ohci_pdata = {
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/* Octeon OHCI matches CPU endianness. */
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#ifdef __BIG_ENDIAN
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.big_endian_mmio = 1,
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#endif
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.power_on = octeon_ohci_power_on,
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.power_off = octeon_ohci_power_off,
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};
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static void __init octeon_ohci_hw_start(void)
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{
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union cvmx_uctlx_ohci_ctl ohci_ctl;
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octeon2_usb_clocks_start();
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ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0));
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ohci_ctl.s.l2c_addr_msb = 0;
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ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
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ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
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cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64);
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octeon2_usb_clocks_stop();
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}
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static int __init octeon_ohci_device_init(void)
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{
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struct platform_device *pd;
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@ -137,7 +404,7 @@ static int __init octeon_ohci_device_init(void)
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if (octeon_is_simulation() || usb_disabled())
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return 0; /* No USB in the simulator. */
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pd = platform_device_alloc("octeon-ohci", 0);
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pd = platform_device_alloc("ohci-platform", 0);
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if (!pd) {
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ret = -ENOMEM;
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goto out;
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@ -154,6 +421,9 @@ static int __init octeon_ohci_device_init(void)
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if (ret)
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goto fail;
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pd->dev.platform_data = &octeon_ohci_pdata;
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octeon_ohci_hw_start();
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ret = platform_device_add(pd);
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if (ret)
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goto fail;
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@ -120,6 +120,9 @@ CONFIG_SPI_OCTEON=y
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# CONFIG_HWMON is not set
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CONFIG_WATCHDOG=y
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# CONFIG_USB_SUPPORT is not set
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CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
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CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
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CONFIG_USB_OHCI_LITTLE_ENDIAN=y
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_DRV_DS1307=y
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CONFIG_STAGING=y
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@ -292,11 +292,15 @@ config USB_EHCI_HCD_PLATFORM
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If unsure, say N.
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config USB_OCTEON_EHCI
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bool "Octeon on-chip EHCI support"
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bool "Octeon on-chip EHCI support (DEPRECATED)"
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depends on CAVIUM_OCTEON_SOC
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default n
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select USB_EHCI_BIG_ENDIAN_MMIO
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select USB_EHCI_HCD_PLATFORM
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help
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This option is deprecated now and the driver was removed, use
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USB_EHCI_HCD_PLATFORM instead.
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Enable support for the Octeon II SOC's on-chip EHCI
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controller. It is needed for high-speed (480Mbit/sec)
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USB 2.0 device support. All CN6XXX based chips with USB are
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@ -575,12 +579,16 @@ config USB_OHCI_HCD_PLATFORM
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If unsure, say N.
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config USB_OCTEON_OHCI
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bool "Octeon on-chip OHCI support"
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bool "Octeon on-chip OHCI support (DEPRECATED)"
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depends on CAVIUM_OCTEON_SOC
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default USB_OCTEON_EHCI
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select USB_OHCI_BIG_ENDIAN_MMIO
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select USB_OHCI_LITTLE_ENDIAN
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select USB_OHCI_HCD_PLATFORM
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help
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This option is deprecated now and the driver was removed, use
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USB_OHCI_HCD_PLATFORM instead.
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Enable support for the Octeon II SOC's on-chip OHCI
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controller. It is needed for low-speed USB 1.0 device
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support. All CN6XXX based chips with USB are supported.
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@ -754,12 +762,6 @@ config USB_IMX21_HCD
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To compile this driver as a module, choose M here: the
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module will be called "imx21-hcd".
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config USB_OCTEON2_COMMON
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bool
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default y if USB_OCTEON_EHCI || USB_OCTEON_OHCI
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config USB_HCD_BCMA
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tristate "BCMA usb host driver"
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depends on BCMA
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@ -73,7 +73,6 @@ obj-$(CONFIG_USB_ISP1760_HCD) += isp1760.o
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obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o
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obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o
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obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o
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obj-$(CONFIG_USB_OCTEON2_COMMON) += octeon2-common.o
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obj-$(CONFIG_USB_HCD_BCMA) += bcma-hcd.o
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obj-$(CONFIG_USB_HCD_SSB) += ssb-hcd.o
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obj-$(CONFIG_USB_FUSBH200_HCD) += fusbh200-hcd.o
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@ -1275,11 +1275,6 @@ MODULE_LICENSE ("GPL");
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#define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver
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#endif
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#ifdef CONFIG_USB_OCTEON_EHCI
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#include "ehci-octeon.c"
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#define PLATFORM_DRIVER ehci_octeon_driver
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#endif
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#ifdef CONFIG_TILE_USB
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#include "ehci-tilegx.c"
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#define PLATFORM_DRIVER ehci_hcd_tilegx_driver
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|
@ -1,182 +0,0 @@
|
||||
/*
|
||||
* EHCI HCD glue for Cavium Octeon II SOCs.
|
||||
*
|
||||
* Loosely based on ehci-au1xxx.c
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2010 Cavium Networks
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/octeon/octeon.h>
|
||||
#include <asm/octeon/cvmx-uctlx-defs.h>
|
||||
|
||||
#define OCTEON_EHCI_HCD_NAME "octeon-ehci"
|
||||
|
||||
/* Common clock init code. */
|
||||
void octeon2_usb_clocks_start(void);
|
||||
void octeon2_usb_clocks_stop(void);
|
||||
|
||||
static void ehci_octeon_start(void)
|
||||
{
|
||||
union cvmx_uctlx_ehci_ctl ehci_ctl;
|
||||
|
||||
octeon2_usb_clocks_start();
|
||||
|
||||
ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0));
|
||||
/* Use 64-bit addressing. */
|
||||
ehci_ctl.s.ehci_64b_addr_en = 1;
|
||||
ehci_ctl.s.l2c_addr_msb = 0;
|
||||
ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
|
||||
ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
|
||||
cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64);
|
||||
}
|
||||
|
||||
static void ehci_octeon_stop(void)
|
||||
{
|
||||
octeon2_usb_clocks_stop();
|
||||
}
|
||||
|
||||
static const struct hc_driver ehci_octeon_hc_driver = {
|
||||
.description = hcd_name,
|
||||
.product_desc = "Octeon EHCI",
|
||||
.hcd_priv_size = sizeof(struct ehci_hcd),
|
||||
|
||||
/*
|
||||
* generic hardware linkage
|
||||
*/
|
||||
.irq = ehci_irq,
|
||||
.flags = HCD_MEMORY | HCD_USB2 | HCD_BH,
|
||||
|
||||
/*
|
||||
* basic lifecycle operations
|
||||
*/
|
||||
.reset = ehci_setup,
|
||||
.start = ehci_run,
|
||||
.stop = ehci_stop,
|
||||
.shutdown = ehci_shutdown,
|
||||
|
||||
/*
|
||||
* managing i/o requests and associated device resources
|
||||
*/
|
||||
.urb_enqueue = ehci_urb_enqueue,
|
||||
.urb_dequeue = ehci_urb_dequeue,
|
||||
.endpoint_disable = ehci_endpoint_disable,
|
||||
.endpoint_reset = ehci_endpoint_reset,
|
||||
|
||||
/*
|
||||
* scheduling support
|
||||
*/
|
||||
.get_frame_number = ehci_get_frame,
|
||||
|
||||
/*
|
||||
* root hub support
|
||||
*/
|
||||
.hub_status_data = ehci_hub_status_data,
|
||||
.hub_control = ehci_hub_control,
|
||||
.bus_suspend = ehci_bus_suspend,
|
||||
.bus_resume = ehci_bus_resume,
|
||||
.relinquish_port = ehci_relinquish_port,
|
||||
.port_handed_over = ehci_port_handed_over,
|
||||
|
||||
.clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
|
||||
};
|
||||
|
||||
static u64 ehci_octeon_dma_mask = DMA_BIT_MASK(64);
|
||||
|
||||
static int ehci_octeon_drv_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct usb_hcd *hcd;
|
||||
struct ehci_hcd *ehci;
|
||||
struct resource *res_mem;
|
||||
int irq;
|
||||
int ret;
|
||||
|
||||
if (usb_disabled())
|
||||
return -ENODEV;
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(&pdev->dev, "No irq assigned\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/*
|
||||
* We can DMA from anywhere. But the descriptors must be in
|
||||
* the lower 4GB.
|
||||
*/
|
||||
pdev->dev.dma_mask = &ehci_octeon_dma_mask;
|
||||
ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
hcd = usb_create_hcd(&ehci_octeon_hc_driver, &pdev->dev, "octeon");
|
||||
if (!hcd)
|
||||
return -ENOMEM;
|
||||
|
||||
res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
hcd->regs = devm_ioremap_resource(&pdev->dev, res_mem);
|
||||
if (IS_ERR(hcd->regs)) {
|
||||
ret = PTR_ERR(hcd->regs);
|
||||
goto err1;
|
||||
}
|
||||
hcd->rsrc_start = res_mem->start;
|
||||
hcd->rsrc_len = resource_size(res_mem);
|
||||
|
||||
ehci_octeon_start();
|
||||
|
||||
ehci = hcd_to_ehci(hcd);
|
||||
|
||||
/* Octeon EHCI matches CPU endianness. */
|
||||
#ifdef __BIG_ENDIAN
|
||||
ehci->big_endian_mmio = 1;
|
||||
#endif
|
||||
|
||||
ehci->caps = hcd->regs;
|
||||
|
||||
ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
|
||||
if (ret) {
|
||||
dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret);
|
||||
goto err2;
|
||||
}
|
||||
device_wakeup_enable(hcd->self.controller);
|
||||
|
||||
platform_set_drvdata(pdev, hcd);
|
||||
|
||||
return 0;
|
||||
err2:
|
||||
ehci_octeon_stop();
|
||||
|
||||
err1:
|
||||
usb_put_hcd(hcd);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int ehci_octeon_drv_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct usb_hcd *hcd = platform_get_drvdata(pdev);
|
||||
|
||||
usb_remove_hcd(hcd);
|
||||
|
||||
ehci_octeon_stop();
|
||||
usb_put_hcd(hcd);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver ehci_octeon_driver = {
|
||||
.probe = ehci_octeon_drv_probe,
|
||||
.remove = ehci_octeon_drv_remove,
|
||||
.shutdown = usb_hcd_platform_shutdown,
|
||||
.driver = {
|
||||
.name = OCTEON_EHCI_HCD_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
}
|
||||
};
|
||||
|
||||
MODULE_ALIAS("platform:" OCTEON_EHCI_HCD_NAME);
|
@ -1,200 +0,0 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2010, 2011 Cavium Networks
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include <asm/octeon/octeon.h>
|
||||
#include <asm/octeon/cvmx-uctlx-defs.h>
|
||||
|
||||
static DEFINE_MUTEX(octeon2_usb_clocks_mutex);
|
||||
|
||||
static int octeon2_usb_clock_start_cnt;
|
||||
|
||||
void octeon2_usb_clocks_start(void)
|
||||
{
|
||||
u64 div;
|
||||
union cvmx_uctlx_if_ena if_ena;
|
||||
union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
|
||||
union cvmx_uctlx_uphy_ctl_status uphy_ctl_status;
|
||||
union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status;
|
||||
int i;
|
||||
unsigned long io_clk_64_to_ns;
|
||||
|
||||
|
||||
mutex_lock(&octeon2_usb_clocks_mutex);
|
||||
|
||||
octeon2_usb_clock_start_cnt++;
|
||||
if (octeon2_usb_clock_start_cnt != 1)
|
||||
goto exit;
|
||||
|
||||
io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate();
|
||||
|
||||
/*
|
||||
* Step 1: Wait for voltages stable. That surely happened
|
||||
* before starting the kernel.
|
||||
*
|
||||
* Step 2: Enable SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1
|
||||
*/
|
||||
if_ena.u64 = 0;
|
||||
if_ena.s.en = 1;
|
||||
cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
|
||||
|
||||
/* Step 3: Configure the reference clock, PHY, and HCLK */
|
||||
clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
|
||||
|
||||
/*
|
||||
* If the UCTL looks like it has already been started, skip
|
||||
* the initialization, otherwise bus errors are obtained.
|
||||
*/
|
||||
if (clk_rst_ctl.s.hrst)
|
||||
goto end_clock;
|
||||
/* 3a */
|
||||
clk_rst_ctl.s.p_por = 1;
|
||||
clk_rst_ctl.s.hrst = 0;
|
||||
clk_rst_ctl.s.p_prst = 0;
|
||||
clk_rst_ctl.s.h_clkdiv_rst = 0;
|
||||
clk_rst_ctl.s.o_clkdiv_rst = 0;
|
||||
clk_rst_ctl.s.h_clkdiv_en = 0;
|
||||
clk_rst_ctl.s.o_clkdiv_en = 0;
|
||||
cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
|
||||
|
||||
/* 3b */
|
||||
/* 12MHz crystal. */
|
||||
clk_rst_ctl.s.p_refclk_sel = 0;
|
||||
clk_rst_ctl.s.p_refclk_div = 0;
|
||||
cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
|
||||
|
||||
/* 3c */
|
||||
div = octeon_get_io_clock_rate() / 130000000ull;
|
||||
|
||||
switch (div) {
|
||||
case 0:
|
||||
div = 1;
|
||||
break;
|
||||
case 1:
|
||||
case 2:
|
||||
case 3:
|
||||
case 4:
|
||||
break;
|
||||
case 5:
|
||||
div = 4;
|
||||
break;
|
||||
case 6:
|
||||
case 7:
|
||||
div = 6;
|
||||
break;
|
||||
case 8:
|
||||
case 9:
|
||||
case 10:
|
||||
case 11:
|
||||
div = 8;
|
||||
break;
|
||||
default:
|
||||
div = 12;
|
||||
break;
|
||||
}
|
||||
clk_rst_ctl.s.h_div = div;
|
||||
cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
|
||||
/* Read it back, */
|
||||
clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
|
||||
clk_rst_ctl.s.h_clkdiv_en = 1;
|
||||
cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
|
||||
/* 3d */
|
||||
clk_rst_ctl.s.h_clkdiv_rst = 1;
|
||||
cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
|
||||
|
||||
/* 3e: delay 64 io clocks */
|
||||
ndelay(io_clk_64_to_ns);
|
||||
|
||||
/*
|
||||
* Step 4: Program the power-on reset field in the UCTL
|
||||
* clock-reset-control register.
|
||||
*/
|
||||
clk_rst_ctl.s.p_por = 0;
|
||||
cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
|
||||
|
||||
/* Step 5: Wait 1 ms for the PHY clock to start. */
|
||||
mdelay(1);
|
||||
|
||||
/*
|
||||
* Step 6: Program the reset input from automatic test
|
||||
* equipment field in the UPHY CSR
|
||||
*/
|
||||
uphy_ctl_status.u64 = cvmx_read_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0));
|
||||
uphy_ctl_status.s.ate_reset = 1;
|
||||
cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64);
|
||||
|
||||
/* Step 7: Wait for at least 10ns. */
|
||||
ndelay(10);
|
||||
|
||||
/* Step 8: Clear the ATE_RESET field in the UPHY CSR. */
|
||||
uphy_ctl_status.s.ate_reset = 0;
|
||||
cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64);
|
||||
|
||||
/*
|
||||
* Step 9: Wait for at least 20ns for UPHY to output PHY clock
|
||||
* signals and OHCI_CLK48
|
||||
*/
|
||||
ndelay(20);
|
||||
|
||||
/* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */
|
||||
/* 10a */
|
||||
clk_rst_ctl.s.o_clkdiv_rst = 1;
|
||||
cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
|
||||
|
||||
/* 10b */
|
||||
clk_rst_ctl.s.o_clkdiv_en = 1;
|
||||
cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
|
||||
|
||||
/* 10c */
|
||||
ndelay(io_clk_64_to_ns);
|
||||
|
||||
/*
|
||||
* Step 11: Program the PHY reset field:
|
||||
* UCTL0_CLK_RST_CTL[P_PRST] = 1
|
||||
*/
|
||||
clk_rst_ctl.s.p_prst = 1;
|
||||
cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
|
||||
|
||||
/* Step 12: Wait 1 uS. */
|
||||
udelay(1);
|
||||
|
||||
/* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */
|
||||
clk_rst_ctl.s.hrst = 1;
|
||||
cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
|
||||
|
||||
end_clock:
|
||||
/* Now we can set some other registers. */
|
||||
|
||||
for (i = 0; i <= 1; i++) {
|
||||
port_ctl_status.u64 =
|
||||
cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0));
|
||||
/* Set txvreftune to 15 to obtain compliant 'eye' diagram. */
|
||||
port_ctl_status.s.txvreftune = 15;
|
||||
port_ctl_status.s.txrisetune = 1;
|
||||
port_ctl_status.s.txpreemphasistune = 1;
|
||||
cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0),
|
||||
port_ctl_status.u64);
|
||||
}
|
||||
|
||||
/* Set uSOF cycle period to 60,000 bits. */
|
||||
cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull);
|
||||
exit:
|
||||
mutex_unlock(&octeon2_usb_clocks_mutex);
|
||||
}
|
||||
EXPORT_SYMBOL(octeon2_usb_clocks_start);
|
||||
|
||||
void octeon2_usb_clocks_stop(void)
|
||||
{
|
||||
mutex_lock(&octeon2_usb_clocks_mutex);
|
||||
octeon2_usb_clock_start_cnt--;
|
||||
mutex_unlock(&octeon2_usb_clocks_mutex);
|
||||
}
|
||||
EXPORT_SYMBOL(octeon2_usb_clocks_stop);
|
@ -1249,11 +1249,6 @@ MODULE_LICENSE ("GPL");
|
||||
#define PLATFORM_DRIVER ohci_hcd_jz4740_driver
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_OCTEON_OHCI
|
||||
#include "ohci-octeon.c"
|
||||
#define PLATFORM_DRIVER ohci_octeon_driver
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TILE_USB
|
||||
#include "ohci-tilegx.c"
|
||||
#define PLATFORM_DRIVER ohci_hcd_tilegx_driver
|
||||
|
@ -1,196 +0,0 @@
|
||||
/*
|
||||
* EHCI HCD glue for Cavium Octeon II SOCs.
|
||||
*
|
||||
* Loosely based on ehci-au1xxx.c
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2010 Cavium Networks
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/octeon/octeon.h>
|
||||
#include <asm/octeon/cvmx-uctlx-defs.h>
|
||||
|
||||
#define OCTEON_OHCI_HCD_NAME "octeon-ohci"
|
||||
|
||||
/* Common clock init code. */
|
||||
void octeon2_usb_clocks_start(void);
|
||||
void octeon2_usb_clocks_stop(void);
|
||||
|
||||
static void ohci_octeon_hw_start(void)
|
||||
{
|
||||
union cvmx_uctlx_ohci_ctl ohci_ctl;
|
||||
|
||||
octeon2_usb_clocks_start();
|
||||
|
||||
ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0));
|
||||
ohci_ctl.s.l2c_addr_msb = 0;
|
||||
ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
|
||||
ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
|
||||
cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64);
|
||||
|
||||
}
|
||||
|
||||
static void ohci_octeon_hw_stop(void)
|
||||
{
|
||||
/* Undo ohci_octeon_start() */
|
||||
octeon2_usb_clocks_stop();
|
||||
}
|
||||
|
||||
static int ohci_octeon_start(struct usb_hcd *hcd)
|
||||
{
|
||||
struct ohci_hcd *ohci = hcd_to_ohci(hcd);
|
||||
int ret;
|
||||
|
||||
ret = ohci_init(ohci);
|
||||
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = ohci_run(ohci);
|
||||
|
||||
if (ret < 0) {
|
||||
ohci_err(ohci, "can't start %s", hcd->self.bus_name);
|
||||
ohci_stop(hcd);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct hc_driver ohci_octeon_hc_driver = {
|
||||
.description = hcd_name,
|
||||
.product_desc = "Octeon OHCI",
|
||||
.hcd_priv_size = sizeof(struct ohci_hcd),
|
||||
|
||||
/*
|
||||
* generic hardware linkage
|
||||
*/
|
||||
.irq = ohci_irq,
|
||||
.flags = HCD_USB11 | HCD_MEMORY,
|
||||
|
||||
/*
|
||||
* basic lifecycle operations
|
||||
*/
|
||||
.start = ohci_octeon_start,
|
||||
.stop = ohci_stop,
|
||||
.shutdown = ohci_shutdown,
|
||||
|
||||
/*
|
||||
* managing i/o requests and associated device resources
|
||||
*/
|
||||
.urb_enqueue = ohci_urb_enqueue,
|
||||
.urb_dequeue = ohci_urb_dequeue,
|
||||
.endpoint_disable = ohci_endpoint_disable,
|
||||
|
||||
/*
|
||||
* scheduling support
|
||||
*/
|
||||
.get_frame_number = ohci_get_frame,
|
||||
|
||||
/*
|
||||
* root hub support
|
||||
*/
|
||||
.hub_status_data = ohci_hub_status_data,
|
||||
.hub_control = ohci_hub_control,
|
||||
|
||||
.start_port_reset = ohci_start_port_reset,
|
||||
};
|
||||
|
||||
static int ohci_octeon_drv_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct usb_hcd *hcd;
|
||||
struct ohci_hcd *ohci;
|
||||
void *reg_base;
|
||||
struct resource *res_mem;
|
||||
int irq;
|
||||
int ret;
|
||||
|
||||
if (usb_disabled())
|
||||
return -ENODEV;
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(&pdev->dev, "No irq assigned\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Ohci is a 32-bit device. */
|
||||
ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
hcd = usb_create_hcd(&ohci_octeon_hc_driver, &pdev->dev, "octeon");
|
||||
if (!hcd)
|
||||
return -ENOMEM;
|
||||
|
||||
res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
reg_base = devm_ioremap_resource(&pdev->dev, res_mem);
|
||||
if (IS_ERR(reg_base)) {
|
||||
ret = PTR_ERR(reg_base);
|
||||
goto err1;
|
||||
}
|
||||
hcd->rsrc_start = res_mem->start;
|
||||
hcd->rsrc_len = resource_size(res_mem);
|
||||
|
||||
ohci_octeon_hw_start();
|
||||
|
||||
hcd->regs = reg_base;
|
||||
|
||||
ohci = hcd_to_ohci(hcd);
|
||||
|
||||
/* Octeon OHCI matches CPU endianness. */
|
||||
#ifdef __BIG_ENDIAN
|
||||
ohci->flags |= OHCI_QUIRK_BE_MMIO;
|
||||
#endif
|
||||
|
||||
ohci_hcd_init(ohci);
|
||||
|
||||
ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
|
||||
if (ret) {
|
||||
dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret);
|
||||
goto err2;
|
||||
}
|
||||
|
||||
device_wakeup_enable(hcd->self.controller);
|
||||
|
||||
platform_set_drvdata(pdev, hcd);
|
||||
|
||||
return 0;
|
||||
|
||||
err2:
|
||||
ohci_octeon_hw_stop();
|
||||
|
||||
err1:
|
||||
usb_put_hcd(hcd);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int ohci_octeon_drv_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct usb_hcd *hcd = platform_get_drvdata(pdev);
|
||||
|
||||
usb_remove_hcd(hcd);
|
||||
|
||||
ohci_octeon_hw_stop();
|
||||
usb_put_hcd(hcd);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver ohci_octeon_driver = {
|
||||
.probe = ohci_octeon_drv_probe,
|
||||
.remove = ohci_octeon_drv_remove,
|
||||
.shutdown = usb_hcd_platform_shutdown,
|
||||
.driver = {
|
||||
.name = OCTEON_OHCI_HCD_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
}
|
||||
};
|
||||
|
||||
MODULE_ALIAS("platform:" OCTEON_OHCI_HCD_NAME);
|
Loading…
Reference in New Issue
Block a user