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drm/amd/display: Disable DTB Ref Clock Switching in dcn32

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[How & Why]
To be enabled once PMFW supports it.

Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dillon Varone 2022-04-13 17:54:19 -04:00 committed by Alex Deucher
parent 2cfe34e189
commit 2267a195e2
1 changed files with 4 additions and 0 deletions
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4
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
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@ -607,6 +607,10 @@ void dcn32_clk_mgr_construct(
if (clk_mgr->base.dentist_vco_freq_khz == 0)
clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */
if (clk_mgr->dccg->ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) {
clk_mgr->dccg->ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk;
}
if (clk_mgr->base.boot_snapshot.dprefclk != 0) {
//ASSERT(clk_mgr->base.dprefclk_khz == clk_mgr->base.boot_snapshot.dprefclk);
//clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk;