diff --git a/Documentation/ABI/testing/debugfs-driver-habanalabs b/Documentation/ABI/testing/debugfs-driver-habanalabs index 0f8d20fe343f..c915bf17b293 100644 --- a/Documentation/ABI/testing/debugfs-driver-habanalabs +++ b/Documentation/ABI/testing/debugfs-driver-habanalabs @@ -101,6 +101,15 @@ Description: Specify the size of the DMA transaction when using DMA to read When the write is finished, the user can read the "data_dma" blob +What: /sys/kernel/debug/habanalabs/hl/dump_razwi_events +Date: Aug 2022 +KernelVersion: 5.20 +Contact: fkassabri@habana.ai +Description: Dumps all razwi events to dmesg if exist. + After reading the status register of an existing event + the routine will clear the status register. + Usage: cat dump_razwi_events + What: /sys/kernel/debug/habanalabs/hl/dump_security_violations Date: Jan 2021 KernelVersion: 5.12 @@ -121,14 +130,16 @@ Date: Jan 2019 KernelVersion: 5.1 Contact: ogabbay@kernel.org Description: Sets I2C device address for I2C transaction that is generated - by the device's CPU + by the device's CPU, Not available when device is loaded with secured + firmware What: /sys/kernel/debug/habanalabs/hl/i2c_bus Date: Jan 2019 KernelVersion: 5.1 Contact: ogabbay@kernel.org Description: Sets I2C bus address for I2C transaction that is generated by - the device's CPU + the device's CPU, Not available when device is loaded with secured + firmware What: /sys/kernel/debug/habanalabs/hl/i2c_data Date: Jan 2019 @@ -136,39 +147,45 @@ KernelVersion: 5.1 Contact: ogabbay@kernel.org Description: Triggers an I2C transaction that is generated by the device's CPU. Writing to this file generates a write transaction while - reading from the file generates a read transaction + reading from the file generates a read transaction, Not available + when device is loaded with secured firmware What: /sys/kernel/debug/habanalabs/hl/i2c_len Date: Dec 2021 KernelVersion: 5.17 Contact: obitton@habana.ai Description: Sets I2C length in bytes for I2C transaction that is generated by - the device's CPU + the device's CPU, Not available when device is loaded with secured + firmware What: /sys/kernel/debug/habanalabs/hl/i2c_reg Date: Jan 2019 KernelVersion: 5.1 Contact: ogabbay@kernel.org Description: Sets I2C register id for I2C transaction that is generated by - the device's CPU + the device's CPU, Not available when device is loaded with secured + firmware What: /sys/kernel/debug/habanalabs/hl/led0 Date: Jan 2019 KernelVersion: 5.1 Contact: ogabbay@kernel.org -Description: Sets the state of the first S/W led on the device +Description: Sets the state of the first S/W led on the device, Not available + when device is loaded with secured firmware What: /sys/kernel/debug/habanalabs/hl/led1 Date: Jan 2019 KernelVersion: 5.1 Contact: ogabbay@kernel.org -Description: Sets the state of the second S/W led on the device +Description: Sets the state of the second S/W led on the device, Not available + when device is loaded with secured firmware What: /sys/kernel/debug/habanalabs/hl/led2 Date: Jan 2019 KernelVersion: 5.1 Contact: ogabbay@kernel.org -Description: Sets the state of the third S/W led on the device +Description: Sets the state of the third S/W led on the device, Not available + when device is loaded with secured firmware What: /sys/kernel/debug/habanalabs/hl/memory_scrub Date: May 2022 @@ -182,7 +199,8 @@ Date: May 2022 KernelVersion: 5.19 Contact: dhirschfeld@habana.ai Description: The value to which the dram will be set to when the user - scrubs the dram using 'memory_scrub' debugfs file + scrubs the dram using 'memory_scrub' debugfs file and + the scrubbing value when using module param 'memory_scrub' What: /sys/kernel/debug/habanalabs/hl/mmu Date: Jan 2019 @@ -277,7 +295,7 @@ Description: Displays a list with information about the currently user to DMA addresses What: /sys/kernel/debug/habanalabs/hl/userptr_lookup -Date: Aug 2021 +Date: Oct 2021 KernelVersion: 5.15 Contact: ogabbay@kernel.org Description: Allows to search for specific user pointers (user virtual diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/testing/sysfs-bus-iio index d4ccc68fdcf0..e81ba6f5e1c8 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -79,6 +79,11 @@ Description: * "accel-base" * "accel-display" + For devices where an accelerometer is housed in the swivel camera subassembly + (for AR application), the following standardized label is used: + + * "accel-camera" + What: /sys/bus/iio/devices/iio:deviceX/current_timestamp_clock KernelVersion: 4.5 Contact: linux-iio@vger.kernel.org @@ -102,6 +107,9 @@ Description: relevant directories. If it affects all of the above then it is to be found in the base device directory. + The stm32-timer-trigger has the additional characteristic that + a sampling_frequency of 0 is defined to stop sampling. + What: /sys/bus/iio/devices/iio:deviceX/sampling_frequency_available What: /sys/bus/iio/devices/iio:deviceX/in_intensity_sampling_frequency_available What: /sys/bus/iio/devices/iio:deviceX/in_proximity_sampling_frequency_available diff --git a/Documentation/ABI/testing/sysfs-bus-iio-sx9324 b/Documentation/ABI/testing/sysfs-bus-iio-sx9324 index 632e3321f5a3..a8342770e7cb 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio-sx9324 +++ b/Documentation/ABI/testing/sysfs-bus-iio-sx9324 @@ -5,6 +5,7 @@ Contact: Gwendal Grignou Description: SX9324 has 3 inputs, CS0, CS1 and CS2. Hardware layout defines if the input is + + not connected (HZ), + grounded (GD), + connected to an antenna where it can act as a base diff --git a/Documentation/ABI/testing/sysfs-bus-iio-temperature-max31856 b/Documentation/ABI/testing/sysfs-bus-iio-temperature-max31856 deleted file mode 100644 index e5ef6d8e5da1..000000000000 --- a/Documentation/ABI/testing/sysfs-bus-iio-temperature-max31856 +++ /dev/null @@ -1,31 +0,0 @@ -What: /sys/bus/iio/devices/iio:deviceX/fault_oc -KernelVersion: 5.1 -Contact: linux-iio@vger.kernel.org -Description: - Open-circuit fault. The detection of open-circuit faults, - such as those caused by broken thermocouple wires. - Reading returns either '1' or '0'. - - === ======================================================= - '1' An open circuit such as broken thermocouple wires - has been detected. - '0' No open circuit or broken thermocouple wires are detected - === ======================================================= - -What: /sys/bus/iio/devices/iio:deviceX/fault_ovuv -KernelVersion: 5.1 -Contact: linux-iio@vger.kernel.org -Description: - Overvoltage or Undervoltage Input Fault. The internal circuitry - is protected from excessive voltages applied to the thermocouple - cables by integrated MOSFETs at the T+ and T- inputs, and the - BIAS output. These MOSFETs turn off when the input voltage is - negative or greater than VDD. - - Reading returns either '1' or '0'. - - === ======================================================= - '1' The input voltage is negative or greater than VDD. - '0' The input voltage is positive and less than VDD (normal - state). - === ======================================================= diff --git a/Documentation/ABI/testing/sysfs-bus-iio-temperature-max31865 b/Documentation/ABI/testing/sysfs-bus-iio-temperature-max31865 deleted file mode 100644 index 4b072da92218..000000000000 --- a/Documentation/ABI/testing/sysfs-bus-iio-temperature-max31865 +++ /dev/null @@ -1,20 +0,0 @@ -What: /sys/bus/iio/devices/iio:deviceX/fault_ovuv -KernelVersion: 5.11 -Contact: linux-iio@vger.kernel.org -Description: - Overvoltage or Undervoltage Input fault. The internal circuitry - is protected from excessive voltages applied to the thermocouple - cables at FORCE+, FORCE2, RTDIN+ & RTDIN-. This circuitry turn - off when the input voltage is negative or greater than VDD. - - Reading returns '1' if input voltage is negative or greater - than VDD, otherwise '0'. - -What: /sys/bus/iio/devices/iio:deviceX/in_filter_notch_center_frequency -KernelVersion: 5.11 -Contact: linux-iio@vger.kernel.org -Description: - Notch frequency in Hz for a noise rejection filter. Used i.e for - line noise rejection. - - Valid notch filter values are 50 Hz and 60 Hz. diff --git a/Documentation/ABI/testing/sysfs-bus-iio-thermocouple b/Documentation/ABI/testing/sysfs-bus-iio-thermocouple new file mode 100644 index 000000000000..01259df297ca --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-iio-thermocouple @@ -0,0 +1,18 @@ +What: /sys/bus/iio/devices/iio:deviceX/fault_ovuv +KernelVersion: 5.1 +Contact: linux-iio@vger.kernel.org +Description: + Overvoltage or Undervoltage Input Fault. The internal circuitry + is protected from excessive voltages applied to the thermocouple + cables. The device can also detect if such a condition occurs. + + Reading returns '1' if input voltage is negative or greater + than VDD, otherwise '0'. + +What: /sys/bus/iio/devices/iio:deviceX/fault_oc +KernelVersion: 5.1 +Contact: linux-iio@vger.kernel.org +Description: + Open-circuit fault. The detection of open-circuit faults, + such as those caused by broken thermocouple wires. + Reading returns '1' if fault, '0' otherwise. diff --git a/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 b/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 index c4a4497c249a..05074c4a65e2 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 +++ b/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 @@ -90,14 +90,6 @@ Description: Reading returns the current master modes. Writing set the master mode -What: /sys/bus/iio/devices/triggerX/sampling_frequency -KernelVersion: 4.11 -Contact: benjamin.gaignard@st.com -Description: - Reading returns the current sampling frequency. - Writing an value different of 0 set and start sampling. - Writing 0 stop sampling. - What: /sys/bus/iio/devices/iio:deviceX/in_count0_preset KernelVersion: 4.12 Contact: benjamin.gaignard@st.com diff --git a/Documentation/ABI/testing/sysfs-class-vduse b/Documentation/ABI/testing/sysfs-class-vduse new file mode 100644 index 000000000000..2f2bc5c8fc48 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-class-vduse @@ -0,0 +1,33 @@ +What: /sys/class/vduse/ +Date: Oct 2021 +KernelVersion: 5.15 +Contact: Yongji Xie +Description: + The vduse/ class sub-directory belongs to the VDUSE + framework and provides a sysfs interface for configuring + VDUSE devices. + +What: /sys/class/vduse/control/ +Date: Oct 2021 +KernelVersion: 5.15 +Contact: Yongji Xie +Description: + This directory entry is created for the control device + of VDUSE framework. + +What: /sys/class/vduse// +Date: Oct 2021 +KernelVersion: 5.15 +Contact: Yongji Xie +Description: + This directory entry is created when a VDUSE device is + created via the control device. + +What: /sys/class/vduse//msg_timeout +Date: Oct 2021 +KernelVersion: 5.15 +Contact: Yongji Xie +Description: + (RW) The timeout (in seconds) for waiting for the control + message's response from userspace. Default value is 30s. + Writing a '0' to the file means to disable the timeout. diff --git a/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update b/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update new file mode 100644 index 000000000000..0a41afe0ab4c --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update @@ -0,0 +1,61 @@ +What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/sr_root_entry_hash +Date: Sep 2022 +KernelVersion: 5.20 +Contact: Russ Weight +Description: Read only. Returns the root entry hash for the static + region if one is programmed, else it returns the + string: "hash not programmed". This file is only + visible if the underlying device supports it. + Format: string. + +What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/pr_root_entry_hash +Date: Sep 2022 +KernelVersion: 5.20 +Contact: Russ Weight +Description: Read only. Returns the root entry hash for the partial + reconfiguration region if one is programmed, else it + returns the string: "hash not programmed". This file + is only visible if the underlying device supports it. + Format: string. + +What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/bmc_root_entry_hash +Date: Sep 2022 +KernelVersion: 5.20 +Contact: Russ Weight +Description: Read only. Returns the root entry hash for the BMC image + if one is programmed, else it returns the string: + "hash not programmed". This file is only visible if the + underlying device supports it. + Format: string. + +What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/sr_canceled_csks +Date: Sep 2022 +KernelVersion: 5.20 +Contact: Russ Weight +Description: Read only. Returns a list of indices for canceled code + signing keys for the static region. The standard bitmap + list format is used (e.g. "1,2-6,9"). + +What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/pr_canceled_csks +Date: Sep 2022 +KernelVersion: 5.20 +Contact: Russ Weight +Description: Read only. Returns a list of indices for canceled code + signing keys for the partial reconfiguration region. The + standard bitmap list format is used (e.g. "1,2-6,9"). + +What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/bmc_canceled_csks +Date: Sep 2022 +KernelVersion: 5.20 +Contact: Russ Weight +Description: Read only. Returns a list of indices for canceled code + signing keys for the BMC. The standard bitmap list format + is used (e.g. "1,2-6,9"). + +What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/flash_count +Date: Sep 2022 +KernelVersion: 5.20 +Contact: Russ Weight +Description: Read only. Returns number of times the secure update + staging area has been flashed. + Format: "%u". diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml new file mode 100644 index 000000000000..d783d9276124 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm Coresight Address Translation Unit (CATU) + +maintainers: + - Mathieu Poirier + - Mike Leach + - Leo Yan + - Suzuki K Poulose + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The CoreSight Address Translation Unit (CATU) translates addresses between an + AXI master and system memory. The CATU is normally used along with the TMC to + implement scattering of virtual trace buffers in physical memory. The CATU + translates contiguous Virtual Addresses (VAs) from an AXI master into + non-contiguous Physical Addresses (PAs) that are intended for system memory. + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + const: arm,coresight-catu + required: + - compatible + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - const: arm,coresight-catu + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: apb_pclk + - const: atclk + + interrupts: + maxItems: 1 + description: Address translation error interrupt + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: AXI Slave connected to another Coresight component + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + +unevaluatedProperties: false + +examples: + - | + #include + catu@207e0000 { + compatible = "arm,coresight-catu", "arm,primecell"; + reg = <0x207e0000 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + + interrupts = ; + in-ports { + port { + catu_in_port: endpoint { + remote-endpoint = <&etr_out_port>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml new file mode 100644 index 000000000000..0a6bc03ebe00 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CoreSight CPU Debug Component + +maintainers: + - Mathieu Poirier + - Mike Leach + - Leo Yan + - Suzuki K Poulose + +description: | + CoreSight CPU debug component are compliant with the ARMv8 architecture + reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The + external debug module is mainly used for two modes: self-hosted debug and + external debug, and it can be accessed from mmio region from Coresight and + eventually the debug module connects with CPU for debugging. And the debug + module provides sample-based profiling extension, which can be used to sample + CPU program counter, secure state and exception level, etc; usually every CPU + has one dedicated debug module to be connected. + +select: + properties: + compatible: + contains: + const: arm,coresight-cpu-debug + required: + - compatible + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - const: arm,coresight-cpu-debug + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + cpu: + description: + A phandle to the cpu this debug component is bound to. + $ref: /schemas/types.yaml#/definitions/phandle + + power-domains: + maxItems: 1 + description: + A phandle to the debug power domain if the debug logic has its own + dedicated power domain. CPU idle states may also need to be separately + constrained to keep CPU cores powered. + +required: + - compatible + - reg + - clocks + - clock-names + - cpu + +unevaluatedProperties: false + +examples: + - | + debug@f6590000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0xf6590000 0x1000>; + clocks = <&sys_ctrl 1>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + }; +... diff --git a/Documentation/devicetree/bindings/arm/coresight-cti.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml similarity index 98% rename from Documentation/devicetree/bindings/arm/coresight-cti.yaml rename to Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml index 21e3515491f4..72ffe4d1e948 100644 --- a/Documentation/devicetree/bindings/arm/coresight-cti.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml @@ -2,7 +2,7 @@ # Copyright 2019 Linaro Ltd. %YAML 1.2 --- -$id: http://devicetree.org/schemas/arm/coresight-cti.yaml# +$id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: ARM Coresight Cross Trigger Interface (CTI) device. @@ -12,8 +12,7 @@ description: | to one or more CoreSight components and/or a CPU, with CTIs interconnected in a star topology via the Cross Trigger Matrix (CTM), which is not programmable. The ECT components are not part of the trace generation data path and are thus - not part of the CoreSight graph described in the general CoreSight bindings - file coresight.txt. + not part of the CoreSight graph. The CTI component properties define the connections between the individual CTI and the components it is directly connected to, consisting of input and diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml new file mode 100644 index 000000000000..1eeedc22857c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-dynamic-funnel.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreSight Programmable Trace Bus Funnel + +maintainers: + - Mathieu Poirier + - Mike Leach + - Leo Yan + - Suzuki K Poulose + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The Coresight funnel merges 2-8 trace sources into a single trace + stream with programmable enable and priority of input ports. + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + const: arm,coresight-dynamic-funnel + required: + - compatible + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - const: arm,coresight-dynamic-funnel + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: apb_pclk + - const: atclk + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port(@[0-7])?$': + description: Input connections from CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Output connection to CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + - out-ports + +unevaluatedProperties: false + +examples: + - | + funnel@20040000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x20040000 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + out-ports { + port { + funnel_out_port0: endpoint { + remote-endpoint = <&replicator_in_port0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in_port0: endpoint { + remote-endpoint = <&ptm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + funnel_in_port1: endpoint { + remote-endpoint = <&ptm1_out_port>; + }; + }; + + port@2 { + reg = <2>; + funnel_in_port2: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml new file mode 100644 index 000000000000..a26ed9214e00 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-dynamic-replicator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm Coresight Programmable Trace Bus Replicator + +maintainers: + - Mathieu Poirier + - Mike Leach + - Leo Yan + - Suzuki K Poulose + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The Coresight replicator splits a single trace stream into two trace streams + for systems that have more than one trace sink component. + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + const: arm,coresight-dynamic-replicator + required: + - compatible + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - const: arm,coresight-dynamic-replicator + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: apb_pclk + - const: atclk + + qcom,replicator-loses-context: + type: boolean + description: + Indicates that the replicator will lose register context when AMBA clock + is removed which is observed in some replicator designs. + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Input connection from CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port(@[01])?$': + description: Output connections to CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + - out-ports + +unevaluatedProperties: false + +examples: + - | + replicator@20120000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x20120000 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + }; + in-ports { + port { + replicator_in_port0: endpoint { + remote-endpoint = <&csys2_funnel_out_port>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml new file mode 100644 index 000000000000..fd06ede26ceb --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-etb10.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreSight Embedded Trace Buffer + +maintainers: + - Mathieu Poirier + - Mike Leach + - Leo Yan + - Suzuki K Poulose + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The CoreSight Embedded Trace Buffer stores traces in a dedicated SRAM that is + used as a circular buffer. + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + const: arm,coresight-etb10 + required: + - compatible + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - const: arm,coresight-etb10 + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: apb_pclk + - const: atclk + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Input connection from CoreSight Trace bus. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + +unevaluatedProperties: false + +examples: + - | + etb@20010000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0x20010000 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + in-ports { + port { + etb_in_port: endpoint { + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml new file mode 100644 index 000000000000..e0377ce48537 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml @@ -0,0 +1,156 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-etm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreSight Embedded Trace MacroCell + +maintainers: + - Mathieu Poirier + - Mike Leach + - Leo Yan + - Suzuki K Poulose + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The Embedded Trace Macrocell (ETM) is a real-time trace module providing + instruction and data tracing of a processor. + +select: + properties: + compatible: + contains: + enum: + - arm,coresight-etm3x + - arm,coresight-etm4x + - arm,coresight-etm4x-sysreg + required: + - compatible + +allOf: + - if: + not: + properties: + compatible: + contains: + const: arm,coresight-etm4x-sysreg + then: + $ref: /schemas/arm/primecell.yaml# + required: + - reg + +properties: + compatible: + oneOf: + - description: + Embedded Trace Macrocell with memory mapped access. + items: + - enum: + - arm,coresight-etm3x + - arm,coresight-etm4x + - const: arm,primecell + - description: + Embedded Trace Macrocell (version 4.x), with system register access only + const: arm,coresight-etm4x-sysreg + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: apb_pclk + - const: atclk + + arm,coresight-loses-context-with-cpu: + type: boolean + description: + Indicates that the hardware will lose register context on CPU power down + (e.g. CPUIdle). An example of where this may be needed are systems which + contain a coresight component and CPU in the same power domain. When the + CPU powers down the coresight component also powers down and loses its + context. + + arm,cp14: + type: boolean + description: + Must be present if the system accesses ETM/PTM management registers via + co-processor 14. + + qcom,skip-power-up: + type: boolean + description: + Indicates that an implementation can skip powering up the trace unit. + TRCPDCR.PU does not have to be set on Qualcomm Technologies Inc. systems + since ETMs are in the same power domain as their CPU cores. This property + is required to identify such systems with hardware errata where the CPU + watchdog counter is stopped when TRCPDCR.PU is set. + + cpu: + description: + phandle to the cpu this ETM is bound to. + $ref: /schemas/types.yaml#/definitions/phandle + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Output connection from the ETM to CoreSight Trace bus. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - clocks + - clock-names + - cpu + - out-ports + +unevaluatedProperties: false + +examples: + - | + ptm@2201c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x2201c000 0x1000>; + + cpu = <&cpu0>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + out-ports { + port { + ptm0_out_port: endpoint { + remote-endpoint = <&funnel_in_port0>; + }; + }; + }; + }; + + ptm@2201d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x2201d000 0x1000>; + + cpu = <&cpu1>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + out-ports { + port { + ptm1_out_port: endpoint { + remote-endpoint = <&funnel_in_port1>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml new file mode 100644 index 000000000000..374083956b20 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-static-funnel.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreSight Static Trace Bus Funnel + +maintainers: + - Mathieu Poirier + - Mike Leach + - Leo Yan + - Suzuki K Poulose + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The Coresight static funnel merges 2-8 trace sources into a single trace + stream. + +properties: + compatible: + const: arm,coresight-static-funnel + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port@[0-7]$': + description: Input connections from CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Output connection to CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - in-ports + - out-ports + +additionalProperties: false + +examples: + - | + funnel { + /* + * non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-funnel"; + + out-ports { + port { + combo_funnel_out: endpoint { + remote-endpoint = <&top_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + combo_funnel_in0: endpoint { + remote-endpoint = <&cluster0_etf_out>; + }; + }; + + port@1 { + reg = <1>; + combo_funnel_in1: endpoint { + remote-endpoint = <&cluster1_etf_out>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml new file mode 100644 index 000000000000..a34d8583830c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-static-replicator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreSight Static Trace Bus Replicator + +maintainers: + - Mathieu Poirier + - Mike Leach + - Leo Yan + - Suzuki K Poulose + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The Coresight replicator splits a single trace stream into two trace streams + for systems that have more than one trace sink component. + +properties: + compatible: + const: arm,coresight-static-replicator + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Input connection from CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port@[01]$': + description: Output connections to CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - in-ports + - out-ports + +additionalProperties: false + +examples: + - | + replicator { + /* + * non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-replicator"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&etb_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + }; + + in-ports { + port { + replicator_in_port0: endpoint { + remote-endpoint = <&funnel_out_port0>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml new file mode 100644 index 000000000000..905008faa012 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreSight System Trace MacroCell + +maintainers: + - Mathieu Poirier + - Mike Leach + - Leo Yan + - Suzuki K Poulose + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The STM is a trace source that is integrated into a CoreSight system, designed + primarily for high-bandwidth trace of instrumentation embedded into software. + This instrumentation is made up of memory-mapped writes to the STM Advanced + eXtensible Interface (AXI) slave, which carry information about the behavior + of the software. + +select: + properties: + compatible: + contains: + const: arm,coresight-stm + required: + - compatible + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - const: arm,coresight-stm + - const: arm,primecell + + reg: + maxItems: 2 + + reg-names: + items: + - const: stm-base + - const: stm-stimulus-base + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: apb_pclk + - const: atclk + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Output connection to the CoreSight Trace bus. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - out-ports + +unevaluatedProperties: false + +examples: + - | + stm@20100000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x20100000 0x1000>, + <0x28000000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + out-ports { + port { + stm_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port2>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml new file mode 100644 index 000000000000..3463b6e53aef --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreSight Trace Memory Controller + +maintainers: + - Mathieu Poirier + - Mike Leach + - Leo Yan + - Suzuki K Poulose + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + Trace Memory Controller is used for Embedded Trace Buffer(ETB), Embedded Trace + FIFO(ETF) and Embedded Trace Router(ETR) configurations. The configuration + mode (ETB, ETF, ETR) is discovered at boot time when the device is probed. + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + const: arm,coresight-tmc + required: + - compatible + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - const: arm,coresight-tmc + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: apb_pclk + - const: atclk + + arm,buffer-size: + $ref: /schemas/types.yaml#/definitions/uint32 + deprecated: true + description: + Size of contiguous buffer space for TMC ETR (embedded trace router). The + buffer size can be configured dynamically via buffer_size property in + sysfs instead. + + arm,scatter-gather: + type: boolean + description: + Indicates that the TMC-ETR can safely use the SG mode on this system. + + arm,max-burst-size: + description: + The maximum burst size initiated by TMC on the AXI master interface. The + burst size can be in the range [0..15], the setting supports one data + transfer per burst up to a maximum of 16 data transfers per burst. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Input connection from the CoreSight Trace bus. + $ref: /schemas/graph.yaml#/properties/port + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: AXI or ATB Master output connection. Used for ETR + and ETF configurations. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + +unevaluatedProperties: false + +examples: + - | + etr@20070000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x20070000 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + in-ports { + port { + etr_in_port: endpoint { + remote-endpoint = <&replicator2_out_port0>; + }; + }; + }; + + out-ports { + port { + etr_out_port: endpoint { + remote-endpoint = <&catu_in_port>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml new file mode 100644 index 000000000000..e80d48200c37 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-tpiu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CoreSight Trace Port Interface Unit + +maintainers: + - Mathieu Poirier + - Mike Leach + - Leo Yan + - Suzuki K Poulose + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a particular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flows + through the intermediate links connecting the source to the currently selected + sink. + + The CoreSight Trace Port Interface Unit captures trace data from the trace bus + and outputs it to an external trace port. + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + const: arm,coresight-tpiu + required: + - compatible + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - const: arm,coresight-tpiu + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: apb_pclk + - const: atclk + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: Input connection from the CoreSight Trace bus. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + +unevaluatedProperties: false + +examples: + - | + tpiu@e3c05000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0xe3c05000 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&funnel4_out_port0>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/ete.yaml b/Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml similarity index 95% rename from Documentation/devicetree/bindings/arm/ete.yaml rename to Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml index 7f9b2d1e1147..5f07fb166c56 100644 --- a/Documentation/devicetree/bindings/arm/ete.yaml +++ b/Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml @@ -2,7 +2,7 @@ # Copyright 2021, Arm Ltd %YAML 1.2 --- -$id: "http://devicetree.org/schemas/arm/ete.yaml#" +$id: "http://devicetree.org/schemas/arm/arm,embedded-trace-extension.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: ARM Embedded Trace Extensions @@ -20,7 +20,6 @@ description: | Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to legacy CoreSight components, a node must be listed per instance, along with any optional connection graph as per the coresight bindings. - See bindings/arm/coresight.txt. properties: $nodename: diff --git a/Documentation/devicetree/bindings/arm/trbe.yaml b/Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml similarity index 94% rename from Documentation/devicetree/bindings/arm/trbe.yaml rename to Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml index 4402d7bfd1fc..b1322658063a 100644 --- a/Documentation/devicetree/bindings/arm/trbe.yaml +++ b/Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml @@ -2,7 +2,7 @@ # Copyright 2021, Arm Ltd %YAML 1.2 --- -$id: "http://devicetree.org/schemas/arm/trbe.yaml#" +$id: "http://devicetree.org/schemas/arm/arm,trace-buffer-extension.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: ARM Trace Buffer Extensions diff --git a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt deleted file mode 100644 index f1de3247c1b7..000000000000 --- a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt +++ /dev/null @@ -1,49 +0,0 @@ -* CoreSight CPU Debug Component: - -CoreSight CPU debug component are compliant with the ARMv8 architecture -reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The -external debug module is mainly used for two modes: self-hosted debug and -external debug, and it can be accessed from mmio region from Coresight -and eventually the debug module connects with CPU for debugging. And the -debug module provides sample-based profiling extension, which can be used -to sample CPU program counter, secure state and exception level, etc; -usually every CPU has one dedicated debug module to be connected. - -Required properties: - -- compatible : should be "arm,coresight-cpu-debug"; supplemented with - "arm,primecell" since this driver is using the AMBA bus - interface. - -- reg : physical base address and length of the register set. - -- clocks : the clock associated to this component. - -- clock-names : the name of the clock referenced by the code. Since we are - using the AMBA framework, the name of the clock providing - the interconnect should be "apb_pclk" and the clock is - mandatory. The interface between the debug logic and the - processor core is clocked by the internal CPU clock, so it - is enabled with CPU clock by default. - -- cpu : the CPU phandle the debug module is affined to. Do not assume it - to default to CPU0 if omitted. - -Optional properties: - -- power-domains: a phandle to the debug power domain. We use "power-domains" - binding to turn on the debug logic if it has own dedicated - power domain and if necessary to use "cpuidle.off=1" or - "nohlt" in the kernel command line or sysfs node to - constrain idle states to ensure registers in the CPU power - domain are accessible. - -Example: - - debug@f6590000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; - reg = <0 0xf6590000 0 0x1000>; - clocks = <&sys_ctrl HI6220_DAPB_CLK>; - clock-names = "apb_pclk"; - cpu = <&cpu0>; - }; diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt deleted file mode 100644 index c68d93a35b6c..000000000000 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ /dev/null @@ -1,402 +0,0 @@ -* CoreSight Components: - -CoreSight components are compliant with the ARM CoreSight architecture -specification and can be connected in various topologies to suit a particular -SoCs tracing needs. These trace components can generally be classified as -sinks, links and sources. Trace data produced by one or more sources flows -through the intermediate links connecting the source to the currently selected -sink. Each CoreSight component device should use these properties to describe -its hardware characteristcs. - -* Required properties for all components *except* non-configurable replicators - and non-configurable funnels: - - * compatible: These have to be supplemented with "arm,primecell" as - drivers are using the AMBA bus interface. Possible values include: - - Embedded Trace Buffer (version 1.0): - "arm,coresight-etb10", "arm,primecell"; - - - Trace Port Interface Unit: - "arm,coresight-tpiu", "arm,primecell"; - - - Trace Memory Controller, used for Embedded Trace Buffer(ETB), - Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) - configuration. The configuration mode (ETB, ETF, ETR) is - discovered at boot time when the device is probed. - "arm,coresight-tmc", "arm,primecell"; - - - Trace Programmable Funnel: - "arm,coresight-dynamic-funnel", "arm,primecell"; - "arm,coresight-funnel", "arm,primecell"; (OBSOLETE. For - backward compatibility and will be removed) - - - Embedded Trace Macrocell (version 3.x) and - Program Flow Trace Macrocell: - "arm,coresight-etm3x", "arm,primecell"; - - - Embedded Trace Macrocell (version 4.x), with memory mapped access. - "arm,coresight-etm4x", "arm,primecell"; - - - Embedded Trace Macrocell (version 4.x), with system register access only. - "arm,coresight-etm4x-sysreg"; - - - Coresight programmable Replicator : - "arm,coresight-dynamic-replicator", "arm,primecell"; - - - System Trace Macrocell: - "arm,coresight-stm", "arm,primecell"; [1] - - Coresight Address Translation Unit (CATU) - "arm,coresight-catu", "arm,primecell"; - - - Coresight Cross Trigger Interface (CTI): - "arm,coresight-cti", "arm,primecell"; - See coresight-cti.yaml for full CTI definitions. - - * reg: physical base address and length of the register - set(s) of the component. - - * clocks: the clocks associated to this component. - - * clock-names: the name of the clocks referenced by the code. - Since we are using the AMBA framework, the name of the clock - providing the interconnect should be "apb_pclk", and some - coresight blocks also have an additional clock "atclk", which - clocks the core of that coresight component. The latter clock - is optional. - - * port or ports: see "Graph bindings for Coresight" below. - -* Additional required property for Embedded Trace Macrocell (version 3.x and - version 4.x): - * cpu: the cpu phandle this ETM/PTM is affined to. Do not - assume it to default to CPU0 if omitted. - -* Additional required properties for System Trace Macrocells (STM): - * reg: along with the physical base address and length of the register - set as described above, another entry is required to describe the - mapping of the extended stimulus port area. - - * reg-names: the only acceptable values are "stm-base" and - "stm-stimulus-base", each corresponding to the areas defined in "reg". - -* Required properties for Coresight Cross Trigger Interface (CTI) - See coresight-cti.yaml for full CTI definitions. - -* Required properties for devices that don't show up on the AMBA bus, such as - non-configurable replicators and non-configurable funnels: - - * compatible: Currently supported value is (note the absence of the - AMBA markee): - - Coresight Non-configurable Replicator: - "arm,coresight-static-replicator"; - "arm,coresight-replicator"; (OBSOLETE. For backward - compatibility and will be removed) - - - Coresight Non-configurable Funnel: - "arm,coresight-static-funnel"; - - * port or ports: see "Graph bindings for Coresight" below. - -* Optional properties for all components: - - * arm,coresight-loses-context-with-cpu : boolean. Indicates that the - hardware will lose register context on CPU power down (e.g. CPUIdle). - An example of where this may be needed are systems which contain a - coresight component and CPU in the same power domain. When the CPU - powers down the coresight component also powers down and loses its - context. This property is currently only used for the ETM 4.x driver. - -* Optional properties for ETM/PTMs: - - * arm,cp14: must be present if the system accesses ETM/PTM management - registers via co-processor 14. - - * qcom,skip-power-up: boolean. Indicates that an implementation can - skip powering up the trace unit. TRCPDCR.PU does not have to be set - on Qualcomm Technologies Inc. systems since ETMs are in the same power - domain as their CPU cores. This property is required to identify such - systems with hardware errata where the CPU watchdog counter is stopped - when TRCPDCR.PU is set. - -* Optional property for TMC: - - * arm,buffer-size: size of contiguous buffer space for TMC ETR - (embedded trace router). This property is obsolete. The buffer size - can be configured dynamically via buffer_size property in sysfs. - - * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely - use the SG mode on this system. - - * arm,max-burst-size: The maximum burst size initiated by TMC on the - AXI master interface. The burst size can be in the range [0..15], - the setting supports one data transfer per burst up to a maximum of - 16 data transfers per burst. - -* Optional property for CATU : - * interrupts : Exactly one SPI may be listed for reporting the address - error - -* Optional property for configurable replicators: - - * qcom,replicator-loses-context: boolean. Indicates that the replicator - will lose register context when AMBA clock is removed which is observed - in some replicator designs. - -Graph bindings for Coresight -------------------------------- - -Coresight components are interconnected to create a data path for the flow of -trace data generated from the "sources" to their collection points "sink". -Each coresight component must describe the "input" and "output" connections. -The connections must be described via generic DT graph bindings as described -by the "bindings/graph.txt", where each "port" along with an "endpoint" -component represents a hardware port and the connection. - - * All output ports must be listed inside a child node named "out-ports" - * All input ports must be listed inside a child node named "in-ports". - * Port address must match the hardware port number. - -Example: - -1. Sinks - etb@20010000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0 0x20010000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - in-ports { - port { - etb_in_port: endpoint@0 { - remote-endpoint = <&replicator_out_port0>; - }; - }; - }; - }; - - tpiu@20030000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0 0x20030000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - in-ports { - port { - tpiu_in_port: endpoint@0 { - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - }; - - etr@20070000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x20070000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - in-ports { - port { - etr_in_port: endpoint { - remote-endpoint = <&replicator2_out_port0>; - }; - }; - }; - - out-ports { - port { - etr_out_port: endpoint { - remote-endpoint = <&catu_in_port>; - }; - }; - }; - }; - -2. Links - replicator { - /* non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-static-replicator"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&etb_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - }; - - in-ports { - port { - replicator_in_port0: endpoint { - remote-endpoint = <&funnel_out_port0>; - }; - }; - }; - }; - - funnel { - /* - * non-configurable funnel don't show up on the AMBA - * bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-static-funnel"; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - - out-ports { - port { - combo_funnel_out: endpoint { - remote-endpoint = <&top_funnel_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - combo_funnel_in0: endpoint { - remote-endpoint = <&cluster0_etf_out>; - }; - }; - - port@1 { - reg = <1>; - combo_funnel_in1: endpoint { - remote-endpoint = <&cluster1_etf_out>; - }; - }; - }; - }; - - funnel@20040000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x20040000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - funnel_out_port0: endpoint { - remote-endpoint = - <&replicator_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_in_port0: endpoint { - remote-endpoint = <&ptm0_out_port>; - }; - }; - - port@1 { - reg = <1>; - funnel_in_port1: endpoint { - remote-endpoint = <&ptm1_out_port>; - }; - }; - - port@2 { - reg = <2>; - funnel_in_port2: endpoint { - remote-endpoint = <&etm0_out_port>; - }; - }; - - }; - }; - -3. Sources - ptm@2201c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2201c000 0 0x1000>; - - cpu = <&cpu0>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - ptm0_out_port: endpoint { - remote-endpoint = <&funnel_in_port0>; - }; - }; - }; - }; - - ptm@2201d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2201d000 0 0x1000>; - - cpu = <&cpu1>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - ptm1_out_port: endpoint { - remote-endpoint = <&funnel_in_port1>; - }; - }; - }; - }; - -4. STM - stm@20100000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0 0x20100000 0 0x1000>, - <0 0x28000000 0 0x180000>; - reg-names = "stm-base", "stm-stimulus-base"; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - out-ports { - port { - stm_out_port: endpoint { - remote-endpoint = <&main_funnel_in_port2>; - }; - }; - }; - }; - -5. CATU - - catu@207e0000 { - compatible = "arm,coresight-catu", "arm,primecell"; - reg = <0 0x207e0000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - - interrupts = ; - in-ports { - port { - catu_in_port: endpoint { - remote-endpoint = <&etr_out_port>; - }; - }; - }; - }; - -[1]. There is currently two version of STM: STM32 and STM500. Both -have the same HW interface and as such don't need an explicit binding name. diff --git a/Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml new file mode 100644 index 000000000000..aee45cb15592 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/microchip,mpf-spi-fpga-mgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Polarfire FPGA manager. + +maintainers: + - Ivan Bornyakov + +description: + Device Tree Bindings for Microchip Polarfire FPGA Manager using slave SPI to + load the bitstream in .dat format. + +properties: + compatible: + enum: + - microchip,mpf-spi-fpga-mgr + + reg: + description: SPI chip select + maxItems: 1 + + spi-max-frequency: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + fpga_mgr@0 { + compatible = "microchip,mpf-spi-fpga-mgr"; + spi-max-frequency = <20000000>; + reg = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml index 4fcbfd93e218..8d829ef878bc 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ADIS16240 Programmable Impact Sensor and Recorder driver maintainers: - - Alexandru Ardelean + - Alexandru Tachici description: | ADIS16240 Programmable Impact Sensor and Recorder driver that supports diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml index 11d32a288535..9bb039e2f533 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml @@ -55,7 +55,7 @@ examples: /* Example for a I2C device node */ accelerometer@2a { compatible = "adi,adxl345"; - reg = <0x53>; + reg = <0x2a>; interrupt-parent = <&gpio0>; interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/Documentation/devicetree/bindings/iio/accel/bosch,bmi088.yaml b/Documentation/devicetree/bindings/iio/accel/bosch,bmi088.yaml index 911a1ae9c83f..272eb48eef5a 100644 --- a/Documentation/devicetree/bindings/iio/accel/bosch,bmi088.yaml +++ b/Documentation/devicetree/bindings/iio/accel/bosch,bmi088.yaml @@ -17,7 +17,9 @@ description: | properties: compatible: enum: + - bosch,bmi085-accel - bosch,bmi088-accel + - bosch,bmi090l-accel reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/iio/accel/murata,sca3300.yaml b/Documentation/devicetree/bindings/iio/accel/murata,sca3300.yaml index 55fd3548e3b6..f6e2a16a710b 100644 --- a/Documentation/devicetree/bindings/iio/accel/murata,sca3300.yaml +++ b/Documentation/devicetree/bindings/iio/accel/murata,sca3300.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - murata,sca3300 + - murata,scl3300 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad9467.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad9467.yaml index b5aed40d8a50..2d72ff6bcbc0 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad9467.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad9467.yaml @@ -8,7 +8,6 @@ title: Analog Devices AD9467 and similar High-Speed ADCs maintainers: - Michael Hennerich - - Alexandru Ardelean description: | The AD9467 and the parts similar with it, are high-speed analog-to-digital diff --git a/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml b/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml index 0924b2b4972b..8e25773d69be 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml @@ -8,7 +8,6 @@ title: Analog Devices AXI ADC IP core maintainers: - Michael Hennerich - - Alexandru Ardelean description: | Analog Devices Generic AXI ADC IP core for interfacing an ADC device diff --git a/Documentation/devicetree/bindings/iio/adc/fsl,vf610-adc.yaml b/Documentation/devicetree/bindings/iio/adc/fsl,vf610-adc.yaml index 925f355cc21f..c770ff4998f5 100644 --- a/Documentation/devicetree/bindings/iio/adc/fsl,vf610-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/fsl,vf610-adc.yaml @@ -14,7 +14,14 @@ description: properties: compatible: - const: fsl,vf610-adc + oneOf: + - items: + - enum: + - fsl,imx6sx-adc + - fsl,imx6ul-adc + - const: fsl,vf610-adc + - items: + - const: fsl,vf610-adc reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml index 65581ad4b816..7f79a06e76f5 100644 --- a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml @@ -35,6 +35,7 @@ properties: - enum: - mediatek,mt8183-auxadc - mediatek,mt8186-auxadc + - mediatek,mt8188-auxadc - mediatek,mt8195-auxadc - mediatek,mt8516-auxadc - const: mediatek,mt8173-auxadc diff --git a/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm750-adc.yaml b/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm750-adc.yaml index 001cf263b7d5..fede2aa64092 100644 --- a/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm750-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm750-adc.yaml @@ -10,11 +10,14 @@ maintainers: - Tomer Maimon description: - The NPCM ADC is a 10-bit converter for eight channel inputs. + The NPCM7XX ADC is a 10-bit converter and NPCM8XX ADC is a 12-bit converter, + both have eight channel inputs. properties: compatible: - const: nuvoton,npcm750-adc + enum: + - nuvoton,npcm750-adc + - nuvoton,npcm845-adc reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml new file mode 100644 index 000000000000..c8cbfd3444be --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-rradc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm's SPMI PMIC Round Robin ADC + +maintainers: + - Caleb Connolly + +description: | + The Qualcomm SPMI Round Robin ADC (RRADC) provides interface to clients to + read the voltage, current and temperature for supported peripherals such as + the battery thermistor die temperature, charger temperature, USB and DC input + voltage / current and battery ID resistor. + +properties: + compatible: + enum: + - qcom,pmi8998-rradc + - qcom,pm660-rradc + + reg: + maxItems: 1 + + qcom,batt-id-delay-ms: + description: Sets the hardware settling time for the battery ID resistor. + enum: [0, 1, 4, 12, 20, 40, 60, 80] + + "#io-channel-cells": + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pmic { + #address-cells = <1>; + #size-cells = <0>; + + pmic_rradc: adc@4500 { + compatible = "qcom,pmi8998-rradc"; + reg = <0x4500>; + #io-channel-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml index d66c24cae1e1..61c6157cf5a9 100644 --- a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml @@ -19,6 +19,7 @@ properties: compatible: items: - enum: + - renesas,r9a07g043-adc # RZ/G2UL - renesas,r9a07g044-adc # RZ/G2L - renesas,r9a07g054-adc # RZ/V2L - const: renesas,rzg2l-adc @@ -76,16 +77,35 @@ patternProperties: properties: reg: description: | - The channel number. It can have up to 8 channels numbered from 0 to 7. - items: - - minimum: 0 - maximum: 7 + The channel number. required: - reg additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + const: renesas,r9a07g043-adc + then: + patternProperties: + "^channel@[2-7]$": false + "^channel@[0-1]$": + properties: + reg: + minimum: 0 + maximum: 1 + else: + patternProperties: + "^channel@[0-7]$": + properties: + reg: + minimum: 0 + maximum: 7 + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml index fb2c48fc7ce4..24ac40180ac1 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Analog Devices AD5770R DAC device driver maintainers: - - Mircea Caprioru + - Alexandru Tachici description: | Bindings for the Analog Devices AD5770R current DAC device. Datasheet can be diff --git a/Documentation/devicetree/bindings/iio/dac/microchip,mcp4922.yaml b/Documentation/devicetree/bindings/iio/dac/microchip,mcp4922.yaml index 12a14b3f36cb..4c430abcdbf9 100644 --- a/Documentation/devicetree/bindings/iio/dac/microchip,mcp4922.yaml +++ b/Documentation/devicetree/bindings/iio/dac/microchip,mcp4922.yaml @@ -15,6 +15,7 @@ properties: enum: - microchip,mcp4902 - microchip,mcp4912 + - microchip,mcp4921 - microchip,mcp4922 reg: diff --git a/Documentation/devicetree/bindings/iio/dac/ti,dac5571.yaml b/Documentation/devicetree/bindings/iio/dac/ti,dac5571.yaml index 714191724f7c..88298bc43b81 100644 --- a/Documentation/devicetree/bindings/iio/dac/ti,dac5571.yaml +++ b/Documentation/devicetree/bindings/iio/dac/ti,dac5571.yaml @@ -21,6 +21,7 @@ properties: - ti,dac5573 - ti,dac6573 - ti,dac7573 + - ti,dac121c081 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/iio/imu/adi,adis16480.yaml b/Documentation/devicetree/bindings/iio/imu/adi,adis16480.yaml index 5dbe24be9925..dd29dc6c4c19 100644 --- a/Documentation/devicetree/bindings/iio/imu/adi,adis16480.yaml +++ b/Documentation/devicetree/bindings/iio/imu/adi,adis16480.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Analog Devices ADIS16480 and similar IMUs maintainers: - - Alexandru Ardelean + - Alexandru Tachici properties: compatible: diff --git a/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml b/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml index b8a6ee16854f..b3aa2ebf9661 100644 --- a/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml +++ b/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml @@ -126,6 +126,42 @@ properties: UINT_MAX (4294967295) represents infinite. Other values represent 1-1/N. + semtech,cs-idle-sleep: + description: + State of CS pins during sleep mode and idle time. + enum: + - hi-z + - gnd + - vdd + + semtech,int-comp-resistor: + description: + Internal resistor setting for compensation. + enum: + - lowest + - low + - high + - highest + + semtech,input-precharge-resistor-ohms: + default: 4000 + multipleOf: 2000 + minimum: 0 + maximum: 30000 + description: + Pre-charge input resistance in Ohm. + + semtech,input-analog-gain: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + description: | + Defines the input antenna analog gain + 0: x1.247 + 1: x1 (default) + 2: x0.768 + 3: x0.552 + required: - compatible - reg @@ -157,5 +193,8 @@ examples: semtech,ph01-proxraw-strength = <2>; semtech,ph23-proxraw-strength = <2>; semtech,avg-pos-strength = <64>; + semtech,int-comp-resistor = "lowest"; + semtech,input-precharge-resistor-ohms = <2000>; + semtech,cs-idle-sleep = "gnd"; }; }; diff --git a/Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml b/Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml index 63e1a1fd00d4..f088c5d2be99 100644 --- a/Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml +++ b/Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml @@ -61,6 +61,14 @@ properties: UINT_MAX (4294967295) represents infinite. Other values represent 1-1/N. + semtech,input-precharge-resistor-ohms: + default: 0 + multipleOf: 2000 + minimum: 0 + maximum: 30000 + description: + Pre-charge input resistance in Ohm. + required: - compatible - reg @@ -85,5 +93,6 @@ examples: semtech,resolution = <256>; semtech,proxraw-strength = <2>; semtech,avg-pos-strength = <64>; + semtech,input-precharge-resistor-ohms = <4000>; }; }; diff --git a/Documentation/devicetree/bindings/iio/proximity/st,vl53l0x.yaml b/Documentation/devicetree/bindings/iio/proximity/st,vl53l0x.yaml index 656460d9d8c8..322befc41de6 100644 --- a/Documentation/devicetree/bindings/iio/proximity/st,vl53l0x.yaml +++ b/Documentation/devicetree/bindings/iio/proximity/st,vl53l0x.yaml @@ -19,6 +19,11 @@ properties: interrupts: maxItems: 1 + reset-gpios: + maxItems: 1 + + vdd-supply: true + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml b/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml index b8204ed22dd5..09c8948b5e25 100644 --- a/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml +++ b/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml @@ -26,14 +26,16 @@ properties: oneOf: - items: - enum: - - fsl,imx8mn-nic - fsl,imx8mm-nic + - fsl,imx8mn-nic + - fsl,imx8mp-nic - fsl,imx8mq-nic - const: fsl,imx8m-nic - items: - enum: - - fsl,imx8mn-noc - fsl,imx8mm-noc + - fsl,imx8mn-noc + - fsl,imx8mp-noc - fsl,imx8mq-noc - const: fsl,imx8m-noc - const: fsl,imx8m-nic diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml index 8a676fef8c1d..4b37aa88a375 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml @@ -45,7 +45,11 @@ properties: - qcom,sdm660-snoc '#interconnect-cells': - const: 1 + description: | + Value: <1> is one cell in an interconnect specifier for the + interconnect node id, <2> requires the interconnect node id and an + extra path tag. + enum: [ 1, 2 ] clocks: minItems: 2 diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml new file mode 100644 index 000000000000..bbeb0541536b --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,rpmh-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect + +maintainers: + - Georgi Djakov + - Bjorn Andersson + +description: + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is + able to communicate with the BCM through the Resource State Coordinator (RSC) + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. + +properties: + '#interconnect-cells': + enum: [ 1, 2 ] + + qcom,bcm-voters: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 + maxItems: 2 + description: + List of phandles to qcom,bcm-voter nodes that are required by + this interconnect to send RPMh commands. + + qcom,bcm-voter-names: + maxItems: 2 + description: + Names for each of the qcom,bcm-voters specified. + +required: + - '#interconnect-cells' + - qcom,bcm-voters + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml index 28b3516aa089..a429a1ed1006 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml @@ -18,6 +18,9 @@ description: | least one RPMh device child node pertaining to their RSC and each provider can map to multiple RPMh resources. +allOf: + - $ref: qcom,rpmh-common.yaml# + properties: reg: maxItems: 1 @@ -130,28 +133,13 @@ properties: - qcom,sm8450-pcie-anoc - qcom,sm8450-system-noc - '#interconnect-cells': - enum: [ 1, 2 ] - - qcom,bcm-voters: - $ref: /schemas/types.yaml#/definitions/phandle-array - items: - maxItems: 1 - description: | - List of phandles to qcom,bcm-voter nodes that are required by - this interconnect to send RPMh commands. - - qcom,bcm-voter-names: - description: | - Names for each of the qcom,bcm-voters specified. + '#interconnect-cells': true required: - compatible - reg - - '#interconnect-cells' - - qcom,bcm-voters -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml new file mode 100644 index 000000000000..49eb156b08e0 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,sm6350-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6350 RPMh Network-On-Chip Interconnect + +maintainers: + - Luca Weiss + +description: + Qualcomm RPMh-based interconnect provider on SM6350. + +allOf: + - $ref: qcom,rpmh-common.yaml# + +properties: + compatible: + enum: + - qcom,sm6350-aggre1-noc + - qcom,sm6350-aggre2-noc + - qcom,sm6350-config-noc + - qcom,sm6350-dc-noc + - qcom,sm6350-gem-noc + - qcom,sm6350-mmss-noc + - qcom,sm6350-npu-noc + - qcom,sm6350-system-noc + + reg: + maxItems: 1 + + '#interconnect-cells': true + +patternProperties: + '^interconnect-[a-z0-9\-]+$': + type: object + description: + The interconnect providers do not have a separate QoS register space, + but share parent's space. + $ref: qcom,rpmh-common.yaml# + + properties: + compatible: + enum: + - qcom,sm6350-clk-virt + - qcom,sm6350-compute-noc + + '#interconnect-cells': true + + required: + - compatible + + unevaluatedProperties: false + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + config_noc: interconnect@1500000 { + compatible = "qcom,sm6350-config-noc"; + reg = <0x01500000 0x28000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + compatible = "qcom,sm6350-system-noc"; + reg = <0x01620000 0x17080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + + clk_virt: interconnect-clk-virt { + compatible = "qcom,sm6350-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + }; diff --git a/Documentation/devicetree/bindings/misc/qemu,vcpu-stall-detector.yaml b/Documentation/devicetree/bindings/misc/qemu,vcpu-stall-detector.yaml new file mode 100644 index 000000000000..1aebeb696ee0 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/qemu,vcpu-stall-detector.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/qemu,vcpu-stall-detector.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: VCPU stall detector + +description: + This binding describes a CPU stall detector mechanism for virtual CPUs + which is accessed through MMIO. + +maintainers: + - Sebastian Ene + +properties: + compatible: + enum: + - qemu,vcpu-stall-detector + + reg: + maxItems: 1 + + clock-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + The internal clock of the stall detector peripheral measure in Hz used + to decrement its internal counter register on each tick. + Defaults to 10 if unset. + default: 10 + + timeout-sec: + description: | + The stall detector expiration timeout measured in seconds. + Defaults to 8 if unset. Please note that it also takes into account the + time spent while the VCPU is not running. + default: 8 + +required: + - compatible + +additionalProperties: false + +examples: + - | + vmwdt@9030000 { + compatible = "qemu,vcpu-stall-detector"; + reg = <0x9030000 0x10000>; + clock-frequency = <10>; + timeout-sec = <8>; + }; diff --git a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml new file mode 100644 index 000000000000..b5a1109f2ee1 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/mediatek,efuse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek efuse + +description: | + MediaTek's efuse is used for storing calibration data, it can be accessed + on ARM devices usiong I/O mapped memory. + +maintainers: + - Andrew-CT Chen + - Lala Lin + +allOf: + - $ref: "nvmem.yaml#" + +properties: + $nodename: + pattern: "^efuse@[0-9a-f]+$" + + compatible: + oneOf: + - items: + - enum: + - mediatek,mt7622-efuse + - mediatek,mt7623-efuse + - mediatek,mt8173-efuse + - mediatek,mt8183-efuse + - mediatek,mt8186-efuse + - mediatek,mt8192-efuse + - mediatek,mt8195-efuse + - mediatek,mt8516-efuse + - const: mediatek,efuse + - const: mediatek,mt8173-efuse + deprecated: true + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + efuse@11c10000 { + compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; + reg = <0x11c10000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + u3_tx_imp_p0: usb3-tx-imp@184,1 { + reg = <0x184 0x1>; + bits = <0 5>; + }; + u3_rx_imp_p0: usb3-rx-imp@184,2 { + reg = <0x184 0x2>; + bits = <5 5>; + }; + u3_intr_p0: usb3-intr@185 { + reg = <0x185 0x1>; + bits = <2 6>; + }; + comb_tx_imp_p1: usb3-tx-imp@186,1 { + reg = <0x186 0x1>; + bits = <0 5>; + }; + comb_rx_imp_p1: usb3-rx-imp@186,2 { + reg = <0x186 0x2>; + bits = <5 5>; + }; + comb_intr_p1: usb3-intr@187 { + reg = <0x187 0x1>; + bits = <2 6>; + }; + u2_intr_p0: usb2-intr-p0@188,1 { + reg = <0x188 0x1>; + bits = <0 5>; + }; + u2_intr_p1: usb2-intr-p1@188,2 { + reg = <0x188 0x2>; + bits = <5 5>; + }; + }; diff --git a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml new file mode 100644 index 000000000000..c3c96fd0baac --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/microchip,sama7g5-otpc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip SAMA7G5 OTP Controller (OTPC) + +maintainers: + - Claudiu Beznea + +description: | + OTP controller drives a NVMEM memory where system specific data + (e.g. calibration data for analog cells, hardware configuration + settings, chip identifiers) or user specific data could be stored. + +allOf: + - $ref: "nvmem.yaml#" + +properties: + compatible: + items: + - const: microchip,sama7g5-otpc + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + otpc: efuse@e8c00000 { + compatible = "microchip,sama7g5-otpc", "syscon"; + reg = <0xe8c00000 0xec>; + #address-cells = <1>; + #size-cells = <1>; + + temperature_calib: calib@1 { + reg = ; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt b/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt deleted file mode 100644 index 39d529599444..000000000000 --- a/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt +++ /dev/null @@ -1,43 +0,0 @@ -= Mediatek MTK-EFUSE device tree bindings = - -This binding is intended to represent MTK-EFUSE which is found in most Mediatek SOCs. - -Required properties: -- compatible: should be - "mediatek,mt7622-efuse", "mediatek,efuse": for MT7622 - "mediatek,mt7623-efuse", "mediatek,efuse": for MT7623 - "mediatek,mt8173-efuse" or "mediatek,efuse": for MT8173 - "mediatek,mt8192-efuse", "mediatek,efuse": for MT8192 - "mediatek,mt8195-efuse", "mediatek,efuse": for MT8195 - "mediatek,mt8516-efuse", "mediatek,efuse": for MT8516 -- reg: Should contain registers location and length -- bits: contain the bits range by offset and size - -= Data cells = -Are child nodes of MTK-EFUSE, bindings of which as described in -bindings/nvmem/nvmem.txt - -Example: - - efuse: efuse@10206000 { - compatible = "mediatek,mt8173-efuse"; - reg = <0 0x10206000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - /* Data cells */ - thermal_calibration: calib@528 { - reg = <0x528 0xc>; - }; - }; - -= Data consumers = -Are device nodes which consume nvmem data cells. - -For example: - - thermal { - ... - nvmem-cells = <&thermal_calibration>; - nvmem-cell-names = "calibration"; - }; diff --git a/Documentation/devicetree/bindings/phy/amlogic,g12a-mipi-dphy-analog.yaml b/Documentation/devicetree/bindings/phy/amlogic,g12a-mipi-dphy-analog.yaml new file mode 100644 index 000000000000..7aa0c05d6ce4 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/amlogic,g12a-mipi-dphy-analog.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/amlogic,g12a-mipi-dphy-analog.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic G12A MIPI analog PHY + +maintainers: + - Neil Armstrong + +properties: + compatible: + const: amlogic,g12a-mipi-dphy-analog + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@0 { + compatible = "amlogic,g12a-mipi-dphy-analog"; + reg = <0x0 0xc>; + #phy-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml index c50629bd1b51..f0e9ca8427bb 100644 --- a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml +++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml @@ -11,8 +11,9 @@ maintainers: properties: compatible: - items: - - const: cdns,dphy + enum: + - cdns,dphy + - ti,j721e-dphy reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8qm-lvds-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8qm-lvds-phy.yaml new file mode 100644 index 000000000000..8767e48c71a6 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,imx8qm-lvds-phy.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mixel LVDS PHY for Freescale i.MX8qm SoC + +maintainers: + - Liu Ying + +description: | + The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC. + It converts two groups of four 7/10 bits of CMOS data into two + groups of four data lanes of LVDS data streams. A phase-locked + transmit clock is transmitted in parallel with each group of + data streams over a fifth LVDS link. Every cycle of the transmit + clock, 56/80 bits of input data are sampled and transmitted + through the two groups of LVDS data streams. Together with the + transmit clocks, the two groups of LVDS data streams form two + LVDS channels. + + The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled + by Control and Status Registers(CSR) module in the SoC. The CSR + module, as a system controller, contains the PHY's registers. + +properties: + compatible: + enum: + - fsl,imx8qm-lvds-phy + - mixel,28fdsoi-lvds-1250-8ch-tx-pll + + "#phy-cells": + const: 1 + description: | + Cell allows setting the LVDS channel index of the PHY. + Index 0 is for LVDS channel0 and index 1 is for LVDS channel1. + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - "#phy-cells" + - clocks + - power-domains + +additionalProperties: false + +examples: + - | + #include + phy { + compatible = "fsl,imx8qm-lvds-phy"; + #phy-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>; + power-domains = <&pd IMX_SC_R_LVDS_0>; + }; diff --git a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml index 6e4d795f9b02..9c2a7345955d 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml @@ -24,6 +24,10 @@ properties: - enum: - mediatek,mt7623-mipi-tx - const: mediatek,mt2701-mipi-tx + - items: + - enum: + - mediatek,mt8365-mipi-tx + - const: mediatek,mt8183-mipi-tx - const: mediatek,mt2701-mipi-tx - const: mediatek,mt8173-mipi-tx - const: mediatek,mt8183-mipi-tx diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml new file mode 100644 index 000000000000..422750cc4121 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek PCIe PHY + +maintainers: + - Jianjun Wang + +description: | + The PCIe PHY supports physical layer functionality for PCIe Gen3 port. + +properties: + compatible: + const: mediatek,mt8195-pcie-phy + + reg: + maxItems: 1 + + reg-names: + items: + - const: sif + + "#phy-cells": + const: 0 + + nvmem-cells: + maxItems: 7 + description: + Phandles to nvmem cell that contains the efuse data, if unspecified, + default value is used. + + nvmem-cell-names: + items: + - const: glb_intr + - const: tx_ln0_pmos + - const: tx_ln0_nmos + - const: rx_ln0 + - const: tx_ln1_pmos + - const: tx_ln1_nmos + - const: rx_ln1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@11e80000 { + compatible = "mediatek,mt8195-pcie-phy"; + #phy-cells = <0>; + reg = <0x11e80000 0x10000>; + reg-names = "sif"; + nvmem-cells = <&pciephy_glb_intr>, + <&pciephy_tx_ln0_pmos>, + <&pciephy_tx_ln0_nmos>, + <&pciephy_rx_ln0>, + <&pciephy_tx_ln1_pmos>, + <&pciephy_tx_ln1_nmos>, + <&pciephy_rx_ln1>; + nvmem-cell-names = "glb_intr", "tx_ln0_pmos", + "tx_ln0_nmos", "rx_ln0", + "tx_ln1_pmos", "tx_ln1_nmos", + "rx_ln1"; + power-domains = <&spm 2>; + }; diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml index 7b2e1bc119be..b3e409988c17 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml @@ -82,9 +82,11 @@ properties: - mediatek,mt8183-tphy - mediatek,mt8186-tphy - mediatek,mt8192-tphy + - mediatek,mt8365-tphy - const: mediatek,generic-tphy-v2 - items: - enum: + - mediatek,mt8188-tphy - mediatek,mt8195-tphy - const: mediatek,generic-tphy-v3 - const: mediatek,mt2701-u3phy diff --git a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt index c9f5c0caf8a9..c9e392c64a7c 100644 --- a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt @@ -8,6 +8,7 @@ Required properties: * "fsl,vf610-usbphy" for Vybrid vf610 * "fsl,imx6sx-usbphy" for imx6sx * "fsl,imx7ulp-usbphy" for imx7ulp + * "fsl,imx8dxl-usbphy" for imx8dxl "fsl,imx23-usbphy" is still a fallback for other strings - reg: Should contain registers location and length - interrupts: Should contain phy interrupt diff --git a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml index 9a89d05efbda..4dc5205d893b 100644 --- a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml +++ b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml @@ -4,7 +4,7 @@ $id: "http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: NVIDIA Tegra194 P2U binding +title: NVIDIA Tegra194 & Tegra234 P2U binding maintainers: - Thierry Reding @@ -12,13 +12,17 @@ maintainers: description: > Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High Speed) each interfacing with 12 and 8 P2U instances respectively. + Tegra234 has three PHY bricks namely HSIO, NVHS and GBE (Gigabit Ethernet) + each interfacing with 8, 8 and 8 P2U instances respectively. A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE - interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe - lane. + interface and PHY of HSIO/NVHS/GBE bricks. Each P2U instance represents one + PCIe lane. properties: compatible: - const: nvidia,tegra194-p2u + enum: + - nvidia,tegra194-p2u + - nvidia,tegra234-p2u reg: maxItems: 1 @@ -28,6 +32,11 @@ properties: items: - const: ctl + nvidia,skip-sz-protect-en: + description: Should be present if two PCIe retimers are present between + the root port and its immediate downstream device. + type: boolean + '#phy-cells': const: 0 diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml index a5850ff529f8..cf9e9b8011cb 100644 --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml @@ -41,6 +41,9 @@ properties: "#phy-cells": const: 0 + vdda-phy-supply: true + vdda-pll-supply: true + required: - compatible - reg @@ -65,5 +68,8 @@ examples: #clock-cells = <1>; #phy-cells = <0>; + + vdda-phy-supply = <&vdd_a_edp_0_1p2>; + vdda-pll-supply = <&vdd_a_edp_0_0p9>; }; ... diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index 8b850c5ab116..220788ce215f 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -19,6 +19,7 @@ properties: enum: - qcom,ipq6018-qmp-pcie-phy - qcom,ipq6018-qmp-usb3-phy + - qcom,ipq8074-qmp-gen3-pcie-phy - qcom,ipq8074-qmp-pcie-phy - qcom,ipq8074-qmp-usb3-phy - qcom,msm8996-qmp-pcie-phy @@ -312,6 +313,7 @@ allOf: contains: enum: - qcom,ipq6018-qmp-pcie-phy + - qcom,ipq8074-qmp-gen3-pcie-phy - qcom,ipq8074-qmp-pcie-phy then: properties: diff --git a/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml index b8483f9edbfc..fe57c5373d18 100644 --- a/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml +++ b/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml @@ -34,7 +34,7 @@ properties: # must not be 0. minItems: 2 items: - - const: usb3-if # The funcional clock + - const: usb3-if # The functional clock - const: usb3s_clk # The usb3's external clock - const: usb_extal # The usb2's external clock diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml index f6ed1a005e7a..8da99461e817 100644 --- a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml @@ -17,6 +17,7 @@ properties: enum: - samsung,exynos7-ufs-phy - samsung,exynosautov9-ufs-phy + - tesla,fsd-ufs-phy reg: maxItems: 1 @@ -40,9 +41,17 @@ properties: - const: tx0_symbol_clk samsung,pmu-syscon: - $ref: '/schemas/types.yaml#/definitions/phandle' - description: phandle for PMU system controller interface, used to - control pmu registers bits for ufs m-phy + $ref: '/schemas/types.yaml#/definitions/phandle-array' + maxItems: 1 + items: + minItems: 1 + items: + - description: phandle for PMU system controller interface, used to + control pmu registers bits for ufs m-phy + - description: offset of the pmu control register + description: + It can be phandle/offset pair. The second cell which can represent an + offset is optional. required: - "#phy-cells" diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 6414a338f244..5a3bc64773a9 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -799,6 +799,8 @@ patternProperties: description: MiraMEMS Sensing Technology Co., Ltd. "^mitsubishi,.*": description: Mitsubishi Electric Corporation + "^mixel,.*": + description: Mixel, Inc. "^miyoo,.*": description: Miyoo "^mntre,.*": diff --git a/Documentation/driver-api/fpga/fpga-mgr.rst b/Documentation/driver-api/fpga/fpga-mgr.rst index 42c01f396dce..49c0a9512653 100644 --- a/Documentation/driver-api/fpga/fpga-mgr.rst +++ b/Documentation/driver-api/fpga/fpga-mgr.rst @@ -79,12 +79,27 @@ do the programming sequence for this particular FPGA. These ops return 0 for success or negative error codes otherwise. The programming sequence is:: - 1. .write_init - 2. .write or .write_sg (may be called once or multiple times) - 3. .write_complete + 1. .parse_header (optional, may be called once or multiple times) + 2. .write_init + 3. .write or .write_sg (may be called once or multiple times) + 4. .write_complete -The .write_init function will prepare the FPGA to receive the image data. The -buffer passed into .write_init will be at most .initial_header_size bytes long; +The .parse_header function will set header_size and data_size to +struct fpga_image_info. Before parse_header call, header_size is initialized +with initial_header_size. If flag skip_header of fpga_manager_ops is true, +.write function will get image buffer starting at header_size offset from the +beginning. If data_size is set, .write function will get data_size bytes of +the image buffer, otherwise .write will get data up to the end of image buffer. +This will not affect .write_sg, .write_sg will still get whole image in +sg_table form. If FPGA image is already mapped as a single contiguous buffer, +whole buffer will be passed into .parse_header. If image is in scatter-gather +form, core code will buffer up at least .initial_header_size before the first +call of .parse_header, if it is not enough, .parse_header should set desired +size into info->header_size and return -EAGAIN, then it will be called again +with greater part of image buffer on the input. + +The .write_init function will prepare the FPGA to receive the image data. The +buffer passed into .write_init will be at least info->header_size bytes long; if the whole bitstream is not immediately available then the core code will buffer up at least this much before starting. diff --git a/Documentation/trace/coresight/coresight-etm4x-reference.rst b/Documentation/trace/coresight/coresight-etm4x-reference.rst index d25dfe86af9b..fb7578fd9372 100644 --- a/Documentation/trace/coresight/coresight-etm4x-reference.rst +++ b/Documentation/trace/coresight/coresight-etm4x-reference.rst @@ -650,13 +650,26 @@ Bit assignments shown below:- parameter is set this value is applied to the currently indexed address range. +.. _coresight-branch-broadcast: **bit (4):** ETM_MODE_BB **description:** - Set to enable branch broadcast if supported in hardware [IDR0]. + Set to enable branch broadcast if supported in hardware [IDR0]. The primary use for this feature + is when code is patched dynamically at run time and the full program flow may not be able to be + reconstructed using only conditional branches. + There is currently no support in Perf for supplying modified binaries to the decoder, so this + feature is only inteded to be used for debugging purposes or with a 3rd party tool. + + Choosing this option will result in a significant increase in the amount of trace generated - + possible danger of overflows, or fewer instructions covered. Note, that this option also + overrides any setting of :ref:`ETM_MODE_RETURNSTACK `, so where a branch + broadcast range overlaps a return stack range, return stacks will not be available for that + range. + +.. _coresight-cycle-accurate: **bit (5):** ETMv4_MODE_CYCACC @@ -678,6 +691,7 @@ Bit assignments shown below:- **description:** Set to enable virtual machine ID tracing if supported [IDR2]. +.. _coresight-timestamp: **bit (11):** ETMv4_MODE_TIMESTAMP @@ -685,6 +699,7 @@ Bit assignments shown below:- **description:** Set to enable timestamp generation if supported [IDR0]. +.. _coresight-return-stack: **bit (12):** ETM_MODE_RETURNSTACK diff --git a/Documentation/trace/coresight/coresight.rst b/Documentation/trace/coresight/coresight.rst index a15571d96cc8..4a71ea6cb390 100644 --- a/Documentation/trace/coresight/coresight.rst +++ b/Documentation/trace/coresight/coresight.rst @@ -130,7 +130,7 @@ Misc: Device Tree Bindings -------------------- -See Documentation/devicetree/bindings/arm/coresight.txt for details. +See Documentation/devicetree/bindings/arm/arm,coresight-\*.yaml for details. As of this writing drivers for ITM, STMs and CTIs are not provided but are expected to be added as the solution matures. @@ -339,7 +339,8 @@ Preference is given to the former as using the sysFS interface requires a deep understanding of the Coresight HW. The following sections provide details on using both methods. -1) Using the sysFS interface: +Using the sysFS interface +~~~~~~~~~~~~~~~~~~~~~~~~~ Before trace collection can start, a coresight sink needs to be identified. There is no limit on the amount of sinks (nor sources) that can be enabled at @@ -446,7 +447,8 @@ wealth of possibilities that coresight provides. Instruction 0 0x8026B588 E8BD8000 true LDM sp!,{pc} Timestamp Timestamp: 17107041535 -2) Using perf framework: +Using perf framework +~~~~~~~~~~~~~~~~~~~~ Coresight tracers are represented using the Perf framework's Performance Monitoring Unit (PMU) abstraction. As such the perf framework takes charge of @@ -495,7 +497,11 @@ More information on the above and other example on how to use Coresight with the perf tools can be found in the "HOWTO.md" file of the openCSD gitHub repository [#third]_. -2.1) AutoFDO analysis using the perf tools: +Advanced perf framework usage +----------------------------- + +AutoFDO analysis using the perf tools +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ perf can be used to record and analyze trace of programs. @@ -513,7 +519,8 @@ The --itrace option controls the type and frequency of synthesized events Note that only 64-bit programs are currently supported - further work is required to support instruction decode of 32-bit Arm programs. -2.2) Tracing PID +Tracing PID +~~~~~~~~~~~ The kernel can be built to write the PID value into the PE ContextID registers. For a kernel running at EL1, the PID is stored in CONTEXTIDR_EL1. A PE may @@ -547,7 +554,7 @@ wants to trace PIDs for both host and guest, the two configs "contextid1" and Generating coverage files for Feedback Directed Optimization: AutoFDO ---------------------------------------------------------------------- +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 'perf inject' accepts the --itrace option in which case tracing data is removed and replaced with the synthesized events. e.g. @@ -578,6 +585,45 @@ sort example is from the AutoFDO tutorial (https://gcc.gnu.org/wiki/AutoFDO/Tuto Bubble sorting array of 30000 elements 5806 ms +Config option formats +~~~~~~~~~~~~~~~~~~~~~ + +The following strings can be provided between // on the perf command line to enable various options. +They are also listed in the folder /sys/bus/event_source/devices/cs_etm/format/ + +.. list-table:: + :header-rows: 1 + + * - Option + - Description + * - branch_broadcast + - Session local version of the system wide setting: + :ref:`ETM_MODE_BB ` + * - contextid + - See `Tracing PID`_ + * - contextid1 + - See `Tracing PID`_ + * - contextid2 + - See `Tracing PID`_ + * - configid + - Selection for a custom configuration. This is an implementation detail and not used directly, + see :ref:`trace/coresight/coresight-config:Using Configurations in perf` + * - preset + - Override for parameters in a custom configuration, see + :ref:`trace/coresight/coresight-config:Using Configurations in perf` + * - sinkid + - Hashed version of the string to select a sink, automatically set when using the @ notation. + This is an internal implementation detail and is not used directly, see `Using perf + framework`_. + * - cycacc + - Session local version of the system wide setting: :ref:`ETMv4_MODE_CYCACC + ` + * - retstack + - Session local version of the system wide setting: :ref:`ETM_MODE_RETURNSTACK + ` + * - timestamp + - Session local version of the system wide setting: :ref:`ETMv4_MODE_TIMESTAMP + ` How to use the STM module ------------------------- diff --git a/MAINTAINERS b/MAINTAINERS index fee3ecc2d6ca..b779a0b435e3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -284,38 +284,37 @@ S: Maintained F: drivers/hwmon/abituguru3.c ACCES 104-DIO-48E GPIO DRIVER -M: William Breathitt Gray +M: William Breathitt Gray L: linux-gpio@vger.kernel.org S: Maintained F: drivers/gpio/gpio-104-dio-48e.c ACCES 104-IDI-48 GPIO DRIVER -M: "William Breathitt Gray" +M: William Breathitt Gray L: linux-gpio@vger.kernel.org S: Maintained F: drivers/gpio/gpio-104-idi-48.c ACCES 104-IDIO-16 GPIO DRIVER -M: "William Breathitt Gray" +M: William Breathitt Gray L: linux-gpio@vger.kernel.org S: Maintained F: drivers/gpio/gpio-104-idio-16.c ACCES 104-QUAD-8 DRIVER -M: William Breathitt Gray -M: Syed Nayyar Waris +M: William Breathitt Gray L: linux-iio@vger.kernel.org S: Maintained F: drivers/counter/104-quad-8.c ACCES PCI-IDIO-16 GPIO DRIVER -M: William Breathitt Gray +M: William Breathitt Gray L: linux-gpio@vger.kernel.org S: Maintained F: drivers/gpio/gpio-pci-idio-16.c ACCES PCIe-IDIO-24 GPIO DRIVER -M: William Breathitt Gray +M: William Breathitt Gray L: linux-gpio@vger.kernel.org S: Maintained F: drivers/gpio/gpio-pcie-idio-24.c @@ -1340,7 +1339,7 @@ M: Todd Kjos M: Martijn Coenen M: Joel Fernandes M: Christian Brauner -M: Hridya Valsaraju +M: Carlos Llamas M: Suren Baghdasaryan L: linux-kernel@vger.kernel.org S: Supported @@ -1367,7 +1366,7 @@ S: Maintained F: sound/aoa/ APEX EMBEDDED SYSTEMS STX104 IIO DRIVER -M: William Breathitt Gray +M: William Breathitt Gray L: linux-iio@vger.kernel.org S: Maintained F: drivers/iio/adc/stx104.c @@ -2002,11 +2001,9 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git F: Documentation/ABI/testing/sysfs-bus-coresight-devices-* -F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt -F: Documentation/devicetree/bindings/arm/coresight-cti.yaml -F: Documentation/devicetree/bindings/arm/coresight.txt -F: Documentation/devicetree/bindings/arm/ete.yaml -F: Documentation/devicetree/bindings/arm/trbe.yaml +F: Documentation/devicetree/bindings/arm/arm,coresight-*.yaml +F: Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml +F: Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml F: Documentation/trace/coresight/* F: drivers/hwtracing/coresight/* F: include/dt-bindings/arm/coresight-cti-dt.h @@ -5256,10 +5253,10 @@ F: Documentation/hwmon/corsair-psu.rst F: drivers/hwmon/corsair-psu.c COUNTER SUBSYSTEM -M: William Breathitt Gray +M: William Breathitt Gray L: linux-iio@vger.kernel.org S: Maintained -T: git git@gitlab.com:vilhelmgray/counter.git +T: git https://git.linaro.org/people/william.gray/counter.git F: Documentation/ABI/testing/sysfs-bus-counter F: Documentation/driver-api/generic-counter.rst F: drivers/counter/ @@ -6019,7 +6016,7 @@ F: include/sound/da[79]*.h F: sound/soc/codecs/da[79]*.[ch] DIAMOND SYSTEMS GPIO-MM GPIO DRIVER -M: William Breathitt Gray +M: William Breathitt Gray L: linux-gpio@vger.kernel.org S: Maintained F: drivers/gpio/gpio-gpio-mm.c @@ -6881,6 +6878,7 @@ L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Supported F: Documentation/devicetree/bindings/display/mediatek/ F: drivers/gpu/drm/mediatek/ +F: drivers/phy/mediatek/phy-mtk-dp.c F: drivers/phy/mediatek/phy-mtk-hdmi* F: drivers/phy/mediatek/phy-mtk-mipi* @@ -8006,6 +8004,21 @@ F: Documentation/fpga/ F: drivers/fpga/ F: include/linux/fpga/ +INTEL MAX10 BMC SECURE UPDATES +M: Russ Weight +L: linux-fpga@vger.kernel.org +S: Maintained +F: Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update +F: drivers/fpga/intel-m10-bmc-sec-update.c + +MICROCHIP POLARFIRE FPGA DRIVERS +M: Conor Dooley +R: Ivan Bornyakov +L: linux-fpga@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml +F: drivers/fpga/microchip-spi.c + FPU EMULATOR M: Bill Metzenthen S: Maintained @@ -8508,6 +8521,7 @@ Q: https://patchwork.kernel.org/project/linux-phy/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git F: Documentation/devicetree/bindings/phy/ F: drivers/phy/ +F: include/dt-bindings/phy/ F: include/linux/phy/ GENERIC PINCTRL I2C DEMULTIPLEXER DRIVER @@ -9829,6 +9843,7 @@ F: Documentation/ABI/testing/sysfs-bus-iio* F: Documentation/devicetree/bindings/iio/ F: drivers/iio/ F: drivers/staging/iio/ +F: include/dt-bindings/iio/ F: include/linux/iio/ F: tools/iio/ @@ -10664,7 +10679,7 @@ F: Documentation/devicetree/bindings/interrupt-controller/ F: drivers/irqchip/ ISA -M: William Breathitt Gray +M: William Breathitt Gray S: Maintained F: Documentation/driver-api/isa.rst F: drivers/base/isa.c @@ -12440,7 +12455,7 @@ F: drivers/net/ieee802154/mcr20a.c F: drivers/net/ieee802154/mcr20a.h MEASUREMENT COMPUTING CIO-DAC IIO DRIVER -M: William Breathitt Gray +M: William Breathitt Gray L: linux-iio@vger.kernel.org S: Maintained F: drivers/iio/dac/cio-dac.c @@ -13359,6 +13374,14 @@ S: Supported F: Documentation/devicetree/bindings/mtd/atmel-nand.txt F: drivers/mtd/nand/raw/atmel/* +MICROCHIP OTPC DRIVER +M: Claudiu Beznea +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +F: Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml +F: drivers/nvmem/microchip-otpc.c +F: include/dt-bindings/nvmem/microchip,sama7g5-otpc.h + MICROCHIP PWM DRIVER M: Claudiu Beznea L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -21361,6 +21384,7 @@ M: Jason Wang L: virtualization@lists.linux-foundation.org S: Maintained F: Documentation/ABI/testing/sysfs-bus-vdpa +F: Documentation/ABI/testing/sysfs-class-vduse F: Documentation/devicetree/bindings/virtio/ F: drivers/block/virtio_blk.c F: drivers/crypto/virtio/ @@ -21779,13 +21803,13 @@ S: Maintained F: drivers/media/rc/winbond-cir.c WINSYSTEMS EBC-C384 WATCHDOG DRIVER -M: William Breathitt Gray +M: William Breathitt Gray L: linux-watchdog@vger.kernel.org S: Maintained F: drivers/watchdog/ebc-c384_wdt.c WINSYSTEMS WS16C48 GPIO DRIVER -M: William Breathitt Gray +M: William Breathitt Gray L: linux-gpio@vger.kernel.org S: Maintained F: drivers/gpio/gpio-ws16c48.c diff --git a/drivers/Makefile b/drivers/Makefile index 9a30842b22c5..123dce286758 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -176,7 +176,7 @@ obj-$(CONFIG_USB4) += thunderbolt/ obj-$(CONFIG_CORESIGHT) += hwtracing/coresight/ obj-y += hwtracing/intel_th/ obj-$(CONFIG_STM) += hwtracing/stm/ -obj-$(CONFIG_ANDROID) += android/ +obj-y += android/ obj-$(CONFIG_NVMEM) += nvmem/ obj-$(CONFIG_FPGA) += fpga/ obj-$(CONFIG_FSI) += fsi/ diff --git a/drivers/accessibility/speakup/.gitignore b/drivers/accessibility/speakup/.gitignore new file mode 100644 index 000000000000..ac084679fea7 --- /dev/null +++ b/drivers/accessibility/speakup/.gitignore @@ -0,0 +1,4 @@ +/makemapdata +/mapdata.h +/genmap +/speakupmap.h diff --git a/drivers/accessibility/speakup/Makefile b/drivers/accessibility/speakup/Makefile index 6e4bfac8af65..ba69b0803d42 100644 --- a/drivers/accessibility/speakup/Makefile +++ b/drivers/accessibility/speakup/Makefile @@ -30,3 +30,31 @@ speakup-y := \ thread.o \ varhandlers.o speakup-$(CONFIG_SPEAKUP_SERIALIO) += serialio.o + + +clean-files := mapdata.h speakupmap.h + + +# Generate mapdata.h from headers +hostprogs += makemapdata +makemapdata-objs := makemapdata.o + +quiet_cmd_mkmap = MKMAP $@ + cmd_mkmap = TOPDIR=$(srctree) $(obj)/makemapdata > $@ + +$(obj)/mapdata.h: $(obj)/makemapdata + $(call cmd,mkmap) + + +# Generate speakupmap.h from mapdata.h +hostprogs += genmap +genmap-objs := genmap.o +$(obj)/genmap.o: $(obj)/mapdata.h + +quiet_cmd_genmap = GENMAP $@ + cmd_genmap = $(obj)/genmap $< > $@ + +$(obj)/speakupmap.h: $(src)/speakupmap.map $(obj)/genmap + $(call cmd,genmap) + +$(obj)/main.o: $(obj)/speakupmap.h diff --git a/drivers/accessibility/speakup/genmap.c b/drivers/accessibility/speakup/genmap.c new file mode 100644 index 000000000000..0125000e00d9 --- /dev/null +++ b/drivers/accessibility/speakup/genmap.c @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* genmap.c + * originally written by: Kirk Reiser. + * + ** Copyright (C) 2002 Kirk Reiser. + * Copyright (C) 2003 David Borowski. + */ + +#include +#include +#include +#include +#include +#include +#include "utils.h" + +struct st_key_init { + char *name; + int value, shift; +}; + +static unsigned char key_data[MAXKEYVAL][16], *kp; + +#include "mapdata.h" + +static const char delims[] = "\t\n "; +static char *cp; +static int map_ver = 119; /* an arbitrary number so speakup can check */ +static int shift_table[17]; +static int max_states = 1, flags; +/* flags reserved for later, maybe for individual console maps */ + +static int get_shift_value(int state) +{ + int i; + + for (i = 0; shift_table[i] != state; i++) { + if (shift_table[i] == -1) { + if (i >= 16) + oops("too many shift states", NULL); + shift_table[i] = state; + max_states = i+1; + break; + } + } + return i; +} + +int +main(int argc, char *argv[]) +{ + int value, shift_state, i, spk_val = 0, lock_val = 0; + int max_key_used = 0, num_keys_used = 0; + struct st_key *this; + struct st_key_init *p_init; + char buffer[256]; + + bzero(key_table, sizeof(key_table)); + bzero(key_data, sizeof(key_data)); + + shift_table[0] = 0; + for (i = 1; i <= 16; i++) + shift_table[i] = -1; + + if (argc < 2) { + fputs("usage: genmap filename\n", stderr); + exit(1); + } + + for (p_init = init_key_data; p_init->name[0] != '.'; p_init++) + add_key(p_init->name, p_init->value, p_init->shift); + + open_input(NULL, argv[1]); + while (fgets(buffer, sizeof(buffer), infile)) { + lc++; + value = shift_state = 0; + + cp = strtok(buffer, delims); + if (*cp == '#') + continue; + + while (cp) { + if (*cp == '=') + break; + this = find_key(cp); + if (this == NULL) + oops("unknown key/modifier", cp); + if (this->shift == is_shift) { + if (value) + oops("modifiers must come first", cp); + shift_state += this->value; + } else if (this->shift == is_input) + value = this->value; + else + oops("bad modifier or key", cp); + cp = strtok(0, delims); + } + if (!cp) + oops("no = found", NULL); + + cp = strtok(0, delims); + if (!cp) + oops("no speakup function after =", NULL); + + this = find_key(cp); + if (this == NULL || this->shift != is_spk) + oops("invalid speakup function", cp); + + i = get_shift_value(shift_state); + if (key_data[value][i]) { + while (--cp > buffer) + if (!*cp) + *cp = ' '; + oops("two functions on same key combination", cp); + } + key_data[value][i] = (char)this->value; + if (value > max_key_used) + max_key_used = value; + } + fclose(infile); + + this = find_key("spk_key"); + if (this) + spk_val = this->value; + + this = find_key("spk_lock"); + if (this) + lock_val = this->value; + + for (lc = 1; lc <= max_key_used; lc++) { + kp = key_data[lc]; + if (!memcmp(key_data[0], kp, 16)) + continue; + num_keys_used++; + for (i = 0; i < max_states; i++) { + if (kp[i] != spk_val && kp[i] != lock_val) + continue; + shift_state = shift_table[i]; + if (shift_state&16) + continue; + shift_state = get_shift_value(shift_state+16); + kp[shift_state] = kp[i]; + /* fill in so we can process the key up, as spk bit will be set */ + } + } + + printf("\t%d, %d, %d,\n\t", map_ver, num_keys_used, max_states); + for (i = 0; i < max_states; i++) + printf("%d, ", shift_table[i]); + printf("%d,", flags); + for (lc = 1; lc <= max_key_used; lc++) { + kp = key_data[lc]; + if (!memcmp(key_data[0], kp, 16)) + continue; + printf("\n\t%d,", lc); + for (i = 0; i < max_states; i++) + printf(" %d,", (unsigned int)kp[i]); + } + printf("\n\t0, %d\n", map_ver); + + exit(0); +} diff --git a/drivers/accessibility/speakup/makemapdata.c b/drivers/accessibility/speakup/makemapdata.c new file mode 100644 index 000000000000..81db9ebf1fff --- /dev/null +++ b/drivers/accessibility/speakup/makemapdata.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* makemapdata.c + * originally written by: Kirk Reiser. + * + ** Copyright (C) 2002 Kirk Reiser. + * Copyright (C) 2003 David Borowski. + */ + +#include +#include +#include +#include +#include +#include +#include "utils.h" + +static char buffer[256]; + +static int get_define(void) +{ + char *c; + + while (fgets(buffer, sizeof(buffer)-1, infile)) { + lc++; + if (strncmp(buffer, "#define", 7)) + continue; + c = buffer + 7; + while (*c == ' ' || *c == '\t') + c++; + def_name = c; + while (*c && *c != ' ' && *c != '\t' && *c != '\n') + c++; + if (!*c || *c == '\n') + continue; + *c++ = '\0'; + while (*c == ' ' || *c == '\t' || *c == '(') + c++; + def_val = c; + while (*c && *c != '\n' && *c != ')') + c++; + *c++ = '\0'; + return 1; + } + fclose(infile); + infile = 0; + return 0; +} + +int +main(int argc, char *argv[]) +{ + int value, i; + struct st_key *this; + const char *dir_name; + char *cp; + + dir_name = getenv("TOPDIR"); + if (!dir_name) + dir_name = "."; + bzero(key_table, sizeof(key_table)); + add_key("shift", 1, is_shift); + add_key("altgr", 2, is_shift); + add_key("ctrl", 4, is_shift); + add_key("alt", 8, is_shift); + add_key("spk", 16, is_shift); + add_key("double", 32, is_shift); + + open_input(dir_name, "include/linux/input.h"); + while (get_define()) { + if (strncmp(def_name, "KEY_", 4)) + continue; + value = atoi(def_val); + if (value > 0 && value < MAXKEYVAL) + add_key(def_name, value, is_input); + } + + open_input(dir_name, "include/uapi/linux/input-event-codes.h"); + while (get_define()) { + if (strncmp(def_name, "KEY_", 4)) + continue; + value = atoi(def_val); + if (value > 0 && value < MAXKEYVAL) + add_key(def_name, value, is_input); + } + + open_input(dir_name, "drivers/accessibility/speakup/spk_priv_keyinfo.h"); + while (get_define()) { + if (strlen(def_val) > 5) { + //if (def_val[0] == '(') + // def_val++; + cp = strchr(def_val, '+'); + if (!cp) + continue; + if (cp[-1] == ' ') + cp[-1] = '\0'; + *cp++ = '\0'; + this = find_key(def_val); + while (*cp == ' ') + cp++; + if (!this || *cp < '0' || *cp > '9') + continue; + value = this->value+atoi(cp); + } else if (!strncmp(def_val, "0x", 2)) + sscanf(def_val+2, "%x", &value); + else if (*def_val >= '0' && *def_val <= '9') + value = atoi(def_val); + else + continue; + add_key(def_name, value, is_spk); + } + + printf("struct st_key_init init_key_data[] = {\n"); + for (i = 0; i < HASHSIZE; i++) { + this = &key_table[i]; + if (!this->name) + continue; + do { + printf("\t{ \"%s\", %d, %d, },\n", this->name, this->value, this->shift); + this = this->next; + } while (this); + } + printf("\t{ \".\", 0, 0 }\n};\n"); + + exit(0); +} diff --git a/drivers/accessibility/speakup/speakupmap.h b/drivers/accessibility/speakup/speakupmap.h deleted file mode 100644 index c60d7339b89a..000000000000 --- a/drivers/accessibility/speakup/speakupmap.h +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - 119, 62, 6, - 0, 16, 20, 17, 32, 48, 0, - 2, 0, 78, 0, 0, 0, 0, - 3, 0, 79, 0, 0, 0, 0, - 4, 0, 76, 0, 0, 0, 0, - 5, 0, 77, 0, 0, 0, 0, - 6, 0, 74, 0, 0, 0, 0, - 7, 0, 75, 0, 0, 0, 0, - 9, 0, 5, 46, 0, 0, 0, - 10, 0, 4, 0, 0, 0, 0, - 11, 0, 0, 1, 0, 0, 0, - 12, 0, 27, 0, 33, 0, 0, - 19, 0, 47, 0, 0, 0, 0, - 21, 0, 29, 17, 0, 0, 0, - 22, 0, 15, 0, 0, 0, 0, - 23, 0, 14, 0, 0, 0, 28, - 24, 0, 16, 0, 0, 0, 0, - 25, 0, 30, 18, 0, 0, 0, - 28, 0, 3, 26, 0, 0, 0, - 35, 0, 31, 0, 0, 0, 0, - 36, 0, 12, 0, 0, 0, 0, - 37, 0, 11, 0, 0, 0, 22, - 38, 0, 13, 0, 0, 0, 0, - 39, 0, 32, 7, 0, 0, 0, - 40, 0, 23, 0, 0, 0, 0, - 44, 0, 44, 0, 0, 0, 0, - 49, 0, 24, 0, 0, 0, 0, - 50, 0, 9, 19, 6, 0, 0, - 51, 0, 8, 0, 0, 0, 36, - 52, 0, 10, 20, 0, 0, 0, - 53, 0, 25, 0, 0, 0, 0, - 55, 46, 1, 0, 0, 0, 0, - 58, 128, 128, 0, 0, 0, 0, - 59, 0, 45, 0, 0, 0, 0, - 60, 0, 40, 0, 0, 0, 0, - 61, 0, 41, 0, 0, 0, 0, - 62, 0, 42, 0, 0, 0, 0, - 63, 0, 34, 0, 0, 0, 0, - 64, 0, 35, 0, 0, 0, 0, - 65, 0, 37, 0, 0, 0, 0, - 66, 0, 38, 0, 0, 0, 0, - 67, 0, 66, 0, 39, 0, 0, - 68, 0, 67, 0, 0, 0, 0, - 71, 15, 19, 0, 0, 0, 0, - 72, 14, 29, 0, 0, 28, 0, - 73, 16, 17, 0, 0, 0, 0, - 74, 27, 33, 0, 0, 0, 0, - 75, 12, 31, 0, 0, 0, 0, - 76, 11, 21, 0, 0, 22, 0, - 77, 13, 32, 0, 0, 0, 0, - 78, 23, 43, 0, 0, 0, 0, - 79, 9, 20, 0, 0, 0, 0, - 80, 8, 30, 0, 0, 36, 0, - 81, 10, 18, 0, 0, 0, 0, - 82, 128, 128, 0, 0, 0, 0, - 83, 24, 25, 0, 0, 0, 0, - 87, 0, 68, 0, 0, 0, 0, - 88, 0, 69, 0, 0, 0, 0, - 96, 3, 26, 0, 0, 0, 0, - 98, 4, 5, 0, 0, 0, 0, - 99, 2, 0, 0, 0, 0, 0, - 104, 0, 6, 0, 0, 0, 0, - 109, 0, 7, 0, 0, 0, 0, - 125, 128, 128, 0, 0, 0, 0, - 0, 119 diff --git a/drivers/accessibility/speakup/utils.h b/drivers/accessibility/speakup/utils.h new file mode 100644 index 000000000000..4bf2ee8ac246 --- /dev/null +++ b/drivers/accessibility/speakup/utils.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* utils.h + * originally written by: Kirk Reiser. + * + ** Copyright (C) 2002 Kirk Reiser. + * Copyright (C) 2003 David Borowski. + */ + +#include + +#define MAXKEYS 512 +#define MAXKEYVAL 160 +#define HASHSIZE 101 +#define is_shift -3 +#define is_spk -2 +#define is_input -1 + +struct st_key { + char *name; + struct st_key *next; + int value, shift; +}; + +struct st_key key_table[MAXKEYS]; +struct st_key *extra_keys = key_table+HASHSIZE; +char *def_name, *def_val; +FILE *infile; +int lc; + +char filename[256]; + +static inline void open_input(const char *dir_name, const char *name) +{ + if (dir_name) + snprintf(filename, sizeof(filename), "%s/%s", dir_name, name); + else + snprintf(filename, sizeof(filename), "%s", name); + infile = fopen(filename, "r"); + if (infile == 0) { + fprintf(stderr, "can't open %s\n", filename); + exit(1); + } + lc = 0; +} + +static inline int oops(const char *msg, const char *info) +{ + if (info == NULL) + info = ""; + fprintf(stderr, "error: file %s line %d\n", filename, lc); + fprintf(stderr, "%s %s\n", msg, info); + exit(1); +} + +static inline struct st_key *hash_name(char *name) +{ + u_char *pn = (u_char *)name; + int hash = 0; + + while (*pn) { + hash = (hash * 17) & 0xfffffff; + if (isupper(*pn)) + *pn = tolower(*pn); + hash += (int)*pn; + pn++; + } + hash %= HASHSIZE; + return &key_table[hash]; +} + +static inline struct st_key *find_key(char *name) +{ + struct st_key *this = hash_name(name); + + while (this) { + if (this->name && !strcmp(name, this->name)) + return this; + this = this->next; + } + return this; +} + +static inline struct st_key *add_key(char *name, int value, int shift) +{ + struct st_key *this = hash_name(name); + + if (extra_keys-key_table >= MAXKEYS) + oops("out of key table space, enlarge MAXKEYS", NULL); + if (this->name != NULL) { + while (this->next) { + if (!strcmp(name, this->name)) + oops("attempt to add duplicate key", name); + this = this->next; + } + this->next = extra_keys++; + this = this->next; + } + this->name = strdup(name); + this->value = value; + this->shift = shift; + return this; +} diff --git a/drivers/android/Kconfig b/drivers/android/Kconfig index 53b22e26266c..07aa8ae0a058 100644 --- a/drivers/android/Kconfig +++ b/drivers/android/Kconfig @@ -1,13 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 menu "Android" -config ANDROID - bool "Android Drivers" - help - Enable support for various drivers needed on the Android platform - -if ANDROID - config ANDROID_BINDER_IPC bool "Android Binder IPC Driver" depends on MMU @@ -54,6 +47,4 @@ config ANDROID_BINDER_IPC_SELFTEST exhaustively with combinations of various buffer sizes and alignments. -endif # if ANDROID - endmenu diff --git a/drivers/android/binder.c b/drivers/android/binder.c index 362c0deb65f1..c964d7c8c384 100644 --- a/drivers/android/binder.c +++ b/drivers/android/binder.c @@ -197,8 +197,32 @@ static inline void binder_stats_created(enum binder_stat_types type) atomic_inc(&binder_stats.obj_created[type]); } -struct binder_transaction_log binder_transaction_log; -struct binder_transaction_log binder_transaction_log_failed; +struct binder_transaction_log_entry { + int debug_id; + int debug_id_done; + int call_type; + int from_proc; + int from_thread; + int target_handle; + int to_proc; + int to_thread; + int to_node; + int data_size; + int offsets_size; + int return_error_line; + uint32_t return_error; + uint32_t return_error_param; + char context_name[BINDERFS_MAX_NAME + 1]; +}; + +struct binder_transaction_log { + atomic_t cur; + bool full; + struct binder_transaction_log_entry entry[32]; +}; + +static struct binder_transaction_log binder_transaction_log; +static struct binder_transaction_log binder_transaction_log_failed; static struct binder_transaction_log_entry *binder_transaction_log_add( struct binder_transaction_log *log) @@ -2626,6 +2650,56 @@ static int binder_fixup_parent(struct list_head *pf_head, return binder_add_fixup(pf_head, buffer_offset, bp->buffer, 0); } +/** + * binder_can_update_transaction() - Can a txn be superseded by an updated one? + * @t1: the pending async txn in the frozen process + * @t2: the new async txn to supersede the outdated pending one + * + * Return: true if t2 can supersede t1 + * false if t2 can not supersede t1 + */ +static bool binder_can_update_transaction(struct binder_transaction *t1, + struct binder_transaction *t2) +{ + if ((t1->flags & t2->flags & (TF_ONE_WAY | TF_UPDATE_TXN)) != + (TF_ONE_WAY | TF_UPDATE_TXN) || !t1->to_proc || !t2->to_proc) + return false; + if (t1->to_proc->tsk == t2->to_proc->tsk && t1->code == t2->code && + t1->flags == t2->flags && t1->buffer->pid == t2->buffer->pid && + t1->buffer->target_node->ptr == t2->buffer->target_node->ptr && + t1->buffer->target_node->cookie == t2->buffer->target_node->cookie) + return true; + return false; +} + +/** + * binder_find_outdated_transaction_ilocked() - Find the outdated transaction + * @t: new async transaction + * @target_list: list to find outdated transaction + * + * Return: the outdated transaction if found + * NULL if no outdated transacton can be found + * + * Requires the proc->inner_lock to be held. + */ +static struct binder_transaction * +binder_find_outdated_transaction_ilocked(struct binder_transaction *t, + struct list_head *target_list) +{ + struct binder_work *w; + + list_for_each_entry(w, target_list, entry) { + struct binder_transaction *t_queued; + + if (w->type != BINDER_WORK_TRANSACTION) + continue; + t_queued = container_of(w, struct binder_transaction, work); + if (binder_can_update_transaction(t_queued, t)) + return t_queued; + } + return NULL; +} + /** * binder_proc_transaction() - sends a transaction to a process and wakes it up * @t: transaction to send @@ -2651,6 +2725,7 @@ static int binder_proc_transaction(struct binder_transaction *t, struct binder_node *node = t->buffer->target_node; bool oneway = !!(t->flags & TF_ONE_WAY); bool pending_async = false; + struct binder_transaction *t_outdated = NULL; BUG_ON(!node); binder_node_lock(node); @@ -2678,12 +2753,24 @@ static int binder_proc_transaction(struct binder_transaction *t, if (!thread && !pending_async) thread = binder_select_thread_ilocked(proc); - if (thread) + if (thread) { binder_enqueue_thread_work_ilocked(thread, &t->work); - else if (!pending_async) + } else if (!pending_async) { binder_enqueue_work_ilocked(&t->work, &proc->todo); - else + } else { + if ((t->flags & TF_UPDATE_TXN) && proc->is_frozen) { + t_outdated = binder_find_outdated_transaction_ilocked(t, + &node->async_todo); + if (t_outdated) { + binder_debug(BINDER_DEBUG_TRANSACTION, + "txn %d supersedes %d\n", + t->debug_id, t_outdated->debug_id); + list_del_init(&t_outdated->work.entry); + proc->outstanding_txns--; + } + } binder_enqueue_work_ilocked(&t->work, &node->async_todo); + } if (!pending_async) binder_wakeup_thread_ilocked(proc, thread, !oneway /* sync */); @@ -2692,6 +2779,22 @@ static int binder_proc_transaction(struct binder_transaction *t, binder_inner_proc_unlock(proc); binder_node_unlock(node); + /* + * To reduce potential contention, free the outdated transaction and + * buffer after releasing the locks. + */ + if (t_outdated) { + struct binder_buffer *buffer = t_outdated->buffer; + + t_outdated->buffer = NULL; + buffer->transaction = NULL; + trace_binder_transaction_update_buffer_release(buffer); + binder_transaction_buffer_release(proc, NULL, buffer, 0, 0); + binder_alloc_free_buf(&proc->alloc, buffer); + kfree(t_outdated); + binder_stats_deleted(BINDER_STAT_TRANSACTION); + } + return 0; } @@ -6197,8 +6300,7 @@ static void print_binder_proc_stats(struct seq_file *m, print_binder_stats(m, " ", &proc->stats); } - -int binder_state_show(struct seq_file *m, void *unused) +static int state_show(struct seq_file *m, void *unused) { struct binder_proc *proc; struct binder_node *node; @@ -6237,7 +6339,7 @@ int binder_state_show(struct seq_file *m, void *unused) return 0; } -int binder_stats_show(struct seq_file *m, void *unused) +static int stats_show(struct seq_file *m, void *unused) { struct binder_proc *proc; @@ -6253,7 +6355,7 @@ int binder_stats_show(struct seq_file *m, void *unused) return 0; } -int binder_transactions_show(struct seq_file *m, void *unused) +static int transactions_show(struct seq_file *m, void *unused) { struct binder_proc *proc; @@ -6309,7 +6411,7 @@ static void print_binder_transaction_log_entry(struct seq_file *m, "\n" : " (incomplete)\n"); } -int binder_transaction_log_show(struct seq_file *m, void *unused) +static int transaction_log_show(struct seq_file *m, void *unused) { struct binder_transaction_log *log = m->private; unsigned int log_cur = atomic_read(&log->cur); @@ -6341,6 +6443,45 @@ const struct file_operations binder_fops = { .release = binder_release, }; +DEFINE_SHOW_ATTRIBUTE(state); +DEFINE_SHOW_ATTRIBUTE(stats); +DEFINE_SHOW_ATTRIBUTE(transactions); +DEFINE_SHOW_ATTRIBUTE(transaction_log); + +const struct binder_debugfs_entry binder_debugfs_entries[] = { + { + .name = "state", + .mode = 0444, + .fops = &state_fops, + .data = NULL, + }, + { + .name = "stats", + .mode = 0444, + .fops = &stats_fops, + .data = NULL, + }, + { + .name = "transactions", + .mode = 0444, + .fops = &transactions_fops, + .data = NULL, + }, + { + .name = "transaction_log", + .mode = 0444, + .fops = &transaction_log_fops, + .data = &binder_transaction_log, + }, + { + .name = "failed_transaction_log", + .mode = 0444, + .fops = &transaction_log_fops, + .data = &binder_transaction_log_failed, + }, + {} /* terminator */ +}; + static int __init init_binder_device(const char *name) { int ret; @@ -6386,36 +6527,18 @@ static int __init binder_init(void) atomic_set(&binder_transaction_log_failed.cur, ~0U); binder_debugfs_dir_entry_root = debugfs_create_dir("binder", NULL); - if (binder_debugfs_dir_entry_root) + if (binder_debugfs_dir_entry_root) { + const struct binder_debugfs_entry *db_entry; + + binder_for_each_debugfs_entry(db_entry) + debugfs_create_file(db_entry->name, + db_entry->mode, + binder_debugfs_dir_entry_root, + db_entry->data, + db_entry->fops); + binder_debugfs_dir_entry_proc = debugfs_create_dir("proc", binder_debugfs_dir_entry_root); - - if (binder_debugfs_dir_entry_root) { - debugfs_create_file("state", - 0444, - binder_debugfs_dir_entry_root, - NULL, - &binder_state_fops); - debugfs_create_file("stats", - 0444, - binder_debugfs_dir_entry_root, - NULL, - &binder_stats_fops); - debugfs_create_file("transactions", - 0444, - binder_debugfs_dir_entry_root, - NULL, - &binder_transactions_fops); - debugfs_create_file("transaction_log", - 0444, - binder_debugfs_dir_entry_root, - &binder_transaction_log, - &binder_transaction_log_fops); - debugfs_create_file("failed_transaction_log", - 0444, - binder_debugfs_dir_entry_root, - &binder_transaction_log_failed, - &binder_transaction_log_fops); } if (!IS_ENABLED(CONFIG_ANDROID_BINDERFS) && diff --git a/drivers/android/binder_internal.h b/drivers/android/binder_internal.h index 8dc0bccf8513..abe19d88c6ec 100644 --- a/drivers/android/binder_internal.h +++ b/drivers/android/binder_internal.h @@ -107,41 +107,19 @@ static inline int __init init_binderfs(void) } #endif -int binder_stats_show(struct seq_file *m, void *unused); -DEFINE_SHOW_ATTRIBUTE(binder_stats); - -int binder_state_show(struct seq_file *m, void *unused); -DEFINE_SHOW_ATTRIBUTE(binder_state); - -int binder_transactions_show(struct seq_file *m, void *unused); -DEFINE_SHOW_ATTRIBUTE(binder_transactions); - -int binder_transaction_log_show(struct seq_file *m, void *unused); -DEFINE_SHOW_ATTRIBUTE(binder_transaction_log); - -struct binder_transaction_log_entry { - int debug_id; - int debug_id_done; - int call_type; - int from_proc; - int from_thread; - int target_handle; - int to_proc; - int to_thread; - int to_node; - int data_size; - int offsets_size; - int return_error_line; - uint32_t return_error; - uint32_t return_error_param; - char context_name[BINDERFS_MAX_NAME + 1]; +struct binder_debugfs_entry { + const char *name; + umode_t mode; + const struct file_operations *fops; + void *data; }; -struct binder_transaction_log { - atomic_t cur; - bool full; - struct binder_transaction_log_entry entry[32]; -}; +extern const struct binder_debugfs_entry binder_debugfs_entries[]; + +#define binder_for_each_debugfs_entry(entry) \ + for ((entry) = binder_debugfs_entries; \ + (entry)->name; \ + (entry)++) enum binder_stat_types { BINDER_STAT_PROC, @@ -580,6 +558,4 @@ struct binder_object { }; }; -extern struct binder_transaction_log binder_transaction_log; -extern struct binder_transaction_log binder_transaction_log_failed; #endif /* _LINUX_BINDER_INTERNAL_H */ diff --git a/drivers/android/binder_trace.h b/drivers/android/binder_trace.h index 8eeccdc64724..8cc07e6a4273 100644 --- a/drivers/android/binder_trace.h +++ b/drivers/android/binder_trace.h @@ -311,6 +311,10 @@ DEFINE_EVENT(binder_buffer_class, binder_transaction_failed_buffer_release, TP_PROTO(struct binder_buffer *buffer), TP_ARGS(buffer)); +DEFINE_EVENT(binder_buffer_class, binder_transaction_update_buffer_release, + TP_PROTO(struct binder_buffer *buffer), + TP_ARGS(buffer)); + TRACE_EVENT(binder_update_page_range, TP_PROTO(struct binder_alloc *alloc, bool allocate, void __user *start, void __user *end), diff --git a/drivers/android/binderfs.c b/drivers/android/binderfs.c index 6c5e94f6cb3a..588d753a7a19 100644 --- a/drivers/android/binderfs.c +++ b/drivers/android/binderfs.c @@ -629,6 +629,7 @@ static int init_binder_features(struct super_block *sb) static int init_binder_logs(struct super_block *sb) { struct dentry *binder_logs_root_dir, *dentry, *proc_log_dir; + const struct binder_debugfs_entry *db_entry; struct binderfs_info *info; int ret = 0; @@ -639,43 +640,15 @@ static int init_binder_logs(struct super_block *sb) goto out; } - dentry = binderfs_create_file(binder_logs_root_dir, "stats", - &binder_stats_fops, NULL); - if (IS_ERR(dentry)) { - ret = PTR_ERR(dentry); - goto out; - } - - dentry = binderfs_create_file(binder_logs_root_dir, "state", - &binder_state_fops, NULL); - if (IS_ERR(dentry)) { - ret = PTR_ERR(dentry); - goto out; - } - - dentry = binderfs_create_file(binder_logs_root_dir, "transactions", - &binder_transactions_fops, NULL); - if (IS_ERR(dentry)) { - ret = PTR_ERR(dentry); - goto out; - } - - dentry = binderfs_create_file(binder_logs_root_dir, - "transaction_log", - &binder_transaction_log_fops, - &binder_transaction_log); - if (IS_ERR(dentry)) { - ret = PTR_ERR(dentry); - goto out; - } - - dentry = binderfs_create_file(binder_logs_root_dir, - "failed_transaction_log", - &binder_transaction_log_fops, - &binder_transaction_log_failed); - if (IS_ERR(dentry)) { - ret = PTR_ERR(dentry); - goto out; + binder_for_each_debugfs_entry(db_entry) { + dentry = binderfs_create_file(binder_logs_root_dir, + db_entry->name, + db_entry->fops, + db_entry->data); + if (IS_ERR(dentry)) { + ret = PTR_ERR(dentry); + goto out; + } } proc_log_dir = binderfs_create_dir(binder_logs_root_dir, "proc"); diff --git a/drivers/bus/mhi/ep/main.c b/drivers/bus/mhi/ep/main.c index 40109a79017a..1dc8a3557a46 100644 --- a/drivers/bus/mhi/ep/main.c +++ b/drivers/bus/mhi/ep/main.c @@ -1242,9 +1242,13 @@ static int mhi_ep_create_device(struct mhi_ep_cntrl *mhi_cntrl, u32 ch_id) /* Channel name is same for both UL and DL */ mhi_dev->name = mhi_chan->name; - dev_set_name(&mhi_dev->dev, "%s_%s", + ret = dev_set_name(&mhi_dev->dev, "%s_%s", dev_name(&mhi_cntrl->mhi_dev->dev), mhi_dev->name); + if (ret) { + put_device(&mhi_dev->dev); + return ret; + } ret = device_add(&mhi_dev->dev); if (ret) @@ -1408,7 +1412,10 @@ int mhi_ep_register_controller(struct mhi_ep_cntrl *mhi_cntrl, goto err_free_irq; } - dev_set_name(&mhi_dev->dev, "mhi_ep%u", mhi_cntrl->index); + ret = dev_set_name(&mhi_dev->dev, "mhi_ep%u", mhi_cntrl->index); + if (ret) + goto err_put_dev; + mhi_dev->name = dev_name(&mhi_dev->dev); mhi_cntrl->mhi_dev = mhi_dev; diff --git a/drivers/bus/mhi/host/init.c b/drivers/bus/mhi/host/init.c index c137d55ccfa0..bf672de35131 100644 --- a/drivers/bus/mhi/host/init.c +++ b/drivers/bus/mhi/host/init.c @@ -178,6 +178,12 @@ int mhi_init_irq_setup(struct mhi_controller *mhi_cntrl) "bhi", mhi_cntrl); if (ret) return ret; + /* + * IRQs should be enabled during mhi_async_power_up(), so disable them explicitly here. + * Due to the use of IRQF_SHARED flag as default while requesting IRQs, we assume that + * IRQ_NOAUTOEN is not applicable. + */ + disable_irq(mhi_cntrl->irq[0]); for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { if (mhi_event->offload_ev) @@ -199,6 +205,8 @@ int mhi_init_irq_setup(struct mhi_controller *mhi_cntrl) mhi_cntrl->irq[mhi_event->irq], i); goto error_request; } + + disable_irq(mhi_cntrl->irq[mhi_event->irq]); } return 0; @@ -978,12 +986,16 @@ int mhi_register_controller(struct mhi_controller *mhi_cntrl, goto err_destroy_wq; } + ret = mhi_init_irq_setup(mhi_cntrl); + if (ret) + goto err_ida_free; + /* Register controller with MHI bus */ mhi_dev = mhi_alloc_device(mhi_cntrl); if (IS_ERR(mhi_dev)) { dev_err(mhi_cntrl->cntrl_dev, "Failed to allocate MHI device\n"); ret = PTR_ERR(mhi_dev); - goto err_ida_free; + goto error_setup_irq; } mhi_dev->dev_type = MHI_DEVICE_CONTROLLER; @@ -1006,6 +1018,8 @@ int mhi_register_controller(struct mhi_controller *mhi_cntrl, err_release_dev: put_device(&mhi_dev->dev); +error_setup_irq: + mhi_deinit_free_irq(mhi_cntrl); err_ida_free: ida_free(&mhi_controller_ida, mhi_cntrl->index); err_destroy_wq: @@ -1026,6 +1040,7 @@ void mhi_unregister_controller(struct mhi_controller *mhi_cntrl) struct mhi_chan *mhi_chan = mhi_cntrl->mhi_chan; unsigned int i; + mhi_deinit_free_irq(mhi_cntrl); mhi_destroy_debugfs(mhi_cntrl); destroy_workqueue(mhi_cntrl->hiprio_wq); diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c index 841626727f6b..9e545f2a5a26 100644 --- a/drivers/bus/mhi/host/pci_generic.c +++ b/drivers/bus/mhi/host/pci_generic.c @@ -557,6 +557,8 @@ static const struct pci_device_id mhi_pci_id_table[] = { .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, + { PCI_DEVICE(0x1eac, 0x2001), /* EM120R-GL for FCCL (sdx24) */ + .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, /* T99W175 (sdx55), Both for eSIM and Non-eSIM */ { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab), .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info }, @@ -569,6 +571,9 @@ static const struct pci_device_id mhi_pci_id_table[] = { /* T99W175 (sdx55), Based on Qualcomm new baseline */ { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0bf), .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info }, + /* T99W175 (sdx55) */ + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0c3), + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info }, /* T99W368 (sdx65) */ { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d8), .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx65_info }, @@ -578,6 +583,9 @@ static const struct pci_device_id mhi_pci_id_table[] = { /* MV31-W (Cinterion) */ { PCI_DEVICE(0x1269, 0x00b3), .driver_data = (kernel_ulong_t) &mhi_mv31_info }, + /* MV31-W (Cinterion), based on new baseline */ + { PCI_DEVICE(0x1269, 0x00b4), + .driver_data = (kernel_ulong_t) &mhi_mv31_info }, /* MV32-WA (Cinterion) */ { PCI_DEVICE(0x1269, 0x00ba), .driver_data = (kernel_ulong_t) &mhi_mv32_info }, diff --git a/drivers/bus/mhi/host/pm.c b/drivers/bus/mhi/host/pm.c index dc2e8ff3bff2..4a42186ff111 100644 --- a/drivers/bus/mhi/host/pm.c +++ b/drivers/bus/mhi/host/pm.c @@ -500,7 +500,7 @@ static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl) for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { if (mhi_event->offload_ev) continue; - free_irq(mhi_cntrl->irq[mhi_event->irq], mhi_event); + disable_irq(mhi_cntrl->irq[mhi_event->irq]); tasklet_kill(&mhi_event->task); } @@ -1060,12 +1060,13 @@ static void mhi_deassert_dev_wake(struct mhi_controller *mhi_cntrl, int mhi_async_power_up(struct mhi_controller *mhi_cntrl) { + struct mhi_event *mhi_event = mhi_cntrl->mhi_event; enum mhi_state state; enum mhi_ee_type current_ee; enum dev_st_transition next_state; struct device *dev = &mhi_cntrl->mhi_dev->dev; u32 interval_us = 25000; /* poll register field every 25 milliseconds */ - int ret; + int ret, i; dev_info(dev, "Requested to power ON\n"); @@ -1117,9 +1118,15 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl) mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0); } - ret = mhi_init_irq_setup(mhi_cntrl); - if (ret) - goto error_exit; + /* IRQs have been requested during probe, so we just need to enable them. */ + enable_irq(mhi_cntrl->irq[0]); + + for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { + if (mhi_event->offload_ev) + continue; + + enable_irq(mhi_cntrl->irq[mhi_event->irq]); + } /* Transition to next state */ next_state = MHI_IN_PBL(current_ee) ? @@ -1182,7 +1189,7 @@ void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful) /* Wait for shutdown to complete */ flush_work(&mhi_cntrl->st_worker); - free_irq(mhi_cntrl->irq[0], mhi_cntrl); + disable_irq(mhi_cntrl->irq[0]); } EXPORT_SYMBOL_GPL(mhi_power_down); diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c index db612045616f..9711e4c827a3 100644 --- a/drivers/bus/mvebu-mbus.c +++ b/drivers/bus/mvebu-mbus.c @@ -25,8 +25,8 @@ * * - Reads out the SDRAM address decoding windows at initialization * time, and fills the mvebu_mbus_dram_info structure with these - * informations. The exported function mv_mbus_dram_info() allow - * device drivers to get those informations related to the SDRAM + * information. The exported function mv_mbus_dram_info() allow + * device drivers to get those information related to the SDRAM * address decoding windows. This is because devices also have their * own windows (configured through registers that are part of each * device register space), and therefore the drivers for Marvell @@ -123,7 +123,7 @@ struct mvebu_mbus_soc_data { }; /* - * Used to store the state of one MBus window accross suspend/resume. + * Used to store the state of one MBus window across suspend/resume. */ struct mvebu_mbus_win_data { u32 ctrl; diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig index 30192e123e5f..0f378d29dab0 100644 --- a/drivers/char/Kconfig +++ b/drivers/char/Kconfig @@ -247,11 +247,6 @@ config SONYPI To compile this driver as a module, choose M here: the module will be called sonypi. -config GPIO_TB0219 - tristate "TANBAC TB0219 GPIO support" - depends on TANBAC_TB022X - select GPIO_VR41XX - source "drivers/char/pcmcia/Kconfig" config MWAVE diff --git a/drivers/char/Makefile b/drivers/char/Makefile index 264eb398fdd4..1b35d1724565 100644 --- a/drivers/char/Makefile +++ b/drivers/char/Makefile @@ -31,7 +31,6 @@ obj-$(CONFIG_NWFLASH) += nwflash.o obj-$(CONFIG_SCx200_GPIO) += scx200_gpio.o obj-$(CONFIG_PC8736x_GPIO) += pc8736x_gpio.o obj-$(CONFIG_NSC_GPIO) += nsc_gpio.o -obj-$(CONFIG_GPIO_TB0219) += tb0219.o obj-$(CONFIG_TELCLOCK) += tlclk.o obj-$(CONFIG_MWAVE) += mwave/ diff --git a/drivers/char/apm-emulation.c b/drivers/char/apm-emulation.c index 230cf852fa9c..e795390b070f 100644 --- a/drivers/char/apm-emulation.c +++ b/drivers/char/apm-emulation.c @@ -544,7 +544,7 @@ static int apm_suspend_notifier(struct notifier_block *nb, wake_up_interruptible(&apm_waitqueue); /* - * Wait for the the suspend_acks_pending variable to drop to + * Wait for the suspend_acks_pending variable to drop to * zero, meaning everybody acked the suspend event (or the * process was killed.) * diff --git a/drivers/char/random.c b/drivers/char/random.c index d44832e9e709..79d7d4e4e582 100644 --- a/drivers/char/random.c +++ b/drivers/char/random.c @@ -763,8 +763,8 @@ static int random_pm_notification(struct notifier_block *nb, unsigned long actio spin_unlock_irqrestore(&input_pool.lock, flags); if (crng_ready() && (action == PM_RESTORE_PREPARE || - (action == PM_POST_SUSPEND && - !IS_ENABLED(CONFIG_PM_AUTOSLEEP) && !IS_ENABLED(CONFIG_ANDROID)))) { + (action == PM_POST_SUSPEND && !IS_ENABLED(CONFIG_PM_AUTOSLEEP) && + !IS_ENABLED(CONFIG_PM_USERSPACE_AUTOSLEEP)))) { crng_reseed(); pr_notice("crng reseeded on system resumption\n"); } diff --git a/drivers/char/tb0219.c b/drivers/char/tb0219.c deleted file mode 100644 index 1f36be14978f..000000000000 --- a/drivers/char/tb0219.c +++ /dev/null @@ -1,359 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Driver for TANBAC TB0219 base board. - * - * Copyright (C) 2005 Yoichi Yuasa - */ -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -MODULE_AUTHOR("Yoichi Yuasa "); -MODULE_DESCRIPTION("TANBAC TB0219 base board driver"); -MODULE_LICENSE("GPL"); - -static int major; /* default is dynamic major device number */ -module_param(major, int, 0); -MODULE_PARM_DESC(major, "Major device number"); - -static void (*old_machine_restart)(char *command); -static void __iomem *tb0219_base; -static DEFINE_SPINLOCK(tb0219_lock); - -#define tb0219_read(offset) readw(tb0219_base + (offset)) -#define tb0219_write(offset, value) writew((value), tb0219_base + (offset)) - -#define TB0219_START 0x0a000000UL -#define TB0219_SIZE 0x20UL - -#define TB0219_LED 0x00 -#define TB0219_GPIO_INPUT 0x02 -#define TB0219_GPIO_OUTPUT 0x04 -#define TB0219_DIP_SWITCH 0x06 -#define TB0219_MISC 0x08 -#define TB0219_RESET 0x0e -#define TB0219_PCI_SLOT1_IRQ_STATUS 0x10 -#define TB0219_PCI_SLOT2_IRQ_STATUS 0x12 -#define TB0219_PCI_SLOT3_IRQ_STATUS 0x14 - -typedef enum { - TYPE_LED, - TYPE_GPIO_OUTPUT, -} tb0219_type_t; - -/* - * Minor device number - * 0 = 7 segment LED - * - * 16 = GPIO IN 0 - * 17 = GPIO IN 1 - * 18 = GPIO IN 2 - * 19 = GPIO IN 3 - * 20 = GPIO IN 4 - * 21 = GPIO IN 5 - * 22 = GPIO IN 6 - * 23 = GPIO IN 7 - * - * 32 = GPIO OUT 0 - * 33 = GPIO OUT 1 - * 34 = GPIO OUT 2 - * 35 = GPIO OUT 3 - * 36 = GPIO OUT 4 - * 37 = GPIO OUT 5 - * 38 = GPIO OUT 6 - * 39 = GPIO OUT 7 - * - * 48 = DIP switch 1 - * 49 = DIP switch 2 - * 50 = DIP switch 3 - * 51 = DIP switch 4 - * 52 = DIP switch 5 - * 53 = DIP switch 6 - * 54 = DIP switch 7 - * 55 = DIP switch 8 - */ - -static inline char get_led(void) -{ - return (char)tb0219_read(TB0219_LED); -} - -static inline char get_gpio_input_pin(unsigned int pin) -{ - uint16_t values; - - values = tb0219_read(TB0219_GPIO_INPUT); - if (values & (1 << pin)) - return '1'; - - return '0'; -} - -static inline char get_gpio_output_pin(unsigned int pin) -{ - uint16_t values; - - values = tb0219_read(TB0219_GPIO_OUTPUT); - if (values & (1 << pin)) - return '1'; - - return '0'; -} - -static inline char get_dip_switch(unsigned int pin) -{ - uint16_t values; - - values = tb0219_read(TB0219_DIP_SWITCH); - if (values & (1 << pin)) - return '1'; - - return '0'; -} - -static inline int set_led(char command) -{ - tb0219_write(TB0219_LED, command); - - return 0; -} - -static inline int set_gpio_output_pin(unsigned int pin, char command) -{ - unsigned long flags; - uint16_t value; - - if (command != '0' && command != '1') - return -EINVAL; - - spin_lock_irqsave(&tb0219_lock, flags); - value = tb0219_read(TB0219_GPIO_OUTPUT); - if (command == '0') - value &= ~(1 << pin); - else - value |= 1 << pin; - tb0219_write(TB0219_GPIO_OUTPUT, value); - spin_unlock_irqrestore(&tb0219_lock, flags); - - return 0; - -} - -static ssize_t tanbac_tb0219_read(struct file *file, char __user *buf, size_t len, - loff_t *ppos) -{ - unsigned int minor; - char value; - - minor = iminor(file_inode(file)); - switch (minor) { - case 0: - value = get_led(); - break; - case 16 ... 23: - value = get_gpio_input_pin(minor - 16); - break; - case 32 ... 39: - value = get_gpio_output_pin(minor - 32); - break; - case 48 ... 55: - value = get_dip_switch(minor - 48); - break; - default: - return -EBADF; - } - - if (len <= 0) - return -EFAULT; - - if (put_user(value, buf)) - return -EFAULT; - - return 1; -} - -static ssize_t tanbac_tb0219_write(struct file *file, const char __user *data, - size_t len, loff_t *ppos) -{ - unsigned int minor; - tb0219_type_t type; - size_t i; - int retval = 0; - char c; - - minor = iminor(file_inode(file)); - switch (minor) { - case 0: - type = TYPE_LED; - break; - case 32 ... 39: - type = TYPE_GPIO_OUTPUT; - break; - default: - return -EBADF; - } - - for (i = 0; i < len; i++) { - if (get_user(c, data + i)) - return -EFAULT; - - switch (type) { - case TYPE_LED: - retval = set_led(c); - break; - case TYPE_GPIO_OUTPUT: - retval = set_gpio_output_pin(minor - 32, c); - break; - } - - if (retval < 0) - break; - } - - return i; -} - -static int tanbac_tb0219_open(struct inode *inode, struct file *file) -{ - unsigned int minor; - - minor = iminor(inode); - switch (minor) { - case 0: - case 16 ... 23: - case 32 ... 39: - case 48 ... 55: - return stream_open(inode, file); - default: - break; - } - - return -EBADF; -} - -static int tanbac_tb0219_release(struct inode *inode, struct file *file) -{ - return 0; -} - -static const struct file_operations tb0219_fops = { - .owner = THIS_MODULE, - .read = tanbac_tb0219_read, - .write = tanbac_tb0219_write, - .open = tanbac_tb0219_open, - .release = tanbac_tb0219_release, - .llseek = no_llseek, -}; - -static void tb0219_restart(char *command) -{ - tb0219_write(TB0219_RESET, 0); -} - -static void tb0219_pci_irq_init(void) -{ - /* PCI Slot 1 */ - vr41xx_set_irq_trigger(TB0219_PCI_SLOT1_PIN, IRQ_TRIGGER_LEVEL, IRQ_SIGNAL_THROUGH); - vr41xx_set_irq_level(TB0219_PCI_SLOT1_PIN, IRQ_LEVEL_LOW); - - /* PCI Slot 2 */ - vr41xx_set_irq_trigger(TB0219_PCI_SLOT2_PIN, IRQ_TRIGGER_LEVEL, IRQ_SIGNAL_THROUGH); - vr41xx_set_irq_level(TB0219_PCI_SLOT2_PIN, IRQ_LEVEL_LOW); - - /* PCI Slot 3 */ - vr41xx_set_irq_trigger(TB0219_PCI_SLOT3_PIN, IRQ_TRIGGER_LEVEL, IRQ_SIGNAL_THROUGH); - vr41xx_set_irq_level(TB0219_PCI_SLOT3_PIN, IRQ_LEVEL_LOW); -} - -static int tb0219_probe(struct platform_device *dev) -{ - int retval; - - if (request_mem_region(TB0219_START, TB0219_SIZE, "TB0219") == NULL) - return -EBUSY; - - tb0219_base = ioremap(TB0219_START, TB0219_SIZE); - if (tb0219_base == NULL) { - release_mem_region(TB0219_START, TB0219_SIZE); - return -ENOMEM; - } - - retval = register_chrdev(major, "TB0219", &tb0219_fops); - if (retval < 0) { - iounmap(tb0219_base); - tb0219_base = NULL; - release_mem_region(TB0219_START, TB0219_SIZE); - return retval; - } - - old_machine_restart = _machine_restart; - _machine_restart = tb0219_restart; - - tb0219_pci_irq_init(); - - if (major == 0) { - major = retval; - printk(KERN_INFO "TB0219: major number %d\n", major); - } - - return 0; -} - -static int tb0219_remove(struct platform_device *dev) -{ - _machine_restart = old_machine_restart; - - iounmap(tb0219_base); - tb0219_base = NULL; - - release_mem_region(TB0219_START, TB0219_SIZE); - - return 0; -} - -static struct platform_device *tb0219_platform_device; - -static struct platform_driver tb0219_device_driver = { - .probe = tb0219_probe, - .remove = tb0219_remove, - .driver = { - .name = "TB0219", - }, -}; - -static int __init tanbac_tb0219_init(void) -{ - int retval; - - tb0219_platform_device = platform_device_alloc("TB0219", -1); - if (!tb0219_platform_device) - return -ENOMEM; - - retval = platform_device_add(tb0219_platform_device); - if (retval < 0) { - platform_device_put(tb0219_platform_device); - return retval; - } - - retval = platform_driver_register(&tb0219_device_driver); - if (retval < 0) - platform_device_unregister(tb0219_platform_device); - - return retval; -} - -static void __exit tanbac_tb0219_exit(void) -{ - platform_driver_unregister(&tb0219_device_driver); - platform_device_unregister(tb0219_platform_device); -} - -module_init(tanbac_tb0219_init); -module_exit(tanbac_tb0219_exit); diff --git a/drivers/counter/104-quad-8.c b/drivers/counter/104-quad-8.c index a17e51d65aca..62c2b7ac4339 100644 --- a/drivers/counter/104-quad-8.c +++ b/drivers/counter/104-quad-8.c @@ -33,6 +33,36 @@ MODULE_PARM_DESC(irq, "ACCES 104-QUAD-8 interrupt line numbers"); #define QUAD8_NUM_COUNTERS 8 +/** + * struct channel_reg - channel register structure + * @data: Count data + * @control: Channel flags and control + */ +struct channel_reg { + u8 data; + u8 control; +}; + +/** + * struct quad8_reg - device register structure + * @channel: quadrature counter data and control + * @interrupt_status: channel interrupt status + * @channel_oper: enable/reset counters and interrupt functions + * @index_interrupt: enable channel interrupts + * @reserved: reserved for Factory Use + * @index_input_levels: index signal logical input level + * @cable_status: differential encoder cable status + */ +struct quad8_reg { + struct channel_reg channel[QUAD8_NUM_COUNTERS]; + u8 interrupt_status; + u8 channel_oper; + u8 index_interrupt; + u8 reserved[3]; + u8 index_input_levels; + u8 cable_status; +}; + /** * struct quad8 - device private data structure * @lock: lock to prevent clobbering device states during R/W ops @@ -48,7 +78,7 @@ MODULE_PARM_DESC(irq, "ACCES 104-QUAD-8 interrupt line numbers"); * @synchronous_mode: array of index function synchronous mode configurations * @index_polarity: array of index function polarity configurations * @cable_fault_enable: differential encoder cable status enable configurations - * @base: base port address of the device + * @reg: I/O address offset for the device registers */ struct quad8 { spinlock_t lock; @@ -63,14 +93,9 @@ struct quad8 { unsigned int synchronous_mode[QUAD8_NUM_COUNTERS]; unsigned int index_polarity[QUAD8_NUM_COUNTERS]; unsigned int cable_fault_enable; - unsigned int base; + struct quad8_reg __iomem *reg; }; -#define QUAD8_REG_INTERRUPT_STATUS 0x10 -#define QUAD8_REG_CHAN_OP 0x11 -#define QUAD8_REG_INDEX_INTERRUPT 0x12 -#define QUAD8_REG_INDEX_INPUT_LEVELS 0x16 -#define QUAD8_DIFF_ENCODER_CABLE_STATUS 0x17 /* Borrow Toggle flip-flop */ #define QUAD8_FLAG_BT BIT(0) /* Carry Toggle flip-flop */ @@ -118,8 +143,7 @@ static int quad8_signal_read(struct counter_device *counter, if (signal->id < 16) return -EINVAL; - state = inb(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS) - & BIT(signal->id - 16); + state = ioread8(&priv->reg->index_input_levels) & BIT(signal->id - 16); *level = (state) ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW; @@ -130,14 +154,14 @@ static int quad8_count_read(struct counter_device *counter, struct counter_count *count, u64 *val) { struct quad8 *const priv = counter_priv(counter); - const int base_offset = priv->base + 2 * count->id; + struct channel_reg __iomem *const chan = priv->reg->channel + count->id; unsigned int flags; unsigned int borrow; unsigned int carry; unsigned long irqflags; int i; - flags = inb(base_offset + 1); + flags = ioread8(&chan->control); borrow = flags & QUAD8_FLAG_BT; carry = !!(flags & QUAD8_FLAG_CT); @@ -147,11 +171,11 @@ static int quad8_count_read(struct counter_device *counter, spin_lock_irqsave(&priv->lock, irqflags); /* Reset Byte Pointer; transfer Counter to Output Latch */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT, - base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT, + &chan->control); for (i = 0; i < 3; i++) - *val |= (unsigned long)inb(base_offset) << (8 * i); + *val |= (unsigned long)ioread8(&chan->data) << (8 * i); spin_unlock_irqrestore(&priv->lock, irqflags); @@ -162,7 +186,7 @@ static int quad8_count_write(struct counter_device *counter, struct counter_count *count, u64 val) { struct quad8 *const priv = counter_priv(counter); - const int base_offset = priv->base + 2 * count->id; + struct channel_reg __iomem *const chan = priv->reg->channel + count->id; unsigned long irqflags; int i; @@ -173,27 +197,27 @@ static int quad8_count_write(struct counter_device *counter, spin_lock_irqsave(&priv->lock, irqflags); /* Reset Byte Pointer */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control); /* Counter can only be set via Preset Register */ for (i = 0; i < 3; i++) - outb(val >> (8 * i), base_offset); + iowrite8(val >> (8 * i), &chan->data); /* Transfer Preset Register to Counter */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, &chan->control); /* Reset Byte Pointer */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control); /* Set Preset Register back to original value */ val = priv->preset[count->id]; for (i = 0; i < 3; i++) - outb(val >> (8 * i), base_offset); + iowrite8(val >> (8 * i), &chan->data); /* Reset Borrow, Carry, Compare, and Sign flags */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, &chan->control); /* Reset Error flag */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, &chan->control); spin_unlock_irqrestore(&priv->lock, irqflags); @@ -246,7 +270,7 @@ static int quad8_function_write(struct counter_device *counter, unsigned int *const quadrature_mode = priv->quadrature_mode + id; unsigned int *const scale = priv->quadrature_scale + id; unsigned int *const synchronous_mode = priv->synchronous_mode + id; - const int base_offset = priv->base + 2 * id + 1; + u8 __iomem *const control = &priv->reg->channel[id].control; unsigned long irqflags; unsigned int mode_cfg; unsigned int idr_cfg; @@ -266,7 +290,7 @@ static int quad8_function_write(struct counter_device *counter, if (*synchronous_mode) { *synchronous_mode = 0; /* Disable synchronous function mode */ - outb(QUAD8_CTR_IDR | idr_cfg, base_offset); + iowrite8(QUAD8_CTR_IDR | idr_cfg, control); } } else { *quadrature_mode = 1; @@ -292,7 +316,7 @@ static int quad8_function_write(struct counter_device *counter, } /* Load mode configuration to Counter Mode Register */ - outb(QUAD8_CTR_CMR | mode_cfg, base_offset); + iowrite8(QUAD8_CTR_CMR | mode_cfg, control); spin_unlock_irqrestore(&priv->lock, irqflags); @@ -305,10 +329,10 @@ static int quad8_direction_read(struct counter_device *counter, { const struct quad8 *const priv = counter_priv(counter); unsigned int ud_flag; - const unsigned int flag_addr = priv->base + 2 * count->id + 1; + u8 __iomem *const flag_addr = &priv->reg->channel[count->id].control; /* U/D flag: nonzero = up, zero = down */ - ud_flag = inb(flag_addr) & QUAD8_FLAG_UD; + ud_flag = ioread8(flag_addr) & QUAD8_FLAG_UD; *direction = (ud_flag) ? COUNTER_COUNT_DIRECTION_FORWARD : COUNTER_COUNT_DIRECTION_BACKWARD; @@ -402,7 +426,6 @@ static int quad8_events_configure(struct counter_device *counter) struct counter_event_node *event_node; unsigned int next_irq_trigger; unsigned long ior_cfg; - unsigned long base_offset; spin_lock_irqsave(&priv->lock, irqflags); @@ -437,14 +460,14 @@ static int quad8_events_configure(struct counter_device *counter) ior_cfg = priv->ab_enable[event_node->channel] | priv->preset_enable[event_node->channel] << 1 | priv->irq_trigger[event_node->channel] << 3; - base_offset = priv->base + 2 * event_node->channel + 1; - outb(QUAD8_CTR_IOR | ior_cfg, base_offset); + iowrite8(QUAD8_CTR_IOR | ior_cfg, + &priv->reg->channel[event_node->channel].control); /* Enable IRQ line */ irq_enabled |= BIT(event_node->channel); } - outb(irq_enabled, priv->base + QUAD8_REG_INDEX_INTERRUPT); + iowrite8(irq_enabled, &priv->reg->index_interrupt); spin_unlock_irqrestore(&priv->lock, irqflags); @@ -508,7 +531,7 @@ static int quad8_index_polarity_set(struct counter_device *counter, { struct quad8 *const priv = counter_priv(counter); const size_t channel_id = signal->id - 16; - const int base_offset = priv->base + 2 * channel_id + 1; + u8 __iomem *const control = &priv->reg->channel[channel_id].control; unsigned long irqflags; unsigned int idr_cfg = index_polarity << 1; @@ -519,7 +542,7 @@ static int quad8_index_polarity_set(struct counter_device *counter, priv->index_polarity[channel_id] = index_polarity; /* Load Index Control configuration to Index Control Register */ - outb(QUAD8_CTR_IDR | idr_cfg, base_offset); + iowrite8(QUAD8_CTR_IDR | idr_cfg, control); spin_unlock_irqrestore(&priv->lock, irqflags); @@ -549,7 +572,7 @@ static int quad8_synchronous_mode_set(struct counter_device *counter, { struct quad8 *const priv = counter_priv(counter); const size_t channel_id = signal->id - 16; - const int base_offset = priv->base + 2 * channel_id + 1; + u8 __iomem *const control = &priv->reg->channel[channel_id].control; unsigned long irqflags; unsigned int idr_cfg = synchronous_mode; @@ -566,7 +589,7 @@ static int quad8_synchronous_mode_set(struct counter_device *counter, priv->synchronous_mode[channel_id] = synchronous_mode; /* Load Index Control configuration to Index Control Register */ - outb(QUAD8_CTR_IDR | idr_cfg, base_offset); + iowrite8(QUAD8_CTR_IDR | idr_cfg, control); spin_unlock_irqrestore(&priv->lock, irqflags); @@ -614,7 +637,7 @@ static int quad8_count_mode_write(struct counter_device *counter, struct quad8 *const priv = counter_priv(counter); unsigned int count_mode; unsigned int mode_cfg; - const int base_offset = priv->base + 2 * count->id + 1; + u8 __iomem *const control = &priv->reg->channel[count->id].control; unsigned long irqflags; /* Map Generic Counter count mode to 104-QUAD-8 count mode */ @@ -648,7 +671,7 @@ static int quad8_count_mode_write(struct counter_device *counter, mode_cfg |= (priv->quadrature_scale[count->id] + 1) << 3; /* Load mode configuration to Counter Mode Register */ - outb(QUAD8_CTR_CMR | mode_cfg, base_offset); + iowrite8(QUAD8_CTR_CMR | mode_cfg, control); spin_unlock_irqrestore(&priv->lock, irqflags); @@ -669,7 +692,7 @@ static int quad8_count_enable_write(struct counter_device *counter, struct counter_count *count, u8 enable) { struct quad8 *const priv = counter_priv(counter); - const int base_offset = priv->base + 2 * count->id; + u8 __iomem *const control = &priv->reg->channel[count->id].control; unsigned long irqflags; unsigned int ior_cfg; @@ -681,7 +704,7 @@ static int quad8_count_enable_write(struct counter_device *counter, priv->irq_trigger[count->id] << 3; /* Load I/O control configuration */ - outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1); + iowrite8(QUAD8_CTR_IOR | ior_cfg, control); spin_unlock_irqrestore(&priv->lock, irqflags); @@ -697,9 +720,9 @@ static int quad8_error_noise_get(struct counter_device *counter, struct counter_count *count, u32 *noise_error) { const struct quad8 *const priv = counter_priv(counter); - const int base_offset = priv->base + 2 * count->id + 1; + u8 __iomem *const flag_addr = &priv->reg->channel[count->id].control; - *noise_error = !!(inb(base_offset) & QUAD8_FLAG_E); + *noise_error = !!(ioread8(flag_addr) & QUAD8_FLAG_E); return 0; } @@ -717,17 +740,17 @@ static int quad8_count_preset_read(struct counter_device *counter, static void quad8_preset_register_set(struct quad8 *const priv, const int id, const unsigned int preset) { - const unsigned int base_offset = priv->base + 2 * id; + struct channel_reg __iomem *const chan = priv->reg->channel + id; int i; priv->preset[id] = preset; /* Reset Byte Pointer */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control); /* Set Preset Register */ for (i = 0; i < 3; i++) - outb(preset >> (8 * i), base_offset); + iowrite8(preset >> (8 * i), &chan->data); } static int quad8_count_preset_write(struct counter_device *counter, @@ -816,7 +839,7 @@ static int quad8_count_preset_enable_write(struct counter_device *counter, u8 preset_enable) { struct quad8 *const priv = counter_priv(counter); - const int base_offset = priv->base + 2 * count->id + 1; + u8 __iomem *const control = &priv->reg->channel[count->id].control; unsigned long irqflags; unsigned int ior_cfg; @@ -831,7 +854,7 @@ static int quad8_count_preset_enable_write(struct counter_device *counter, priv->irq_trigger[count->id] << 3; /* Load I/O control configuration to Input / Output Control Register */ - outb(QUAD8_CTR_IOR | ior_cfg, base_offset); + iowrite8(QUAD8_CTR_IOR | ior_cfg, control); spin_unlock_irqrestore(&priv->lock, irqflags); @@ -858,7 +881,7 @@ static int quad8_signal_cable_fault_read(struct counter_device *counter, } /* Logic 0 = cable fault */ - status = inb(priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); + status = ioread8(&priv->reg->cable_status); spin_unlock_irqrestore(&priv->lock, irqflags); @@ -899,7 +922,7 @@ static int quad8_signal_cable_fault_enable_write(struct counter_device *counter, /* Enable is active low in Differential Encoder Cable Status register */ cable_fault_enable = ~priv->cable_fault_enable; - outb(cable_fault_enable, priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); + iowrite8(cable_fault_enable, &priv->reg->cable_status); spin_unlock_irqrestore(&priv->lock, irqflags); @@ -923,7 +946,7 @@ static int quad8_signal_fck_prescaler_write(struct counter_device *counter, { struct quad8 *const priv = counter_priv(counter); const size_t channel_id = signal->id / 2; - const int base_offset = priv->base + 2 * channel_id; + struct channel_reg __iomem *const chan = priv->reg->channel + channel_id; unsigned long irqflags; spin_lock_irqsave(&priv->lock, irqflags); @@ -931,12 +954,12 @@ static int quad8_signal_fck_prescaler_write(struct counter_device *counter, priv->fck_prescaler[channel_id] = prescaler; /* Reset Byte Pointer */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control); /* Set filter clock factor */ - outb(prescaler, base_offset); - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, - base_offset + 1); + iowrite8(prescaler, &chan->data); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, + &chan->control); spin_unlock_irqrestore(&priv->lock, irqflags); @@ -1084,12 +1107,11 @@ static irqreturn_t quad8_irq_handler(int irq, void *private) { struct counter_device *counter = private; struct quad8 *const priv = counter_priv(counter); - const unsigned long base = priv->base; unsigned long irq_status; unsigned long channel; u8 event; - irq_status = inb(base + QUAD8_REG_INTERRUPT_STATUS); + irq_status = ioread8(&priv->reg->interrupt_status); if (!irq_status) return IRQ_NONE; @@ -1118,17 +1140,43 @@ static irqreturn_t quad8_irq_handler(int irq, void *private) } /* Clear pending interrupts on device */ - outb(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, base + QUAD8_REG_CHAN_OP); + iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, &priv->reg->channel_oper); return IRQ_HANDLED; } +static void quad8_init_counter(struct channel_reg __iomem *const chan) +{ + unsigned long i; + + /* Reset Byte Pointer */ + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control); + /* Reset filter clock factor */ + iowrite8(0, &chan->data); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, + &chan->control); + /* Reset Byte Pointer */ + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control); + /* Reset Preset Register */ + for (i = 0; i < 3; i++) + iowrite8(0x00, &chan->data); + /* Reset Borrow, Carry, Compare, and Sign flags */ + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, &chan->control); + /* Reset Error flag */ + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, &chan->control); + /* Binary encoding; Normal count; non-quadrature mode */ + iowrite8(QUAD8_CTR_CMR, &chan->control); + /* Disable A and B inputs; preset on index; FLG1 as Carry */ + iowrite8(QUAD8_CTR_IOR, &chan->control); + /* Disable index function; negative index polarity */ + iowrite8(QUAD8_CTR_IDR, &chan->control); +} + static int quad8_probe(struct device *dev, unsigned int id) { struct counter_device *counter; struct quad8 *priv; - int i, j; - unsigned int base_offset; + unsigned long i; int err; if (!devm_request_region(dev, base[id], QUAD8_EXTENT, dev_name(dev))) { @@ -1142,6 +1190,10 @@ static int quad8_probe(struct device *dev, unsigned int id) return -ENOMEM; priv = counter_priv(counter); + priv->reg = devm_ioport_map(dev, base[id], QUAD8_EXTENT); + if (!priv->reg) + return -ENOMEM; + /* Initialize Counter device and driver data */ counter->name = dev_name(dev); counter->parent = dev; @@ -1150,43 +1202,20 @@ static int quad8_probe(struct device *dev, unsigned int id) counter->num_counts = ARRAY_SIZE(quad8_counts); counter->signals = quad8_signals; counter->num_signals = ARRAY_SIZE(quad8_signals); - priv->base = base[id]; spin_lock_init(&priv->lock); /* Reset Index/Interrupt Register */ - outb(0x00, base[id] + QUAD8_REG_INDEX_INTERRUPT); + iowrite8(0x00, &priv->reg->index_interrupt); /* Reset all counters and disable interrupt function */ - outb(QUAD8_CHAN_OP_RESET_COUNTERS, base[id] + QUAD8_REG_CHAN_OP); + iowrite8(QUAD8_CHAN_OP_RESET_COUNTERS, &priv->reg->channel_oper); /* Set initial configuration for all counters */ - for (i = 0; i < QUAD8_NUM_COUNTERS; i++) { - base_offset = base[id] + 2 * i; - /* Reset Byte Pointer */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); - /* Reset filter clock factor */ - outb(0, base_offset); - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, - base_offset + 1); - /* Reset Byte Pointer */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); - /* Reset Preset Register */ - for (j = 0; j < 3; j++) - outb(0x00, base_offset); - /* Reset Borrow, Carry, Compare, and Sign flags */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1); - /* Reset Error flag */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); - /* Binary encoding; Normal count; non-quadrature mode */ - outb(QUAD8_CTR_CMR, base_offset + 1); - /* Disable A and B inputs; preset on index; FLG1 as Carry */ - outb(QUAD8_CTR_IOR, base_offset + 1); - /* Disable index function; negative index polarity */ - outb(QUAD8_CTR_IDR, base_offset + 1); - } + for (i = 0; i < QUAD8_NUM_COUNTERS; i++) + quad8_init_counter(priv->reg->channel + i); /* Disable Differential Encoder Cable Status for all channels */ - outb(0xFF, base[id] + QUAD8_DIFF_ENCODER_CABLE_STATUS); + iowrite8(0xFF, &priv->reg->cable_status); /* Enable all counters and enable interrupt function */ - outb(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, base[id] + QUAD8_REG_CHAN_OP); + iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, &priv->reg->channel_oper); err = devm_request_irq(&counter->dev, irq[id], quad8_irq_handler, IRQF_SHARED, counter->name, counter); diff --git a/drivers/devfreq/imx-bus.c b/drivers/devfreq/imx-bus.c index f87067fc574d..a727067980fb 100644 --- a/drivers/devfreq/imx-bus.c +++ b/drivers/devfreq/imx-bus.c @@ -145,6 +145,7 @@ static const struct of_device_id imx_bus_of_match[] = { { .compatible = "fsl,imx8mq-noc", .data = "imx8mq-interconnect", }, { .compatible = "fsl,imx8mm-noc", .data = "imx8mm-interconnect", }, { .compatible = "fsl,imx8mn-noc", .data = "imx8mn-interconnect", }, + { .compatible = "fsl,imx8mp-noc", .data = "imx8mp-interconnect", }, { .compatible = "fsl,imx8m-noc", }, { .compatible = "fsl,imx8m-nic", }, { /* sentinel */ }, diff --git a/drivers/extcon/extcon-fsa9480.c b/drivers/extcon/extcon-fsa9480.c index 08bdedbcdb0d..7cff66c29907 100644 --- a/drivers/extcon/extcon-fsa9480.c +++ b/drivers/extcon/extcon-fsa9480.c @@ -324,11 +324,6 @@ static int fsa9480_probe(struct i2c_client *client, return 0; } -static int fsa9480_remove(struct i2c_client *client) -{ - return 0; -} - #ifdef CONFIG_PM_SLEEP static int fsa9480_suspend(struct device *dev) { @@ -376,7 +371,6 @@ static struct i2c_driver fsa9480_i2c_driver = { .of_match_table = fsa9480_of_match, }, .probe = fsa9480_probe, - .remove = fsa9480_remove, .id_table = fsa9480_id, }; diff --git a/drivers/extcon/extcon-palmas.c b/drivers/extcon/extcon-palmas.c index d2c1a8b89c08..32f8b541770b 100644 --- a/drivers/extcon/extcon-palmas.c +++ b/drivers/extcon/extcon-palmas.c @@ -107,7 +107,7 @@ static irqreturn_t palmas_id_irq_handler(int irq, void *_palmas_usb) (id_src & PALMAS_USB_ID_INT_SRC_ID_GND)) { palmas_usb->linkstat = PALMAS_USB_STATE_ID; extcon_set_state_sync(edev, EXTCON_USB_HOST, true); - dev_dbg(palmas_usb->dev, " USB-HOST cable is attached\n"); + dev_dbg(palmas_usb->dev, "USB-HOST cable is attached\n"); } return IRQ_HANDLED; diff --git a/drivers/extcon/extcon-rt8973a.c b/drivers/extcon/extcon-rt8973a.c index 40c07f4d656e..02ba770acb27 100644 --- a/drivers/extcon/extcon-rt8973a.c +++ b/drivers/extcon/extcon-rt8973a.c @@ -192,7 +192,6 @@ static const struct regmap_irq_chip rt8973a_muic_irq_chip = { .name = "rt8973a", .status_base = RT8973A_REG_INT1, .mask_base = RT8973A_REG_INTM1, - .mask_invert = false, .num_regs = 2, .irqs = rt8973a_irqs, .num_irqs = ARRAY_SIZE(rt8973a_irqs), diff --git a/drivers/extcon/extcon-sm5502.c b/drivers/extcon/extcon-sm5502.c index f706f5288257..8401e8b27788 100644 --- a/drivers/extcon/extcon-sm5502.c +++ b/drivers/extcon/extcon-sm5502.c @@ -227,7 +227,6 @@ static const struct regmap_irq_chip sm5502_muic_irq_chip = { .name = "sm5502", .status_base = SM5502_REG_INT1, .mask_base = SM5502_REG_INTMASK1, - .mask_invert = false, .num_regs = 2, .irqs = sm5502_irqs, .num_irqs = ARRAY_SIZE(sm5502_irqs), @@ -276,7 +275,6 @@ static const struct regmap_irq_chip sm5504_muic_irq_chip = { .name = "sm5504", .status_base = SM5502_REG_INT1, .mask_base = SM5502_REG_INTMASK1, - .mask_invert = false, .num_regs = 2, .irqs = sm5504_irqs, .num_irqs = ARRAY_SIZE(sm5504_irqs), diff --git a/drivers/extcon/extcon.c b/drivers/extcon/extcon.c index d3a32b806499..e1c71359b605 100644 --- a/drivers/extcon/extcon.c +++ b/drivers/extcon/extcon.c @@ -167,6 +167,16 @@ static const struct __extcon_info { .id = EXTCON_DISP_HMD, .name = "HMD", }, + [EXTCON_DISP_CVBS] = { + .type = EXTCON_TYPE_DISP, + .id = EXTCON_DISP_CVBS, + .name = "CVBS", + }, + [EXTCON_DISP_EDP] = { + .type = EXTCON_TYPE_DISP, + .id = EXTCON_DISP_EDP, + .name = "EDP", + }, /* Miscellaneous external connector */ [EXTCON_DOCK] = { @@ -247,7 +257,7 @@ static int find_cable_index_by_id(struct extcon_dev *edev, const unsigned int id { int i; - /* Find the the index of extcon cable in edev->supported_cable */ + /* Find the index of extcon cable in edev->supported_cable */ for (i = 0; i < edev->max_supported; i++) { if (edev->supported_cable[i] == id) return i; diff --git a/drivers/firmware/stratix10-rsu.c b/drivers/firmware/stratix10-rsu.c index 9378075d04e9..e51c95f8d445 100644 --- a/drivers/firmware/stratix10-rsu.c +++ b/drivers/firmware/stratix10-rsu.c @@ -24,12 +24,16 @@ #define RSU_DCMF1_MASK GENMASK_ULL(63, 32) #define RSU_DCMF2_MASK GENMASK_ULL(31, 0) #define RSU_DCMF3_MASK GENMASK_ULL(63, 32) +#define RSU_DCMF0_STATUS_MASK GENMASK_ULL(15, 0) +#define RSU_DCMF1_STATUS_MASK GENMASK_ULL(31, 16) +#define RSU_DCMF2_STATUS_MASK GENMASK_ULL(47, 32) +#define RSU_DCMF3_STATUS_MASK GENMASK_ULL(63, 48) #define RSU_TIMEOUT (msecs_to_jiffies(SVC_RSU_REQUEST_TIMEOUT_MS)) #define INVALID_RETRY_COUNTER 0xFF #define INVALID_DCMF_VERSION 0xFF - +#define INVALID_DCMF_STATUS 0xFFFFFFFF typedef void (*rsu_callback)(struct stratix10_svc_client *client, struct stratix10_svc_cb_data *data); @@ -49,6 +53,10 @@ typedef void (*rsu_callback)(struct stratix10_svc_client *client, * @dcmf_version.dcmf1: Quartus dcmf1 version * @dcmf_version.dcmf2: Quartus dcmf2 version * @dcmf_version.dcmf3: Quartus dcmf3 version + * @dcmf_status.dcmf0: dcmf0 status + * @dcmf_status.dcmf1: dcmf1 status + * @dcmf_status.dcmf2: dcmf2 status + * @dcmf_status.dcmf3: dcmf3 status * @retry_counter: the current image's retry counter * @max_retry: the preset max retry value */ @@ -73,6 +81,13 @@ struct stratix10_rsu_priv { unsigned int dcmf3; } dcmf_version; + struct { + unsigned int dcmf0; + unsigned int dcmf1; + unsigned int dcmf2; + unsigned int dcmf3; + } dcmf_status; + unsigned int retry_counter; unsigned int max_retry; }; @@ -129,7 +144,7 @@ static void rsu_command_callback(struct stratix10_svc_client *client, struct stratix10_rsu_priv *priv = client->priv; if (data->status == BIT(SVC_STATUS_NO_SUPPORT)) - dev_warn(client->dev, "FW doesn't support notify\n"); + dev_warn(client->dev, "Secure FW doesn't support notify\n"); else if (data->status == BIT(SVC_STATUS_ERROR)) dev_err(client->dev, "Failure, returned status is %lu\n", BIT(data->status)); @@ -156,7 +171,7 @@ static void rsu_retry_callback(struct stratix10_svc_client *client, if (data->status == BIT(SVC_STATUS_OK)) priv->retry_counter = *counter; else if (data->status == BIT(SVC_STATUS_NO_SUPPORT)) - dev_warn(client->dev, "FW doesn't support retry\n"); + dev_warn(client->dev, "Secure FW doesn't support retry\n"); else dev_err(client->dev, "Failed to get retry counter %lu\n", BIT(data->status)); @@ -181,7 +196,7 @@ static void rsu_max_retry_callback(struct stratix10_svc_client *client, if (data->status == BIT(SVC_STATUS_OK)) priv->max_retry = *max_retry; else if (data->status == BIT(SVC_STATUS_NO_SUPPORT)) - dev_warn(client->dev, "FW doesn't support max retry\n"); + dev_warn(client->dev, "Secure FW doesn't support max retry\n"); else dev_err(client->dev, "Failed to get max retry %lu\n", BIT(data->status)); @@ -215,6 +230,35 @@ static void rsu_dcmf_version_callback(struct stratix10_svc_client *client, complete(&priv->completion); } +/** + * rsu_dcmf_status_callback() - Callback from Intel service layer for getting + * the DCMF status + * @client: pointer to client + * @data: pointer to callback data structure + * + * Callback from Intel service layer for DCMF status + */ +static void rsu_dcmf_status_callback(struct stratix10_svc_client *client, + struct stratix10_svc_cb_data *data) +{ + struct stratix10_rsu_priv *priv = client->priv; + unsigned long long *value = (unsigned long long *)data->kaddr1; + + if (data->status == BIT(SVC_STATUS_OK)) { + priv->dcmf_status.dcmf0 = FIELD_GET(RSU_DCMF0_STATUS_MASK, + *value); + priv->dcmf_status.dcmf1 = FIELD_GET(RSU_DCMF1_STATUS_MASK, + *value); + priv->dcmf_status.dcmf2 = FIELD_GET(RSU_DCMF2_STATUS_MASK, + *value); + priv->dcmf_status.dcmf3 = FIELD_GET(RSU_DCMF3_STATUS_MASK, + *value); + } else + dev_err(client->dev, "failed to get DCMF status\n"); + + complete(&priv->completion); +} + /** * rsu_send_msg() - send a message to Intel service layer * @priv: pointer to rsu private data @@ -361,7 +405,8 @@ static ssize_t max_retry_show(struct device *dev, if (!priv) return -ENODEV; - return sprintf(buf, "0x%08x\n", priv->max_retry); + return scnprintf(buf, sizeof(priv->max_retry), + "0x%08x\n", priv->max_retry); } static ssize_t dcmf0_show(struct device *dev, @@ -408,6 +453,61 @@ static ssize_t dcmf3_show(struct device *dev, return sprintf(buf, "0x%08x\n", priv->dcmf_version.dcmf3); } +static ssize_t dcmf0_status_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct stratix10_rsu_priv *priv = dev_get_drvdata(dev); + + if (!priv) + return -ENODEV; + + if (priv->dcmf_status.dcmf0 == INVALID_DCMF_STATUS) + return -EIO; + + return sprintf(buf, "0x%08x\n", priv->dcmf_status.dcmf0); +} + +static ssize_t dcmf1_status_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct stratix10_rsu_priv *priv = dev_get_drvdata(dev); + + if (!priv) + return -ENODEV; + + if (priv->dcmf_status.dcmf1 == INVALID_DCMF_STATUS) + return -EIO; + + return sprintf(buf, "0x%08x\n", priv->dcmf_status.dcmf1); +} + +static ssize_t dcmf2_status_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct stratix10_rsu_priv *priv = dev_get_drvdata(dev); + + if (!priv) + return -ENODEV; + + if (priv->dcmf_status.dcmf2 == INVALID_DCMF_STATUS) + return -EIO; + + return sprintf(buf, "0x%08x\n", priv->dcmf_status.dcmf2); +} + +static ssize_t dcmf3_status_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct stratix10_rsu_priv *priv = dev_get_drvdata(dev); + + if (!priv) + return -ENODEV; + + if (priv->dcmf_status.dcmf3 == INVALID_DCMF_STATUS) + return -EIO; + + return sprintf(buf, "0x%08x\n", priv->dcmf_status.dcmf3); +} static ssize_t reboot_image_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) @@ -484,6 +584,10 @@ static DEVICE_ATTR_RO(dcmf0); static DEVICE_ATTR_RO(dcmf1); static DEVICE_ATTR_RO(dcmf2); static DEVICE_ATTR_RO(dcmf3); +static DEVICE_ATTR_RO(dcmf0_status); +static DEVICE_ATTR_RO(dcmf1_status); +static DEVICE_ATTR_RO(dcmf2_status); +static DEVICE_ATTR_RO(dcmf3_status); static DEVICE_ATTR_WO(reboot_image); static DEVICE_ATTR_WO(notify); @@ -500,6 +604,10 @@ static struct attribute *rsu_attrs[] = { &dev_attr_dcmf1.attr, &dev_attr_dcmf2.attr, &dev_attr_dcmf3.attr, + &dev_attr_dcmf0_status.attr, + &dev_attr_dcmf1_status.attr, + &dev_attr_dcmf2_status.attr, + &dev_attr_dcmf3_status.attr, &dev_attr_reboot_image.attr, &dev_attr_notify.attr, NULL @@ -532,6 +640,10 @@ static int stratix10_rsu_probe(struct platform_device *pdev) priv->dcmf_version.dcmf2 = INVALID_DCMF_VERSION; priv->dcmf_version.dcmf3 = INVALID_DCMF_VERSION; priv->max_retry = INVALID_RETRY_COUNTER; + priv->dcmf_status.dcmf0 = INVALID_DCMF_STATUS; + priv->dcmf_status.dcmf1 = INVALID_DCMF_STATUS; + priv->dcmf_status.dcmf2 = INVALID_DCMF_STATUS; + priv->dcmf_status.dcmf3 = INVALID_DCMF_STATUS; mutex_init(&priv->lock); priv->chan = stratix10_svc_request_channel_byname(&priv->client, @@ -561,6 +673,13 @@ static int stratix10_rsu_probe(struct platform_device *pdev) stratix10_svc_free_channel(priv->chan); } + ret = rsu_send_msg(priv, COMMAND_RSU_DCMF_STATUS, + 0, rsu_dcmf_status_callback); + if (ret) { + dev_err(dev, "Error, getting DCMF status %i\n", ret); + stratix10_svc_free_channel(priv->chan); + } + ret = rsu_send_msg(priv, COMMAND_RSU_RETRY, 0, rsu_retry_callback); if (ret) { dev_err(dev, "Error, getting RSU retry %i\n", ret); diff --git a/drivers/firmware/stratix10-svc.c b/drivers/firmware/stratix10-svc.c index 14663f671323..b4081f4d88a3 100644 --- a/drivers/firmware/stratix10-svc.c +++ b/drivers/firmware/stratix10-svc.c @@ -34,12 +34,13 @@ * timeout is set to 30 seconds (30 * 1000) at Intel Stratix10 SoC. */ #define SVC_NUM_DATA_IN_FIFO 32 -#define SVC_NUM_CHANNEL 2 +#define SVC_NUM_CHANNEL 3 #define FPGA_CONFIG_DATA_CLAIM_TIMEOUT_MS 200 #define FPGA_CONFIG_STATUS_TIMEOUT_SEC 30 /* stratix10 service layer clients */ #define STRATIX10_RSU "stratix10-rsu" +#define INTEL_FCS "intel-fcs" typedef void (svc_invoke_fn)(unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, @@ -53,6 +54,7 @@ struct stratix10_svc_chan; */ struct stratix10_svc { struct platform_device *stratix10_svc_rsu; + struct platform_device *intel_svc_fcs; }; /** @@ -97,8 +99,10 @@ struct stratix10_svc_data_mem { /** * struct stratix10_svc_data - service data structure * @chan: service channel - * @paddr: playload physical address - * @size: playload size + * @paddr: physical address of to be processed payload + * @size: to be processed playload size + * @paddr_output: physical address of processed payload + * @size_output: processed payload size * @command: service command requested by client * @flag: configuration type (full or partial) * @arg: args to be passed via registers and not physically mapped buffers @@ -109,6 +113,8 @@ struct stratix10_svc_data { struct stratix10_svc_chan *chan; phys_addr_t paddr; size_t size; + phys_addr_t paddr_output; + size_t size_output; u32 command; u32 flag; u64 arg[3]; @@ -246,6 +252,7 @@ static void svc_thread_cmd_config_status(struct stratix10_svc_controller *ctrl, { struct arm_smccc_res res; int count_in_sec; + unsigned long a0, a1, a2; cb_data->kaddr1 = NULL; cb_data->kaddr2 = NULL; @@ -254,24 +261,45 @@ static void svc_thread_cmd_config_status(struct stratix10_svc_controller *ctrl, pr_debug("%s: polling config status\n", __func__); + a0 = INTEL_SIP_SMC_FPGA_CONFIG_ISDONE; + a1 = (unsigned long)p_data->paddr; + a2 = (unsigned long)p_data->size; + + if (p_data->command == COMMAND_POLL_SERVICE_STATUS) + a0 = INTEL_SIP_SMC_SERVICE_COMPLETED; + count_in_sec = FPGA_CONFIG_STATUS_TIMEOUT_SEC; while (count_in_sec) { - ctrl->invoke_fn(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, - 0, 0, 0, 0, 0, 0, 0, &res); + ctrl->invoke_fn(a0, a1, a2, 0, 0, 0, 0, 0, &res); if ((res.a0 == INTEL_SIP_SMC_STATUS_OK) || - (res.a0 == INTEL_SIP_SMC_STATUS_ERROR)) + (res.a0 == INTEL_SIP_SMC_STATUS_ERROR) || + (res.a0 == INTEL_SIP_SMC_STATUS_REJECTED)) break; /* - * configuration is still in progress, wait one second then + * request is still in progress, wait one second then * poll again */ msleep(1000); count_in_sec--; } - if (res.a0 == INTEL_SIP_SMC_STATUS_OK && count_in_sec) + if (!count_in_sec) { + pr_err("%s: poll status timeout\n", __func__); + cb_data->status = BIT(SVC_STATUS_BUSY); + } else if (res.a0 == INTEL_SIP_SMC_STATUS_OK) { cb_data->status = BIT(SVC_STATUS_COMPLETED); + cb_data->kaddr2 = (res.a2) ? + svc_pa_to_va(res.a2) : NULL; + cb_data->kaddr3 = (res.a3) ? &res.a3 : NULL; + } else { + pr_err("%s: poll status error\n", __func__); + cb_data->kaddr1 = &res.a1; + cb_data->kaddr2 = (res.a2) ? + svc_pa_to_va(res.a2) : NULL; + cb_data->kaddr3 = (res.a3) ? &res.a3 : NULL; + cb_data->status = BIT(SVC_STATUS_ERROR); + } p_data->chan->scl->receive_cb(p_data->chan->scl, cb_data); } @@ -296,6 +324,10 @@ static void svc_thread_recv_status_ok(struct stratix10_svc_data *p_data, case COMMAND_RECONFIG: case COMMAND_RSU_UPDATE: case COMMAND_RSU_NOTIFY: + case COMMAND_FCS_REQUEST_SERVICE: + case COMMAND_FCS_SEND_CERTIFICATE: + case COMMAND_FCS_DATA_ENCRYPTION: + case COMMAND_FCS_DATA_DECRYPTION: cb_data->status = BIT(SVC_STATUS_OK); break; case COMMAND_RECONFIG_DATA_SUBMIT: @@ -306,15 +338,29 @@ static void svc_thread_recv_status_ok(struct stratix10_svc_data *p_data, break; case COMMAND_RSU_RETRY: case COMMAND_RSU_MAX_RETRY: + case COMMAND_RSU_DCMF_STATUS: case COMMAND_FIRMWARE_VERSION: cb_data->status = BIT(SVC_STATUS_OK); cb_data->kaddr1 = &res.a1; break; + case COMMAND_SMC_SVC_VERSION: + cb_data->status = BIT(SVC_STATUS_OK); + cb_data->kaddr1 = &res.a1; + cb_data->kaddr2 = &res.a2; + break; case COMMAND_RSU_DCMF_VERSION: cb_data->status = BIT(SVC_STATUS_OK); cb_data->kaddr1 = &res.a1; cb_data->kaddr2 = &res.a2; break; + case COMMAND_FCS_RANDOM_NUMBER_GEN: + case COMMAND_FCS_GET_PROVISION_DATA: + case COMMAND_POLL_SERVICE_STATUS: + cb_data->status = BIT(SVC_STATUS_OK); + cb_data->kaddr1 = &res.a1; + cb_data->kaddr2 = svc_pa_to_va(res.a2); + cb_data->kaddr3 = &res.a3; + break; default: pr_warn("it shouldn't happen\n"); break; @@ -341,7 +387,7 @@ static int svc_normal_to_secure_thread(void *data) struct stratix10_svc_data *pdata; struct stratix10_svc_cb_data *cbdata; struct arm_smccc_res res; - unsigned long a0, a1, a2; + unsigned long a0, a1, a2, a3, a4, a5, a6, a7; int ret_fifo = 0; pdata = kmalloc(sizeof(*pdata), GFP_KERNEL); @@ -358,6 +404,11 @@ static int svc_normal_to_secure_thread(void *data) a0 = INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK; a1 = 0; a2 = 0; + a3 = 0; + a4 = 0; + a5 = 0; + a6 = 0; + a7 = 0; pr_debug("smc_hvc_shm_thread is running\n"); @@ -428,15 +479,74 @@ static int svc_normal_to_secure_thread(void *data) a1 = 0; a2 = 0; break; + + /* for FCS */ + case COMMAND_FCS_DATA_ENCRYPTION: + a0 = INTEL_SIP_SMC_FCS_CRYPTION; + a1 = 1; + a2 = (unsigned long)pdata->paddr; + a3 = (unsigned long)pdata->size; + a4 = (unsigned long)pdata->paddr_output; + a5 = (unsigned long)pdata->size_output; + break; + case COMMAND_FCS_DATA_DECRYPTION: + a0 = INTEL_SIP_SMC_FCS_CRYPTION; + a1 = 0; + a2 = (unsigned long)pdata->paddr; + a3 = (unsigned long)pdata->size; + a4 = (unsigned long)pdata->paddr_output; + a5 = (unsigned long)pdata->size_output; + break; + case COMMAND_FCS_RANDOM_NUMBER_GEN: + a0 = INTEL_SIP_SMC_FCS_RANDOM_NUMBER; + a1 = (unsigned long)pdata->paddr; + a2 = 0; + break; + case COMMAND_FCS_REQUEST_SERVICE: + a0 = INTEL_SIP_SMC_FCS_SERVICE_REQUEST; + a1 = (unsigned long)pdata->paddr; + a2 = (unsigned long)pdata->size; + break; + case COMMAND_FCS_SEND_CERTIFICATE: + a0 = INTEL_SIP_SMC_FCS_SEND_CERTIFICATE; + a1 = (unsigned long)pdata->paddr; + a2 = (unsigned long)pdata->size; + break; + case COMMAND_FCS_GET_PROVISION_DATA: + a0 = INTEL_SIP_SMC_FCS_GET_PROVISION_DATA; + a1 = (unsigned long)pdata->paddr; + a2 = 0; + break; + + /* for polling */ + case COMMAND_POLL_SERVICE_STATUS: + a0 = INTEL_SIP_SMC_SERVICE_COMPLETED; + a1 = (unsigned long)pdata->paddr; + a2 = (unsigned long)pdata->size; + break; + case COMMAND_RSU_DCMF_STATUS: + a0 = INTEL_SIP_SMC_RSU_DCMF_STATUS; + a1 = 0; + a2 = 0; + break; + case COMMAND_SMC_SVC_VERSION: + a0 = INTEL_SIP_SMC_SVC_VERSION; + a1 = 0; + a2 = 0; + break; default: pr_warn("it shouldn't happen\n"); break; } pr_debug("%s: before SMC call -- a0=0x%016x a1=0x%016x", - __func__, (unsigned int)a0, (unsigned int)a1); + __func__, + (unsigned int)a0, + (unsigned int)a1); pr_debug(" a2=0x%016x\n", (unsigned int)a2); - - ctrl->invoke_fn(a0, a1, a2, 0, 0, 0, 0, 0, &res); + pr_debug(" a3=0x%016x\n", (unsigned int)a3); + pr_debug(" a4=0x%016x\n", (unsigned int)a4); + pr_debug(" a5=0x%016x\n", (unsigned int)a5); + ctrl->invoke_fn(a0, a1, a2, a3, a4, a5, a6, a7, &res); pr_debug("%s: after SMC call -- res.a0=0x%016x", __func__, (unsigned int)res.a0); @@ -468,6 +578,7 @@ static int svc_normal_to_secure_thread(void *data) pdata, cbdata); break; case COMMAND_RECONFIG_STATUS: + case COMMAND_POLL_SERVICE_STATUS: svc_thread_cmd_config_status(ctrl, pdata, cbdata); break; @@ -478,14 +589,31 @@ static int svc_normal_to_secure_thread(void *data) break; case INTEL_SIP_SMC_STATUS_REJECTED: pr_debug("%s: STATUS_REJECTED\n", __func__); + /* for FCS */ + switch (pdata->command) { + case COMMAND_FCS_REQUEST_SERVICE: + case COMMAND_FCS_SEND_CERTIFICATE: + case COMMAND_FCS_GET_PROVISION_DATA: + case COMMAND_FCS_DATA_ENCRYPTION: + case COMMAND_FCS_DATA_DECRYPTION: + case COMMAND_FCS_RANDOM_NUMBER_GEN: + cbdata->status = BIT(SVC_STATUS_INVALID_PARAM); + cbdata->kaddr1 = NULL; + cbdata->kaddr2 = NULL; + cbdata->kaddr3 = NULL; + pdata->chan->scl->receive_cb(pdata->chan->scl, + cbdata); + break; + } break; case INTEL_SIP_SMC_STATUS_ERROR: case INTEL_SIP_SMC_RSU_ERROR: pr_err("%s: STATUS_ERROR\n", __func__); cbdata->status = BIT(SVC_STATUS_ERROR); cbdata->kaddr1 = &res.a1; - cbdata->kaddr2 = NULL; - cbdata->kaddr3 = NULL; + cbdata->kaddr2 = (res.a2) ? + svc_pa_to_va(res.a2) : NULL; + cbdata->kaddr3 = (res.a3) ? &res.a3 : NULL; pdata->chan->scl->receive_cb(pdata->chan->scl, cbdata); break; default: @@ -493,12 +621,10 @@ static int svc_normal_to_secure_thread(void *data) /* * be compatible with older version firmware which - * doesn't support RSU notify or retry + * doesn't support newer RSU commands */ - if ((pdata->command == COMMAND_RSU_RETRY) || - (pdata->command == COMMAND_RSU_MAX_RETRY) || - (pdata->command == COMMAND_RSU_NOTIFY) || - (pdata->command == COMMAND_FIRMWARE_VERSION)) { + if ((pdata->command != COMMAND_RSU_UPDATE) && + (pdata->command != COMMAND_RSU_STATUS)) { cbdata->status = BIT(SVC_STATUS_NO_SUPPORT); cbdata->kaddr1 = NULL; @@ -852,8 +978,19 @@ int stratix10_svc_send(struct stratix10_svc_chan *chan, void *msg) list_for_each_entry(p_mem, &svc_data_mem, node) if (p_mem->vaddr == p_msg->payload) { p_data->paddr = p_mem->paddr; + p_data->size = p_msg->payload_length; break; } + if (p_msg->payload_output) { + list_for_each_entry(p_mem, &svc_data_mem, node) + if (p_mem->vaddr == p_msg->payload_output) { + p_data->paddr_output = + p_mem->paddr; + p_data->size_output = + p_msg->payload_length_output; + break; + } + } } p_data->command = p_msg->command; @@ -1036,6 +1173,11 @@ static int stratix10_svc_drv_probe(struct platform_device *pdev) chans[1].name = SVC_CLIENT_RSU; spin_lock_init(&chans[1].lock); + chans[2].scl = NULL; + chans[2].ctrl = controller; + chans[2].name = SVC_CLIENT_FCS; + spin_lock_init(&chans[2].lock); + list_add_tail(&controller->node, &svc_ctrl); platform_set_drvdata(pdev, controller); @@ -1054,8 +1196,22 @@ static int stratix10_svc_drv_probe(struct platform_device *pdev) } ret = platform_device_add(svc->stratix10_svc_rsu); - if (ret) - goto err_put_device; + if (ret) { + platform_device_put(svc->stratix10_svc_rsu); + return ret; + } + + svc->intel_svc_fcs = platform_device_alloc(INTEL_FCS, 1); + if (!svc->intel_svc_fcs) { + dev_err(dev, "failed to allocate %s device\n", INTEL_FCS); + return -ENOMEM; + } + + ret = platform_device_add(svc->intel_svc_fcs); + if (ret) { + platform_device_put(svc->intel_svc_fcs); + return ret; + } dev_set_drvdata(dev, svc); @@ -1063,8 +1219,6 @@ static int stratix10_svc_drv_probe(struct platform_device *pdev) return 0; -err_put_device: - platform_device_put(svc->stratix10_svc_rsu); err_free_kfifo: kfifo_free(&controller->svc_fifo); return ret; @@ -1075,6 +1229,7 @@ static int stratix10_svc_drv_remove(struct platform_device *pdev) struct stratix10_svc *svc = dev_get_drvdata(&pdev->dev); struct stratix10_svc_controller *ctrl = platform_get_drvdata(pdev); + platform_device_unregister(svc->intel_svc_fcs); platform_device_unregister(svc->stratix10_svc_rsu); kfifo_free(&ctrl->svc_fifo); diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 991b3f361ec9..6c416955da53 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -243,4 +243,24 @@ config FPGA_MGR_VERSAL_FPGA configure the programmable logic(PL). To compile this as a module, choose M here. + +config FPGA_M10_BMC_SEC_UPDATE + tristate "Intel MAX10 BMC Secure Update driver" + depends on MFD_INTEL_M10_BMC && FW_UPLOAD + help + Secure update support for the Intel MAX10 board management + controller. + + This is a subdriver of the Intel MAX10 board management controller + (BMC) and provides support for secure updates for the BMC image, + the FPGA image, the Root Entry Hashes, etc. + +config FPGA_MGR_MICROCHIP_SPI + tristate "Microchip Polarfire SPI FPGA manager" + depends on SPI + help + FPGA manager driver support for Microchip Polarfire FPGAs + programming over slave SPI interface with .dat formatted + bitstream image. + endif # FPGA diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 5935b3d0abd5..42ae8b58abce 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -19,9 +19,13 @@ obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o +obj-$(CONFIG_FPGA_MGR_MICROCHIP_SPI) += microchip-spi.o obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o +# FPGA Secure Update Drivers +obj-$(CONFIG_FPGA_M10_BMC_SEC_UPDATE) += intel-m10-bmc-sec-update.o + # FPGA Bridge Drivers obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o diff --git a/drivers/fpga/altera-pr-ip-core.c b/drivers/fpga/altera-pr-ip-core.c index be0667968d33..df8671af4a92 100644 --- a/drivers/fpga/altera-pr-ip-core.c +++ b/drivers/fpga/altera-pr-ip-core.c @@ -108,7 +108,7 @@ static int alt_pr_fpga_write(struct fpga_manager *mgr, const char *buf, u32 *buffer_32 = (u32 *)buf; size_t i = 0; - if (count <= 0) + if (!count) return -EINVAL; /* Write out the complete 32-bit chunks */ diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c index 6bff39ff21a0..5498bc337f8b 100644 --- a/drivers/fpga/dfl.c +++ b/drivers/fpga/dfl.c @@ -342,7 +342,7 @@ static void release_dfl_dev(struct device *dev) if (ddev->mmio_res.parent) release_resource(&ddev->mmio_res); - ida_simple_remove(&dfl_device_ida, ddev->id); + ida_free(&dfl_device_ida, ddev->id); kfree(ddev->irqs); kfree(ddev); } @@ -360,7 +360,7 @@ dfl_dev_add(struct dfl_feature_platform_data *pdata, if (!ddev) return ERR_PTR(-ENOMEM); - id = ida_simple_get(&dfl_device_ida, 0, 0, GFP_KERNEL); + id = ida_alloc(&dfl_device_ida, GFP_KERNEL); if (id < 0) { dev_err(&pdev->dev, "unable to get id\n"); kfree(ddev); diff --git a/drivers/fpga/fpga-bridge.c b/drivers/fpga/fpga-bridge.c index 16f2b164a178..727704431f61 100644 --- a/drivers/fpga/fpga-bridge.c +++ b/drivers/fpga/fpga-bridge.c @@ -342,7 +342,7 @@ fpga_bridge_register(struct device *parent, const char *name, if (!bridge) return ERR_PTR(-ENOMEM); - id = ida_simple_get(&fpga_bridge_ida, 0, 0, GFP_KERNEL); + id = ida_alloc(&fpga_bridge_ida, GFP_KERNEL); if (id < 0) { ret = id; goto error_kfree; @@ -375,7 +375,7 @@ fpga_bridge_register(struct device *parent, const char *name, return bridge; error_device: - ida_simple_remove(&fpga_bridge_ida, id); + ida_free(&fpga_bridge_ida, id); error_kfree: kfree(bridge); @@ -407,7 +407,7 @@ static void fpga_bridge_dev_release(struct device *dev) { struct fpga_bridge *bridge = to_fpga_bridge(dev); - ida_simple_remove(&fpga_bridge_ida, bridge->dev.id); + ida_free(&fpga_bridge_ida, bridge->dev.id); kfree(bridge); } diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c index a3595ecc3f79..8efa67620e21 100644 --- a/drivers/fpga/fpga-mgr.c +++ b/drivers/fpga/fpga-mgr.c @@ -74,6 +74,15 @@ static inline int fpga_mgr_write_complete(struct fpga_manager *mgr, return 0; } +static inline int fpga_mgr_parse_header(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t count) +{ + if (mgr->mops->parse_header) + return mgr->mops->parse_header(mgr, info, buf, count); + return 0; +} + static inline int fpga_mgr_write_init(struct fpga_manager *mgr, struct fpga_image_info *info, const char *buf, size_t count) @@ -136,24 +145,141 @@ void fpga_image_info_free(struct fpga_image_info *info) EXPORT_SYMBOL_GPL(fpga_image_info_free); /* - * Call the low level driver's write_init function. This will do the + * Call the low level driver's parse_header function with entire FPGA image + * buffer on the input. This will set info->header_size and info->data_size. + */ +static int fpga_mgr_parse_header_mapped(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t count) +{ + int ret; + + mgr->state = FPGA_MGR_STATE_PARSE_HEADER; + ret = fpga_mgr_parse_header(mgr, info, buf, count); + + if (info->header_size + info->data_size > count) { + dev_err(&mgr->dev, "Bitstream data outruns FPGA image\n"); + ret = -EINVAL; + } + + if (ret) { + dev_err(&mgr->dev, "Error while parsing FPGA image header\n"); + mgr->state = FPGA_MGR_STATE_PARSE_HEADER_ERR; + } + + return ret; +} + +/* + * Call the low level driver's parse_header function with first fragment of + * scattered FPGA image on the input. If header fits first fragment, + * parse_header will set info->header_size and info->data_size. If it is not, + * parse_header will set desired size to info->header_size and -EAGAIN will be + * returned. + */ +static int fpga_mgr_parse_header_sg_first(struct fpga_manager *mgr, + struct fpga_image_info *info, + struct sg_table *sgt) +{ + struct sg_mapping_iter miter; + int ret; + + mgr->state = FPGA_MGR_STATE_PARSE_HEADER; + + sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG); + if (sg_miter_next(&miter) && + miter.length >= info->header_size) + ret = fpga_mgr_parse_header(mgr, info, miter.addr, miter.length); + else + ret = -EAGAIN; + sg_miter_stop(&miter); + + if (ret && ret != -EAGAIN) { + dev_err(&mgr->dev, "Error while parsing FPGA image header\n"); + mgr->state = FPGA_MGR_STATE_PARSE_HEADER_ERR; + } + + return ret; +} + +/* + * Copy scattered FPGA image fragments to temporary buffer and call the + * low level driver's parse_header function. This should be called after + * fpga_mgr_parse_header_sg_first() returned -EAGAIN. In case of success, + * pointer to the newly allocated image header copy will be returned and + * its size will be set into *ret_size. Returned buffer needs to be freed. + */ +static void *fpga_mgr_parse_header_sg(struct fpga_manager *mgr, + struct fpga_image_info *info, + struct sg_table *sgt, size_t *ret_size) +{ + size_t len, new_header_size, header_size = 0; + char *new_buf, *buf = NULL; + int ret; + + do { + new_header_size = info->header_size; + if (new_header_size <= header_size) { + dev_err(&mgr->dev, "Requested invalid header size\n"); + ret = -EFAULT; + break; + } + + new_buf = krealloc(buf, new_header_size, GFP_KERNEL); + if (!new_buf) { + ret = -ENOMEM; + break; + } + + buf = new_buf; + + len = sg_pcopy_to_buffer(sgt->sgl, sgt->nents, + buf + header_size, + new_header_size - header_size, + header_size); + if (len != new_header_size - header_size) { + ret = -EFAULT; + break; + } + + header_size = new_header_size; + ret = fpga_mgr_parse_header(mgr, info, buf, header_size); + } while (ret == -EAGAIN); + + if (ret) { + dev_err(&mgr->dev, "Error while parsing FPGA image header\n"); + mgr->state = FPGA_MGR_STATE_PARSE_HEADER_ERR; + kfree(buf); + buf = ERR_PTR(ret); + } + + *ret_size = header_size; + + return buf; +} + +/* + * Call the low level driver's write_init function. This will do the * device-specific things to get the FPGA into the state where it is ready to - * receive an FPGA image. The low level driver only gets to see the first - * initial_header_size bytes in the buffer. + * receive an FPGA image. The low level driver gets to see at least first + * info->header_size bytes in the buffer. If info->header_size is 0, + * write_init will not get any bytes of image buffer. */ static int fpga_mgr_write_init_buf(struct fpga_manager *mgr, struct fpga_image_info *info, const char *buf, size_t count) { + size_t header_size = info->header_size; int ret; mgr->state = FPGA_MGR_STATE_WRITE_INIT; - if (!mgr->mops->initial_header_size) { + + if (header_size > count) + ret = -EINVAL; + else if (!header_size) ret = fpga_mgr_write_init(mgr, info, NULL, 0); - } else { - count = min(mgr->mops->initial_header_size, count); + else ret = fpga_mgr_write_init(mgr, info, buf, count); - } if (ret) { dev_err(&mgr->dev, "Error preparing FPGA for writing\n"); @@ -164,39 +290,50 @@ static int fpga_mgr_write_init_buf(struct fpga_manager *mgr, return 0; } -static int fpga_mgr_write_init_sg(struct fpga_manager *mgr, - struct fpga_image_info *info, - struct sg_table *sgt) +static int fpga_mgr_prepare_sg(struct fpga_manager *mgr, + struct fpga_image_info *info, + struct sg_table *sgt) { struct sg_mapping_iter miter; size_t len; char *buf; int ret; - if (!mgr->mops->initial_header_size) + /* Short path. Low level driver don't care about image header. */ + if (!mgr->mops->initial_header_size && !mgr->mops->parse_header) return fpga_mgr_write_init_buf(mgr, info, NULL, 0); /* * First try to use miter to map the first fragment to access the * header, this is the typical path. */ - sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG); - if (sg_miter_next(&miter) && - miter.length >= mgr->mops->initial_header_size) { - ret = fpga_mgr_write_init_buf(mgr, info, miter.addr, - miter.length); + ret = fpga_mgr_parse_header_sg_first(mgr, info, sgt); + /* If 0, header fits first fragment, call write_init on it */ + if (!ret) { + sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG); + if (sg_miter_next(&miter)) { + ret = fpga_mgr_write_init_buf(mgr, info, miter.addr, + miter.length); + sg_miter_stop(&miter); + return ret; + } sg_miter_stop(&miter); + /* + * If -EAGAIN, more sg buffer is needed, + * otherwise an error has occurred. + */ + } else if (ret != -EAGAIN) { return ret; } - sg_miter_stop(&miter); - /* Otherwise copy the fragments into temporary memory. */ - buf = kmalloc(mgr->mops->initial_header_size, GFP_KERNEL); - if (!buf) - return -ENOMEM; + /* + * Copy the fragments into temporary memory. + * Copying is done inside fpga_mgr_parse_header_sg(). + */ + buf = fpga_mgr_parse_header_sg(mgr, info, sgt, &len); + if (IS_ERR(buf)) + return PTR_ERR(buf); - len = sg_copy_to_buffer(sgt->sgl, sgt->nents, buf, - mgr->mops->initial_header_size); ret = fpga_mgr_write_init_buf(mgr, info, buf, len); kfree(buf); @@ -227,7 +364,7 @@ static int fpga_mgr_buf_load_sg(struct fpga_manager *mgr, { int ret; - ret = fpga_mgr_write_init_sg(mgr, info, sgt); + ret = fpga_mgr_prepare_sg(mgr, info, sgt); if (ret) return ret; @@ -236,17 +373,35 @@ static int fpga_mgr_buf_load_sg(struct fpga_manager *mgr, if (mgr->mops->write_sg) { ret = fpga_mgr_write_sg(mgr, sgt); } else { + size_t length, count = 0, data_size = info->data_size; struct sg_mapping_iter miter; sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG); + + if (mgr->mops->skip_header && + !sg_miter_skip(&miter, info->header_size)) { + ret = -EINVAL; + goto out; + } + while (sg_miter_next(&miter)) { - ret = fpga_mgr_write(mgr, miter.addr, miter.length); + if (data_size) + length = min(miter.length, data_size - count); + else + length = miter.length; + + ret = fpga_mgr_write(mgr, miter.addr, length); if (ret) break; + + count += length; + if (data_size && count >= data_size) + break; } sg_miter_stop(&miter); } +out: if (ret) { dev_err(&mgr->dev, "Error while writing image data to FPGA\n"); mgr->state = FPGA_MGR_STATE_WRITE_ERR; @@ -262,10 +417,22 @@ static int fpga_mgr_buf_load_mapped(struct fpga_manager *mgr, { int ret; + ret = fpga_mgr_parse_header_mapped(mgr, info, buf, count); + if (ret) + return ret; + ret = fpga_mgr_write_init_buf(mgr, info, buf, count); if (ret) return ret; + if (mgr->mops->skip_header) { + buf += info->header_size; + count -= info->header_size; + } + + if (info->data_size) + count = info->data_size; + /* * Write the FPGA image to the FPGA. */ @@ -404,6 +571,8 @@ static int fpga_mgr_firmware_load(struct fpga_manager *mgr, */ int fpga_mgr_load(struct fpga_manager *mgr, struct fpga_image_info *info) { + info->header_size = mgr->mops->initial_header_size; + if (info->sgt) return fpga_mgr_buf_load_sg(mgr, info, info->sgt); if (info->buf && info->count) @@ -424,6 +593,10 @@ static const char * const state_str[] = { [FPGA_MGR_STATE_FIRMWARE_REQ] = "firmware request", [FPGA_MGR_STATE_FIRMWARE_REQ_ERR] = "firmware request error", + /* Parse FPGA image header */ + [FPGA_MGR_STATE_PARSE_HEADER] = "parse header", + [FPGA_MGR_STATE_PARSE_HEADER_ERR] = "parse header error", + /* Preparing FPGA to receive image */ [FPGA_MGR_STATE_WRITE_INIT] = "write init", [FPGA_MGR_STATE_WRITE_INIT_ERR] = "write init error", @@ -623,7 +796,7 @@ fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *in if (!mgr) return ERR_PTR(-ENOMEM); - id = ida_simple_get(&fpga_mgr_ida, 0, 0, GFP_KERNEL); + id = ida_alloc(&fpga_mgr_ida, GFP_KERNEL); if (id < 0) { ret = id; goto error_kfree; @@ -662,7 +835,7 @@ fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *in return mgr; error_device: - ida_simple_remove(&fpga_mgr_ida, id); + ida_free(&fpga_mgr_ida, id); error_kfree: kfree(mgr); @@ -790,7 +963,7 @@ static void fpga_mgr_dev_release(struct device *dev) { struct fpga_manager *mgr = to_fpga_manager(dev); - ida_simple_remove(&fpga_mgr_ida, mgr->dev.id); + ida_free(&fpga_mgr_ida, mgr->dev.id); kfree(mgr); } diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c index 485948e3c0db..27ff9dea04ae 100644 --- a/drivers/fpga/fpga-region.c +++ b/drivers/fpga/fpga-region.c @@ -202,7 +202,7 @@ fpga_region_register_full(struct device *parent, const struct fpga_region_info * if (!region) return ERR_PTR(-ENOMEM); - id = ida_simple_get(&fpga_region_ida, 0, 0, GFP_KERNEL); + id = ida_alloc(&fpga_region_ida, GFP_KERNEL); if (id < 0) { ret = id; goto err_free; @@ -234,7 +234,7 @@ fpga_region_register_full(struct device *parent, const struct fpga_region_info * return region; err_remove: - ida_simple_remove(&fpga_region_ida, id); + ida_free(&fpga_region_ida, id); err_free: kfree(region); @@ -283,7 +283,7 @@ static void fpga_region_dev_release(struct device *dev) { struct fpga_region *region = to_fpga_region(dev); - ida_simple_remove(&fpga_region_ida, region->dev.id); + ida_free(&fpga_region_ida, region->dev.id); kfree(region); } diff --git a/drivers/fpga/intel-m10-bmc-sec-update.c b/drivers/fpga/intel-m10-bmc-sec-update.c new file mode 100644 index 000000000000..72c677c910de --- /dev/null +++ b/drivers/fpga/intel-m10-bmc-sec-update.c @@ -0,0 +1,625 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Intel MAX10 Board Management Controller Secure Update Driver + * + * Copyright (C) 2019-2022 Intel Corporation. All rights reserved. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include + +struct m10bmc_sec { + struct device *dev; + struct intel_m10bmc *m10bmc; + struct fw_upload *fwl; + char *fw_name; + u32 fw_name_id; + bool cancel_request; +}; + +static DEFINE_XARRAY_ALLOC(fw_upload_xa); + +/* Root Entry Hash (REH) support */ +#define REH_SHA256_SIZE 32 +#define REH_SHA384_SIZE 48 +#define REH_MAGIC GENMASK(15, 0) +#define REH_SHA_NUM_BYTES GENMASK(31, 16) + +static ssize_t +show_root_entry_hash(struct device *dev, u32 exp_magic, + u32 prog_addr, u32 reh_addr, char *buf) +{ + struct m10bmc_sec *sec = dev_get_drvdata(dev); + int sha_num_bytes, i, ret, cnt = 0; + u8 hash[REH_SHA384_SIZE]; + unsigned int stride; + u32 magic; + + stride = regmap_get_reg_stride(sec->m10bmc->regmap); + ret = m10bmc_raw_read(sec->m10bmc, prog_addr, &magic); + if (ret) + return ret; + + if (FIELD_GET(REH_MAGIC, magic) != exp_magic) + return sysfs_emit(buf, "hash not programmed\n"); + + sha_num_bytes = FIELD_GET(REH_SHA_NUM_BYTES, magic) / 8; + if ((sha_num_bytes % stride) || + (sha_num_bytes != REH_SHA256_SIZE && + sha_num_bytes != REH_SHA384_SIZE)) { + dev_err(sec->dev, "%s bad sha num bytes %d\n", __func__, + sha_num_bytes); + return -EINVAL; + } + + ret = regmap_bulk_read(sec->m10bmc->regmap, reh_addr, + hash, sha_num_bytes / stride); + if (ret) { + dev_err(dev, "failed to read root entry hash: %x cnt %x: %d\n", + reh_addr, sha_num_bytes / stride, ret); + return ret; + } + + for (i = 0; i < sha_num_bytes; i++) + cnt += sprintf(buf + cnt, "%02x", hash[i]); + cnt += sprintf(buf + cnt, "\n"); + + return cnt; +} + +#define DEVICE_ATTR_SEC_REH_RO(_name, _magic, _prog_addr, _reh_addr) \ +static ssize_t _name##_root_entry_hash_show(struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ +{ return show_root_entry_hash(dev, _magic, _prog_addr, _reh_addr, buf); } \ +static DEVICE_ATTR_RO(_name##_root_entry_hash) + +DEVICE_ATTR_SEC_REH_RO(bmc, BMC_PROG_MAGIC, BMC_PROG_ADDR, BMC_REH_ADDR); +DEVICE_ATTR_SEC_REH_RO(sr, SR_PROG_MAGIC, SR_PROG_ADDR, SR_REH_ADDR); +DEVICE_ATTR_SEC_REH_RO(pr, PR_PROG_MAGIC, PR_PROG_ADDR, PR_REH_ADDR); + +#define CSK_BIT_LEN 128U +#define CSK_32ARRAY_SIZE DIV_ROUND_UP(CSK_BIT_LEN, 32) + +static ssize_t +show_canceled_csk(struct device *dev, u32 addr, char *buf) +{ + unsigned int i, stride, size = CSK_32ARRAY_SIZE * sizeof(u32); + struct m10bmc_sec *sec = dev_get_drvdata(dev); + DECLARE_BITMAP(csk_map, CSK_BIT_LEN); + __le32 csk_le32[CSK_32ARRAY_SIZE]; + u32 csk32[CSK_32ARRAY_SIZE]; + int ret; + + stride = regmap_get_reg_stride(sec->m10bmc->regmap); + if (size % stride) { + dev_err(sec->dev, + "CSK vector size (0x%x) not aligned to stride (0x%x)\n", + size, stride); + WARN_ON_ONCE(1); + return -EINVAL; + } + + ret = regmap_bulk_read(sec->m10bmc->regmap, addr, csk_le32, + size / stride); + if (ret) { + dev_err(sec->dev, "failed to read CSK vector: %x cnt %x: %d\n", + addr, size / stride, ret); + return ret; + } + + for (i = 0; i < CSK_32ARRAY_SIZE; i++) + csk32[i] = le32_to_cpu(((csk_le32[i]))); + + bitmap_from_arr32(csk_map, csk32, CSK_BIT_LEN); + bitmap_complement(csk_map, csk_map, CSK_BIT_LEN); + return bitmap_print_to_pagebuf(1, buf, csk_map, CSK_BIT_LEN); +} + +#define DEVICE_ATTR_SEC_CSK_RO(_name, _addr) \ +static ssize_t _name##_canceled_csks_show(struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ +{ return show_canceled_csk(dev, _addr, buf); } \ +static DEVICE_ATTR_RO(_name##_canceled_csks) + +#define CSK_VEC_OFFSET 0x34 + +DEVICE_ATTR_SEC_CSK_RO(bmc, BMC_PROG_ADDR + CSK_VEC_OFFSET); +DEVICE_ATTR_SEC_CSK_RO(sr, SR_PROG_ADDR + CSK_VEC_OFFSET); +DEVICE_ATTR_SEC_CSK_RO(pr, PR_PROG_ADDR + CSK_VEC_OFFSET); + +#define FLASH_COUNT_SIZE 4096 /* count stored as inverted bit vector */ + +static ssize_t flash_count_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct m10bmc_sec *sec = dev_get_drvdata(dev); + unsigned int stride, num_bits; + u8 *flash_buf; + int cnt, ret; + + stride = regmap_get_reg_stride(sec->m10bmc->regmap); + num_bits = FLASH_COUNT_SIZE * 8; + + flash_buf = kmalloc(FLASH_COUNT_SIZE, GFP_KERNEL); + if (!flash_buf) + return -ENOMEM; + + if (FLASH_COUNT_SIZE % stride) { + dev_err(sec->dev, + "FLASH_COUNT_SIZE (0x%x) not aligned to stride (0x%x)\n", + FLASH_COUNT_SIZE, stride); + WARN_ON_ONCE(1); + return -EINVAL; + } + + ret = regmap_bulk_read(sec->m10bmc->regmap, STAGING_FLASH_COUNT, + flash_buf, FLASH_COUNT_SIZE / stride); + if (ret) { + dev_err(sec->dev, + "failed to read flash count: %x cnt %x: %d\n", + STAGING_FLASH_COUNT, FLASH_COUNT_SIZE / stride, ret); + goto exit_free; + } + cnt = num_bits - bitmap_weight((unsigned long *)flash_buf, num_bits); + +exit_free: + kfree(flash_buf); + + return ret ? : sysfs_emit(buf, "%u\n", cnt); +} +static DEVICE_ATTR_RO(flash_count); + +static struct attribute *m10bmc_security_attrs[] = { + &dev_attr_flash_count.attr, + &dev_attr_bmc_root_entry_hash.attr, + &dev_attr_sr_root_entry_hash.attr, + &dev_attr_pr_root_entry_hash.attr, + &dev_attr_sr_canceled_csks.attr, + &dev_attr_pr_canceled_csks.attr, + &dev_attr_bmc_canceled_csks.attr, + NULL, +}; + +static struct attribute_group m10bmc_security_attr_group = { + .name = "security", + .attrs = m10bmc_security_attrs, +}; + +static const struct attribute_group *m10bmc_sec_attr_groups[] = { + &m10bmc_security_attr_group, + NULL, +}; + +static void log_error_regs(struct m10bmc_sec *sec, u32 doorbell) +{ + u32 auth_result; + + dev_err(sec->dev, "RSU error status: 0x%08x\n", doorbell); + + if (!m10bmc_sys_read(sec->m10bmc, M10BMC_AUTH_RESULT, &auth_result)) + dev_err(sec->dev, "RSU auth result: 0x%08x\n", auth_result); +} + +static enum fw_upload_err rsu_check_idle(struct m10bmc_sec *sec) +{ + u32 doorbell; + int ret; + + ret = m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell); + if (ret) + return FW_UPLOAD_ERR_RW_ERROR; + + if (rsu_prog(doorbell) != RSU_PROG_IDLE && + rsu_prog(doorbell) != RSU_PROG_RSU_DONE) { + log_error_regs(sec, doorbell); + return FW_UPLOAD_ERR_BUSY; + } + + return FW_UPLOAD_ERR_NONE; +} + +static inline bool rsu_start_done(u32 doorbell) +{ + u32 status, progress; + + if (doorbell & DRBL_RSU_REQUEST) + return false; + + status = rsu_stat(doorbell); + if (status == RSU_STAT_ERASE_FAIL || status == RSU_STAT_WEAROUT) + return true; + + progress = rsu_prog(doorbell); + if (progress != RSU_PROG_IDLE && progress != RSU_PROG_RSU_DONE) + return true; + + return false; +} + +static enum fw_upload_err rsu_update_init(struct m10bmc_sec *sec) +{ + u32 doorbell, status; + int ret; + + ret = regmap_update_bits(sec->m10bmc->regmap, + M10BMC_SYS_BASE + M10BMC_DOORBELL, + DRBL_RSU_REQUEST | DRBL_HOST_STATUS, + DRBL_RSU_REQUEST | + FIELD_PREP(DRBL_HOST_STATUS, + HOST_STATUS_IDLE)); + if (ret) + return FW_UPLOAD_ERR_RW_ERROR; + + ret = regmap_read_poll_timeout(sec->m10bmc->regmap, + M10BMC_SYS_BASE + M10BMC_DOORBELL, + doorbell, + rsu_start_done(doorbell), + NIOS_HANDSHAKE_INTERVAL_US, + NIOS_HANDSHAKE_TIMEOUT_US); + + if (ret == -ETIMEDOUT) { + log_error_regs(sec, doorbell); + return FW_UPLOAD_ERR_TIMEOUT; + } else if (ret) { + return FW_UPLOAD_ERR_RW_ERROR; + } + + status = rsu_stat(doorbell); + if (status == RSU_STAT_WEAROUT) { + dev_warn(sec->dev, "Excessive flash update count detected\n"); + return FW_UPLOAD_ERR_WEAROUT; + } else if (status == RSU_STAT_ERASE_FAIL) { + log_error_regs(sec, doorbell); + return FW_UPLOAD_ERR_HW_ERROR; + } + + return FW_UPLOAD_ERR_NONE; +} + +static enum fw_upload_err rsu_prog_ready(struct m10bmc_sec *sec) +{ + unsigned long poll_timeout; + u32 doorbell, progress; + int ret; + + ret = m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell); + if (ret) + return FW_UPLOAD_ERR_RW_ERROR; + + poll_timeout = jiffies + msecs_to_jiffies(RSU_PREP_TIMEOUT_MS); + while (rsu_prog(doorbell) == RSU_PROG_PREPARE) { + msleep(RSU_PREP_INTERVAL_MS); + if (time_after(jiffies, poll_timeout)) + break; + + ret = m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell); + if (ret) + return FW_UPLOAD_ERR_RW_ERROR; + } + + progress = rsu_prog(doorbell); + if (progress == RSU_PROG_PREPARE) { + log_error_regs(sec, doorbell); + return FW_UPLOAD_ERR_TIMEOUT; + } else if (progress != RSU_PROG_READY) { + log_error_regs(sec, doorbell); + return FW_UPLOAD_ERR_HW_ERROR; + } + + return FW_UPLOAD_ERR_NONE; +} + +static enum fw_upload_err rsu_send_data(struct m10bmc_sec *sec) +{ + u32 doorbell; + int ret; + + ret = regmap_update_bits(sec->m10bmc->regmap, + M10BMC_SYS_BASE + M10BMC_DOORBELL, + DRBL_HOST_STATUS, + FIELD_PREP(DRBL_HOST_STATUS, + HOST_STATUS_WRITE_DONE)); + if (ret) + return FW_UPLOAD_ERR_RW_ERROR; + + ret = regmap_read_poll_timeout(sec->m10bmc->regmap, + M10BMC_SYS_BASE + M10BMC_DOORBELL, + doorbell, + rsu_prog(doorbell) != RSU_PROG_READY, + NIOS_HANDSHAKE_INTERVAL_US, + NIOS_HANDSHAKE_TIMEOUT_US); + + if (ret == -ETIMEDOUT) { + log_error_regs(sec, doorbell); + return FW_UPLOAD_ERR_TIMEOUT; + } else if (ret) { + return FW_UPLOAD_ERR_RW_ERROR; + } + + switch (rsu_stat(doorbell)) { + case RSU_STAT_NORMAL: + case RSU_STAT_NIOS_OK: + case RSU_STAT_USER_OK: + case RSU_STAT_FACTORY_OK: + break; + default: + log_error_regs(sec, doorbell); + return FW_UPLOAD_ERR_HW_ERROR; + } + + return FW_UPLOAD_ERR_NONE; +} + +static int rsu_check_complete(struct m10bmc_sec *sec, u32 *doorbell) +{ + if (m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, doorbell)) + return -EIO; + + switch (rsu_stat(*doorbell)) { + case RSU_STAT_NORMAL: + case RSU_STAT_NIOS_OK: + case RSU_STAT_USER_OK: + case RSU_STAT_FACTORY_OK: + break; + default: + return -EINVAL; + } + + switch (rsu_prog(*doorbell)) { + case RSU_PROG_IDLE: + case RSU_PROG_RSU_DONE: + return 0; + case RSU_PROG_AUTHENTICATING: + case RSU_PROG_COPYING: + case RSU_PROG_UPDATE_CANCEL: + case RSU_PROG_PROGRAM_KEY_HASH: + return -EAGAIN; + default: + return -EINVAL; + } +} + +static enum fw_upload_err rsu_cancel(struct m10bmc_sec *sec) +{ + u32 doorbell; + int ret; + + ret = m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell); + if (ret) + return FW_UPLOAD_ERR_RW_ERROR; + + if (rsu_prog(doorbell) != RSU_PROG_READY) + return FW_UPLOAD_ERR_BUSY; + + ret = regmap_update_bits(sec->m10bmc->regmap, + M10BMC_SYS_BASE + M10BMC_DOORBELL, + DRBL_HOST_STATUS, + FIELD_PREP(DRBL_HOST_STATUS, + HOST_STATUS_ABORT_RSU)); + if (ret) + return FW_UPLOAD_ERR_RW_ERROR; + + return FW_UPLOAD_ERR_CANCELED; +} + +static enum fw_upload_err m10bmc_sec_prepare(struct fw_upload *fwl, + const u8 *data, u32 size) +{ + struct m10bmc_sec *sec = fwl->dd_handle; + u32 ret; + + sec->cancel_request = false; + + if (!size || size > M10BMC_STAGING_SIZE) + return FW_UPLOAD_ERR_INVALID_SIZE; + + ret = rsu_check_idle(sec); + if (ret != FW_UPLOAD_ERR_NONE) + return ret; + + ret = rsu_update_init(sec); + if (ret != FW_UPLOAD_ERR_NONE) + return ret; + + ret = rsu_prog_ready(sec); + if (ret != FW_UPLOAD_ERR_NONE) + return ret; + + if (sec->cancel_request) + return rsu_cancel(sec); + + return FW_UPLOAD_ERR_NONE; +} + +#define WRITE_BLOCK_SIZE 0x4000 /* Default write-block size is 0x4000 bytes */ + +static enum fw_upload_err m10bmc_sec_write(struct fw_upload *fwl, const u8 *data, + u32 offset, u32 size, u32 *written) +{ + struct m10bmc_sec *sec = fwl->dd_handle; + u32 blk_size, doorbell, extra_offset; + unsigned int stride, extra = 0; + int ret; + + stride = regmap_get_reg_stride(sec->m10bmc->regmap); + if (sec->cancel_request) + return rsu_cancel(sec); + + ret = m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell); + if (ret) { + return FW_UPLOAD_ERR_RW_ERROR; + } else if (rsu_prog(doorbell) != RSU_PROG_READY) { + log_error_regs(sec, doorbell); + return FW_UPLOAD_ERR_HW_ERROR; + } + + WARN_ON_ONCE(WRITE_BLOCK_SIZE % stride); + blk_size = min_t(u32, WRITE_BLOCK_SIZE, size); + ret = regmap_bulk_write(sec->m10bmc->regmap, + M10BMC_STAGING_BASE + offset, + (void *)data + offset, + blk_size / stride); + if (ret) + return FW_UPLOAD_ERR_RW_ERROR; + + /* + * If blk_size is not aligned to stride, then handle the extra + * bytes with regmap_write. + */ + if (blk_size % stride) { + extra_offset = offset + ALIGN_DOWN(blk_size, stride); + memcpy(&extra, (u8 *)(data + extra_offset), blk_size % stride); + ret = regmap_write(sec->m10bmc->regmap, + M10BMC_STAGING_BASE + extra_offset, extra); + if (ret) + return FW_UPLOAD_ERR_RW_ERROR; + } + + *written = blk_size; + return FW_UPLOAD_ERR_NONE; +} + +static enum fw_upload_err m10bmc_sec_poll_complete(struct fw_upload *fwl) +{ + struct m10bmc_sec *sec = fwl->dd_handle; + unsigned long poll_timeout; + u32 doorbell, result; + int ret; + + if (sec->cancel_request) + return rsu_cancel(sec); + + result = rsu_send_data(sec); + if (result != FW_UPLOAD_ERR_NONE) + return result; + + poll_timeout = jiffies + msecs_to_jiffies(RSU_COMPLETE_TIMEOUT_MS); + do { + msleep(RSU_COMPLETE_INTERVAL_MS); + ret = rsu_check_complete(sec, &doorbell); + } while (ret == -EAGAIN && !time_after(jiffies, poll_timeout)); + + if (ret == -EAGAIN) { + log_error_regs(sec, doorbell); + return FW_UPLOAD_ERR_TIMEOUT; + } else if (ret == -EIO) { + return FW_UPLOAD_ERR_RW_ERROR; + } else if (ret) { + log_error_regs(sec, doorbell); + return FW_UPLOAD_ERR_HW_ERROR; + } + + return FW_UPLOAD_ERR_NONE; +} + +/* + * m10bmc_sec_cancel() may be called asynchronously with an on-going update. + * All other functions are called sequentially in a single thread. To avoid + * contention on register accesses, m10bmc_sec_cancel() must only update + * the cancel_request flag. Other functions will check this flag and handle + * the cancel request synchronously. + */ +static void m10bmc_sec_cancel(struct fw_upload *fwl) +{ + struct m10bmc_sec *sec = fwl->dd_handle; + + sec->cancel_request = true; +} + +static void m10bmc_sec_cleanup(struct fw_upload *fwl) +{ + struct m10bmc_sec *sec = fwl->dd_handle; + + (void)rsu_cancel(sec); +} + +static const struct fw_upload_ops m10bmc_ops = { + .prepare = m10bmc_sec_prepare, + .write = m10bmc_sec_write, + .poll_complete = m10bmc_sec_poll_complete, + .cancel = m10bmc_sec_cancel, + .cleanup = m10bmc_sec_cleanup, +}; + +#define SEC_UPDATE_LEN_MAX 32 +static int m10bmc_sec_probe(struct platform_device *pdev) +{ + char buf[SEC_UPDATE_LEN_MAX]; + struct m10bmc_sec *sec; + struct fw_upload *fwl; + unsigned int len; + int ret; + + sec = devm_kzalloc(&pdev->dev, sizeof(*sec), GFP_KERNEL); + if (!sec) + return -ENOMEM; + + sec->dev = &pdev->dev; + sec->m10bmc = dev_get_drvdata(pdev->dev.parent); + dev_set_drvdata(&pdev->dev, sec); + + ret = xa_alloc(&fw_upload_xa, &sec->fw_name_id, sec, + xa_limit_32b, GFP_KERNEL); + if (ret) + return ret; + + len = scnprintf(buf, SEC_UPDATE_LEN_MAX, "secure-update%d", + sec->fw_name_id); + sec->fw_name = kmemdup_nul(buf, len, GFP_KERNEL); + if (!sec->fw_name) + return -ENOMEM; + + fwl = firmware_upload_register(THIS_MODULE, sec->dev, sec->fw_name, + &m10bmc_ops, sec); + if (IS_ERR(fwl)) { + dev_err(sec->dev, "Firmware Upload driver failed to start\n"); + kfree(sec->fw_name); + xa_erase(&fw_upload_xa, sec->fw_name_id); + return PTR_ERR(fwl); + } + + sec->fwl = fwl; + return 0; +} + +static int m10bmc_sec_remove(struct platform_device *pdev) +{ + struct m10bmc_sec *sec = dev_get_drvdata(&pdev->dev); + + firmware_upload_unregister(sec->fwl); + kfree(sec->fw_name); + xa_erase(&fw_upload_xa, sec->fw_name_id); + + return 0; +} + +static const struct platform_device_id intel_m10bmc_sec_ids[] = { + { + .name = "n3000bmc-sec-update", + }, + { } +}; +MODULE_DEVICE_TABLE(platform, intel_m10bmc_sec_ids); + +static struct platform_driver intel_m10bmc_sec_driver = { + .probe = m10bmc_sec_probe, + .remove = m10bmc_sec_remove, + .driver = { + .name = "intel-m10bmc-sec-update", + .dev_groups = m10bmc_sec_attr_groups, + }, + .id_table = intel_m10bmc_sec_ids, +}; +module_platform_driver(intel_m10bmc_sec_driver); + +MODULE_AUTHOR("Intel Corporation"); +MODULE_DESCRIPTION("Intel MAX10 BMC Secure Update"); +MODULE_LICENSE("GPL"); diff --git a/drivers/fpga/microchip-spi.c b/drivers/fpga/microchip-spi.c new file mode 100644 index 000000000000..bd284c7b8dc9 --- /dev/null +++ b/drivers/fpga/microchip-spi.c @@ -0,0 +1,398 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Microchip Polarfire FPGA programming over slave SPI interface. + */ + +#include +#include +#include +#include +#include +#include + +#define MPF_SPI_ISC_ENABLE 0x0B +#define MPF_SPI_ISC_DISABLE 0x0C +#define MPF_SPI_READ_STATUS 0x00 +#define MPF_SPI_READ_DATA 0x01 +#define MPF_SPI_FRAME_INIT 0xAE +#define MPF_SPI_FRAME 0xEE +#define MPF_SPI_PRG_MODE 0x01 +#define MPF_SPI_RELEASE 0x23 + +#define MPF_SPI_FRAME_SIZE 16 + +#define MPF_HEADER_SIZE_OFFSET 24 +#define MPF_DATA_SIZE_OFFSET 55 + +#define MPF_LOOKUP_TABLE_RECORD_SIZE 9 +#define MPF_LOOKUP_TABLE_BLOCK_ID_OFFSET 0 +#define MPF_LOOKUP_TABLE_BLOCK_START_OFFSET 1 + +#define MPF_COMPONENTS_SIZE_ID 5 +#define MPF_BITSTREAM_ID 8 + +#define MPF_BITS_PER_COMPONENT_SIZE 22 + +#define MPF_STATUS_POLL_RETRIES 10000 +#define MPF_STATUS_BUSY BIT(0) +#define MPF_STATUS_READY BIT(1) +#define MPF_STATUS_SPI_VIOLATION BIT(2) +#define MPF_STATUS_SPI_ERROR BIT(3) + +struct mpf_priv { + struct spi_device *spi; + bool program_mode; +}; + +static int mpf_read_status(struct spi_device *spi) +{ + u8 status = 0, status_command = MPF_SPI_READ_STATUS; + struct spi_transfer xfers[2] = { 0 }; + int ret; + + /* + * HW status is returned on MISO in the first byte after CS went + * active. However, first reading can be inadequate, so we submit + * two identical SPI transfers and use result of the later one. + */ + xfers[0].tx_buf = &status_command; + xfers[1].tx_buf = &status_command; + xfers[0].rx_buf = &status; + xfers[1].rx_buf = &status; + xfers[0].len = 1; + xfers[1].len = 1; + xfers[0].cs_change = 1; + + ret = spi_sync_transfer(spi, xfers, 2); + + if ((status & MPF_STATUS_SPI_VIOLATION) || + (status & MPF_STATUS_SPI_ERROR)) + ret = -EIO; + + return ret ? : status; +} + +static enum fpga_mgr_states mpf_ops_state(struct fpga_manager *mgr) +{ + struct mpf_priv *priv = mgr->priv; + struct spi_device *spi; + bool program_mode; + int status; + + spi = priv->spi; + program_mode = priv->program_mode; + status = mpf_read_status(spi); + + if (!program_mode && !status) + return FPGA_MGR_STATE_OPERATING; + + return FPGA_MGR_STATE_UNKNOWN; +} + +static int mpf_ops_parse_header(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t count) +{ + size_t component_size_byte_num, component_size_byte_off, + components_size_start, bitstream_start, + block_id_offset, block_start_offset; + u8 header_size, blocks_num, block_id; + u32 block_start, component_size; + u16 components_num, i; + + if (!buf) { + dev_err(&mgr->dev, "Image buffer is not provided\n"); + return -EINVAL; + } + + header_size = *(buf + MPF_HEADER_SIZE_OFFSET); + if (header_size > count) { + info->header_size = header_size; + return -EAGAIN; + } + + /* + * Go through look-up table to find out where actual bitstream starts + * and where sizes of components of the bitstream lies. + */ + blocks_num = *(buf + header_size - 1); + block_id_offset = header_size + MPF_LOOKUP_TABLE_BLOCK_ID_OFFSET; + block_start_offset = header_size + MPF_LOOKUP_TABLE_BLOCK_START_OFFSET; + + header_size += blocks_num * MPF_LOOKUP_TABLE_RECORD_SIZE; + if (header_size > count) { + info->header_size = header_size; + return -EAGAIN; + } + + components_size_start = 0; + bitstream_start = 0; + + while (blocks_num--) { + block_id = *(buf + block_id_offset); + block_start = get_unaligned_le32(buf + block_start_offset); + + switch (block_id) { + case MPF_BITSTREAM_ID: + bitstream_start = block_start; + info->header_size = block_start; + if (block_start > count) + return -EAGAIN; + + break; + case MPF_COMPONENTS_SIZE_ID: + components_size_start = block_start; + break; + default: + break; + } + + if (bitstream_start && components_size_start) + break; + + block_id_offset += MPF_LOOKUP_TABLE_RECORD_SIZE; + block_start_offset += MPF_LOOKUP_TABLE_RECORD_SIZE; + } + + if (!bitstream_start || !components_size_start) { + dev_err(&mgr->dev, "Failed to parse header look-up table\n"); + return -EFAULT; + } + + /* + * Parse bitstream size. + * Sizes of components of the bitstream are 22-bits long placed next + * to each other. Image header should be extended by now up to where + * actual bitstream starts, so no need for overflow check anymore. + */ + components_num = get_unaligned_le16(buf + MPF_DATA_SIZE_OFFSET); + + for (i = 0; i < components_num; i++) { + component_size_byte_num = + (i * MPF_BITS_PER_COMPONENT_SIZE) / BITS_PER_BYTE; + component_size_byte_off = + (i * MPF_BITS_PER_COMPONENT_SIZE) % BITS_PER_BYTE; + + component_size = get_unaligned_le32(buf + + components_size_start + + component_size_byte_num); + component_size >>= component_size_byte_off; + component_size &= GENMASK(MPF_BITS_PER_COMPONENT_SIZE - 1, 0); + + info->data_size += component_size * MPF_SPI_FRAME_SIZE; + } + + return 0; +} + +/* Poll HW status until busy bit is cleared and mask bits are set. */ +static int mpf_poll_status(struct spi_device *spi, u8 mask) +{ + int status, retries = MPF_STATUS_POLL_RETRIES; + + while (retries--) { + status = mpf_read_status(spi); + if (status < 0) + return status; + + if (status & MPF_STATUS_BUSY) + continue; + + if (!mask || (status & mask)) + return status; + } + + return -EBUSY; +} + +static int mpf_spi_write(struct spi_device *spi, const void *buf, size_t buf_size) +{ + int status = mpf_poll_status(spi, 0); + + if (status < 0) + return status; + + return spi_write(spi, buf, buf_size); +} + +static int mpf_spi_write_then_read(struct spi_device *spi, + const void *txbuf, size_t txbuf_size, + void *rxbuf, size_t rxbuf_size) +{ + const u8 read_command[] = { MPF_SPI_READ_DATA }; + int ret; + + ret = mpf_spi_write(spi, txbuf, txbuf_size); + if (ret) + return ret; + + ret = mpf_poll_status(spi, MPF_STATUS_READY); + if (ret < 0) + return ret; + + return spi_write_then_read(spi, read_command, sizeof(read_command), + rxbuf, rxbuf_size); +} + +static int mpf_ops_write_init(struct fpga_manager *mgr, + struct fpga_image_info *info, const char *buf, + size_t count) +{ + const u8 program_mode[] = { MPF_SPI_FRAME_INIT, MPF_SPI_PRG_MODE }; + const u8 isc_en_command[] = { MPF_SPI_ISC_ENABLE }; + struct mpf_priv *priv = mgr->priv; + struct device *dev = &mgr->dev; + struct spi_device *spi; + u32 isc_ret = 0; + int ret; + + if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { + dev_err(dev, "Partial reconfiguration is not supported\n"); + return -EOPNOTSUPP; + } + + spi = priv->spi; + + ret = mpf_spi_write_then_read(spi, isc_en_command, sizeof(isc_en_command), + &isc_ret, sizeof(isc_ret)); + if (ret || isc_ret) { + dev_err(dev, "Failed to enable ISC: spi_ret %d, isc_ret %u\n", + ret, isc_ret); + return -EFAULT; + } + + ret = mpf_spi_write(spi, program_mode, sizeof(program_mode)); + if (ret) { + dev_err(dev, "Failed to enter program mode: %d\n", ret); + return ret; + } + + priv->program_mode = true; + + return 0; +} + +static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count) +{ + u8 spi_frame_command[] = { MPF_SPI_FRAME }; + struct spi_transfer xfers[2] = { 0 }; + struct mpf_priv *priv = mgr->priv; + struct device *dev = &mgr->dev; + struct spi_device *spi; + int ret, i; + + if (count % MPF_SPI_FRAME_SIZE) { + dev_err(dev, "Bitstream size is not a multiple of %d\n", + MPF_SPI_FRAME_SIZE); + return -EINVAL; + } + + spi = priv->spi; + + xfers[0].tx_buf = spi_frame_command; + xfers[0].len = sizeof(spi_frame_command); + + for (i = 0; i < count / MPF_SPI_FRAME_SIZE; i++) { + xfers[1].tx_buf = buf + i * MPF_SPI_FRAME_SIZE; + xfers[1].len = MPF_SPI_FRAME_SIZE; + + ret = mpf_poll_status(spi, 0); + if (ret >= 0) + ret = spi_sync_transfer(spi, xfers, ARRAY_SIZE(xfers)); + + if (ret) { + dev_err(dev, "Failed to write bitstream frame %d/%zu\n", + i, count / MPF_SPI_FRAME_SIZE); + return ret; + } + } + + return 0; +} + +static int mpf_ops_write_complete(struct fpga_manager *mgr, + struct fpga_image_info *info) +{ + const u8 isc_dis_command[] = { MPF_SPI_ISC_DISABLE }; + const u8 release_command[] = { MPF_SPI_RELEASE }; + struct mpf_priv *priv = mgr->priv; + struct device *dev = &mgr->dev; + struct spi_device *spi; + int ret; + + spi = priv->spi; + + ret = mpf_spi_write(spi, isc_dis_command, sizeof(isc_dis_command)); + if (ret) { + dev_err(dev, "Failed to disable ISC: %d\n", ret); + return ret; + } + + usleep_range(1000, 2000); + + ret = mpf_spi_write(spi, release_command, sizeof(release_command)); + if (ret) { + dev_err(dev, "Failed to exit program mode: %d\n", ret); + return ret; + } + + priv->program_mode = false; + + return 0; +} + +static const struct fpga_manager_ops mpf_ops = { + .state = mpf_ops_state, + .initial_header_size = 71, + .skip_header = true, + .parse_header = mpf_ops_parse_header, + .write_init = mpf_ops_write_init, + .write = mpf_ops_write, + .write_complete = mpf_ops_write_complete, +}; + +static int mpf_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + struct fpga_manager *mgr; + struct mpf_priv *priv; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->spi = spi; + + mgr = devm_fpga_mgr_register(dev, "Microchip Polarfire SPI FPGA Manager", + &mpf_ops, priv); + + return PTR_ERR_OR_ZERO(mgr); +} + +static const struct spi_device_id mpf_spi_ids[] = { + { .name = "mpf-spi-fpga-mgr", }, + {}, +}; +MODULE_DEVICE_TABLE(spi, mpf_spi_ids); + +#if IS_ENABLED(CONFIG_OF) +static const struct of_device_id mpf_of_ids[] = { + { .compatible = "microchip,mpf-spi-fpga-mgr" }, + {}, +}; +MODULE_DEVICE_TABLE(of, mpf_of_ids); +#endif /* IS_ENABLED(CONFIG_OF) */ + +static struct spi_driver mpf_driver = { + .probe = mpf_probe, + .id_table = mpf_spi_ids, + .driver = { + .name = "microchip_mpf_spi_fpga_mgr", + .of_match_table = of_match_ptr(mpf_of_ids), + }, +}; + +module_spi_driver(mpf_driver); + +MODULE_DESCRIPTION("Microchip Polarfire SPI FPGA Manager"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c index f6ab3b5586ce..dd732215d55b 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.c +++ b/drivers/gpu/drm/msm/dp/dp_parser.c @@ -22,14 +22,6 @@ #define DP_DEFAULT_P0_OFFSET 0x1000 #define DP_DEFAULT_P0_SIZE 0x0400 -static const struct dp_regulator_cfg sdm845_dp_reg_cfg = { - .num = 2, - .regs = { - {"vdda-1p2", 21800, 4 }, /* 1.2 V */ - {"vdda-0p9", 36000, 32 }, /* 0.9 V */ - }, -}; - static void __iomem *dp_ioremap(struct platform_device *pdev, int idx, size_t *len) { struct resource *res; @@ -283,12 +275,6 @@ static int dp_parser_parse(struct dp_parser *parser) if (rc) return rc; - /* Map the corresponding regulator information according to - * version. Currently, since we only have one supported platform, - * mapping the regulator directly. - */ - parser->regulator_cfg = &sdm845_dp_reg_cfg; - return 0; } diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h index 9abddc6d50c0..866c1a82bf1a 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.h +++ b/drivers/gpu/drm/msm/dp/dp_parser.h @@ -91,8 +91,6 @@ struct dp_pinctrl { struct pinctrl_state *state_suspend; }; -#define DP_DEV_REGULATOR_MAX 4 - /* Regulators for DP devices */ struct dp_reg_entry { char name[32]; @@ -100,11 +98,6 @@ struct dp_reg_entry { int disable_load; }; -struct dp_regulator_cfg { - int num; - struct dp_reg_entry regs[DP_DEV_REGULATOR_MAX]; -}; - struct dss_module_power { unsigned int num_clk; struct clk_bulk_data *clocks; @@ -125,7 +118,6 @@ struct dp_parser { struct dp_pinctrl pinctrl; struct dp_io io; struct dp_display_data disp_data; - const struct dp_regulator_cfg *regulator_cfg; u32 max_dp_lanes; struct drm_bridge *next_bridge; diff --git a/drivers/gpu/drm/msm/dp/dp_power.c b/drivers/gpu/drm/msm/dp/dp_power.c index b415b35c2b8c..c0aaabb03389 100644 --- a/drivers/gpu/drm/msm/dp/dp_power.c +++ b/drivers/gpu/drm/msm/dp/dp_power.c @@ -20,82 +20,10 @@ struct dp_power_private { struct clk *link_clk_src; struct clk *pixel_provider; struct clk *link_provider; - struct regulator_bulk_data supplies[DP_DEV_REGULATOR_MAX]; struct dp_power dp_power; }; -static void dp_power_regulator_disable(struct dp_power_private *power) -{ - struct regulator_bulk_data *s = power->supplies; - const struct dp_reg_entry *regs = power->parser->regulator_cfg->regs; - int num = power->parser->regulator_cfg->num; - int i; - - DBG(""); - for (i = num - 1; i >= 0; i--) - if (regs[i].disable_load >= 0) - regulator_set_load(s[i].consumer, - regs[i].disable_load); - - regulator_bulk_disable(num, s); -} - -static int dp_power_regulator_enable(struct dp_power_private *power) -{ - struct regulator_bulk_data *s = power->supplies; - const struct dp_reg_entry *regs = power->parser->regulator_cfg->regs; - int num = power->parser->regulator_cfg->num; - int ret, i; - - DBG(""); - for (i = 0; i < num; i++) { - if (regs[i].enable_load >= 0) { - ret = regulator_set_load(s[i].consumer, - regs[i].enable_load); - if (ret < 0) { - pr_err("regulator %d set op mode failed, %d\n", - i, ret); - goto fail; - } - } - } - - ret = regulator_bulk_enable(num, s); - if (ret < 0) { - pr_err("regulator enable failed, %d\n", ret); - goto fail; - } - - return 0; - -fail: - for (i--; i >= 0; i--) - regulator_set_load(s[i].consumer, regs[i].disable_load); - return ret; -} - -static int dp_power_regulator_init(struct dp_power_private *power) -{ - struct regulator_bulk_data *s = power->supplies; - const struct dp_reg_entry *regs = power->parser->regulator_cfg->regs; - struct platform_device *pdev = power->pdev; - int num = power->parser->regulator_cfg->num; - int i, ret; - - for (i = 0; i < num; i++) - s[i].supply = regs[i].name; - - ret = devm_regulator_bulk_get(&pdev->dev, num, s); - if (ret < 0) { - pr_err("%s: failed to init regulator, ret=%d\n", - __func__, ret); - return ret; - } - - return 0; -} - static int dp_power_clk_init(struct dp_power_private *power) { int rc = 0; @@ -246,21 +174,10 @@ int dp_power_client_init(struct dp_power *dp_power) pm_runtime_enable(&power->pdev->dev); - rc = dp_power_regulator_init(power); - if (rc) { - DRM_ERROR("failed to init regulators %d\n", rc); - goto error; - } - rc = dp_power_clk_init(power); - if (rc) { + if (rc) DRM_ERROR("failed to init clocks %d\n", rc); - goto error; - } - return 0; -error: - pm_runtime_disable(&power->pdev->dev); return rc; } @@ -291,22 +208,15 @@ int dp_power_init(struct dp_power *dp_power, bool flip) power = container_of(dp_power, struct dp_power_private, dp_power); pm_runtime_get_sync(&power->pdev->dev); - rc = dp_power_regulator_enable(power); - if (rc) { - DRM_ERROR("failed to enable regulators, %d\n", rc); - goto exit; - } rc = dp_power_clk_enable(dp_power, DP_CORE_PM, true); if (rc) { DRM_ERROR("failed to enable DP core clocks, %d\n", rc); - goto err_clk; + goto exit; } return 0; -err_clk: - dp_power_regulator_disable(power); exit: pm_runtime_put_sync(&power->pdev->dev); return rc; @@ -319,7 +229,6 @@ int dp_power_deinit(struct dp_power *dp_power) power = container_of(dp_power, struct dp_power_private, dp_power); dp_power_clk_enable(dp_power, DP_CORE_PM, false); - dp_power_regulator_disable(power); pm_runtime_put_sync(&power->pdev->dev); return 0; } diff --git a/drivers/hwtracing/coresight/coresight-config.h b/drivers/hwtracing/coresight/coresight-config.h index 2e1670523461..6ba013975741 100644 --- a/drivers/hwtracing/coresight/coresight-config.h +++ b/drivers/hwtracing/coresight/coresight-config.h @@ -134,6 +134,7 @@ struct cscfg_feature_desc { * @active_cnt: ref count for activate on this configuration. * @load_owner: handle to load owner for dynamic load and unload of configs. * @fs_group: reference to configfs group for dynamic unload. + * @available: config can be activated - multi-stage load sets true on completion. */ struct cscfg_config_desc { const char *name; @@ -148,6 +149,7 @@ struct cscfg_config_desc { atomic_t active_cnt; void *load_owner; struct config_group *fs_group; + bool available; }; /** diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index ee6ce92ab4c3..1edfec1e9d18 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1424,6 +1424,7 @@ static int coresight_remove_match(struct device *dev, void *data) * platform data. */ fwnode_handle_put(conn->child_fwnode); + conn->child_fwnode = NULL; /* No need to continue */ break; } diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index c039b6ae206f..43bbd5dc3d3b 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -52,6 +52,7 @@ static DEFINE_PER_CPU(struct coresight_device *, csdev_src); * The PMU formats were orignally for ETMv3.5/PTM's ETMCR 'config'; * now take them as general formats and apply on all ETMs. */ +PMU_FORMAT_ATTR(branch_broadcast, "config:"__stringify(ETM_OPT_BRANCH_BROADCAST)); PMU_FORMAT_ATTR(cycacc, "config:" __stringify(ETM_OPT_CYCACC)); /* contextid1 enables tracing CONTEXTIDR_EL1 for ETMv4 */ PMU_FORMAT_ATTR(contextid1, "config:" __stringify(ETM_OPT_CTXTID)); @@ -97,6 +98,7 @@ static struct attribute *etm_config_formats_attr[] = { &format_attr_sinkid.attr, &format_attr_preset.attr, &format_attr_configid.attr, + &format_attr_branch_broadcast.attr, NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 87299e99dabb..cf249ecad5a5 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -696,6 +696,20 @@ static int etm4_parse_event_config(struct coresight_device *csdev, ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset); } + /* branch broadcast - enable if selected and supported */ + if (attr->config & BIT(ETM_OPT_BRANCH_BROADCAST)) { + if (!drvdata->trcbb) { + /* + * Missing BB support could cause silent decode errors + * so fail to open if it's not supported. + */ + ret = -EINVAL; + goto out; + } else { + config->cfg |= BIT(ETM4_CFG_BIT_BB); + } + } + out: return ret; } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 33869c1d20c3..a7bfea31f7d8 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -7,6 +7,7 @@ #define _CORESIGHT_CORESIGHT_ETM_H #include +#include #include #include #include "coresight-priv.h" @@ -515,7 +516,7 @@ ({ \ u64 __val; \ \ - if (__builtin_constant_p((offset))) \ + if (__is_constexpr((offset))) \ __val = read_etm4x_sysreg_const_offset((offset)); \ else \ __val = etm4x_sysreg_read((offset), true, (_64bit)); \ diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c index 11850fd8c3b5..11138a9762b0 100644 --- a/drivers/hwtracing/coresight/coresight-syscfg.c +++ b/drivers/hwtracing/coresight/coresight-syscfg.c @@ -414,6 +414,27 @@ static void cscfg_remove_owned_csdev_features(struct coresight_device *csdev, vo } } +/* + * Unregister all configuration and features from configfs owned by load_owner. + * Although this is called without the list mutex being held, it is in the + * context of an unload operation which are strictly serialised, + * so the lists cannot change during this call. + */ +static void cscfg_fs_unregister_cfgs_feats(void *load_owner) +{ + struct cscfg_config_desc *config_desc; + struct cscfg_feature_desc *feat_desc; + + list_for_each_entry(config_desc, &cscfg_mgr->config_desc_list, item) { + if (config_desc->load_owner == load_owner) + cscfg_configfs_del_config(config_desc); + } + list_for_each_entry(feat_desc, &cscfg_mgr->feat_desc_list, item) { + if (feat_desc->load_owner == load_owner) + cscfg_configfs_del_feature(feat_desc); + } +} + /* * removal is relatively easy - just remove from all lists, anything that * matches the owner. Memory for the descriptors will be managed by the owner, @@ -426,6 +447,8 @@ static void cscfg_unload_owned_cfgs_feats(void *load_owner) struct cscfg_feature_desc *feat_desc, *feat_tmp; struct cscfg_registered_csdev *csdev_item; + lockdep_assert_held(&cscfg_mutex); + /* remove from each csdev instance feature and config lists */ list_for_each_entry(csdev_item, &cscfg_mgr->csdev_desc_list, item) { /* @@ -439,7 +462,6 @@ static void cscfg_unload_owned_cfgs_feats(void *load_owner) /* remove from the config descriptor lists */ list_for_each_entry_safe(config_desc, cfg_tmp, &cscfg_mgr->config_desc_list, item) { if (config_desc->load_owner == load_owner) { - cscfg_configfs_del_config(config_desc); etm_perf_del_symlink_cscfg(config_desc); list_del(&config_desc->item); } @@ -448,12 +470,90 @@ static void cscfg_unload_owned_cfgs_feats(void *load_owner) /* remove from the feature descriptor lists */ list_for_each_entry_safe(feat_desc, feat_tmp, &cscfg_mgr->feat_desc_list, item) { if (feat_desc->load_owner == load_owner) { - cscfg_configfs_del_feature(feat_desc); list_del(&feat_desc->item); } } } +/* + * load the features and configs to the lists - called with list mutex held + */ +static int cscfg_load_owned_cfgs_feats(struct cscfg_config_desc **config_descs, + struct cscfg_feature_desc **feat_descs, + struct cscfg_load_owner_info *owner_info) +{ + int i, err; + + lockdep_assert_held(&cscfg_mutex); + + /* load features first */ + if (feat_descs) { + for (i = 0; feat_descs[i]; i++) { + err = cscfg_load_feat(feat_descs[i]); + if (err) { + pr_err("coresight-syscfg: Failed to load feature %s\n", + feat_descs[i]->name); + return err; + } + feat_descs[i]->load_owner = owner_info; + } + } + + /* next any configurations to check feature dependencies */ + if (config_descs) { + for (i = 0; config_descs[i]; i++) { + err = cscfg_load_config(config_descs[i]); + if (err) { + pr_err("coresight-syscfg: Failed to load configuration %s\n", + config_descs[i]->name); + return err; + } + config_descs[i]->load_owner = owner_info; + config_descs[i]->available = false; + } + } + return 0; +} + +/* set configurations as available to activate at the end of the load process */ +static void cscfg_set_configs_available(struct cscfg_config_desc **config_descs) +{ + int i; + + lockdep_assert_held(&cscfg_mutex); + + if (config_descs) { + for (i = 0; config_descs[i]; i++) + config_descs[i]->available = true; + } +} + +/* + * Create and register each of the configurations and features with configfs. + * Called without mutex being held. + */ +static int cscfg_fs_register_cfgs_feats(struct cscfg_config_desc **config_descs, + struct cscfg_feature_desc **feat_descs) +{ + int i, err; + + if (feat_descs) { + for (i = 0; feat_descs[i]; i++) { + err = cscfg_configfs_add_feature(feat_descs[i]); + if (err) + return err; + } + } + if (config_descs) { + for (i = 0; config_descs[i]; i++) { + err = cscfg_configfs_add_config(config_descs[i]); + if (err) + return err; + } + } + return 0; +} + /** * cscfg_load_config_sets - API function to load feature and config sets. * @@ -476,57 +576,63 @@ int cscfg_load_config_sets(struct cscfg_config_desc **config_descs, struct cscfg_feature_desc **feat_descs, struct cscfg_load_owner_info *owner_info) { - int err = 0, i = 0; + int err = 0; mutex_lock(&cscfg_mutex); - - /* load features first */ - if (feat_descs) { - while (feat_descs[i]) { - err = cscfg_load_feat(feat_descs[i]); - if (!err) - err = cscfg_configfs_add_feature(feat_descs[i]); - if (err) { - pr_err("coresight-syscfg: Failed to load feature %s\n", - feat_descs[i]->name); - cscfg_unload_owned_cfgs_feats(owner_info); - goto exit_unlock; - } - feat_descs[i]->load_owner = owner_info; - i++; - } + if (cscfg_mgr->load_state != CSCFG_NONE) { + mutex_unlock(&cscfg_mutex); + return -EBUSY; } + cscfg_mgr->load_state = CSCFG_LOAD; - /* next any configurations to check feature dependencies */ - i = 0; - if (config_descs) { - while (config_descs[i]) { - err = cscfg_load_config(config_descs[i]); - if (!err) - err = cscfg_configfs_add_config(config_descs[i]); - if (err) { - pr_err("coresight-syscfg: Failed to load configuration %s\n", - config_descs[i]->name); - cscfg_unload_owned_cfgs_feats(owner_info); - goto exit_unlock; - } - config_descs[i]->load_owner = owner_info; - i++; - } - } + /* first load and add to the lists */ + err = cscfg_load_owned_cfgs_feats(config_descs, feat_descs, owner_info); + if (err) + goto err_clean_load; /* add the load owner to the load order list */ list_add_tail(&owner_info->item, &cscfg_mgr->load_order_list); if (!list_is_singular(&cscfg_mgr->load_order_list)) { /* lock previous item in load order list */ err = cscfg_owner_get(list_prev_entry(owner_info, item)); - if (err) { - cscfg_unload_owned_cfgs_feats(owner_info); - list_del(&owner_info->item); - } + if (err) + goto err_clean_owner_list; } + /* + * make visible to configfs - configfs manipulation must occur outside + * the list mutex lock to avoid circular lockdep issues with configfs + * built in mutexes and semaphores. This is safe as it is not possible + * to start a new load/unload operation till the current one is done. + */ + mutex_unlock(&cscfg_mutex); + + /* create the configfs elements */ + err = cscfg_fs_register_cfgs_feats(config_descs, feat_descs); + mutex_lock(&cscfg_mutex); + + if (err) + goto err_clean_cfs; + + /* mark any new configs as available for activation */ + cscfg_set_configs_available(config_descs); + goto exit_unlock; + +err_clean_cfs: + /* cleanup after error registering with configfs */ + cscfg_fs_unregister_cfgs_feats(owner_info); + + if (!list_is_singular(&cscfg_mgr->load_order_list)) + cscfg_owner_put(list_prev_entry(owner_info, item)); + +err_clean_owner_list: + list_del(&owner_info->item); + +err_clean_load: + cscfg_unload_owned_cfgs_feats(owner_info); + exit_unlock: + cscfg_mgr->load_state = CSCFG_NONE; mutex_unlock(&cscfg_mutex); return err; } @@ -543,6 +649,9 @@ EXPORT_SYMBOL_GPL(cscfg_load_config_sets); * 1) no configurations are active. * 2) the set being unloaded was the last to be loaded to maintain dependencies. * + * Once the unload operation commences, we disallow any configuration being + * made active until it is complete. + * * @owner_info: Information on owner for set being unloaded. */ int cscfg_unload_config_sets(struct cscfg_load_owner_info *owner_info) @@ -551,6 +660,13 @@ int cscfg_unload_config_sets(struct cscfg_load_owner_info *owner_info) struct cscfg_load_owner_info *load_list_item = NULL; mutex_lock(&cscfg_mutex); + if (cscfg_mgr->load_state != CSCFG_NONE) { + mutex_unlock(&cscfg_mutex); + return -EBUSY; + } + + /* unload op in progress also prevents activation of any config */ + cscfg_mgr->load_state = CSCFG_UNLOAD; /* cannot unload if anything is active */ if (atomic_read(&cscfg_mgr->sys_active_cnt)) { @@ -571,7 +687,12 @@ int cscfg_unload_config_sets(struct cscfg_load_owner_info *owner_info) goto exit_unlock; } - /* unload all belonging to load_owner */ + /* remove from configfs - again outside the scope of the list mutex */ + mutex_unlock(&cscfg_mutex); + cscfg_fs_unregister_cfgs_feats(owner_info); + mutex_lock(&cscfg_mutex); + + /* unload everything from lists belonging to load_owner */ cscfg_unload_owned_cfgs_feats(owner_info); /* remove from load order list */ @@ -582,6 +703,7 @@ int cscfg_unload_config_sets(struct cscfg_load_owner_info *owner_info) list_del(&owner_info->item); exit_unlock: + cscfg_mgr->load_state = CSCFG_NONE; mutex_unlock(&cscfg_mutex); return err; } @@ -759,8 +881,15 @@ static int _cscfg_activate_config(unsigned long cfg_hash) struct cscfg_config_desc *config_desc; int err = -EINVAL; + if (cscfg_mgr->load_state == CSCFG_UNLOAD) + return -EBUSY; + list_for_each_entry(config_desc, &cscfg_mgr->config_desc_list, item) { if ((unsigned long)config_desc->event_ea->var == cfg_hash) { + /* if we happen upon a partly loaded config, can't use it */ + if (config_desc->available == false) + return -EBUSY; + /* must ensure that config cannot be unloaded in use */ err = cscfg_owner_get(config_desc->load_owner); if (err) @@ -1022,8 +1151,10 @@ struct device *cscfg_device(void) /* Must have a release function or the kernel will complain on module unload */ static void cscfg_dev_release(struct device *dev) { + mutex_lock(&cscfg_mutex); kfree(cscfg_mgr); cscfg_mgr = NULL; + mutex_unlock(&cscfg_mutex); } /* a device is needed to "own" some kernel elements such as sysfs entries. */ @@ -1042,6 +1173,14 @@ static int cscfg_create_device(void) if (!cscfg_mgr) goto create_dev_exit_unlock; + /* initialise the cscfg_mgr structure */ + INIT_LIST_HEAD(&cscfg_mgr->csdev_desc_list); + INIT_LIST_HEAD(&cscfg_mgr->feat_desc_list); + INIT_LIST_HEAD(&cscfg_mgr->config_desc_list); + INIT_LIST_HEAD(&cscfg_mgr->load_order_list); + atomic_set(&cscfg_mgr->sys_active_cnt, 0); + cscfg_mgr->load_state = CSCFG_NONE; + /* setup the device */ dev = cscfg_device(); dev->release = cscfg_dev_release; @@ -1056,17 +1195,73 @@ create_dev_exit_unlock: return err; } +/* + * Loading and unloading is generally on user discretion. + * If exiting due to coresight module unload, we need to unload any configurations that remain, + * before we unregister the configfs intrastructure. + * + * Do this by walking the load_owner list and taking appropriate action, depending on the load + * owner type. + */ +static void cscfg_unload_cfgs_on_exit(void) +{ + struct cscfg_load_owner_info *owner_info = NULL; + + /* + * grab the mutex - even though we are exiting, some configfs files + * may still be live till we dump them, so ensure list data is + * protected from a race condition. + */ + mutex_lock(&cscfg_mutex); + while (!list_empty(&cscfg_mgr->load_order_list)) { + + /* remove in reverse order of loading */ + owner_info = list_last_entry(&cscfg_mgr->load_order_list, + struct cscfg_load_owner_info, item); + + /* action according to type */ + switch (owner_info->type) { + case CSCFG_OWNER_PRELOAD: + /* + * preloaded descriptors are statically allocated in + * this module - just need to unload dynamic items from + * csdev lists, and remove from configfs directories. + */ + pr_info("cscfg: unloading preloaded configurations\n"); + break; + + case CSCFG_OWNER_MODULE: + /* + * this is an error - the loadable module must have been unloaded prior + * to the coresight module unload. Therefore that module has not + * correctly unloaded configs in its own exit code. + * Nothing to do other than emit an error string as the static descriptor + * references we need to unload will have disappeared with the module. + */ + pr_err("cscfg: ERROR: prior module failed to unload configuration\n"); + goto list_remove; + } + + /* remove from configfs - outside the scope of the list mutex */ + mutex_unlock(&cscfg_mutex); + cscfg_fs_unregister_cfgs_feats(owner_info); + mutex_lock(&cscfg_mutex); + + /* Next unload from csdev lists. */ + cscfg_unload_owned_cfgs_feats(owner_info); + +list_remove: + /* remove from load order list */ + list_del(&owner_info->item); + } + mutex_unlock(&cscfg_mutex); +} + static void cscfg_clear_device(void) { - struct cscfg_config_desc *cfg_desc; - - mutex_lock(&cscfg_mutex); - list_for_each_entry(cfg_desc, &cscfg_mgr->config_desc_list, item) { - etm_perf_del_symlink_cscfg(cfg_desc); - } + cscfg_unload_cfgs_on_exit(); cscfg_configfs_release(cscfg_mgr); device_unregister(cscfg_device()); - mutex_unlock(&cscfg_mutex); } /* Initialise system config management API device */ @@ -1074,20 +1269,16 @@ int __init cscfg_init(void) { int err = 0; + /* create the device and init cscfg_mgr */ err = cscfg_create_device(); if (err) return err; + /* initialise configfs subsystem */ err = cscfg_configfs_init(cscfg_mgr); if (err) goto exit_err; - INIT_LIST_HEAD(&cscfg_mgr->csdev_desc_list); - INIT_LIST_HEAD(&cscfg_mgr->feat_desc_list); - INIT_LIST_HEAD(&cscfg_mgr->config_desc_list); - INIT_LIST_HEAD(&cscfg_mgr->load_order_list); - atomic_set(&cscfg_mgr->sys_active_cnt, 0); - /* preload built-in configurations */ err = cscfg_preload(THIS_MODULE); if (err) diff --git a/drivers/hwtracing/coresight/coresight-syscfg.h b/drivers/hwtracing/coresight/coresight-syscfg.h index 9106ffab4833..66e2db890d82 100644 --- a/drivers/hwtracing/coresight/coresight-syscfg.h +++ b/drivers/hwtracing/coresight/coresight-syscfg.h @@ -12,6 +12,17 @@ #include "coresight-config.h" +/* + * Load operation types. + * When loading or unloading, another load operation cannot be run. + * When unloading configurations cannot be activated. + */ +enum cscfg_load_ops { + CSCFG_NONE, + CSCFG_LOAD, + CSCFG_UNLOAD +}; + /** * System configuration manager device. * @@ -30,6 +41,7 @@ * @cfgfs_subsys: configfs subsystem used to manage configurations. * @sysfs_active_config:Active config hash used if CoreSight controlled from sysfs. * @sysfs_active_preset:Active preset index used if CoreSight controlled from sysfs. + * @load_state: A multi-stage load/unload operation is in progress. */ struct cscfg_manager { struct device dev; @@ -41,6 +53,7 @@ struct cscfg_manager { struct configfs_subsystem cfgfs_subsys; u32 sysfs_active_config; int sysfs_active_preset; + enum cscfg_load_ops load_state; }; /* get reference to dev in cscfg_manager */ diff --git a/drivers/hwtracing/intel_th/msu-sink.c b/drivers/hwtracing/intel_th/msu-sink.c index 2c7f5116be12..891b28ea25fe 100644 --- a/drivers/hwtracing/intel_th/msu-sink.c +++ b/drivers/hwtracing/intel_th/msu-sink.c @@ -71,6 +71,9 @@ static int msu_sink_alloc_window(void *data, struct sg_table **sgt, size_t size) block = dma_alloc_coherent(priv->dev->parent->parent, PAGE_SIZE, &sg_dma_address(sg_ptr), GFP_KERNEL); + if (!block) + return -ENOMEM; + sg_set_buf(sg_ptr, block, PAGE_SIZE); } diff --git a/drivers/hwtracing/intel_th/msu.c b/drivers/hwtracing/intel_th/msu.c index 70a07b4e9967..6c8215a47a60 100644 --- a/drivers/hwtracing/intel_th/msu.c +++ b/drivers/hwtracing/intel_th/msu.c @@ -1067,6 +1067,16 @@ msc_buffer_set_uc(struct msc *msc) {} static inline void msc_buffer_set_wb(struct msc *msc) {} #endif /* CONFIG_X86 */ +static struct page *msc_sg_page(struct scatterlist *sg) +{ + void *addr = sg_virt(sg); + + if (is_vmalloc_addr(addr)) + return vmalloc_to_page(addr); + + return sg_page(sg); +} + /** * msc_buffer_win_alloc() - alloc a window for a multiblock mode * @msc: MSC device @@ -1137,7 +1147,7 @@ static void __msc_buffer_win_free(struct msc *msc, struct msc_window *win) int i; for_each_sg(win->sgt->sgl, sg, win->nr_segs, i) { - struct page *page = sg_page(sg); + struct page *page = msc_sg_page(sg); page->mapping = NULL; dma_free_coherent(msc_dev(win->msc)->parent->parent, PAGE_SIZE, @@ -1401,7 +1411,7 @@ found: pgoff -= win->pgoff; for_each_sg(win->sgt->sgl, sg, win->nr_segs, blk) { - struct page *page = sg_page(sg); + struct page *page = msc_sg_page(sg); size_t pgsz = PFN_DOWN(sg->length); if (pgoff < pgsz) diff --git a/drivers/hwtracing/intel_th/pci.c b/drivers/hwtracing/intel_th/pci.c index 7da4f298ed01..147d338c191e 100644 --- a/drivers/hwtracing/intel_th/pci.c +++ b/drivers/hwtracing/intel_th/pci.c @@ -100,8 +100,10 @@ static int intel_th_pci_probe(struct pci_dev *pdev, } th = intel_th_alloc(&pdev->dev, drvdata, resource, r); - if (IS_ERR(th)) - return PTR_ERR(th); + if (IS_ERR(th)) { + err = PTR_ERR(th); + goto err_free_irq; + } th->activate = intel_th_pci_activate; th->deactivate = intel_th_pci_deactivate; @@ -109,6 +111,10 @@ static int intel_th_pci_probe(struct pci_dev *pdev, pci_set_master(pdev); return 0; + +err_free_irq: + pci_free_irq_vectors(pdev); + return err; } static void intel_th_pci_remove(struct pci_dev *pdev) @@ -278,6 +284,21 @@ static const struct pci_device_id intel_th_pci_id_table[] = { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x54a6), .driver_data = (kernel_ulong_t)&intel_th_2x, }, + { + /* Meteor Lake-P */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7e24), + .driver_data = (kernel_ulong_t)&intel_th_2x, + }, + { + /* Raptor Lake-S */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7a26), + .driver_data = (kernel_ulong_t)&intel_th_2x, + }, + { + /* Raptor Lake-S CPU */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa76f), + .driver_data = (kernel_ulong_t)&intel_th_2x, + }, { /* Alder Lake CPU */ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x466f), diff --git a/drivers/iio/accel/Kconfig b/drivers/iio/accel/Kconfig index b53f010f3e40..35798712f811 100644 --- a/drivers/iio/accel/Kconfig +++ b/drivers/iio/accel/Kconfig @@ -204,6 +204,8 @@ config BMA220 config BMA400 tristate "Bosch BMA400 3-Axis Accelerometer Driver" select REGMAP + select IIO_BUFFER + select IIO_TRIGGERED_BUFFER select BMA400_I2C if I2C select BMA400_SPI if SPI help diff --git a/drivers/iio/accel/adxl313_core.c b/drivers/iio/accel/adxl313_core.c index 9e4193e64765..afeef779e1d0 100644 --- a/drivers/iio/accel/adxl313_core.c +++ b/drivers/iio/accel/adxl313_core.c @@ -46,7 +46,7 @@ EXPORT_SYMBOL_NS_GPL(adxl313_writable_regs_table, IIO_ADXL313); struct adxl313_data { struct regmap *regmap; struct mutex lock; /* lock to protect transf_buf */ - __le16 transf_buf ____cacheline_aligned; + __le16 transf_buf __aligned(IIO_DMA_MINALIGN); }; static const int adxl313_odr_freqs[][2] = { diff --git a/drivers/iio/accel/adxl355_core.c b/drivers/iio/accel/adxl355_core.c index 7561399daef3..4bc648eac8b2 100644 --- a/drivers/iio/accel/adxl355_core.c +++ b/drivers/iio/accel/adxl355_core.c @@ -177,7 +177,7 @@ struct adxl355_data { u8 buf[14]; s64 ts; } buffer; - } ____cacheline_aligned; + } __aligned(IIO_DMA_MINALIGN); }; static int adxl355_set_op_mode(struct adxl355_data *data, diff --git a/drivers/iio/accel/adxl367.c b/drivers/iio/accel/adxl367.c index 0289ed8cf2c6..47feb375b70b 100644 --- a/drivers/iio/accel/adxl367.c +++ b/drivers/iio/accel/adxl367.c @@ -179,7 +179,7 @@ struct adxl367_state { unsigned int fifo_set_size; unsigned int fifo_watermark; - __be16 fifo_buf[ADXL367_FIFO_SIZE] ____cacheline_aligned; + __be16 fifo_buf[ADXL367_FIFO_SIZE] __aligned(IIO_DMA_MINALIGN); __be16 sample_buf; u8 act_threshold_buf[2]; u8 inact_time_buf[2]; @@ -447,21 +447,17 @@ static int adxl367_set_fifo_format(struct adxl367_state *st, fifo_format)); } -static int adxl367_set_fifo_samples(struct adxl367_state *st, - unsigned int fifo_watermark, - unsigned int fifo_set_size) +static int adxl367_set_fifo_watermark(struct adxl367_state *st, + unsigned int fifo_watermark) { - unsigned int fifo_samples = fifo_watermark * fifo_set_size; + unsigned int fifo_samples = fifo_watermark * st->fifo_set_size; unsigned int fifo_samples_h, fifo_samples_l; int ret; if (fifo_samples > ADXL367_FIFO_MAX_WATERMARK) fifo_samples = ADXL367_FIFO_MAX_WATERMARK; - if (fifo_set_size == 0) - return 0; - - fifo_samples /= fifo_set_size; + fifo_samples /= st->fifo_set_size; fifo_samples_h = FIELD_PREP(ADXL367_SAMPLES_H_MASK, FIELD_GET(ADXL367_SAMPLES_VAL_H_MASK, @@ -475,30 +471,8 @@ static int adxl367_set_fifo_samples(struct adxl367_state *st, if (ret) return ret; - return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_SAMPLES, - ADXL367_SAMPLES_L_MASK, fifo_samples_l); -} - -static int adxl367_set_fifo_set_size(struct adxl367_state *st, - unsigned int fifo_set_size) -{ - int ret; - - ret = adxl367_set_fifo_samples(st, st->fifo_watermark, fifo_set_size); - if (ret) - return ret; - - st->fifo_set_size = fifo_set_size; - - return 0; -} - -static int adxl367_set_fifo_watermark(struct adxl367_state *st, - unsigned int fifo_watermark) -{ - int ret; - - ret = adxl367_set_fifo_samples(st, fifo_watermark, st->fifo_set_size); + ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_SAMPLES, + ADXL367_SAMPLES_L_MASK, fifo_samples_l); if (ret) return ret; @@ -1276,14 +1250,11 @@ static int adxl367_update_scan_mode(struct iio_dev *indio_dev, { struct adxl367_state *st = iio_priv(indio_dev); enum adxl367_fifo_format fifo_format; - unsigned int fifo_set_size; int ret; if (!adxl367_find_mask_fifo_format(active_scan_mask, &fifo_format)) return -EINVAL; - fifo_set_size = bitmap_weight(active_scan_mask, indio_dev->masklength); - mutex_lock(&st->lock); ret = adxl367_set_measure_en(st, false); @@ -1294,11 +1265,12 @@ static int adxl367_update_scan_mode(struct iio_dev *indio_dev, if (ret) goto out; - ret = adxl367_set_fifo_set_size(st, fifo_set_size); + ret = adxl367_set_measure_en(st, true); if (ret) goto out; - ret = adxl367_set_measure_en(st, true); + st->fifo_set_size = bitmap_weight(active_scan_mask, + indio_dev->masklength); out: mutex_unlock(&st->lock); diff --git a/drivers/iio/accel/adxl367_spi.c b/drivers/iio/accel/adxl367_spi.c index 26dfc821ebbe..118c894015a5 100644 --- a/drivers/iio/accel/adxl367_spi.c +++ b/drivers/iio/accel/adxl367_spi.c @@ -9,6 +9,8 @@ #include #include +#include + #include "adxl367.h" #define ADXL367_SPI_WRITE_COMMAND 0x0A @@ -28,10 +30,10 @@ struct adxl367_spi_state { struct spi_transfer fifo_xfer[2]; /* - * DMA (thus cache coherency maintenance) requires the - * transfer buffers to live in their own cache lines. + * DMA (thus cache coherency maintenance) may require the + * transfer buffers live in their own cache lines. */ - u8 reg_write_tx_buf[1] ____cacheline_aligned; + u8 reg_write_tx_buf[1] __aligned(IIO_DMA_MINALIGN); u8 reg_read_tx_buf[2]; u8 fifo_tx_buf[1]; }; diff --git a/drivers/iio/accel/bma220_spi.c b/drivers/iio/accel/bma220_spi.c index 74024d7ce5ac..fcbd695e4654 100644 --- a/drivers/iio/accel/bma220_spi.c +++ b/drivers/iio/accel/bma220_spi.c @@ -67,7 +67,7 @@ struct bma220_data { /* Ensure timestamp is naturally aligned. */ s64 timestamp __aligned(8); } scan; - u8 tx_buf[2] ____cacheline_aligned; + u8 tx_buf[2] __aligned(IIO_DMA_MINALIGN); }; static const struct iio_chan_spec bma220_channels[] = { @@ -289,20 +289,20 @@ static int bma220_probe(struct spi_device *spi) return devm_iio_device_register(&spi->dev, indio_dev); } -static __maybe_unused int bma220_suspend(struct device *dev) +static int bma220_suspend(struct device *dev) { struct spi_device *spi = to_spi_device(dev); return bma220_power(spi, false); } -static __maybe_unused int bma220_resume(struct device *dev) +static int bma220_resume(struct device *dev) { struct spi_device *spi = to_spi_device(dev); return bma220_power(spi, true); } -static SIMPLE_DEV_PM_OPS(bma220_pm_ops, bma220_suspend, bma220_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(bma220_pm_ops, bma220_suspend, bma220_resume); static const struct spi_device_id bma220_spi_id[] = { {"bma220", 0}, @@ -318,7 +318,7 @@ MODULE_DEVICE_TABLE(spi, bma220_spi_id); static struct spi_driver bma220_driver = { .driver = { .name = "bma220_spi", - .pm = &bma220_pm_ops, + .pm = pm_sleep_ptr(&bma220_pm_ops), .acpi_match_table = bma220_acpi_id, }, .probe = bma220_probe, diff --git a/drivers/iio/accel/bma400.h b/drivers/iio/accel/bma400.h index c4c8d74155c2..e8f802a82300 100644 --- a/drivers/iio/accel/bma400.h +++ b/drivers/iio/accel/bma400.h @@ -39,6 +39,7 @@ #define BMA400_INT_STAT0_REG 0x0e #define BMA400_INT_STAT1_REG 0x0f #define BMA400_INT_STAT2_REG 0x10 +#define BMA400_INT12_MAP_REG 0x23 /* Temperature register */ #define BMA400_TEMP_DATA_REG 0x11 @@ -53,6 +54,9 @@ #define BMA400_STEP_CNT1_REG 0x16 #define BMA400_STEP_CNT3_REG 0x17 #define BMA400_STEP_STAT_REG 0x18 +#define BMA400_STEP_INT_MSK BIT(0) +#define BMA400_STEP_RAW_LEN 0x03 +#define BMA400_STEP_STAT_MASK GENMASK(9, 8) /* * Read-write configuration registers @@ -62,6 +66,13 @@ #define BMA400_ACC_CONFIG2_REG 0x1b #define BMA400_CMD_REG 0x7e +/* Interrupt registers */ +#define BMA400_INT_CONFIG0_REG 0x1f +#define BMA400_INT_CONFIG1_REG 0x20 +#define BMA400_INT1_MAP_REG 0x21 +#define BMA400_INT_IO_CTRL_REG 0x24 +#define BMA400_INT_DRDY_MSK BIT(7) + /* Chip ID of BMA 400 devices found in the chip ID register. */ #define BMA400_ID_REG_VAL 0x90 @@ -83,8 +94,38 @@ #define BMA400_ACC_ODR_MIN_WHOLE_HZ 25 #define BMA400_ACC_ODR_MIN_HZ 12 -#define BMA400_SCALE_MIN 38357 -#define BMA400_SCALE_MAX 306864 +/* Generic interrupts register */ +#define BMA400_GEN1INT_CONFIG0 0x3f +#define BMA400_GEN2INT_CONFIG0 0x4A +#define BMA400_GEN_CONFIG1_OFF 0x01 +#define BMA400_GEN_CONFIG2_OFF 0x02 +#define BMA400_GEN_CONFIG3_OFF 0x03 +#define BMA400_GEN_CONFIG31_OFF 0x04 +#define BMA400_INT_GEN1_MSK BIT(2) +#define BMA400_INT_GEN2_MSK BIT(3) +#define BMA400_GEN_HYST_MSK GENMASK(1, 0) + +/* + * BMA400_SCALE_MIN macro value represents m/s^2 for 1 LSB before + * converting to micro values for +-2g range. + * + * For +-2g - 1 LSB = 0.976562 milli g = 0.009576 m/s^2 + * For +-4g - 1 LSB = 1.953125 milli g = 0.019153 m/s^2 + * For +-16g - 1 LSB = 7.8125 milli g = 0.076614 m/s^2 + * + * The raw value which is used to select the different ranges is determined + * by the first bit set position from the scale value, so BMA400_SCALE_MIN + * should be odd. + * + * Scale values for +-2g, +-4g, +-8g and +-16g are populated into bma400_scales + * array by left shifting BMA400_SCALE_MIN. + * e.g.: + * To select +-2g = 9577 << 0 = raw value to write is 0. + * To select +-8g = 9577 << 2 = raw value to write is 2. + * To select +-16g = 9577 << 3 = raw value to write is 3. + */ +#define BMA400_SCALE_MIN 9577 +#define BMA400_SCALE_MAX 76617 #define BMA400_NUM_REGULATORS 2 #define BMA400_VDD_REGULATOR 0 @@ -92,8 +133,7 @@ extern const struct regmap_config bma400_regmap_config; -int bma400_probe(struct device *dev, struct regmap *regmap, const char *name); - -void bma400_remove(struct device *dev); +int bma400_probe(struct device *dev, struct regmap *regmap, int irq, + const char *name); #endif diff --git a/drivers/iio/accel/bma400_core.c b/drivers/iio/accel/bma400_core.c index 043002fe6f63..c31bdd9b168e 100644 --- a/drivers/iio/accel/bma400_core.c +++ b/drivers/iio/accel/bma400_core.c @@ -11,15 +11,24 @@ * - Create channel for sensor time */ +#include #include #include -#include -#include #include #include #include #include #include +#include + +#include + +#include +#include +#include +#include +#include +#include #include "bma400.h" @@ -46,11 +55,24 @@ enum bma400_power_mode { POWER_MODE_INVALID = 0x03, }; +enum bma400_scan { + BMA400_ACCL_X, + BMA400_ACCL_Y, + BMA400_ACCL_Z, + BMA400_TEMP, +}; + struct bma400_sample_freq { int hz; int uhz; }; +enum bma400_activity { + BMA400_STILL, + BMA400_WALKING, + BMA400_RUNNING, +}; + struct bma400_data { struct device *dev; struct regmap *regmap; @@ -61,6 +83,19 @@ struct bma400_data { struct bma400_sample_freq sample_freq; int oversampling_ratio; int scale; + struct iio_trigger *trig; + int steps_enabled; + bool step_event_en; + bool activity_event_en; + unsigned int generic_event_en; + /* Correct time stamp alignment */ + struct { + __le16 buff[3]; + u8 temperature; + s64 ts __aligned(8); + } buffer __aligned(IIO_DMA_MINALIGN); + __le16 status; + __be16 duration; }; static bool bma400_is_writable_reg(struct device *dev, unsigned int reg) @@ -152,7 +187,38 @@ static const struct iio_chan_spec_ext_info bma400_ext_info[] = { { } }; -#define BMA400_ACC_CHANNEL(_axis) { \ +static const struct iio_event_spec bma400_step_detect_event = { + .type = IIO_EV_TYPE_CHANGE, + .dir = IIO_EV_DIR_NONE, + .mask_separate = BIT(IIO_EV_INFO_ENABLE), +}; + +static const struct iio_event_spec bma400_activity_event = { + .type = IIO_EV_TYPE_CHANGE, + .dir = IIO_EV_DIR_NONE, + .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE), +}; + +static const struct iio_event_spec bma400_accel_event[] = { + { + .type = IIO_EV_TYPE_MAG, + .dir = IIO_EV_DIR_FALLING, + .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | + BIT(IIO_EV_INFO_PERIOD) | + BIT(IIO_EV_INFO_HYSTERESIS) | + BIT(IIO_EV_INFO_ENABLE), + }, + { + .type = IIO_EV_TYPE_MAG, + .dir = IIO_EV_DIR_RISING, + .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | + BIT(IIO_EV_INFO_PERIOD) | + BIT(IIO_EV_INFO_HYSTERESIS) | + BIT(IIO_EV_INFO_ENABLE), + }, +}; + +#define BMA400_ACC_CHANNEL(_index, _axis) { \ .type = IIO_ACCEL, \ .modified = 1, \ .channel2 = IIO_MOD_##_axis, \ @@ -164,17 +230,55 @@ static const struct iio_chan_spec_ext_info bma400_ext_info[] = { BIT(IIO_CHAN_INFO_SCALE) | \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .ext_info = bma400_ext_info, \ + .scan_index = _index, \ + .scan_type = { \ + .sign = 's', \ + .realbits = 12, \ + .storagebits = 16, \ + .endianness = IIO_LE, \ + }, \ + .event_spec = bma400_accel_event, \ + .num_event_specs = ARRAY_SIZE(bma400_accel_event) \ +} + +#define BMA400_ACTIVITY_CHANNEL(_chan2) { \ + .type = IIO_ACTIVITY, \ + .modified = 1, \ + .channel2 = _chan2, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ + .scan_index = -1, /* No buffer support */ \ + .event_spec = &bma400_activity_event, \ + .num_event_specs = 1, \ } static const struct iio_chan_spec bma400_channels[] = { - BMA400_ACC_CHANNEL(X), - BMA400_ACC_CHANNEL(Y), - BMA400_ACC_CHANNEL(Z), + BMA400_ACC_CHANNEL(0, X), + BMA400_ACC_CHANNEL(1, Y), + BMA400_ACC_CHANNEL(2, Z), { .type = IIO_TEMP, .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), + .scan_index = 3, + .scan_type = { + .sign = 's', + .realbits = 8, + .storagebits = 8, + .endianness = IIO_LE, + }, }, + { + .type = IIO_STEPS, + .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | + BIT(IIO_CHAN_INFO_ENABLE), + .scan_index = -1, /* No buffer support */ + .event_spec = &bma400_step_detect_event, + .num_event_specs = 1, + }, + BMA400_ACTIVITY_CHANNEL(IIO_MOD_STILL), + BMA400_ACTIVITY_CHANNEL(IIO_MOD_WALKING), + BMA400_ACTIVITY_CHANNEL(IIO_MOD_RUNNING), + IIO_CHAN_SOFT_TIMESTAMP(4), }; static int bma400_get_temp_reg(struct bma400_data *data, int *val, int *val2) @@ -542,6 +646,40 @@ static int bma400_set_power_mode(struct bma400_data *data, return 0; } +static int bma400_enable_steps(struct bma400_data *data, int val) +{ + int ret; + + if (data->steps_enabled == val) + return 0; + + ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG1_REG, + BMA400_STEP_INT_MSK, + FIELD_PREP(BMA400_STEP_INT_MSK, val ? 1 : 0)); + if (ret) + return ret; + data->steps_enabled = val; + return ret; +} + +static int bma400_get_steps_reg(struct bma400_data *data, int *val) +{ + u8 *steps_raw; + int ret; + + steps_raw = kmalloc(BMA400_STEP_RAW_LEN, GFP_KERNEL); + if (!steps_raw) + return -ENOMEM; + + ret = regmap_bulk_read(data->regmap, BMA400_STEP_CNT0_REG, + steps_raw, BMA400_STEP_RAW_LEN); + if (ret) + return ret; + *val = get_unaligned_le24(steps_raw); + kfree(steps_raw); + return IIO_VAL_INT; +} + static void bma400_init_tables(void) { int raw; @@ -560,6 +698,40 @@ static void bma400_init_tables(void) } } +static void bma400_regulators_disable(void *data_ptr) +{ + struct bma400_data *data = data_ptr; + + regulator_bulk_disable(ARRAY_SIZE(data->regulators), data->regulators); +} + +static void bma400_power_disable(void *data_ptr) +{ + struct bma400_data *data = data_ptr; + int ret; + + mutex_lock(&data->mutex); + ret = bma400_set_power_mode(data, POWER_MODE_SLEEP); + mutex_unlock(&data->mutex); + if (ret) + dev_warn(data->dev, "Failed to put device into sleep mode (%pe)\n", + ERR_PTR(ret)); +} + +static enum iio_modifier bma400_act_to_mod(enum bma400_activity activity) +{ + switch (activity) { + case BMA400_STILL: + return IIO_MOD_STILL; + case BMA400_WALKING: + return IIO_MOD_WALKING; + case BMA400_RUNNING: + return IIO_MOD_RUNNING; + default: + return IIO_NO_MOD; + } +} + static int bma400_init(struct bma400_data *data) { unsigned int val; @@ -569,13 +741,12 @@ static int bma400_init(struct bma400_data *data) ret = regmap_read(data->regmap, BMA400_CHIP_ID_REG, &val); if (ret) { dev_err(data->dev, "Failed to read chip id register\n"); - goto out; + return ret; } if (val != BMA400_ID_REG_VAL) { dev_err(data->dev, "Chip ID mismatch\n"); - ret = -ENODEV; - goto out; + return -ENODEV; } data->regulators[BMA400_VDD_REGULATOR].supply = "vdd"; @@ -589,27 +760,31 @@ static int bma400_init(struct bma400_data *data) "Failed to get regulators: %d\n", ret); - goto out; + return ret; } ret = regulator_bulk_enable(ARRAY_SIZE(data->regulators), data->regulators); if (ret) { dev_err(data->dev, "Failed to enable regulators: %d\n", ret); - goto out; + return ret; } + ret = devm_add_action_or_reset(data->dev, bma400_regulators_disable, data); + if (ret) + return ret; + ret = bma400_get_power_mode(data); if (ret) { dev_err(data->dev, "Failed to get the initial power-mode\n"); - goto err_reg_disable; + return ret; } if (data->power_mode != POWER_MODE_NORMAL) { ret = bma400_set_power_mode(data, POWER_MODE_NORMAL); if (ret) { dev_err(data->dev, "Failed to wake up the device\n"); - goto err_reg_disable; + return ret; } /* * TODO: The datasheet waits 1500us here in the example, but @@ -618,20 +793,28 @@ static int bma400_init(struct bma400_data *data) usleep_range(1500, 2000); } + ret = devm_add_action_or_reset(data->dev, bma400_power_disable, data); + if (ret) + return ret; + bma400_init_tables(); ret = bma400_get_accel_output_data_rate(data); if (ret) - goto err_reg_disable; + return ret; ret = bma400_get_accel_oversampling_ratio(data); if (ret) - goto err_reg_disable; + return ret; ret = bma400_get_accel_scale(data); if (ret) - goto err_reg_disable; + return ret; + /* Configure INT1 pin to open drain */ + ret = regmap_write(data->regmap, BMA400_INT_IO_CTRL_REG, 0x06); + if (ret) + return ret; /* * Once the interrupt engine is supported we might use the * data_src_reg, but for now ensure this is set to the @@ -639,12 +822,6 @@ static int bma400_init(struct bma400_data *data) * channel. */ return regmap_write(data->regmap, BMA400_ACC_CONFIG2_REG, 0x00); - -err_reg_disable: - regulator_bulk_disable(ARRAY_SIZE(data->regulators), - data->regulators); -out: - return ret; } static int bma400_read_raw(struct iio_dev *indio_dev, @@ -652,14 +829,37 @@ static int bma400_read_raw(struct iio_dev *indio_dev, int *val2, long mask) { struct bma400_data *data = iio_priv(indio_dev); + unsigned int activity; int ret; switch (mask) { case IIO_CHAN_INFO_PROCESSED: - mutex_lock(&data->mutex); - ret = bma400_get_temp_reg(data, val, val2); - mutex_unlock(&data->mutex); - return ret; + switch (chan->type) { + case IIO_TEMP: + mutex_lock(&data->mutex); + ret = bma400_get_temp_reg(data, val, val2); + mutex_unlock(&data->mutex); + return ret; + case IIO_STEPS: + return bma400_get_steps_reg(data, val); + case IIO_ACTIVITY: + ret = regmap_read(data->regmap, BMA400_STEP_STAT_REG, + &activity); + if (ret) + return ret; + /* + * The device does not support confidence value levels, + * so we will always have 100% for current activity and + * 0% for the others. + */ + if (chan->channel2 == bma400_act_to_mod(activity)) + *val = 100; + else + *val = 0; + return IIO_VAL_INT; + default: + return -EINVAL; + } case IIO_CHAN_INFO_RAW: mutex_lock(&data->mutex); ret = bma400_get_accel_reg(data, chan, val); @@ -700,6 +900,9 @@ static int bma400_read_raw(struct iio_dev *indio_dev, *val = data->oversampling_ratio; return IIO_VAL_INT; + case IIO_CHAN_INFO_ENABLE: + *val = data->steps_enabled; + return IIO_VAL_INT; default: return -EINVAL; } @@ -765,6 +968,11 @@ static int bma400_write_raw(struct iio_dev *indio_dev, ret = bma400_set_accel_oversampling_ratio(data, val); mutex_unlock(&data->mutex); return ret; + case IIO_CHAN_INFO_ENABLE: + mutex_lock(&data->mutex); + ret = bma400_enable_steps(data, val); + mutex_unlock(&data->mutex); + return ret; default: return -EINVAL; } @@ -781,19 +989,419 @@ static int bma400_write_raw_get_fmt(struct iio_dev *indio_dev, return IIO_VAL_INT_PLUS_MICRO; case IIO_CHAN_INFO_OVERSAMPLING_RATIO: return IIO_VAL_INT; + case IIO_CHAN_INFO_ENABLE: + return IIO_VAL_INT; default: return -EINVAL; } } +static int bma400_read_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir) +{ + struct bma400_data *data = iio_priv(indio_dev); + + switch (chan->type) { + case IIO_ACCEL: + switch (dir) { + case IIO_EV_DIR_RISING: + return FIELD_GET(BMA400_INT_GEN1_MSK, + data->generic_event_en); + case IIO_EV_DIR_FALLING: + return FIELD_GET(BMA400_INT_GEN2_MSK, + data->generic_event_en); + default: + return -EINVAL; + } + case IIO_STEPS: + return data->step_event_en; + case IIO_ACTIVITY: + return data->activity_event_en; + default: + return -EINVAL; + } +} + +static int bma400_steps_event_enable(struct bma400_data *data, int state) +{ + int ret; + + ret = bma400_enable_steps(data, 1); + if (ret) + return ret; + + ret = regmap_update_bits(data->regmap, BMA400_INT12_MAP_REG, + BMA400_STEP_INT_MSK, + FIELD_PREP(BMA400_STEP_INT_MSK, + state)); + if (ret) + return ret; + data->step_event_en = state; + return 0; +} + +static int bma400_activity_event_en(struct bma400_data *data, + enum iio_event_direction dir, + int state) +{ + int ret, reg, msk, value, field_value; + + switch (dir) { + case IIO_EV_DIR_RISING: + reg = BMA400_GEN1INT_CONFIG0; + msk = BMA400_INT_GEN1_MSK; + value = 2; + set_mask_bits(&field_value, BMA400_INT_GEN1_MSK, + FIELD_PREP(BMA400_INT_GEN1_MSK, state)); + break; + case IIO_EV_DIR_FALLING: + reg = BMA400_GEN2INT_CONFIG0; + msk = BMA400_INT_GEN2_MSK; + value = 0; + set_mask_bits(&field_value, BMA400_INT_GEN2_MSK, + FIELD_PREP(BMA400_INT_GEN2_MSK, state)); + break; + default: + return -EINVAL; + } + + /* Enabling all axis for interrupt evaluation */ + ret = regmap_write(data->regmap, reg, 0xF8); + if (ret) + return ret; + + /* OR combination of all axis for interrupt evaluation */ + ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG1_OFF, value); + if (ret) + return ret; + + /* Initial value to avoid interrupts while enabling*/ + ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG2_OFF, 0x0A); + if (ret) + return ret; + + /* Initial duration value to avoid interrupts while enabling*/ + ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG31_OFF, 0x0F); + if (ret) + return ret; + + ret = regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, msk, + field_value); + if (ret) + return ret; + + ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, msk, + field_value); + if (ret) + return ret; + + set_mask_bits(&data->generic_event_en, msk, field_value); + return 0; +} + +static int bma400_write_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, int state) +{ + struct bma400_data *data = iio_priv(indio_dev); + int ret; + + switch (chan->type) { + case IIO_ACCEL: + mutex_lock(&data->mutex); + ret = bma400_activity_event_en(data, dir, state); + mutex_unlock(&data->mutex); + return ret; + case IIO_STEPS: + mutex_lock(&data->mutex); + ret = bma400_steps_event_enable(data, state); + mutex_unlock(&data->mutex); + return ret; + case IIO_ACTIVITY: + mutex_lock(&data->mutex); + if (!data->step_event_en) { + ret = bma400_steps_event_enable(data, true); + if (ret) { + mutex_unlock(&data->mutex); + return ret; + } + } + data->activity_event_en = state; + mutex_unlock(&data->mutex); + return 0; + default: + return -EINVAL; + } +} + +static int get_gen_config_reg(enum iio_event_direction dir) +{ + switch (dir) { + case IIO_EV_DIR_FALLING: + return BMA400_GEN2INT_CONFIG0; + case IIO_EV_DIR_RISING: + return BMA400_GEN1INT_CONFIG0; + default: + return -EINVAL; + } +} + +static int bma400_read_event_value(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, + int *val, int *val2) +{ + struct bma400_data *data = iio_priv(indio_dev); + int ret, reg; + + switch (chan->type) { + case IIO_ACCEL: + reg = get_gen_config_reg(dir); + if (reg < 0) + return -EINVAL; + + *val2 = 0; + switch (info) { + case IIO_EV_INFO_VALUE: + ret = regmap_read(data->regmap, + reg + BMA400_GEN_CONFIG2_OFF, + val); + if (ret) + return ret; + return IIO_VAL_INT; + case IIO_EV_INFO_PERIOD: + mutex_lock(&data->mutex); + ret = regmap_bulk_read(data->regmap, + reg + BMA400_GEN_CONFIG3_OFF, + &data->duration, + sizeof(data->duration)); + if (ret) { + mutex_unlock(&data->mutex); + return ret; + } + *val = be16_to_cpu(data->duration); + mutex_unlock(&data->mutex); + return IIO_VAL_INT; + case IIO_EV_INFO_HYSTERESIS: + ret = regmap_read(data->regmap, reg, val); + if (ret) + return ret; + *val = FIELD_GET(BMA400_GEN_HYST_MSK, *val); + return IIO_VAL_INT; + default: + return -EINVAL; + } + default: + return -EINVAL; + } +} + +static int bma400_write_event_value(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, + int val, int val2) +{ + struct bma400_data *data = iio_priv(indio_dev); + int reg, ret; + + switch (chan->type) { + case IIO_ACCEL: + reg = get_gen_config_reg(dir); + if (reg < 0) + return -EINVAL; + + switch (info) { + case IIO_EV_INFO_VALUE: + if (val < 1 || val > 255) + return -EINVAL; + + return regmap_write(data->regmap, + reg + BMA400_GEN_CONFIG2_OFF, + val); + case IIO_EV_INFO_PERIOD: + if (val < 1 || val > 65535) + return -EINVAL; + + mutex_lock(&data->mutex); + put_unaligned_be16(val, &data->duration); + ret = regmap_bulk_write(data->regmap, + reg + BMA400_GEN_CONFIG3_OFF, + &data->duration, + sizeof(data->duration)); + mutex_unlock(&data->mutex); + return ret; + case IIO_EV_INFO_HYSTERESIS: + if (val < 0 || val > 3) + return -EINVAL; + + return regmap_update_bits(data->regmap, reg, + BMA400_GEN_HYST_MSK, + FIELD_PREP(BMA400_GEN_HYST_MSK, + val)); + default: + return -EINVAL; + } + default: + return -EINVAL; + } +} + +static int bma400_data_rdy_trigger_set_state(struct iio_trigger *trig, + bool state) +{ + struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); + struct bma400_data *data = iio_priv(indio_dev); + int ret; + + ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, + BMA400_INT_DRDY_MSK, + FIELD_PREP(BMA400_INT_DRDY_MSK, state)); + if (ret) + return ret; + + return regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, + BMA400_INT_DRDY_MSK, + FIELD_PREP(BMA400_INT_DRDY_MSK, state)); +} + +static const unsigned long bma400_avail_scan_masks[] = { + BIT(BMA400_ACCL_X) | BIT(BMA400_ACCL_Y) | BIT(BMA400_ACCL_Z), + BIT(BMA400_ACCL_X) | BIT(BMA400_ACCL_Y) | BIT(BMA400_ACCL_Z) + | BIT(BMA400_TEMP), + 0 +}; + static const struct iio_info bma400_info = { .read_raw = bma400_read_raw, .read_avail = bma400_read_avail, .write_raw = bma400_write_raw, .write_raw_get_fmt = bma400_write_raw_get_fmt, + .read_event_config = bma400_read_event_config, + .write_event_config = bma400_write_event_config, + .write_event_value = bma400_write_event_value, + .read_event_value = bma400_read_event_value, }; -int bma400_probe(struct device *dev, struct regmap *regmap, const char *name) +static const struct iio_trigger_ops bma400_trigger_ops = { + .set_trigger_state = &bma400_data_rdy_trigger_set_state, + .validate_device = &iio_trigger_validate_own_device, +}; + +static irqreturn_t bma400_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf = p; + struct iio_dev *indio_dev = pf->indio_dev; + struct bma400_data *data = iio_priv(indio_dev); + int ret, temp; + + /* Lock to protect the data->buffer */ + mutex_lock(&data->mutex); + + /* bulk read six registers, with the base being the LSB register */ + ret = regmap_bulk_read(data->regmap, BMA400_X_AXIS_LSB_REG, + &data->buffer.buff, sizeof(data->buffer.buff)); + if (ret) + goto unlock_err; + + if (test_bit(BMA400_TEMP, indio_dev->active_scan_mask)) { + ret = regmap_read(data->regmap, BMA400_TEMP_DATA_REG, &temp); + if (ret) + goto unlock_err; + + data->buffer.temperature = temp; + } + + iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer, + iio_get_time_ns(indio_dev)); + + mutex_unlock(&data->mutex); + iio_trigger_notify_done(indio_dev->trig); + return IRQ_HANDLED; + +unlock_err: + mutex_unlock(&data->mutex); + return IRQ_NONE; +} + +static irqreturn_t bma400_interrupt(int irq, void *private) +{ + struct iio_dev *indio_dev = private; + struct bma400_data *data = iio_priv(indio_dev); + s64 timestamp = iio_get_time_ns(indio_dev); + unsigned int act, ev_dir = IIO_EV_DIR_NONE; + int ret; + + /* Lock to protect the data->status */ + mutex_lock(&data->mutex); + ret = regmap_bulk_read(data->regmap, BMA400_INT_STAT0_REG, + &data->status, + sizeof(data->status)); + /* + * if none of the bit is set in the status register then it is + * spurious interrupt. + */ + if (ret || !data->status) + goto unlock_err; + + if (FIELD_GET(BMA400_INT_GEN1_MSK, le16_to_cpu(data->status))) + ev_dir = IIO_EV_DIR_RISING; + + if (FIELD_GET(BMA400_INT_GEN2_MSK, le16_to_cpu(data->status))) + ev_dir = IIO_EV_DIR_FALLING; + + if (ev_dir != IIO_EV_DIR_NONE) { + iio_push_event(indio_dev, + IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, + IIO_MOD_X_OR_Y_OR_Z, + IIO_EV_TYPE_MAG, ev_dir), + timestamp); + } + + if (FIELD_GET(BMA400_STEP_STAT_MASK, le16_to_cpu(data->status))) { + iio_push_event(indio_dev, + IIO_MOD_EVENT_CODE(IIO_STEPS, 0, IIO_NO_MOD, + IIO_EV_TYPE_CHANGE, + IIO_EV_DIR_NONE), + timestamp); + + if (data->activity_event_en) { + ret = regmap_read(data->regmap, BMA400_STEP_STAT_REG, + &act); + if (ret) + goto unlock_err; + + iio_push_event(indio_dev, + IIO_MOD_EVENT_CODE(IIO_ACTIVITY, 0, + bma400_act_to_mod(act), + IIO_EV_TYPE_CHANGE, + IIO_EV_DIR_NONE), + timestamp); + } + } + + if (FIELD_GET(BMA400_INT_DRDY_MSK, le16_to_cpu(data->status))) { + mutex_unlock(&data->mutex); + iio_trigger_poll_chained(data->trig); + return IRQ_HANDLED; + } + + mutex_unlock(&data->mutex); + return IRQ_HANDLED; + +unlock_err: + mutex_unlock(&data->mutex); + return IRQ_NONE; +} + +int bma400_probe(struct device *dev, struct regmap *regmap, int irq, + const char *name) { struct iio_dev *indio_dev; struct bma400_data *data; @@ -820,34 +1428,44 @@ int bma400_probe(struct device *dev, struct regmap *regmap, const char *name) indio_dev->info = &bma400_info; indio_dev->channels = bma400_channels; indio_dev->num_channels = ARRAY_SIZE(bma400_channels); + indio_dev->available_scan_masks = bma400_avail_scan_masks; indio_dev->modes = INDIO_DIRECT_MODE; - dev_set_drvdata(dev, indio_dev); + if (irq > 0) { + data->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", + indio_dev->name, + iio_device_id(indio_dev)); + if (!data->trig) + return -ENOMEM; - return iio_device_register(indio_dev); + data->trig->ops = &bma400_trigger_ops; + iio_trigger_set_drvdata(data->trig, indio_dev); + + ret = devm_iio_trigger_register(data->dev, data->trig); + if (ret) + return dev_err_probe(data->dev, ret, + "iio trigger register fail\n"); + + indio_dev->trig = iio_trigger_get(data->trig); + ret = devm_request_threaded_irq(dev, irq, NULL, + &bma400_interrupt, + IRQF_TRIGGER_RISING | IRQF_ONESHOT, + indio_dev->name, indio_dev); + if (ret) + return dev_err_probe(data->dev, ret, + "request irq %d failed\n", irq); + } + + ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, + &bma400_trigger_handler, NULL); + if (ret) + return dev_err_probe(data->dev, ret, + "iio triggered buffer setup failed\n"); + + return devm_iio_device_register(dev, indio_dev); } EXPORT_SYMBOL_NS(bma400_probe, IIO_BMA400); -void bma400_remove(struct device *dev) -{ - struct iio_dev *indio_dev = dev_get_drvdata(dev); - struct bma400_data *data = iio_priv(indio_dev); - int ret; - - mutex_lock(&data->mutex); - ret = bma400_set_power_mode(data, POWER_MODE_SLEEP); - mutex_unlock(&data->mutex); - - if (ret) - dev_warn(dev, "Failed to put device into sleep mode (%pe)\n", ERR_PTR(ret)); - - regulator_bulk_disable(ARRAY_SIZE(data->regulators), - data->regulators); - - iio_device_unregister(indio_dev); -} -EXPORT_SYMBOL_NS(bma400_remove, IIO_BMA400); - MODULE_AUTHOR("Dan Robertson "); MODULE_DESCRIPTION("Bosch BMA400 triaxial acceleration sensor core"); MODULE_LICENSE("GPL"); diff --git a/drivers/iio/accel/bma400_i2c.c b/drivers/iio/accel/bma400_i2c.c index da104ffd3fe0..1ba2a982ea73 100644 --- a/drivers/iio/accel/bma400_i2c.c +++ b/drivers/iio/accel/bma400_i2c.c @@ -24,14 +24,7 @@ static int bma400_i2c_probe(struct i2c_client *client, return PTR_ERR(regmap); } - return bma400_probe(&client->dev, regmap, id->name); -} - -static int bma400_i2c_remove(struct i2c_client *client) -{ - bma400_remove(&client->dev); - - return 0; + return bma400_probe(&client->dev, regmap, client->irq, id->name); } static const struct i2c_device_id bma400_i2c_ids[] = { @@ -52,7 +45,6 @@ static struct i2c_driver bma400_i2c_driver = { .of_match_table = bma400_of_i2c_match, }, .probe = bma400_i2c_probe, - .remove = bma400_i2c_remove, .id_table = bma400_i2c_ids, }; diff --git a/drivers/iio/accel/bma400_spi.c b/drivers/iio/accel/bma400_spi.c index 51f23bdc0ea5..ec13c044b304 100644 --- a/drivers/iio/accel/bma400_spi.c +++ b/drivers/iio/accel/bma400_spi.c @@ -84,12 +84,7 @@ static int bma400_spi_probe(struct spi_device *spi) if (ret) dev_err(&spi->dev, "Failed to read chip id register\n"); - return bma400_probe(&spi->dev, regmap, id->name); -} - -static void bma400_spi_remove(struct spi_device *spi) -{ - bma400_remove(&spi->dev); + return bma400_probe(&spi->dev, regmap, spi->irq, id->name); } static const struct spi_device_id bma400_spi_ids[] = { @@ -110,7 +105,6 @@ static struct spi_driver bma400_spi_driver = { .of_match_table = bma400_of_spi_match, }, .probe = bma400_spi_probe, - .remove = bma400_spi_remove, .id_table = bma400_spi_ids, }; diff --git a/drivers/iio/accel/bmi088-accel-core.c b/drivers/iio/accel/bmi088-accel-core.c index 8b2728bbcade..bca4cf98bf4d 100644 --- a/drivers/iio/accel/bmi088-accel-core.c +++ b/drivers/iio/accel/bmi088-accel-core.c @@ -6,6 +6,7 @@ * Copyright (c) 2018-2021, Topic Embedded Products */ +#include #include #include #include @@ -73,6 +74,8 @@ #define BMI088_ACCEL_FIFO_MODE_FIFO 0x40 #define BMI088_ACCEL_FIFO_MODE_STREAM 0x80 +#define BMIO088_ACCEL_ACC_RANGE_MSK GENMASK(1, 0) + enum bmi088_accel_axis { AXIS_X, AXIS_Y, @@ -119,12 +122,13 @@ struct bmi088_accel_chip_info { u8 chip_id; const struct iio_chan_spec *channels; int num_channels; + const int scale_table[4][2]; }; struct bmi088_accel_data { struct regmap *regmap; const struct bmi088_accel_chip_info *chip_info; - u8 buffer[2] ____cacheline_aligned; /* shared DMA safe buffer */ + u8 buffer[2] __aligned(IIO_DMA_MINALIGN); /* shared DMA safe buffer */ }; static const struct regmap_range bmi088_volatile_ranges[] = { @@ -236,6 +240,21 @@ static int bmi088_accel_set_sample_freq(struct bmi088_accel_data *data, int val) BMI088_ACCEL_MODE_ODR_MASK, regval); } +static int bmi088_accel_set_scale(struct bmi088_accel_data *data, int val, int val2) +{ + unsigned int i; + + for (i = 0; i < 4; i++) + if (val == data->chip_info->scale_table[i][0] && + val2 == data->chip_info->scale_table[i][1]) + break; + + if (i == 4) + return -EINVAL; + + return regmap_write(data->regmap, BMI088_ACCEL_REG_ACC_RANGE, i); +} + static int bmi088_accel_get_temp(struct bmi088_accel_data *data, int *val) { int ret; @@ -280,6 +299,7 @@ static int bmi088_accel_read_raw(struct iio_dev *indio_dev, struct bmi088_accel_data *data = iio_priv(indio_dev); struct device *dev = regmap_get_device(data->regmap); int ret; + int reg; switch (mask) { case IIO_CHAN_INFO_RAW: @@ -330,13 +350,14 @@ static int bmi088_accel_read_raw(struct iio_dev *indio_dev, return ret; ret = regmap_read(data->regmap, - BMI088_ACCEL_REG_ACC_RANGE, val); + BMI088_ACCEL_REG_ACC_RANGE, ®); if (ret) goto out_read_raw_pm_put; - *val2 = 15 - (*val & 0x3); - *val = 3 * 980; - ret = IIO_VAL_FRACTIONAL_LOG2; + reg = FIELD_GET(BMIO088_ACCEL_ACC_RANGE_MSK, reg); + *val = data->chip_info->scale_table[reg][0]; + *val2 = data->chip_info->scale_table[reg][1]; + ret = IIO_VAL_INT_PLUS_MICRO; goto out_read_raw_pm_put; default: @@ -367,7 +388,14 @@ static int bmi088_accel_read_avail(struct iio_dev *indio_dev, const int **vals, int *type, int *length, long mask) { + struct bmi088_accel_data *data = iio_priv(indio_dev); + switch (mask) { + case IIO_CHAN_INFO_SCALE: + *vals = (const int *)data->chip_info->scale_table; + *length = 8; + *type = IIO_VAL_INT_PLUS_MICRO; + return IIO_AVAIL_LIST; case IIO_CHAN_INFO_SAMP_FREQ: *type = IIO_VAL_INT_PLUS_MICRO; *vals = bmi088_sample_freqs; @@ -387,6 +415,15 @@ static int bmi088_accel_write_raw(struct iio_dev *indio_dev, int ret; switch (mask) { + case IIO_CHAN_INFO_SCALE: + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + ret = bmi088_accel_set_scale(data, val, val2); + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + return ret; case IIO_CHAN_INFO_SAMP_FREQ: ret = pm_runtime_resume_and_get(dev); if (ret) @@ -408,7 +445,8 @@ static int bmi088_accel_write_raw(struct iio_dev *indio_dev, .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT(IIO_CHAN_INFO_SAMP_FREQ), \ - .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ + BIT(IIO_CHAN_INFO_SCALE), \ .scan_index = AXIS_##_axis, \ } @@ -427,11 +465,26 @@ static const struct iio_chan_spec bmi088_accel_channels[] = { }; static const struct bmi088_accel_chip_info bmi088_accel_chip_info_tbl[] = { - [0] = { - .name = "bmi088a", + [BOSCH_BMI085] = { + .name = "bmi085-accel", + .chip_id = 0x1F, + .channels = bmi088_accel_channels, + .num_channels = ARRAY_SIZE(bmi088_accel_channels), + .scale_table = {{0, 598}, {0, 1196}, {0, 2393}, {0, 4785}}, + }, + [BOSCH_BMI088] = { + .name = "bmi088-accel", .chip_id = 0x1E, .channels = bmi088_accel_channels, .num_channels = ARRAY_SIZE(bmi088_accel_channels), + .scale_table = {{0, 897}, {0, 1794}, {0, 3589}, {0, 7178}}, + }, + [BOSCH_BMI090L] = { + .name = "bmi090l-accel", + .chip_id = 0x1A, + .channels = bmi088_accel_channels, + .num_channels = ARRAY_SIZE(bmi088_accel_channels), + .scale_table = {{0, 897}, {0, 1794}, {0, 3589}, {0, 7178}}, }, }; @@ -446,12 +499,15 @@ static const unsigned long bmi088_accel_scan_masks[] = { 0 }; -static int bmi088_accel_chip_init(struct bmi088_accel_data *data) +static int bmi088_accel_chip_init(struct bmi088_accel_data *data, enum bmi_device_type type) { struct device *dev = regmap_get_device(data->regmap); int ret, i; unsigned int val; + if (type >= BOSCH_UNKNOWN) + return -ENODEV; + /* Do a dummy read to enable SPI interface, won't harm I2C */ regmap_read(data->regmap, BMI088_ACCEL_REG_INT_STATUS, &val); @@ -477,22 +533,23 @@ static int bmi088_accel_chip_init(struct bmi088_accel_data *data) } /* Validate chip ID */ - for (i = 0; i < ARRAY_SIZE(bmi088_accel_chip_info_tbl); i++) { - if (bmi088_accel_chip_info_tbl[i].chip_id == val) { - data->chip_info = &bmi088_accel_chip_info_tbl[i]; + for (i = 0; i < ARRAY_SIZE(bmi088_accel_chip_info_tbl); i++) + if (bmi088_accel_chip_info_tbl[i].chip_id == val) break; - } - } - if (i == ARRAY_SIZE(bmi088_accel_chip_info_tbl)) { - dev_err(dev, "Invalid chip %x\n", val); - return -ENODEV; - } + + if (i == ARRAY_SIZE(bmi088_accel_chip_info_tbl)) + data->chip_info = &bmi088_accel_chip_info_tbl[type]; + else + data->chip_info = &bmi088_accel_chip_info_tbl[i]; + + if (i != type) + dev_warn(dev, "unexpected chip id 0x%X\n", val); return 0; } int bmi088_accel_core_probe(struct device *dev, struct regmap *regmap, - int irq, const char *name, bool block_supported) + int irq, enum bmi_device_type type) { struct bmi088_accel_data *data; struct iio_dev *indio_dev; @@ -507,13 +564,13 @@ int bmi088_accel_core_probe(struct device *dev, struct regmap *regmap, data->regmap = regmap; - ret = bmi088_accel_chip_init(data); + ret = bmi088_accel_chip_init(data, type); if (ret) return ret; indio_dev->channels = data->chip_info->channels; indio_dev->num_channels = data->chip_info->num_channels; - indio_dev->name = name ? name : data->chip_info->name; + indio_dev->name = data->chip_info->name; indio_dev->available_scan_masks = bmi088_accel_scan_masks; indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->info = &bmi088_accel_info; diff --git a/drivers/iio/accel/bmi088-accel-spi.c b/drivers/iio/accel/bmi088-accel-spi.c index 167c36cf1eb8..9e2ed3bd5661 100644 --- a/drivers/iio/accel/bmi088-accel-spi.c +++ b/drivers/iio/accel/bmi088-accel-spi.c @@ -52,8 +52,8 @@ static int bmi088_accel_probe(struct spi_device *spi) return PTR_ERR(regmap); } - return bmi088_accel_core_probe(&spi->dev, regmap, spi->irq, id->name, - true); + return bmi088_accel_core_probe(&spi->dev, regmap, spi->irq, + id->driver_data); } static void bmi088_accel_remove(struct spi_device *spi) @@ -61,8 +61,18 @@ static void bmi088_accel_remove(struct spi_device *spi) bmi088_accel_core_remove(&spi->dev); } +static const struct of_device_id bmi088_of_match[] = { + { .compatible = "bosch,bmi085-accel" }, + { .compatible = "bosch,bmi088-accel" }, + { .compatible = "bosch,bmi090l-accel" }, + {} +}; +MODULE_DEVICE_TABLE(of, bmi088_of_match); + static const struct spi_device_id bmi088_accel_id[] = { - {"bmi088-accel", }, + {"bmi085-accel", BOSCH_BMI085}, + {"bmi088-accel", BOSCH_BMI088}, + {"bmi090l-accel", BOSCH_BMI090L}, {} }; MODULE_DEVICE_TABLE(spi, bmi088_accel_id); @@ -71,6 +81,7 @@ static struct spi_driver bmi088_accel_driver = { .driver = { .name = "bmi088_accel_spi", .pm = &bmi088_accel_pm_ops, + .of_match_table = bmi088_of_match, }, .probe = bmi088_accel_probe, .remove = bmi088_accel_remove, diff --git a/drivers/iio/accel/bmi088-accel.h b/drivers/iio/accel/bmi088-accel.h index 5d40c7cf1cbc..80cd396a3141 100644 --- a/drivers/iio/accel/bmi088-accel.h +++ b/drivers/iio/accel/bmi088-accel.h @@ -8,11 +8,18 @@ struct device; +enum bmi_device_type { + BOSCH_BMI085, + BOSCH_BMI088, + BOSCH_BMI090L, + BOSCH_UNKNOWN, +}; + extern const struct regmap_config bmi088_regmap_conf; extern const struct dev_pm_ops bmi088_accel_pm_ops; int bmi088_accel_core_probe(struct device *dev, struct regmap *regmap, int irq, - const char *name, bool block_supported); + enum bmi_device_type type); void bmi088_accel_core_remove(struct device *dev); #endif /* BMI088_ACCEL_H */ diff --git a/drivers/iio/accel/cros_ec_accel_legacy.c b/drivers/iio/accel/cros_ec_accel_legacy.c index b6f3471b62dc..0f403342b1fc 100644 --- a/drivers/iio/accel/cros_ec_accel_legacy.c +++ b/drivers/iio/accel/cros_ec_accel_legacy.c @@ -215,7 +215,7 @@ static int cros_ec_accel_legacy_probe(struct platform_device *pdev) return -ENOMEM; ret = cros_ec_sensors_core_init(pdev, indio_dev, true, - cros_ec_sensors_capture, NULL); + cros_ec_sensors_capture); if (ret) return ret; @@ -230,12 +230,12 @@ static int cros_ec_accel_legacy_probe(struct platform_device *pdev) indio_dev->channels = cros_ec_accel_legacy_channels; indio_dev->num_channels = ARRAY_SIZE(cros_ec_accel_legacy_channels); /* The lid sensor needs to be presented inverted. */ - if (state->loc == MOTIONSENSE_LOC_LID) { + if (!strcmp(indio_dev->label, "accel-display")) { state->sign[CROS_EC_SENSOR_X] = -1; state->sign[CROS_EC_SENSOR_Z] = -1; } - return devm_iio_device_register(dev, indio_dev); + return cros_ec_sensors_core_register(dev, indio_dev, NULL); } static struct platform_driver cros_ec_accel_platform_driver = { diff --git a/drivers/iio/accel/kxsd9-i2c.c b/drivers/iio/accel/kxsd9-i2c.c index c8dc52f11037..d57f264bd6c8 100644 --- a/drivers/iio/accel/kxsd9-i2c.c +++ b/drivers/iio/accel/kxsd9-i2c.c @@ -55,7 +55,7 @@ static struct i2c_driver kxsd9_i2c_driver = { .driver = { .name = "kxsd9", .of_match_table = kxsd9_of_match, - .pm = &kxsd9_dev_pm_ops, + .pm = pm_ptr(&kxsd9_dev_pm_ops), }, .probe = kxsd9_i2c_probe, .remove = kxsd9_i2c_remove, diff --git a/drivers/iio/accel/kxsd9-spi.c b/drivers/iio/accel/kxsd9-spi.c index b7b5af45429e..07f14a9f22c7 100644 --- a/drivers/iio/accel/kxsd9-spi.c +++ b/drivers/iio/accel/kxsd9-spi.c @@ -52,7 +52,7 @@ MODULE_DEVICE_TABLE(of, kxsd9_of_match); static struct spi_driver kxsd9_spi_driver = { .driver = { .name = "kxsd9", - .pm = &kxsd9_dev_pm_ops, + .pm = pm_ptr(&kxsd9_dev_pm_ops), .of_match_table = kxsd9_of_match, }, .probe = kxsd9_spi_probe, diff --git a/drivers/iio/accel/kxsd9.c b/drivers/iio/accel/kxsd9.c index 3975860331a6..ba99649fe195 100644 --- a/drivers/iio/accel/kxsd9.c +++ b/drivers/iio/accel/kxsd9.c @@ -492,7 +492,6 @@ void kxsd9_common_remove(struct device *dev) } EXPORT_SYMBOL_NS(kxsd9_common_remove, IIO_KXSD9); -#ifdef CONFIG_PM static int kxsd9_runtime_suspend(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); @@ -508,15 +507,9 @@ static int kxsd9_runtime_resume(struct device *dev) return kxsd9_power_up(st); } -#endif /* CONFIG_PM */ -const struct dev_pm_ops kxsd9_dev_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, - pm_runtime_force_resume) - SET_RUNTIME_PM_OPS(kxsd9_runtime_suspend, - kxsd9_runtime_resume, NULL) -}; -EXPORT_SYMBOL_NS(kxsd9_dev_pm_ops, IIO_KXSD9); +EXPORT_NS_RUNTIME_DEV_PM_OPS(kxsd9_dev_pm_ops, kxsd9_runtime_suspend, + kxsd9_runtime_resume, NULL, IIO_KXSD9); MODULE_AUTHOR("Jonathan Cameron "); MODULE_DESCRIPTION("Kionix KXSD9 driver"); diff --git a/drivers/iio/accel/mc3230.c b/drivers/iio/accel/mc3230.c index 679e69cd7657..c15d16e7f1da 100644 --- a/drivers/iio/accel/mc3230.c +++ b/drivers/iio/accel/mc3230.c @@ -157,7 +157,9 @@ static int mc3230_remove(struct i2c_client *client) iio_device_unregister(indio_dev); - return mc3230_set_opcon(iio_priv(indio_dev), MC3230_MODE_OPCON_STANDBY); + mc3230_set_opcon(iio_priv(indio_dev), MC3230_MODE_OPCON_STANDBY); + + return 0; } static int mc3230_suspend(struct device *dev) diff --git a/drivers/iio/accel/mma7660.c b/drivers/iio/accel/mma7660.c index 112a5a33c29f..794f2f383303 100644 --- a/drivers/iio/accel/mma7660.c +++ b/drivers/iio/accel/mma7660.c @@ -7,8 +7,8 @@ * IIO driver for Freescale MMA7660FC; 7-bit I2C address: 0x4c. */ -#include #include +#include #include #include #include @@ -255,7 +255,7 @@ static const struct of_device_id mma7660_of_match[] = { }; MODULE_DEVICE_TABLE(of, mma7660_of_match); -static const struct acpi_device_id __maybe_unused mma7660_acpi_id[] = { +static const struct acpi_device_id mma7660_acpi_id[] = { {"MMA7660", 0}, {} }; @@ -267,7 +267,7 @@ static struct i2c_driver mma7660_driver = { .name = "mma7660", .pm = pm_sleep_ptr(&mma7660_pm_ops), .of_match_table = mma7660_of_match, - .acpi_match_table = ACPI_PTR(mma7660_acpi_id), + .acpi_match_table = mma7660_acpi_id, }, .probe = mma7660_probe, .remove = mma7660_remove, diff --git a/drivers/iio/accel/sca3000.c b/drivers/iio/accel/sca3000.c index 29a68a7d34cd..87c54e41f6cc 100644 --- a/drivers/iio/accel/sca3000.c +++ b/drivers/iio/accel/sca3000.c @@ -167,8 +167,8 @@ struct sca3000_state { int mo_det_use_count; struct mutex lock; /* Can these share a cacheline ? */ - u8 rx[384] ____cacheline_aligned; - u8 tx[6] ____cacheline_aligned; + u8 rx[384] __aligned(IIO_DMA_MINALIGN); + u8 tx[6] __aligned(IIO_DMA_MINALIGN); }; /** @@ -424,7 +424,7 @@ error_ret: * sca3000_print_rev() - sysfs interface to read the chip revision number * @indio_dev: Device instance specific generic IIO data. * Driver specific device instance data can be obtained via - * via iio_priv(indio_dev) + * iio_priv(indio_dev) */ static int sca3000_print_rev(struct iio_dev *indio_dev) { diff --git a/drivers/iio/accel/sca3300.c b/drivers/iio/accel/sca3300.c index f7ef8ecfd34a..eaa0c9cfda44 100644 --- a/drivers/iio/accel/sca3300.c +++ b/drivers/iio/accel/sca3300.c @@ -38,19 +38,35 @@ /* Device ID */ #define SCA3300_REG_WHOAMI 0x10 #define SCA3300_WHOAMI_ID 0x51 +#define SCL3300_WHOAMI_ID 0xC1 /* Device return status and mask */ #define SCA3300_VALUE_RS_ERROR 0x3 #define SCA3300_MASK_RS_STATUS GENMASK(1, 0) +#define SCL3300_REG_ANG_CTRL 0x0C +#define SCL3300_ANG_ENABLE 0x1F + enum sca3300_scan_indexes { SCA3300_ACC_X = 0, SCA3300_ACC_Y, SCA3300_ACC_Z, SCA3300_TEMP, - SCA3300_TIMESTAMP, + SCA3300_INCLI_X, + SCA3300_INCLI_Y, + SCA3300_INCLI_Z, + SCA3300_SCAN_MAX }; +/* + * Buffer size max case: + * Three accel channels, two bytes per channel. + * Temperature channel, two bytes. + * Three incli channels, two bytes per channel. + * Timestamp channel, eight bytes. + */ +#define SCA3300_MAX_BUFFER_SIZE (ALIGN(sizeof(s16) * SCA3300_SCAN_MAX, sizeof(s64)) + sizeof(s64)) + #define SCA3300_ACCEL_CHANNEL(index, reg, axis) { \ .type = IIO_ACCEL, \ .address = reg, \ @@ -72,27 +88,72 @@ enum sca3300_scan_indexes { }, \ } +#define SCA3300_INCLI_CHANNEL(index, reg, axis) { \ + .type = IIO_INCLI, \ + .address = reg, \ + .modified = 1, \ + .channel2 = IIO_MOD_##axis, \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \ + .scan_index = index, \ + .scan_type = { \ + .sign = 's', \ + .realbits = 16, \ + .storagebits = 16, \ + .endianness = IIO_CPU, \ + }, \ +} + +#define SCA3300_TEMP_CHANNEL(index, reg) { \ + .type = IIO_TEMP, \ + .address = reg, \ + .scan_index = index, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .scan_type = { \ + .sign = 's', \ + .realbits = 16, \ + .storagebits = 16, \ + .endianness = IIO_CPU, \ + }, \ +} + static const struct iio_chan_spec sca3300_channels[] = { SCA3300_ACCEL_CHANNEL(SCA3300_ACC_X, 0x1, X), SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Y, 0x2, Y), SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Z, 0x3, Z), - { - .type = IIO_TEMP, - .address = 0x5, - .scan_index = SCA3300_TEMP, - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), - .scan_type = { - .sign = 's', - .realbits = 16, - .storagebits = 16, - .endianness = IIO_CPU, - }, - }, + SCA3300_TEMP_CHANNEL(SCA3300_TEMP, 0x05), IIO_CHAN_SOFT_TIMESTAMP(4), }; -static const int sca3300_lp_freq[] = {70, 70, 70, 10}; -static const int sca3300_accel_scale[][2] = {{0, 370}, {0, 741}, {0, 185}, {0, 185}}; +static const int sca3300_lp_freq[] = {70, 10}; +static const int sca3300_lp_freq_map[] = {0, 0, 0, 1}; + +static const int scl3300_lp_freq[] = {40, 70, 10}; +static const int scl3300_lp_freq_map[] = {0, 1, 2}; + +static const int sca3300_accel_scale[][2] = {{0, 370}, {0, 741}, {0, 185}}; +static const int sca3300_accel_scale_map[] = {0, 1, 2, 2}; + +static const int scl3300_accel_scale[][2] = {{0, 167}, {0, 333}, {0, 83}}; +static const int scl3300_accel_scale_map[] = {0, 1, 2}; + +static const int scl3300_incli_scale[][2] = {{0, 5495}}; +static const int scl3300_incli_scale_map[] = {0, 0, 0}; + +static const int sca3300_avail_modes_map[] = {0, 1, 2, 3}; +static const int scl3300_avail_modes_map[] = {0, 1, 3}; + +static const struct iio_chan_spec scl3300_channels[] = { + SCA3300_ACCEL_CHANNEL(SCA3300_ACC_X, 0x1, X), + SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Y, 0x2, Y), + SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Z, 0x3, Z), + SCA3300_TEMP_CHANNEL(SCA3300_TEMP, 0x05), + SCA3300_INCLI_CHANNEL(SCA3300_INCLI_X, 0x09, X), + SCA3300_INCLI_CHANNEL(SCA3300_INCLI_Y, 0x0A, Y), + SCA3300_INCLI_CHANNEL(SCA3300_INCLI_Z, 0x0B, Z), + IIO_CHAN_SOFT_TIMESTAMP(7), +}; static const unsigned long sca3300_scan_masks[] = { BIT(SCA3300_ACC_X) | BIT(SCA3300_ACC_Y) | BIT(SCA3300_ACC_Z) | @@ -100,25 +161,91 @@ static const unsigned long sca3300_scan_masks[] = { 0 }; +static const unsigned long scl3300_scan_masks[] = { + BIT(SCA3300_ACC_X) | BIT(SCA3300_ACC_Y) | BIT(SCA3300_ACC_Z) | + BIT(SCA3300_TEMP) | + BIT(SCA3300_INCLI_X) | BIT(SCA3300_INCLI_Y) | BIT(SCA3300_INCLI_Z), + 0 +}; + +struct sca3300_chip_info { + const char *name; + const unsigned long *scan_masks; + const struct iio_chan_spec *channels; + u8 num_channels; + u8 num_accel_scales; + const int (*accel_scale)[2]; + const int *accel_scale_map; + const int (*incli_scale)[2]; + const int *incli_scale_map; + u8 num_incli_scales; + u8 num_freqs; + const int *freq_table; + const int *freq_map; + const int *avail_modes_table; + u8 num_avail_modes; + u8 chip_id; + bool angle_supported; +}; + /** * struct sca3300_data - device data * @spi: SPI device structure * @lock: Data buffer lock - * @scan: Triggered buffer. Four channel 16-bit data + 64-bit timestamp + * @chip: Sensor chip specific information + * @buffer: Triggered buffer: + * -SCA3300: 4 channel 16-bit data + 64-bit timestamp + * -SCL3300: 7 channel 16-bit data + 64-bit timestamp * @txbuf: Transmit buffer * @rxbuf: Receive buffer */ struct sca3300_data { struct spi_device *spi; struct mutex lock; - struct { - s16 channels[4]; - s64 ts __aligned(sizeof(s64)); - } scan; - u8 txbuf[4] ____cacheline_aligned; + const struct sca3300_chip_info *chip; + u8 buffer[SCA3300_MAX_BUFFER_SIZE] __aligned(sizeof(s64)); + u8 txbuf[4] __aligned(IIO_DMA_MINALIGN); u8 rxbuf[4]; }; +static const struct sca3300_chip_info sca3300_chip_tbl[] = { + { + .name = "sca3300", + .scan_masks = sca3300_scan_masks, + .channels = sca3300_channels, + .num_channels = ARRAY_SIZE(sca3300_channels), + .num_accel_scales = ARRAY_SIZE(sca3300_accel_scale)*2, + .accel_scale = sca3300_accel_scale, + .accel_scale_map = sca3300_accel_scale_map, + .num_freqs = ARRAY_SIZE(sca3300_lp_freq), + .freq_table = sca3300_lp_freq, + .freq_map = sca3300_lp_freq_map, + .avail_modes_table = sca3300_avail_modes_map, + .num_avail_modes = 4, + .chip_id = SCA3300_WHOAMI_ID, + .angle_supported = false, + }, + { + .name = "scl3300", + .scan_masks = scl3300_scan_masks, + .channels = scl3300_channels, + .num_channels = ARRAY_SIZE(scl3300_channels), + .num_accel_scales = ARRAY_SIZE(scl3300_accel_scale)*2, + .accel_scale = scl3300_accel_scale, + .accel_scale_map = scl3300_accel_scale_map, + .incli_scale = scl3300_incli_scale, + .incli_scale_map = scl3300_incli_scale_map, + .num_incli_scales = ARRAY_SIZE(scl3300_incli_scale)*2, + .num_freqs = ARRAY_SIZE(scl3300_lp_freq), + .freq_table = scl3300_lp_freq, + .freq_map = scl3300_lp_freq_map, + .avail_modes_table = scl3300_avail_modes_map, + .num_avail_modes = 3, + .chip_id = SCL3300_WHOAMI_ID, + .angle_supported = true, + }, +}; + DECLARE_CRC8_TABLE(sca3300_crc_table); static int sca3300_transfer(struct sca3300_data *sca_data, int *val) @@ -225,36 +352,91 @@ static int sca3300_write_reg(struct sca3300_data *sca_data, u8 reg, int val) return sca3300_error_handler(sca_data); } +static int sca3300_set_op_mode(struct sca3300_data *sca_data, int index) +{ + if ((index < 0) || (index >= sca_data->chip->num_avail_modes)) + return -EINVAL; + + return sca3300_write_reg(sca_data, SCA3300_REG_MODE, + sca_data->chip->avail_modes_table[index]); +} + +static int sca3300_get_op_mode(struct sca3300_data *sca_data, int *index) +{ + int reg_val; + int ret; + int i; + + ret = sca3300_read_reg(sca_data, SCA3300_REG_MODE, ®_val); + if (ret) + return ret; + + for (i = 0; i < sca_data->chip->num_avail_modes; i++) { + if (sca_data->chip->avail_modes_table[i] == reg_val) + break; + } + if (i == sca_data->chip->num_avail_modes) + return -EINVAL; + + *index = i; + return 0; +} + +static int sca3300_set_frequency(struct sca3300_data *data, int val) +{ + const struct sca3300_chip_info *chip = data->chip; + unsigned int index; + int *opmode_scale; + int *new_scale; + unsigned int i; + + if (sca3300_get_op_mode(data, &index)) + return -EINVAL; + + /* + * Find a mode in which the requested sampling frequency is available + * and the scaling currently set is retained. + */ + opmode_scale = (int *)chip->accel_scale[chip->accel_scale_map[index]]; + for (i = 0; i < chip->num_avail_modes; i++) { + new_scale = (int *)chip->accel_scale[chip->accel_scale_map[i]]; + if ((val == chip->freq_table[chip->freq_map[i]]) && + (opmode_scale[1] == new_scale[1]) && + (opmode_scale[0] == new_scale[0])) + break; + } + if (i == chip->num_avail_modes) + return -EINVAL; + + return sca3300_set_op_mode(data, i); +} + static int sca3300_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) { struct sca3300_data *data = iio_priv(indio_dev); - int reg_val; - int ret; + int index; int i; switch (mask) { case IIO_CHAN_INFO_SCALE: - if (val) + if (chan->type != IIO_ACCEL) return -EINVAL; - - for (i = 0; i < ARRAY_SIZE(sca3300_accel_scale); i++) { - if (val2 == sca3300_accel_scale[i][1]) - return sca3300_write_reg(data, SCA3300_REG_MODE, i); + /* + * Letting scale take priority over sampling frequency. + * That makes sense given we can only ever end up increasing + * the sampling frequency which is unlikely to be a problem. + */ + for (i = 0; i < data->chip->num_avail_modes; i++) { + index = data->chip->accel_scale_map[i]; + if ((val == data->chip->accel_scale[index][0]) && + (val2 == data->chip->accel_scale[index][1])) + return sca3300_set_op_mode(data, i); } return -EINVAL; - case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: - ret = sca3300_read_reg(data, SCA3300_REG_MODE, ®_val); - if (ret) - return ret; - /* freq. change is possible only for mode 3 and 4 */ - if (reg_val == 2 && val == sca3300_lp_freq[3]) - return sca3300_write_reg(data, SCA3300_REG_MODE, 3); - if (reg_val == 3 && val == sca3300_lp_freq[2]) - return sca3300_write_reg(data, SCA3300_REG_MODE, 2); - return -EINVAL; + return sca3300_set_frequency(data, val); default: return -EINVAL; } @@ -265,8 +447,8 @@ static int sca3300_read_raw(struct iio_dev *indio_dev, int *val, int *val2, long mask) { struct sca3300_data *data = iio_priv(indio_dev); + int index; int ret; - int reg_val; switch (mask) { case IIO_CHAN_INFO_RAW: @@ -275,17 +457,29 @@ static int sca3300_read_raw(struct iio_dev *indio_dev, return ret; return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: - ret = sca3300_read_reg(data, SCA3300_REG_MODE, ®_val); + ret = sca3300_get_op_mode(data, &index); if (ret) return ret; - *val = 0; - *val2 = sca3300_accel_scale[reg_val][1]; - return IIO_VAL_INT_PLUS_MICRO; + switch (chan->type) { + case IIO_INCLI: + index = data->chip->incli_scale_map[index]; + *val = data->chip->incli_scale[index][0]; + *val2 = data->chip->incli_scale[index][1]; + return IIO_VAL_INT_PLUS_MICRO; + case IIO_ACCEL: + index = data->chip->accel_scale_map[index]; + *val = data->chip->accel_scale[index][0]; + *val2 = data->chip->accel_scale[index][1]; + return IIO_VAL_INT_PLUS_MICRO; + default: + return -EINVAL; + } case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: - ret = sca3300_read_reg(data, SCA3300_REG_MODE, ®_val); + ret = sca3300_get_op_mode(data, &index); if (ret) return ret; - *val = sca3300_lp_freq[reg_val]; + index = data->chip->freq_map[index]; + *val = data->chip->freq_table[index]; return IIO_VAL_INT; default: return -EINVAL; @@ -298,21 +492,21 @@ static irqreturn_t sca3300_trigger_handler(int irq, void *p) struct iio_dev *indio_dev = pf->indio_dev; struct sca3300_data *data = iio_priv(indio_dev); int bit, ret, val, i = 0; + s16 *channels = (s16 *)data->buffer; for_each_set_bit(bit, indio_dev->active_scan_mask, indio_dev->masklength) { - ret = sca3300_read_reg(data, sca3300_channels[bit].address, - &val); + ret = sca3300_read_reg(data, indio_dev->channels[bit].address, &val); if (ret) { dev_err_ratelimited(&data->spi->dev, "failed to read register, error: %d\n", ret); /* handled, but bailing out due to errors */ goto out; } - data->scan.channels[i++] = val; + channels[i++] = val; } - iio_push_to_buffers_with_timestamp(indio_dev, &data->scan, + iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, iio_get_time_ns(indio_dev)); out: iio_trigger_notify_done(indio_dev->trig); @@ -329,6 +523,7 @@ static int sca3300_init(struct sca3300_data *sca_data, { int value = 0; int ret; + int i; ret = sca3300_write_reg(sca_data, SCA3300_REG_MODE, SCA3300_MODE_SW_RESET); @@ -337,20 +532,33 @@ static int sca3300_init(struct sca3300_data *sca_data, /* * Wait 1ms after SW-reset command. - * Wait 15ms for settling of signal paths. + * Wait for the settling of signal paths, + * 15ms for SCA3300 and 25ms for SCL3300, */ - usleep_range(16e3, 50e3); + usleep_range(26e3, 50e3); ret = sca3300_read_reg(sca_data, SCA3300_REG_WHOAMI, &value); if (ret) return ret; - if (value != SCA3300_WHOAMI_ID) { - dev_err(&sca_data->spi->dev, - "device id not expected value, %d != %u\n", - value, SCA3300_WHOAMI_ID); + for (i = 0; i < ARRAY_SIZE(sca3300_chip_tbl); i++) { + if (sca3300_chip_tbl[i].chip_id == value) + break; + } + if (i == ARRAY_SIZE(sca3300_chip_tbl)) { + dev_err(&sca_data->spi->dev, "unknown chip id %x\n", value); return -ENODEV; } + + sca_data->chip = &sca3300_chip_tbl[i]; + + if (sca_data->chip->angle_supported) { + ret = sca3300_write_reg(sca_data, SCL3300_REG_ANG_CTRL, + SCL3300_ANG_ENABLE); + if (ret) + return ret; + } + return 0; } @@ -382,15 +590,26 @@ static int sca3300_read_avail(struct iio_dev *indio_dev, const int **vals, int *type, int *length, long mask) { + struct sca3300_data *data = iio_priv(indio_dev); switch (mask) { case IIO_CHAN_INFO_SCALE: - *vals = (const int *)sca3300_accel_scale; - *length = ARRAY_SIZE(sca3300_accel_scale) * 2 - 2; - *type = IIO_VAL_INT_PLUS_MICRO; - return IIO_AVAIL_LIST; + switch (chan->type) { + case IIO_INCLI: + *vals = (const int *)data->chip->incli_scale; + *length = data->chip->num_incli_scales; + *type = IIO_VAL_INT_PLUS_MICRO; + return IIO_AVAIL_LIST; + case IIO_ACCEL: + *vals = (const int *)data->chip->accel_scale; + *length = data->chip->num_accel_scales; + *type = IIO_VAL_INT_PLUS_MICRO; + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: - *vals = &sca3300_lp_freq[2]; - *length = 2; + *vals = (const int *)data->chip->freq_table; + *length = data->chip->num_freqs; *type = IIO_VAL_INT; return IIO_AVAIL_LIST; default: @@ -422,11 +641,6 @@ static int sca3300_probe(struct spi_device *spi) crc8_populate_msb(sca3300_crc_table, SCA3300_CRC8_POLYNOMIAL); indio_dev->info = &sca3300_info; - indio_dev->name = SCA3300_ALIAS; - indio_dev->modes = INDIO_DIRECT_MODE; - indio_dev->channels = sca3300_channels; - indio_dev->num_channels = ARRAY_SIZE(sca3300_channels); - indio_dev->available_scan_masks = sca3300_scan_masks; ret = sca3300_init(sca_data, indio_dev); if (ret) { @@ -434,6 +648,12 @@ static int sca3300_probe(struct spi_device *spi) return ret; } + indio_dev->name = sca_data->chip->name; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->channels = sca_data->chip->channels; + indio_dev->num_channels = sca_data->chip->num_channels; + indio_dev->available_scan_masks = sca_data->chip->scan_masks; + ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, iio_pollfunc_store_time, sca3300_trigger_handler, NULL); @@ -454,6 +674,7 @@ static int sca3300_probe(struct spi_device *spi) static const struct of_device_id sca3300_dt_ids[] = { { .compatible = "murata,sca3300"}, + { .compatible = "murata,scl3300"}, {} }; MODULE_DEVICE_TABLE(of, sca3300_dt_ids); diff --git a/drivers/iio/accel/stk8312.c b/drivers/iio/accel/stk8312.c index a71dfff3ca4a..ceca28913355 100644 --- a/drivers/iio/accel/stk8312.c +++ b/drivers/iio/accel/stk8312.c @@ -608,7 +608,9 @@ static int stk8312_remove(struct i2c_client *client) if (data->dready_trig) iio_trigger_unregister(data->dready_trig); - return stk8312_set_mode(data, STK8312_MODE_STANDBY); + stk8312_set_mode(data, STK8312_MODE_STANDBY); + + return 0; } static int stk8312_suspend(struct device *dev) diff --git a/drivers/iio/accel/stk8ba50.c b/drivers/iio/accel/stk8ba50.c index 0067ec5cbae8..7d59efb41e22 100644 --- a/drivers/iio/accel/stk8ba50.c +++ b/drivers/iio/accel/stk8ba50.c @@ -501,7 +501,9 @@ static int stk8ba50_remove(struct i2c_client *client) if (data->dready_trig) iio_trigger_unregister(data->dready_trig); - return stk8ba50_set_power(data, STK8BA50_MODE_SUSPEND); + stk8ba50_set_power(data, STK8BA50_MODE_SUSPEND); + + return 0; } static int stk8ba50_suspend(struct device *dev) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 48ace7412874..7fe5930891e0 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -417,7 +417,6 @@ config DLN2_ADC config ENVELOPE_DETECTOR tristate "Envelope detector using a DAC and a comparator" - depends on OF help Say yes here to build support for an envelope detector using a DAC and a comparator. @@ -563,7 +562,7 @@ config LP8788_ADC config LPC18XX_ADC tristate "NXP LPC18xx ADC driver" depends on ARCH_LPC18XX || COMPILE_TEST - depends on OF && HAS_IOMEM + depends on HAS_IOMEM help Say yes here to build support for NXP LPC18XX ADC. @@ -823,6 +822,18 @@ config QCOM_PM8XXX_XOADC To compile this driver as a module, choose M here: the module will be called qcom-pm8xxx-xoadc. +config QCOM_SPMI_RRADC + tristate "Qualcomm SPMI RRADC" + depends on MFD_SPMI_PMIC + help + This is for the PMIC Round Robin ADC driver. + + This driver exposes the battery ID resistor, battery thermal, PMIC die + temperature, charger USB in and DC in voltage and current. + + To compile this driver as a module, choose M here: the module will + be called qcom-qpmi-rradc. + config QCOM_SPMI_IADC tristate "Qualcomm SPMI PMIC current ADC" depends on SPMI @@ -941,7 +952,6 @@ config SPEAR_ADC config SD_ADC_MODULATOR tristate "Generic sigma delta modulator" - depends on OF select IIO_BUFFER select IIO_TRIGGERED_BUFFER help @@ -1259,7 +1269,6 @@ config TWL6030_GPADC config VF610_ADC tristate "Freescale vf610 ADC driver" - depends on OF depends on HAS_IOMEM select IIO_BUFFER select IIO_TRIGGERED_BUFFER diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 39d806f6d457..1772a549a3c8 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -78,6 +78,7 @@ obj-$(CONFIG_NPCM_ADC) += npcm_adc.o obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o obj-$(CONFIG_QCOM_SPMI_ADC5) += qcom-spmi-adc5.o obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o +obj-$(CONFIG_QCOM_SPMI_RRADC) += qcom-spmi-rradc.o obj-$(CONFIG_QCOM_VADC_COMMON) += qcom-vadc-common.o obj-$(CONFIG_QCOM_SPMI_VADC) += qcom-spmi-vadc.o obj-$(CONFIG_QCOM_PM8XXX_XOADC) += qcom-pm8xxx-xoadc.o diff --git a/drivers/iio/adc/ad7266.c b/drivers/iio/adc/ad7266.c index f20d39f0bc01..468c2656d2be 100644 --- a/drivers/iio/adc/ad7266.c +++ b/drivers/iio/adc/ad7266.c @@ -37,7 +37,7 @@ struct ad7266_state { struct gpio_desc *gpios[3]; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. * The buffer needs to be large enough to hold two samples (4 bytes) and * the naturally aligned timestamp (8 bytes). @@ -45,7 +45,7 @@ struct ad7266_state { struct { __be16 sample[2]; s64 timestamp; - } data ____cacheline_aligned; + } data __aligned(IIO_DMA_MINALIGN); }; static int ad7266_wakeup(struct ad7266_state *st) diff --git a/drivers/iio/adc/ad7280a.c b/drivers/iio/adc/ad7280a.c index 3bdf3d9422f2..d4a4e15c8244 100644 --- a/drivers/iio/adc/ad7280a.c +++ b/drivers/iio/adc/ad7280a.c @@ -183,7 +183,7 @@ struct ad7280_state { unsigned char cb_mask[AD7280A_MAX_CHAIN]; struct mutex lock; /* protect sensor state */ - __be32 tx ____cacheline_aligned; + __be32 tx __aligned(IIO_DMA_MINALIGN); __be32 rx; }; diff --git a/drivers/iio/adc/ad7292.c b/drivers/iio/adc/ad7292.c index 3271a31afde1..92c68d467c50 100644 --- a/drivers/iio/adc/ad7292.c +++ b/drivers/iio/adc/ad7292.c @@ -80,7 +80,7 @@ struct ad7292_state { struct regulator *reg; unsigned short vref_mv; - __be16 d16 ____cacheline_aligned; + __be16 d16 __aligned(IIO_DMA_MINALIGN); u8 d8[2]; }; diff --git a/drivers/iio/adc/ad7298.c b/drivers/iio/adc/ad7298.c index 3f4e73f7d35a..c0430f71f592 100644 --- a/drivers/iio/adc/ad7298.c +++ b/drivers/iio/adc/ad7298.c @@ -49,7 +49,7 @@ struct ad7298_state { * DMA (thus cache coherency maintenance) requires the * transfer buffers to live in their own cache lines. */ - __be16 rx_buf[12] ____cacheline_aligned; + __be16 rx_buf[12] __aligned(IIO_DMA_MINALIGN); __be16 tx_buf[2]; }; diff --git a/drivers/iio/adc/ad7476.c b/drivers/iio/adc/ad7476.c index a1e8b32671cf..94776f696290 100644 --- a/drivers/iio/adc/ad7476.c +++ b/drivers/iio/adc/ad7476.c @@ -44,13 +44,12 @@ struct ad7476_state { struct spi_transfer xfer; struct spi_message msg; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. * Make the buffer large enough for one 16 bit sample and one 64 bit * aligned 64 bit timestamp. */ - unsigned char data[ALIGN(2, sizeof(s64)) + sizeof(s64)] - ____cacheline_aligned; + unsigned char data[ALIGN(2, sizeof(s64)) + sizeof(s64)] __aligned(IIO_DMA_MINALIGN); }; enum ad7476_supported_device_ids { diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index 3b193dc26438..ba24f99523e0 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index 4f82d7c9acfd..2dc4f599f9df 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -116,11 +116,11 @@ struct ad7606_state { struct completion completion; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. * 16 * 16-bit samples + 64-bit timestamp */ - unsigned short data[20] ____cacheline_aligned; + unsigned short data[20] __aligned(IIO_DMA_MINALIGN); __be16 d16[2]; }; diff --git a/drivers/iio/adc/ad7606_par.c b/drivers/iio/adc/ad7606_par.c index 8888e56b5e90..b912b4df9b56 100644 --- a/drivers/iio/adc/ad7606_par.c +++ b/drivers/iio/adc/ad7606_par.c @@ -5,6 +5,7 @@ * Copyright 2011 Analog Devices Inc. */ +#include #include #include #include diff --git a/drivers/iio/adc/ad7766.c b/drivers/iio/adc/ad7766.c index 51ee9482e0df..3079a0872947 100644 --- a/drivers/iio/adc/ad7766.c +++ b/drivers/iio/adc/ad7766.c @@ -45,13 +45,12 @@ struct ad7766 { struct spi_message msg; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. * Make the buffer large enough for one 24 bit sample and one 64 bit * aligned 64 bit timestamp. */ - unsigned char data[ALIGN(3, sizeof(s64)) + sizeof(s64)] - ____cacheline_aligned; + unsigned char data[ALIGN(3, sizeof(s64)) + sizeof(s64)] __aligned(IIO_DMA_MINALIGN); }; /* diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index aa42ba759fa1..652db768ef37 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -163,7 +163,7 @@ struct ad7768_state { struct gpio_desc *gpio_sync_in; const char *labels[ARRAY_SIZE(ad7768_channels)]; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ union { @@ -173,7 +173,7 @@ struct ad7768_state { } scan; __be32 d32; u8 d8[2]; - } data ____cacheline_aligned; + } data __aligned(IIO_DMA_MINALIGN); }; static int ad7768_spi_reg_read(struct ad7768_state *st, unsigned int addr, @@ -620,7 +620,7 @@ static int ad7768_probe(struct spi_device *spi) indio_dev->num_channels = ARRAY_SIZE(ad7768_channels); indio_dev->name = spi_get_device_id(spi)->name; indio_dev->info = &ad7768_info; - indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_TRIGGERED; + indio_dev->modes = INDIO_DIRECT_MODE; ret = ad7768_setup(st); if (ret < 0) { diff --git a/drivers/iio/adc/ad7887.c b/drivers/iio/adc/ad7887.c index f64999714a4d..965bdc8aa696 100644 --- a/drivers/iio/adc/ad7887.c +++ b/drivers/iio/adc/ad7887.c @@ -66,13 +66,12 @@ struct ad7887_state { unsigned char tx_cmd_buf[4]; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. * Buffer needs to be large enough to hold two 16 bit samples and a * 64 bit aligned 64 bit timestamp. */ - unsigned char data[ALIGN(4, sizeof(s64)) + sizeof(s64)] - ____cacheline_aligned; + unsigned char data[ALIGN(4, sizeof(s64)) + sizeof(s64)] __aligned(IIO_DMA_MINALIGN); }; enum ad7887_supported_device_ids { diff --git a/drivers/iio/adc/ad7923.c b/drivers/iio/adc/ad7923.c index 069b561ee768..edad1f30121d 100644 --- a/drivers/iio/adc/ad7923.c +++ b/drivers/iio/adc/ad7923.c @@ -57,12 +57,12 @@ struct ad7923_state { unsigned int settings; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. * Ensure rx_buf can be directly used in iio_push_to_buffers_with_timetamp * Length = 8 channels + 4 extra for 8 byte timestamp */ - __be16 rx_buf[12] ____cacheline_aligned; + __be16 rx_buf[12] __aligned(IIO_DMA_MINALIGN); __be16 tx_buf[4]; }; diff --git a/drivers/iio/adc/ad7949.c b/drivers/iio/adc/ad7949.c index 44bb5fde83de..edd0c3a35ab7 100644 --- a/drivers/iio/adc/ad7949.c +++ b/drivers/iio/adc/ad7949.c @@ -86,7 +86,7 @@ struct ad7949_adc_chip { u8 resolution; u16 cfg; unsigned int current_channel; - u16 buffer ____cacheline_aligned; + u16 buffer __aligned(IIO_DMA_MINALIGN); __be16 buf8b; }; @@ -400,7 +400,7 @@ static int ad7949_spi_probe(struct spi_device *spi) ret = ad7949_spi_init(ad7949_adc); if (ret) { - dev_err(dev, "enable to init this device: %d\n", ret); + dev_err(dev, "fail to init this device: %d\n", ret); return ret; } diff --git a/drivers/iio/adc/ad799x.c b/drivers/iio/adc/ad799x.c index 220228c375d3..262bd7665b33 100644 --- a/drivers/iio/adc/ad799x.c +++ b/drivers/iio/adc/ad799x.c @@ -896,7 +896,7 @@ static int ad799x_remove(struct i2c_client *client) return 0; } -static int __maybe_unused ad799x_suspend(struct device *dev) +static int ad799x_suspend(struct device *dev) { struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); struct ad799x_state *st = iio_priv(indio_dev); @@ -908,7 +908,7 @@ static int __maybe_unused ad799x_suspend(struct device *dev) return 0; } -static int __maybe_unused ad799x_resume(struct device *dev) +static int ad799x_resume(struct device *dev) { struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); struct ad799x_state *st = iio_priv(indio_dev); @@ -941,7 +941,7 @@ static int __maybe_unused ad799x_resume(struct device *dev) return 0; } -static SIMPLE_DEV_PM_OPS(ad799x_pm_ops, ad799x_suspend, ad799x_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(ad799x_pm_ops, ad799x_suspend, ad799x_resume); static const struct i2c_device_id ad799x_id[] = { { "ad7991", ad7991 }, @@ -960,7 +960,7 @@ MODULE_DEVICE_TABLE(i2c, ad799x_id); static struct i2c_driver ad799x_driver = { .driver = { .name = "ad799x", - .pm = &ad799x_pm_ops, + .pm = pm_sleep_ptr(&ad799x_pm_ops), }, .probe = ad799x_probe, .remove = ad799x_remove, diff --git a/drivers/iio/adc/ad9467.c b/drivers/iio/adc/ad9467.c index dbfc8517cb8a..5a5f33f7bc8f 100644 --- a/drivers/iio/adc/ad9467.c +++ b/drivers/iio/adc/ad9467.c @@ -474,3 +474,4 @@ module_spi_driver(ad9467_driver); MODULE_AUTHOR("Michael Hennerich "); MODULE_DESCRIPTION("Analog Devices AD9467 ADC driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(IIO_ADI_AXI); diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c index a9e655e69eaa..e8a8ea4140f1 100644 --- a/drivers/iio/adc/adi-axi-adc.c +++ b/drivers/iio/adc/adi-axi-adc.c @@ -84,9 +84,10 @@ void *adi_axi_adc_conv_priv(struct adi_axi_adc_conv *conv) { struct adi_axi_adc_client *cl = conv_to_client(conv); - return (char *)cl + ALIGN(sizeof(struct adi_axi_adc_client), IIO_ALIGN); + return (char *)cl + ALIGN(sizeof(struct adi_axi_adc_client), + IIO_DMA_MINALIGN); } -EXPORT_SYMBOL_GPL(adi_axi_adc_conv_priv); +EXPORT_SYMBOL_NS_GPL(adi_axi_adc_conv_priv, IIO_ADI_AXI); static void adi_axi_adc_write(struct adi_axi_adc_state *st, unsigned int reg, @@ -169,9 +170,9 @@ static struct adi_axi_adc_conv *adi_axi_adc_conv_register(struct device *dev, struct adi_axi_adc_client *cl; size_t alloc_size; - alloc_size = ALIGN(sizeof(struct adi_axi_adc_client), IIO_ALIGN); + alloc_size = ALIGN(sizeof(struct adi_axi_adc_client), IIO_DMA_MINALIGN); if (sizeof_priv) - alloc_size += ALIGN(sizeof_priv, IIO_ALIGN); + alloc_size += ALIGN(sizeof_priv, IIO_DMA_MINALIGN); cl = kzalloc(alloc_size, GFP_KERNEL); if (!cl) @@ -224,7 +225,7 @@ struct adi_axi_adc_conv *devm_adi_axi_adc_conv_register(struct device *dev, return conv; } -EXPORT_SYMBOL_GPL(devm_adi_axi_adc_conv_register); +EXPORT_SYMBOL_NS_GPL(devm_adi_axi_adc_conv_register, IIO_ADI_AXI); static ssize_t in_voltage_scale_available_show(struct device *dev, struct device_attribute *attr, diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index b764823ce57e..279430c1d88c 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -1752,7 +1752,7 @@ static int at91_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val) int ret; if (val > AT91_HWFIFO_MAX_SIZE) - return -EINVAL; + val = AT91_HWFIFO_MAX_SIZE; if (!st->selected_trig->hw_trig) { dev_dbg(&indio_dev->dev, "we need hw trigger for DMA\n"); @@ -2103,7 +2103,7 @@ static int at91_adc_remove(struct platform_device *pdev) return 0; } -static __maybe_unused int at91_adc_suspend(struct device *dev) +static int at91_adc_suspend(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); struct at91_adc_state *st = iio_priv(indio_dev); @@ -2123,7 +2123,7 @@ static __maybe_unused int at91_adc_suspend(struct device *dev) return pinctrl_pm_select_sleep_state(dev); } -static __maybe_unused int at91_adc_resume(struct device *dev) +static int at91_adc_resume(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); struct at91_adc_state *st = iio_priv(indio_dev); @@ -2169,7 +2169,8 @@ resume_failed: return ret; } -static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, + at91_adc_resume); static const struct of_device_id at91_adc_dt_match[] = { { @@ -2190,7 +2191,7 @@ static struct platform_driver at91_adc_driver = { .driver = { .name = "at91-sama5d2_adc", .of_match_table = at91_adc_dt_match, - .pm = &at91_adc_pm_ops, + .pm = pm_sleep_ptr(&at91_adc_pm_ops), }, }; module_platform_driver(at91_adc_driver) diff --git a/drivers/iio/adc/berlin2-adc.c b/drivers/iio/adc/berlin2-adc.c index 03987d7e6b3d..3d2e8b4db61a 100644 --- a/drivers/iio/adc/berlin2-adc.c +++ b/drivers/iio/adc/berlin2-adc.c @@ -15,7 +15,9 @@ #include #include #include +#include #include +#include #include #include #include diff --git a/drivers/iio/adc/hi8435.c b/drivers/iio/adc/hi8435.c index 8eb0140df133..771fa12bdc02 100644 --- a/drivers/iio/adc/hi8435.c +++ b/drivers/iio/adc/hi8435.c @@ -49,7 +49,7 @@ struct hi8435_priv { unsigned threshold_lo[2]; /* GND-Open and Supply-Open thresholds */ unsigned threshold_hi[2]; /* GND-Open and Supply-Open thresholds */ - u8 reg_buffer[3] ____cacheline_aligned; + u8 reg_buffer[3] __aligned(IIO_DMA_MINALIGN); }; static int hi8435_readb(struct hi8435_priv *priv, u8 reg, u8 *val) diff --git a/drivers/iio/adc/imx7d_adc.c b/drivers/iio/adc/imx7d_adc.c index 12f5b8e34c84..86caff1d006b 100644 --- a/drivers/iio/adc/imx7d_adc.c +++ b/drivers/iio/adc/imx7d_adc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -539,14 +540,15 @@ static int imx7d_adc_probe(struct platform_device *pdev) return 0; } -static SIMPLE_DEV_PM_OPS(imx7d_adc_pm_ops, imx7d_adc_disable, imx7d_adc_enable); +static DEFINE_SIMPLE_DEV_PM_OPS(imx7d_adc_pm_ops, imx7d_adc_disable, + imx7d_adc_enable); static struct platform_driver imx7d_adc_driver = { .probe = imx7d_adc_probe, .driver = { .name = "imx7d_adc", .of_match_table = imx7d_adc_match, - .pm = &imx7d_adc_pm_ops, + .pm = pm_sleep_ptr(&imx7d_adc_pm_ops), }, }; diff --git a/drivers/iio/adc/imx8qxp-adc.c b/drivers/iio/adc/imx8qxp-adc.c index 901dd8e1b32f..e48446784a0a 100644 --- a/drivers/iio/adc/imx8qxp-adc.c +++ b/drivers/iio/adc/imx8qxp-adc.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -416,7 +417,7 @@ static int imx8qxp_adc_remove(struct platform_device *pdev) return 0; } -static __maybe_unused int imx8qxp_adc_runtime_suspend(struct device *dev) +static int imx8qxp_adc_runtime_suspend(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); struct imx8qxp_adc *adc = iio_priv(indio_dev); @@ -430,7 +431,7 @@ static __maybe_unused int imx8qxp_adc_runtime_suspend(struct device *dev) return 0; } -static __maybe_unused int imx8qxp_adc_runtime_resume(struct device *dev) +static int imx8qxp_adc_runtime_resume(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); struct imx8qxp_adc *adc = iio_priv(indio_dev); @@ -467,10 +468,9 @@ err_disable_reg: return ret; } -static const struct dev_pm_ops imx8qxp_adc_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) - SET_RUNTIME_PM_OPS(imx8qxp_adc_runtime_suspend, imx8qxp_adc_runtime_resume, NULL) -}; +static DEFINE_RUNTIME_DEV_PM_OPS(imx8qxp_adc_pm_ops, + imx8qxp_adc_runtime_suspend, + imx8qxp_adc_runtime_resume, NULL); static const struct of_device_id imx8qxp_adc_match[] = { { .compatible = "nxp,imx8qxp-adc", }, @@ -484,7 +484,7 @@ static struct platform_driver imx8qxp_adc_driver = { .driver = { .name = ADC_DRIVER_NAME, .of_match_table = imx8qxp_adc_match, - .pm = &imx8qxp_adc_pm_ops, + .pm = pm_ptr(&imx8qxp_adc_pm_ops), }, }; diff --git a/drivers/iio/adc/ina2xx-adc.c b/drivers/iio/adc/ina2xx-adc.c index abad16803849..240e6c420701 100644 --- a/drivers/iio/adc/ina2xx-adc.c +++ b/drivers/iio/adc/ina2xx-adc.c @@ -1038,12 +1038,18 @@ static int ina2xx_remove(struct i2c_client *client) { struct iio_dev *indio_dev = i2c_get_clientdata(client); struct ina2xx_chip_info *chip = iio_priv(indio_dev); + int ret; iio_device_unregister(indio_dev); /* Powerdown */ - return regmap_update_bits(chip->regmap, INA2XX_CONFIG, - INA2XX_MODE_MASK, 0); + ret = regmap_update_bits(chip->regmap, INA2XX_CONFIG, + INA2XX_MODE_MASK, 0); + if (ret) + dev_warn(&client->dev, "Failed to power down device (%pe)\n", + ERR_PTR(ret)); + + return 0; } static const struct i2c_device_id ina2xx_id[] = { diff --git a/drivers/iio/adc/ingenic-adc.c b/drivers/iio/adc/ingenic-adc.c index 2b3912c6ca6b..bf5c03c34f84 100644 --- a/drivers/iio/adc/ingenic-adc.c +++ b/drivers/iio/adc/ingenic-adc.c @@ -17,7 +17,9 @@ #include #include #include +#include #include +#include #define JZ_ADC_REG_ENABLE 0x00 #define JZ_ADC_REG_CFG 0x04 diff --git a/drivers/iio/adc/intel_mrfld_adc.c b/drivers/iio/adc/intel_mrfld_adc.c index 616de0c3a049..7263ad76124d 100644 --- a/drivers/iio/adc/intel_mrfld_adc.c +++ b/drivers/iio/adc/intel_mrfld_adc.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/iio/adc/lpc18xx_adc.c b/drivers/iio/adc/lpc18xx_adc.c index ae9c9384f23e..42e6cd6fa6f7 100644 --- a/drivers/iio/adc/lpc18xx_adc.c +++ b/drivers/iio/adc/lpc18xx_adc.c @@ -17,10 +17,9 @@ #include #include #include +#include #include #include -#include -#include #include #include diff --git a/drivers/iio/adc/ltc2496.c b/drivers/iio/adc/ltc2496.c index 5a55f79f2574..dfb3bb5997e5 100644 --- a/drivers/iio/adc/ltc2496.c +++ b/drivers/iio/adc/ltc2496.c @@ -24,10 +24,10 @@ struct ltc2496_driverdata { struct spi_device *spi; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ - unsigned char rxbuf[3] ____cacheline_aligned; + unsigned char rxbuf[3] __aligned(IIO_DMA_MINALIGN); unsigned char txbuf[3]; }; diff --git a/drivers/iio/adc/ltc2497.c b/drivers/iio/adc/ltc2497.c index 1adddf5a88a9..f7c786f37ceb 100644 --- a/drivers/iio/adc/ltc2497.c +++ b/drivers/iio/adc/ltc2497.c @@ -20,10 +20,10 @@ struct ltc2497_driverdata { struct ltc2497core_driverdata common_ddata; struct i2c_client *client; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ - __be32 buf ____cacheline_aligned; + __be32 buf __aligned(IIO_DMA_MINALIGN); }; static int ltc2497_result_and_measure(struct ltc2497core_driverdata *ddata, diff --git a/drivers/iio/adc/max1027.c b/drivers/iio/adc/max1027.c index 4daf1d576c4e..136fcf753837 100644 --- a/drivers/iio/adc/max1027.c +++ b/drivers/iio/adc/max1027.c @@ -272,7 +272,7 @@ struct max1027_state { struct mutex lock; struct completion complete; - u8 reg ____cacheline_aligned; + u8 reg __aligned(IIO_DMA_MINALIGN); }; static int max1027_wait_eoc(struct iio_dev *indio_dev) @@ -349,8 +349,7 @@ static int max1027_read_single_value(struct iio_dev *indio_dev, if (ret < 0) { dev_err(&indio_dev->dev, "Failed to configure conversion register\n"); - iio_device_release_direct_mode(indio_dev); - return ret; + goto release; } /* @@ -360,11 +359,12 @@ static int max1027_read_single_value(struct iio_dev *indio_dev, */ ret = max1027_wait_eoc(indio_dev); if (ret) - return ret; + goto release; /* Read result */ ret = spi_read(st->spi, st->buffer, (chan->type == IIO_TEMP) ? 4 : 2); +release: iio_device_release_direct_mode(indio_dev); if (ret < 0) diff --git a/drivers/iio/adc/max11100.c b/drivers/iio/adc/max11100.c index eb1ce6a0315c..49e38dca8fe2 100644 --- a/drivers/iio/adc/max11100.c +++ b/drivers/iio/adc/max11100.c @@ -33,10 +33,10 @@ struct max11100_state { struct spi_device *spi; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ - u8 buffer[3] ____cacheline_aligned; + u8 buffer[3] __aligned(IIO_DMA_MINALIGN); }; static const struct iio_chan_spec max11100_channels[] = { diff --git a/drivers/iio/adc/max1118.c b/drivers/iio/adc/max1118.c index a41bc570be21..75ab57d9aef7 100644 --- a/drivers/iio/adc/max1118.c +++ b/drivers/iio/adc/max1118.c @@ -42,7 +42,7 @@ struct max1118 { s64 ts __aligned(8); } scan; - u8 data ____cacheline_aligned; + u8 data __aligned(IIO_DMA_MINALIGN); }; #define MAX1118_CHANNEL(ch) \ diff --git a/drivers/iio/adc/max1241.c b/drivers/iio/adc/max1241.c index a5afd84af58b..a815ad1f6913 100644 --- a/drivers/iio/adc/max1241.c +++ b/drivers/iio/adc/max1241.c @@ -26,7 +26,7 @@ struct max1241 { struct regulator *vref; struct gpio_desc *shutdown; - __be16 data ____cacheline_aligned; + __be16 data __aligned(IIO_DMA_MINALIGN); }; static const struct iio_chan_spec max1241_channels[] = { diff --git a/drivers/iio/adc/mcp320x.c b/drivers/iio/adc/mcp320x.c index b4c69acb33e3..f3b81798b3c9 100644 --- a/drivers/iio/adc/mcp320x.c +++ b/drivers/iio/adc/mcp320x.c @@ -92,7 +92,7 @@ struct mcp320x { struct mutex lock; const struct mcp320x_chip_info *chip_info; - u8 tx_buf ____cacheline_aligned; + u8 tx_buf __aligned(IIO_DMA_MINALIGN); u8 rx_buf[4]; }; diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c index 62cc6fb0ef85..1a68b099d323 100644 --- a/drivers/iio/adc/meson_saradc.c +++ b/drivers/iio/adc/meson_saradc.c @@ -322,22 +322,17 @@ static int meson_sar_adc_calib_val(struct iio_dev *indio_dev, int val) static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev) { struct meson_sar_adc_priv *priv = iio_priv(indio_dev); - int regval, timeout = 10000; + int val; /* * NOTE: we need a small delay before reading the status, otherwise * the sample engine may not have started internally (which would * seem to us that sampling is already finished). */ - do { - udelay(1); - regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); - } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--); - - if (timeout < 0) - return -ETIMEDOUT; - - return 0; + udelay(1); + return regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_REG0, val, + !FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, val), + 1, 10000); } static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev, @@ -345,6 +340,7 @@ static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev, int *val) { struct meson_sar_adc_priv *priv = iio_priv(indio_dev); + struct device *dev = indio_dev->dev.parent; int regval, fifo_chan, fifo_val, count; if (!wait_for_completion_timeout(&priv->done, @@ -353,16 +349,14 @@ static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev, count = meson_sar_adc_get_fifo_count(indio_dev); if (count != 1) { - dev_err(&indio_dev->dev, - "ADC FIFO has %d element(s) instead of one\n", count); + dev_err(dev, "ADC FIFO has %d element(s) instead of one\n", count); return -EINVAL; } regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val); fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval); if (fifo_chan != chan->address) { - dev_err(&indio_dev->dev, - "ADC FIFO entry belongs to channel %d instead of %lu\n", + dev_err(dev, "ADC FIFO entry belongs to channel %d instead of %lu\n", fifo_chan, chan->address); return -EINVAL; } @@ -490,7 +484,7 @@ static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev) static int meson_sar_adc_lock(struct iio_dev *indio_dev) { struct meson_sar_adc_priv *priv = iio_priv(indio_dev); - int val, timeout = 10000; + int val, ret; mutex_lock(&indio_dev->mlock); @@ -500,18 +494,18 @@ static int meson_sar_adc_lock(struct iio_dev *indio_dev) MESON_SAR_ADC_DELAY_KERNEL_BUSY, MESON_SAR_ADC_DELAY_KERNEL_BUSY); + udelay(1); + /* * wait until BL30 releases it's lock (so we can use the SAR * ADC) */ - do { - udelay(1); - regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val); - } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--); - - if (timeout < 0) { + ret = regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_DELAY, val, + !(val & MESON_SAR_ADC_DELAY_BL30_BUSY), + 1, 10000); + if (ret) { mutex_unlock(&indio_dev->mlock); - return -ETIMEDOUT; + return ret; } } @@ -550,6 +544,7 @@ static int meson_sar_adc_get_sample(struct iio_dev *indio_dev, int *val) { struct meson_sar_adc_priv *priv = iio_priv(indio_dev); + struct device *dev = indio_dev->dev.parent; int ret; if (chan->type == IIO_TEMP && !priv->temperature_sensor_calibrated) @@ -573,8 +568,7 @@ static int meson_sar_adc_get_sample(struct iio_dev *indio_dev, meson_sar_adc_unlock(indio_dev); if (ret) { - dev_warn(indio_dev->dev.parent, - "failed to read sample for channel %lu: %d\n", + dev_warn(dev, "failed to read sample for channel %lu: %d\n", chan->address, ret); return ret; } @@ -587,6 +581,7 @@ static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev, int *val, int *val2, long mask) { struct meson_sar_adc_priv *priv = iio_priv(indio_dev); + struct device *dev = indio_dev->dev.parent; int ret; switch (mask) { @@ -603,9 +598,7 @@ static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev, if (chan->type == IIO_VOLTAGE) { ret = regulator_get_voltage(priv->vref); if (ret < 0) { - dev_err(indio_dev->dev.parent, - "failed to get vref voltage: %d\n", - ret); + dev_err(dev, "failed to get vref voltage: %d\n", ret); return ret; } @@ -650,11 +643,11 @@ static int meson_sar_adc_clk_init(struct iio_dev *indio_dev, void __iomem *base) { struct meson_sar_adc_priv *priv = iio_priv(indio_dev); + struct device *dev = indio_dev->dev.parent; struct clk_init_data init; const char *clk_parents[1]; - init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div", - dev_name(indio_dev->dev.parent)); + init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#adc_div", dev_name(dev)); if (!init.name) return -ENOMEM; @@ -670,13 +663,11 @@ static int meson_sar_adc_clk_init(struct iio_dev *indio_dev, priv->clk_div.hw.init = &init; priv->clk_div.flags = 0; - priv->adc_div_clk = devm_clk_register(&indio_dev->dev, - &priv->clk_div.hw); + priv->adc_div_clk = devm_clk_register(dev, &priv->clk_div.hw); if (WARN_ON(IS_ERR(priv->adc_div_clk))) return PTR_ERR(priv->adc_div_clk); - init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en", - dev_name(indio_dev->dev.parent)); + init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#adc_en", dev_name(dev)); if (!init.name) return -ENOMEM; @@ -690,7 +681,7 @@ static int meson_sar_adc_clk_init(struct iio_dev *indio_dev, priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN); priv->clk_gate.hw.init = &init; - priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw); + priv->adc_clk = devm_clk_register(dev, &priv->clk_gate.hw); if (WARN_ON(IS_ERR(priv->adc_clk))) return PTR_ERR(priv->adc_clk); @@ -701,12 +692,12 @@ static int meson_sar_adc_temp_sensor_init(struct iio_dev *indio_dev) { struct meson_sar_adc_priv *priv = iio_priv(indio_dev); u8 *buf, trimming_bits, trimming_mask, upper_adc_val; + struct device *dev = indio_dev->dev.parent; struct nvmem_cell *temperature_calib; size_t read_len; int ret; - temperature_calib = devm_nvmem_cell_get(indio_dev->dev.parent, - "temperature_calib"); + temperature_calib = devm_nvmem_cell_get(dev, "temperature_calib"); if (IS_ERR(temperature_calib)) { ret = PTR_ERR(temperature_calib); @@ -717,30 +708,21 @@ static int meson_sar_adc_temp_sensor_init(struct iio_dev *indio_dev) if (ret == -ENODEV) return 0; - return dev_err_probe(indio_dev->dev.parent, ret, - "failed to get temperature_calib cell\n"); + return dev_err_probe(dev, ret, "failed to get temperature_calib cell\n"); } - priv->tsc_regmap = - syscon_regmap_lookup_by_phandle(indio_dev->dev.parent->of_node, - "amlogic,hhi-sysctrl"); - if (IS_ERR(priv->tsc_regmap)) { - dev_err(indio_dev->dev.parent, - "failed to get amlogic,hhi-sysctrl regmap\n"); - return PTR_ERR(priv->tsc_regmap); - } + priv->tsc_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "amlogic,hhi-sysctrl"); + if (IS_ERR(priv->tsc_regmap)) + return dev_err_probe(dev, PTR_ERR(priv->tsc_regmap), + "failed to get amlogic,hhi-sysctrl regmap\n"); read_len = MESON_SAR_ADC_EFUSE_BYTES; buf = nvmem_cell_read(temperature_calib, &read_len); - if (IS_ERR(buf)) { - dev_err(indio_dev->dev.parent, - "failed to read temperature_calib cell\n"); - return PTR_ERR(buf); - } else if (read_len != MESON_SAR_ADC_EFUSE_BYTES) { + if (IS_ERR(buf)) + return dev_err_probe(dev, PTR_ERR(buf), "failed to read temperature_calib cell\n"); + if (read_len != MESON_SAR_ADC_EFUSE_BYTES) { kfree(buf); - dev_err(indio_dev->dev.parent, - "invalid read size of temperature_calib cell\n"); - return -EINVAL; + return dev_err_probe(dev, -EINVAL, "invalid read size of temperature_calib cell\n"); } trimming_bits = priv->param->temperature_trimming_bits; @@ -765,6 +747,7 @@ static int meson_sar_adc_temp_sensor_init(struct iio_dev *indio_dev) static int meson_sar_adc_init(struct iio_dev *indio_dev) { struct meson_sar_adc_priv *priv = iio_priv(indio_dev); + struct device *dev = indio_dev->dev.parent; int regval, i, ret; /* @@ -888,18 +871,12 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev) } ret = clk_set_parent(priv->adc_sel_clk, priv->clkin); - if (ret) { - dev_err(indio_dev->dev.parent, - "failed to set adc parent to clkin\n"); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "failed to set adc parent to clkin\n"); ret = clk_set_rate(priv->adc_clk, priv->param->clock_rate); - if (ret) { - dev_err(indio_dev->dev.parent, - "failed to set adc clock rate\n"); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "failed to set adc clock rate\n"); return 0; } @@ -922,6 +899,7 @@ static void meson_sar_adc_set_bandgap(struct iio_dev *indio_dev, bool on_off) static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev) { struct meson_sar_adc_priv *priv = iio_priv(indio_dev); + struct device *dev = indio_dev->dev.parent; int ret; u32 regval; @@ -931,14 +909,13 @@ static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev) ret = regulator_enable(priv->vref); if (ret < 0) { - dev_err(indio_dev->dev.parent, - "failed to enable vref regulator\n"); + dev_err(dev, "failed to enable vref regulator\n"); goto err_vref; } ret = clk_prepare_enable(priv->core_clk); if (ret) { - dev_err(indio_dev->dev.parent, "failed to enable core clk\n"); + dev_err(dev, "failed to enable core clk\n"); goto err_core_clk; } @@ -956,7 +933,7 @@ static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev) ret = clk_prepare_enable(priv->adc_clk); if (ret) { - dev_err(indio_dev->dev.parent, "failed to enable adc clk\n"); + dev_err(dev, "failed to enable adc clk\n"); goto err_adc_clk; } @@ -1186,24 +1163,21 @@ static int meson_sar_adc_probe(struct platform_device *pdev) { const struct meson_sar_adc_data *match_data; struct meson_sar_adc_priv *priv; + struct device *dev = &pdev->dev; struct iio_dev *indio_dev; void __iomem *base; int irq, ret; - indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv)); - if (!indio_dev) { - dev_err(&pdev->dev, "failed allocating iio device\n"); - return -ENOMEM; - } + indio_dev = devm_iio_device_alloc(dev, sizeof(*priv)); + if (!indio_dev) + return dev_err_probe(dev, -ENOMEM, "failed allocating iio device\n"); priv = iio_priv(indio_dev); init_completion(&priv->done); - match_data = of_device_get_match_data(&pdev->dev); - if (!match_data) { - dev_err(&pdev->dev, "failed to get match data\n"); - return -ENODEV; - } + match_data = of_device_get_match_data(dev); + if (!match_data) + return dev_err_probe(dev, -ENODEV, "failed to get match data\n"); priv->param = match_data->param; @@ -1215,47 +1189,33 @@ static int meson_sar_adc_probe(struct platform_device *pdev) if (IS_ERR(base)) return PTR_ERR(base); - priv->regmap = devm_regmap_init_mmio(&pdev->dev, base, - priv->param->regmap_config); + priv->regmap = devm_regmap_init_mmio(dev, base, priv->param->regmap_config); if (IS_ERR(priv->regmap)) return PTR_ERR(priv->regmap); - irq = irq_of_parse_and_map(pdev->dev.of_node, 0); + irq = irq_of_parse_and_map(dev->of_node, 0); if (!irq) return -EINVAL; - ret = devm_request_irq(&pdev->dev, irq, meson_sar_adc_irq, IRQF_SHARED, - dev_name(&pdev->dev), indio_dev); + ret = devm_request_irq(dev, irq, meson_sar_adc_irq, IRQF_SHARED, dev_name(dev), indio_dev); if (ret) return ret; - priv->clkin = devm_clk_get(&pdev->dev, "clkin"); + priv->clkin = devm_clk_get(dev, "clkin"); if (IS_ERR(priv->clkin)) - return dev_err_probe(&pdev->dev, PTR_ERR(priv->clkin), - "failed to get clkin\n"); + return dev_err_probe(dev, PTR_ERR(priv->clkin), "failed to get clkin\n"); - priv->core_clk = devm_clk_get(&pdev->dev, "core"); + priv->core_clk = devm_clk_get(dev, "core"); if (IS_ERR(priv->core_clk)) - return dev_err_probe(&pdev->dev, PTR_ERR(priv->core_clk), - "failed to get core clk\n"); + return dev_err_probe(dev, PTR_ERR(priv->core_clk), "failed to get core clk\n"); - priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk"); - if (IS_ERR(priv->adc_clk)) { - if (PTR_ERR(priv->adc_clk) == -ENOENT) - priv->adc_clk = NULL; - else - return dev_err_probe(&pdev->dev, PTR_ERR(priv->adc_clk), - "failed to get adc clk\n"); - } + priv->adc_clk = devm_clk_get_optional(dev, "adc_clk"); + if (IS_ERR(priv->adc_clk)) + return dev_err_probe(dev, PTR_ERR(priv->adc_clk), "failed to get adc clk\n"); - priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel"); - if (IS_ERR(priv->adc_sel_clk)) { - if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) - priv->adc_sel_clk = NULL; - else - return dev_err_probe(&pdev->dev, PTR_ERR(priv->adc_sel_clk), - "failed to get adc_sel clk\n"); - } + priv->adc_sel_clk = devm_clk_get_optional(dev, "adc_sel"); + if (IS_ERR(priv->adc_sel_clk)) + return dev_err_probe(dev, PTR_ERR(priv->adc_sel_clk), "failed to get adc_sel clk\n"); /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */ if (!priv->adc_clk) { @@ -1264,10 +1224,9 @@ static int meson_sar_adc_probe(struct platform_device *pdev) return ret; } - priv->vref = devm_regulator_get(&pdev->dev, "vref"); + priv->vref = devm_regulator_get(dev, "vref"); if (IS_ERR(priv->vref)) - return dev_err_probe(&pdev->dev, PTR_ERR(priv->vref), - "failed to get vref regulator\n"); + return dev_err_probe(dev, PTR_ERR(priv->vref), "failed to get vref regulator\n"); priv->calibscale = MILLION; @@ -1297,7 +1256,7 @@ static int meson_sar_adc_probe(struct platform_device *pdev) ret = meson_sar_adc_calib(indio_dev); if (ret) - dev_warn(&pdev->dev, "calibration failed\n"); + dev_warn(dev, "calibration failed\n"); platform_set_drvdata(pdev, indio_dev); @@ -1322,22 +1281,22 @@ static int meson_sar_adc_remove(struct platform_device *pdev) return meson_sar_adc_hw_disable(indio_dev); } -static int __maybe_unused meson_sar_adc_suspend(struct device *dev) +static int meson_sar_adc_suspend(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); return meson_sar_adc_hw_disable(indio_dev); } -static int __maybe_unused meson_sar_adc_resume(struct device *dev) +static int meson_sar_adc_resume(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); return meson_sar_adc_hw_enable(indio_dev); } -static SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops, - meson_sar_adc_suspend, meson_sar_adc_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops, + meson_sar_adc_suspend, meson_sar_adc_resume); static struct platform_driver meson_sar_adc_driver = { .probe = meson_sar_adc_probe, @@ -1345,7 +1304,7 @@ static struct platform_driver meson_sar_adc_driver = { .driver = { .name = "meson-saradc", .of_match_table = meson_sar_adc_of_match, - .pm = &meson_sar_adc_pm_ops, + .pm = pm_sleep_ptr(&meson_sar_adc_pm_ops), }, }; diff --git a/drivers/iio/adc/mp2629_adc.c b/drivers/iio/adc/mp2629_adc.c index aca084f1e78a..30a31f185d08 100644 --- a/drivers/iio/adc/mp2629_adc.c +++ b/drivers/iio/adc/mp2629_adc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/iio/adc/mt6360-adc.c b/drivers/iio/adc/mt6360-adc.c index 07c0e6768391..35260d9e4e47 100644 --- a/drivers/iio/adc/mt6360-adc.c +++ b/drivers/iio/adc/mt6360-adc.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/iio/adc/mt6577_auxadc.c b/drivers/iio/adc/mt6577_auxadc.c index e78c96a185db..0e134777bdd2 100644 --- a/drivers/iio/adc/mt6577_auxadc.c +++ b/drivers/iio/adc/mt6577_auxadc.c @@ -215,7 +215,7 @@ static const struct iio_info mt6577_auxadc_info = { .read_raw = &mt6577_auxadc_read_raw, }; -static int __maybe_unused mt6577_auxadc_resume(struct device *dev) +static int mt6577_auxadc_resume(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev); @@ -234,7 +234,7 @@ static int __maybe_unused mt6577_auxadc_resume(struct device *dev) return 0; } -static int __maybe_unused mt6577_auxadc_suspend(struct device *dev) +static int mt6577_auxadc_suspend(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev); @@ -330,9 +330,9 @@ static int mt6577_auxadc_remove(struct platform_device *pdev) return 0; } -static SIMPLE_DEV_PM_OPS(mt6577_auxadc_pm_ops, - mt6577_auxadc_suspend, - mt6577_auxadc_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(mt6577_auxadc_pm_ops, + mt6577_auxadc_suspend, + mt6577_auxadc_resume); static const struct of_device_id mt6577_auxadc_of_match[] = { { .compatible = "mediatek,mt2701-auxadc", .data = &mt8173_compat }, @@ -349,7 +349,7 @@ static struct platform_driver mt6577_auxadc_driver = { .driver = { .name = "mt6577-auxadc", .of_match_table = mt6577_auxadc_of_match, - .pm = &mt6577_auxadc_pm_ops, + .pm = pm_sleep_ptr(&mt6577_auxadc_pm_ops), }, .probe = mt6577_auxadc_probe, .remove = mt6577_auxadc_remove, diff --git a/drivers/iio/adc/nau7802.c b/drivers/iio/adc/nau7802.c index 976c235f3079..c1261ecd400c 100644 --- a/drivers/iio/adc/nau7802.c +++ b/drivers/iio/adc/nau7802.c @@ -8,10 +8,11 @@ #include #include #include +#include #include +#include #include #include -#include #include #include @@ -407,21 +408,14 @@ static const struct iio_info nau7802_info = { .attrs = &nau7802_attribute_group, }; -static int nau7802_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int nau7802_probe(struct i2c_client *client) { struct iio_dev *indio_dev; struct nau7802_state *st; - struct device_node *np = client->dev.of_node; int i, ret; u8 data; u32 tmp = 0; - if (!client->dev.of_node) { - dev_err(&client->dev, "No device tree node available.\n"); - return -EINVAL; - } - indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st)); if (indio_dev == NULL) return -ENOMEM; @@ -457,7 +451,7 @@ static int nau7802_probe(struct i2c_client *client, if (!(ret & NAU7802_PUCTRL_PUR_BIT)) return ret; - of_property_read_u32(np, "nuvoton,vldo", &tmp); + device_property_read_u32(&client->dev, "nuvoton,vldo", &tmp); st->vref_mv = tmp; data = NAU7802_PUCTRL_PUD_BIT | NAU7802_PUCTRL_PUA_BIT | @@ -550,7 +544,7 @@ static const struct of_device_id nau7802_dt_ids[] = { MODULE_DEVICE_TABLE(of, nau7802_dt_ids); static struct i2c_driver nau7802_driver = { - .probe = nau7802_probe, + .probe_new = nau7802_probe, .id_table = nau7802_i2c_id, .driver = { .name = "nau7802", diff --git a/drivers/iio/adc/npcm_adc.c b/drivers/iio/adc/npcm_adc.c index f7bc0bb7f112..ba4cd8f49f66 100644 --- a/drivers/iio/adc/npcm_adc.c +++ b/drivers/iio/adc/npcm_adc.c @@ -8,14 +8,22 @@ #include #include #include +#include #include #include +#include #include #include #include #include #include +struct npcm_adc_info { + u32 data_mask; + u32 internal_vref; + u32 res_bits; +}; + struct npcm_adc { bool int_status; u32 adc_sample_hz; @@ -34,6 +42,7 @@ struct npcm_adc { * has finished. */ struct mutex lock; + const struct npcm_adc_info *data; }; /* ADC registers */ @@ -52,13 +61,21 @@ struct npcm_adc { #define NPCM_ADCCON_CH(x) ((x) << 24) #define NPCM_ADCCON_DIV_SHIFT 1 #define NPCM_ADCCON_DIV_MASK GENMASK(8, 1) -#define NPCM_ADC_DATA_MASK(x) ((x) & GENMASK(9, 0)) #define NPCM_ADC_ENABLE (NPCM_ADCCON_ADC_EN | NPCM_ADCCON_ADC_INT_EN) /* ADC General Definition */ -#define NPCM_RESOLUTION_BITS 10 -#define NPCM_INT_VREF_MV 2000 +static const struct npcm_adc_info npxm7xx_adc_info = { + .data_mask = GENMASK(9, 0), + .internal_vref = 2048, + .res_bits = 10, +}; + +static const struct npcm_adc_info npxm8xx_adc_info = { + .data_mask = GENMASK(11, 0), + .internal_vref = 1229, + .res_bits = 12, +}; #define NPCM_ADC_CHAN(ch) { \ .type = IIO_VOLTAGE, \ @@ -129,7 +146,8 @@ static int npcm_adc_read(struct npcm_adc *info, int *val, u8 channel) if (ret < 0) return ret; - *val = NPCM_ADC_DATA_MASK(ioread32(info->regs + NPCM_ADCDATA)); + *val = ioread32(info->regs + NPCM_ADCDATA); + *val &= info->data->data_mask; return 0; } @@ -157,9 +175,9 @@ static int npcm_adc_read_raw(struct iio_dev *indio_dev, vref_uv = regulator_get_voltage(info->vref); *val = vref_uv / 1000; } else { - *val = NPCM_INT_VREF_MV; + *val = info->data->internal_vref; } - *val2 = NPCM_RESOLUTION_BITS; + *val2 = info->data->res_bits; return IIO_VAL_FRACTIONAL_LOG2; case IIO_CHAN_INFO_SAMP_FREQ: *val = info->adc_sample_hz; @@ -176,7 +194,8 @@ static const struct iio_info npcm_adc_iio_info = { }; static const struct of_device_id npcm_adc_match[] = { - { .compatible = "nuvoton,npcm750-adc", }, + { .compatible = "nuvoton,npcm750-adc", .data = &npxm7xx_adc_info}, + { .compatible = "nuvoton,npcm845-adc", .data = &npxm8xx_adc_info}, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, npcm_adc_match); @@ -196,6 +215,10 @@ static int npcm_adc_probe(struct platform_device *pdev) return -ENOMEM; info = iio_priv(indio_dev); + info->data = device_get_match_data(dev); + if (!info->data) + return -EINVAL; + mutex_init(&info->lock); info->dev = &pdev->dev; diff --git a/drivers/iio/adc/qcom-spmi-rradc.c b/drivers/iio/adc/qcom-spmi-rradc.c new file mode 100644 index 000000000000..56a713766954 --- /dev/null +++ b/drivers/iio/adc/qcom-spmi-rradc.c @@ -0,0 +1,1022 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Linaro Limited. + * Author: Caleb Connolly + * + * This driver is for the Round Robin ADC found in the pmi8998 and pm660 PMICs. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include + +#define DRIVER_NAME "qcom-spmi-rradc" + +#define RR_ADC_EN_CTL 0x46 +#define RR_ADC_SKIN_TEMP_LSB 0x50 +#define RR_ADC_SKIN_TEMP_MSB 0x51 +#define RR_ADC_CTL 0x52 +#define RR_ADC_CTL_CONTINUOUS_SEL BIT(3) +#define RR_ADC_LOG 0x53 +#define RR_ADC_LOG_CLR_CTRL BIT(0) + +#define RR_ADC_FAKE_BATT_LOW_LSB 0x58 +#define RR_ADC_FAKE_BATT_LOW_MSB 0x59 +#define RR_ADC_FAKE_BATT_HIGH_LSB 0x5A +#define RR_ADC_FAKE_BATT_HIGH_MSB 0x5B + +#define RR_ADC_BATT_ID_CTRL 0x60 +#define RR_ADC_BATT_ID_CTRL_CHANNEL_CONV BIT(0) +#define RR_ADC_BATT_ID_TRIGGER 0x61 +#define RR_ADC_BATT_ID_STS 0x62 +#define RR_ADC_BATT_ID_CFG 0x63 +#define BATT_ID_SETTLE_MASK GENMASK(7, 5) +#define RR_ADC_BATT_ID_5_LSB 0x66 +#define RR_ADC_BATT_ID_5_MSB 0x67 +#define RR_ADC_BATT_ID_15_LSB 0x68 +#define RR_ADC_BATT_ID_15_MSB 0x69 +#define RR_ADC_BATT_ID_150_LSB 0x6A +#define RR_ADC_BATT_ID_150_MSB 0x6B + +#define RR_ADC_BATT_THERM_CTRL 0x70 +#define RR_ADC_BATT_THERM_TRIGGER 0x71 +#define RR_ADC_BATT_THERM_STS 0x72 +#define RR_ADC_BATT_THERM_CFG 0x73 +#define RR_ADC_BATT_THERM_LSB 0x74 +#define RR_ADC_BATT_THERM_MSB 0x75 +#define RR_ADC_BATT_THERM_FREQ 0x76 + +#define RR_ADC_AUX_THERM_CTRL 0x80 +#define RR_ADC_AUX_THERM_TRIGGER 0x81 +#define RR_ADC_AUX_THERM_STS 0x82 +#define RR_ADC_AUX_THERM_CFG 0x83 +#define RR_ADC_AUX_THERM_LSB 0x84 +#define RR_ADC_AUX_THERM_MSB 0x85 + +#define RR_ADC_SKIN_HOT 0x86 +#define RR_ADC_SKIN_TOO_HOT 0x87 + +#define RR_ADC_AUX_THERM_C1 0x88 +#define RR_ADC_AUX_THERM_C2 0x89 +#define RR_ADC_AUX_THERM_C3 0x8A +#define RR_ADC_AUX_THERM_HALF_RANGE 0x8B + +#define RR_ADC_USB_IN_V_CTRL 0x90 +#define RR_ADC_USB_IN_V_TRIGGER 0x91 +#define RR_ADC_USB_IN_V_STS 0x92 +#define RR_ADC_USB_IN_V_LSB 0x94 +#define RR_ADC_USB_IN_V_MSB 0x95 +#define RR_ADC_USB_IN_I_CTRL 0x98 +#define RR_ADC_USB_IN_I_TRIGGER 0x99 +#define RR_ADC_USB_IN_I_STS 0x9A +#define RR_ADC_USB_IN_I_LSB 0x9C +#define RR_ADC_USB_IN_I_MSB 0x9D + +#define RR_ADC_DC_IN_V_CTRL 0xA0 +#define RR_ADC_DC_IN_V_TRIGGER 0xA1 +#define RR_ADC_DC_IN_V_STS 0xA2 +#define RR_ADC_DC_IN_V_LSB 0xA4 +#define RR_ADC_DC_IN_V_MSB 0xA5 +#define RR_ADC_DC_IN_I_CTRL 0xA8 +#define RR_ADC_DC_IN_I_TRIGGER 0xA9 +#define RR_ADC_DC_IN_I_STS 0xAA +#define RR_ADC_DC_IN_I_LSB 0xAC +#define RR_ADC_DC_IN_I_MSB 0xAD + +#define RR_ADC_PMI_DIE_TEMP_CTRL 0xB0 +#define RR_ADC_PMI_DIE_TEMP_TRIGGER 0xB1 +#define RR_ADC_PMI_DIE_TEMP_STS 0xB2 +#define RR_ADC_PMI_DIE_TEMP_CFG 0xB3 +#define RR_ADC_PMI_DIE_TEMP_LSB 0xB4 +#define RR_ADC_PMI_DIE_TEMP_MSB 0xB5 + +#define RR_ADC_CHARGER_TEMP_CTRL 0xB8 +#define RR_ADC_CHARGER_TEMP_TRIGGER 0xB9 +#define RR_ADC_CHARGER_TEMP_STS 0xBA +#define RR_ADC_CHARGER_TEMP_CFG 0xBB +#define RR_ADC_CHARGER_TEMP_LSB 0xBC +#define RR_ADC_CHARGER_TEMP_MSB 0xBD +#define RR_ADC_CHARGER_HOT 0xBE +#define RR_ADC_CHARGER_TOO_HOT 0xBF + +#define RR_ADC_GPIO_CTRL 0xC0 +#define RR_ADC_GPIO_TRIGGER 0xC1 +#define RR_ADC_GPIO_STS 0xC2 +#define RR_ADC_GPIO_LSB 0xC4 +#define RR_ADC_GPIO_MSB 0xC5 + +#define RR_ADC_ATEST_CTRL 0xC8 +#define RR_ADC_ATEST_TRIGGER 0xC9 +#define RR_ADC_ATEST_STS 0xCA +#define RR_ADC_ATEST_LSB 0xCC +#define RR_ADC_ATEST_MSB 0xCD +#define RR_ADC_SEC_ACCESS 0xD0 + +#define RR_ADC_PERPH_RESET_CTL2 0xD9 +#define RR_ADC_PERPH_RESET_CTL3 0xDA +#define RR_ADC_PERPH_RESET_CTL4 0xDB +#define RR_ADC_INT_TEST1 0xE0 +#define RR_ADC_INT_TEST_VAL 0xE1 + +#define RR_ADC_TM_TRIGGER_CTRLS 0xE2 +#define RR_ADC_TM_ADC_CTRLS 0xE3 +#define RR_ADC_TM_CNL_CTRL 0xE4 +#define RR_ADC_TM_BATT_ID_CTRL 0xE5 +#define RR_ADC_TM_THERM_CTRL 0xE6 +#define RR_ADC_TM_CONV_STS 0xE7 +#define RR_ADC_TM_ADC_READ_LSB 0xE8 +#define RR_ADC_TM_ADC_READ_MSB 0xE9 +#define RR_ADC_TM_ATEST_MUX_1 0xEA +#define RR_ADC_TM_ATEST_MUX_2 0xEB +#define RR_ADC_TM_REFERENCES 0xED +#define RR_ADC_TM_MISC_CTL 0xEE +#define RR_ADC_TM_RR_CTRL 0xEF + +#define RR_ADC_TRIGGER_EVERY_CYCLE BIT(7) +#define RR_ADC_TRIGGER_CTL BIT(0) + +#define RR_ADC_BATT_ID_RANGE 820 + +#define RR_ADC_BITS 10 +#define RR_ADC_CHAN_MSB (1 << RR_ADC_BITS) +#define RR_ADC_FS_VOLTAGE_MV 2500 + +/* BATT_THERM 0.25K/LSB */ +#define RR_ADC_BATT_THERM_LSB_K 4 + +#define RR_ADC_TEMP_FS_VOLTAGE_NUM 5000000 +#define RR_ADC_TEMP_FS_VOLTAGE_DEN 3 +#define RR_ADC_DIE_TEMP_OFFSET 601400 +#define RR_ADC_DIE_TEMP_SLOPE 2 +#define RR_ADC_DIE_TEMP_OFFSET_MILLI_DEGC 25000 + +#define RR_ADC_CHG_TEMP_GF_OFFSET_UV 1303168 +#define RR_ADC_CHG_TEMP_GF_SLOPE_UV_PER_C 3784 +#define RR_ADC_CHG_TEMP_SMIC_OFFSET_UV 1338433 +#define RR_ADC_CHG_TEMP_SMIC_SLOPE_UV_PER_C 3655 +#define RR_ADC_CHG_TEMP_660_GF_OFFSET_UV 1309001 +#define RR_ADC_CHG_TEMP_660_GF_SLOPE_UV_PER_C 3403 +#define RR_ADC_CHG_TEMP_660_SMIC_OFFSET_UV 1295898 +#define RR_ADC_CHG_TEMP_660_SMIC_SLOPE_UV_PER_C 3596 +#define RR_ADC_CHG_TEMP_660_MGNA_OFFSET_UV 1314779 +#define RR_ADC_CHG_TEMP_660_MGNA_SLOPE_UV_PER_C 3496 +#define RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC 25000 +#define RR_ADC_CHG_THRESHOLD_SCALE 4 + +#define RR_ADC_VOLT_INPUT_FACTOR 8 +#define RR_ADC_CURR_INPUT_FACTOR 2000 +#define RR_ADC_CURR_USBIN_INPUT_FACTOR_MIL 1886 +#define RR_ADC_CURR_USBIN_660_FACTOR_MIL 9 +#define RR_ADC_CURR_USBIN_660_UV_VAL 579500 + +#define RR_ADC_GPIO_FS_RANGE 5000 +#define RR_ADC_COHERENT_CHECK_RETRY 5 +#define RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN 16 + +#define RR_ADC_STS_CHANNEL_READING_MASK GENMASK(1, 0) +#define RR_ADC_STS_CHANNEL_STS BIT(1) + +#define RR_ADC_TP_REV_VERSION1 21 +#define RR_ADC_TP_REV_VERSION2 29 +#define RR_ADC_TP_REV_VERSION3 32 + +#define RRADC_BATT_ID_DELAY_MAX 8 + +enum rradc_channel_id { + RR_ADC_BATT_ID = 0, + RR_ADC_BATT_THERM, + RR_ADC_SKIN_TEMP, + RR_ADC_USBIN_I, + RR_ADC_USBIN_V, + RR_ADC_DCIN_I, + RR_ADC_DCIN_V, + RR_ADC_DIE_TEMP, + RR_ADC_CHG_TEMP, + RR_ADC_GPIO, + RR_ADC_CHAN_MAX +}; + +struct rradc_chip; + +/** + * struct rradc_channel - rradc channel data + * @label: channel label + * @lsb: Channel least significant byte + * @status: Channel status address + * @size: number of bytes to read + * @trigger_addr: Trigger address, trigger is only used on some channels + * @trigger_mask: Trigger mask + * @scale_fn: Post process callback for channels which can't be exposed + * as offset + scale. + */ +struct rradc_channel { + const char *label; + u8 lsb; + u8 status; + int size; + int trigger_addr; + int trigger_mask; + int (*scale_fn)(struct rradc_chip *chip, u16 adc_code, int *result); +}; + +struct rradc_chip { + struct device *dev; + const struct qcom_spmi_pmic *pmic; + /* + * Lock held while doing channel conversion + * involving multiple register read/writes + */ + struct mutex conversion_lock; + struct regmap *regmap; + u32 base; + int batt_id_delay; + u16 batt_id_data; +}; + +static const int batt_id_delays[] = { 0, 1, 4, 12, 20, 40, 60, 80 }; +static const struct rradc_channel rradc_chans[RR_ADC_CHAN_MAX]; +static const struct iio_chan_spec rradc_iio_chans[RR_ADC_CHAN_MAX]; + +static int rradc_read(struct rradc_chip *chip, u16 addr, __le16 *buf, int len) +{ + int ret, retry_cnt = 0; + __le16 data_check[RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN / 2]; + + if (len > RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN) { + dev_err(chip->dev, + "Can't read more than %d bytes, but asked to read %d bytes.\n", + RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN, len); + return -EINVAL; + } + + while (retry_cnt < RR_ADC_COHERENT_CHECK_RETRY) { + ret = regmap_bulk_read(chip->regmap, chip->base + addr, buf, + len); + if (ret < 0) { + dev_err(chip->dev, "rr_adc reg 0x%x failed :%d\n", addr, + ret); + return ret; + } + + ret = regmap_bulk_read(chip->regmap, chip->base + addr, + data_check, len); + if (ret < 0) { + dev_err(chip->dev, "rr_adc reg 0x%x failed :%d\n", addr, + ret); + return ret; + } + + if (memcmp(buf, data_check, len) != 0) { + retry_cnt++; + dev_dbg(chip->dev, + "coherent read error, retry_cnt:%d\n", + retry_cnt); + continue; + } + + break; + } + + if (retry_cnt == RR_ADC_COHERENT_CHECK_RETRY) + dev_err(chip->dev, "Retry exceeded for coherency check\n"); + + return ret; +} + +static int rradc_get_fab_coeff(struct rradc_chip *chip, int64_t *offset, + int64_t *slope) +{ + if (chip->pmic->subtype == PM660_SUBTYPE) { + switch (chip->pmic->fab_id) { + case PM660_FAB_ID_GF: + *offset = RR_ADC_CHG_TEMP_660_GF_OFFSET_UV; + *slope = RR_ADC_CHG_TEMP_660_GF_SLOPE_UV_PER_C; + return 0; + case PM660_FAB_ID_TSMC: + *offset = RR_ADC_CHG_TEMP_660_SMIC_OFFSET_UV; + *slope = RR_ADC_CHG_TEMP_660_SMIC_SLOPE_UV_PER_C; + return 0; + default: + *offset = RR_ADC_CHG_TEMP_660_MGNA_OFFSET_UV; + *slope = RR_ADC_CHG_TEMP_660_MGNA_SLOPE_UV_PER_C; + } + } else if (chip->pmic->subtype == PMI8998_SUBTYPE) { + switch (chip->pmic->fab_id) { + case PMI8998_FAB_ID_GF: + *offset = RR_ADC_CHG_TEMP_GF_OFFSET_UV; + *slope = RR_ADC_CHG_TEMP_GF_SLOPE_UV_PER_C; + return 0; + case PMI8998_FAB_ID_SMIC: + *offset = RR_ADC_CHG_TEMP_SMIC_OFFSET_UV; + *slope = RR_ADC_CHG_TEMP_SMIC_SLOPE_UV_PER_C; + return 0; + default: + return -EINVAL; + } + } + + return -EINVAL; +} + +/* + * These functions explicitly cast int64_t to int. + * They will never overflow, as the values are small enough. + */ +static int rradc_post_process_batt_id(struct rradc_chip *chip, u16 adc_code, + int *result_ohms) +{ + uint32_t current_value; + int64_t r_id; + + current_value = chip->batt_id_data; + r_id = ((int64_t)adc_code * RR_ADC_FS_VOLTAGE_MV); + r_id = div64_s64(r_id, (RR_ADC_CHAN_MSB * current_value)); + *result_ohms = (int)(r_id * MILLI); + + return 0; +} + +static int rradc_enable_continuous_mode(struct rradc_chip *chip) +{ + int ret; + + /* Clear channel log */ + ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_LOG, + RR_ADC_LOG_CLR_CTRL, RR_ADC_LOG_CLR_CTRL); + if (ret < 0) { + dev_err(chip->dev, "log ctrl update to clear failed:%d\n", ret); + return ret; + } + + ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_LOG, + RR_ADC_LOG_CLR_CTRL, 0); + if (ret < 0) { + dev_err(chip->dev, "log ctrl update to not clear failed:%d\n", + ret); + return ret; + } + + /* Switch to continuous mode */ + ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_CTL, + RR_ADC_CTL_CONTINUOUS_SEL, + RR_ADC_CTL_CONTINUOUS_SEL); + if (ret < 0) + dev_err(chip->dev, "Update to continuous mode failed:%d\n", + ret); + + return ret; +} + +static int rradc_disable_continuous_mode(struct rradc_chip *chip) +{ + int ret; + + /* Switch to non continuous mode */ + ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_CTL, + RR_ADC_CTL_CONTINUOUS_SEL, 0); + if (ret < 0) + dev_err(chip->dev, "Update to non-continuous mode failed:%d\n", + ret); + + return ret; +} + +static bool rradc_is_ready(struct rradc_chip *chip, + enum rradc_channel_id chan_address) +{ + const struct rradc_channel *chan = &rradc_chans[chan_address]; + int ret; + unsigned int status, mask; + + /* BATT_ID STS bit does not get set initially */ + switch (chan_address) { + case RR_ADC_BATT_ID: + mask = RR_ADC_STS_CHANNEL_STS; + break; + default: + mask = RR_ADC_STS_CHANNEL_READING_MASK; + break; + } + + ret = regmap_read(chip->regmap, chip->base + chan->status, &status); + if (ret < 0 || !(status & mask)) + return false; + + return true; +} + +static int rradc_read_status_in_cont_mode(struct rradc_chip *chip, + enum rradc_channel_id chan_address) +{ + const struct rradc_channel *chan = &rradc_chans[chan_address]; + const struct iio_chan_spec *iio_chan = &rradc_iio_chans[chan_address]; + int ret, i; + + if (chan->trigger_mask == 0) { + dev_err(chip->dev, "Channel doesn't have a trigger mask\n"); + return -EINVAL; + } + + ret = regmap_update_bits(chip->regmap, chip->base + chan->trigger_addr, + chan->trigger_mask, chan->trigger_mask); + if (ret < 0) { + dev_err(chip->dev, + "Failed to apply trigger for channel '%s' ret=%d\n", + iio_chan->extend_name, ret); + return ret; + } + + ret = rradc_enable_continuous_mode(chip); + if (ret < 0) { + dev_err(chip->dev, "Failed to switch to continuous mode\n"); + goto disable_trigger; + } + + /* + * The wait/sleep values were found through trial and error, + * this is mostly for the battery ID channel which takes some + * time to settle. + */ + for (i = 0; i < 5; i++) { + if (rradc_is_ready(chip, chan_address)) + break; + usleep_range(50000, 50000 + 500); + } + + if (i == 5) { + dev_err(chip->dev, "Channel '%s' is not ready\n", + iio_chan->extend_name); + ret = -ETIMEDOUT; + } + + rradc_disable_continuous_mode(chip); + +disable_trigger: + regmap_update_bits(chip->regmap, chip->base + chan->trigger_addr, + chan->trigger_mask, 0); + + return ret; +} + +static int rradc_prepare_batt_id_conversion(struct rradc_chip *chip, + enum rradc_channel_id chan_address, + u16 *data) +{ + int ret; + + ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL, + RR_ADC_BATT_ID_CTRL_CHANNEL_CONV, + RR_ADC_BATT_ID_CTRL_CHANNEL_CONV); + if (ret < 0) { + dev_err(chip->dev, "Enabling BATT ID channel failed:%d\n", ret); + return ret; + } + + ret = regmap_update_bits(chip->regmap, + chip->base + RR_ADC_BATT_ID_TRIGGER, + RR_ADC_TRIGGER_CTL, RR_ADC_TRIGGER_CTL); + if (ret < 0) { + dev_err(chip->dev, "BATT_ID trigger set failed:%d\n", ret); + goto out_disable_batt_id; + } + + ret = rradc_read_status_in_cont_mode(chip, chan_address); + + /* Reset registers back to default values */ + regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_TRIGGER, + RR_ADC_TRIGGER_CTL, 0); + +out_disable_batt_id: + regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL, + RR_ADC_BATT_ID_CTRL_CHANNEL_CONV, 0); + + return ret; +} + +static int rradc_do_conversion(struct rradc_chip *chip, + enum rradc_channel_id chan_address, u16 *data) +{ + const struct rradc_channel *chan = &rradc_chans[chan_address]; + const struct iio_chan_spec *iio_chan = &rradc_iio_chans[chan_address]; + int ret; + __le16 buf[3]; + + mutex_lock(&chip->conversion_lock); + + switch (chan_address) { + case RR_ADC_BATT_ID: + ret = rradc_prepare_batt_id_conversion(chip, chan_address, data); + if (ret < 0) { + dev_err(chip->dev, "Battery ID conversion failed:%d\n", + ret); + goto unlock_out; + } + break; + + case RR_ADC_USBIN_V: + case RR_ADC_DIE_TEMP: + ret = rradc_read_status_in_cont_mode(chip, chan_address); + if (ret < 0) { + dev_err(chip->dev, + "Error reading in continuous mode:%d\n", ret); + goto unlock_out; + } + break; + default: + if (!rradc_is_ready(chip, chan_address)) { + /* + * Usually this means the channel isn't attached, for example + * the in_voltage_usbin_v_input channel will not be ready if + * no USB cable is attached + */ + dev_dbg(chip->dev, "channel '%s' is not ready\n", + iio_chan->extend_name); + ret = -ENODATA; + goto unlock_out; + } + break; + } + + ret = rradc_read(chip, chan->lsb, buf, chan->size); + if (ret) { + dev_err(chip->dev, "read data failed\n"); + goto unlock_out; + } + + /* + * For the battery ID we read the register for every ID ADC and then + * see which one is actually connected. + */ + if (chan_address == RR_ADC_BATT_ID) { + u16 batt_id_150 = le16_to_cpu(buf[2]); + u16 batt_id_15 = le16_to_cpu(buf[1]); + u16 batt_id_5 = le16_to_cpu(buf[0]); + + if (!batt_id_150 && !batt_id_15 && !batt_id_5) { + dev_err(chip->dev, + "Invalid batt_id values with all zeros\n"); + ret = -EINVAL; + goto unlock_out; + } + + if (batt_id_150 <= RR_ADC_BATT_ID_RANGE) { + *data = batt_id_150; + chip->batt_id_data = 150; + } else if (batt_id_15 <= RR_ADC_BATT_ID_RANGE) { + *data = batt_id_15; + chip->batt_id_data = 15; + } else { + *data = batt_id_5; + chip->batt_id_data = 5; + } + } else { + /* + * All of the other channels are either 1 or 2 bytes. + * We can rely on the second byte being 0 for 1-byte channels. + */ + *data = le16_to_cpu(buf[0]); + } + +unlock_out: + mutex_unlock(&chip->conversion_lock); + + return ret; +} + +static int rradc_read_scale(struct rradc_chip *chip, int chan_address, int *val, + int *val2) +{ + int64_t fab_offset, fab_slope; + int ret; + + ret = rradc_get_fab_coeff(chip, &fab_offset, &fab_slope); + if (ret < 0) { + dev_err(chip->dev, "Unable to get fab id coefficients\n"); + return -EINVAL; + } + + switch (chan_address) { + case RR_ADC_SKIN_TEMP: + *val = MILLI; + *val2 = RR_ADC_BATT_THERM_LSB_K; + return IIO_VAL_FRACTIONAL; + case RR_ADC_USBIN_I: + *val = RR_ADC_CURR_USBIN_INPUT_FACTOR_MIL * + RR_ADC_FS_VOLTAGE_MV; + *val2 = RR_ADC_CHAN_MSB; + return IIO_VAL_FRACTIONAL; + case RR_ADC_DCIN_I: + *val = RR_ADC_CURR_INPUT_FACTOR * RR_ADC_FS_VOLTAGE_MV; + *val2 = RR_ADC_CHAN_MSB; + return IIO_VAL_FRACTIONAL; + case RR_ADC_USBIN_V: + case RR_ADC_DCIN_V: + *val = RR_ADC_VOLT_INPUT_FACTOR * RR_ADC_FS_VOLTAGE_MV * MILLI; + *val2 = RR_ADC_CHAN_MSB; + return IIO_VAL_FRACTIONAL; + case RR_ADC_GPIO: + *val = RR_ADC_GPIO_FS_RANGE; + *val2 = RR_ADC_CHAN_MSB; + return IIO_VAL_FRACTIONAL; + case RR_ADC_CHG_TEMP: + /* + * We divide val2 by MILLI instead of multiplying val + * to avoid an integer overflow. + */ + *val = -RR_ADC_TEMP_FS_VOLTAGE_NUM; + *val2 = div64_s64(RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB * + fab_slope, + MILLI); + + return IIO_VAL_FRACTIONAL; + case RR_ADC_DIE_TEMP: + *val = RR_ADC_TEMP_FS_VOLTAGE_NUM; + *val2 = RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB * + RR_ADC_DIE_TEMP_SLOPE; + + return IIO_VAL_FRACTIONAL; + default: + return -EINVAL; + } +} + +static int rradc_read_offset(struct rradc_chip *chip, int chan_address, int *val) +{ + int64_t fab_offset, fab_slope; + int64_t offset1, offset2; + int ret; + + switch (chan_address) { + case RR_ADC_SKIN_TEMP: + /* + * Offset from kelvin to degC, divided by the + * scale factor (250). We lose some precision here. + * 273150 / 250 = 1092.6 + */ + *val = div64_s64(ABSOLUTE_ZERO_MILLICELSIUS, + (MILLI / RR_ADC_BATT_THERM_LSB_K)); + return IIO_VAL_INT; + case RR_ADC_CHG_TEMP: + ret = rradc_get_fab_coeff(chip, &fab_offset, &fab_slope); + if (ret < 0) { + dev_err(chip->dev, + "Unable to get fab id coefficients\n"); + return -EINVAL; + } + offset1 = -(fab_offset * RR_ADC_TEMP_FS_VOLTAGE_DEN * + RR_ADC_CHAN_MSB); + offset1 += (int64_t)RR_ADC_TEMP_FS_VOLTAGE_NUM / 2ULL; + offset1 = div64_s64(offset1, + (int64_t)(RR_ADC_TEMP_FS_VOLTAGE_NUM)); + + offset2 = (int64_t)RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC * + RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB * + (int64_t)fab_slope; + offset2 += ((int64_t)MILLI * RR_ADC_TEMP_FS_VOLTAGE_NUM) / 2; + offset2 = div64_s64( + offset2, ((int64_t)MILLI * RR_ADC_TEMP_FS_VOLTAGE_NUM)); + + /* + * The -1 is to compensate for lost precision. + * It should actually be -0.7906976744186046. + * This works out to every value being off + * by about +0.091 degrees C after applying offset and scale. + */ + *val = (int)(offset1 - offset2 - 1); + return IIO_VAL_INT; + case RR_ADC_DIE_TEMP: + offset1 = -RR_ADC_DIE_TEMP_OFFSET * + (int64_t)RR_ADC_TEMP_FS_VOLTAGE_DEN * + (int64_t)RR_ADC_CHAN_MSB; + offset1 = div64_s64(offset1, RR_ADC_TEMP_FS_VOLTAGE_NUM); + + offset2 = -(int64_t)RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC * + RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB * + RR_ADC_DIE_TEMP_SLOPE; + offset2 = div64_s64(offset2, + ((int64_t)RR_ADC_TEMP_FS_VOLTAGE_NUM)); + + /* + * The result is -339, it should be -338.69789, this results + * in the calculated die temp being off by + * -0.004 - -0.0175 degrees C + */ + *val = (int)(offset1 - offset2); + return IIO_VAL_INT; + default: + break; + } + return -EINVAL; +} + +static int rradc_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan_spec, int *val, + int *val2, long mask) +{ + struct rradc_chip *chip = iio_priv(indio_dev); + const struct rradc_channel *chan; + int ret; + u16 adc_code; + + if (chan_spec->address >= RR_ADC_CHAN_MAX) { + dev_err(chip->dev, "Invalid channel index:%lu\n", + chan_spec->address); + return -EINVAL; + } + + switch (mask) { + case IIO_CHAN_INFO_SCALE: + return rradc_read_scale(chip, chan_spec->address, val, val2); + case IIO_CHAN_INFO_OFFSET: + return rradc_read_offset(chip, chan_spec->address, val); + case IIO_CHAN_INFO_RAW: + ret = rradc_do_conversion(chip, chan_spec->address, &adc_code); + if (ret < 0) + return ret; + + *val = adc_code; + return IIO_VAL_INT; + case IIO_CHAN_INFO_PROCESSED: + chan = &rradc_chans[chan_spec->address]; + if (!chan->scale_fn) + return -EINVAL; + ret = rradc_do_conversion(chip, chan_spec->address, &adc_code); + if (ret < 0) + return ret; + + *val = chan->scale_fn(chip, adc_code, val); + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int rradc_read_label(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, char *label) +{ + return snprintf(label, PAGE_SIZE, "%s\n", + rradc_chans[chan->address].label); +} + +static const struct iio_info rradc_info = { + .read_raw = rradc_read_raw, + .read_label = rradc_read_label, +}; + +static const struct rradc_channel rradc_chans[RR_ADC_CHAN_MAX] = { + { + .label = "batt_id", + .scale_fn = rradc_post_process_batt_id, + .lsb = RR_ADC_BATT_ID_5_LSB, + .status = RR_ADC_BATT_ID_STS, + .size = 6, + .trigger_addr = RR_ADC_BATT_ID_TRIGGER, + .trigger_mask = BIT(0), + }, { + .label = "batt", + .lsb = RR_ADC_BATT_THERM_LSB, + .status = RR_ADC_BATT_THERM_STS, + .size = 2, + .trigger_addr = RR_ADC_BATT_THERM_TRIGGER, + }, { + .label = "pmi8998_skin", + .lsb = RR_ADC_SKIN_TEMP_LSB, + .status = RR_ADC_AUX_THERM_STS, + .size = 2, + .trigger_addr = RR_ADC_AUX_THERM_TRIGGER, + }, { + .label = "usbin_i", + .lsb = RR_ADC_USB_IN_I_LSB, + .status = RR_ADC_USB_IN_I_STS, + .size = 2, + .trigger_addr = RR_ADC_USB_IN_I_TRIGGER, + }, { + .label = "usbin_v", + .lsb = RR_ADC_USB_IN_V_LSB, + .status = RR_ADC_USB_IN_V_STS, + .size = 2, + .trigger_addr = RR_ADC_USB_IN_V_TRIGGER, + .trigger_mask = BIT(7), + }, { + .label = "dcin_i", + .lsb = RR_ADC_DC_IN_I_LSB, + .status = RR_ADC_DC_IN_I_STS, + .size = 2, + .trigger_addr = RR_ADC_DC_IN_I_TRIGGER, + }, { + .label = "dcin_v", + .lsb = RR_ADC_DC_IN_V_LSB, + .status = RR_ADC_DC_IN_V_STS, + .size = 2, + .trigger_addr = RR_ADC_DC_IN_V_TRIGGER, + }, { + .label = "pmi8998_die", + .lsb = RR_ADC_PMI_DIE_TEMP_LSB, + .status = RR_ADC_PMI_DIE_TEMP_STS, + .size = 2, + .trigger_addr = RR_ADC_PMI_DIE_TEMP_TRIGGER, + .trigger_mask = RR_ADC_TRIGGER_EVERY_CYCLE, + }, { + .label = "chg", + .lsb = RR_ADC_CHARGER_TEMP_LSB, + .status = RR_ADC_CHARGER_TEMP_STS, + .size = 2, + .trigger_addr = RR_ADC_CHARGER_TEMP_TRIGGER, + }, { + .label = "gpio", + .lsb = RR_ADC_GPIO_LSB, + .status = RR_ADC_GPIO_STS, + .size = 2, + .trigger_addr = RR_ADC_GPIO_TRIGGER, + }, +}; + +static const struct iio_chan_spec rradc_iio_chans[RR_ADC_CHAN_MAX] = { + { + .type = IIO_RESISTANCE, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), + .address = RR_ADC_BATT_ID, + .channel = 0, + .indexed = 1, + }, { + .type = IIO_TEMP, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), + .address = RR_ADC_BATT_THERM, + .channel = 0, + .indexed = 1, + }, { + .type = IIO_TEMP, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_OFFSET), + .address = RR_ADC_SKIN_TEMP, + .channel = 1, + .indexed = 1, + }, { + .type = IIO_CURRENT, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + .address = RR_ADC_USBIN_I, + .channel = 0, + .indexed = 1, + }, { + .type = IIO_VOLTAGE, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + .address = RR_ADC_USBIN_V, + .channel = 0, + .indexed = 1, + }, { + .type = IIO_CURRENT, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + .address = RR_ADC_DCIN_I, + .channel = 1, + .indexed = 1, + }, { + .type = IIO_VOLTAGE, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + .address = RR_ADC_DCIN_V, + .channel = 1, + .indexed = 1, + }, { + .type = IIO_TEMP, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_OFFSET), + .address = RR_ADC_DIE_TEMP, + .channel = 2, + .indexed = 1, + }, { + .type = IIO_TEMP, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_OFFSET) | + BIT(IIO_CHAN_INFO_SCALE), + .address = RR_ADC_CHG_TEMP, + .channel = 3, + .indexed = 1, + }, { + .type = IIO_VOLTAGE, + .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | + BIT(IIO_CHAN_INFO_SCALE), + .address = RR_ADC_GPIO, + .channel = 2, + .indexed = 1, + }, +}; + +static int rradc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct iio_dev *indio_dev; + struct rradc_chip *chip; + int ret, i, batt_id_delay; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*chip)); + if (!indio_dev) + return -ENOMEM; + + chip = iio_priv(indio_dev); + chip->regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!chip->regmap) { + dev_err(dev, "Couldn't get parent's regmap\n"); + return -EINVAL; + } + + chip->dev = dev; + mutex_init(&chip->conversion_lock); + + ret = device_property_read_u32(dev, "reg", &chip->base); + if (ret < 0) { + dev_err(chip->dev, "Couldn't find reg address, ret = %d\n", + ret); + return ret; + } + + batt_id_delay = -1; + ret = device_property_read_u32(dev, "qcom,batt-id-delay-ms", + &batt_id_delay); + if (!ret) { + for (i = 0; i < RRADC_BATT_ID_DELAY_MAX; i++) { + if (batt_id_delay == batt_id_delays[i]) + break; + } + if (i == RRADC_BATT_ID_DELAY_MAX) + batt_id_delay = -1; + } + + if (batt_id_delay >= 0) { + batt_id_delay = FIELD_PREP(BATT_ID_SETTLE_MASK, batt_id_delay); + ret = regmap_update_bits(chip->regmap, + chip->base + RR_ADC_BATT_ID_CFG, + batt_id_delay, batt_id_delay); + if (ret < 0) { + dev_err(chip->dev, + "BATT_ID settling time config failed:%d\n", + ret); + } + } + + /* Get the PMIC revision, we need it to handle some varying coefficients */ + chip->pmic = qcom_pmic_get(chip->dev); + if (IS_ERR(chip->pmic)) { + dev_err(chip->dev, "Unable to get reference to PMIC device\n"); + return PTR_ERR(chip->pmic); + } + + switch (chip->pmic->subtype) { + case PMI8998_SUBTYPE: + indio_dev->name = "pmi8998-rradc"; + break; + case PM660_SUBTYPE: + indio_dev->name = "pm660-rradc"; + break; + default: + indio_dev->name = DRIVER_NAME; + break; + } + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->info = &rradc_info; + indio_dev->channels = rradc_iio_chans; + indio_dev->num_channels = ARRAY_SIZE(rradc_iio_chans); + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct of_device_id rradc_match_table[] = { + { .compatible = "qcom,pm660-rradc" }, + { .compatible = "qcom,pmi8998-rradc" }, + {} +}; +MODULE_DEVICE_TABLE(of, rradc_match_table); + +static struct platform_driver rradc_driver = { + .driver = { + .name = DRIVER_NAME, + .of_match_table = rradc_match_table, + }, + .probe = rradc_probe, +}; +module_platform_driver(rradc_driver); + +MODULE_DESCRIPTION("QCOM SPMI PMIC RR ADC driver"); +MODULE_AUTHOR("Caleb Connolly "); +MODULE_LICENSE("GPL"); diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c index 5b09a93fdf34..0921ff2d9b3a 100644 --- a/drivers/iio/adc/rzg2l_adc.c +++ b/drivers/iio/adc/rzg2l_adc.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #define DRIVER_NAME "rzg2l-adc" @@ -260,9 +261,6 @@ static int rzg2l_adc_read_label(struct iio_dev *iio_dev, const struct iio_chan_spec *chan, char *label) { - if (chan->channel >= RZG2L_ADC_MAX_CHANNELS) - return -EINVAL; - return sysfs_emit(label, "%s\n", rzg2l_adc_channel_name[chan->channel]); } diff --git a/drivers/iio/adc/sc27xx_adc.c b/drivers/iio/adc/sc27xx_adc.c index e9ff2d6a8a57..f8421cbba8fa 100644 --- a/drivers/iio/adc/sc27xx_adc.c +++ b/drivers/iio/adc/sc27xx_adc.c @@ -579,15 +579,14 @@ unlock_adc: return ret; } -static void sc27xx_adc_volt_ratio(struct sc27xx_adc_data *data, - int channel, int scale, - u32 *div_numerator, u32 *div_denominator) +static void sc27xx_adc_volt_ratio(struct sc27xx_adc_data *data, int channel, int scale, + struct u32_fract *fract) { u32 ratio; ratio = data->var_data->get_ratio(channel, scale); - *div_numerator = ratio >> SC27XX_RATIO_NUMERATOR_OFFSET; - *div_denominator = ratio & SC27XX_RATIO_DENOMINATOR_MASK; + fract->numerator = ratio >> SC27XX_RATIO_NUMERATOR_OFFSET; + fract->denominator = ratio & SC27XX_RATIO_DENOMINATOR_MASK; } static int adc_to_volt(struct sc27xx_adc_linear_graph *graph, @@ -615,7 +614,7 @@ static int sc27xx_adc_to_volt(struct sc27xx_adc_linear_graph *graph, static int sc27xx_adc_convert_volt(struct sc27xx_adc_data *data, int channel, int scale, int raw_adc) { - u32 numerator, denominator; + struct u32_fract fract; u32 volt; /* @@ -637,9 +636,9 @@ static int sc27xx_adc_convert_volt(struct sc27xx_adc_data *data, int channel, break; } - sc27xx_adc_volt_ratio(data, channel, scale, &numerator, &denominator); + sc27xx_adc_volt_ratio(data, channel, scale, &fract); - return DIV_ROUND_CLOSEST(volt * denominator, numerator); + return DIV_ROUND_CLOSEST(volt * fract.denominator, fract.numerator); } static int sc27xx_adc_read_processed(struct sc27xx_adc_data *data, diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-core.c index 3efb8c404ccc..1ce52af3fe8b 100644 --- a/drivers/iio/adc/stm32-adc-core.c +++ b/drivers/iio/adc/stm32-adc-core.c @@ -358,7 +358,7 @@ static void stm32_adc_irq_handler(struct irq_desc *desc) if ((status & priv->cfg->regs->eoc_msk[i] && stm32_adc_eoc_enabled(priv, i)) || (status & priv->cfg->regs->ovr_msk[i])) - generic_handle_irq(irq_find_mapping(priv->domain, i)); + generic_handle_domain_irq(priv->domain, i); } chained_irq_exit(chip, desc); diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c index 11ef873d6453..130e8dd6f0c8 100644 --- a/drivers/iio/adc/stm32-adc.c +++ b/drivers/iio/adc/stm32-adc.c @@ -876,6 +876,9 @@ static void stm32h7_adc_disable(struct iio_dev *indio_dev) int ret; u32 val; + if (!(stm32_adc_readl(adc, STM32H7_ADC_CR) & STM32H7_ADEN)) + return; + /* Disable ADC and wait until it's effectively disabled */ stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, @@ -1016,6 +1019,9 @@ static int stm32h7_adc_selfcalib(struct iio_dev *indio_dev) if (adc->cal.calibrated) return true; + /* ADC must be disabled for calibration */ + stm32h7_adc_disable(indio_dev); + /* * Select calibration mode: * - Offset calibration for single ended inputs diff --git a/drivers/iio/adc/stmpe-adc.c b/drivers/iio/adc/stmpe-adc.c index 000e5cfecb43..67518e460e05 100644 --- a/drivers/iio/adc/stmpe-adc.c +++ b/drivers/iio/adc/stmpe-adc.c @@ -333,7 +333,7 @@ static int stmpe_adc_probe(struct platform_device *pdev) return devm_iio_device_register(&pdev->dev, indio_dev); } -static int __maybe_unused stmpe_adc_resume(struct device *dev) +static int stmpe_adc_resume(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); struct stmpe_adc *info = iio_priv(indio_dev); @@ -343,7 +343,7 @@ static int __maybe_unused stmpe_adc_resume(struct device *dev) return 0; } -static SIMPLE_DEV_PM_OPS(stmpe_adc_pm_ops, NULL, stmpe_adc_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(stmpe_adc_pm_ops, NULL, stmpe_adc_resume); static const struct of_device_id stmpe_adc_ids[] = { { .compatible = "st,stmpe-adc", }, @@ -355,7 +355,7 @@ static struct platform_driver stmpe_adc_driver = { .probe = stmpe_adc_probe, .driver = { .name = "stmpe-adc", - .pm = &stmpe_adc_pm_ops, + .pm = pm_sleep_ptr(&stmpe_adc_pm_ops), .of_match_table = stmpe_adc_ids, }, }; diff --git a/drivers/iio/adc/stx104.c b/drivers/iio/adc/stx104.c index 55bd2dc514e9..48a91a95e597 100644 --- a/drivers/iio/adc/stx104.c +++ b/drivers/iio/adc/stx104.c @@ -16,6 +16,7 @@ #include #include #include +#include #define STX104_OUT_CHAN(chan) { \ .type = IIO_VOLTAGE, \ @@ -44,14 +45,36 @@ static unsigned int num_stx104; module_param_hw_array(base, uint, ioport, &num_stx104, 0); MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base addresses"); +/** + * struct stx104_reg - device register structure + * @ssr_ad: Software Strobe Register and ADC Data + * @achan: ADC Channel + * @dio: Digital I/O + * @dac: DAC Channels + * @cir_asr: Clear Interrupts and ADC Status + * @acr: ADC Control + * @pccr_fsh: Pacer Clock Control and FIFO Status MSB + * @acfg: ADC Configuration + */ +struct stx104_reg { + u16 ssr_ad; + u8 achan; + u8 dio; + u16 dac[2]; + u8 cir_asr; + u8 acr; + u8 pccr_fsh; + u8 acfg; +}; + /** * struct stx104_iio - IIO device private data structure * @chan_out_states: channels' output states - * @base: base port address of the IIO device + * @reg: I/O address offset for the device registers */ struct stx104_iio { unsigned int chan_out_states[STX104_NUM_OUT_CHAN]; - unsigned int base; + struct stx104_reg __iomem *reg; }; /** @@ -64,7 +87,7 @@ struct stx104_iio { struct stx104_gpio { struct gpio_chip chip; spinlock_t lock; - unsigned int base; + u8 __iomem *base; unsigned int out_state; }; @@ -72,6 +95,7 @@ static int stx104_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) { struct stx104_iio *const priv = iio_priv(indio_dev); + struct stx104_reg __iomem *const reg = priv->reg; unsigned int adc_config; int adbu; int gain; @@ -79,7 +103,7 @@ static int stx104_read_raw(struct iio_dev *indio_dev, switch (mask) { case IIO_CHAN_INFO_HARDWAREGAIN: /* get gain configuration */ - adc_config = inb(priv->base + 11); + adc_config = ioread8(®->acfg); gain = adc_config & 0x3; *val = 1 << gain; @@ -91,24 +115,26 @@ static int stx104_read_raw(struct iio_dev *indio_dev, } /* select ADC channel */ - outb(chan->channel | (chan->channel << 4), priv->base + 2); + iowrite8(chan->channel | (chan->channel << 4), ®->achan); - /* trigger ADC sample capture and wait for completion */ - outb(0, priv->base); - while (inb(priv->base + 8) & BIT(7)); + /* trigger ADC sample capture by writing to the 8-bit + * Software Strobe Register and wait for completion + */ + iowrite8(0, ®->ssr_ad); + while (ioread8(®->cir_asr) & BIT(7)); - *val = inw(priv->base); + *val = ioread16(®->ssr_ad); return IIO_VAL_INT; case IIO_CHAN_INFO_OFFSET: /* get ADC bipolar/unipolar configuration */ - adc_config = inb(priv->base + 11); + adc_config = ioread8(®->acfg); adbu = !(adc_config & BIT(2)); *val = -32768 * adbu; return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: /* get ADC bipolar/unipolar and gain configuration */ - adc_config = inb(priv->base + 11); + adc_config = ioread8(®->acfg); adbu = !(adc_config & BIT(2)); gain = adc_config & 0x3; @@ -130,16 +156,16 @@ static int stx104_write_raw(struct iio_dev *indio_dev, /* Only four gain states (x1, x2, x4, x8) */ switch (val) { case 1: - outb(0, priv->base + 11); + iowrite8(0, &priv->reg->acfg); break; case 2: - outb(1, priv->base + 11); + iowrite8(1, &priv->reg->acfg); break; case 4: - outb(2, priv->base + 11); + iowrite8(2, &priv->reg->acfg); break; case 8: - outb(3, priv->base + 11); + iowrite8(3, &priv->reg->acfg); break; default: return -EINVAL; @@ -153,7 +179,7 @@ static int stx104_write_raw(struct iio_dev *indio_dev, return -EINVAL; priv->chan_out_states[chan->channel] = val; - outw(val, priv->base + 4 + 2 * chan->channel); + iowrite16(val, &priv->reg->dac[chan->channel]); return 0; } @@ -222,7 +248,7 @@ static int stx104_gpio_get(struct gpio_chip *chip, unsigned int offset) if (offset >= 4) return -EINVAL; - return !!(inb(stx104gpio->base) & BIT(offset)); + return !!(ioread8(stx104gpio->base) & BIT(offset)); } static int stx104_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, @@ -230,7 +256,7 @@ static int stx104_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, { struct stx104_gpio *const stx104gpio = gpiochip_get_data(chip); - *bits = inb(stx104gpio->base); + *bits = ioread8(stx104gpio->base); return 0; } @@ -252,7 +278,7 @@ static void stx104_gpio_set(struct gpio_chip *chip, unsigned int offset, else stx104gpio->out_state &= ~mask; - outb(stx104gpio->out_state, stx104gpio->base); + iowrite8(stx104gpio->out_state, stx104gpio->base); spin_unlock_irqrestore(&stx104gpio->lock, flags); } @@ -279,7 +305,7 @@ static void stx104_gpio_set_multiple(struct gpio_chip *chip, stx104gpio->out_state &= ~*mask; stx104gpio->out_state |= *mask & *bits; - outb(stx104gpio->out_state, stx104gpio->base); + iowrite8(stx104gpio->out_state, stx104gpio->base); spin_unlock_irqrestore(&stx104gpio->lock, flags); } @@ -306,11 +332,16 @@ static int stx104_probe(struct device *dev, unsigned int id) return -EBUSY; } + priv = iio_priv(indio_dev); + priv->reg = devm_ioport_map(dev, base[id], STX104_EXTENT); + if (!priv->reg) + return -ENOMEM; + indio_dev->info = &stx104_info; indio_dev->modes = INDIO_DIRECT_MODE; /* determine if differential inputs */ - if (inb(base[id] + 8) & BIT(5)) { + if (ioread8(&priv->reg->cir_asr) & BIT(5)) { indio_dev->num_channels = ARRAY_SIZE(stx104_channels_diff); indio_dev->channels = stx104_channels_diff; } else { @@ -320,18 +351,15 @@ static int stx104_probe(struct device *dev, unsigned int id) indio_dev->name = dev_name(dev); - priv = iio_priv(indio_dev); - priv->base = base[id]; - /* configure device for software trigger operation */ - outb(0, base[id] + 9); + iowrite8(0, &priv->reg->acr); /* initialize gain setting to x1 */ - outb(0, base[id] + 11); + iowrite8(0, &priv->reg->acfg); /* initialize DAC output to 0V */ - outw(0, base[id] + 4); - outw(0, base[id] + 6); + iowrite16(0, &priv->reg->dac[0]); + iowrite16(0, &priv->reg->dac[1]); stx104gpio->chip.label = dev_name(dev); stx104gpio->chip.parent = dev; @@ -346,7 +374,7 @@ static int stx104_probe(struct device *dev, unsigned int id) stx104gpio->chip.get_multiple = stx104_gpio_get_multiple; stx104gpio->chip.set = stx104_gpio_set; stx104gpio->chip.set_multiple = stx104_gpio_set_multiple; - stx104gpio->base = base[id] + 3; + stx104gpio->base = &priv->reg->dio; stx104gpio->out_state = 0x0; spin_lock_init(&stx104gpio->lock); diff --git a/drivers/iio/adc/ti-adc0832.c b/drivers/iio/adc/ti-adc0832.c index fb5e72600b96..b11ce555ba3b 100644 --- a/drivers/iio/adc/ti-adc0832.c +++ b/drivers/iio/adc/ti-adc0832.c @@ -36,7 +36,7 @@ struct adc0832 { */ u8 data[24] __aligned(8); - u8 tx_buf[2] ____cacheline_aligned; + u8 tx_buf[2] __aligned(IIO_DMA_MINALIGN); u8 rx_buf[2]; }; diff --git a/drivers/iio/adc/ti-adc084s021.c b/drivers/iio/adc/ti-adc084s021.c index c9b5d9aec3dc..1f6e53832e06 100644 --- a/drivers/iio/adc/ti-adc084s021.c +++ b/drivers/iio/adc/ti-adc084s021.c @@ -32,10 +32,10 @@ struct adc084s021 { s64 ts __aligned(8); } scan; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache line. */ - u16 tx_buf[4] ____cacheline_aligned; + u16 tx_buf[4] __aligned(IIO_DMA_MINALIGN); __be16 rx_buf[5]; /* First 16-bits are trash */ }; diff --git a/drivers/iio/adc/ti-adc108s102.c b/drivers/iio/adc/ti-adc108s102.c index c8e48881c37f..c82a161630e1 100644 --- a/drivers/iio/adc/ti-adc108s102.c +++ b/drivers/iio/adc/ti-adc108s102.c @@ -77,8 +77,8 @@ struct adc108s102_state { * tx_buf: 8 channel read commands, plus 1 dummy command * rx_buf: 1 dummy response, 8 channel responses */ - __be16 rx_buf[9] ____cacheline_aligned; - __be16 tx_buf[9] ____cacheline_aligned; + __be16 rx_buf[9] __aligned(IIO_DMA_MINALIGN); + __be16 tx_buf[9] __aligned(IIO_DMA_MINALIGN); }; #define ADC108S102_V_CHAN(index) \ diff --git a/drivers/iio/adc/ti-adc12138.c b/drivers/iio/adc/ti-adc12138.c index 59d75d09604f..c0a72d72f3a9 100644 --- a/drivers/iio/adc/ti-adc12138.c +++ b/drivers/iio/adc/ti-adc12138.c @@ -55,7 +55,7 @@ struct adc12138 { */ __be16 data[20] __aligned(8); - u8 tx_buf[2] ____cacheline_aligned; + u8 tx_buf[2] __aligned(IIO_DMA_MINALIGN); u8 rx_buf[2]; }; diff --git a/drivers/iio/adc/ti-adc128s052.c b/drivers/iio/adc/ti-adc128s052.c index 8e7adec87755..622fd384983c 100644 --- a/drivers/iio/adc/ti-adc128s052.c +++ b/drivers/iio/adc/ti-adc128s052.c @@ -29,7 +29,7 @@ struct adc128 { struct regulator *reg; struct mutex lock; - u8 buffer[2] ____cacheline_aligned; + u8 buffer[2] __aligned(IIO_DMA_MINALIGN); }; static int adc128_adc_conversion(struct adc128 *adc, u8 channel) diff --git a/drivers/iio/adc/ti-adc161s626.c b/drivers/iio/adc/ti-adc161s626.c index 75ca7f1c8726..b789891dcf49 100644 --- a/drivers/iio/adc/ti-adc161s626.c +++ b/drivers/iio/adc/ti-adc161s626.c @@ -71,7 +71,7 @@ struct ti_adc_data { u8 read_size; u8 shift; - u8 buffer[16] ____cacheline_aligned; + u8 buffer[16] __aligned(IIO_DMA_MINALIGN); }; static int ti_adc_read_measurement(struct ti_adc_data *data, diff --git a/drivers/iio/adc/ti-ads1015.c b/drivers/iio/adc/ti-ads1015.c index 5544da80b636..e3dfc155fbe2 100644 --- a/drivers/iio/adc/ti-ads1015.c +++ b/drivers/iio/adc/ti-ads1015.c @@ -1098,6 +1098,7 @@ static int ads1015_remove(struct i2c_client *client) { struct iio_dev *indio_dev = i2c_get_clientdata(client); struct ads1015_data *data = iio_priv(indio_dev); + int ret; iio_device_unregister(indio_dev); @@ -1105,7 +1106,12 @@ static int ads1015_remove(struct i2c_client *client) pm_runtime_set_suspended(&client->dev); /* power down single shot mode */ - return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT); + ret = ads1015_set_conv_mode(data, ADS1015_SINGLESHOT); + if (ret) + dev_warn(&client->dev, "Failed to power down (%pe)\n", + ERR_PTR(ret)); + + return 0; } #ifdef CONFIG_PM diff --git a/drivers/iio/adc/ti-ads124s08.c b/drivers/iio/adc/ti-ads124s08.c index 767b3b634809..4ca62121f0d1 100644 --- a/drivers/iio/adc/ti-ads124s08.c +++ b/drivers/iio/adc/ti-ads124s08.c @@ -106,7 +106,7 @@ struct ads124s_private { * timestamp is maintained. */ u32 buffer[ADS124S08_MAX_CHANNELS + sizeof(s64)/sizeof(u32)] __aligned(8); - u8 data[5] ____cacheline_aligned; + u8 data[5] __aligned(IIO_DMA_MINALIGN); }; #define ADS124S08_CHAN(index) \ @@ -193,7 +193,7 @@ static int ads124s_reset(struct iio_dev *indio_dev) return 0; }; -static int ads124s_read(struct iio_dev *indio_dev, unsigned int chan) +static int ads124s_read(struct iio_dev *indio_dev) { struct ads124s_private *priv = iio_priv(indio_dev); int ret; @@ -242,7 +242,7 @@ static int ads124s_read_raw(struct iio_dev *indio_dev, goto out; } - ret = ads124s_read(indio_dev, chan->channel); + ret = ads124s_read(indio_dev); if (ret < 0) { dev_err(&priv->spi->dev, "Read ADC failed\n"); goto out; @@ -290,7 +290,7 @@ static irqreturn_t ads124s_trigger_handler(int irq, void *p) if (ret) dev_err(&priv->spi->dev, "Start ADC conversions failed\n"); - priv->buffer[j] = ads124s_read(indio_dev, scan_index); + priv->buffer[j] = ads124s_read(indio_dev); ret = ads124s_write_cmd(indio_dev, ADS124S08_STOP_CONV); if (ret) dev_err(&priv->spi->dev, "Stop ADC conversions failed\n"); diff --git a/drivers/iio/adc/ti-ads131e08.c b/drivers/iio/adc/ti-ads131e08.c index 80a09817c119..32237cacc9a3 100644 --- a/drivers/iio/adc/ti-ads131e08.c +++ b/drivers/iio/adc/ti-ads131e08.c @@ -105,7 +105,7 @@ struct ads131e08_state { s64 ts __aligned(8); } tmp_buf; - u8 tx_buf[3] ____cacheline_aligned; + u8 tx_buf[3] __aligned(IIO_DMA_MINALIGN); /* * Add extra one padding byte to be able to access the last channel * value using u32 pointer diff --git a/drivers/iio/adc/ti-ads7950.c b/drivers/iio/adc/ti-ads7950.c index e3658b969c5b..2cc9a9bd9db6 100644 --- a/drivers/iio/adc/ti-ads7950.c +++ b/drivers/iio/adc/ti-ads7950.c @@ -102,11 +102,11 @@ struct ti_ads7950_state { unsigned int gpio_cmd_settings_bitmask; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ u16 rx_buf[TI_ADS7950_MAX_CHAN + 2 + TI_ADS7950_TIMESTAMP_SIZE] - ____cacheline_aligned; + __aligned(IIO_DMA_MINALIGN); u16 tx_buf[TI_ADS7950_MAX_CHAN + 2]; u16 single_tx; u16 single_rx; diff --git a/drivers/iio/adc/ti-ads8344.c b/drivers/iio/adc/ti-ads8344.c index c96d2a9ba924..bbd85cb47f81 100644 --- a/drivers/iio/adc/ti-ads8344.c +++ b/drivers/iio/adc/ti-ads8344.c @@ -28,7 +28,7 @@ struct ads8344 { */ struct mutex lock; - u8 tx_buf ____cacheline_aligned; + u8 tx_buf __aligned(IIO_DMA_MINALIGN); u8 rx_buf[3]; }; diff --git a/drivers/iio/adc/ti-ads8688.c b/drivers/iio/adc/ti-ads8688.c index 708cca0a63be..ef06a897421a 100644 --- a/drivers/iio/adc/ti-ads8688.c +++ b/drivers/iio/adc/ti-ads8688.c @@ -71,7 +71,7 @@ struct ads8688_state { union { __be32 d32; u8 d8[4]; - } data[2] ____cacheline_aligned; + } data[2] __aligned(IIO_DMA_MINALIGN); }; enum ads8688_id { diff --git a/drivers/iio/adc/ti-tlc4541.c b/drivers/iio/adc/ti-tlc4541.c index 2406eda9dfc6..30f629a553a1 100644 --- a/drivers/iio/adc/ti-tlc4541.c +++ b/drivers/iio/adc/ti-tlc4541.c @@ -37,12 +37,12 @@ struct tlc4541_state { struct spi_message scan_single_msg; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. * 2 bytes data + 6 bytes padding + 8 bytes timestamp when * call iio_push_to_buffers_with_timestamp. */ - __be16 rx_buf[8] ____cacheline_aligned; + __be16 rx_buf[8] __aligned(IIO_DMA_MINALIGN); }; struct tlc4541_chip_info { diff --git a/drivers/iio/adc/ti-tsc2046.c b/drivers/iio/adc/ti-tsc2046.c index 55b35570ad8b..0d9436a69cbf 100644 --- a/drivers/iio/adc/ti-tsc2046.c +++ b/drivers/iio/adc/ti-tsc2046.c @@ -776,7 +776,7 @@ static int tsc2046_adc_probe(struct spi_device *spi) priv->spi = spi; indio_dev->name = TI_TSC2046_NAME; - indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_TRIGGERED; + indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->channels = dcfg->channels; indio_dev->num_channels = dcfg->num_channels; indio_dev->info = &tsc2046_adc_info; diff --git a/drivers/iio/adc/ti_am335x_adc.c b/drivers/iio/adc/ti_am335x_adc.c index 567d43a30955..642c5c4895e3 100644 --- a/drivers/iio/adc/ti_am335x_adc.c +++ b/drivers/iio/adc/ti_am335x_adc.c @@ -702,7 +702,7 @@ static int tiadc_remove(struct platform_device *pdev) return 0; } -static int __maybe_unused tiadc_suspend(struct device *dev) +static int tiadc_suspend(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); struct tiadc_device *adc_dev = iio_priv(indio_dev); @@ -715,7 +715,7 @@ static int __maybe_unused tiadc_suspend(struct device *dev) return 0; } -static int __maybe_unused tiadc_resume(struct device *dev) +static int tiadc_resume(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); struct tiadc_device *adc_dev = iio_priv(indio_dev); @@ -732,7 +732,7 @@ static int __maybe_unused tiadc_resume(struct device *dev) return 0; } -static SIMPLE_DEV_PM_OPS(tiadc_pm_ops, tiadc_suspend, tiadc_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(tiadc_pm_ops, tiadc_suspend, tiadc_resume); static const struct of_device_id ti_adc_dt_ids[] = { { .compatible = "ti,am3359-adc", }, @@ -744,7 +744,7 @@ MODULE_DEVICE_TABLE(of, ti_adc_dt_ids); static struct platform_driver tiadc_driver = { .driver = { .name = "TI-am335x-adc", - .pm = &tiadc_pm_ops, + .pm = pm_sleep_ptr(&tiadc_pm_ops), .of_match_table = ti_adc_dt_ids, }, .probe = tiadc_probe, diff --git a/drivers/iio/adc/vf610_adc.c b/drivers/iio/adc/vf610_adc.c index c84293efc129..c6b16cf6e367 100644 --- a/drivers/iio/adc/vf610_adc.c +++ b/drivers/iio/adc/vf610_adc.c @@ -5,7 +5,9 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ +#include #include +#include #include #include #include @@ -14,10 +16,7 @@ #include #include #include -#include -#include #include -#include #include #include @@ -799,6 +798,7 @@ MODULE_DEVICE_TABLE(of, vf610_adc_match); static int vf610_adc_probe(struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct vf610_adc *info; struct iio_dev *indio_dev; int irq; @@ -846,13 +846,10 @@ static int vf610_adc_probe(struct platform_device *pdev) info->vref_uv = regulator_get_voltage(info->vref); - of_property_read_u32_array(pdev->dev.of_node, "fsl,adck-max-frequency", - info->max_adck_rate, 3); + device_property_read_u32_array(dev, "fsl,adck-max-frequency", info->max_adck_rate, 3); - ret = of_property_read_u32(pdev->dev.of_node, "min-sample-time", - &info->adc_feature.default_sample_time); - if (ret) - info->adc_feature.default_sample_time = DEFAULT_SAMPLE_TIME; + info->adc_feature.default_sample_time = DEFAULT_SAMPLE_TIME; + device_property_read_u32(dev, "min-sample-time", &info->adc_feature.default_sample_time); platform_set_drvdata(pdev, indio_dev); diff --git a/drivers/iio/adc/xilinx-ams.c b/drivers/iio/adc/xilinx-ams.c index a7687706012d..9cd2713146e5 100644 --- a/drivers/iio/adc/xilinx-ams.c +++ b/drivers/iio/adc/xilinx-ams.c @@ -1421,7 +1421,7 @@ static int ams_probe(struct platform_device *pdev) return devm_iio_device_register(&pdev->dev, indio_dev); } -static int __maybe_unused ams_suspend(struct device *dev) +static int ams_suspend(struct device *dev) { struct ams *ams = iio_priv(dev_get_drvdata(dev)); @@ -1430,20 +1430,20 @@ static int __maybe_unused ams_suspend(struct device *dev) return 0; } -static int __maybe_unused ams_resume(struct device *dev) +static int ams_resume(struct device *dev) { struct ams *ams = iio_priv(dev_get_drvdata(dev)); return clk_prepare_enable(ams->clk); } -static SIMPLE_DEV_PM_OPS(ams_pm_ops, ams_suspend, ams_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(ams_pm_ops, ams_suspend, ams_resume); static struct platform_driver ams_driver = { .probe = ams_probe, .driver = { .name = "xilinx-ams", - .pm = &ams_pm_ops, + .pm = pm_sleep_ptr(&ams_pm_ops), .of_match_table = ams_of_match_table, }, }; diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c index 823c8e5f9809..1b247722ba25 100644 --- a/drivers/iio/adc/xilinx-xadc-core.c +++ b/drivers/iio/adc/xilinx-xadc-core.c @@ -17,10 +17,11 @@ #include #include #include +#include #include -#include #include #include +#include #include #include @@ -1182,14 +1183,13 @@ static const struct of_device_id xadc_of_match_table[] = { }; MODULE_DEVICE_TABLE(of, xadc_of_match_table); -static int xadc_parse_dt(struct iio_dev *indio_dev, struct device_node *np, - unsigned int *conf, int irq) +static int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq) { struct device *dev = indio_dev->dev.parent; struct xadc *xadc = iio_priv(indio_dev); const struct iio_chan_spec *channel_templates; struct iio_chan_spec *channels, *chan; - struct device_node *chan_node, *child; + struct fwnode_handle *chan_node, *child; unsigned int max_channels; unsigned int num_channels; const char *external_mux; @@ -1200,7 +1200,7 @@ static int xadc_parse_dt(struct iio_dev *indio_dev, struct device_node *np, *conf = 0; - ret = of_property_read_string(np, "xlnx,external-mux", &external_mux); + ret = device_property_read_string(dev, "xlnx,external-mux", &external_mux); if (ret < 0 || strcasecmp(external_mux, "none") == 0) xadc->external_mux_mode = XADC_EXTERNAL_MUX_NONE; else if (strcasecmp(external_mux, "single") == 0) @@ -1211,8 +1211,7 @@ static int xadc_parse_dt(struct iio_dev *indio_dev, struct device_node *np, return -EINVAL; if (xadc->external_mux_mode != XADC_EXTERNAL_MUX_NONE) { - ret = of_property_read_u32(np, "xlnx,external-mux-channel", - &ext_mux_chan); + ret = device_property_read_u32(dev, "xlnx,external-mux-channel", &ext_mux_chan); if (ret < 0) return ret; @@ -1247,33 +1246,31 @@ static int xadc_parse_dt(struct iio_dev *indio_dev, struct device_node *np, num_channels = 9; chan = &channels[9]; - chan_node = of_get_child_by_name(np, "xlnx,channels"); - if (chan_node) { - for_each_child_of_node(chan_node, child) { - if (num_channels >= max_channels) { - of_node_put(child); - break; - } - - ret = of_property_read_u32(child, "reg", ®); - if (ret || reg > 16) - continue; - - if (of_property_read_bool(child, "xlnx,bipolar")) - chan->scan_type.sign = 's'; - - if (reg == 0) { - chan->scan_index = 11; - chan->address = XADC_REG_VPVN; - } else { - chan->scan_index = 15 + reg; - chan->address = XADC_REG_VAUX(reg - 1); - } - num_channels++; - chan++; + chan_node = device_get_named_child_node(dev, "xlnx,channels"); + fwnode_for_each_child_node(chan_node, child) { + if (num_channels >= max_channels) { + fwnode_handle_put(child); + break; } + + ret = fwnode_property_read_u32(child, "reg", ®); + if (ret || reg > 16) + continue; + + if (fwnode_property_read_bool(child, "xlnx,bipolar")) + chan->scan_type.sign = 's'; + + if (reg == 0) { + chan->scan_index = 11; + chan->address = XADC_REG_VPVN; + } else { + chan->scan_index = 15 + reg; + chan->address = XADC_REG_VAUX(reg - 1); + } + num_channels++; + chan++; } - of_node_put(chan_node); + fwnode_handle_put(chan_node); /* No IRQ => no events */ if (irq <= 0) { @@ -1316,7 +1313,6 @@ static void xadc_cancel_delayed_work(void *data) static int xadc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - const struct of_device_id *id; const struct xadc_ops *ops; struct iio_dev *indio_dev; unsigned int bipolar_mask; @@ -1326,15 +1322,10 @@ static int xadc_probe(struct platform_device *pdev) int irq; int i; - if (!dev->of_node) - return -ENODEV; - - id = of_match_node(xadc_of_match_table, dev->of_node); - if (!id) + ops = device_get_match_data(dev); + if (!ops) return -EINVAL; - ops = id->data; - irq = platform_get_irq_optional(pdev, 0); if (irq < 0 && (irq != -ENXIO || !(ops->flags & XADC_FLAGS_IRQ_OPTIONAL))) @@ -1345,7 +1336,7 @@ static int xadc_probe(struct platform_device *pdev) return -ENOMEM; xadc = iio_priv(indio_dev); - xadc->ops = id->data; + xadc->ops = ops; init_completion(&xadc->completion); mutex_init(&xadc->mutex); spin_lock_init(&xadc->lock); @@ -1359,7 +1350,7 @@ static int xadc_probe(struct platform_device *pdev) indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->info = &xadc_info; - ret = xadc_parse_dt(indio_dev, dev->of_node, &conf0, irq); + ret = xadc_parse_dt(indio_dev, &conf0, irq); if (ret) return ret; diff --git a/drivers/iio/addac/ad74413r.c b/drivers/iio/addac/ad74413r.c index acd230a6af35..899bcd83f40b 100644 --- a/drivers/iio/addac/ad74413r.c +++ b/drivers/iio/addac/ad74413r.c @@ -77,13 +77,13 @@ struct ad74413r_state { struct spi_transfer adc_samples_xfer[AD74413R_CHANNEL_MAX + 1]; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ struct { u8 rx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX]; s64 timestamp; - } adc_samples_buf ____cacheline_aligned; + } adc_samples_buf __aligned(IIO_DMA_MINALIGN); u8 adc_samples_tx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX]; u8 reg_tx_buf[AD74413R_FRAME_SIZE]; @@ -284,10 +284,10 @@ static void ad74413r_gpio_set_multiple(struct gpio_chip *chip, struct ad74413r_state *st = gpiochip_get_data(chip); unsigned long real_mask = 0; unsigned long real_bits = 0; - unsigned int offset = 0; + unsigned int offset; int ret; - for_each_set_bit_from(offset, mask, chip->ngpio) { + for_each_set_bit(offset, mask, chip->ngpio) { unsigned int real_offset = st->gpo_gpio_offsets[offset]; ret = ad74413r_set_gpo_config(st, real_offset, @@ -325,7 +325,7 @@ static int ad74413r_gpio_get_multiple(struct gpio_chip *chip, unsigned long *bits) { struct ad74413r_state *st = gpiochip_get_data(chip); - unsigned int offset = 0; + unsigned int offset; unsigned int val; int ret; @@ -333,7 +333,7 @@ static int ad74413r_gpio_get_multiple(struct gpio_chip *chip, if (ret) return ret; - for_each_set_bit_from(offset, mask, chip->ngpio) { + for_each_set_bit(offset, mask, chip->ngpio) { unsigned int real_offset = st->comp_gpio_offsets[offset]; __assign_bit(offset, bits, val & BIT(real_offset)); diff --git a/drivers/iio/afe/iio-rescale.c b/drivers/iio/afe/iio-rescale.c index 6949d2151025..1f280c360701 100644 --- a/drivers/iio/afe/iio-rescale.c +++ b/drivers/iio/afe/iio-rescale.c @@ -107,6 +107,7 @@ int rescale_process_scale(struct rescale *rescale, int scale_type, return -EOPNOTSUPP; } } +EXPORT_SYMBOL_NS_GPL(rescale_process_scale, IIO_RESCALE); int rescale_process_offset(struct rescale *rescale, int scale_type, int scale, int scale2, int schan_off, @@ -140,6 +141,7 @@ int rescale_process_offset(struct rescale *rescale, int scale_type, return -EOPNOTSUPP; } } +EXPORT_SYMBOL_NS_GPL(rescale_process_offset, IIO_RESCALE); static int rescale_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, diff --git a/drivers/iio/amplifiers/ad8366.c b/drivers/iio/amplifiers/ad8366.c index 1134ae12e531..f2c2ea79a07f 100644 --- a/drivers/iio/amplifiers/ad8366.c +++ b/drivers/iio/amplifiers/ad8366.c @@ -45,10 +45,10 @@ struct ad8366_state { enum ad8366_type type; struct ad8366_info *info; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ - unsigned char data[2] ____cacheline_aligned; + unsigned char data[2] __aligned(IIO_DMA_MINALIGN); }; static struct ad8366_info ad8366_infos[] = { diff --git a/drivers/iio/chemical/atlas-sensor.c b/drivers/iio/chemical/atlas-sensor.c index 56dea9734c8d..8378c00fa2ff 100644 --- a/drivers/iio/chemical/atlas-sensor.c +++ b/drivers/iio/chemical/atlas-sensor.c @@ -726,6 +726,7 @@ static int atlas_remove(struct i2c_client *client) { struct iio_dev *indio_dev = i2c_get_clientdata(client); struct atlas_data *data = iio_priv(indio_dev); + int ret; iio_device_unregister(indio_dev); iio_triggered_buffer_cleanup(indio_dev); @@ -734,7 +735,12 @@ static int atlas_remove(struct i2c_client *client) pm_runtime_disable(&client->dev); pm_runtime_set_suspended(&client->dev); - return atlas_set_powermode(data, 0); + ret = atlas_set_powermode(data, 0); + if (ret) + dev_err(&client->dev, "Failed to power down device (%pe)\n", + ERR_PTR(ret)); + + return 0; } static int atlas_runtime_suspend(struct device *dev) diff --git a/drivers/iio/chemical/bme680_core.c b/drivers/iio/chemical/bme680_core.c index 16ff7a98c9f0..ef5e0e46fd34 100644 --- a/drivers/iio/chemical/bme680_core.c +++ b/drivers/iio/chemical/bme680_core.c @@ -638,7 +638,7 @@ static int bme680_read_temp(struct bme680_data *data, int *val) comp_temp = bme680_compensate_temp(data, adc_temp); /* * val might be NULL if we're called by the read_press/read_humid - * routine which is callled to get t_fine value used in + * routine which is called to get t_fine value used in * compensate_press/compensate_humid to get compensated * pressure/humidity readings. */ diff --git a/drivers/iio/chemical/ccs811.c b/drivers/iio/chemical/ccs811.c index 80ef1aa9aae3..560183efb36f 100644 --- a/drivers/iio/chemical/ccs811.c +++ b/drivers/iio/chemical/ccs811.c @@ -536,14 +536,20 @@ static int ccs811_remove(struct i2c_client *client) { struct iio_dev *indio_dev = i2c_get_clientdata(client); struct ccs811_data *data = iio_priv(indio_dev); + int ret; iio_device_unregister(indio_dev); iio_triggered_buffer_cleanup(indio_dev); if (data->drdy_trig) iio_trigger_unregister(data->drdy_trig); - return i2c_smbus_write_byte_data(client, CCS811_MEAS_MODE, - CCS811_MODE_IDLE); + ret = i2c_smbus_write_byte_data(client, CCS811_MEAS_MODE, + CCS811_MODE_IDLE); + if (ret) + dev_warn(&client->dev, "Failed to power down device (%pe)\n", + ERR_PTR(ret)); + + return 0; } static const struct i2c_device_id ccs811_id[] = { diff --git a/drivers/iio/chemical/scd4x.c b/drivers/iio/chemical/scd4x.c index 37143b5526ee..54066532ea45 100644 --- a/drivers/iio/chemical/scd4x.c +++ b/drivers/iio/chemical/scd4x.c @@ -551,7 +551,7 @@ static const struct iio_chan_spec scd4x_channels[] = { }, }; -static int __maybe_unused scd4x_suspend(struct device *dev) +static int scd4x_suspend(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); struct scd4x_state *state = iio_priv(indio_dev); @@ -564,7 +564,7 @@ static int __maybe_unused scd4x_suspend(struct device *dev) return regulator_disable(state->vdd); } -static int __maybe_unused scd4x_resume(struct device *dev) +static int scd4x_resume(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); struct scd4x_state *state = iio_priv(indio_dev); @@ -577,7 +577,7 @@ static int __maybe_unused scd4x_resume(struct device *dev) return scd4x_send_command(state, CMD_START_MEAS); } -static __maybe_unused SIMPLE_DEV_PM_OPS(scd4x_pm_ops, scd4x_suspend, scd4x_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(scd4x_pm_ops, scd4x_suspend, scd4x_resume); static void scd4x_stop_meas(void *state) { @@ -688,7 +688,7 @@ static struct i2c_driver scd4x_i2c_driver = { .driver = { .name = KBUILD_MODNAME, .of_match_table = scd4x_dt_ids, - .pm = &scd4x_pm_ops + .pm = pm_sleep_ptr(&scd4x_pm_ops), }, .probe = scd4x_probe, }; diff --git a/drivers/iio/chemical/sps30.c b/drivers/iio/chemical/sps30.c index abd67559e451..814ce0aad1cc 100644 --- a/drivers/iio/chemical/sps30.c +++ b/drivers/iio/chemical/sps30.c @@ -372,7 +372,7 @@ int sps30_probe(struct device *dev, const char *name, void *priv, const struct s return devm_iio_device_register(dev, indio_dev); } -EXPORT_SYMBOL_GPL(sps30_probe); +EXPORT_SYMBOL_NS_GPL(sps30_probe, IIO_SPS30); MODULE_AUTHOR("Tomasz Duszynski "); MODULE_DESCRIPTION("Sensirion SPS30 particulate matter sensor driver"); diff --git a/drivers/iio/chemical/sps30_i2c.c b/drivers/iio/chemical/sps30_i2c.c index d33560ed7184..2aed483a2fde 100644 --- a/drivers/iio/chemical/sps30_i2c.c +++ b/drivers/iio/chemical/sps30_i2c.c @@ -256,3 +256,4 @@ module_i2c_driver(sps30_i2c_driver); MODULE_AUTHOR("Tomasz Duszynski "); MODULE_DESCRIPTION("Sensirion SPS30 particulate matter sensor i2c driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(IIO_SPS30); diff --git a/drivers/iio/chemical/sps30_serial.c b/drivers/iio/chemical/sps30_serial.c index 3f311d50087c..164f4b3e025c 100644 --- a/drivers/iio/chemical/sps30_serial.c +++ b/drivers/iio/chemical/sps30_serial.c @@ -429,3 +429,4 @@ module_serdev_device_driver(sps30_serial_driver); MODULE_AUTHOR("Tomasz Duszynski "); MODULE_DESCRIPTION("Sensirion SPS30 particulate matter sensor serial driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(IIO_SPS30); diff --git a/drivers/iio/common/cros_ec_sensors/cros_ec_lid_angle.c b/drivers/iio/common/cros_ec_sensors/cros_ec_lid_angle.c index af801e203623..119acb078af3 100644 --- a/drivers/iio/common/cros_ec_sensors/cros_ec_lid_angle.c +++ b/drivers/iio/common/cros_ec_sensors/cros_ec_lid_angle.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -97,7 +98,7 @@ static int cros_ec_lid_angle_probe(struct platform_device *pdev) if (!indio_dev) return -ENOMEM; - ret = cros_ec_sensors_core_init(pdev, indio_dev, false, NULL, NULL); + ret = cros_ec_sensors_core_init(pdev, indio_dev, false, NULL); if (ret) return ret; @@ -113,7 +114,7 @@ static int cros_ec_lid_angle_probe(struct platform_device *pdev) if (ret) return ret; - return devm_iio_device_register(dev, indio_dev); + return cros_ec_sensors_core_register(dev, indio_dev, NULL); } static const struct platform_device_id cros_ec_lid_angle_ids[] = { diff --git a/drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c b/drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c index 376a5b30010a..66153b1850f1 100644 --- a/drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c +++ b/drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -235,8 +236,7 @@ static int cros_ec_sensors_probe(struct platform_device *pdev) return -ENOMEM; ret = cros_ec_sensors_core_init(pdev, indio_dev, true, - cros_ec_sensors_capture, - cros_ec_sensors_push_data); + cros_ec_sensors_capture); if (ret) return ret; @@ -297,7 +297,8 @@ static int cros_ec_sensors_probe(struct platform_device *pdev) else state->core.read_ec_sensors_data = cros_ec_sensors_read_cmd; - return devm_iio_device_register(dev, indio_dev); + return cros_ec_sensors_core_register(dev, indio_dev, + cros_ec_sensors_push_data); } static const struct platform_device_id cros_ec_sensors_ids[] = { diff --git a/drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c b/drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c index 5976aca48e3b..05a28d353e34 100644 --- a/drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c +++ b/drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c @@ -29,12 +29,6 @@ */ #define CROS_EC_FIFO_SIZE (2048 * 2 / 3) -static char *cros_ec_loc[] = { - [MOTIONSENSE_LOC_BASE] = "base", - [MOTIONSENSE_LOC_LID] = "lid", - [MOTIONSENSE_LOC_MAX] = "unknown", -}; - static int cros_ec_get_host_cmd_version_mask(struct cros_ec_device *ec_dev, u16 cmd_offset, u16 cmd, u32 *mask) { @@ -234,21 +228,18 @@ static void cros_ec_sensors_core_clean(void *arg) /** * cros_ec_sensors_core_init() - basic initialization of the core structure - * @pdev: platform device created for the sensors + * @pdev: platform device created for the sensor * @indio_dev: iio device structure of the device * @physical_device: true if the device refers to a physical device * @trigger_capture: function pointer to call buffer is triggered, * for backward compatibility. - * @push_data: function to call when cros_ec_sensorhub receives - * a sample for that sensor. * * Return: 0 on success, -errno on failure. */ int cros_ec_sensors_core_init(struct platform_device *pdev, struct iio_dev *indio_dev, bool physical_device, - cros_ec_sensors_capture_t trigger_capture, - cros_ec_sensorhub_push_data_cb_t push_data) + cros_ec_sensors_capture_t trigger_capture) { struct device *dev = &pdev->dev; struct cros_ec_sensors_core_state *state = iio_priv(indio_dev); @@ -287,6 +278,8 @@ int cros_ec_sensors_core_init(struct platform_device *pdev, indio_dev->name = pdev->name; if (physical_device) { + enum motionsensor_location loc; + state->param.cmd = MOTIONSENSE_CMD_INFO; state->param.info.sensor_num = sensor_platform->sensor_num; ret = cros_ec_motion_send_host_cmd(state, 0); @@ -295,7 +288,13 @@ int cros_ec_sensors_core_init(struct platform_device *pdev, return ret; } state->type = state->resp->info.type; - state->loc = state->resp->info.location; + loc = state->resp->info.location; + if (loc == MOTIONSENSE_LOC_BASE) + indio_dev->label = "accel-base"; + else if (loc == MOTIONSENSE_LOC_LID) + indio_dev->label = "accel-display"; + else if (loc == MOTIONSENSE_LOC_CAMERA) + indio_dev->label = "accel-camera"; /* Set sign vector, only used for backward compatibility. */ memset(state->sign, 1, CROS_EC_SENSOR_MAX_AXIS); @@ -338,17 +337,6 @@ int cros_ec_sensors_core_init(struct platform_device *pdev, if (ret) return ret; - ret = cros_ec_sensorhub_register_push_data( - sensor_hub, sensor_platform->sensor_num, - indio_dev, push_data); - if (ret) - return ret; - - ret = devm_add_action_or_reset( - dev, cros_ec_sensors_core_clean, pdev); - if (ret) - return ret; - /* Timestamp coming from FIFO are in ns since boot. */ ret = iio_device_set_clock(indio_dev, CLOCK_BOOTTIME); if (ret) @@ -370,6 +358,46 @@ int cros_ec_sensors_core_init(struct platform_device *pdev, } EXPORT_SYMBOL_GPL(cros_ec_sensors_core_init); +/** + * cros_ec_sensors_core_register() - Register callback to FIFO and IIO when + * sensor is ready. + * It must be called at the end of the sensor probe routine. + * @dev: device created for the sensor + * @indio_dev: iio device structure of the device + * @push_data: function to call when cros_ec_sensorhub receives + * a sample for that sensor. + * + * Return: 0 on success, -errno on failure. + */ +int cros_ec_sensors_core_register(struct device *dev, + struct iio_dev *indio_dev, + cros_ec_sensorhub_push_data_cb_t push_data) +{ + struct cros_ec_sensor_platform *sensor_platform = dev_get_platdata(dev); + struct cros_ec_sensorhub *sensor_hub = dev_get_drvdata(dev->parent); + struct platform_device *pdev = to_platform_device(dev); + struct cros_ec_dev *ec = sensor_hub->ec; + int ret; + + ret = devm_iio_device_register(dev, indio_dev); + if (ret) + return ret; + + if (!push_data || + !cros_ec_check_features(ec, EC_FEATURE_MOTION_SENSE_FIFO)) + return 0; + + ret = cros_ec_sensorhub_register_push_data( + sensor_hub, sensor_platform->sensor_num, + indio_dev, push_data); + if (ret) + return ret; + + return devm_add_action_or_reset( + dev, cros_ec_sensors_core_clean, pdev); +} +EXPORT_SYMBOL_GPL(cros_ec_sensors_core_register); + /** * cros_ec_motion_send_host_cmd() - send motion sense host command * @state: pointer to state information for device @@ -442,15 +470,6 @@ static ssize_t cros_ec_sensors_id(struct iio_dev *indio_dev, return snprintf(buf, PAGE_SIZE, "%d\n", st->param.info.sensor_num); } -static ssize_t cros_ec_sensors_loc(struct iio_dev *indio_dev, - uintptr_t private, const struct iio_chan_spec *chan, - char *buf) -{ - struct cros_ec_sensors_core_state *st = iio_priv(indio_dev); - - return snprintf(buf, PAGE_SIZE, "%s\n", cros_ec_loc[st->loc]); -} - const struct iio_chan_spec_ext_info cros_ec_sensors_ext_info[] = { { .name = "calibrate", @@ -462,11 +481,6 @@ const struct iio_chan_spec_ext_info cros_ec_sensors_ext_info[] = { .shared = IIO_SHARED_BY_ALL, .read = cros_ec_sensors_id }, - { - .name = "location", - .shared = IIO_SHARED_BY_ALL, - .read = cros_ec_sensors_loc - }, { }, }; EXPORT_SYMBOL_GPL(cros_ec_sensors_ext_info); diff --git a/drivers/iio/common/ssp_sensors/ssp.h b/drivers/iio/common/ssp_sensors/ssp.h index abb832795619..f649cdecc277 100644 --- a/drivers/iio/common/ssp_sensors/ssp.h +++ b/drivers/iio/common/ssp_sensors/ssp.h @@ -221,8 +221,7 @@ struct ssp_data { struct iio_dev *sensor_devs[SSP_SENSOR_MAX]; atomic_t enable_refcount; - __le16 header_buffer[SSP_HEADER_BUFFER_SIZE / sizeof(__le16)] - ____cacheline_aligned; + __le16 header_buffer[SSP_HEADER_BUFFER_SIZE / sizeof(__le16)] __aligned(IIO_DMA_MINALIGN); }; void ssp_clean_pending_list(struct ssp_data *data); diff --git a/drivers/iio/dac/Kconfig b/drivers/iio/dac/Kconfig index d1c7bde8aece..80521bd28d0f 100644 --- a/drivers/iio/dac/Kconfig +++ b/drivers/iio/dac/Kconfig @@ -416,7 +416,7 @@ config TI_DAC5571 help Driver for the Texas Instruments DAC5571, DAC6571, DAC7571, DAC5574, DAC6574, DAC7574, DAC5573, - DAC6573, DAC7573, DAC8571, DAC8574. + DAC6573, DAC7573, DAC8571, DAC8574, DAC121C081. If compiled as a module, it will be called ti-dac5571. diff --git a/drivers/iio/dac/ad5064.c b/drivers/iio/dac/ad5064.c index d87cf14daabe..4447b8811827 100644 --- a/drivers/iio/dac/ad5064.c +++ b/drivers/iio/dac/ad5064.c @@ -115,13 +115,13 @@ struct ad5064_state { struct mutex lock; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ union { u8 i2c[3]; __be32 spi; - } data ____cacheline_aligned; + } data __aligned(IIO_DMA_MINALIGN); }; enum ad5064_type { diff --git a/drivers/iio/dac/ad5360.c b/drivers/iio/dac/ad5360.c index 22b000a40828..e0b7f658d611 100644 --- a/drivers/iio/dac/ad5360.c +++ b/drivers/iio/dac/ad5360.c @@ -79,13 +79,13 @@ struct ad5360_state { struct mutex lock; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ union { __be32 d32; u8 d8[4]; - } data[2] ____cacheline_aligned; + } data[2] __aligned(IIO_DMA_MINALIGN); }; enum ad5360_type { diff --git a/drivers/iio/dac/ad5380.c b/drivers/iio/dac/ad5380.c index a44c83242fb1..81775152aac6 100644 --- a/drivers/iio/dac/ad5380.c +++ b/drivers/iio/dac/ad5380.c @@ -36,8 +36,7 @@ * @channel_template: channel specification template * @num_channels: number of channels * @int_vref: internal vref in uV -*/ - + */ struct ad5380_chip_info { struct iio_chan_spec channel_template; unsigned int num_channels; @@ -53,7 +52,6 @@ struct ad5380_chip_info { * @pwr_down: whether the chip is currently in power down mode * @lock: lock to protect the data buffer during regmap ops */ - struct ad5380_state { struct regmap *regmap; const struct ad5380_chip_info *chip_info; diff --git a/drivers/iio/dac/ad5421.c b/drivers/iio/dac/ad5421.c index eedf661d32b2..7644acfd879e 100644 --- a/drivers/iio/dac/ad5421.c +++ b/drivers/iio/dac/ad5421.c @@ -72,13 +72,13 @@ struct ad5421_state { struct mutex lock; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ union { __be32 d32; u8 d8[4]; - } data[2] ____cacheline_aligned; + } data[2] __aligned(IIO_DMA_MINALIGN); }; static const struct iio_event_spec ad5421_current_event[] = { diff --git a/drivers/iio/dac/ad5449.c b/drivers/iio/dac/ad5449.c index bad9bdaafa94..4572d6f49275 100644 --- a/drivers/iio/dac/ad5449.c +++ b/drivers/iio/dac/ad5449.c @@ -68,10 +68,10 @@ struct ad5449 { uint16_t dac_cache[AD5449_MAX_CHANNELS]; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ - __be16 data[2] ____cacheline_aligned; + __be16 data[2] __aligned(IIO_DMA_MINALIGN); }; enum ad5449_type { diff --git a/drivers/iio/dac/ad5504.c b/drivers/iio/dac/ad5504.c index a0817e799cc0..e6c5be728bb2 100644 --- a/drivers/iio/dac/ad5504.c +++ b/drivers/iio/dac/ad5504.c @@ -54,7 +54,7 @@ struct ad5504_state { unsigned pwr_down_mask; unsigned pwr_down_mode; - __be16 data[2] ____cacheline_aligned; + __be16 data[2] __aligned(IIO_DMA_MINALIGN); }; /* diff --git a/drivers/iio/dac/ad5592r-base.c b/drivers/iio/dac/ad5592r-base.c index 4434c1b2a322..7a9b5fc1e579 100644 --- a/drivers/iio/dac/ad5592r-base.c +++ b/drivers/iio/dac/ad5592r-base.c @@ -603,7 +603,7 @@ int ad5592r_probe(struct device *dev, const char *name, st->reg = devm_regulator_get_optional(dev, "vref"); if (IS_ERR(st->reg)) { - if ((PTR_ERR(st->reg) != -ENODEV) && dev->of_node) + if ((PTR_ERR(st->reg) != -ENODEV) && dev_fwnode(dev)) return PTR_ERR(st->reg); st->reg = NULL; diff --git a/drivers/iio/dac/ad5592r-base.h b/drivers/iio/dac/ad5592r-base.h index 2a22ef691996..cc7be426cbc8 100644 --- a/drivers/iio/dac/ad5592r-base.h +++ b/drivers/iio/dac/ad5592r-base.h @@ -14,6 +14,8 @@ #include #include +#include + struct device; struct ad5592r_state; @@ -65,7 +67,7 @@ struct ad5592r_state { u8 gpio_in; u8 gpio_val; - __be16 spi_msg ____cacheline_aligned; + __be16 spi_msg __aligned(IIO_DMA_MINALIGN); __be16 spi_msg_nop; }; diff --git a/drivers/iio/dac/ad5686.h b/drivers/iio/dac/ad5686.h index cd5fff9e9d53..b7ade3a6b9b6 100644 --- a/drivers/iio/dac/ad5686.h +++ b/drivers/iio/dac/ad5686.h @@ -13,6 +13,8 @@ #include #include +#include + #define AD5310_CMD(x) ((x) << 12) #define AD5683_DATA(x) ((x) << 4) @@ -137,7 +139,7 @@ struct ad5686_state { struct mutex lock; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ @@ -145,7 +147,7 @@ struct ad5686_state { __be32 d32; __be16 d16; u8 d8[4]; - } data[3] ____cacheline_aligned; + } data[3] __aligned(IIO_DMA_MINALIGN); }; diff --git a/drivers/iio/dac/ad5755.c b/drivers/iio/dac/ad5755.c index 1a63b8456725..beadfa938d2d 100644 --- a/drivers/iio/dac/ad5755.c +++ b/drivers/iio/dac/ad5755.c @@ -189,14 +189,14 @@ struct ad5755_state { struct mutex lock; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ union { __be32 d32; u8 d8[4]; - } data[2] ____cacheline_aligned; + } data[2] __aligned(IIO_DMA_MINALIGN); }; enum ad5755_type { diff --git a/drivers/iio/dac/ad5761.c b/drivers/iio/dac/ad5761.c index 4cb8471db81e..6aa1a068adb0 100644 --- a/drivers/iio/dac/ad5761.c +++ b/drivers/iio/dac/ad5761.c @@ -70,13 +70,13 @@ struct ad5761_state { enum ad5761_voltage_range range; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ union { __be32 d32; u8 d8[4]; - } data[3] ____cacheline_aligned; + } data[3] __aligned(IIO_DMA_MINALIGN); }; static const struct ad5761_range_params ad5761_range_params[] = { diff --git a/drivers/iio/dac/ad5764.c b/drivers/iio/dac/ad5764.c index d235a8047ba0..26c049d5b73a 100644 --- a/drivers/iio/dac/ad5764.c +++ b/drivers/iio/dac/ad5764.c @@ -56,13 +56,13 @@ struct ad5764_state { struct mutex lock; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ union { __be32 d32; u8 d8[4]; - } data[2] ____cacheline_aligned; + } data[2] __aligned(IIO_DMA_MINALIGN); }; enum ad5764_type { diff --git a/drivers/iio/dac/ad5766.c b/drivers/iio/dac/ad5766.c index 43189af2fb1f..899894523752 100644 --- a/drivers/iio/dac/ad5766.c +++ b/drivers/iio/dac/ad5766.c @@ -123,7 +123,7 @@ struct ad5766_state { u32 d32; u16 w16[2]; u8 b8[4]; - } data[3] ____cacheline_aligned; + } data[3] __aligned(IIO_DMA_MINALIGN); }; struct ad5766_span_tbl { diff --git a/drivers/iio/dac/ad5770r.c b/drivers/iio/dac/ad5770r.c index 7e2fd32e993a..f66d67402e43 100644 --- a/drivers/iio/dac/ad5770r.c +++ b/drivers/iio/dac/ad5770r.c @@ -140,7 +140,7 @@ struct ad5770r_state { bool ch_pwr_down[AD5770R_MAX_CHANNELS]; bool internal_ref; bool external_res; - u8 transf_buf[2] ____cacheline_aligned; + u8 transf_buf[2] __aligned(IIO_DMA_MINALIGN); }; static const struct regmap_config ad5770r_spi_regmap_config = { diff --git a/drivers/iio/dac/ad5791.c b/drivers/iio/dac/ad5791.c index 339564fe47d1..a4167454da81 100644 --- a/drivers/iio/dac/ad5791.c +++ b/drivers/iio/dac/ad5791.c @@ -95,7 +95,7 @@ struct ad5791_state { union { __be32 d32; u8 d8[4]; - } data[3] ____cacheline_aligned; + } data[3] __aligned(IIO_DMA_MINALIGN); }; enum ad5791_supported_device_ids { diff --git a/drivers/iio/dac/ad7293.c b/drivers/iio/dac/ad7293.c index 59a38ca4c3c7..06f05750d921 100644 --- a/drivers/iio/dac/ad7293.c +++ b/drivers/iio/dac/ad7293.c @@ -144,7 +144,7 @@ struct ad7293_state { struct regulator *reg_avdd; struct regulator *reg_vdrive; u8 page_select; - u8 data[3] ____cacheline_aligned; + u8 data[3] __aligned(IIO_DMA_MINALIGN); }; static int ad7293_page_select(struct ad7293_state *st, unsigned int reg) diff --git a/drivers/iio/dac/ad7303.c b/drivers/iio/dac/ad7303.c index 03edf046dec6..bff6bf697d9c 100644 --- a/drivers/iio/dac/ad7303.c +++ b/drivers/iio/dac/ad7303.c @@ -44,10 +44,10 @@ struct ad7303_state { struct mutex lock; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ - __be16 data ____cacheline_aligned; + __be16 data __aligned(IIO_DMA_MINALIGN); }; static int ad7303_write(struct ad7303_state *st, unsigned int chan, diff --git a/drivers/iio/dac/ad8801.c b/drivers/iio/dac/ad8801.c index 6be35c92d435..919e8c880697 100644 --- a/drivers/iio/dac/ad8801.c +++ b/drivers/iio/dac/ad8801.c @@ -26,7 +26,7 @@ struct ad8801_state { struct regulator *vrefh_reg; struct regulator *vrefl_reg; - __be16 data ____cacheline_aligned; + __be16 data __aligned(IIO_DMA_MINALIGN); }; static int ad8801_spi_write(struct ad8801_state *state, diff --git a/drivers/iio/dac/cio-dac.c b/drivers/iio/dac/cio-dac.c index 95813569f394..791dd999cf29 100644 --- a/drivers/iio/dac/cio-dac.c +++ b/drivers/iio/dac/cio-dac.c @@ -16,6 +16,7 @@ #include #include #include +#include #define CIO_DAC_NUM_CHAN 16 @@ -37,11 +38,11 @@ MODULE_PARM_DESC(base, "Measurement Computing CIO-DAC base addresses"); /** * struct cio_dac_iio - IIO device private data structure * @chan_out_states: channels' output states - * @base: base port address of the IIO device + * @base: base memory address of the DAC device */ struct cio_dac_iio { int chan_out_states[CIO_DAC_NUM_CHAN]; - unsigned int base; + u16 __iomem *base; }; static int cio_dac_read_raw(struct iio_dev *indio_dev, @@ -61,7 +62,6 @@ static int cio_dac_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) { struct cio_dac_iio *const priv = iio_priv(indio_dev); - const unsigned int chan_addr_offset = 2 * chan->channel; if (mask != IIO_CHAN_INFO_RAW) return -EINVAL; @@ -71,7 +71,7 @@ static int cio_dac_write_raw(struct iio_dev *indio_dev, return -EINVAL; priv->chan_out_states[chan->channel] = val; - outw(val, priv->base + chan_addr_offset); + iowrite16(val, priv->base + chan->channel); return 0; } @@ -105,18 +105,20 @@ static int cio_dac_probe(struct device *dev, unsigned int id) return -EBUSY; } + priv = iio_priv(indio_dev); + priv->base = devm_ioport_map(dev, base[id], CIO_DAC_EXTENT); + if (!priv->base) + return -ENOMEM; + indio_dev->info = &cio_dac_info; indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->channels = cio_dac_channels; indio_dev->num_channels = CIO_DAC_NUM_CHAN; indio_dev->name = dev_name(dev); - priv = iio_priv(indio_dev); - priv->base = base[id]; - /* initialize DAC outputs to 0V */ - for (i = 0; i < 32; i += 2) - outw(0, base[id] + i); + for (i = 0; i < CIO_DAC_NUM_CHAN; i++) + iowrite16(0, priv->base + i); return devm_iio_device_register(dev, indio_dev); } diff --git a/drivers/iio/dac/ds4424.c b/drivers/iio/dac/ds4424.c index 5a5e967b0be4..509394690bcc 100644 --- a/drivers/iio/dac/ds4424.c +++ b/drivers/iio/dac/ds4424.c @@ -171,7 +171,7 @@ static int ds4424_verify_chip(struct iio_dev *indio_dev) return ret; } -static int __maybe_unused ds4424_suspend(struct device *dev) +static int ds4424_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct iio_dev *indio_dev = i2c_get_clientdata(client); @@ -189,7 +189,7 @@ static int __maybe_unused ds4424_suspend(struct device *dev) return ret; } -static int __maybe_unused ds4424_resume(struct device *dev) +static int ds4424_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct iio_dev *indio_dev = i2c_get_clientdata(client); @@ -206,7 +206,7 @@ static int __maybe_unused ds4424_resume(struct device *dev) return ret; } -static SIMPLE_DEV_PM_OPS(ds4424_pm_ops, ds4424_suspend, ds4424_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(ds4424_pm_ops, ds4424_suspend, ds4424_resume); static const struct iio_info ds4424_info = { .read_raw = ds4424_read_raw, @@ -312,7 +312,7 @@ static struct i2c_driver ds4424_driver = { .driver = { .name = "ds4424", .of_match_table = ds4424_of_match, - .pm = &ds4424_pm_ops, + .pm = pm_sleep_ptr(&ds4424_pm_ops), }, .probe = ds4424_probe, .remove = ds4424_remove, diff --git a/drivers/iio/dac/ltc1660.c b/drivers/iio/dac/ltc1660.c index c76233c9bb72..2758fc8a5ad5 100644 --- a/drivers/iio/dac/ltc1660.c +++ b/drivers/iio/dac/ltc1660.c @@ -137,20 +137,21 @@ static const struct iio_info ltc1660_info = { .write_raw = <c1660_write_raw, }; -static int __maybe_unused ltc1660_suspend(struct device *dev) +static int ltc1660_suspend(struct device *dev) { struct ltc1660_priv *priv = iio_priv(spi_get_drvdata( to_spi_device(dev))); return regmap_write(priv->regmap, LTC1660_REG_SLEEP, 0x00); } -static int __maybe_unused ltc1660_resume(struct device *dev) +static int ltc1660_resume(struct device *dev) { struct ltc1660_priv *priv = iio_priv(spi_get_drvdata( to_spi_device(dev))); return regmap_write(priv->regmap, LTC1660_REG_WAKE, 0x00); } -static SIMPLE_DEV_PM_OPS(ltc1660_pm_ops, ltc1660_suspend, ltc1660_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(ltc1660_pm_ops, ltc1660_suspend, + ltc1660_resume); static int ltc1660_probe(struct spi_device *spi) { @@ -233,7 +234,7 @@ static struct spi_driver ltc1660_driver = { .driver = { .name = "ltc1660", .of_match_table = ltc1660_dt_ids, - .pm = <c1660_pm_ops, + .pm = pm_sleep_ptr(<c1660_pm_ops), }, .probe = ltc1660_probe, .remove = ltc1660_remove, diff --git a/drivers/iio/dac/ltc2688.c b/drivers/iio/dac/ltc2688.c index 937b0d25a11c..28bdde2d3088 100644 --- a/drivers/iio/dac/ltc2688.c +++ b/drivers/iio/dac/ltc2688.c @@ -91,10 +91,10 @@ struct ltc2688_state { struct mutex lock; int vref; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ - u8 tx_data[6] ____cacheline_aligned; + u8 tx_data[6] __aligned(IIO_DMA_MINALIGN); u8 rx_data[3]; }; diff --git a/drivers/iio/dac/max517.c b/drivers/iio/dac/max517.c index a6ef555153f4..373ce6ff83b7 100644 --- a/drivers/iio/dac/max517.c +++ b/drivers/iio/dac/max517.c @@ -100,21 +100,21 @@ static int max517_write_raw(struct iio_dev *indio_dev, return ret; } -static int __maybe_unused max517_suspend(struct device *dev) +static int max517_suspend(struct device *dev) { u8 outbuf = COMMAND_PD; return i2c_master_send(to_i2c_client(dev), &outbuf, 1); } -static int __maybe_unused max517_resume(struct device *dev) +static int max517_resume(struct device *dev) { u8 outbuf = 0; return i2c_master_send(to_i2c_client(dev), &outbuf, 1); } -static SIMPLE_DEV_PM_OPS(max517_pm_ops, max517_suspend, max517_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(max517_pm_ops, max517_suspend, max517_resume); static const struct iio_info max517_info = { .read_raw = max517_read_raw, @@ -201,7 +201,7 @@ MODULE_DEVICE_TABLE(i2c, max517_id); static struct i2c_driver max517_driver = { .driver = { .name = MAX517_DRV_NAME, - .pm = &max517_pm_ops, + .pm = pm_sleep_ptr(&max517_pm_ops), }, .probe = max517_probe, .id_table = max517_id, diff --git a/drivers/iio/dac/max5821.c b/drivers/iio/dac/max5821.c index 540f9ea7cada..e001b594d5b1 100644 --- a/drivers/iio/dac/max5821.c +++ b/drivers/iio/dac/max5821.c @@ -267,7 +267,7 @@ static int max5821_write_raw(struct iio_dev *indio_dev, } } -static int __maybe_unused max5821_suspend(struct device *dev) +static int max5821_suspend(struct device *dev) { u8 outbuf[2] = { MAX5821_EXTENDED_COMMAND_MODE, MAX5821_EXTENDED_DAC_A | @@ -277,7 +277,7 @@ static int __maybe_unused max5821_suspend(struct device *dev) return i2c_master_send(to_i2c_client(dev), outbuf, 2); } -static int __maybe_unused max5821_resume(struct device *dev) +static int max5821_resume(struct device *dev) { u8 outbuf[2] = { MAX5821_EXTENDED_COMMAND_MODE, MAX5821_EXTENDED_DAC_A | @@ -287,7 +287,8 @@ static int __maybe_unused max5821_resume(struct device *dev) return i2c_master_send(to_i2c_client(dev), outbuf, 2); } -static SIMPLE_DEV_PM_OPS(max5821_pm_ops, max5821_suspend, max5821_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(max5821_pm_ops, max5821_suspend, + max5821_resume); static const struct iio_info max5821_info = { .read_raw = max5821_read_raw, @@ -374,7 +375,7 @@ static struct i2c_driver max5821_driver = { .driver = { .name = "max5821", .of_match_table = max5821_of_match, - .pm = &max5821_pm_ops, + .pm = pm_sleep_ptr(&max5821_pm_ops), }, .probe = max5821_probe, .id_table = max5821_id, diff --git a/drivers/iio/dac/mcp4725.c b/drivers/iio/dac/mcp4725.c index 7fcb86288823..bb4b85a7b95b 100644 --- a/drivers/iio/dac/mcp4725.c +++ b/drivers/iio/dac/mcp4725.c @@ -42,7 +42,7 @@ struct mcp4725_data { struct regulator *vref_reg; }; -static int __maybe_unused mcp4725_suspend(struct device *dev) +static int mcp4725_suspend(struct device *dev) { struct mcp4725_data *data = iio_priv(i2c_get_clientdata( to_i2c_client(dev))); @@ -55,7 +55,7 @@ static int __maybe_unused mcp4725_suspend(struct device *dev) return i2c_master_send(data->client, outbuf, 2); } -static int __maybe_unused mcp4725_resume(struct device *dev) +static int mcp4725_resume(struct device *dev) { struct mcp4725_data *data = iio_priv(i2c_get_clientdata( to_i2c_client(dev))); @@ -68,7 +68,8 @@ static int __maybe_unused mcp4725_resume(struct device *dev) return i2c_master_send(data->client, outbuf, 2); } -static SIMPLE_DEV_PM_OPS(mcp4725_pm_ops, mcp4725_suspend, mcp4725_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(mcp4725_pm_ops, mcp4725_suspend, + mcp4725_resume); static ssize_t mcp4725_store_eeprom(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) @@ -523,7 +524,7 @@ static struct i2c_driver mcp4725_driver = { .driver = { .name = MCP4725_DRV_NAME, .of_match_table = mcp4725_of_match, - .pm = &mcp4725_pm_ops, + .pm = pm_sleep_ptr(&mcp4725_pm_ops), }, .probe = mcp4725_probe, .remove = mcp4725_remove, diff --git a/drivers/iio/dac/mcp4922.c b/drivers/iio/dac/mcp4922.c index cb9e60e71b91..da4327624d45 100644 --- a/drivers/iio/dac/mcp4922.c +++ b/drivers/iio/dac/mcp4922.c @@ -17,10 +17,12 @@ #include #define MCP4922_NUM_CHANNELS 2 +#define MCP4921_NUM_CHANNELS 1 enum mcp4922_supported_device_ids { ID_MCP4902, ID_MCP4912, + ID_MCP4921, ID_MCP4922, }; @@ -29,7 +31,7 @@ struct mcp4922_state { unsigned int value[MCP4922_NUM_CHANNELS]; unsigned int vref_mv; struct regulator *vref_reg; - u8 mosi[2] ____cacheline_aligned; + u8 mosi[2] __aligned(IIO_DMA_MINALIGN); }; #define MCP4922_CHAN(chan, bits) { \ @@ -105,9 +107,10 @@ static int mcp4922_write_raw(struct iio_dev *indio_dev, } } -static const struct iio_chan_spec mcp4922_channels[3][MCP4922_NUM_CHANNELS] = { +static const struct iio_chan_spec mcp4922_channels[4][MCP4922_NUM_CHANNELS] = { [ID_MCP4902] = { MCP4922_CHAN(0, 8), MCP4922_CHAN(1, 8) }, [ID_MCP4912] = { MCP4922_CHAN(0, 10), MCP4922_CHAN(1, 10) }, + [ID_MCP4921] = { MCP4922_CHAN(0, 12), {} }, [ID_MCP4922] = { MCP4922_CHAN(0, 12), MCP4922_CHAN(1, 12) }, }; @@ -154,7 +157,10 @@ static int mcp4922_probe(struct spi_device *spi) indio_dev->info = &mcp4922_info; indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->channels = mcp4922_channels[id->driver_data]; - indio_dev->num_channels = MCP4922_NUM_CHANNELS; + if (id->driver_data == ID_MCP4921) + indio_dev->num_channels = MCP4921_NUM_CHANNELS; + else + indio_dev->num_channels = MCP4922_NUM_CHANNELS; indio_dev->name = id->name; ret = iio_device_register(indio_dev); @@ -185,6 +191,7 @@ static void mcp4922_remove(struct spi_device *spi) static const struct spi_device_id mcp4922_id[] = { {"mcp4902", ID_MCP4902}, {"mcp4912", ID_MCP4912}, + {"mcp4921", ID_MCP4921}, {"mcp4922", ID_MCP4922}, {} }; diff --git a/drivers/iio/dac/stm32-dac.c b/drivers/iio/dac/stm32-dac.c index daa42bcbae83..15eb44075107 100644 --- a/drivers/iio/dac/stm32-dac.c +++ b/drivers/iio/dac/stm32-dac.c @@ -12,8 +12,11 @@ #include #include #include +#include +#include #include #include +#include #include "stm32-dac-core.h" @@ -79,8 +82,7 @@ static int stm32_dac_set_enable_state(struct iio_dev *indio_dev, int ch, ret = regmap_update_bits(dac->common->regmap, STM32_DAC_CR, msk, en); mutex_unlock(&dac->lock); if (ret < 0) { - dev_err(&indio_dev->dev, "%s failed\n", en ? - "Enable" : "Disable"); + dev_err(&indio_dev->dev, "%s failed\n", str_enable_disable(en)); goto err_put_pm; } diff --git a/drivers/iio/dac/ti-dac082s085.c b/drivers/iio/dac/ti-dac082s085.c index 106ce3546419..8e1590e3cc8b 100644 --- a/drivers/iio/dac/ti-dac082s085.c +++ b/drivers/iio/dac/ti-dac082s085.c @@ -55,7 +55,7 @@ struct ti_dac_chip { bool powerdown; u8 powerdown_mode; u8 resolution; - u8 buf[2] ____cacheline_aligned; + u8 buf[2] __aligned(IIO_DMA_MINALIGN); }; #define WRITE_NOT_UPDATE(chan) (0x00 | (chan) << 6) diff --git a/drivers/iio/dac/ti-dac5571.c b/drivers/iio/dac/ti-dac5571.c index 4b6b04038e94..f91f8a504989 100644 --- a/drivers/iio/dac/ti-dac5571.c +++ b/drivers/iio/dac/ti-dac5571.c @@ -13,6 +13,7 @@ * https://www.ti.com/lit/ds/symlink/dac5573.pdf * https://www.ti.com/lit/ds/symlink/dac6573.pdf * https://www.ti.com/lit/ds/symlink/dac7573.pdf + * https://www.ti.com/lit/ds/symlink/dac121c081.pdf */ #include @@ -52,7 +53,7 @@ struct dac5571_data { struct dac5571_spec const *spec; int (*dac5571_cmd)(struct dac5571_data *data, int channel, u16 val); int (*dac5571_pwrdwn)(struct dac5571_data *data, int channel, u8 pwrdwn); - u8 buf[3] ____cacheline_aligned; + u8 buf[3] __aligned(IIO_DMA_MINALIGN); }; #define DAC5571_POWERDOWN(mode) ((mode) + 1) @@ -402,6 +403,7 @@ static const struct of_device_id dac5571_of_id[] = { {.compatible = "ti,dac5573", .data = (void *)quad_8bit}, {.compatible = "ti,dac6573", .data = (void *)quad_10bit}, {.compatible = "ti,dac7573", .data = (void *)quad_12bit}, + {.compatible = "ti,dac121c081", .data = (void *)single_12bit}, {} }; MODULE_DEVICE_TABLE(of, dac5571_of_id); @@ -416,6 +418,7 @@ static const struct i2c_device_id dac5571_id[] = { {"dac5573", quad_8bit}, {"dac6573", quad_10bit}, {"dac7573", quad_12bit}, + {"dac121c081", single_12bit}, {} }; MODULE_DEVICE_TABLE(i2c, dac5571_id); diff --git a/drivers/iio/dac/ti-dac7311.c b/drivers/iio/dac/ti-dac7311.c index 4afc411725d9..7f89d2a52f49 100644 --- a/drivers/iio/dac/ti-dac7311.c +++ b/drivers/iio/dac/ti-dac7311.c @@ -52,7 +52,7 @@ struct ti_dac_chip { bool powerdown; u8 powerdown_mode; u8 resolution; - u8 buf[2] ____cacheline_aligned; + u8 buf[2] __aligned(IIO_DMA_MINALIGN); }; static u8 ti_dac_get_power(struct ti_dac_chip *ti_dac, bool powerdown) diff --git a/drivers/iio/dac/ti-dac7612.c b/drivers/iio/dac/ti-dac7612.c index 4c0f4b5e9ff4..8195815de26f 100644 --- a/drivers/iio/dac/ti-dac7612.c +++ b/drivers/iio/dac/ti-dac7612.c @@ -31,10 +31,10 @@ struct dac7612 { struct mutex lock; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ - uint8_t data[2] ____cacheline_aligned; + uint8_t data[2] __aligned(IIO_DMA_MINALIGN); }; static int dac7612_cmd_single(struct dac7612 *priv, int channel, u16 val) diff --git a/drivers/iio/dac/vf610_dac.c b/drivers/iio/dac/vf610_dac.c index 92429c0d2685..fc182250c622 100644 --- a/drivers/iio/dac/vf610_dac.c +++ b/drivers/iio/dac/vf610_dac.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/iio/frequency/ad9523.c b/drivers/iio/frequency/ad9523.c index 942870539268..97662ca1ca96 100644 --- a/drivers/iio/frequency/ad9523.c +++ b/drivers/iio/frequency/ad9523.c @@ -287,13 +287,13 @@ struct ad9523_state { struct mutex lock; /* - * DMA (thus cache coherency maintenance) requires the - * transfer buffers to live in their own cache lines. + * DMA (thus cache coherency maintenance) may require that + * transfer buffers live in their own cache lines. */ union { __be32 d32; u8 d8[4]; - } data[2] ____cacheline_aligned; + } data[2] __aligned(IIO_DMA_MINALIGN); }; static int ad9523_read(struct iio_dev *indio_dev, unsigned int addr) diff --git a/drivers/iio/frequency/adf4350.c b/drivers/iio/frequency/adf4350.c index be1218d86291..85e289700c3c 100644 --- a/drivers/iio/frequency/adf4350.c +++ b/drivers/iio/frequency/adf4350.c @@ -56,10 +56,10 @@ struct adf4350_state { */ struct mutex lock; /* - * DMA (thus cache coherency maintenance) requires the - * transfer buffers to live in their own cache lines. + * DMA (thus cache coherency maintenance) may require that + * transfer buffers live in their own cache lines. */ - __be32 val ____cacheline_aligned; + __be32 val __aligned(IIO_DMA_MINALIGN); }; static struct adf4350_platform_data default_pdata = { diff --git a/drivers/iio/frequency/adf4371.c b/drivers/iio/frequency/adf4371.c index ecd5e18995ad..135c8cedc33d 100644 --- a/drivers/iio/frequency/adf4371.c +++ b/drivers/iio/frequency/adf4371.c @@ -175,7 +175,7 @@ struct adf4371_state { unsigned int mod2; unsigned int rf_div_sel; unsigned int ref_div_factor; - u8 buf[10] ____cacheline_aligned; + u8 buf[10] __aligned(IIO_DMA_MINALIGN); }; static unsigned long long adf4371_pll_fract_n_get_rate(struct adf4371_state *st, diff --git a/drivers/iio/frequency/admv1013.c b/drivers/iio/frequency/admv1013.c index b0e1f6571afb..ed8167271358 100644 --- a/drivers/iio/frequency/admv1013.c +++ b/drivers/iio/frequency/admv1013.c @@ -100,7 +100,7 @@ struct admv1013_state { unsigned int input_mode; unsigned int quad_se_mode; bool det_en; - u8 data[3] ____cacheline_aligned; + u8 data[3] __aligned(IIO_DMA_MINALIGN); }; static int __admv1013_spi_read(struct admv1013_state *st, unsigned int reg, diff --git a/drivers/iio/frequency/admv1014.c b/drivers/iio/frequency/admv1014.c index 1aac5665b5de..865addd10db4 100644 --- a/drivers/iio/frequency/admv1014.c +++ b/drivers/iio/frequency/admv1014.c @@ -127,7 +127,7 @@ struct admv1014_state { unsigned int quad_se_mode; unsigned int p1db_comp; bool det_en; - u8 data[3] ____cacheline_aligned; + u8 data[3] __aligned(IIO_DMA_MINALIGN); }; static const int mixer_vgate_table[] = {106, 107, 108, 110, 111, 112, 113, 114, diff --git a/drivers/iio/frequency/admv4420.c b/drivers/iio/frequency/admv4420.c index 51134aee8510..863ba8e98c95 100644 --- a/drivers/iio/frequency/admv4420.c +++ b/drivers/iio/frequency/admv4420.c @@ -113,7 +113,7 @@ struct admv4420_state { struct admv4420_n_counter n_counter; enum admv4420_mux_sel mux_sel; struct mutex lock; - u8 transf_buf[4] ____cacheline_aligned; + u8 transf_buf[4] __aligned(IIO_DMA_MINALIGN); }; static const struct regmap_config admv4420_regmap_config = { diff --git a/drivers/iio/frequency/adrf6780.c b/drivers/iio/frequency/adrf6780.c index 8255ffd174f6..21878bad0909 100644 --- a/drivers/iio/frequency/adrf6780.c +++ b/drivers/iio/frequency/adrf6780.c @@ -86,7 +86,7 @@ struct adrf6780_state { bool uc_bias_en; bool lo_sideband; bool vdet_out_en; - u8 data[3] ____cacheline_aligned; + u8 data[3] __aligned(IIO_DMA_MINALIGN); }; static int __adrf6780_spi_read(struct adrf6780_state *st, unsigned int reg, diff --git a/drivers/iio/gyro/adis16080.c b/drivers/iio/gyro/adis16080.c index acef59d822b1..14b3abf6dce9 100644 --- a/drivers/iio/gyro/adis16080.c +++ b/drivers/iio/gyro/adis16080.c @@ -45,7 +45,7 @@ struct adis16080_state { const struct adis16080_chip_info *info; struct mutex lock; - __be16 buf ____cacheline_aligned; + __be16 buf __aligned(IIO_DMA_MINALIGN); }; static int adis16080_read_sample(struct iio_dev *indio_dev, diff --git a/drivers/iio/gyro/adis16130.c b/drivers/iio/gyro/adis16130.c index b9c952e65b55..33cde9e6fca5 100644 --- a/drivers/iio/gyro/adis16130.c +++ b/drivers/iio/gyro/adis16130.c @@ -41,7 +41,7 @@ struct adis16130_state { struct spi_device *us; struct mutex buf_lock; - u8 buf[4] ____cacheline_aligned; + u8 buf[4] __aligned(IIO_DMA_MINALIGN); }; static int adis16130_spi_read(struct iio_dev *indio_dev, u8 reg_addr, u32 *val) diff --git a/drivers/iio/gyro/adxrs450.c b/drivers/iio/gyro/adxrs450.c index 04f350025215..f84438e0c42c 100644 --- a/drivers/iio/gyro/adxrs450.c +++ b/drivers/iio/gyro/adxrs450.c @@ -73,7 +73,7 @@ enum { struct adxrs450_state { struct spi_device *us; struct mutex buf_lock; - __be32 tx ____cacheline_aligned; + __be32 tx __aligned(IIO_DMA_MINALIGN); __be32 rx; }; diff --git a/drivers/iio/gyro/bmg160_core.c b/drivers/iio/gyro/bmg160_core.c index 81a6d09788bd..cedd9f02ea21 100644 --- a/drivers/iio/gyro/bmg160_core.c +++ b/drivers/iio/gyro/bmg160_core.c @@ -766,7 +766,7 @@ static int bmg160_write_event_config(struct iio_dev *indio_dev, return 0; } /* - * We will expect the enable and disable to do operation in + * We will expect the enable and disable to do operation * in reverse order. This will happen here anyway as our * resume operation uses sync mode runtime pm calls, the * suspend operation will be delayed by autosuspend delay diff --git a/drivers/iio/gyro/fxas21002c_core.c b/drivers/iio/gyro/fxas21002c_core.c index 0923fd793492..a36d71d9e3ea 100644 --- a/drivers/iio/gyro/fxas21002c_core.c +++ b/drivers/iio/gyro/fxas21002c_core.c @@ -150,10 +150,10 @@ struct fxas21002c_data { struct regulator *vddio; /* - * DMA (thus cache coherency maintenance) requires the - * transfer buffers to live in their own cache lines. + * DMA (thus cache coherency maintenance) may require the + * transfer buffers live in their own cache lines. */ - s16 buffer[8] ____cacheline_aligned; + s16 buffer[8] __aligned(IIO_DMA_MINALIGN); }; enum fxas21002c_channel_index { diff --git a/drivers/iio/gyro/itg3200_core.c b/drivers/iio/gyro/itg3200_core.c index a7f1bbb5f289..0491c64e1b32 100644 --- a/drivers/iio/gyro/itg3200_core.c +++ b/drivers/iio/gyro/itg3200_core.c @@ -364,7 +364,7 @@ static int itg3200_remove(struct i2c_client *client) return 0; } -static int __maybe_unused itg3200_suspend(struct device *dev) +static int itg3200_suspend(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); struct itg3200 *st = iio_priv(indio_dev); @@ -375,14 +375,15 @@ static int __maybe_unused itg3200_suspend(struct device *dev) ITG3200_SLEEP); } -static int __maybe_unused itg3200_resume(struct device *dev) +static int itg3200_resume(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); return itg3200_initial_setup(indio_dev); } -static SIMPLE_DEV_PM_OPS(itg3200_pm_ops, itg3200_suspend, itg3200_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(itg3200_pm_ops, itg3200_suspend, + itg3200_resume); static const struct i2c_device_id itg3200_id[] = { { "itg3200", 0 }, @@ -400,7 +401,7 @@ static struct i2c_driver itg3200_driver = { .driver = { .name = "itg3200", .of_match_table = itg3200_of_match, - .pm = &itg3200_pm_ops, + .pm = pm_sleep_ptr(&itg3200_pm_ops), }, .id_table = itg3200_id, .probe = itg3200_probe, diff --git a/drivers/iio/gyro/mpu3050-core.c b/drivers/iio/gyro/mpu3050-core.c index 5908a96ca8af..6a6d84a3deda 100644 --- a/drivers/iio/gyro/mpu3050-core.c +++ b/drivers/iio/gyro/mpu3050-core.c @@ -1262,7 +1262,6 @@ err_power_down: return ret; } -EXPORT_SYMBOL(mpu3050_common_probe); void mpu3050_common_remove(struct device *dev) { @@ -1278,9 +1277,7 @@ void mpu3050_common_remove(struct device *dev) iio_device_unregister(indio_dev); mpu3050_power_down(mpu3050); } -EXPORT_SYMBOL(mpu3050_common_remove); -#ifdef CONFIG_PM static int mpu3050_runtime_suspend(struct device *dev) { return mpu3050_power_down(iio_priv(dev_get_drvdata(dev))); @@ -1290,16 +1287,9 @@ static int mpu3050_runtime_resume(struct device *dev) { return mpu3050_power_up(iio_priv(dev_get_drvdata(dev))); } -#endif /* CONFIG_PM */ - -const struct dev_pm_ops mpu3050_dev_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, - pm_runtime_force_resume) - SET_RUNTIME_PM_OPS(mpu3050_runtime_suspend, - mpu3050_runtime_resume, NULL) -}; -EXPORT_SYMBOL(mpu3050_dev_pm_ops); +DEFINE_RUNTIME_DEV_PM_OPS(mpu3050_dev_pm_ops, mpu3050_runtime_suspend, + mpu3050_runtime_resume, NULL); MODULE_AUTHOR("Linus Walleij"); MODULE_DESCRIPTION("MPU3050 gyroscope driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/iio/gyro/mpu3050-i2c.c b/drivers/iio/gyro/mpu3050-i2c.c index 5b5f58baaf7f..78f4a0102986 100644 --- a/drivers/iio/gyro/mpu3050-i2c.c +++ b/drivers/iio/gyro/mpu3050-i2c.c @@ -116,7 +116,7 @@ static struct i2c_driver mpu3050_i2c_driver = { .driver = { .of_match_table = mpu3050_i2c_of_match, .name = "mpu3050-i2c", - .pm = &mpu3050_dev_pm_ops, + .pm = pm_ptr(&mpu3050_dev_pm_ops), }, }; module_i2c_driver(mpu3050_i2c_driver); diff --git a/drivers/iio/health/afe4403.c b/drivers/iio/health/afe4403.c index 856ec901b091..3bb4028c5d74 100644 --- a/drivers/iio/health/afe4403.c +++ b/drivers/iio/health/afe4403.c @@ -408,7 +408,7 @@ static const struct of_device_id afe4403_of_match[] = { }; MODULE_DEVICE_TABLE(of, afe4403_of_match); -static int __maybe_unused afe4403_suspend(struct device *dev) +static int afe4403_suspend(struct device *dev) { struct iio_dev *indio_dev = spi_get_drvdata(to_spi_device(dev)); struct afe4403_data *afe = iio_priv(indio_dev); @@ -429,7 +429,7 @@ static int __maybe_unused afe4403_suspend(struct device *dev) return 0; } -static int __maybe_unused afe4403_resume(struct device *dev) +static int afe4403_resume(struct device *dev) { struct iio_dev *indio_dev = spi_get_drvdata(to_spi_device(dev)); struct afe4403_data *afe = iio_priv(indio_dev); @@ -449,7 +449,8 @@ static int __maybe_unused afe4403_resume(struct device *dev) return 0; } -static SIMPLE_DEV_PM_OPS(afe4403_pm_ops, afe4403_suspend, afe4403_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(afe4403_pm_ops, afe4403_suspend, + afe4403_resume); static int afe4403_probe(struct spi_device *spi) { @@ -598,7 +599,7 @@ static struct spi_driver afe4403_spi_driver = { .driver = { .name = AFE4403_DRIVER_NAME, .of_match_table = afe4403_of_match, - .pm = &afe4403_pm_ops, + .pm = pm_sleep_ptr(&afe4403_pm_ops), }, .probe = afe4403_probe, .remove = afe4403_remove, diff --git a/drivers/iio/health/afe4404.c b/drivers/iio/health/afe4404.c index aa9311e1e655..dd7800159051 100644 --- a/drivers/iio/health/afe4404.c +++ b/drivers/iio/health/afe4404.c @@ -415,7 +415,7 @@ static const struct of_device_id afe4404_of_match[] = { }; MODULE_DEVICE_TABLE(of, afe4404_of_match); -static int __maybe_unused afe4404_suspend(struct device *dev) +static int afe4404_suspend(struct device *dev) { struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); struct afe4404_data *afe = iio_priv(indio_dev); @@ -436,7 +436,7 @@ static int __maybe_unused afe4404_suspend(struct device *dev) return 0; } -static int __maybe_unused afe4404_resume(struct device *dev) +static int afe4404_resume(struct device *dev) { struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); struct afe4404_data *afe = iio_priv(indio_dev); @@ -456,7 +456,8 @@ static int __maybe_unused afe4404_resume(struct device *dev) return 0; } -static SIMPLE_DEV_PM_OPS(afe4404_pm_ops, afe4404_suspend, afe4404_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(afe4404_pm_ops, afe4404_suspend, + afe4404_resume); static int afe4404_probe(struct i2c_client *client, const struct i2c_device_id *id) @@ -591,10 +592,8 @@ static int afe4404_remove(struct i2c_client *client) iio_trigger_unregister(afe->trig); ret = regulator_disable(afe->regulator); - if (ret) { + if (ret) dev_err(afe->dev, "Unable to disable regulator\n"); - return ret; - } return 0; } @@ -609,7 +608,7 @@ static struct i2c_driver afe4404_i2c_driver = { .driver = { .name = AFE4404_DRIVER_NAME, .of_match_table = afe4404_of_match, - .pm = &afe4404_pm_ops, + .pm = pm_sleep_ptr(&afe4404_pm_ops), }, .probe = afe4404_probe, .remove = afe4404_remove, diff --git a/drivers/iio/humidity/hts221_buffer.c b/drivers/iio/humidity/hts221_buffer.c index 66b32413cf5e..2a4107a79662 100644 --- a/drivers/iio/humidity/hts221_buffer.c +++ b/drivers/iio/humidity/hts221_buffer.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include diff --git a/drivers/iio/humidity/hts221_core.c b/drivers/iio/humidity/hts221_core.c index 6a39615b6961..517158307d8c 100644 --- a/drivers/iio/humidity/hts221_core.c +++ b/drivers/iio/humidity/hts221_core.c @@ -668,9 +668,9 @@ int hts221_probe(struct device *dev, int irq, const char *name, return devm_iio_device_register(hw->dev, iio_dev); } -EXPORT_SYMBOL(hts221_probe); +EXPORT_SYMBOL_NS(hts221_probe, IIO_HTS221); -static int __maybe_unused hts221_suspend(struct device *dev) +static int hts221_suspend(struct device *dev) { struct iio_dev *iio_dev = dev_get_drvdata(dev); struct hts221_hw *hw = iio_priv(iio_dev); @@ -680,7 +680,7 @@ static int __maybe_unused hts221_suspend(struct device *dev) FIELD_PREP(HTS221_ENABLE_MASK, false)); } -static int __maybe_unused hts221_resume(struct device *dev) +static int hts221_resume(struct device *dev) { struct iio_dev *iio_dev = dev_get_drvdata(dev); struct hts221_hw *hw = iio_priv(iio_dev); @@ -694,10 +694,8 @@ static int __maybe_unused hts221_resume(struct device *dev) return err; } -const struct dev_pm_ops hts221_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(hts221_suspend, hts221_resume) -}; -EXPORT_SYMBOL(hts221_pm_ops); +EXPORT_NS_SIMPLE_DEV_PM_OPS(hts221_pm_ops, hts221_suspend, hts221_resume, + IIO_HTS221); MODULE_AUTHOR("Lorenzo Bianconi "); MODULE_DESCRIPTION("STMicroelectronics hts221 sensor driver"); diff --git a/drivers/iio/humidity/hts221_i2c.c b/drivers/iio/humidity/hts221_i2c.c index cab39c4756f8..afbc611f7712 100644 --- a/drivers/iio/humidity/hts221_i2c.c +++ b/drivers/iio/humidity/hts221_i2c.c @@ -62,7 +62,7 @@ MODULE_DEVICE_TABLE(i2c, hts221_i2c_id_table); static struct i2c_driver hts221_driver = { .driver = { .name = "hts221_i2c", - .pm = &hts221_pm_ops, + .pm = pm_sleep_ptr(&hts221_pm_ops), .of_match_table = hts221_i2c_of_match, .acpi_match_table = ACPI_PTR(hts221_acpi_match), }, @@ -74,3 +74,4 @@ module_i2c_driver(hts221_driver); MODULE_AUTHOR("Lorenzo Bianconi "); MODULE_DESCRIPTION("STMicroelectronics hts221 i2c driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(IIO_HTS221); diff --git a/drivers/iio/humidity/hts221_spi.c b/drivers/iio/humidity/hts221_spi.c index 729e86e433b1..fc4adb68faf6 100644 --- a/drivers/iio/humidity/hts221_spi.c +++ b/drivers/iio/humidity/hts221_spi.c @@ -55,7 +55,7 @@ MODULE_DEVICE_TABLE(spi, hts221_spi_id_table); static struct spi_driver hts221_driver = { .driver = { .name = "hts221_spi", - .pm = &hts221_pm_ops, + .pm = pm_sleep_ptr(&hts221_pm_ops), .of_match_table = hts221_spi_of_match, }, .probe = hts221_spi_probe, @@ -66,3 +66,4 @@ module_spi_driver(hts221_driver); MODULE_AUTHOR("Lorenzo Bianconi "); MODULE_DESCRIPTION("STMicroelectronics hts221 spi driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(IIO_HTS221); diff --git a/drivers/iio/imu/bmi160/bmi160_core.c b/drivers/iio/imu/bmi160/bmi160_core.c index e7aec56ea136..a77f1a8348ff 100644 --- a/drivers/iio/imu/bmi160/bmi160_core.c +++ b/drivers/iio/imu/bmi160/bmi160_core.c @@ -143,7 +143,7 @@ const struct regmap_config bmi160_regmap_config = { .reg_bits = 8, .val_bits = 8, }; -EXPORT_SYMBOL(bmi160_regmap_config); +EXPORT_SYMBOL_NS(bmi160_regmap_config, IIO_BMI160); struct bmi160_regs { u8 data; /* LSB byte register for X-axis */ @@ -633,7 +633,7 @@ int bmi160_enable_irq(struct regmap *regmap, bool enable) BMI160_DRDY_INT_EN, enable_bit, BMI160_NORMAL_WRITE_USLEEP); } -EXPORT_SYMBOL(bmi160_enable_irq); +EXPORT_SYMBOL_NS(bmi160_enable_irq, IIO_BMI160); static int bmi160_get_irq(struct fwnode_handle *fwnode, enum bmi160_int_pin *pin) { @@ -884,7 +884,7 @@ int bmi160_core_probe(struct device *dev, struct regmap *regmap, return devm_iio_device_register(dev, indio_dev); } -EXPORT_SYMBOL_GPL(bmi160_core_probe); +EXPORT_SYMBOL_NS_GPL(bmi160_core_probe, IIO_BMI160); MODULE_AUTHOR("Daniel Baluta "); MODULE_DESCRIPTION("Bosch BMI160 driver"); diff --git a/drivers/iio/imu/bmi160/bmi160_i2c.c b/drivers/iio/imu/bmi160/bmi160_i2c.c index 02f149d37b17..d93f4fa2ad55 100644 --- a/drivers/iio/imu/bmi160/bmi160_i2c.c +++ b/drivers/iio/imu/bmi160/bmi160_i2c.c @@ -68,3 +68,4 @@ module_i2c_driver(bmi160_i2c_driver); MODULE_AUTHOR("Daniel Baluta "); MODULE_DESCRIPTION("BMI160 I2C driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(IIO_BMI160); diff --git a/drivers/iio/imu/bmi160/bmi160_spi.c b/drivers/iio/imu/bmi160/bmi160_spi.c index 24f7d75c7903..8b573ea99af2 100644 --- a/drivers/iio/imu/bmi160/bmi160_spi.c +++ b/drivers/iio/imu/bmi160/bmi160_spi.c @@ -65,3 +65,4 @@ module_spi_driver(bmi160_spi_driver); MODULE_AUTHOR("Daniel Baluta #include #include +#include #include #include #include @@ -1615,8 +1616,7 @@ int st_lsm6dsx_set_watermark(struct iio_dev *iio_dev, unsigned int val) struct st_lsm6dsx_hw *hw = sensor->hw; int err; - if (val < 1 || val > hw->settings->fifo_ops.max_size) - return -EINVAL; + val = clamp_val(val, 1, hw->settings->fifo_ops.max_size); mutex_lock(&hw->conf_lock); @@ -2289,9 +2289,9 @@ int st_lsm6dsx_probe(struct device *dev, int irq, int hw_id, return 0; } -EXPORT_SYMBOL(st_lsm6dsx_probe); +EXPORT_SYMBOL_NS(st_lsm6dsx_probe, IIO_LSM6DSX); -static int __maybe_unused st_lsm6dsx_suspend(struct device *dev) +static int st_lsm6dsx_suspend(struct device *dev) { struct st_lsm6dsx_hw *hw = dev_get_drvdata(dev); struct st_lsm6dsx_sensor *sensor; @@ -2330,7 +2330,7 @@ static int __maybe_unused st_lsm6dsx_suspend(struct device *dev) return err; } -static int __maybe_unused st_lsm6dsx_resume(struct device *dev) +static int st_lsm6dsx_resume(struct device *dev) { struct st_lsm6dsx_hw *hw = dev_get_drvdata(dev); struct st_lsm6dsx_sensor *sensor; @@ -2366,10 +2366,8 @@ static int __maybe_unused st_lsm6dsx_resume(struct device *dev) return err; } -const struct dev_pm_ops st_lsm6dsx_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(st_lsm6dsx_suspend, st_lsm6dsx_resume) -}; -EXPORT_SYMBOL(st_lsm6dsx_pm_ops); +EXPORT_NS_SIMPLE_DEV_PM_OPS(st_lsm6dsx_pm_ops, st_lsm6dsx_suspend, + st_lsm6dsx_resume, IIO_LSM6DSX); MODULE_AUTHOR("Lorenzo Bianconi "); MODULE_AUTHOR("Denis Ciocca "); diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c index 715fbdc8190e..2ea34c0d3a8c 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c @@ -134,7 +134,7 @@ MODULE_DEVICE_TABLE(i2c, st_lsm6dsx_i2c_id_table); static struct i2c_driver st_lsm6dsx_driver = { .driver = { .name = "st_lsm6dsx_i2c", - .pm = &st_lsm6dsx_pm_ops, + .pm = pm_sleep_ptr(&st_lsm6dsx_pm_ops), .of_match_table = st_lsm6dsx_i2c_of_match, }, .probe = st_lsm6dsx_i2c_probe, @@ -146,3 +146,4 @@ MODULE_AUTHOR("Lorenzo Bianconi "); MODULE_AUTHOR("Denis Ciocca "); MODULE_DESCRIPTION("STMicroelectronics st_lsm6dsx i2c driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(IIO_LSM6DSX); diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i3c.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i3c.c index 8d4201b86e87..3b0c8b19c448 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i3c.c +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i3c.c @@ -6,11 +6,11 @@ */ #include +#include #include #include #include #include -#include #include #include "st_lsm6dsx.h" @@ -44,7 +44,7 @@ static int st_lsm6dsx_i3c_probe(struct i3c_device *i3cdev) static struct i3c_driver st_lsm6dsx_driver = { .driver = { .name = "st_lsm6dsx_i3c", - .pm = &st_lsm6dsx_pm_ops, + .pm = pm_sleep_ptr(&st_lsm6dsx_pm_ops), }, .probe = st_lsm6dsx_i3c_probe, .id_table = st_lsm6dsx_i3c_ids, @@ -54,3 +54,4 @@ module_i3c_driver(st_lsm6dsx_driver); MODULE_AUTHOR("Vitor Soares "); MODULE_DESCRIPTION("STMicroelectronics st_lsm6dsx i3c driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(IIO_LSM6DSX); diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c index f5767cf76c1d..6a8883f022a8 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c @@ -134,7 +134,7 @@ MODULE_DEVICE_TABLE(spi, st_lsm6dsx_spi_id_table); static struct spi_driver st_lsm6dsx_driver = { .driver = { .name = "st_lsm6dsx_spi", - .pm = &st_lsm6dsx_pm_ops, + .pm = pm_sleep_ptr(&st_lsm6dsx_pm_ops), .of_match_table = st_lsm6dsx_spi_of_match, }, .probe = st_lsm6dsx_spi_probe, @@ -146,3 +146,4 @@ MODULE_AUTHOR("Lorenzo Bianconi "); MODULE_AUTHOR("Denis Ciocca "); MODULE_DESCRIPTION("STMicroelectronics st_lsm6dsx spi driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(IIO_LSM6DSX); diff --git a/drivers/iio/industrialio-buffer.c b/drivers/iio/industrialio-buffer.c index 06141ca27e1f..acc2b6c05d57 100644 --- a/drivers/iio/industrialio-buffer.c +++ b/drivers/iio/industrialio-buffer.c @@ -630,18 +630,16 @@ static int iio_buffer_add_channel_sysfs(struct iio_dev *indio_dev, return ret; } -static ssize_t iio_buffer_read_length(struct device *dev, - struct device_attribute *attr, - char *buf) +static ssize_t length_show(struct device *dev, struct device_attribute *attr, + char *buf) { struct iio_buffer *buffer = to_iio_dev_attr(attr)->buffer; return sysfs_emit(buf, "%d\n", buffer->length); } -static ssize_t iio_buffer_write_length(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t len) +static ssize_t length_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) { struct iio_dev *indio_dev = dev_to_iio_dev(dev); struct iio_buffer *buffer = to_iio_dev_attr(attr)->buffer; @@ -672,9 +670,8 @@ out: return ret ? ret : len; } -static ssize_t iio_buffer_show_enable(struct device *dev, - struct device_attribute *attr, - char *buf) +static ssize_t enable_show(struct device *dev, struct device_attribute *attr, + char *buf) { struct iio_buffer *buffer = to_iio_dev_attr(attr)->buffer; @@ -705,7 +702,7 @@ static unsigned int iio_storage_bytes_for_timestamp(struct iio_dev *indio_dev) static int iio_compute_scan_bytes(struct iio_dev *indio_dev, const unsigned long *mask, bool timestamp) { - unsigned bytes = 0; + unsigned int bytes = 0; int length, i, largest = 0; /* How much space will the demuxed element take? */ @@ -934,9 +931,9 @@ static int iio_verify_update(struct iio_dev *indio_dev, * @l: list head used for management */ struct iio_demux_table { - unsigned from; - unsigned to; - unsigned length; + unsigned int from; + unsigned int to; + unsigned int length; struct list_head l; }; @@ -974,7 +971,7 @@ static int iio_buffer_update_demux(struct iio_dev *indio_dev, struct iio_buffer *buffer) { int ret, in_ind = -1, out_ind, length; - unsigned in_loc = 0, out_loc = 0; + unsigned int in_loc = 0, out_loc = 0; struct iio_demux_table *p = NULL; /* Clear out any old demux */ @@ -1292,10 +1289,8 @@ void iio_disable_all_buffers(struct iio_dev *indio_dev) iio_buffer_deactivate_all(indio_dev); } -static ssize_t iio_buffer_store_enable(struct device *dev, - struct device_attribute *attr, - const char *buf, - size_t len) +static ssize_t enable_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) { int ret; bool requested_state; @@ -1325,19 +1320,17 @@ done: return (ret < 0) ? ret : len; } -static ssize_t iio_buffer_show_watermark(struct device *dev, - struct device_attribute *attr, - char *buf) +static ssize_t watermark_show(struct device *dev, struct device_attribute *attr, + char *buf) { struct iio_buffer *buffer = to_iio_dev_attr(attr)->buffer; return sysfs_emit(buf, "%u\n", buffer->watermark); } -static ssize_t iio_buffer_store_watermark(struct device *dev, - struct device_attribute *attr, - const char *buf, - size_t len) +static ssize_t watermark_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) { struct iio_dev *indio_dev = dev_to_iio_dev(dev); struct iio_buffer *buffer = to_iio_dev_attr(attr)->buffer; @@ -1369,9 +1362,8 @@ out: return ret ? ret : len; } -static ssize_t iio_dma_show_data_available(struct device *dev, - struct device_attribute *attr, - char *buf) +static ssize_t data_available_show(struct device *dev, + struct device_attribute *attr, char *buf) { struct iio_buffer *buffer = to_iio_dev_attr(attr)->buffer; @@ -1394,18 +1386,12 @@ static ssize_t direction_show(struct device *dev, } } -static DEVICE_ATTR(length, S_IRUGO | S_IWUSR, iio_buffer_read_length, - iio_buffer_write_length); -static struct device_attribute dev_attr_length_ro = __ATTR(length, - S_IRUGO, iio_buffer_read_length, NULL); -static DEVICE_ATTR(enable, S_IRUGO | S_IWUSR, - iio_buffer_show_enable, iio_buffer_store_enable); -static DEVICE_ATTR(watermark, S_IRUGO | S_IWUSR, - iio_buffer_show_watermark, iio_buffer_store_watermark); -static struct device_attribute dev_attr_watermark_ro = __ATTR(watermark, - S_IRUGO, iio_buffer_show_watermark, NULL); -static DEVICE_ATTR(data_available, S_IRUGO, - iio_dma_show_data_available, NULL); +static DEVICE_ATTR_RW(length); +static struct device_attribute dev_attr_length_ro = __ATTR_RO(length); +static DEVICE_ATTR_RW(enable); +static DEVICE_ATTR_RW(watermark); +static struct device_attribute dev_attr_watermark_ro = __ATTR_RO(watermark); +static DEVICE_ATTR_RO(data_available); static DEVICE_ATTR_RO(direction); /* diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c index adf054c7a75e..0f4dbda3b9d3 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -334,29 +334,6 @@ s64 iio_get_time_ns(const struct iio_dev *indio_dev) } EXPORT_SYMBOL(iio_get_time_ns); -/** - * iio_get_time_res() - utility function to get time stamp clock resolution in - * nano seconds. - * @indio_dev: device - */ -unsigned int iio_get_time_res(const struct iio_dev *indio_dev) -{ - switch (iio_device_get_clock(indio_dev)) { - case CLOCK_REALTIME: - case CLOCK_MONOTONIC: - case CLOCK_MONOTONIC_RAW: - case CLOCK_BOOTTIME: - case CLOCK_TAI: - return hrtimer_resolution; - case CLOCK_REALTIME_COARSE: - case CLOCK_MONOTONIC_COARSE: - return LOW_RES_NSEC; - default: - BUG(); - } -} -EXPORT_SYMBOL(iio_get_time_res); - static int __init iio_init(void) { int ret; @@ -398,7 +375,7 @@ static ssize_t iio_debugfs_read_reg(struct file *file, char __user *userbuf, { struct iio_dev *indio_dev = file->private_data; struct iio_dev_opaque *iio_dev_opaque = to_iio_dev_opaque(indio_dev); - unsigned val = 0; + unsigned int val = 0; int ret; if (*ppos > 0) @@ -428,7 +405,7 @@ static ssize_t iio_debugfs_write_reg(struct file *file, { struct iio_dev *indio_dev = file->private_data; struct iio_dev_opaque *iio_dev_opaque = to_iio_dev_opaque(indio_dev); - unsigned reg, val; + unsigned int reg, val; char buf[80]; int ret; @@ -835,7 +812,23 @@ static ssize_t iio_format_avail_list(char *buf, const int *vals, static ssize_t iio_format_avail_range(char *buf, const int *vals, int type) { - return iio_format_list(buf, vals, type, 3, "[", "]"); + int length; + + /* + * length refers to the array size , not the number of elements. + * The purpose is to print the range [min , step ,max] so length should + * be 3 in case of int, and 6 for other types. + */ + switch (type) { + case IIO_VAL_INT: + length = 3; + break; + default: + length = 6; + break; + } + + return iio_format_list(buf, vals, type, length, "[", "]"); } static ssize_t iio_read_channel_info_avail(struct device *dev, @@ -1127,12 +1120,12 @@ int __iio_device_attr_init(struct device_attribute *dev_attr, dev_attr->attr.name = name; if (readfunc) { - dev_attr->attr.mode |= S_IRUGO; + dev_attr->attr.mode |= 0444; dev_attr->show = readfunc; } if (writefunc) { - dev_attr->attr.mode |= S_IWUSR; + dev_attr->attr.mode |= 0200; dev_attr->store = writefunc; } @@ -1406,29 +1399,27 @@ void iio_free_chan_devattr_list(struct list_head *attr_list) } } -static ssize_t iio_show_dev_name(struct device *dev, - struct device_attribute *attr, - char *buf) +static ssize_t name_show(struct device *dev, struct device_attribute *attr, + char *buf) { struct iio_dev *indio_dev = dev_to_iio_dev(dev); return sysfs_emit(buf, "%s\n", indio_dev->name); } -static DEVICE_ATTR(name, S_IRUGO, iio_show_dev_name, NULL); +static DEVICE_ATTR_RO(name); -static ssize_t iio_show_dev_label(struct device *dev, - struct device_attribute *attr, - char *buf) +static ssize_t label_show(struct device *dev, struct device_attribute *attr, + char *buf) { struct iio_dev *indio_dev = dev_to_iio_dev(dev); return sysfs_emit(buf, "%s\n", indio_dev->label); } -static DEVICE_ATTR(label, S_IRUGO, iio_show_dev_label, NULL); +static DEVICE_ATTR_RO(label); -static ssize_t iio_show_timestamp_clock(struct device *dev, - struct device_attribute *attr, - char *buf) +static ssize_t current_timestamp_clock_show(struct device *dev, + struct device_attribute *attr, + char *buf) { const struct iio_dev *indio_dev = dev_to_iio_dev(dev); const clockid_t clk = iio_device_get_clock(indio_dev); @@ -1472,9 +1463,9 @@ static ssize_t iio_show_timestamp_clock(struct device *dev, return sz; } -static ssize_t iio_store_timestamp_clock(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t len) +static ssize_t current_timestamp_clock_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) { clockid_t clk; int ret; @@ -1522,8 +1513,7 @@ int iio_device_register_sysfs_group(struct iio_dev *indio_dev, return 0; } -static DEVICE_ATTR(current_timestamp_clock, S_IRUGO | S_IWUSR, - iio_show_timestamp_clock, iio_store_timestamp_clock); +static DEVICE_ATTR_RW(current_timestamp_clock); static int iio_device_register_sysfs(struct iio_dev *indio_dev) { @@ -1631,7 +1621,7 @@ static void iio_dev_release(struct device *device) iio_device_detach_buffers(indio_dev); - ida_simple_remove(&iio_ida, iio_dev_opaque->id); + ida_free(&iio_ida, iio_dev_opaque->id); kfree(iio_dev_opaque); } @@ -1653,7 +1643,7 @@ struct iio_dev *iio_device_alloc(struct device *parent, int sizeof_priv) alloc_size = sizeof(struct iio_dev_opaque); if (sizeof_priv) { - alloc_size = ALIGN(alloc_size, IIO_ALIGN); + alloc_size = ALIGN(alloc_size, IIO_DMA_MINALIGN); alloc_size += sizeof_priv; } @@ -1663,7 +1653,7 @@ struct iio_dev *iio_device_alloc(struct device *parent, int sizeof_priv) indio_dev = &iio_dev_opaque->indio_dev; indio_dev->priv = (char *)iio_dev_opaque + - ALIGN(sizeof(struct iio_dev_opaque), IIO_ALIGN); + ALIGN(sizeof(struct iio_dev_opaque), IIO_DMA_MINALIGN); indio_dev->dev.parent = parent; indio_dev->dev.type = &iio_device_type; @@ -1673,7 +1663,7 @@ struct iio_dev *iio_device_alloc(struct device *parent, int sizeof_priv) mutex_init(&iio_dev_opaque->info_exist_lock); INIT_LIST_HEAD(&iio_dev_opaque->channel_attr_list); - iio_dev_opaque->id = ida_simple_get(&iio_ida, 0, 0, GFP_KERNEL); + iio_dev_opaque->id = ida_alloc(&iio_ida, GFP_KERNEL); if (iio_dev_opaque->id < 0) { /* cannot use a dev_err as the name isn't available */ pr_err("failed to get device id\n"); @@ -1682,7 +1672,7 @@ struct iio_dev *iio_device_alloc(struct device *parent, int sizeof_priv) } if (dev_set_name(&indio_dev->dev, "iio:device%d", iio_dev_opaque->id)) { - ida_simple_remove(&iio_ida, iio_dev_opaque->id); + ida_free(&iio_ida, iio_dev_opaque->id); kfree(iio_dev_opaque); return NULL; } diff --git a/drivers/iio/industrialio-sw-device.c b/drivers/iio/industrialio-sw-device.c index 49f775f16ad5..cdaf30a3f233 100644 --- a/drivers/iio/industrialio-sw-device.c +++ b/drivers/iio/industrialio-sw-device.c @@ -27,7 +27,7 @@ static DEFINE_MUTEX(iio_device_types_lock); static struct iio_sw_device_type *__iio_find_sw_device_type(const char *name, - unsigned len) + unsigned int len) { struct iio_sw_device_type *d = NULL, *iter; diff --git a/drivers/iio/industrialio-sw-trigger.c b/drivers/iio/industrialio-sw-trigger.c index 9ae793a70b8b..994f03a71520 100644 --- a/drivers/iio/industrialio-sw-trigger.c +++ b/drivers/iio/industrialio-sw-trigger.c @@ -27,7 +27,7 @@ static DEFINE_MUTEX(iio_trigger_types_lock); static struct iio_sw_trigger_type *__iio_find_sw_trigger_type(const char *name, - unsigned len) + unsigned int len) { struct iio_sw_trigger_type *t = NULL, *iter; diff --git a/drivers/iio/industrialio-trigger.c b/drivers/iio/industrialio-trigger.c index 585b6cef8fcc..b78814d869b7 100644 --- a/drivers/iio/industrialio-trigger.c +++ b/drivers/iio/industrialio-trigger.c @@ -37,7 +37,7 @@ static LIST_HEAD(iio_trigger_list); static DEFINE_MUTEX(iio_trigger_list_lock); /** - * iio_trigger_read_name() - retrieve useful identifying name + * name_show() - retrieve useful identifying name * @dev: device associated with the iio_trigger * @attr: pointer to the device_attribute structure that is * being processed @@ -46,15 +46,14 @@ static DEFINE_MUTEX(iio_trigger_list_lock); * Return: a negative number on failure or the number of written * characters on success. */ -static ssize_t iio_trigger_read_name(struct device *dev, - struct device_attribute *attr, - char *buf) +static ssize_t name_show(struct device *dev, struct device_attribute *attr, + char *buf) { struct iio_trigger *trig = to_iio_trigger(dev); return sysfs_emit(buf, "%s\n", trig->name); } -static DEVICE_ATTR(name, S_IRUGO, iio_trigger_read_name, NULL); +static DEVICE_ATTR_RO(name); static struct attribute *iio_trig_dev_attrs[] = { &dev_attr_name.attr, @@ -64,14 +63,11 @@ ATTRIBUTE_GROUPS(iio_trig_dev); static struct iio_trigger *__iio_trigger_find_by_name(const char *name); -int __iio_trigger_register(struct iio_trigger *trig_info, - struct module *this_mod) +int iio_trigger_register(struct iio_trigger *trig_info) { int ret; - trig_info->owner = this_mod; - - trig_info->id = ida_simple_get(&iio_trigger_ida, 0, 0, GFP_KERNEL); + trig_info->id = ida_alloc(&iio_trigger_ida, GFP_KERNEL); if (trig_info->id < 0) return trig_info->id; @@ -98,10 +94,10 @@ error_device_del: mutex_unlock(&iio_trigger_list_lock); device_del(&trig_info->dev); error_unregister_id: - ida_simple_remove(&iio_trigger_ida, trig_info->id); + ida_free(&iio_trigger_ida, trig_info->id); return ret; } -EXPORT_SYMBOL(__iio_trigger_register); +EXPORT_SYMBOL(iio_trigger_register); void iio_trigger_unregister(struct iio_trigger *trig_info) { @@ -109,7 +105,7 @@ void iio_trigger_unregister(struct iio_trigger *trig_info) list_del(&trig_info->list); mutex_unlock(&iio_trigger_list_lock); - ida_simple_remove(&iio_trigger_ida, trig_info->id); + ida_free(&iio_trigger_ida, trig_info->id); /* Possible issue in here */ device_del(&trig_info->dev); } @@ -368,8 +364,8 @@ struct iio_poll_func va_list vargs; struct iio_poll_func *pf; - pf = kmalloc(sizeof *pf, GFP_KERNEL); - if (pf == NULL) + pf = kmalloc(sizeof(*pf), GFP_KERNEL); + if (!pf) return NULL; va_start(vargs, fmt); pf->name = kvasprintf(GFP_KERNEL, fmt, vargs); @@ -395,7 +391,7 @@ void iio_dealloc_pollfunc(struct iio_poll_func *pf) EXPORT_SYMBOL_GPL(iio_dealloc_pollfunc); /** - * iio_trigger_read_current() - trigger consumer sysfs query current trigger + * current_trigger_show() - trigger consumer sysfs query current trigger * @dev: device associated with an industrial I/O device * @attr: pointer to the device_attribute structure that * is being processed @@ -407,9 +403,8 @@ EXPORT_SYMBOL_GPL(iio_dealloc_pollfunc); * Return: a negative number on failure, the number of characters written * on success or 0 if no trigger is available */ -static ssize_t iio_trigger_read_current(struct device *dev, - struct device_attribute *attr, - char *buf) +static ssize_t current_trigger_show(struct device *dev, + struct device_attribute *attr, char *buf) { struct iio_dev *indio_dev = dev_to_iio_dev(dev); @@ -419,7 +414,7 @@ static ssize_t iio_trigger_read_current(struct device *dev, } /** - * iio_trigger_write_current() - trigger consumer sysfs set current trigger + * current_trigger_store() - trigger consumer sysfs set current trigger * @dev: device associated with an industrial I/O device * @attr: device attribute that is being processed * @buf: string buffer that holds the name of the trigger @@ -432,10 +427,9 @@ static ssize_t iio_trigger_read_current(struct device *dev, * Return: negative error code on failure or length of the buffer * on success */ -static ssize_t iio_trigger_write_current(struct device *dev, - struct device_attribute *attr, - const char *buf, - size_t len) +static ssize_t current_trigger_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) { struct iio_dev *indio_dev = dev_to_iio_dev(dev); struct iio_dev_opaque *iio_dev_opaque = to_iio_dev_opaque(indio_dev); @@ -494,9 +488,7 @@ out_trigger_put: return ret; } -static DEVICE_ATTR(current_trigger, S_IRUGO | S_IWUSR, - iio_trigger_read_current, - iio_trigger_write_current); +static DEVICE_ATTR_RW(current_trigger); static struct attribute *iio_trigger_consumer_attrs[] = { &dev_attr_current_trigger.attr, @@ -552,15 +544,16 @@ static void iio_trig_subirqunmask(struct irq_data *d) trig->subirqs[d->irq - trig->subirq_base].enabled = true; } -static __printf(2, 0) +static __printf(3, 0) struct iio_trigger *viio_trigger_alloc(struct device *parent, + struct module *this_mod, const char *fmt, va_list vargs) { struct iio_trigger *trig; int i; - trig = kzalloc(sizeof *trig, GFP_KERNEL); + trig = kzalloc(sizeof(*trig), GFP_KERNEL); if (!trig) return NULL; @@ -581,6 +574,10 @@ struct iio_trigger *viio_trigger_alloc(struct device *parent, if (trig->name == NULL) goto free_descs; + INIT_LIST_HEAD(&trig->list); + + trig->owner = this_mod; + trig->subirq_chip.name = trig->name; trig->subirq_chip.irq_mask = &iio_trig_subirqmask; trig->subirq_chip.irq_unmask = &iio_trig_subirqunmask; @@ -601,8 +598,9 @@ free_trig: } /** - * iio_trigger_alloc - Allocate a trigger + * __iio_trigger_alloc - Allocate a trigger * @parent: Device to allocate iio_trigger for + * @this_mod: module allocating the trigger * @fmt: trigger name format. If it includes format * specifiers, the additional arguments following * format are formatted and inserted in the resulting @@ -610,18 +608,20 @@ free_trig: * RETURNS: * Pointer to allocated iio_trigger on success, NULL on failure. */ -struct iio_trigger *iio_trigger_alloc(struct device *parent, const char *fmt, ...) +struct iio_trigger *__iio_trigger_alloc(struct device *parent, + struct module *this_mod, + const char *fmt, ...) { struct iio_trigger *trig; va_list vargs; va_start(vargs, fmt); - trig = viio_trigger_alloc(parent, fmt, vargs); + trig = viio_trigger_alloc(parent, this_mod, fmt, vargs); va_end(vargs); return trig; } -EXPORT_SYMBOL(iio_trigger_alloc); +EXPORT_SYMBOL(__iio_trigger_alloc); void iio_trigger_free(struct iio_trigger *trig) { @@ -636,10 +636,11 @@ static void devm_iio_trigger_release(struct device *dev, void *res) } /** - * devm_iio_trigger_alloc - Resource-managed iio_trigger_alloc() + * __devm_iio_trigger_alloc - Resource-managed iio_trigger_alloc() * Managed iio_trigger_alloc. iio_trigger allocated with this function is * automatically freed on driver detach. * @parent: Device to allocate iio_trigger for + * @this_mod: module allocating the trigger * @fmt: trigger name format. If it includes format * specifiers, the additional arguments following * format are formatted and inserted in the resulting @@ -649,7 +650,9 @@ static void devm_iio_trigger_release(struct device *dev, void *res) * RETURNS: * Pointer to allocated iio_trigger on success, NULL on failure. */ -struct iio_trigger *devm_iio_trigger_alloc(struct device *parent, const char *fmt, ...) +struct iio_trigger *__devm_iio_trigger_alloc(struct device *parent, + struct module *this_mod, + const char *fmt, ...) { struct iio_trigger **ptr, *trig; va_list vargs; @@ -661,7 +664,7 @@ struct iio_trigger *devm_iio_trigger_alloc(struct device *parent, const char *fm /* use raw alloc_dr for kmalloc caller tracing */ va_start(vargs, fmt); - trig = viio_trigger_alloc(parent, fmt, vargs); + trig = viio_trigger_alloc(parent, this_mod, fmt, vargs); va_end(vargs); if (trig) { *ptr = trig; @@ -672,7 +675,7 @@ struct iio_trigger *devm_iio_trigger_alloc(struct device *parent, const char *fm return trig; } -EXPORT_SYMBOL_GPL(devm_iio_trigger_alloc); +EXPORT_SYMBOL_GPL(__devm_iio_trigger_alloc); static void devm_iio_trigger_unreg(void *trigger_info) { @@ -680,10 +683,9 @@ static void devm_iio_trigger_unreg(void *trigger_info) } /** - * __devm_iio_trigger_register - Resource-managed iio_trigger_register() + * devm_iio_trigger_register - Resource-managed iio_trigger_register() * @dev: device this trigger was allocated for * @trig_info: trigger to register - * @this_mod: module registering the trigger * * Managed iio_trigger_register(). The IIO trigger registered with this * function is automatically unregistered on driver detach. This function @@ -693,19 +695,18 @@ static void devm_iio_trigger_unreg(void *trigger_info) * RETURNS: * 0 on success, negative error number on failure. */ -int __devm_iio_trigger_register(struct device *dev, - struct iio_trigger *trig_info, - struct module *this_mod) +int devm_iio_trigger_register(struct device *dev, + struct iio_trigger *trig_info) { int ret; - ret = __iio_trigger_register(trig_info, this_mod); + ret = iio_trigger_register(trig_info); if (ret) return ret; return devm_add_action_or_reset(dev, devm_iio_trigger_unreg, trig_info); } -EXPORT_SYMBOL_GPL(__devm_iio_trigger_register); +EXPORT_SYMBOL_GPL(devm_iio_trigger_register); bool iio_trigger_using_own(struct iio_dev *indio_dev) { diff --git a/drivers/iio/light/al3010.c b/drivers/iio/light/al3010.c index b4e9924094cd..ce5363845b22 100644 --- a/drivers/iio/light/al3010.c +++ b/drivers/iio/light/al3010.c @@ -200,17 +200,17 @@ static int al3010_probe(struct i2c_client *client, return devm_iio_device_register(&client->dev, indio_dev); } -static int __maybe_unused al3010_suspend(struct device *dev) +static int al3010_suspend(struct device *dev) { return al3010_set_pwr(to_i2c_client(dev), false); } -static int __maybe_unused al3010_resume(struct device *dev) +static int al3010_resume(struct device *dev) { return al3010_set_pwr(to_i2c_client(dev), true); } -static SIMPLE_DEV_PM_OPS(al3010_pm_ops, al3010_suspend, al3010_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(al3010_pm_ops, al3010_suspend, al3010_resume); static const struct i2c_device_id al3010_id[] = { {"al3010", }, @@ -228,7 +228,7 @@ static struct i2c_driver al3010_driver = { .driver = { .name = AL3010_DRV_NAME, .of_match_table = al3010_of_match, - .pm = &al3010_pm_ops, + .pm = pm_sleep_ptr(&al3010_pm_ops), }, .probe = al3010_probe, .id_table = al3010_id, diff --git a/drivers/iio/light/al3320a.c b/drivers/iio/light/al3320a.c index cc1407ccc10a..bc99179728ed 100644 --- a/drivers/iio/light/al3320a.c +++ b/drivers/iio/light/al3320a.c @@ -223,17 +223,18 @@ static int al3320a_probe(struct i2c_client *client, return devm_iio_device_register(&client->dev, indio_dev); } -static int __maybe_unused al3320a_suspend(struct device *dev) +static int al3320a_suspend(struct device *dev) { return al3320a_set_pwr(to_i2c_client(dev), false); } -static int __maybe_unused al3320a_resume(struct device *dev) +static int al3320a_resume(struct device *dev) { return al3320a_set_pwr(to_i2c_client(dev), true); } -static SIMPLE_DEV_PM_OPS(al3320a_pm_ops, al3320a_suspend, al3320a_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(al3320a_pm_ops, al3320a_suspend, + al3320a_resume); static const struct i2c_device_id al3320a_id[] = { {"al3320a", 0}, @@ -251,7 +252,7 @@ static struct i2c_driver al3320a_driver = { .driver = { .name = AL3320A_DRV_NAME, .of_match_table = al3320a_of_match, - .pm = &al3320a_pm_ops, + .pm = pm_sleep_ptr(&al3320a_pm_ops), }, .probe = al3320a_probe, .id_table = al3320a_id, diff --git a/drivers/iio/light/as73211.c b/drivers/iio/light/as73211.c index 3ba2378df3dd..2307fc531752 100644 --- a/drivers/iio/light/as73211.c +++ b/drivers/iio/light/as73211.c @@ -755,21 +755,22 @@ static int as73211_probe(struct i2c_client *client) return devm_iio_device_register(dev, indio_dev); } -static int __maybe_unused as73211_suspend(struct device *dev) +static int as73211_suspend(struct device *dev) { struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); return as73211_power(indio_dev, false); } -static int __maybe_unused as73211_resume(struct device *dev) +static int as73211_resume(struct device *dev) { struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); return as73211_power(indio_dev, true); } -static SIMPLE_DEV_PM_OPS(as73211_pm_ops, as73211_suspend, as73211_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(as73211_pm_ops, as73211_suspend, + as73211_resume); static const struct of_device_id as73211_of_match[] = { { .compatible = "ams,as73211" }, @@ -787,7 +788,7 @@ static struct i2c_driver as73211_driver = { .driver = { .name = AS73211_DRV_NAME, .of_match_table = as73211_of_match, - .pm = &as73211_pm_ops, + .pm = pm_sleep_ptr(&as73211_pm_ops), }, .probe_new = as73211_probe, .id_table = as73211_id, diff --git a/drivers/iio/light/bh1750.c b/drivers/iio/light/bh1750.c index 48484b9401b9..471985c220bb 100644 --- a/drivers/iio/light/bh1750.c +++ b/drivers/iio/light/bh1750.c @@ -277,7 +277,7 @@ static int bh1750_remove(struct i2c_client *client) return 0; } -static int __maybe_unused bh1750_suspend(struct device *dev) +static int bh1750_suspend(struct device *dev) { int ret; struct bh1750_data *data = @@ -294,7 +294,7 @@ static int __maybe_unused bh1750_suspend(struct device *dev) return ret; } -static SIMPLE_DEV_PM_OPS(bh1750_pm_ops, bh1750_suspend, NULL); +static DEFINE_SIMPLE_DEV_PM_OPS(bh1750_pm_ops, bh1750_suspend, NULL); static const struct i2c_device_id bh1750_id[] = { { "bh1710", BH1710 }, @@ -320,7 +320,7 @@ static struct i2c_driver bh1750_driver = { .driver = { .name = "bh1750", .of_match_table = bh1750_of_match, - .pm = &bh1750_pm_ops, + .pm = pm_sleep_ptr(&bh1750_pm_ops), }, .probe = bh1750_probe, .remove = bh1750_remove, diff --git a/drivers/iio/light/bh1780.c b/drivers/iio/light/bh1780.c index 790d3d613979..fc7141390117 100644 --- a/drivers/iio/light/bh1780.c +++ b/drivers/iio/light/bh1780.c @@ -213,10 +213,9 @@ static int bh1780_remove(struct i2c_client *client) pm_runtime_put_noidle(&client->dev); pm_runtime_disable(&client->dev); ret = bh1780_write(bh1780, BH1780_REG_CONTROL, BH1780_POFF); - if (ret < 0) { - dev_err(&client->dev, "failed to power off\n"); - return ret; - } + if (ret < 0) + dev_err(&client->dev, "failed to power off (%pe)\n", + ERR_PTR(ret)); return 0; } diff --git a/drivers/iio/light/cm32181.c b/drivers/iio/light/cm32181.c index 97649944f1df..edbe6a3138d0 100644 --- a/drivers/iio/light/cm32181.c +++ b/drivers/iio/light/cm32181.c @@ -460,6 +460,8 @@ static int cm32181_probe(struct i2c_client *client) return PTR_ERR(client); } + i2c_set_clientdata(client, indio_dev); + cm32181 = iio_priv(indio_dev); cm32181->client = client; cm32181->dev = dev; @@ -486,6 +488,25 @@ static int cm32181_probe(struct i2c_client *client) return 0; } +static int cm32181_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + + return i2c_smbus_write_word_data(client, CM32181_REG_ADDR_CMD, + CM32181_CMD_ALS_DISABLE); +} + +static int cm32181_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct cm32181_chip *cm32181 = iio_priv(dev_get_drvdata(dev)); + + return i2c_smbus_write_word_data(client, CM32181_REG_ADDR_CMD, + cm32181->conf_regs[CM32181_REG_ADDR_CMD]); +} + +DEFINE_SIMPLE_DEV_PM_OPS(cm32181_pm_ops, cm32181_suspend, cm32181_resume); + static const struct of_device_id cm32181_of_match[] = { { .compatible = "capella,cm3218" }, { .compatible = "capella,cm32181" }, @@ -506,6 +527,7 @@ static struct i2c_driver cm32181_driver = { .name = "cm32181", .acpi_match_table = ACPI_PTR(cm32181_acpi_match), .of_match_table = cm32181_of_match, + .pm = pm_sleep_ptr(&cm32181_pm_ops), }, .probe_new = cm32181_probe, }; diff --git a/drivers/iio/light/cm3605.c b/drivers/iio/light/cm3605.c index 50d34a98839c..c721b69d5095 100644 --- a/drivers/iio/light/cm3605.c +++ b/drivers/iio/light/cm3605.c @@ -278,7 +278,7 @@ static int cm3605_remove(struct platform_device *pdev) return 0; } -static int __maybe_unused cm3605_pm_suspend(struct device *dev) +static int cm3605_pm_suspend(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); struct cm3605 *cm3605 = iio_priv(indio_dev); @@ -289,7 +289,7 @@ static int __maybe_unused cm3605_pm_suspend(struct device *dev) return 0; } -static int __maybe_unused cm3605_pm_resume(struct device *dev) +static int cm3605_pm_resume(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); struct cm3605 *cm3605 = iio_priv(indio_dev); @@ -302,11 +302,8 @@ static int __maybe_unused cm3605_pm_resume(struct device *dev) return 0; } - -static const struct dev_pm_ops cm3605_dev_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(cm3605_pm_suspend, - cm3605_pm_resume) -}; +static DEFINE_SIMPLE_DEV_PM_OPS(cm3605_dev_pm_ops, cm3605_pm_suspend, + cm3605_pm_resume); static const struct of_device_id cm3605_of_match[] = { {.compatible = "capella,cm3605"}, @@ -318,7 +315,7 @@ static struct platform_driver cm3605_driver = { .driver = { .name = "cm3605", .of_match_table = cm3605_of_match, - .pm = &cm3605_dev_pm_ops, + .pm = pm_sleep_ptr(&cm3605_dev_pm_ops), }, .probe = cm3605_probe, .remove = cm3605_remove, diff --git a/drivers/iio/light/cros_ec_light_prox.c b/drivers/iio/light/cros_ec_light_prox.c index de472f23d1cb..19e529c84e95 100644 --- a/drivers/iio/light/cros_ec_light_prox.c +++ b/drivers/iio/light/cros_ec_light_prox.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -181,15 +182,12 @@ static int cros_ec_light_prox_probe(struct platform_device *pdev) return -ENOMEM; ret = cros_ec_sensors_core_init(pdev, indio_dev, true, - cros_ec_sensors_capture, - cros_ec_sensors_push_data); + cros_ec_sensors_capture); if (ret) return ret; indio_dev->info = &cros_ec_light_prox_info; state = iio_priv(indio_dev); - state->core.type = state->core.resp->info.type; - state->core.loc = state->core.resp->info.location; channel = state->channels; /* Common part */ @@ -240,7 +238,8 @@ static int cros_ec_light_prox_probe(struct platform_device *pdev) state->core.read_ec_sensors_data = cros_ec_sensors_read_cmd; - return devm_iio_device_register(dev, indio_dev); + return cros_ec_sensors_core_register(dev, indio_dev, + cros_ec_sensors_push_data); } static const struct platform_device_id cros_ec_light_prox_ids[] = { diff --git a/drivers/iio/light/gp2ap002.c b/drivers/iio/light/gp2ap002.c index c6d1d88d3775..e2707416f9a8 100644 --- a/drivers/iio/light/gp2ap002.c +++ b/drivers/iio/light/gp2ap002.c @@ -635,7 +635,7 @@ static int gp2ap002_remove(struct i2c_client *client) return 0; } -static int __maybe_unused gp2ap002_runtime_suspend(struct device *dev) +static int gp2ap002_runtime_suspend(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); struct gp2ap002 *gp2ap002 = iio_priv(indio_dev); @@ -660,7 +660,7 @@ static int __maybe_unused gp2ap002_runtime_suspend(struct device *dev) return 0; } -static int __maybe_unused gp2ap002_runtime_resume(struct device *dev) +static int gp2ap002_runtime_resume(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); struct gp2ap002 *gp2ap002 = iio_priv(indio_dev); @@ -691,12 +691,8 @@ static int __maybe_unused gp2ap002_runtime_resume(struct device *dev) return 0; } -static const struct dev_pm_ops gp2ap002_dev_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, - pm_runtime_force_resume) - SET_RUNTIME_PM_OPS(gp2ap002_runtime_suspend, - gp2ap002_runtime_resume, NULL) -}; +static DEFINE_RUNTIME_DEV_PM_OPS(gp2ap002_dev_pm_ops, gp2ap002_runtime_suspend, + gp2ap002_runtime_resume, NULL); static const struct i2c_device_id gp2ap002_id_table[] = { { "gp2ap002", 0 }, @@ -715,7 +711,7 @@ static struct i2c_driver gp2ap002_driver = { .driver = { .name = "gp2ap002", .of_match_table = gp2ap002_of_match, - .pm = &gp2ap002_dev_pm_ops, + .pm = pm_ptr(&gp2ap002_dev_pm_ops), }, .probe = gp2ap002_probe, .remove = gp2ap002_remove, diff --git a/drivers/iio/light/isl29028.c b/drivers/iio/light/isl29028.c index 9de3262aa688..ff5996d77818 100644 --- a/drivers/iio/light/isl29028.c +++ b/drivers/iio/light/isl29028.c @@ -625,7 +625,7 @@ static int isl29028_probe(struct i2c_client *client, ISL29028_POWER_OFF_DELAY_MS); pm_runtime_use_autosuspend(&client->dev); - ret = devm_iio_device_register(indio_dev->dev.parent, indio_dev); + ret = iio_device_register(indio_dev); if (ret < 0) { dev_err(&client->dev, "%s(): iio registration failed with error %d\n", @@ -646,10 +646,12 @@ static int isl29028_remove(struct i2c_client *client) pm_runtime_disable(&client->dev); pm_runtime_set_suspended(&client->dev); - return isl29028_clear_configure_reg(chip); + isl29028_clear_configure_reg(chip); + + return 0; } -static int __maybe_unused isl29028_suspend(struct device *dev) +static int isl29028_suspend(struct device *dev) { struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); struct isl29028_chip *chip = iio_priv(indio_dev); @@ -664,7 +666,7 @@ static int __maybe_unused isl29028_suspend(struct device *dev) return ret; } -static int __maybe_unused isl29028_resume(struct device *dev) +static int isl29028_resume(struct device *dev) { /** * The specific component (ALS/IR or proximity) will enable itself as @@ -674,11 +676,8 @@ static int __maybe_unused isl29028_resume(struct device *dev) return 0; } -static const struct dev_pm_ops isl29028_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, - pm_runtime_force_resume) - SET_RUNTIME_PM_OPS(isl29028_suspend, isl29028_resume, NULL) -}; +static DEFINE_RUNTIME_DEV_PM_OPS(isl29028_pm_ops, isl29028_suspend, + isl29028_resume, NULL); static const struct i2c_device_id isl29028_id[] = { {"isl29028", 0}, @@ -698,7 +697,7 @@ MODULE_DEVICE_TABLE(of, isl29028_of_match); static struct i2c_driver isl29028_driver = { .driver = { .name = "isl29028", - .pm = &isl29028_pm_ops, + .pm = pm_ptr(&isl29028_pm_ops), .of_match_table = isl29028_of_match, }, .probe = isl29028_probe, diff --git a/drivers/iio/light/jsa1212.c b/drivers/iio/light/jsa1212.c index a55194263d23..5387c12231cf 100644 --- a/drivers/iio/light/jsa1212.c +++ b/drivers/iio/light/jsa1212.c @@ -380,7 +380,9 @@ static int jsa1212_remove(struct i2c_client *client) iio_device_unregister(indio_dev); - return jsa1212_power_off(data); + jsa1212_power_off(data); + + return 0; } static int jsa1212_suspend(struct device *dev) diff --git a/drivers/iio/light/opt3001.c b/drivers/iio/light/opt3001.c index 1880bd5bb258..a326d47afc9b 100644 --- a/drivers/iio/light/opt3001.c +++ b/drivers/iio/light/opt3001.c @@ -808,7 +808,7 @@ static int opt3001_remove(struct i2c_client *client) if (ret < 0) { dev_err(opt->dev, "failed to read register %02x\n", OPT3001_CONFIGURATION); - return ret; + return 0; } reg = ret; @@ -819,7 +819,6 @@ static int opt3001_remove(struct i2c_client *client) if (ret < 0) { dev_err(opt->dev, "failed to write register %02x\n", OPT3001_CONFIGURATION); - return ret; } return 0; diff --git a/drivers/iio/light/pa12203001.c b/drivers/iio/light/pa12203001.c index 528fa5dd2b13..772874e707ae 100644 --- a/drivers/iio/light/pa12203001.c +++ b/drivers/iio/light/pa12203001.c @@ -397,13 +397,19 @@ out_err: static int pa12203001_remove(struct i2c_client *client) { struct iio_dev *indio_dev = i2c_get_clientdata(client); + int ret; iio_device_unregister(indio_dev); pm_runtime_disable(&client->dev); pm_runtime_set_suspended(&client->dev); - return pa12203001_power_chip(indio_dev, PA12203001_CHIP_DISABLE); + ret = pa12203001_power_chip(indio_dev, PA12203001_CHIP_DISABLE); + if (ret) + dev_warn(&client->dev, "Failed to power down (%pe)\n", + ERR_PTR(ret)); + + return 0; } #if defined(CONFIG_PM_SLEEP) || defined(CONFIG_PM) diff --git a/drivers/iio/light/stk3310.c b/drivers/iio/light/stk3310.c index b578b46276cc..f7cc7a6c0c8d 100644 --- a/drivers/iio/light/stk3310.c +++ b/drivers/iio/light/stk3310.c @@ -654,7 +654,9 @@ static int stk3310_remove(struct i2c_client *client) struct iio_dev *indio_dev = i2c_get_clientdata(client); iio_device_unregister(indio_dev); - return stk3310_set_state(iio_priv(indio_dev), STK3310_STATE_STANDBY); + stk3310_set_state(iio_priv(indio_dev), STK3310_STATE_STANDBY); + + return 0; } static int stk3310_suspend(struct device *dev) diff --git a/drivers/iio/light/tsl2563.c b/drivers/iio/light/tsl2563.c index 0a278eea36ca..bbb577459fb9 100644 --- a/drivers/iio/light/tsl2563.c +++ b/drivers/iio/light/tsl2563.c @@ -310,7 +310,7 @@ static int tsl2563_get_adc(struct tsl2563_chip *chip) goto out; if (!chip->int_enabled) { - cancel_delayed_work(&chip->poweroff_work); + cancel_delayed_work_sync(&chip->poweroff_work); if (!tsl2563_get_power(chip)) { ret = tsl2563_set_power(chip, 1); @@ -638,7 +638,7 @@ static int tsl2563_write_interrupt_config(struct iio_dev *indio_dev, chip->intr &= ~0x30; chip->intr |= 0x10; /* ensure the chip is actually on */ - cancel_delayed_work(&chip->poweroff_work); + cancel_delayed_work_sync(&chip->poweroff_work); if (!tsl2563_get_power(chip)) { ret = tsl2563_set_power(chip, 1); if (ret) @@ -803,12 +803,11 @@ static int tsl2563_remove(struct i2c_client *client) iio_device_unregister(indio_dev); if (!chip->int_enabled) - cancel_delayed_work(&chip->poweroff_work); + cancel_delayed_work_sync(&chip->poweroff_work); /* Ensure that interrupts are disabled - then flush any bottom halves */ chip->intr &= ~0x30; i2c_smbus_write_byte_data(chip->client, TSL2563_CMD | TSL2563_REG_INT, chip->intr); - flush_scheduled_work(); tsl2563_set_power(chip, 0); return 0; diff --git a/drivers/iio/light/tsl2583.c b/drivers/iio/light/tsl2583.c index 7e101d5f72ee..82662dab87c0 100644 --- a/drivers/iio/light/tsl2583.c +++ b/drivers/iio/light/tsl2583.c @@ -883,10 +883,12 @@ static int tsl2583_remove(struct i2c_client *client) pm_runtime_disable(&client->dev); pm_runtime_set_suspended(&client->dev); - return tsl2583_set_power_state(chip, TSL2583_CNTL_PWR_OFF); + tsl2583_set_power_state(chip, TSL2583_CNTL_PWR_OFF); + + return 0; } -static int __maybe_unused tsl2583_suspend(struct device *dev) +static int tsl2583_suspend(struct device *dev) { struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); struct tsl2583_chip *chip = iio_priv(indio_dev); @@ -901,7 +903,7 @@ static int __maybe_unused tsl2583_suspend(struct device *dev) return ret; } -static int __maybe_unused tsl2583_resume(struct device *dev) +static int tsl2583_resume(struct device *dev) { struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); struct tsl2583_chip *chip = iio_priv(indio_dev); @@ -916,11 +918,8 @@ static int __maybe_unused tsl2583_resume(struct device *dev) return ret; } -static const struct dev_pm_ops tsl2583_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, - pm_runtime_force_resume) - SET_RUNTIME_PM_OPS(tsl2583_suspend, tsl2583_resume, NULL) -}; +static DEFINE_RUNTIME_DEV_PM_OPS(tsl2583_pm_ops, tsl2583_suspend, + tsl2583_resume, NULL); static const struct i2c_device_id tsl2583_idtable[] = { { "tsl2580", 0 }, @@ -942,7 +941,7 @@ MODULE_DEVICE_TABLE(of, tsl2583_of_match); static struct i2c_driver tsl2583_driver = { .driver = { .name = "tsl2583", - .pm = &tsl2583_pm_ops, + .pm = pm_ptr(&tsl2583_pm_ops), .of_match_table = tsl2583_of_match, }, .id_table = tsl2583_idtable, diff --git a/drivers/iio/light/tsl2591.c b/drivers/iio/light/tsl2591.c index 39e68d0c9d6a..e485a556e6da 100644 --- a/drivers/iio/light/tsl2591.c +++ b/drivers/iio/light/tsl2591.c @@ -1019,7 +1019,7 @@ static const struct iio_info tsl2591_info_no_irq = { .read_avail = tsl2591_read_available, }; -static int __maybe_unused tsl2591_suspend(struct device *dev) +static int tsl2591_suspend(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); struct tsl2591_chip *chip = iio_priv(indio_dev); @@ -1032,7 +1032,7 @@ static int __maybe_unused tsl2591_suspend(struct device *dev) return ret; } -static int __maybe_unused tsl2591_resume(struct device *dev) +static int tsl2591_resume(struct device *dev) { int power_state = TSL2591_PWR_ON | TSL2591_ENABLE_ALS; struct iio_dev *indio_dev = dev_get_drvdata(dev); @@ -1049,10 +1049,8 @@ static int __maybe_unused tsl2591_resume(struct device *dev) return ret; } -static const struct dev_pm_ops tsl2591_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) - SET_RUNTIME_PM_OPS(tsl2591_suspend, tsl2591_resume, NULL) -}; +static DEFINE_RUNTIME_DEV_PM_OPS(tsl2591_pm_ops, tsl2591_suspend, + tsl2591_resume, NULL); static irqreturn_t tsl2591_event_handler(int irq, void *private) { @@ -1213,7 +1211,7 @@ MODULE_DEVICE_TABLE(of, tsl2591_of_match); static struct i2c_driver tsl2591_driver = { .driver = { .name = "tsl2591", - .pm = &tsl2591_pm_ops, + .pm = pm_ptr(&tsl2591_pm_ops), .of_match_table = tsl2591_of_match, }, .probe_new = tsl2591_probe diff --git a/drivers/iio/light/us5182d.c b/drivers/iio/light/us5182d.c index 1492aaf8d84c..80d2299da561 100644 --- a/drivers/iio/light/us5182d.c +++ b/drivers/iio/light/us5182d.c @@ -907,16 +907,21 @@ out_err: static int us5182d_remove(struct i2c_client *client) { struct us5182d_data *data = iio_priv(i2c_get_clientdata(client)); + int ret; iio_device_unregister(i2c_get_clientdata(client)); pm_runtime_disable(&client->dev); pm_runtime_set_suspended(&client->dev); - return us5182d_shutdown_en(data, US5182D_CFG0_SHUTDOWN_EN); + ret = us5182d_shutdown_en(data, US5182D_CFG0_SHUTDOWN_EN); + if (ret) + dev_warn(&client->dev, "Failed to shut down (%pe)\n", + ERR_PTR(ret)); + + return 0; } -#if defined(CONFIG_PM_SLEEP) || defined(CONFIG_PM) static int us5182d_suspend(struct device *dev) { struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); @@ -939,11 +944,10 @@ static int us5182d_resume(struct device *dev) return 0; } -#endif static const struct dev_pm_ops us5182d_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(us5182d_suspend, us5182d_resume) - SET_RUNTIME_PM_OPS(us5182d_suspend, us5182d_resume, NULL) + SYSTEM_SLEEP_PM_OPS(us5182d_suspend, us5182d_resume) + RUNTIME_PM_OPS(us5182d_suspend, us5182d_resume, NULL) }; static const struct acpi_device_id us5182d_acpi_match[] = { @@ -969,7 +973,7 @@ MODULE_DEVICE_TABLE(of, us5182d_of_match); static struct i2c_driver us5182d_driver = { .driver = { .name = US5182D_DRV_NAME, - .pm = &us5182d_pm_ops, + .pm = pm_ptr(&us5182d_pm_ops), .of_match_table = us5182d_of_match, .acpi_match_table = ACPI_PTR(us5182d_acpi_match), }, diff --git a/drivers/iio/light/vcnl4000.c b/drivers/iio/light/vcnl4000.c index e02e92bc2928..3db4e26731bb 100644 --- a/drivers/iio/light/vcnl4000.c +++ b/drivers/iio/light/vcnl4000.c @@ -1115,16 +1115,22 @@ static int vcnl4000_remove(struct i2c_client *client) { struct iio_dev *indio_dev = i2c_get_clientdata(client); struct vcnl4000_data *data = iio_priv(indio_dev); + int ret; pm_runtime_dont_use_autosuspend(&client->dev); pm_runtime_disable(&client->dev); iio_device_unregister(indio_dev); pm_runtime_set_suspended(&client->dev); - return data->chip_spec->set_power_state(data, false); + ret = data->chip_spec->set_power_state(data, false); + if (ret) + dev_warn(&client->dev, "Failed to power down (%pe)\n", + ERR_PTR(ret)); + + return 0; } -static int __maybe_unused vcnl4000_runtime_suspend(struct device *dev) +static int vcnl4000_runtime_suspend(struct device *dev) { struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); struct vcnl4000_data *data = iio_priv(indio_dev); @@ -1132,7 +1138,7 @@ static int __maybe_unused vcnl4000_runtime_suspend(struct device *dev) return data->chip_spec->set_power_state(data, false); } -static int __maybe_unused vcnl4000_runtime_resume(struct device *dev) +static int vcnl4000_runtime_resume(struct device *dev) { struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); struct vcnl4000_data *data = iio_priv(indio_dev); @@ -1140,17 +1146,13 @@ static int __maybe_unused vcnl4000_runtime_resume(struct device *dev) return data->chip_spec->set_power_state(data, true); } -static const struct dev_pm_ops vcnl4000_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, - pm_runtime_force_resume) - SET_RUNTIME_PM_OPS(vcnl4000_runtime_suspend, - vcnl4000_runtime_resume, NULL) -}; +static DEFINE_RUNTIME_DEV_PM_OPS(vcnl4000_pm_ops, vcnl4000_runtime_suspend, + vcnl4000_runtime_resume, NULL); static struct i2c_driver vcnl4000_driver = { .driver = { .name = VCNL4000_DRV_NAME, - .pm = &vcnl4000_pm_ops, + .pm = pm_ptr(&vcnl4000_pm_ops), .of_match_table = vcnl_4000_of_match, }, .probe = vcnl4000_probe, diff --git a/drivers/iio/light/vcnl4035.c b/drivers/iio/light/vcnl4035.c index da2bf622a67b..6a196cf2270b 100644 --- a/drivers/iio/light/vcnl4035.c +++ b/drivers/iio/light/vcnl4035.c @@ -604,17 +604,23 @@ fail_poweroff: static int vcnl4035_remove(struct i2c_client *client) { struct iio_dev *indio_dev = i2c_get_clientdata(client); + int ret; pm_runtime_dont_use_autosuspend(&client->dev); pm_runtime_disable(&client->dev); iio_device_unregister(indio_dev); pm_runtime_set_suspended(&client->dev); - return vcnl4035_set_als_power_state(iio_priv(indio_dev), - VCNL4035_MODE_ALS_DISABLE); + ret = vcnl4035_set_als_power_state(iio_priv(indio_dev), + VCNL4035_MODE_ALS_DISABLE); + if (ret) + dev_warn(&client->dev, "Failed to put device into standby (%pe)\n", + ERR_PTR(ret)); + + return 0; } -static int __maybe_unused vcnl4035_runtime_suspend(struct device *dev) +static int vcnl4035_runtime_suspend(struct device *dev) { struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); struct vcnl4035_data *data = iio_priv(indio_dev); @@ -626,7 +632,7 @@ static int __maybe_unused vcnl4035_runtime_suspend(struct device *dev) return ret; } -static int __maybe_unused vcnl4035_runtime_resume(struct device *dev) +static int vcnl4035_runtime_resume(struct device *dev) { struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); struct vcnl4035_data *data = iio_priv(indio_dev); @@ -643,12 +649,8 @@ static int __maybe_unused vcnl4035_runtime_resume(struct device *dev) return 0; } -static const struct dev_pm_ops vcnl4035_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, - pm_runtime_force_resume) - SET_RUNTIME_PM_OPS(vcnl4035_runtime_suspend, - vcnl4035_runtime_resume, NULL) -}; +static DEFINE_RUNTIME_DEV_PM_OPS(vcnl4035_pm_ops, vcnl4035_runtime_suspend, + vcnl4035_runtime_resume, NULL); static const struct i2c_device_id vcnl4035_id[] = { { "vcnl4035", 0 }, @@ -665,7 +667,7 @@ MODULE_DEVICE_TABLE(of, vcnl4035_of_match); static struct i2c_driver vcnl4035_driver = { .driver = { .name = VCNL4035_DRV_NAME, - .pm = &vcnl4035_pm_ops, + .pm = pm_ptr(&vcnl4035_pm_ops), .of_match_table = vcnl4035_of_match, }, .probe = vcnl4035_probe, diff --git a/drivers/iio/light/veml6030.c b/drivers/iio/light/veml6030.c index 3c937c55a10d..9a7800cdfee2 100644 --- a/drivers/iio/light/veml6030.c +++ b/drivers/iio/light/veml6030.c @@ -846,7 +846,7 @@ static int veml6030_probe(struct i2c_client *client, return devm_iio_device_register(&client->dev, indio_dev); } -static int __maybe_unused veml6030_runtime_suspend(struct device *dev) +static int veml6030_runtime_suspend(struct device *dev) { int ret; struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); @@ -859,7 +859,7 @@ static int __maybe_unused veml6030_runtime_suspend(struct device *dev) return ret; } -static int __maybe_unused veml6030_runtime_resume(struct device *dev) +static int veml6030_runtime_resume(struct device *dev) { int ret; struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); @@ -872,12 +872,8 @@ static int __maybe_unused veml6030_runtime_resume(struct device *dev) return ret; } -static const struct dev_pm_ops veml6030_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, - pm_runtime_force_resume) - SET_RUNTIME_PM_OPS(veml6030_runtime_suspend, - veml6030_runtime_resume, NULL) -}; +static DEFINE_RUNTIME_DEV_PM_OPS(veml6030_pm_ops, veml6030_runtime_suspend, + veml6030_runtime_resume, NULL); static const struct of_device_id veml6030_of_match[] = { { .compatible = "vishay,veml6030" }, @@ -895,7 +891,7 @@ static struct i2c_driver veml6030_driver = { .driver = { .name = "veml6030", .of_match_table = veml6030_of_match, - .pm = &veml6030_pm_ops, + .pm = pm_ptr(&veml6030_pm_ops), }, .probe = veml6030_probe, .id_table = veml6030_id, diff --git a/drivers/iio/magnetometer/ak8974.c b/drivers/iio/magnetometer/ak8974.c index e54feacfb980..c89a91db0690 100644 --- a/drivers/iio/magnetometer/ak8974.c +++ b/drivers/iio/magnetometer/ak8974.c @@ -985,7 +985,7 @@ static int ak8974_remove(struct i2c_client *i2c) return 0; } -static int __maybe_unused ak8974_runtime_suspend(struct device *dev) +static int ak8974_runtime_suspend(struct device *dev) { struct ak8974 *ak8974 = iio_priv(i2c_get_clientdata(to_i2c_client(dev))); @@ -996,7 +996,7 @@ static int __maybe_unused ak8974_runtime_suspend(struct device *dev) return 0; } -static int __maybe_unused ak8974_runtime_resume(struct device *dev) +static int ak8974_runtime_resume(struct device *dev) { struct ak8974 *ak8974 = iio_priv(i2c_get_clientdata(to_i2c_client(dev))); @@ -1024,12 +1024,8 @@ out_regulator_disable: return ret; } -static const struct dev_pm_ops ak8974_dev_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, - pm_runtime_force_resume) - SET_RUNTIME_PM_OPS(ak8974_runtime_suspend, - ak8974_runtime_resume, NULL) -}; +static DEFINE_RUNTIME_DEV_PM_OPS(ak8974_dev_pm_ops, ak8974_runtime_suspend, + ak8974_runtime_resume, NULL); static const struct i2c_device_id ak8974_id[] = { {"ami305", 0 }, @@ -1050,7 +1046,7 @@ MODULE_DEVICE_TABLE(of, ak8974_of_match); static struct i2c_driver ak8974_driver = { .driver = { .name = "ak8974", - .pm = &ak8974_dev_pm_ops, + .pm = pm_ptr(&ak8974_dev_pm_ops), .of_match_table = ak8974_of_match, }, .probe = ak8974_probe, diff --git a/drivers/iio/magnetometer/bmc150_magn.c b/drivers/iio/magnetometer/bmc150_magn.c index 64e8b04e654b..06d5a1ef1fbd 100644 --- a/drivers/iio/magnetometer/bmc150_magn.c +++ b/drivers/iio/magnetometer/bmc150_magn.c @@ -985,7 +985,7 @@ err_poweroff: } EXPORT_SYMBOL_NS(bmc150_magn_probe, IIO_BMC150_MAGN); -int bmc150_magn_remove(struct device *dev) +void bmc150_magn_remove(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); struct bmc150_magn_data *data = iio_priv(indio_dev); @@ -1008,7 +1008,6 @@ int bmc150_magn_remove(struct device *dev) mutex_unlock(&data->mutex); regulator_bulk_disable(ARRAY_SIZE(data->regulators), data->regulators); - return 0; } EXPORT_SYMBOL_NS(bmc150_magn_remove, IIO_BMC150_MAGN); diff --git a/drivers/iio/magnetometer/bmc150_magn.h b/drivers/iio/magnetometer/bmc150_magn.h index 3b69232afd2c..98c086d10c13 100644 --- a/drivers/iio/magnetometer/bmc150_magn.h +++ b/drivers/iio/magnetometer/bmc150_magn.h @@ -7,6 +7,6 @@ extern const struct dev_pm_ops bmc150_magn_pm_ops; int bmc150_magn_probe(struct device *dev, struct regmap *regmap, int irq, const char *name); -int bmc150_magn_remove(struct device *dev); +void bmc150_magn_remove(struct device *dev); #endif /* _BMC150_MAGN_H_ */ diff --git a/drivers/iio/magnetometer/bmc150_magn_i2c.c b/drivers/iio/magnetometer/bmc150_magn_i2c.c index e39b89661ad1..65c004411d0f 100644 --- a/drivers/iio/magnetometer/bmc150_magn_i2c.c +++ b/drivers/iio/magnetometer/bmc150_magn_i2c.c @@ -36,7 +36,9 @@ static int bmc150_magn_i2c_probe(struct i2c_client *client, static int bmc150_magn_i2c_remove(struct i2c_client *client) { - return bmc150_magn_remove(&client->dev); + bmc150_magn_remove(&client->dev); + + return 0; } static const struct acpi_device_id bmc150_magn_acpi_match[] = { diff --git a/drivers/iio/magnetometer/hmc5843_core.c b/drivers/iio/magnetometer/hmc5843_core.c index 92eb2d156ddb..4a63b2da9df0 100644 --- a/drivers/iio/magnetometer/hmc5843_core.c +++ b/drivers/iio/magnetometer/hmc5843_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * Device driver for the the HMC5843 multi-chip module designed + * Device driver for the HMC5843 multi-chip module designed * for low field magnetic sensing. * * Copyright (C) 2010 Texas Instruments diff --git a/drivers/iio/magnetometer/rm3100-core.c b/drivers/iio/magnetometer/rm3100-core.c index 707ba25360b8..69938204456f 100644 --- a/drivers/iio/magnetometer/rm3100-core.c +++ b/drivers/iio/magnetometer/rm3100-core.c @@ -544,7 +544,7 @@ int rm3100_common_probe(struct device *dev, struct regmap *regmap, int irq) indio_dev->info = &rm3100_info; indio_dev->channels = rm3100_channels; indio_dev->num_channels = ARRAY_SIZE(rm3100_channels); - indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_TRIGGERED; + indio_dev->modes = INDIO_DIRECT_MODE; if (!irq) data->use_interrupt = false; diff --git a/drivers/iio/magnetometer/yamaha-yas530.c b/drivers/iio/magnetometer/yamaha-yas530.c index b2bc637150bf..aeaa4da6923b 100644 --- a/drivers/iio/magnetometer/yamaha-yas530.c +++ b/drivers/iio/magnetometer/yamaha-yas530.c @@ -965,7 +965,7 @@ static int yas5xx_remove(struct i2c_client *i2c) return 0; } -static int __maybe_unused yas5xx_runtime_suspend(struct device *dev) +static int yas5xx_runtime_suspend(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); struct yas5xx *yas5xx = iio_priv(indio_dev); @@ -976,7 +976,7 @@ static int __maybe_unused yas5xx_runtime_suspend(struct device *dev) return 0; } -static int __maybe_unused yas5xx_runtime_resume(struct device *dev) +static int yas5xx_runtime_resume(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); struct yas5xx *yas5xx = iio_priv(indio_dev); @@ -1011,12 +1011,8 @@ out_reset: return ret; } -static const struct dev_pm_ops yas5xx_dev_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, - pm_runtime_force_resume) - SET_RUNTIME_PM_OPS(yas5xx_runtime_suspend, - yas5xx_runtime_resume, NULL) -}; +static DEFINE_RUNTIME_DEV_PM_OPS(yas5xx_dev_pm_ops, yas5xx_runtime_suspend, + yas5xx_runtime_resume, NULL); static const struct i2c_device_id yas5xx_id[] = { {"yas530", }, @@ -1038,7 +1034,7 @@ static struct i2c_driver yas5xx_driver = { .driver = { .name = "yas5xx", .of_match_table = yas5xx_of_match, - .pm = &yas5xx_dev_pm_ops, + .pm = pm_ptr(&yas5xx_dev_pm_ops), }, .probe = yas5xx_probe, .remove = yas5xx_remove, diff --git a/drivers/iio/potentiometer/ad5110.c b/drivers/iio/potentiometer/ad5110.c index d4eeedae56e5..8fbcce482989 100644 --- a/drivers/iio/potentiometer/ad5110.c +++ b/drivers/iio/potentiometer/ad5110.c @@ -63,10 +63,10 @@ struct ad5110_data { struct mutex lock; const struct ad5110_cfg *cfg; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ - u8 buf[2] ____cacheline_aligned; + u8 buf[2] __aligned(IIO_DMA_MINALIGN); }; static const struct iio_chan_spec ad5110_channels[] = { diff --git a/drivers/iio/potentiometer/ad5272.c b/drivers/iio/potentiometer/ad5272.c index d8cbd170262f..ed5fc0b50fe9 100644 --- a/drivers/iio/potentiometer/ad5272.c +++ b/drivers/iio/potentiometer/ad5272.c @@ -50,7 +50,7 @@ struct ad5272_data { struct i2c_client *client; struct mutex lock; const struct ad5272_cfg *cfg; - u8 buf[2] ____cacheline_aligned; + u8 buf[2] __aligned(IIO_DMA_MINALIGN); }; static const struct iio_chan_spec ad5272_channel = { diff --git a/drivers/iio/potentiometer/max5481.c b/drivers/iio/potentiometer/max5481.c index 098d144a8fdd..b40e5ac218d7 100644 --- a/drivers/iio/potentiometer/max5481.c +++ b/drivers/iio/potentiometer/max5481.c @@ -44,7 +44,7 @@ static const struct max5481_cfg max5481_cfg[] = { struct max5481_data { struct spi_device *spi; const struct max5481_cfg *cfg; - u8 msg[3] ____cacheline_aligned; + u8 msg[3] __aligned(IIO_DMA_MINALIGN); }; #define MAX5481_CHANNEL { \ diff --git a/drivers/iio/potentiometer/mcp41010.c b/drivers/iio/potentiometer/mcp41010.c index 30a4594d4e11..2b73c7540209 100644 --- a/drivers/iio/potentiometer/mcp41010.c +++ b/drivers/iio/potentiometer/mcp41010.c @@ -60,7 +60,7 @@ struct mcp41010_data { const struct mcp41010_cfg *cfg; struct mutex lock; /* Protect write sequences */ unsigned int value[MCP41010_MAX_WIPERS]; /* Cache wiper values */ - u8 buf[2] ____cacheline_aligned; + u8 buf[2] __aligned(IIO_DMA_MINALIGN); }; #define MCP41010_CHANNEL(ch) { \ diff --git a/drivers/iio/potentiometer/mcp4131.c b/drivers/iio/potentiometer/mcp4131.c index 7c8c18ab8764..7890c0993ec4 100644 --- a/drivers/iio/potentiometer/mcp4131.c +++ b/drivers/iio/potentiometer/mcp4131.c @@ -129,7 +129,7 @@ struct mcp4131_data { struct spi_device *spi; const struct mcp4131_cfg *cfg; struct mutex lock; - u8 buf[2] ____cacheline_aligned; + u8 buf[2] __aligned(IIO_DMA_MINALIGN); }; #define MCP4131_CHANNEL(ch) { \ diff --git a/drivers/iio/pressure/bmp280-core.c b/drivers/iio/pressure/bmp280-core.c index bf8167f43c56..fe7aa81e7cc9 100644 --- a/drivers/iio/pressure/bmp280-core.c +++ b/drivers/iio/pressure/bmp280-core.c @@ -1136,7 +1136,7 @@ int bmp280_common_probe(struct device *dev, return devm_iio_device_register(dev, indio_dev); } -EXPORT_SYMBOL(bmp280_common_probe); +EXPORT_SYMBOL_NS(bmp280_common_probe, IIO_BMP280); static int bmp280_runtime_suspend(struct device *dev) { diff --git a/drivers/iio/pressure/bmp280-i2c.c b/drivers/iio/pressure/bmp280-i2c.c index 35045bd92846..bf4a7a617537 100644 --- a/drivers/iio/pressure/bmp280-i2c.c +++ b/drivers/iio/pressure/bmp280-i2c.c @@ -68,3 +68,4 @@ module_i2c_driver(bmp280_i2c_driver); MODULE_AUTHOR("Vlad Dogaru "); MODULE_DESCRIPTION("Driver for Bosch Sensortec BMP180/BMP280 pressure and temperature sensor"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(IIO_BMP280); diff --git a/drivers/iio/pressure/bmp280-regmap.c b/drivers/iio/pressure/bmp280-regmap.c index da136dbadc8f..969698518984 100644 --- a/drivers/iio/pressure/bmp280-regmap.c +++ b/drivers/iio/pressure/bmp280-regmap.c @@ -39,7 +39,7 @@ const struct regmap_config bmp180_regmap_config = { .writeable_reg = bmp180_is_writeable_reg, .volatile_reg = bmp180_is_volatile_reg, }; -EXPORT_SYMBOL(bmp180_regmap_config); +EXPORT_SYMBOL_NS(bmp180_regmap_config, IIO_BMP280); static bool bmp280_is_writeable_reg(struct device *dev, unsigned int reg) { @@ -82,4 +82,4 @@ const struct regmap_config bmp280_regmap_config = { .writeable_reg = bmp280_is_writeable_reg, .volatile_reg = bmp280_is_volatile_reg, }; -EXPORT_SYMBOL(bmp280_regmap_config); +EXPORT_SYMBOL_NS(bmp280_regmap_config, IIO_BMP280); diff --git a/drivers/iio/pressure/bmp280-spi.c b/drivers/iio/pressure/bmp280-spi.c index 41f6cc56d229..4cfaf3e869b8 100644 --- a/drivers/iio/pressure/bmp280-spi.c +++ b/drivers/iio/pressure/bmp280-spi.c @@ -118,3 +118,4 @@ module_spi_driver(bmp280_spi_driver); MODULE_DESCRIPTION("BMP280 SPI bus driver"); MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(IIO_BMP280); diff --git a/drivers/iio/pressure/cros_ec_baro.c b/drivers/iio/pressure/cros_ec_baro.c index 2f882e109423..2649c2f89e89 100644 --- a/drivers/iio/pressure/cros_ec_baro.c +++ b/drivers/iio/pressure/cros_ec_baro.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -138,15 +139,12 @@ static int cros_ec_baro_probe(struct platform_device *pdev) return -ENOMEM; ret = cros_ec_sensors_core_init(pdev, indio_dev, true, - cros_ec_sensors_capture, - cros_ec_sensors_push_data); + cros_ec_sensors_capture); if (ret) return ret; indio_dev->info = &cros_ec_baro_info; state = iio_priv(indio_dev); - state->core.type = state->core.resp->info.type; - state->core.loc = state->core.resp->info.location; channel = state->channels; /* Common part */ channel->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); @@ -186,7 +184,8 @@ static int cros_ec_baro_probe(struct platform_device *pdev) state->core.read_ec_sensors_data = cros_ec_sensors_read_cmd; - return devm_iio_device_register(dev, indio_dev); + return cros_ec_sensors_core_register(dev, indio_dev, + cros_ec_sensors_push_data); } static const struct platform_device_id cros_ec_baro_ids[] = { diff --git a/drivers/iio/pressure/dlhl60d.c b/drivers/iio/pressure/dlhl60d.c index ade73267d5eb..5f6bb3603a8b 100644 --- a/drivers/iio/pressure/dlhl60d.c +++ b/drivers/iio/pressure/dlhl60d.c @@ -47,7 +47,7 @@ struct dlh_state { struct dlh_info info; bool use_interrupt; struct completion completion; - u8 rx_buf[DLH_NUM_READ_BYTES] ____cacheline_aligned; + u8 rx_buf[DLH_NUM_READ_BYTES]; }; static struct dlh_info dlh_info_tbl[] = { diff --git a/drivers/iio/proximity/as3935.c b/drivers/iio/proximity/as3935.c index 67891ce2bd09..ebc95cf8f5f4 100644 --- a/drivers/iio/proximity/as3935.c +++ b/drivers/iio/proximity/as3935.c @@ -65,7 +65,7 @@ struct as3935_state { u8 chan; s64 timestamp __aligned(8); } scan; - u8 buf[2] ____cacheline_aligned; + u8 buf[2] __aligned(IIO_DMA_MINALIGN); }; static const struct iio_chan_spec as3935_channels[] = { diff --git a/drivers/iio/proximity/cros_ec_mkbp_proximity.c b/drivers/iio/proximity/cros_ec_mkbp_proximity.c index 8213b0081713..571ea1812246 100644 --- a/drivers/iio/proximity/cros_ec_mkbp_proximity.c +++ b/drivers/iio/proximity/cros_ec_mkbp_proximity.c @@ -184,7 +184,7 @@ static const struct iio_info cros_ec_mkbp_proximity_info = { .write_event_config = cros_ec_mkbp_proximity_write_event_config, }; -static __maybe_unused int cros_ec_mkbp_proximity_resume(struct device *dev) +static int cros_ec_mkbp_proximity_resume(struct device *dev) { struct cros_ec_mkbp_proximity_data *data = dev_get_drvdata(dev); struct cros_ec_device *ec = data->ec; @@ -201,8 +201,8 @@ static __maybe_unused int cros_ec_mkbp_proximity_resume(struct device *dev) return 0; } -static SIMPLE_DEV_PM_OPS(cros_ec_mkbp_proximity_pm_ops, NULL, - cros_ec_mkbp_proximity_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(cros_ec_mkbp_proximity_pm_ops, NULL, + cros_ec_mkbp_proximity_resume); static int cros_ec_mkbp_proximity_probe(struct platform_device *pdev) { @@ -260,7 +260,7 @@ static struct platform_driver cros_ec_mkbp_proximity_driver = { .driver = { .name = "cros-ec-mkbp-proximity", .of_match_table = cros_ec_mkbp_proximity_of_match, - .pm = &cros_ec_mkbp_proximity_pm_ops, + .pm = pm_sleep_ptr(&cros_ec_mkbp_proximity_pm_ops), }, .probe = cros_ec_mkbp_proximity_probe, .remove = cros_ec_mkbp_proximity_remove, diff --git a/drivers/iio/proximity/ping.c b/drivers/iio/proximity/ping.c index d56e037378de..2ad69b150902 100644 --- a/drivers/iio/proximity/ping.c +++ b/drivers/iio/proximity/ping.c @@ -173,7 +173,7 @@ static int ping_read(struct iio_dev *indio_dev) /* * read error code of laser ping sensor and give users chance to - * figure out error by using dynamic debuggging + * figure out error by using dynamic debugging */ if (data->cfg->laserping_error) { if ((time_ns > 12500000) && (time_ns <= 13500000)) { diff --git a/drivers/iio/proximity/srf04.c b/drivers/iio/proximity/srf04.c index 4e6286765f01..05015351a34a 100644 --- a/drivers/iio/proximity/srf04.c +++ b/drivers/iio/proximity/srf04.c @@ -37,9 +37,8 @@ #include #include #include +#include #include -#include -#include #include #include #include @@ -261,7 +260,7 @@ static int srf04_probe(struct platform_device *pdev) data = iio_priv(indio_dev); data->dev = dev; - data->cfg = of_match_device(of_srf04_match, dev)->data; + data->cfg = device_get_match_data(dev); mutex_init(&data->lock); init_completion(&data->rising); @@ -289,10 +288,8 @@ static int srf04_probe(struct platform_device *pdev) return PTR_ERR(data->gpiod_power); } if (data->gpiod_power) { - - if (of_property_read_u32(dev->of_node, "startup-time-ms", - &data->startup_time_ms)) - data->startup_time_ms = 100; + data->startup_time_ms = 100; + device_property_read_u32(dev, "startup-time-ms", &data->startup_time_ms); dev_dbg(dev, "using power gpio: startup-time-ms=%d\n", data->startup_time_ms); } diff --git a/drivers/iio/proximity/srf08.c b/drivers/iio/proximity/srf08.c index ac1ab7e89d4e..7ed11339c31e 100644 --- a/drivers/iio/proximity/srf08.c +++ b/drivers/iio/proximity/srf08.c @@ -354,7 +354,7 @@ static ssize_t srf08_write_sensitivity(struct srf08_data *data, return -EINVAL; for (i = 0; i < data->chip_info->num_sensitivity_avail; i++) - if (val && (val == data->chip_info->sensitivity_avail[i])) { + if (val == data->chip_info->sensitivity_avail[i]) { regval = i; break; } diff --git a/drivers/iio/proximity/sx9324.c b/drivers/iio/proximity/sx9324.c index 63fbcaa4cac8..edb5a2ce4e27 100644 --- a/drivers/iio/proximity/sx9324.c +++ b/drivers/iio/proximity/sx9324.c @@ -52,6 +52,16 @@ #define SX9324_REG_CLK_SPRD 0x15 #define SX9324_REG_AFE_CTRL0 0x20 +#define SX9324_REG_AFE_CTRL0_RINT_SHIFT 6 +#define SX9324_REG_AFE_CTRL0_RINT_MASK \ + GENMASK(SX9324_REG_AFE_CTRL0_RINT_SHIFT + 1, \ + SX9324_REG_AFE_CTRL0_RINT_SHIFT) +#define SX9324_REG_AFE_CTRL0_RINT_LOWEST 0x00 +#define SX9324_REG_AFE_CTRL0_CSIDLE_SHIFT 4 +#define SX9324_REG_AFE_CTRL0_CSIDLE_MASK \ + GENMASK(SX9324_REG_AFE_CTRL0_CSIDLE_SHIFT + 1, \ + SX9324_REG_AFE_CTRL0_CSIDLE_SHIFT) +#define SX9324_REG_AFE_CTRL0_RINT_LOWEST 0x00 #define SX9324_REG_AFE_CTRL1 0x21 #define SX9324_REG_AFE_CTRL2 0x22 #define SX9324_REG_AFE_CTRL3 0x23 @@ -72,7 +82,9 @@ #define SX9324_REG_AFE_CTRL8 0x2c #define SX9324_REG_AFE_CTRL8_RESERVED 0x10 #define SX9324_REG_AFE_CTRL8_RESFILTIN_4KOHM 0x02 +#define SX9324_REG_AFE_CTRL8_RESFILTIN_MASK GENMASK(3, 0) #define SX9324_REG_AFE_CTRL9 0x2d +#define SX9324_REG_AFE_CTRL9_AGAIN_MASK GENMASK(3, 0) #define SX9324_REG_AFE_CTRL9_AGAIN_1 0x08 #define SX9324_REG_PROX_CTRL0 0x30 @@ -93,7 +105,7 @@ #define SX9324_REG_PROX_CTRL4_AVGNEGFILT_MASK GENMASK(5, 3) #define SX9324_REG_PROX_CTRL4_AVGNEG_FILT_2 0x08 #define SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK GENMASK(2, 0) -#define SX9324_REG_PROX_CTRL3_AVGPOS_FILT_256 0x04 +#define SX9324_REG_PROX_CTRL4_AVGPOS_FILT_256 0x04 #define SX9324_REG_PROX_CTRL5 0x35 #define SX9324_REG_PROX_CTRL5_HYST_MASK GENMASK(5, 4) #define SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK GENMASK(3, 2) @@ -782,7 +794,7 @@ static const struct sx_common_reg_default sx9324_default_regs[] = { */ { SX9324_REG_GNRL_CTRL1, SX9324_REG_GNRL_CTRL1_PAUSECTRL }, - { SX9324_REG_AFE_CTRL0, 0x00 }, + { SX9324_REG_AFE_CTRL0, SX9324_REG_AFE_CTRL0_RINT_LOWEST }, { SX9324_REG_AFE_CTRL3, 0x00 }, { SX9324_REG_AFE_CTRL4, SX9324_REG_AFE_CTRL4_FREQ_83_33HZ | SX9324_REG_AFE_CTRL4_RES_100 }, @@ -810,7 +822,7 @@ static const struct sx_common_reg_default sx9324_default_regs[] = { { SX9324_REG_PROX_CTRL3, SX9324_REG_PROX_CTRL3_AVGDEB_2SAMPLES | SX9324_REG_PROX_CTRL3_AVGPOS_THRESH_16K }, { SX9324_REG_PROX_CTRL4, SX9324_REG_PROX_CTRL4_AVGNEG_FILT_2 | - SX9324_REG_PROX_CTRL3_AVGPOS_FILT_256 }, + SX9324_REG_PROX_CTRL4_AVGPOS_FILT_256 }, { SX9324_REG_PROX_CTRL5, 0x00 }, { SX9324_REG_PROX_CTRL6, SX9324_REG_PROX_CTRL6_PROXTHRESH_32 }, { SX9324_REG_PROX_CTRL7, SX9324_REG_PROX_CTRL6_PROXTHRESH_32 }, @@ -863,6 +875,10 @@ static const struct sx_common_reg_default * sx9324_get_default_reg(struct device *dev, int idx, struct sx_common_reg_default *reg_def) { + static const char * const sx9324_rints[] = { "lowest", "low", "high", + "highest" }; + static const char * const sx9324_csidle[] = { "hi-z", "hi-z", "gnd", + "vdd" }; #define SX9324_PIN_DEF "semtech,ph0-pin" #define SX9324_RESOLUTION_DEF "semtech,ph01-resolution" #define SX9324_PROXRAW_DEF "semtech,ph01-proxraw-strength" @@ -870,6 +886,7 @@ sx9324_get_default_reg(struct device *dev, int idx, char prop[] = SX9324_PROXRAW_DEF; u32 start = 0, raw = 0, pos = 0; int ret, count, ph, pin; + const char *res; memcpy(reg_def, &sx9324_default_regs[idx], sizeof(*reg_def)); switch (reg_def->reg) { @@ -893,6 +910,26 @@ sx9324_get_default_reg(struct device *dev, int idx, SX9324_REG_AFE_PH0_PIN_MASK(pin); reg_def->def = raw; break; + case SX9324_REG_AFE_CTRL0: + ret = device_property_read_string(dev, + "semtech,cs-idle-sleep", &res); + if (!ret) + ret = match_string(sx9324_csidle, ARRAY_SIZE(sx9324_csidle), res); + if (ret >= 0) { + reg_def->def &= ~SX9324_REG_AFE_CTRL0_CSIDLE_MASK; + reg_def->def |= ret << SX9324_REG_AFE_CTRL0_CSIDLE_SHIFT; + } + + ret = device_property_read_string(dev, + "semtech,int-comp-resistor", &res); + if (ret) + break; + ret = match_string(sx9324_rints, ARRAY_SIZE(sx9324_rints), res); + if (ret < 0) + break; + reg_def->def &= ~SX9324_REG_AFE_CTRL0_RINT_MASK; + reg_def->def |= ret << SX9324_REG_AFE_CTRL0_RINT_SHIFT; + break; case SX9324_REG_AFE_CTRL4: case SX9324_REG_AFE_CTRL7: if (reg_def->reg == SX9324_REG_AFE_CTRL4) @@ -912,6 +949,39 @@ sx9324_get_default_reg(struct device *dev, int idx, reg_def->def |= FIELD_PREP(SX9324_REG_AFE_CTRL4_RESOLUTION_MASK, raw); break; + case SX9324_REG_AFE_CTRL8: + ret = device_property_read_u32(dev, + "semtech,input-precharge-resistor-ohms", + &raw); + if (ret) + break; + + reg_def->def &= ~SX9324_REG_AFE_CTRL8_RESFILTIN_MASK; + reg_def->def |= FIELD_PREP(SX9324_REG_AFE_CTRL8_RESFILTIN_MASK, + raw / 2000); + break; + + case SX9324_REG_AFE_CTRL9: + ret = device_property_read_u32(dev, + "semtech,input-analog-gain", &raw); + if (ret) + break; + /* + * The analog gain has the following setting: + * +---------+----------------+----------------+ + * | dt(raw) | physical value | register value | + * +---------+----------------+----------------+ + * | 0 | x1.247 | 6 | + * | 1 | x1 | 8 | + * | 2 | x0.768 | 11 | + * | 3 | x0.552 | 15 | + * +---------+----------------+----------------+ + */ + reg_def->def &= ~SX9324_REG_AFE_CTRL9_AGAIN_MASK; + reg_def->def |= FIELD_PREP(SX9324_REG_AFE_CTRL9_AGAIN_MASK, + 6 + raw * (raw + 3) / 2); + break; + case SX9324_REG_ADV_CTRL5: ret = device_property_read_u32(dev, "semtech,startup-sensor", &start); diff --git a/drivers/iio/proximity/sx9360.c b/drivers/iio/proximity/sx9360.c index 3ebb30c8a4f6..d9a12e6be6ca 100644 --- a/drivers/iio/proximity/sx9360.c +++ b/drivers/iio/proximity/sx9360.c @@ -51,6 +51,8 @@ #define SX9360_REG_GNRL_REG_2_FREQ(_r) (SX9360_FOSC_HZ / ((_r) * 8192)) #define SX9360_REG_AFE_CTRL1 0x21 +#define SX9360_REG_AFE_CTRL1_RESFILTIN_MASK GENMASK(3, 0) +#define SX9360_REG_AFE_CTRL1_RESFILTIN_0OHMS 0 #define SX9360_REG_AFE_PARAM0_PHR 0x22 #define SX9360_REG_AFE_PARAM1_PHR 0x23 #define SX9360_REG_AFE_PARAM0_PHM 0x24 @@ -671,7 +673,7 @@ static const struct sx_common_reg_default sx9360_default_regs[] = { { SX9360_REG_GNRL_CTRL1, 0x00 }, { SX9360_REG_GNRL_CTRL2, SX9360_REG_GNRL_CTRL2_PERIOD_102MS }, - { SX9360_REG_AFE_CTRL1, 0x00 }, + { SX9360_REG_AFE_CTRL1, SX9360_REG_AFE_CTRL1_RESFILTIN_0OHMS }, { SX9360_REG_AFE_PARAM0_PHR, SX9360_REG_AFE_PARAM0_RSVD | SX9360_REG_AFE_PARAM0_RESOLUTION_128 }, { SX9360_REG_AFE_PARAM1_PHR, SX9360_REG_AFE_PARAM1_AGAIN_PHM_6PF | @@ -722,6 +724,17 @@ sx9360_get_default_reg(struct device *dev, int idx, memcpy(reg_def, &sx9360_default_regs[idx], sizeof(*reg_def)); switch (reg_def->reg) { + case SX9360_REG_AFE_CTRL1: + ret = device_property_read_u32(dev, + "semtech,input-precharge-resistor-ohms", + &raw); + if (ret) + break; + + reg_def->def &= ~SX9360_REG_AFE_CTRL1_RESFILTIN_MASK; + reg_def->def |= FIELD_PREP(SX9360_REG_AFE_CTRL1_RESFILTIN_MASK, + raw / 2000); + break; case SX9360_REG_AFE_PARAM0_PHR: case SX9360_REG_AFE_PARAM0_PHM: ret = device_property_read_u32(dev, "semtech,resolution", &raw); diff --git a/drivers/iio/proximity/sx_common.c b/drivers/iio/proximity/sx_common.c index 8ad814d96b7e..d70a6b4f0bf8 100644 --- a/drivers/iio/proximity/sx_common.c +++ b/drivers/iio/proximity/sx_common.c @@ -5,7 +5,6 @@ * Common part of most Semtech SAR sensor. */ -#include #include #include #include @@ -434,7 +433,7 @@ static void sx_common_regulator_disable(void *_data) #define SX_COMMON_SOFT_RESET 0xde -static int sx_common_init_device(struct iio_dev *indio_dev) +static int sx_common_init_device(struct device *dev, struct iio_dev *indio_dev) { struct sx_common_data *data = iio_priv(indio_dev); struct sx_common_reg_default tmp; @@ -456,8 +455,7 @@ static int sx_common_init_device(struct iio_dev *indio_dev) /* Program defaults from constant or BIOS. */ for (i = 0; i < data->chip_info->num_default_regs; i++) { - initval = data->chip_info->ops.get_default_reg(&indio_dev->dev, - i, &tmp); + initval = data->chip_info->ops.get_default_reg(dev, i, &tmp); ret = regmap_write(data->regmap, initval->reg, initval->def); if (ret) return ret; @@ -520,8 +518,6 @@ int sx_common_probe(struct i2c_client *client, if (ret) return dev_err_probe(dev, ret, "error reading WHOAMI\n"); - ACPI_COMPANION_SET(&indio_dev->dev, ACPI_COMPANION(dev)); - indio_dev->dev.of_node = client->dev.of_node; indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->channels = data->chip_info->iio_channels; @@ -530,7 +526,7 @@ int sx_common_probe(struct i2c_client *client, i2c_set_clientdata(client, indio_dev); - ret = sx_common_init_device(indio_dev); + ret = sx_common_init_device(dev, indio_dev); if (ret) return dev_err_probe(dev, ret, "Unable to initialize sensor\n"); diff --git a/drivers/iio/proximity/vcnl3020.c b/drivers/iio/proximity/vcnl3020.c index ff83638db16f..cbc8400c773c 100644 --- a/drivers/iio/proximity/vcnl3020.c +++ b/drivers/iio/proximity/vcnl3020.c @@ -71,14 +71,14 @@ static const int vcnl3020_prox_sampling_frequency[][2] = { * @dev: vcnl3020 device. * @rev: revision id. * @lock: lock for protecting access to device hardware registers. - * @buf: DMA safe __be16 buffer. + * @buf: __be16 buffer. */ struct vcnl3020_data { struct regmap *regmap; struct device *dev; u8 rev; struct mutex lock; - __be16 buf ____cacheline_aligned; + __be16 buf; }; /** diff --git a/drivers/iio/proximity/vl53l0x-i2c.c b/drivers/iio/proximity/vl53l0x-i2c.c index a284b20529fb..c7c4d33d340f 100644 --- a/drivers/iio/proximity/vl53l0x-i2c.c +++ b/drivers/iio/proximity/vl53l0x-i2c.c @@ -15,7 +15,9 @@ */ #include +#include #include +#include #include #include @@ -42,6 +44,8 @@ struct vl53l0x_data { struct i2c_client *client; struct completion completion; + struct regulator *vdd_supply; + struct gpio_desc *reset_gpio; }; static irqreturn_t vl53l0x_handle_irq(int irq, void *priv) @@ -57,11 +61,15 @@ static irqreturn_t vl53l0x_handle_irq(int irq, void *priv) static int vl53l0x_configure_irq(struct i2c_client *client, struct iio_dev *indio_dev) { + int irq_flags = irq_get_trigger_type(client->irq); struct vl53l0x_data *data = iio_priv(indio_dev); int ret; + if (!irq_flags) + irq_flags = IRQF_TRIGGER_FALLING; + ret = devm_request_irq(&client->dev, client->irq, vl53l0x_handle_irq, - IRQF_TRIGGER_FALLING, indio_dev->name, indio_dev); + irq_flags, indio_dev->name, indio_dev); if (ret) { dev_err(&client->dev, "devm_request_irq error: %d\n", ret); return ret; @@ -186,10 +194,35 @@ static const struct iio_info vl53l0x_info = { .read_raw = vl53l0x_read_raw, }; +static void vl53l0x_power_off(void *_data) +{ + struct vl53l0x_data *data = _data; + + gpiod_set_value_cansleep(data->reset_gpio, 1); + + regulator_disable(data->vdd_supply); +} + +static int vl53l0x_power_on(struct vl53l0x_data *data) +{ + int ret; + + ret = regulator_enable(data->vdd_supply); + if (ret) + return ret; + + gpiod_set_value_cansleep(data->reset_gpio, 0); + + usleep_range(3200, 5000); + + return 0; +} + static int vl53l0x_probe(struct i2c_client *client) { struct vl53l0x_data *data; struct iio_dev *indio_dev; + int error; indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); if (!indio_dev) @@ -204,6 +237,26 @@ static int vl53l0x_probe(struct i2c_client *client) I2C_FUNC_SMBUS_BYTE_DATA)) return -EOPNOTSUPP; + data->vdd_supply = devm_regulator_get(&client->dev, "vdd"); + if (IS_ERR(data->vdd_supply)) + return dev_err_probe(&client->dev, PTR_ERR(data->vdd_supply), + "Unable to get VDD regulator\n"); + + data->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(data->reset_gpio)) + return dev_err_probe(&client->dev, PTR_ERR(data->reset_gpio), + "Cannot get reset GPIO\n"); + + error = vl53l0x_power_on(data); + if (error) + return dev_err_probe(&client->dev, error, + "Failed to power on the chip\n"); + + error = devm_add_action_or_reset(&client->dev, vl53l0x_power_off, data); + if (error) + return dev_err_probe(&client->dev, error, + "Failed to install poweroff action\n"); + indio_dev->name = "vl53l0x"; indio_dev->info = &vl53l0x_info; indio_dev->channels = vl53l0x_channels; diff --git a/drivers/iio/resolver/ad2s1200.c b/drivers/iio/resolver/ad2s1200.c index 9746bd935628..9d95241bdf8f 100644 --- a/drivers/iio/resolver/ad2s1200.c +++ b/drivers/iio/resolver/ad2s1200.c @@ -41,7 +41,7 @@ struct ad2s1200_state { struct spi_device *sdev; struct gpio_desc *sample; struct gpio_desc *rdvel; - __be16 rx ____cacheline_aligned; + __be16 rx __aligned(IIO_DMA_MINALIGN); }; static int ad2s1200_read_raw(struct iio_dev *indio_dev, diff --git a/drivers/iio/resolver/ad2s90.c b/drivers/iio/resolver/ad2s90.c index d6a91f137e13..be6836e55376 100644 --- a/drivers/iio/resolver/ad2s90.c +++ b/drivers/iio/resolver/ad2s90.c @@ -24,7 +24,7 @@ struct ad2s90_state { struct mutex lock; /* lock to protect rx buffer */ struct spi_device *sdev; - u8 rx[2] ____cacheline_aligned; + u8 rx[2] __aligned(IIO_DMA_MINALIGN); }; static int ad2s90_read_raw(struct iio_dev *indio_dev, diff --git a/drivers/iio/temperature/ltc2983.c b/drivers/iio/temperature/ltc2983.c index 4fc654275155..b652d2b39bcf 100644 --- a/drivers/iio/temperature/ltc2983.c +++ b/drivers/iio/temperature/ltc2983.c @@ -204,11 +204,11 @@ struct ltc2983_data { u8 num_channels; u8 iio_channels; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. * Holds the converted temperature */ - __be32 temp ____cacheline_aligned; + __be32 temp __aligned(IIO_DMA_MINALIGN); }; struct ltc2983_sensor { @@ -1534,7 +1534,7 @@ static int ltc2983_probe(struct spi_device *spi) return devm_iio_device_register(&spi->dev, indio_dev); } -static int __maybe_unused ltc2983_resume(struct device *dev) +static int ltc2983_resume(struct device *dev) { struct ltc2983_data *st = spi_get_drvdata(to_spi_device(dev)); int dummy; @@ -1545,14 +1545,15 @@ static int __maybe_unused ltc2983_resume(struct device *dev) return ltc2983_setup(st, false); } -static int __maybe_unused ltc2983_suspend(struct device *dev) +static int ltc2983_suspend(struct device *dev) { struct ltc2983_data *st = spi_get_drvdata(to_spi_device(dev)); return regmap_write(st->regmap, LTC2983_STATUS_REG, LTC2983_SLEEP); } -static SIMPLE_DEV_PM_OPS(ltc2983_pm_ops, ltc2983_suspend, ltc2983_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(ltc2983_pm_ops, ltc2983_suspend, + ltc2983_resume); static const struct spi_device_id ltc2983_id_table[] = { { "ltc2983" }, @@ -1570,7 +1571,7 @@ static struct spi_driver ltc2983_driver = { .driver = { .name = "ltc2983", .of_match_table = ltc2983_of_match, - .pm = <c2983_pm_ops, + .pm = pm_sleep_ptr(<c2983_pm_ops), }, .probe = ltc2983_probe, .id_table = ltc2983_id_table, diff --git a/drivers/iio/temperature/max31865.c b/drivers/iio/temperature/max31865.c index e3bb78184c6e..29e23652ba5a 100644 --- a/drivers/iio/temperature/max31865.c +++ b/drivers/iio/temperature/max31865.c @@ -55,7 +55,7 @@ struct max31865_data { struct mutex lock; bool filter_50hz; bool three_wire; - u8 buf[2] ____cacheline_aligned; + u8 buf[2] __aligned(IIO_DMA_MINALIGN); }; static int max31865_read(struct max31865_data *data, u8 reg, diff --git a/drivers/iio/temperature/maxim_thermocouple.c b/drivers/iio/temperature/maxim_thermocouple.c index 98c41cddc6f0..c28a7a6dea5f 100644 --- a/drivers/iio/temperature/maxim_thermocouple.c +++ b/drivers/iio/temperature/maxim_thermocouple.c @@ -122,7 +122,7 @@ struct maxim_thermocouple_data { struct spi_device *spi; const struct maxim_thermocouple_chip *chip; - u8 buffer[16] ____cacheline_aligned; + u8 buffer[16] __aligned(IIO_DMA_MINALIGN); char tc_type; }; diff --git a/drivers/iio/test/Kconfig b/drivers/iio/test/Kconfig index 4c66c3f18c34..0b6e4e278a2f 100644 --- a/drivers/iio/test/Kconfig +++ b/drivers/iio/test/Kconfig @@ -5,15 +5,25 @@ # Keep in alphabetical order config IIO_RESCALE_KUNIT_TEST - bool "Test IIO rescale conversion functions" - depends on KUNIT=y && IIO_RESCALE=y + tristate "Test IIO rescale conversion functions" if !KUNIT_ALL_TESTS + depends on KUNIT && IIO_RESCALE default KUNIT_ALL_TESTS help - If you want to run tests on the iio-rescale code say Y here. + Build unit tests for the iio-rescale code. - This takes advantage of ARCH=um to run tests and should be used by - developers to tests their changes to the rescaling logic. + For more information on KUnit and unit tests in general, please refer + to the KUnit documentation in Documentation/dev-tools/kunit/. -config IIO_TEST_FORMAT - bool "Test IIO formatting functions" - depends on KUNIT=y + If unsure, say N. + +config IIO_FORMAT_KUNIT_TEST + tristate "Test IIO formatting functions" if !KUNIT_ALL_TESTS + depends on KUNIT + default KUNIT_ALL_TESTS + help + build unit tests for the IIO formatting functions. + + For more information on KUnit and unit tests in general, please refer + to the KUnit documentation in Documentation/dev-tools/kunit/. + + If unsure, say N. diff --git a/drivers/iio/test/Makefile b/drivers/iio/test/Makefile index 880360f8d02c..d76eaf36da82 100644 --- a/drivers/iio/test/Makefile +++ b/drivers/iio/test/Makefile @@ -5,5 +5,5 @@ # Keep in alphabetical order obj-$(CONFIG_IIO_RESCALE_KUNIT_TEST) += iio-test-rescale.o -obj-$(CONFIG_IIO_TEST_FORMAT) += iio-test-format.o +obj-$(CONFIG_IIO_FORMAT_KUNIT_TEST) += iio-test-format.o CFLAGS_iio-test-format.o += $(DISABLE_STRUCTLEAK_PLUGIN) diff --git a/drivers/iio/test/iio-test-format.c b/drivers/iio/test/iio-test-format.c index 237321436b83..fc67e6b73df7 100644 --- a/drivers/iio/test/iio-test-format.c +++ b/drivers/iio/test/iio-test-format.c @@ -265,3 +265,7 @@ static struct kunit_suite iio_format_test_suite = { .test_cases = iio_format_test_cases, }; kunit_test_suite(iio_format_test_suite); + +MODULE_AUTHOR("Lars-Peter Clausen "); +MODULE_DESCRIPTION("Test IIO formatting functions"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/iio/test/iio-test-rescale.c b/drivers/iio/test/iio-test-rescale.c index 0b6699bfd553..cc782ccff880 100644 --- a/drivers/iio/test/iio-test-rescale.c +++ b/drivers/iio/test/iio-test-rescale.c @@ -708,3 +708,8 @@ static struct kunit_suite iio_rescale_test_suite = { .test_cases = iio_rescale_test_cases, }; kunit_test_suite(iio_rescale_test_suite); + +MODULE_AUTHOR("Liam Beguin "); +MODULE_DESCRIPTION("Test IIO rescale conversion functions"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(IIO_RESCALE); diff --git a/drivers/iio/trigger/stm32-lptimer-trigger.c b/drivers/iio/trigger/stm32-lptimer-trigger.c index 98cdc7e47f3d..2e447a3f047d 100644 --- a/drivers/iio/trigger/stm32-lptimer-trigger.c +++ b/drivers/iio/trigger/stm32-lptimer-trigger.c @@ -11,8 +11,10 @@ #include #include +#include #include #include +#include /* List Low-Power Timer triggers */ static const char * const stm32_lptim_triggers[] = { @@ -77,7 +79,7 @@ static int stm32_lptim_trigger_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; - if (of_property_read_u32(pdev->dev.of_node, "reg", &index)) + if (device_property_read_u32(&pdev->dev, "reg", &index)) return -EINVAL; if (index >= ARRAY_SIZE(stm32_lptim_triggers)) diff --git a/drivers/interconnect/bulk.c b/drivers/interconnect/bulk.c index 448cc536aa79..8b1d8a412464 100644 --- a/drivers/interconnect/bulk.c +++ b/drivers/interconnect/bulk.c @@ -115,3 +115,45 @@ void icc_bulk_disable(int num_paths, const struct icc_bulk_data *paths) icc_disable(paths[num_paths].path); } EXPORT_SYMBOL_GPL(icc_bulk_disable); + +struct icc_bulk_devres { + struct icc_bulk_data *paths; + int num_paths; +}; + +static void devm_icc_bulk_release(struct device *dev, void *res) +{ + struct icc_bulk_devres *devres = res; + + icc_bulk_put(devres->num_paths, devres->paths); +} + +/** + * devm_of_icc_bulk_get() - resource managed of_icc_bulk_get + * @dev: the device requesting the path + * @num_paths: the number of icc_bulk_data + * @paths: the table with the paths we want to get + * + * Returns 0 on success or negative errno otherwise. + */ +int devm_of_icc_bulk_get(struct device *dev, int num_paths, struct icc_bulk_data *paths) +{ + struct icc_bulk_devres *devres; + int ret; + + devres = devres_alloc(devm_icc_bulk_release, sizeof(*devres), GFP_KERNEL); + if (!devres) + return -ENOMEM; + + ret = of_icc_bulk_get(dev, num_paths, paths); + if (!ret) { + devres->paths = paths; + devres->num_paths = num_paths; + devres_add(dev, devres); + } else { + devres_free(devres); + } + + return ret; +} +EXPORT_SYMBOL_GPL(devm_of_icc_bulk_get); diff --git a/drivers/interconnect/imx/Kconfig b/drivers/interconnect/imx/Kconfig index be2928362bb7..c772552431f5 100644 --- a/drivers/interconnect/imx/Kconfig +++ b/drivers/interconnect/imx/Kconfig @@ -15,3 +15,7 @@ config INTERCONNECT_IMX8MN config INTERCONNECT_IMX8MQ tristate "i.MX8MQ interconnect driver" depends on INTERCONNECT_IMX + +config INTERCONNECT_IMX8MP + tristate "i.MX8MP interconnect driver" + depends on INTERCONNECT_IMX diff --git a/drivers/interconnect/imx/Makefile b/drivers/interconnect/imx/Makefile index 21fd5233754f..16d256cdeab4 100644 --- a/drivers/interconnect/imx/Makefile +++ b/drivers/interconnect/imx/Makefile @@ -2,8 +2,10 @@ imx-interconnect-objs := imx.o imx8mm-interconnect-objs := imx8mm.o imx8mq-interconnect-objs := imx8mq.o imx8mn-interconnect-objs := imx8mn.o +imx8mp-interconnect-objs := imx8mp.o obj-$(CONFIG_INTERCONNECT_IMX) += imx-interconnect.o obj-$(CONFIG_INTERCONNECT_IMX8MM) += imx8mm-interconnect.o obj-$(CONFIG_INTERCONNECT_IMX8MQ) += imx8mq-interconnect.o obj-$(CONFIG_INTERCONNECT_IMX8MN) += imx8mn-interconnect.o +obj-$(CONFIG_INTERCONNECT_IMX8MP) += imx8mp-interconnect.o diff --git a/drivers/interconnect/imx/imx.c b/drivers/interconnect/imx/imx.c index 249ca25d1d55..48ffd59953bf 100644 --- a/drivers/interconnect/imx/imx.c +++ b/drivers/interconnect/imx/imx.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -21,8 +22,10 @@ /* private icc_node data */ struct imx_icc_node { const struct imx_icc_node_desc *desc; + const struct imx_icc_noc_setting *setting; struct device *qos_dev; struct dev_pm_qos_request qos_req; + struct imx_icc_provider *imx_provider; }; static int imx_icc_get_bw(struct icc_node *node, u32 *avg, u32 *peak) @@ -37,8 +40,30 @@ static int imx_icc_node_set(struct icc_node *node) { struct device *dev = node->provider->dev; struct imx_icc_node *node_data = node->data; + void __iomem *base; + u32 prio; u64 freq; + if (node_data->setting && node->peak_bw) { + base = node_data->setting->reg + node_data->imx_provider->noc_base; + if (node_data->setting->mode == IMX_NOC_MODE_FIXED) { + prio = node_data->setting->prio_level; + prio = PRIORITY_COMP_MARK | (prio << 8) | prio; + writel(prio, base + IMX_NOC_PRIO_REG); + writel(node_data->setting->mode, base + IMX_NOC_MODE_REG); + writel(node_data->setting->ext_control, base + IMX_NOC_EXT_CTL_REG); + dev_dbg(dev, "%s: mode: 0x%x, prio: 0x%x, ext_control: 0x%x\n", + node_data->desc->name, node_data->setting->mode, prio, + node_data->setting->ext_control); + } else if (node_data->setting->mode == IMX_NOC_MODE_UNCONFIGURED) { + dev_dbg(dev, "%s: mode not unconfigured\n", node_data->desc->name); + } else { + dev_info(dev, "%s: mode: %d not supported\n", + node_data->desc->name, node_data->setting->mode); + return -EOPNOTSUPP; + } + } + if (!node_data->qos_dev) return 0; @@ -61,6 +86,12 @@ static int imx_icc_node_set(struct icc_node *node) static int imx_icc_set(struct icc_node *src, struct icc_node *dst) { + int ret; + + ret = imx_icc_node_set(src); + if (ret) + return ret; + return imx_icc_node_set(dst); } @@ -128,9 +159,11 @@ static int imx_icc_node_init_qos(struct icc_provider *provider, DEV_PM_QOS_MIN_FREQUENCY, 0); } -static struct icc_node *imx_icc_node_add(struct icc_provider *provider, - const struct imx_icc_node_desc *node_desc) +static struct icc_node *imx_icc_node_add(struct imx_icc_provider *imx_provider, + const struct imx_icc_node_desc *node_desc, + const struct imx_icc_noc_setting *setting) { + struct icc_provider *provider = &imx_provider->provider; struct device *dev = provider->dev; struct imx_icc_node *node_data; struct icc_node *node; @@ -157,6 +190,8 @@ static struct icc_node *imx_icc_node_add(struct icc_provider *provider, node->name = node_desc->name; node->data = node_data; node_data->desc = node_desc; + node_data->setting = setting; + node_data->imx_provider = imx_provider; icc_node_add(node, provider); if (node_desc->adj) { @@ -178,10 +213,12 @@ static void imx_icc_unregister_nodes(struct icc_provider *provider) imx_icc_node_destroy(node); } -static int imx_icc_register_nodes(struct icc_provider *provider, +static int imx_icc_register_nodes(struct imx_icc_provider *imx_provider, const struct imx_icc_node_desc *descs, - int count) + int count, + const struct imx_icc_noc_setting *settings) { + struct icc_provider *provider = &imx_provider->provider; struct icc_onecell_data *provider_data = provider->data; int ret; int i; @@ -191,7 +228,8 @@ static int imx_icc_register_nodes(struct icc_provider *provider, const struct imx_icc_node_desc *node_desc = &descs[i]; size_t j; - node = imx_icc_node_add(provider, node_desc); + node = imx_icc_node_add(imx_provider, node_desc, + settings ? &settings[node_desc->id] : NULL); if (IS_ERR(node)) { ret = dev_err_probe(provider->dev, PTR_ERR(node), "failed to add %s\n", node_desc->name); @@ -229,32 +267,44 @@ static int get_max_node_id(struct imx_icc_node_desc *nodes, int nodes_count) } int imx_icc_register(struct platform_device *pdev, - struct imx_icc_node_desc *nodes, int nodes_count) + struct imx_icc_node_desc *nodes, int nodes_count, + struct imx_icc_noc_setting *settings) { struct device *dev = &pdev->dev; struct icc_onecell_data *data; + struct imx_icc_provider *imx_provider; struct icc_provider *provider; - int max_node_id; + int num_nodes; int ret; /* icc_onecell_data is indexed by node_id, unlike nodes param */ - max_node_id = get_max_node_id(nodes, nodes_count); - data = devm_kzalloc(dev, struct_size(data, nodes, max_node_id), + num_nodes = get_max_node_id(nodes, nodes_count) + 1; + data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes), GFP_KERNEL); if (!data) return -ENOMEM; - data->num_nodes = max_node_id; + data->num_nodes = num_nodes; - provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL); - if (!provider) + imx_provider = devm_kzalloc(dev, sizeof(*imx_provider), GFP_KERNEL); + if (!imx_provider) return -ENOMEM; + provider = &imx_provider->provider; provider->set = imx_icc_set; provider->get_bw = imx_icc_get_bw; provider->aggregate = icc_std_aggregate; provider->xlate = of_icc_xlate_onecell; provider->data = data; provider->dev = dev->parent; - platform_set_drvdata(pdev, provider); + platform_set_drvdata(pdev, imx_provider); + + if (settings) { + imx_provider->noc_base = devm_of_iomap(dev, provider->dev->of_node, 0, NULL); + if (IS_ERR(imx_provider->noc_base)) { + ret = PTR_ERR(imx_provider->noc_base); + dev_err(dev, "Error mapping NoC: %d\n", ret); + return ret; + } + } ret = icc_provider_add(provider); if (ret) { @@ -262,7 +312,7 @@ int imx_icc_register(struct platform_device *pdev, return ret; } - ret = imx_icc_register_nodes(provider, nodes, nodes_count); + ret = imx_icc_register_nodes(imx_provider, nodes, nodes_count, settings); if (ret) goto provider_del; @@ -276,11 +326,11 @@ EXPORT_SYMBOL_GPL(imx_icc_register); int imx_icc_unregister(struct platform_device *pdev) { - struct icc_provider *provider = platform_get_drvdata(pdev); + struct imx_icc_provider *imx_provider = platform_get_drvdata(pdev); - imx_icc_unregister_nodes(provider); + imx_icc_unregister_nodes(&imx_provider->provider); - return icc_provider_del(provider); + return icc_provider_del(&imx_provider->provider); } EXPORT_SYMBOL_GPL(imx_icc_unregister); diff --git a/drivers/interconnect/imx/imx.h b/drivers/interconnect/imx/imx.h index 75da51076c68..e0a2ee173ecd 100644 --- a/drivers/interconnect/imx/imx.h +++ b/drivers/interconnect/imx/imx.h @@ -10,10 +10,42 @@ #ifndef __DRIVERS_INTERCONNECT_IMX_H #define __DRIVERS_INTERCONNECT_IMX_H +#include #include #define IMX_ICC_MAX_LINKS 4 +/* + * High throughput priority level in Regulator mode + * Read Priority in Fixed/Limiter mode + */ +#define PRIORITY0_SHIFT 0 +/* + * Low throughput priority level in Regulator mode + * Write Priority in Fixed/Limiter mode + */ +#define PRIORITY1_SHIFT 8 +#define PRIORITY_MASK 0x7 + +#define PRIORITY_COMP_MARK BIT(31) /* Must set */ + +#define IMX_NOC_MODE_FIXED 0 +#define IMX_NOC_MODE_LIMITER 1 +#define IMX_NOC_MODE_BYPASS 2 +#define IMX_NOC_MODE_REGULATOR 3 +#define IMX_NOC_MODE_UNCONFIGURED 0xFF + +#define IMX_NOC_PRIO_REG 0x8 +#define IMX_NOC_MODE_REG 0xC +#define IMX_NOC_BANDWIDTH_REG 0x10 +#define IMX_NOC_SATURATION 0x14 +#define IMX_NOC_EXT_CTL_REG 0x18 + +struct imx_icc_provider { + void __iomem *noc_base; + struct icc_provider provider; +}; + /* * struct imx_icc_node_adj - Describe a dynamic adjustable node */ @@ -38,6 +70,20 @@ struct imx_icc_node_desc { const struct imx_icc_node_adj_desc *adj; }; +/* + * struct imx_icc_noc_setting - Describe an interconnect node setting + * @reg: register offset inside the NoC + * @prio_level: priority level + * @mode: functional mode + * @ext_control: external input control + */ +struct imx_icc_noc_setting { + u32 reg; + u32 prio_level; + u32 mode; + u32 ext_control; +}; + #define DEFINE_BUS_INTERCONNECT(_name, _id, _adj, ...) \ { \ .id = _id, \ @@ -55,7 +101,8 @@ struct imx_icc_node_desc { int imx_icc_register(struct platform_device *pdev, struct imx_icc_node_desc *nodes, - int nodes_count); + int nodes_count, + struct imx_icc_noc_setting *noc_settings); int imx_icc_unregister(struct platform_device *pdev); #endif /* __DRIVERS_INTERCONNECT_IMX_H */ diff --git a/drivers/interconnect/imx/imx8mm.c b/drivers/interconnect/imx/imx8mm.c index 1083490bb391..ae797412db96 100644 --- a/drivers/interconnect/imx/imx8mm.c +++ b/drivers/interconnect/imx/imx8mm.c @@ -83,7 +83,7 @@ static struct imx_icc_node_desc nodes[] = { static int imx8mm_icc_probe(struct platform_device *pdev) { - return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes)); + return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes), NULL); } static int imx8mm_icc_remove(struct platform_device *pdev) diff --git a/drivers/interconnect/imx/imx8mn.c b/drivers/interconnect/imx/imx8mn.c index ad97e55fd4e5..1ce94c5bdd8c 100644 --- a/drivers/interconnect/imx/imx8mn.c +++ b/drivers/interconnect/imx/imx8mn.c @@ -72,7 +72,7 @@ static struct imx_icc_node_desc nodes[] = { static int imx8mn_icc_probe(struct platform_device *pdev) { - return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes)); + return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes), NULL); } static int imx8mn_icc_remove(struct platform_device *pdev) diff --git a/drivers/interconnect/imx/imx8mp.c b/drivers/interconnect/imx/imx8mp.c new file mode 100644 index 000000000000..5f1c83ed157b --- /dev/null +++ b/drivers/interconnect/imx/imx8mp.c @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Interconnect framework driver for i.MX8MP SoC + * + * Copyright 2022 NXP + * Peng Fan + */ + +#include +#include +#include +#include + +#include "imx.h" + +static const struct imx_icc_node_adj_desc imx8mp_noc_adj = { + .bw_mul = 1, + .bw_div = 16, + .main_noc = true, +}; + +static struct imx_icc_noc_setting noc_setting_nodes[] = { + [IMX8MP_ICM_MLMIX] = { + .reg = 0x180, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 3, + }, + [IMX8MP_ICM_DSP] = { + .reg = 0x200, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 3, + }, + [IMX8MP_ICM_SDMA2PER] = { + .reg = 0x280, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 4, + }, + [IMX8MP_ICM_SDMA2BURST] = { + .reg = 0x300, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 4, + }, + [IMX8MP_ICM_SDMA3PER] = { + .reg = 0x380, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 4, + }, + [IMX8MP_ICM_SDMA3BURST] = { + .reg = 0x400, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 4, + }, + [IMX8MP_ICM_EDMA] = { + .reg = 0x480, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 4, + }, + [IMX8MP_ICM_GPU3D] = { + .reg = 0x500, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 3, + }, + [IMX8MP_ICM_GPU2D] = { + .reg = 0x580, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 3, + }, + [IMX8MP_ICM_HRV] = { + .reg = 0x600, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 2, + .ext_control = 1, + }, + [IMX8MP_ICM_LCDIF_HDMI] = { + .reg = 0x680, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 2, + .ext_control = 1, + }, + [IMX8MP_ICM_HDCP] = { + .reg = 0x700, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 5, + }, + [IMX8MP_ICM_NOC_PCIE] = { + .reg = 0x780, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 3, + }, + [IMX8MP_ICM_USB1] = { + .reg = 0x800, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 3, + }, + [IMX8MP_ICM_USB2] = { + .reg = 0x880, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 3, + }, + [IMX8MP_ICM_PCIE] = { + .reg = 0x900, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 3, + }, + [IMX8MP_ICM_LCDIF_RD] = { + .reg = 0x980, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 2, + .ext_control = 1, + }, + [IMX8MP_ICM_LCDIF_WR] = { + .reg = 0xa00, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 2, + .ext_control = 1, + }, + [IMX8MP_ICM_ISI0] = { + .reg = 0xa80, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 2, + .ext_control = 1, + }, + [IMX8MP_ICM_ISI1] = { + .reg = 0xb00, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 2, + .ext_control = 1, + }, + [IMX8MP_ICM_ISI2] = { + .reg = 0xb80, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 2, + .ext_control = 1, + }, + [IMX8MP_ICM_ISP0] = { + .reg = 0xc00, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 7, + }, + [IMX8MP_ICM_ISP1] = { + .reg = 0xc80, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 7, + }, + [IMX8MP_ICM_DWE] = { + .reg = 0xd00, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 7, + }, + [IMX8MP_ICM_VPU_G1] = { + .reg = 0xd80, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 3, + }, + [IMX8MP_ICM_VPU_G2] = { + .reg = 0xe00, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 3, + }, + [IMX8MP_ICM_VPU_H1] = { + .reg = 0xe80, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 3, + }, + [IMX8MP_ICN_MEDIA] = { + .mode = IMX_NOC_MODE_UNCONFIGURED, + }, + [IMX8MP_ICN_VIDEO] = { + .mode = IMX_NOC_MODE_UNCONFIGURED, + }, + [IMX8MP_ICN_AUDIO] = { + .mode = IMX_NOC_MODE_UNCONFIGURED, + }, + [IMX8MP_ICN_HDMI] = { + .mode = IMX_NOC_MODE_UNCONFIGURED, + }, + [IMX8MP_ICN_GPU] = { + .mode = IMX_NOC_MODE_UNCONFIGURED, + }, + [IMX8MP_ICN_HSIO] = { + .mode = IMX_NOC_MODE_UNCONFIGURED, + }, +}; + +/* Describe bus masters, slaves and connections between them */ +static struct imx_icc_node_desc nodes[] = { + DEFINE_BUS_INTERCONNECT("NOC", IMX8MP_ICN_NOC, &imx8mp_noc_adj, + IMX8MP_ICS_DRAM, IMX8MP_ICN_MAIN), + + DEFINE_BUS_SLAVE("OCRAM", IMX8MP_ICS_OCRAM, NULL), + DEFINE_BUS_SLAVE("DRAM", IMX8MP_ICS_DRAM, NULL), + DEFINE_BUS_MASTER("A53", IMX8MP_ICM_A53, IMX8MP_ICN_NOC), + DEFINE_BUS_MASTER("SUPERMIX", IMX8MP_ICM_SUPERMIX, IMX8MP_ICN_NOC), + DEFINE_BUS_MASTER("GIC", IMX8MP_ICM_GIC, IMX8MP_ICN_NOC), + DEFINE_BUS_MASTER("MLMIX", IMX8MP_ICM_MLMIX, IMX8MP_ICN_NOC), + + DEFINE_BUS_INTERCONNECT("NOC_AUDIO", IMX8MP_ICN_AUDIO, NULL, IMX8MP_ICN_NOC), + DEFINE_BUS_MASTER("DSP", IMX8MP_ICM_DSP, IMX8MP_ICN_AUDIO), + DEFINE_BUS_MASTER("SDMA2PER", IMX8MP_ICM_SDMA2PER, IMX8MP_ICN_AUDIO), + DEFINE_BUS_MASTER("SDMA2BURST", IMX8MP_ICM_SDMA2BURST, IMX8MP_ICN_AUDIO), + DEFINE_BUS_MASTER("SDMA3PER", IMX8MP_ICM_SDMA3PER, IMX8MP_ICN_AUDIO), + DEFINE_BUS_MASTER("SDMA3BURST", IMX8MP_ICM_SDMA3BURST, IMX8MP_ICN_AUDIO), + DEFINE_BUS_MASTER("EDMA", IMX8MP_ICM_EDMA, IMX8MP_ICN_AUDIO), + + DEFINE_BUS_INTERCONNECT("NOC_GPU", IMX8MP_ICN_GPU, NULL, IMX8MP_ICN_NOC), + DEFINE_BUS_MASTER("GPU 2D", IMX8MP_ICM_GPU2D, IMX8MP_ICN_GPU), + DEFINE_BUS_MASTER("GPU 3D", IMX8MP_ICM_GPU3D, IMX8MP_ICN_GPU), + + DEFINE_BUS_INTERCONNECT("NOC_HDMI", IMX8MP_ICN_HDMI, NULL, IMX8MP_ICN_NOC), + DEFINE_BUS_MASTER("HRV", IMX8MP_ICM_HRV, IMX8MP_ICN_HDMI), + DEFINE_BUS_MASTER("LCDIF_HDMI", IMX8MP_ICM_LCDIF_HDMI, IMX8MP_ICN_HDMI), + DEFINE_BUS_MASTER("HDCP", IMX8MP_ICM_HDCP, IMX8MP_ICN_HDMI), + + DEFINE_BUS_INTERCONNECT("NOC_HSIO", IMX8MP_ICN_HSIO, NULL, IMX8MP_ICN_NOC), + DEFINE_BUS_MASTER("NOC_PCIE", IMX8MP_ICM_NOC_PCIE, IMX8MP_ICN_HSIO), + DEFINE_BUS_MASTER("USB1", IMX8MP_ICM_USB1, IMX8MP_ICN_HSIO), + DEFINE_BUS_MASTER("USB2", IMX8MP_ICM_USB2, IMX8MP_ICN_HSIO), + DEFINE_BUS_MASTER("PCIE", IMX8MP_ICM_PCIE, IMX8MP_ICN_HSIO), + + DEFINE_BUS_INTERCONNECT("NOC_MEDIA", IMX8MP_ICN_MEDIA, NULL, IMX8MP_ICN_NOC), + DEFINE_BUS_MASTER("LCDIF_RD", IMX8MP_ICM_LCDIF_RD, IMX8MP_ICN_MEDIA), + DEFINE_BUS_MASTER("LCDIF_WR", IMX8MP_ICM_LCDIF_WR, IMX8MP_ICN_MEDIA), + DEFINE_BUS_MASTER("ISI0", IMX8MP_ICM_ISI0, IMX8MP_ICN_MEDIA), + DEFINE_BUS_MASTER("ISI1", IMX8MP_ICM_ISI1, IMX8MP_ICN_MEDIA), + DEFINE_BUS_MASTER("ISI2", IMX8MP_ICM_ISI2, IMX8MP_ICN_MEDIA), + DEFINE_BUS_MASTER("ISP0", IMX8MP_ICM_ISP0, IMX8MP_ICN_MEDIA), + DEFINE_BUS_MASTER("ISP1", IMX8MP_ICM_ISP1, IMX8MP_ICN_MEDIA), + DEFINE_BUS_MASTER("DWE", IMX8MP_ICM_DWE, IMX8MP_ICN_MEDIA), + + DEFINE_BUS_INTERCONNECT("NOC_VIDEO", IMX8MP_ICN_VIDEO, NULL, IMX8MP_ICN_NOC), + DEFINE_BUS_MASTER("VPU G1", IMX8MP_ICM_VPU_G1, IMX8MP_ICN_VIDEO), + DEFINE_BUS_MASTER("VPU G2", IMX8MP_ICM_VPU_G2, IMX8MP_ICN_VIDEO), + DEFINE_BUS_MASTER("VPU H1", IMX8MP_ICM_VPU_H1, IMX8MP_ICN_VIDEO), + DEFINE_BUS_INTERCONNECT("PL301_MAIN", IMX8MP_ICN_MAIN, NULL, + IMX8MP_ICN_NOC, IMX8MP_ICS_OCRAM), +}; + +static int imx8mp_icc_probe(struct platform_device *pdev) +{ + return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes), noc_setting_nodes); +} + +static int imx8mp_icc_remove(struct platform_device *pdev) +{ + return imx_icc_unregister(pdev); +} + +static struct platform_driver imx8mp_icc_driver = { + .probe = imx8mp_icc_probe, + .remove = imx8mp_icc_remove, + .driver = { + .name = "imx8mp-interconnect", + }, +}; + +module_platform_driver(imx8mp_icc_driver); +MODULE_AUTHOR("Peng Fan "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:imx8mp-interconnect"); diff --git a/drivers/interconnect/imx/imx8mq.c b/drivers/interconnect/imx/imx8mq.c index d7768d3c6d8a..7f00a0511c6e 100644 --- a/drivers/interconnect/imx/imx8mq.c +++ b/drivers/interconnect/imx/imx8mq.c @@ -82,7 +82,7 @@ static struct imx_icc_node_desc nodes[] = { static int imx8mq_icc_probe(struct platform_device *pdev) { - return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes)); + return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes), NULL); } static int imx8mq_icc_remove(struct platform_device *pdev) diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig index 22adff5d7f53..25d5b4baf6f6 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -155,6 +155,15 @@ config INTERCONNECT_QCOM_SDX65 This is a driver for the Qualcomm Network-on-Chip on sdx65-based platforms. +config INTERCONNECT_QCOM_SM6350 + tristate "Qualcomm SM6350 interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on sm6350-based + platforms. + config INTERCONNECT_QCOM_SM8150 tristate "Qualcomm SM8150 interconnect driver" depends on INTERCONNECT_QCOM_RPMH_POSSIBLE diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile index 8d1fe9d38ac3..8e357528185d 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -1,5 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_INTERCONNECT_QCOM) += interconnect_qcom.o + +interconnect_qcom-y := icc-common.o icc-bcm-voter-objs := bcm-voter.o qnoc-msm8916-objs := msm8916.o qnoc-msm8939-objs := msm8939.o @@ -17,6 +20,7 @@ qnoc-sdm660-objs := sdm660.o qnoc-sdm845-objs := sdm845.o qnoc-sdx55-objs := sdx55.o qnoc-sdx65-objs := sdx65.o +qnoc-sm6350-objs := sm6350.o qnoc-sm8150-objs := sm8150.o qnoc-sm8250-objs := sm8250.o qnoc-sm8350-objs := sm8350.o @@ -40,6 +44,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SDM660) += qnoc-sdm660.o obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o obj-$(CONFIG_INTERCONNECT_QCOM_SDX65) += qnoc-sdx65.o +obj-$(CONFIG_INTERCONNECT_QCOM_SM6350) += qnoc-sm6350.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8350) += qnoc-sm8350.o diff --git a/drivers/interconnect/qcom/icc-common.c b/drivers/interconnect/qcom/icc-common.c new file mode 100644 index 000000000000..0822ce207b5d --- /dev/null +++ b/drivers/interconnect/qcom/icc-common.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Linaro Ltd. + */ + +#include +#include + +#include "icc-common.h" + +struct icc_node_data *qcom_icc_xlate_extended(struct of_phandle_args *spec, void *data) +{ + struct icc_node_data *ndata; + struct icc_node *node; + + node = of_icc_xlate_onecell(spec, data); + if (IS_ERR(node)) + return ERR_CAST(node); + + ndata = kzalloc(sizeof(*ndata), GFP_KERNEL); + if (!ndata) + return ERR_PTR(-ENOMEM); + + ndata->node = node; + + if (spec->args_count == 2) + ndata->tag = spec->args[1]; + + if (spec->args_count > 2) + pr_warn("%pOF: Too many arguments, path tag is not parsed\n", spec->np); + + return ndata; +} +EXPORT_SYMBOL_GPL(qcom_icc_xlate_extended); diff --git a/drivers/interconnect/qcom/icc-common.h b/drivers/interconnect/qcom/icc-common.h new file mode 100644 index 000000000000..33bb2c38dff3 --- /dev/null +++ b/drivers/interconnect/qcom/icc-common.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 Linaro Ltd. + */ + +#ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_COMMON_H__ +#define __DRIVERS_INTERCONNECT_QCOM_ICC_COMMON_H__ + +#include + +struct icc_node_data *qcom_icc_xlate_extended(struct of_phandle_args *spec, void *data); + +#endif diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index fb013191c29b..7f6a70e0256a 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -16,6 +16,7 @@ #include #include "smd-rpm.h" +#include "icc-common.h" #include "icc-rpm.h" /* QNOC QoS */ @@ -233,29 +234,10 @@ static int qcom_icc_rpm_set(int mas_rpm_id, int slv_rpm_id, u64 sum_bw) return ret; } -static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) +static int __qcom_icc_set(struct icc_node *n, struct qcom_icc_node *qn, + u64 sum_bw) { - struct qcom_icc_provider *qp; - struct qcom_icc_node *qn; - struct icc_provider *provider; - struct icc_node *n; - u64 sum_bw; - u64 max_peak_bw; - u64 rate; - u32 agg_avg = 0; - u32 agg_peak = 0; - int ret, i; - - qn = src->data; - provider = src->provider; - qp = to_qcom_provider(provider); - - list_for_each_entry(n, &provider->nodes, node_list) - provider->aggregate(n, 0, n->avg_bw, n->peak_bw, - &agg_avg, &agg_peak); - - sum_bw = icc_units_to_bps(agg_avg); - max_peak_bw = icc_units_to_bps(agg_peak); + int ret; if (!qn->qos.ap_owned) { /* send bandwidth request message to the RPM processor */ @@ -264,17 +246,150 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) return ret; } else if (qn->qos.qos_mode != -1) { /* set bandwidth directly from the AP */ - ret = qcom_icc_qos_set(src, sum_bw); + ret = qcom_icc_qos_set(n, sum_bw); if (ret) return ret; } - rate = max(sum_bw, max_peak_bw); + return 0; +} - do_div(rate, qn->buswidth); - rate = min_t(u64, rate, LONG_MAX); +/** + * qcom_icc_pre_bw_aggregate - cleans up values before re-aggregate requests + * @node: icc node to operate on + */ +static void qcom_icc_pre_bw_aggregate(struct icc_node *node) +{ + struct qcom_icc_node *qn; + size_t i; + + qn = node->data; + for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) { + qn->sum_avg[i] = 0; + qn->max_peak[i] = 0; + } +} + +/** + * qcom_icc_bw_aggregate - aggregate bw for buckets indicated by tag + * @node: node to aggregate + * @tag: tag to indicate which buckets to aggregate + * @avg_bw: new bw to sum aggregate + * @peak_bw: new bw to max aggregate + * @agg_avg: existing aggregate avg bw val + * @agg_peak: existing aggregate peak bw val + */ +static int qcom_icc_bw_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak) +{ + size_t i; + struct qcom_icc_node *qn; + + qn = node->data; + + if (!tag) + tag = QCOM_ICC_TAG_ALWAYS; + + for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) { + if (tag & BIT(i)) { + qn->sum_avg[i] += avg_bw; + qn->max_peak[i] = max_t(u32, qn->max_peak[i], peak_bw); + } + } + + *agg_avg += avg_bw; + *agg_peak = max_t(u32, *agg_peak, peak_bw); + return 0; +} + +/** + * qcom_icc_bus_aggregate - aggregate bandwidth by traversing all nodes + * @provider: generic interconnect provider + * @agg_avg: an array for aggregated average bandwidth of buckets + * @agg_peak: an array for aggregated peak bandwidth of buckets + * @max_agg_avg: pointer to max value of aggregated average bandwidth + */ +static void qcom_icc_bus_aggregate(struct icc_provider *provider, + u64 *agg_avg, u64 *agg_peak, + u64 *max_agg_avg) +{ + struct icc_node *node; + struct qcom_icc_node *qn; + int i; + + /* Initialise aggregate values */ + for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) { + agg_avg[i] = 0; + agg_peak[i] = 0; + } + + *max_agg_avg = 0; + + /* + * Iterate nodes on the interconnect and aggregate bandwidth + * requests for every bucket. + */ + list_for_each_entry(node, &provider->nodes, node_list) { + qn = node->data; + for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) { + agg_avg[i] += qn->sum_avg[i]; + agg_peak[i] = max_t(u64, agg_peak[i], qn->max_peak[i]); + } + } + + /* Find maximum values across all buckets */ + for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) + *max_agg_avg = max_t(u64, *max_agg_avg, agg_avg[i]); +} + +static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct qcom_icc_provider *qp; + struct qcom_icc_node *src_qn = NULL, *dst_qn = NULL; + struct icc_provider *provider; + u64 sum_bw; + u64 rate; + u64 agg_avg[QCOM_ICC_NUM_BUCKETS], agg_peak[QCOM_ICC_NUM_BUCKETS]; + u64 max_agg_avg; + int ret, i; + int bucket; + + src_qn = src->data; + if (dst) + dst_qn = dst->data; + provider = src->provider; + qp = to_qcom_provider(provider); + + qcom_icc_bus_aggregate(provider, agg_avg, agg_peak, &max_agg_avg); + + sum_bw = icc_units_to_bps(max_agg_avg); + + ret = __qcom_icc_set(src, src_qn, sum_bw); + if (ret) + return ret; + if (dst_qn) { + ret = __qcom_icc_set(dst, dst_qn, sum_bw); + if (ret) + return ret; + } for (i = 0; i < qp->num_clks; i++) { + /* + * Use WAKE bucket for active clock, otherwise, use SLEEP bucket + * for other clocks. If a platform doesn't set interconnect + * path tags, by default use sleep bucket for all clocks. + * + * Note, AMC bucket is not supported yet. + */ + if (!strcmp(qp->bus_clks[i].id, "bus_a")) + bucket = QCOM_ICC_BUCKET_WAKE; + else + bucket = QCOM_ICC_BUCKET_SLEEP; + + rate = icc_units_to_bps(max(agg_avg[bucket], agg_peak[bucket])); + do_div(rate, src_qn->buswidth); + rate = min_t(u64, rate, LONG_MAX); + if (qp->bus_clk_rate[i] == rate) continue; @@ -394,8 +509,9 @@ regmap_done: INIT_LIST_HEAD(&provider->nodes); provider->dev = dev; provider->set = qcom_icc_set; - provider->aggregate = icc_std_aggregate; - provider->xlate = of_icc_xlate_onecell; + provider->pre_aggregate = qcom_icc_pre_bw_aggregate; + provider->aggregate = qcom_icc_bw_aggregate; + provider->xlate_extended = qcom_icc_xlate_extended; provider->data = data; ret = icc_provider_add(provider); diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h index ebee9009301e..a49af844ab13 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -6,6 +6,8 @@ #ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H #define __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H +#include + #define RPM_BUS_MASTER_REQ 0x73616d62 #define RPM_BUS_SLAVE_REQ 0x766c7362 @@ -65,6 +67,8 @@ struct qcom_icc_qos { * @links: an array of nodes where we can go next while traversing * @num_links: the total number of @links * @buswidth: width of the interconnect between a node and the bus (bytes) + * @sum_avg: current sum aggregate value of all avg bw requests + * @max_peak: current max aggregate value of all peak bw requests * @mas_rpm_id: RPM id for devices that are bus masters * @slv_rpm_id: RPM id for devices that are bus slaves * @qos: NoC QoS setting parameters @@ -75,6 +79,8 @@ struct qcom_icc_node { const u16 *links; u16 num_links; u16 buswidth; + u64 sum_avg[QCOM_ICC_NUM_BUCKETS]; + u64 max_peak[QCOM_ICC_NUM_BUCKETS]; int mas_rpm_id; int slv_rpm_id; struct qcom_icc_qos qos; diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c index 3c40076eb5fb..114bb8f64573 100644 --- a/drivers/interconnect/qcom/icc-rpmh.c +++ b/drivers/interconnect/qcom/icc-rpmh.c @@ -11,6 +11,7 @@ #include #include "bcm-voter.h" +#include "icc-common.h" #include "icc-rpmh.h" /** @@ -100,31 +101,6 @@ int qcom_icc_set(struct icc_node *src, struct icc_node *dst) } EXPORT_SYMBOL_GPL(qcom_icc_set); -struct icc_node_data *qcom_icc_xlate_extended(struct of_phandle_args *spec, void *data) -{ - struct icc_node_data *ndata; - struct icc_node *node; - - node = of_icc_xlate_onecell(spec, data); - if (IS_ERR(node)) - return ERR_CAST(node); - - ndata = kzalloc(sizeof(*ndata), GFP_KERNEL); - if (!ndata) - return ERR_PTR(-ENOMEM); - - ndata->node = node; - - if (spec->args_count == 2) - ndata->tag = spec->args[1]; - - if (spec->args_count > 2) - pr_warn("%pOF: Too many arguments, path tag is not parsed\n", spec->np); - - return ndata; -} -EXPORT_SYMBOL_GPL(qcom_icc_xlate_extended); - /** * qcom_icc_bcm_init - populates bcm aux data and connect qnodes * @bcm: bcm to be initialized @@ -258,6 +234,10 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) data->num_nodes = num_nodes; platform_set_drvdata(pdev, qp); + /* Populate child NoC devices if any */ + if (of_get_child_count(dev->of_node) > 0) + return of_platform_populate(dev->of_node, NULL, NULL, dev); + return 0; err: icc_nodes_remove(provider); diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h index d29929461c17..04391c1ba465 100644 --- a/drivers/interconnect/qcom/icc-rpmh.h +++ b/drivers/interconnect/qcom/icc-rpmh.h @@ -131,7 +131,6 @@ struct qcom_icc_desc { int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, u32 peak_bw, u32 *agg_avg, u32 *agg_peak); int qcom_icc_set(struct icc_node *src, struct icc_node *dst); -struct icc_node_data *qcom_icc_xlate_extended(struct of_phandle_args *spec, void *data); int qcom_icc_bcm_init(struct qcom_icc_bcm *bcm, struct device *dev); void qcom_icc_pre_aggregate(struct icc_node *node); int qcom_icc_rpmh_probe(struct platform_device *pdev); diff --git a/drivers/interconnect/qcom/msm8939.c b/drivers/interconnect/qcom/msm8939.c index 63b31deea722..caf0aefad668 100644 --- a/drivers/interconnect/qcom/msm8939.c +++ b/drivers/interconnect/qcom/msm8939.c @@ -1423,6 +1423,7 @@ static struct platform_driver msm8939_noc_driver = { .driver = { .name = "qnoc-msm8939", .of_match_table = msm8939_noc_of_match, + .sync_state = icc_sync_state, }, }; module_platform_driver(msm8939_noc_driver); diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom/sm6350.c new file mode 100644 index 000000000000..a3d46e59444e --- /dev/null +++ b/drivers/interconnect/qcom/sm6350.c @@ -0,0 +1,493 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Luca Weiss + */ + +#include +#include +#include +#include +#include +#include + +#include "bcm-voter.h" +#include "icc-rpmh.h" +#include "sm6350.h" + +DEFINE_QNODE(qhm_a1noc_cfg, SM6350_MASTER_A1NOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_A1NOC); +DEFINE_QNODE(qhm_qup_0, SM6350_MASTER_QUP_0, 1, 4, SM6350_A1NOC_SNOC_SLV); +DEFINE_QNODE(xm_emmc, SM6350_MASTER_EMMC, 1, 8, SM6350_A1NOC_SNOC_SLV); +DEFINE_QNODE(xm_ufs_mem, SM6350_MASTER_UFS_MEM, 1, 8, SM6350_A1NOC_SNOC_SLV); +DEFINE_QNODE(qhm_a2noc_cfg, SM6350_MASTER_A2NOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_A2NOC); +DEFINE_QNODE(qhm_qdss_bam, SM6350_MASTER_QDSS_BAM, 1, 4, SM6350_A2NOC_SNOC_SLV); +DEFINE_QNODE(qhm_qup_1, SM6350_MASTER_QUP_1, 1, 4, SM6350_A2NOC_SNOC_SLV); +DEFINE_QNODE(qxm_crypto, SM6350_MASTER_CRYPTO_CORE_0, 1, 8, SM6350_A2NOC_SNOC_SLV); +DEFINE_QNODE(qxm_ipa, SM6350_MASTER_IPA, 1, 8, SM6350_A2NOC_SNOC_SLV); +DEFINE_QNODE(xm_qdss_etr, SM6350_MASTER_QDSS_ETR, 1, 8, SM6350_A2NOC_SNOC_SLV); +DEFINE_QNODE(xm_sdc2, SM6350_MASTER_SDCC_2, 1, 8, SM6350_A2NOC_SNOC_SLV); +DEFINE_QNODE(xm_usb3_0, SM6350_MASTER_USB3, 1, 8, SM6350_A2NOC_SNOC_SLV); +DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SM6350_MASTER_CAMNOC_HF0_UNCOMP, 2, 32, SM6350_SLAVE_CAMNOC_UNCOMP); +DEFINE_QNODE(qxm_camnoc_icp_uncomp, SM6350_MASTER_CAMNOC_ICP_UNCOMP, 1, 32, SM6350_SLAVE_CAMNOC_UNCOMP); +DEFINE_QNODE(qxm_camnoc_sf_uncomp, SM6350_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SM6350_SLAVE_CAMNOC_UNCOMP); +DEFINE_QNODE(qup0_core_master, SM6350_MASTER_QUP_CORE_0, 1, 4, SM6350_SLAVE_QUP_CORE_0); +DEFINE_QNODE(qup1_core_master, SM6350_MASTER_QUP_CORE_1, 1, 4, SM6350_SLAVE_QUP_CORE_1); +DEFINE_QNODE(qnm_npu, SM6350_MASTER_NPU, 2, 32, SM6350_SLAVE_CDSP_GEM_NOC); +DEFINE_QNODE(qxm_npu_dsp, SM6350_MASTER_NPU_PROC, 1, 8, SM6350_SLAVE_CDSP_GEM_NOC); +DEFINE_QNODE(qnm_snoc, SM6350_SNOC_CNOC_MAS, 1, 8, SM6350_SLAVE_CAMERA_CFG, SM6350_SLAVE_SDCC_2, SM6350_SLAVE_CNOC_MNOC_CFG, SM6350_SLAVE_UFS_MEM_CFG, SM6350_SLAVE_QM_CFG, SM6350_SLAVE_SNOC_CFG, SM6350_SLAVE_QM_MPU_CFG, SM6350_SLAVE_GLM, SM6350_SLAVE_PDM, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, SM6350_SLAVE_A2NOC_CFG, SM6350_SLAVE_QDSS_CFG, SM6350_SLAVE_VSENSE_CTRL_CFG, SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, SM6350_SLAVE_DISPLAY_CFG, SM6350_SLAVE_TCSR, SM6350_SLAVE_DCC_CFG, SM6350_SLAVE_CNOC_DDRSS, SM6350_SLAVE_DISPLAY_THROTTLE_CFG, SM6350_SLAVE_NPU_CFG, SM6350_SLAVE_AHB2PHY, SM6350_SLAVE_GRAPHICS_3D_CFG, SM6350_SLAVE_BOOT_ROM, SM6350_SLAVE_VENUS_CFG, SM6350_SLAVE_IPA_CFG, SM6350_SLAVE_SECURITY, SM6350_SLAVE_IMEM_CFG, SM6350_SLAVE_CNOC_MSS, SM6350_SLAVE_SERVICE_CNOC, SM6350_SLAVE_USB3, SM6350_SLAVE_VENUS_THROTTLE_CFG, SM6350_SLAVE_RBCPR_CX_CFG, SM6350_SLAVE_A1NOC_CFG, SM6350_SLAVE_AOSS, SM6350_SLAVE_PRNG, SM6350_SLAVE_EMMC_CFG, SM6350_SLAVE_CRYPTO_0_CFG, SM6350_SLAVE_PIMEM_CFG, SM6350_SLAVE_RBCPR_MX_CFG, SM6350_SLAVE_QUP_0, SM6350_SLAVE_QUP_1, SM6350_SLAVE_CLK_CTL); +DEFINE_QNODE(xm_qdss_dap, SM6350_MASTER_QDSS_DAP, 1, 8, SM6350_SLAVE_CAMERA_CFG, SM6350_SLAVE_SDCC_2, SM6350_SLAVE_CNOC_MNOC_CFG, SM6350_SLAVE_UFS_MEM_CFG, SM6350_SLAVE_QM_CFG, SM6350_SLAVE_SNOC_CFG, SM6350_SLAVE_QM_MPU_CFG, SM6350_SLAVE_GLM, SM6350_SLAVE_PDM, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, SM6350_SLAVE_A2NOC_CFG, SM6350_SLAVE_QDSS_CFG, SM6350_SLAVE_VSENSE_CTRL_CFG, SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, SM6350_SLAVE_DISPLAY_CFG, SM6350_SLAVE_TCSR, SM6350_SLAVE_DCC_CFG, SM6350_SLAVE_CNOC_DDRSS, SM6350_SLAVE_DISPLAY_THROTTLE_CFG, SM6350_SLAVE_NPU_CFG, SM6350_SLAVE_AHB2PHY, SM6350_SLAVE_GRAPHICS_3D_CFG, SM6350_SLAVE_BOOT_ROM, SM6350_SLAVE_VENUS_CFG, SM6350_SLAVE_IPA_CFG, SM6350_SLAVE_SECURITY, SM6350_SLAVE_IMEM_CFG, SM6350_SLAVE_CNOC_MSS, SM6350_SLAVE_SERVICE_CNOC, SM6350_SLAVE_USB3, SM6350_SLAVE_VENUS_THROTTLE_CFG, SM6350_SLAVE_RBCPR_CX_CFG, SM6350_SLAVE_A1NOC_CFG, SM6350_SLAVE_AOSS, SM6350_SLAVE_PRNG, SM6350_SLAVE_EMMC_CFG, SM6350_SLAVE_CRYPTO_0_CFG, SM6350_SLAVE_PIMEM_CFG, SM6350_SLAVE_RBCPR_MX_CFG, SM6350_SLAVE_QUP_0, SM6350_SLAVE_QUP_1, SM6350_SLAVE_CLK_CTL); +DEFINE_QNODE(qhm_cnoc_dc_noc, SM6350_MASTER_CNOC_DC_NOC, 1, 4, SM6350_SLAVE_LLCC_CFG, SM6350_SLAVE_GEM_NOC_CFG); +DEFINE_QNODE(acm_apps, SM6350_MASTER_AMPSS_M0, 1, 16, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); +DEFINE_QNODE(acm_sys_tcu, SM6350_MASTER_SYS_TCU, 1, 8, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); +DEFINE_QNODE(qhm_gemnoc_cfg, SM6350_MASTER_GEM_NOC_CFG, 1, 4, SM6350_SLAVE_MCDMA_MS_MPU_CFG, SM6350_SLAVE_SERVICE_GEM_NOC, SM6350_SLAVE_MSS_PROC_MS_MPU_CFG); +DEFINE_QNODE(qnm_cmpnoc, SM6350_MASTER_COMPUTE_NOC, 1, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); +DEFINE_QNODE(qnm_mnoc_hf, SM6350_MASTER_MNOC_HF_MEM_NOC, 1, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); +DEFINE_QNODE(qnm_mnoc_sf, SM6350_MASTER_MNOC_SF_MEM_NOC, 1, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); +DEFINE_QNODE(qnm_snoc_gc, SM6350_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM6350_SLAVE_LLCC); +DEFINE_QNODE(qnm_snoc_sf, SM6350_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM6350_SLAVE_LLCC); +DEFINE_QNODE(qxm_gpu, SM6350_MASTER_GRAPHICS_3D, 2, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); +DEFINE_QNODE(llcc_mc, SM6350_MASTER_LLCC, 2, 4, SM6350_SLAVE_EBI_CH0); +DEFINE_QNODE(qhm_mnoc_cfg, SM6350_MASTER_CNOC_MNOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_MNOC); +DEFINE_QNODE(qnm_video0, SM6350_MASTER_VIDEO_P0, 1, 32, SM6350_SLAVE_MNOC_SF_MEM_NOC); +DEFINE_QNODE(qnm_video_cvp, SM6350_MASTER_VIDEO_PROC, 1, 8, SM6350_SLAVE_MNOC_SF_MEM_NOC); +DEFINE_QNODE(qxm_camnoc_hf, SM6350_MASTER_CAMNOC_HF, 2, 32, SM6350_SLAVE_MNOC_HF_MEM_NOC); +DEFINE_QNODE(qxm_camnoc_icp, SM6350_MASTER_CAMNOC_ICP, 1, 8, SM6350_SLAVE_MNOC_SF_MEM_NOC); +DEFINE_QNODE(qxm_camnoc_sf, SM6350_MASTER_CAMNOC_SF, 1, 32, SM6350_SLAVE_MNOC_SF_MEM_NOC); +DEFINE_QNODE(qxm_mdp0, SM6350_MASTER_MDP_PORT0, 1, 32, SM6350_SLAVE_MNOC_HF_MEM_NOC); +DEFINE_QNODE(amm_npu_sys, SM6350_MASTER_NPU_SYS, 2, 32, SM6350_SLAVE_NPU_COMPUTE_NOC); +DEFINE_QNODE(qhm_npu_cfg, SM6350_MASTER_NPU_NOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_NPU_NOC, SM6350_SLAVE_ISENSE_CFG, SM6350_SLAVE_NPU_LLM_CFG, SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, SM6350_SLAVE_NPU_CP, SM6350_SLAVE_NPU_TCM, SM6350_SLAVE_NPU_CAL_DP0, SM6350_SLAVE_NPU_DPM); +DEFINE_QNODE(qhm_snoc_cfg, SM6350_MASTER_SNOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_SNOC); +DEFINE_QNODE(qnm_aggre1_noc, SM6350_A1NOC_SNOC_MAS, 1, 16, SM6350_SLAVE_SNOC_GEM_NOC_SF, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS, SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_QDSS_STM); +DEFINE_QNODE(qnm_aggre2_noc, SM6350_A2NOC_SNOC_MAS, 1, 16, SM6350_SLAVE_SNOC_GEM_NOC_SF, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS, SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_TCU, SM6350_SLAVE_QDSS_STM); +DEFINE_QNODE(qnm_gemnoc, SM6350_MASTER_GEM_NOC_SNOC, 1, 8, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS, SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_TCU, SM6350_SLAVE_QDSS_STM); +DEFINE_QNODE(qxm_pimem, SM6350_MASTER_PIMEM, 1, 8, SM6350_SLAVE_SNOC_GEM_NOC_GC, SM6350_SLAVE_OCIMEM); +DEFINE_QNODE(xm_gic, SM6350_MASTER_GIC, 1, 8, SM6350_SLAVE_SNOC_GEM_NOC_GC); +DEFINE_QNODE(qns_a1noc_snoc, SM6350_A1NOC_SNOC_SLV, 1, 16, SM6350_A1NOC_SNOC_MAS); +DEFINE_QNODE(srvc_aggre1_noc, SM6350_SLAVE_SERVICE_A1NOC, 1, 4); +DEFINE_QNODE(qns_a2noc_snoc, SM6350_A2NOC_SNOC_SLV, 1, 16, SM6350_A2NOC_SNOC_MAS); +DEFINE_QNODE(srvc_aggre2_noc, SM6350_SLAVE_SERVICE_A2NOC, 1, 4); +DEFINE_QNODE(qns_camnoc_uncomp, SM6350_SLAVE_CAMNOC_UNCOMP, 1, 32); +DEFINE_QNODE(qup0_core_slave, SM6350_SLAVE_QUP_CORE_0, 1, 4); +DEFINE_QNODE(qup1_core_slave, SM6350_SLAVE_QUP_CORE_1, 1, 4); +DEFINE_QNODE(qns_cdsp_gemnoc, SM6350_SLAVE_CDSP_GEM_NOC, 1, 32, SM6350_MASTER_COMPUTE_NOC); +DEFINE_QNODE(qhs_a1_noc_cfg, SM6350_SLAVE_A1NOC_CFG, 1, 4, SM6350_MASTER_A1NOC_CFG); +DEFINE_QNODE(qhs_a2_noc_cfg, SM6350_SLAVE_A2NOC_CFG, 1, 4, SM6350_MASTER_A2NOC_CFG); +DEFINE_QNODE(qhs_ahb2phy0, SM6350_SLAVE_AHB2PHY, 1, 4); +DEFINE_QNODE(qhs_ahb2phy2, SM6350_SLAVE_AHB2PHY_2, 1, 4); +DEFINE_QNODE(qhs_aoss, SM6350_SLAVE_AOSS, 1, 4); +DEFINE_QNODE(qhs_boot_rom, SM6350_SLAVE_BOOT_ROM, 1, 4); +DEFINE_QNODE(qhs_camera_cfg, SM6350_SLAVE_CAMERA_CFG, 1, 4); +DEFINE_QNODE(qhs_camera_nrt_thrott_cfg, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, 1, 4); +DEFINE_QNODE(qhs_camera_rt_throttle_cfg, SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, 1, 4); +DEFINE_QNODE(qhs_clk_ctl, SM6350_SLAVE_CLK_CTL, 1, 4); +DEFINE_QNODE(qhs_cpr_cx, SM6350_SLAVE_RBCPR_CX_CFG, 1, 4); +DEFINE_QNODE(qhs_cpr_mx, SM6350_SLAVE_RBCPR_MX_CFG, 1, 4); +DEFINE_QNODE(qhs_crypto0_cfg, SM6350_SLAVE_CRYPTO_0_CFG, 1, 4); +DEFINE_QNODE(qhs_dcc_cfg, SM6350_SLAVE_DCC_CFG, 1, 4); +DEFINE_QNODE(qhs_ddrss_cfg, SM6350_SLAVE_CNOC_DDRSS, 1, 4, SM6350_MASTER_CNOC_DC_NOC); +DEFINE_QNODE(qhs_display_cfg, SM6350_SLAVE_DISPLAY_CFG, 1, 4); +DEFINE_QNODE(qhs_display_throttle_cfg, SM6350_SLAVE_DISPLAY_THROTTLE_CFG, 1, 4); +DEFINE_QNODE(qhs_emmc_cfg, SM6350_SLAVE_EMMC_CFG, 1, 4); +DEFINE_QNODE(qhs_glm, SM6350_SLAVE_GLM, 1, 4); +DEFINE_QNODE(qhs_gpuss_cfg, SM6350_SLAVE_GRAPHICS_3D_CFG, 1, 8); +DEFINE_QNODE(qhs_imem_cfg, SM6350_SLAVE_IMEM_CFG, 1, 4); +DEFINE_QNODE(qhs_ipa, SM6350_SLAVE_IPA_CFG, 1, 4); +DEFINE_QNODE(qhs_mnoc_cfg, SM6350_SLAVE_CNOC_MNOC_CFG, 1, 4, SM6350_MASTER_CNOC_MNOC_CFG); +DEFINE_QNODE(qhs_mss_cfg, SM6350_SLAVE_CNOC_MSS, 1, 4); +DEFINE_QNODE(qhs_npu_cfg, SM6350_SLAVE_NPU_CFG, 1, 4, SM6350_MASTER_NPU_NOC_CFG); +DEFINE_QNODE(qhs_pdm, SM6350_SLAVE_PDM, 1, 4); +DEFINE_QNODE(qhs_pimem_cfg, SM6350_SLAVE_PIMEM_CFG, 1, 4); +DEFINE_QNODE(qhs_prng, SM6350_SLAVE_PRNG, 1, 4); +DEFINE_QNODE(qhs_qdss_cfg, SM6350_SLAVE_QDSS_CFG, 1, 4); +DEFINE_QNODE(qhs_qm_cfg, SM6350_SLAVE_QM_CFG, 1, 4); +DEFINE_QNODE(qhs_qm_mpu_cfg, SM6350_SLAVE_QM_MPU_CFG, 1, 4); +DEFINE_QNODE(qhs_qup0, SM6350_SLAVE_QUP_0, 1, 4); +DEFINE_QNODE(qhs_qup1, SM6350_SLAVE_QUP_1, 1, 4); +DEFINE_QNODE(qhs_sdc2, SM6350_SLAVE_SDCC_2, 1, 4); +DEFINE_QNODE(qhs_security, SM6350_SLAVE_SECURITY, 1, 4); +DEFINE_QNODE(qhs_snoc_cfg, SM6350_SLAVE_SNOC_CFG, 1, 4, SM6350_MASTER_SNOC_CFG); +DEFINE_QNODE(qhs_tcsr, SM6350_SLAVE_TCSR, 1, 4); +DEFINE_QNODE(qhs_ufs_mem_cfg, SM6350_SLAVE_UFS_MEM_CFG, 1, 4); +DEFINE_QNODE(qhs_usb3_0, SM6350_SLAVE_USB3, 1, 4); +DEFINE_QNODE(qhs_venus_cfg, SM6350_SLAVE_VENUS_CFG, 1, 4); +DEFINE_QNODE(qhs_venus_throttle_cfg, SM6350_SLAVE_VENUS_THROTTLE_CFG, 1, 4); +DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM6350_SLAVE_VSENSE_CTRL_CFG, 1, 4); +DEFINE_QNODE(srvc_cnoc, SM6350_SLAVE_SERVICE_CNOC, 1, 4); +DEFINE_QNODE(qhs_gemnoc, SM6350_SLAVE_GEM_NOC_CFG, 1, 4, SM6350_MASTER_GEM_NOC_CFG); +DEFINE_QNODE(qhs_llcc, SM6350_SLAVE_LLCC_CFG, 1, 4); +DEFINE_QNODE(qhs_mcdma_ms_mpu_cfg, SM6350_SLAVE_MCDMA_MS_MPU_CFG, 1, 4); +DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM6350_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); +DEFINE_QNODE(qns_gem_noc_snoc, SM6350_SLAVE_GEM_NOC_SNOC, 1, 8, SM6350_MASTER_GEM_NOC_SNOC); +DEFINE_QNODE(qns_llcc, SM6350_SLAVE_LLCC, 1, 16, SM6350_MASTER_LLCC); +DEFINE_QNODE(srvc_gemnoc, SM6350_SLAVE_SERVICE_GEM_NOC, 1, 4); +DEFINE_QNODE(ebi, SM6350_SLAVE_EBI_CH0, 2, 4); +DEFINE_QNODE(qns_mem_noc_hf, SM6350_SLAVE_MNOC_HF_MEM_NOC, 1, 32, SM6350_MASTER_MNOC_HF_MEM_NOC); +DEFINE_QNODE(qns_mem_noc_sf, SM6350_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM6350_MASTER_MNOC_SF_MEM_NOC); +DEFINE_QNODE(srvc_mnoc, SM6350_SLAVE_SERVICE_MNOC, 1, 4); +DEFINE_QNODE(qhs_cal_dp0, SM6350_SLAVE_NPU_CAL_DP0, 1, 4); +DEFINE_QNODE(qhs_cp, SM6350_SLAVE_NPU_CP, 1, 4); +DEFINE_QNODE(qhs_dma_bwmon, SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4); +DEFINE_QNODE(qhs_dpm, SM6350_SLAVE_NPU_DPM, 1, 4); +DEFINE_QNODE(qhs_isense, SM6350_SLAVE_ISENSE_CFG, 1, 4); +DEFINE_QNODE(qhs_llm, SM6350_SLAVE_NPU_LLM_CFG, 1, 4); +DEFINE_QNODE(qhs_tcm, SM6350_SLAVE_NPU_TCM, 1, 4); +DEFINE_QNODE(qns_npu_sys, SM6350_SLAVE_NPU_COMPUTE_NOC, 2, 32); +DEFINE_QNODE(srvc_noc, SM6350_SLAVE_SERVICE_NPU_NOC, 1, 4); +DEFINE_QNODE(qhs_apss, SM6350_SLAVE_APPSS, 1, 8); +DEFINE_QNODE(qns_cnoc, SM6350_SNOC_CNOC_SLV, 1, 8, SM6350_SNOC_CNOC_MAS); +DEFINE_QNODE(qns_gemnoc_gc, SM6350_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM6350_MASTER_SNOC_GC_MEM_NOC); +DEFINE_QNODE(qns_gemnoc_sf, SM6350_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM6350_MASTER_SNOC_SF_MEM_NOC); +DEFINE_QNODE(qxs_imem, SM6350_SLAVE_OCIMEM, 1, 8); +DEFINE_QNODE(qxs_pimem, SM6350_SLAVE_PIMEM, 1, 8); +DEFINE_QNODE(srvc_snoc, SM6350_SLAVE_SERVICE_SNOC, 1, 4); +DEFINE_QNODE(xs_qdss_stm, SM6350_SLAVE_QDSS_STM, 1, 4); +DEFINE_QNODE(xs_sys_tcu_cfg, SM6350_SLAVE_TCU, 1, 8); + +DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); +DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); +DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aoss, &qhs_boot_rom, &qhs_camera_cfg, &qhs_camera_nrt_thrott_cfg, &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_display_throttle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_mss_cfg, &qhs_npu_cfg, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_cfg, &qhs_qup0, &qhs_qup1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_venus_cfg, &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc); +DEFINE_QBCM(bcm_cn1, "CN1", false, &xm_emmc, &xm_sdc2, &qhs_ahb2phy2, &qhs_emmc_cfg, &qhs_pdm, &qhs_sdc2); +DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_gemnoc); +DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu); +DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_npu_dsp); +DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); +DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf); +DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_icp_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf, &qxm_mdp0); +DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf); +DEFINE_QBCM(bcm_mm3, "MM3", false, &qhm_mnoc_cfg, &qnm_video0, &qnm_video_cvp, &qxm_camnoc_sf); +DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup0_core_master, &qup1_core_master, &qup0_core_slave, &qup1_core_slave); +DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); +DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu); +DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc); +DEFINE_QBCM(bcm_sh4, "SH4", false, &acm_apps); +DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf); +DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); +DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc); +DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem); +DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm); +DEFINE_QBCM(bcm_sn5, "SN5", false, &qnm_aggre1_noc); +DEFINE_QBCM(bcm_sn6, "SN6", false, &qnm_aggre2_noc); +DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_gemnoc); + +static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { + &bcm_cn1, +}; + +static struct qcom_icc_node * const aggre1_noc_nodes[] = { + [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, + [MASTER_QUP_0] = &qhm_qup_0, + [MASTER_EMMC] = &xm_emmc, + [MASTER_UFS_MEM] = &xm_ufs_mem, + [A1NOC_SNOC_SLV] = &qns_a1noc_snoc, + [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, +}; + +static const struct qcom_icc_desc sm6350_aggre1_noc = { + .nodes = aggre1_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), + .bcms = aggre1_noc_bcms, + .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), +}; + +static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { + &bcm_ce0, + &bcm_cn1, +}; + +static struct qcom_icc_node * const aggre2_noc_nodes[] = { + [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, + [MASTER_QDSS_BAM] = &qhm_qdss_bam, + [MASTER_QUP_1] = &qhm_qup_1, + [MASTER_CRYPTO_CORE_0] = &qxm_crypto, + [MASTER_IPA] = &qxm_ipa, + [MASTER_QDSS_ETR] = &xm_qdss_etr, + [MASTER_SDCC_2] = &xm_sdc2, + [MASTER_USB3] = &xm_usb3_0, + [A2NOC_SNOC_SLV] = &qns_a2noc_snoc, + [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, +}; + +static const struct qcom_icc_desc sm6350_aggre2_noc = { + .nodes = aggre2_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), + .bcms = aggre2_noc_bcms, + .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), +}; + +static struct qcom_icc_bcm * const clk_virt_bcms[] = { + &bcm_acv, + &bcm_mc0, + &bcm_mm1, + &bcm_qup0, +}; + +static struct qcom_icc_node * const clk_virt_nodes[] = { + [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, + [MASTER_CAMNOC_ICP_UNCOMP] = &qxm_camnoc_icp_uncomp, + [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, + [MASTER_QUP_CORE_0] = &qup0_core_master, + [MASTER_QUP_CORE_1] = &qup1_core_master, + [MASTER_LLCC] = &llcc_mc, + [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, + [SLAVE_QUP_CORE_0] = &qup0_core_slave, + [SLAVE_QUP_CORE_1] = &qup1_core_slave, + [SLAVE_EBI_CH0] = &ebi, +}; + +static const struct qcom_icc_desc sm6350_clk_virt = { + .nodes = clk_virt_nodes, + .num_nodes = ARRAY_SIZE(clk_virt_nodes), + .bcms = clk_virt_bcms, + .num_bcms = ARRAY_SIZE(clk_virt_bcms), +}; + +static struct qcom_icc_bcm * const compute_noc_bcms[] = { + &bcm_co0, + &bcm_co2, + &bcm_co3, +}; + +static struct qcom_icc_node * const compute_noc_nodes[] = { + [MASTER_NPU] = &qnm_npu, + [MASTER_NPU_PROC] = &qxm_npu_dsp, + [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc, +}; + +static const struct qcom_icc_desc sm6350_compute_noc = { + .nodes = compute_noc_nodes, + .num_nodes = ARRAY_SIZE(compute_noc_nodes), + .bcms = compute_noc_bcms, + .num_bcms = ARRAY_SIZE(compute_noc_bcms), +}; + +static struct qcom_icc_bcm * const config_noc_bcms[] = { + &bcm_cn0, + &bcm_cn1, +}; + +static struct qcom_icc_node * const config_noc_nodes[] = { + [SNOC_CNOC_MAS] = &qnm_snoc, + [MASTER_QDSS_DAP] = &xm_qdss_dap, + [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, + [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg, + [SLAVE_AHB2PHY] = &qhs_ahb2phy0, + [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2, + [SLAVE_AOSS] = &qhs_aoss, + [SLAVE_BOOT_ROM] = &qhs_boot_rom, + [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, + [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_thrott_cfg, + [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg, + [SLAVE_CLK_CTL] = &qhs_clk_ctl, + [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, + [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, + [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, + [SLAVE_DCC_CFG] = &qhs_dcc_cfg, + [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, + [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, + [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg, + [SLAVE_EMMC_CFG] = &qhs_emmc_cfg, + [SLAVE_GLM] = &qhs_glm, + [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg, + [SLAVE_IMEM_CFG] = &qhs_imem_cfg, + [SLAVE_IPA_CFG] = &qhs_ipa, + [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, + [SLAVE_CNOC_MSS] = &qhs_mss_cfg, + [SLAVE_NPU_CFG] = &qhs_npu_cfg, + [SLAVE_PDM] = &qhs_pdm, + [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, + [SLAVE_PRNG] = &qhs_prng, + [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, + [SLAVE_QM_CFG] = &qhs_qm_cfg, + [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg, + [SLAVE_QUP_0] = &qhs_qup0, + [SLAVE_QUP_1] = &qhs_qup1, + [SLAVE_SDCC_2] = &qhs_sdc2, + [SLAVE_SECURITY] = &qhs_security, + [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, + [SLAVE_TCSR] = &qhs_tcsr, + [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, + [SLAVE_USB3] = &qhs_usb3_0, + [SLAVE_VENUS_CFG] = &qhs_venus_cfg, + [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg, + [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, + [SLAVE_SERVICE_CNOC] = &srvc_cnoc, +}; + +static const struct qcom_icc_desc sm6350_config_noc = { + .nodes = config_noc_nodes, + .num_nodes = ARRAY_SIZE(config_noc_nodes), + .bcms = config_noc_bcms, + .num_bcms = ARRAY_SIZE(config_noc_bcms), +}; + +static struct qcom_icc_bcm * const dc_noc_bcms[] = { +}; + +static struct qcom_icc_node * const dc_noc_nodes[] = { + [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc, + [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc, + [SLAVE_LLCC_CFG] = &qhs_llcc, +}; + +static const struct qcom_icc_desc sm6350_dc_noc = { + .nodes = dc_noc_nodes, + .num_nodes = ARRAY_SIZE(dc_noc_nodes), + .bcms = dc_noc_bcms, + .num_bcms = ARRAY_SIZE(dc_noc_bcms), +}; + +static struct qcom_icc_bcm * const gem_noc_bcms[] = { + &bcm_sh0, + &bcm_sh2, + &bcm_sh3, + &bcm_sh4, +}; + +static struct qcom_icc_node * const gem_noc_nodes[] = { + [MASTER_AMPSS_M0] = &acm_apps, + [MASTER_SYS_TCU] = &acm_sys_tcu, + [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg, + [MASTER_COMPUTE_NOC] = &qnm_cmpnoc, + [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, + [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, + [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, + [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, + [MASTER_GRAPHICS_3D] = &qxm_gpu, + [SLAVE_MCDMA_MS_MPU_CFG] = &qhs_mcdma_ms_mpu_cfg, + [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, + [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc, + [SLAVE_LLCC] = &qns_llcc, + [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, +}; + +static const struct qcom_icc_desc sm6350_gem_noc = { + .nodes = gem_noc_nodes, + .num_nodes = ARRAY_SIZE(gem_noc_nodes), + .bcms = gem_noc_bcms, + .num_bcms = ARRAY_SIZE(gem_noc_bcms), +}; + +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { + &bcm_mm0, + &bcm_mm1, + &bcm_mm2, + &bcm_mm3, +}; + +static struct qcom_icc_node * const mmss_noc_nodes[] = { + [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, + [MASTER_VIDEO_P0] = &qnm_video0, + [MASTER_VIDEO_PROC] = &qnm_video_cvp, + [MASTER_CAMNOC_HF] = &qxm_camnoc_hf, + [MASTER_CAMNOC_ICP] = &qxm_camnoc_icp, + [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, + [MASTER_MDP_PORT0] = &qxm_mdp0, + [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, + [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, + [SLAVE_SERVICE_MNOC] = &srvc_mnoc, +}; + +static const struct qcom_icc_desc sm6350_mmss_noc = { + .nodes = mmss_noc_nodes, + .num_nodes = ARRAY_SIZE(mmss_noc_nodes), + .bcms = mmss_noc_bcms, + .num_bcms = ARRAY_SIZE(mmss_noc_bcms), +}; + +static struct qcom_icc_bcm * const npu_noc_bcms[] = { +}; + +static struct qcom_icc_node * const npu_noc_nodes[] = { + [MASTER_NPU_SYS] = &amm_npu_sys, + [MASTER_NPU_NOC_CFG] = &qhm_npu_cfg, + [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0, + [SLAVE_NPU_CP] = &qhs_cp, + [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon, + [SLAVE_NPU_DPM] = &qhs_dpm, + [SLAVE_ISENSE_CFG] = &qhs_isense, + [SLAVE_NPU_LLM_CFG] = &qhs_llm, + [SLAVE_NPU_TCM] = &qhs_tcm, + [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys, + [SLAVE_SERVICE_NPU_NOC] = &srvc_noc, +}; + +static const struct qcom_icc_desc sm6350_npu_noc = { + .nodes = npu_noc_nodes, + .num_nodes = ARRAY_SIZE(npu_noc_nodes), + .bcms = npu_noc_bcms, + .num_bcms = ARRAY_SIZE(npu_noc_bcms), +}; + +static struct qcom_icc_bcm * const system_noc_bcms[] = { + &bcm_sn0, + &bcm_sn1, + &bcm_sn10, + &bcm_sn2, + &bcm_sn3, + &bcm_sn4, + &bcm_sn5, + &bcm_sn6, +}; + +static struct qcom_icc_node * const system_noc_nodes[] = { + [MASTER_SNOC_CFG] = &qhm_snoc_cfg, + [A1NOC_SNOC_MAS] = &qnm_aggre1_noc, + [A2NOC_SNOC_MAS] = &qnm_aggre2_noc, + [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc, + [MASTER_PIMEM] = &qxm_pimem, + [MASTER_GIC] = &xm_gic, + [SLAVE_APPSS] = &qhs_apss, + [SNOC_CNOC_SLV] = &qns_cnoc, + [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, + [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, + [SLAVE_OCIMEM] = &qxs_imem, + [SLAVE_PIMEM] = &qxs_pimem, + [SLAVE_SERVICE_SNOC] = &srvc_snoc, + [SLAVE_QDSS_STM] = &xs_qdss_stm, + [SLAVE_TCU] = &xs_sys_tcu_cfg, +}; + +static const struct qcom_icc_desc sm6350_system_noc = { + .nodes = system_noc_nodes, + .num_nodes = ARRAY_SIZE(system_noc_nodes), + .bcms = system_noc_bcms, + .num_bcms = ARRAY_SIZE(system_noc_bcms), +}; + +static const struct of_device_id qnoc_of_match[] = { + { .compatible = "qcom,sm6350-aggre1-noc", + .data = &sm6350_aggre1_noc}, + { .compatible = "qcom,sm6350-aggre2-noc", + .data = &sm6350_aggre2_noc}, + { .compatible = "qcom,sm6350-clk-virt", + .data = &sm6350_clk_virt}, + { .compatible = "qcom,sm6350-compute-noc", + .data = &sm6350_compute_noc}, + { .compatible = "qcom,sm6350-config-noc", + .data = &sm6350_config_noc}, + { .compatible = "qcom,sm6350-dc-noc", + .data = &sm6350_dc_noc}, + { .compatible = "qcom,sm6350-gem-noc", + .data = &sm6350_gem_noc}, + { .compatible = "qcom,sm6350-mmss-noc", + .data = &sm6350_mmss_noc}, + { .compatible = "qcom,sm6350-npu-noc", + .data = &sm6350_npu_noc}, + { .compatible = "qcom,sm6350-system-noc", + .data = &sm6350_system_noc}, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver = { + .probe = qcom_icc_rpmh_probe, + .remove = qcom_icc_rpmh_remove, + .driver = { + .name = "qnoc-sm6350", + .of_match_table = qnoc_of_match, + .sync_state = icc_sync_state, + }, +}; +module_platform_driver(qnoc_driver); + +MODULE_DESCRIPTION("Qualcomm SM6350 NoC driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/interconnect/qcom/sm6350.h b/drivers/interconnect/qcom/sm6350.h new file mode 100644 index 000000000000..43cf2930c88a --- /dev/null +++ b/drivers/interconnect/qcom/sm6350.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Qualcomm #define SM6350 interconnect IDs + * + * Copyright (C) 2022 Luca Weiss + */ + +#ifndef __DRIVERS_INTERCONNECT_QCOM_SM6350_H +#define __DRIVERS_INTERCONNECT_QCOM_SM6350_H + +#define SM6350_A1NOC_SNOC_MAS 0 +#define SM6350_A1NOC_SNOC_SLV 1 +#define SM6350_A2NOC_SNOC_MAS 2 +#define SM6350_A2NOC_SNOC_SLV 3 +#define SM6350_MASTER_A1NOC_CFG 4 +#define SM6350_MASTER_A2NOC_CFG 5 +#define SM6350_MASTER_AMPSS_M0 6 +#define SM6350_MASTER_CAMNOC_HF 7 +#define SM6350_MASTER_CAMNOC_HF0_UNCOMP 8 +#define SM6350_MASTER_CAMNOC_ICP 9 +#define SM6350_MASTER_CAMNOC_ICP_UNCOMP 10 +#define SM6350_MASTER_CAMNOC_SF 11 +#define SM6350_MASTER_CAMNOC_SF_UNCOMP 12 +#define SM6350_MASTER_CNOC_DC_NOC 13 +#define SM6350_MASTER_CNOC_MNOC_CFG 14 +#define SM6350_MASTER_COMPUTE_NOC 15 +#define SM6350_MASTER_CRYPTO_CORE_0 16 +#define SM6350_MASTER_EMMC 17 +#define SM6350_MASTER_GEM_NOC_CFG 18 +#define SM6350_MASTER_GEM_NOC_SNOC 19 +#define SM6350_MASTER_GIC 20 +#define SM6350_MASTER_GRAPHICS_3D 21 +#define SM6350_MASTER_IPA 22 +#define SM6350_MASTER_LLCC 23 +#define SM6350_MASTER_MDP_PORT0 24 +#define SM6350_MASTER_MNOC_HF_MEM_NOC 25 +#define SM6350_MASTER_MNOC_SF_MEM_NOC 26 +#define SM6350_MASTER_NPU 27 +#define SM6350_MASTER_NPU_NOC_CFG 28 +#define SM6350_MASTER_NPU_PROC 29 +#define SM6350_MASTER_NPU_SYS 30 +#define SM6350_MASTER_PIMEM 31 +#define SM6350_MASTER_QDSS_BAM 32 +#define SM6350_MASTER_QDSS_DAP 33 +#define SM6350_MASTER_QDSS_ETR 34 +#define SM6350_MASTER_QUP_0 35 +#define SM6350_MASTER_QUP_1 36 +#define SM6350_MASTER_QUP_CORE_0 37 +#define SM6350_MASTER_QUP_CORE_1 38 +#define SM6350_MASTER_SDCC_2 39 +#define SM6350_MASTER_SNOC_CFG 40 +#define SM6350_MASTER_SNOC_GC_MEM_NOC 41 +#define SM6350_MASTER_SNOC_SF_MEM_NOC 42 +#define SM6350_MASTER_SYS_TCU 43 +#define SM6350_MASTER_UFS_MEM 44 +#define SM6350_MASTER_USB3 45 +#define SM6350_MASTER_VIDEO_P0 46 +#define SM6350_MASTER_VIDEO_PROC 47 +#define SM6350_SLAVE_A1NOC_CFG 48 +#define SM6350_SLAVE_A2NOC_CFG 49 +#define SM6350_SLAVE_AHB2PHY 50 +#define SM6350_SLAVE_AHB2PHY_2 51 +#define SM6350_SLAVE_AOSS 52 +#define SM6350_SLAVE_APPSS 53 +#define SM6350_SLAVE_BOOT_ROM 54 +#define SM6350_SLAVE_CAMERA_CFG 55 +#define SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG 56 +#define SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG 57 +#define SM6350_SLAVE_CAMNOC_UNCOMP 58 +#define SM6350_SLAVE_CDSP_GEM_NOC 59 +#define SM6350_SLAVE_CLK_CTL 60 +#define SM6350_SLAVE_CNOC_DDRSS 61 +#define SM6350_SLAVE_CNOC_MNOC_CFG 62 +#define SM6350_SLAVE_CNOC_MSS 63 +#define SM6350_SLAVE_CRYPTO_0_CFG 64 +#define SM6350_SLAVE_DCC_CFG 65 +#define SM6350_SLAVE_DISPLAY_CFG 66 +#define SM6350_SLAVE_DISPLAY_THROTTLE_CFG 67 +#define SM6350_SLAVE_EBI_CH0 68 +#define SM6350_SLAVE_EMMC_CFG 69 +#define SM6350_SLAVE_GEM_NOC_CFG 70 +#define SM6350_SLAVE_GEM_NOC_SNOC 71 +#define SM6350_SLAVE_GLM 72 +#define SM6350_SLAVE_GRAPHICS_3D_CFG 73 +#define SM6350_SLAVE_IMEM_CFG 74 +#define SM6350_SLAVE_IPA_CFG 75 +#define SM6350_SLAVE_ISENSE_CFG 76 +#define SM6350_SLAVE_LLCC 77 +#define SM6350_SLAVE_LLCC_CFG 78 +#define SM6350_SLAVE_MCDMA_MS_MPU_CFG 79 +#define SM6350_SLAVE_MNOC_HF_MEM_NOC 80 +#define SM6350_SLAVE_MNOC_SF_MEM_NOC 81 +#define SM6350_SLAVE_MSS_PROC_MS_MPU_CFG 82 +#define SM6350_SLAVE_NPU_CAL_DP0 83 +#define SM6350_SLAVE_NPU_CFG 84 +#define SM6350_SLAVE_NPU_COMPUTE_NOC 85 +#define SM6350_SLAVE_NPU_CP 86 +#define SM6350_SLAVE_NPU_DPM 87 +#define SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG 88 +#define SM6350_SLAVE_NPU_LLM_CFG 89 +#define SM6350_SLAVE_NPU_TCM 90 +#define SM6350_SLAVE_OCIMEM 91 +#define SM6350_SLAVE_PDM 92 +#define SM6350_SLAVE_PIMEM 93 +#define SM6350_SLAVE_PIMEM_CFG 94 +#define SM6350_SLAVE_PRNG 95 +#define SM6350_SLAVE_QDSS_CFG 96 +#define SM6350_SLAVE_QDSS_STM 97 +#define SM6350_SLAVE_QM_CFG 98 +#define SM6350_SLAVE_QM_MPU_CFG 99 +#define SM6350_SLAVE_QUP_0 100 +#define SM6350_SLAVE_QUP_1 101 +#define SM6350_SLAVE_QUP_CORE_0 102 +#define SM6350_SLAVE_QUP_CORE_1 103 +#define SM6350_SLAVE_RBCPR_CX_CFG 104 +#define SM6350_SLAVE_RBCPR_MX_CFG 105 +#define SM6350_SLAVE_SDCC_2 106 +#define SM6350_SLAVE_SECURITY 107 +#define SM6350_SLAVE_SERVICE_A1NOC 108 +#define SM6350_SLAVE_SERVICE_A2NOC 109 +#define SM6350_SLAVE_SERVICE_CNOC 110 +#define SM6350_SLAVE_SERVICE_GEM_NOC 111 +#define SM6350_SLAVE_SERVICE_MNOC 112 +#define SM6350_SLAVE_SERVICE_NPU_NOC 113 +#define SM6350_SLAVE_SERVICE_SNOC 114 +#define SM6350_SLAVE_SNOC_CFG 115 +#define SM6350_SLAVE_SNOC_GEM_NOC_GC 116 +#define SM6350_SLAVE_SNOC_GEM_NOC_SF 117 +#define SM6350_SLAVE_TCSR 118 +#define SM6350_SLAVE_TCU 119 +#define SM6350_SLAVE_UFS_MEM_CFG 120 +#define SM6350_SLAVE_USB3 121 +#define SM6350_SLAVE_VENUS_CFG 122 +#define SM6350_SLAVE_VENUS_THROTTLE_CFG 123 +#define SM6350_SLAVE_VSENSE_CTRL_CFG 124 +#define SM6350_SNOC_CNOC_MAS 125 +#define SM6350_SNOC_CNOC_SLV 126 + +#endif diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom/sm8450.c index 7e3d372b712f..e821fd0b2f66 100644 --- a/drivers/interconnect/qcom/sm8450.c +++ b/drivers/interconnect/qcom/sm8450.c @@ -12,6 +12,7 @@ #include #include "bcm-voter.h" +#include "icc-common.h" #include "icc-rpmh.h" #include "sm8450.h" diff --git a/drivers/mcb/mcb-core.c b/drivers/mcb/mcb-core.c index cf128b3471d7..338fc889b357 100644 --- a/drivers/mcb/mcb-core.c +++ b/drivers/mcb/mcb-core.c @@ -254,7 +254,7 @@ static void mcb_free_bus(struct device *dev) struct mcb_bus *bus = to_mcb_bus(dev); put_device(bus->carrier); - ida_simple_remove(&mcb_ida, bus->bus_nr); + ida_free(&mcb_ida, bus->bus_nr); kfree(bus); } @@ -273,7 +273,7 @@ struct mcb_bus *mcb_alloc_bus(struct device *carrier) if (!bus) return ERR_PTR(-ENOMEM); - bus_nr = ida_simple_get(&mcb_ida, 0, 0, GFP_KERNEL); + bus_nr = ida_alloc(&mcb_ida, GFP_KERNEL); if (bus_nr < 0) { kfree(bus); return ERR_PTR(bus_nr); diff --git a/drivers/mfd/intel-m10-bmc.c b/drivers/mfd/intel-m10-bmc.c index 8db3bcf5fccc..f4d0d72573c8 100644 --- a/drivers/mfd/intel-m10-bmc.c +++ b/drivers/mfd/intel-m10-bmc.c @@ -26,7 +26,7 @@ static struct mfd_cell m10bmc_d5005_subdevs[] = { static struct mfd_cell m10bmc_pacn3000_subdevs[] = { { .name = "n3000bmc-hwmon" }, { .name = "n3000bmc-retimer" }, - { .name = "n3000bmc-secure" }, + { .name = "n3000bmc-sec-update" }, }; static struct mfd_cell m10bmc_n5010_subdevs[] = { diff --git a/drivers/mfd/qcom-spmi-pmic.c b/drivers/mfd/qcom-spmi-pmic.c index 1cacc00aa6c9..00003a868d28 100644 --- a/drivers/mfd/qcom-spmi-pmic.c +++ b/drivers/mfd/qcom-spmi-pmic.c @@ -3,137 +3,217 @@ * Copyright (c) 2014, The Linux Foundation. All rights reserved. */ +#include +#include +#include #include #include #include +#include #include #include +#include #define PMIC_REV2 0x101 #define PMIC_REV3 0x102 #define PMIC_REV4 0x103 #define PMIC_TYPE 0x104 #define PMIC_SUBTYPE 0x105 +#define PMIC_FAB_ID 0x1f2 #define PMIC_TYPE_VALUE 0x51 -#define COMMON_SUBTYPE 0x00 -#define PM8941_SUBTYPE 0x01 -#define PM8841_SUBTYPE 0x02 -#define PM8019_SUBTYPE 0x03 -#define PM8226_SUBTYPE 0x04 -#define PM8110_SUBTYPE 0x05 -#define PMA8084_SUBTYPE 0x06 -#define PMI8962_SUBTYPE 0x07 -#define PMD9635_SUBTYPE 0x08 -#define PM8994_SUBTYPE 0x09 -#define PMI8994_SUBTYPE 0x0a -#define PM8916_SUBTYPE 0x0b -#define PM8004_SUBTYPE 0x0c -#define PM8909_SUBTYPE 0x0d -#define PM8028_SUBTYPE 0x0e -#define PM8901_SUBTYPE 0x0f -#define PM8950_SUBTYPE 0x10 -#define PMI8950_SUBTYPE 0x11 -#define PM8998_SUBTYPE 0x14 -#define PMI8998_SUBTYPE 0x15 -#define PM8005_SUBTYPE 0x18 -#define PM660L_SUBTYPE 0x1A -#define PM660_SUBTYPE 0x1B -#define PM8150_SUBTYPE 0x1E -#define PM8150L_SUBTYPE 0x1f -#define PM8150B_SUBTYPE 0x20 -#define PMK8002_SUBTYPE 0x21 -#define PM8009_SUBTYPE 0x24 -#define PM8150C_SUBTYPE 0x26 -#define SMB2351_SUBTYPE 0x29 +#define PMIC_REV4_V2 0x02 + +struct qcom_spmi_dev { + int num_usids; + struct qcom_spmi_pmic pmic; +}; + +#define N_USIDS(n) ((void *)n) static const struct of_device_id pmic_spmi_id_table[] = { - { .compatible = "qcom,pm660", .data = (void *)PM660_SUBTYPE }, - { .compatible = "qcom,pm660l", .data = (void *)PM660L_SUBTYPE }, - { .compatible = "qcom,pm8004", .data = (void *)PM8004_SUBTYPE }, - { .compatible = "qcom,pm8005", .data = (void *)PM8005_SUBTYPE }, - { .compatible = "qcom,pm8019", .data = (void *)PM8019_SUBTYPE }, - { .compatible = "qcom,pm8028", .data = (void *)PM8028_SUBTYPE }, - { .compatible = "qcom,pm8110", .data = (void *)PM8110_SUBTYPE }, - { .compatible = "qcom,pm8150", .data = (void *)PM8150_SUBTYPE }, - { .compatible = "qcom,pm8150b", .data = (void *)PM8150B_SUBTYPE }, - { .compatible = "qcom,pm8150c", .data = (void *)PM8150C_SUBTYPE }, - { .compatible = "qcom,pm8150l", .data = (void *)PM8150L_SUBTYPE }, - { .compatible = "qcom,pm8226", .data = (void *)PM8226_SUBTYPE }, - { .compatible = "qcom,pm8841", .data = (void *)PM8841_SUBTYPE }, - { .compatible = "qcom,pm8901", .data = (void *)PM8901_SUBTYPE }, - { .compatible = "qcom,pm8909", .data = (void *)PM8909_SUBTYPE }, - { .compatible = "qcom,pm8916", .data = (void *)PM8916_SUBTYPE }, - { .compatible = "qcom,pm8941", .data = (void *)PM8941_SUBTYPE }, - { .compatible = "qcom,pm8950", .data = (void *)PM8950_SUBTYPE }, - { .compatible = "qcom,pm8994", .data = (void *)PM8994_SUBTYPE }, - { .compatible = "qcom,pm8998", .data = (void *)PM8998_SUBTYPE }, - { .compatible = "qcom,pma8084", .data = (void *)PMA8084_SUBTYPE }, - { .compatible = "qcom,pmd9635", .data = (void *)PMD9635_SUBTYPE }, - { .compatible = "qcom,pmi8950", .data = (void *)PMI8950_SUBTYPE }, - { .compatible = "qcom,pmi8962", .data = (void *)PMI8962_SUBTYPE }, - { .compatible = "qcom,pmi8994", .data = (void *)PMI8994_SUBTYPE }, - { .compatible = "qcom,pmi8998", .data = (void *)PMI8998_SUBTYPE }, - { .compatible = "qcom,pmk8002", .data = (void *)PMK8002_SUBTYPE }, - { .compatible = "qcom,smb2351", .data = (void *)SMB2351_SUBTYPE }, - { .compatible = "qcom,spmi-pmic", .data = (void *)COMMON_SUBTYPE }, + { .compatible = "qcom,pm660", .data = N_USIDS(2) }, + { .compatible = "qcom,pm660l", .data = N_USIDS(2) }, + { .compatible = "qcom,pm8004", .data = N_USIDS(2) }, + { .compatible = "qcom,pm8005", .data = N_USIDS(2) }, + { .compatible = "qcom,pm8019", .data = N_USIDS(2) }, + { .compatible = "qcom,pm8028", .data = N_USIDS(2) }, + { .compatible = "qcom,pm8110", .data = N_USIDS(2) }, + { .compatible = "qcom,pm8150", .data = N_USIDS(2) }, + { .compatible = "qcom,pm8150b", .data = N_USIDS(2) }, + { .compatible = "qcom,pm8150c", .data = N_USIDS(2) }, + { .compatible = "qcom,pm8150l", .data = N_USIDS(2) }, + { .compatible = "qcom,pm8226", .data = N_USIDS(2) }, + { .compatible = "qcom,pm8841", .data = N_USIDS(2) }, + { .compatible = "qcom,pm8901", .data = N_USIDS(2) }, + { .compatible = "qcom,pm8909", .data = N_USIDS(2) }, + { .compatible = "qcom,pm8916", .data = N_USIDS(2) }, + { .compatible = "qcom,pm8941", .data = N_USIDS(2) }, + { .compatible = "qcom,pm8950", .data = N_USIDS(2) }, + { .compatible = "qcom,pm8994", .data = N_USIDS(2) }, + { .compatible = "qcom,pm8998", .data = N_USIDS(2) }, + { .compatible = "qcom,pma8084", .data = N_USIDS(2) }, + { .compatible = "qcom,pmd9635", .data = N_USIDS(2) }, + { .compatible = "qcom,pmi8950", .data = N_USIDS(2) }, + { .compatible = "qcom,pmi8962", .data = N_USIDS(2) }, + { .compatible = "qcom,pmi8994", .data = N_USIDS(2) }, + { .compatible = "qcom,pmi8998", .data = N_USIDS(2) }, + { .compatible = "qcom,pmk8002", .data = N_USIDS(2) }, + { .compatible = "qcom,smb2351", .data = N_USIDS(2) }, + { .compatible = "qcom,spmi-pmic", .data = N_USIDS(1) }, { } }; -static void pmic_spmi_show_revid(struct regmap *map, struct device *dev) +/* + * A PMIC can be represented by multiple SPMI devices, but + * only the base PMIC device will contain a reference to + * the revision information. + * + * This function takes a pointer to a pmic device and + * returns a pointer to the base PMIC device. + * + * This only supports PMICs with 1 or 2 USIDs. + */ +static struct spmi_device *qcom_pmic_get_base_usid(struct device *dev) { - unsigned int rev2, minor, major, type, subtype; - const char *name = "unknown"; - int ret, i; + struct spmi_device *sdev; + struct qcom_spmi_dev *ctx; + struct device_node *spmi_bus; + struct device_node *other_usid = NULL; + int function_parent_usid, ret; + u32 pmic_addr; - ret = regmap_read(map, PMIC_TYPE, &type); + sdev = to_spmi_device(dev); + ctx = dev_get_drvdata(&sdev->dev); + + /* + * Quick return if the function device is already in the base + * USID. This will always be hit for PMICs with only 1 USID. + */ + if (sdev->usid % ctx->num_usids == 0) + return sdev; + + function_parent_usid = sdev->usid; + + /* + * Walk through the list of PMICs until we find the sibling USID. + * The goal is to find the first USID which is less than the + * number of USIDs in the PMIC array, e.g. for a PMIC with 2 USIDs + * where the function device is under USID 3, we want to find the + * device for USID 2. + */ + spmi_bus = of_get_parent(sdev->dev.of_node); + do { + other_usid = of_get_next_child(spmi_bus, other_usid); + + ret = of_property_read_u32_index(other_usid, "reg", 0, &pmic_addr); + if (ret) + return ERR_PTR(ret); + + sdev = spmi_device_from_of(other_usid); + if (pmic_addr == function_parent_usid - (ctx->num_usids - 1)) { + if (!sdev) + /* + * If the base USID for this PMIC hasn't probed yet + * but the secondary USID has, then we need to defer + * the function driver so that it will attempt to + * probe again when the base USID is ready. + */ + return ERR_PTR(-EPROBE_DEFER); + return sdev; + } + } while (other_usid->sibling); + + return ERR_PTR(-ENODATA); +} + +static int pmic_spmi_load_revid(struct regmap *map, struct device *dev, + struct qcom_spmi_pmic *pmic) +{ + int ret; + + ret = regmap_read(map, PMIC_TYPE, &pmic->type); if (ret < 0) - return; + return ret; - if (type != PMIC_TYPE_VALUE) - return; + if (pmic->type != PMIC_TYPE_VALUE) + return ret; - ret = regmap_read(map, PMIC_SUBTYPE, &subtype); + ret = regmap_read(map, PMIC_SUBTYPE, &pmic->subtype); if (ret < 0) - return; + return ret; - for (i = 0; i < ARRAY_SIZE(pmic_spmi_id_table); i++) { - if (subtype == (unsigned long)pmic_spmi_id_table[i].data) - break; + pmic->name = of_match_device(pmic_spmi_id_table, dev)->compatible; + + ret = regmap_read(map, PMIC_REV2, &pmic->rev2); + if (ret < 0) + return ret; + + ret = regmap_read(map, PMIC_REV3, &pmic->minor); + if (ret < 0) + return ret; + + ret = regmap_read(map, PMIC_REV4, &pmic->major); + if (ret < 0) + return ret; + + if (pmic->subtype == PMI8998_SUBTYPE || pmic->subtype == PM660_SUBTYPE) { + ret = regmap_read(map, PMIC_FAB_ID, &pmic->fab_id); + if (ret < 0) + return ret; } - if (i != ARRAY_SIZE(pmic_spmi_id_table)) - name = pmic_spmi_id_table[i].compatible; - - ret = regmap_read(map, PMIC_REV2, &rev2); - if (ret < 0) - return; - - ret = regmap_read(map, PMIC_REV3, &minor); - if (ret < 0) - return; - - ret = regmap_read(map, PMIC_REV4, &major); - if (ret < 0) - return; - /* * In early versions of PM8941 and PM8226, the major revision number * started incrementing from 0 (eg 0 = v1.0, 1 = v2.0). * Increment the major revision number here if the chip is an early * version of PM8941 or PM8226. */ - if ((subtype == PM8941_SUBTYPE || subtype == PM8226_SUBTYPE) && - major < 0x02) - major++; + if ((pmic->subtype == PM8941_SUBTYPE || pmic->subtype == PM8226_SUBTYPE) && + pmic->major < PMIC_REV4_V2) + pmic->major++; - if (subtype == PM8110_SUBTYPE) - minor = rev2; + if (pmic->subtype == PM8110_SUBTYPE) + pmic->minor = pmic->rev2; - dev_dbg(dev, "%x: %s v%d.%d\n", subtype, name, major, minor); + dev_dbg(dev, "%x: %s v%d.%d\n", + pmic->subtype, pmic->name, pmic->major, pmic->minor); + + return 0; } +/** + * qcom_pmic_get() - Get a pointer to the base PMIC device + * + * This function takes a struct device for a driver which is a child of a PMIC. + * And locates the PMIC revision information for it. + * + * @dev: the pmic function device + * @return: the struct qcom_spmi_pmic* pointer associated with the function device + */ +const struct qcom_spmi_pmic *qcom_pmic_get(struct device *dev) +{ + struct spmi_device *sdev; + struct qcom_spmi_dev *spmi; + + /* + * Make sure the device is actually a child of a PMIC + */ + if (!of_match_device(pmic_spmi_id_table, dev->parent)) + return ERR_PTR(-EINVAL); + + sdev = qcom_pmic_get_base_usid(dev->parent); + + if (IS_ERR(sdev)) + return ERR_CAST(sdev); + + spmi = dev_get_drvdata(&sdev->dev); + + return &spmi->pmic; +} +EXPORT_SYMBOL(qcom_pmic_get); + static const struct regmap_config spmi_regmap_config = { .reg_bits = 16, .val_bits = 8, @@ -144,14 +224,26 @@ static const struct regmap_config spmi_regmap_config = { static int pmic_spmi_probe(struct spmi_device *sdev) { struct regmap *regmap; + struct qcom_spmi_dev *ctx; + int ret; regmap = devm_regmap_init_spmi_ext(sdev, &spmi_regmap_config); if (IS_ERR(regmap)) return PTR_ERR(regmap); + ctx = devm_kzalloc(&sdev->dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->num_usids = (uintptr_t)of_device_get_match_data(&sdev->dev); + /* Only the first slave id for a PMIC contains this information */ - if (sdev->usid % 2 == 0) - pmic_spmi_show_revid(regmap, &sdev->dev); + if (sdev->usid % ctx->num_usids == 0) { + ret = pmic_spmi_load_revid(regmap, &sdev->dev, &ctx->pmic); + if (ret < 0) + return ret; + } + spmi_device_set_drvdata(sdev, ctx); return devm_of_platform_populate(&sdev->dev); } diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 41d2bb0ae23a..94e9fb4cdd76 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -483,6 +483,19 @@ config OPEN_DICE If unsure, say N. +config VCPU_STALL_DETECTOR + tristate "Guest vCPU stall detector" + depends on OF && HAS_IOMEM + help + When this driver is bound inside a KVM guest, it will + periodically "pet" an MMIO stall detector device from each vCPU + and allow the host to detect vCPU stalls. + + To compile this driver as a module, choose M here: the module + will be called vcpu_stall_detector. + + If you do not intend to run this kernel as a guest, say N. + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 70e800e9127f..2be8542616dd 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -60,3 +60,4 @@ obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o obj-$(CONFIG_HI6421V600_IRQ) += hi6421v600-irq.o obj-$(CONFIG_OPEN_DICE) += open-dice.o +obj-$(CONFIG_VCPU_STALL_DETECTOR) += vcpu_stall_detector.o \ No newline at end of file diff --git a/drivers/misc/cardreader/rtsx_pcr.c b/drivers/misc/cardreader/rtsx_pcr.c index 2a2619e3c72c..32b7783e9d4f 100644 --- a/drivers/misc/cardreader/rtsx_pcr.c +++ b/drivers/misc/cardreader/rtsx_pcr.c @@ -131,7 +131,7 @@ static void rtsx_comm_pm_full_on(struct rtsx_pcr *pcr) rtsx_disable_aspm(pcr); - /* Fixes DMA transfer timout issue after disabling ASPM on RTS5260 */ + /* Fixes DMA transfer timeout issue after disabling ASPM on RTS5260 */ msleep(1); if (option->ltr_enabled) @@ -1507,7 +1507,7 @@ static int rtsx_pci_probe(struct pci_dev *pcidev, pcr->remap_addr = ioremap(base, len); if (!pcr->remap_addr) { ret = -ENOMEM; - goto free_handle; + goto free_idr; } pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev), @@ -1570,6 +1570,10 @@ disable_msi: pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr); unmap: iounmap(pcr->remap_addr); +free_idr: + spin_lock(&rtsx_pci_lock); + idr_remove(&rtsx_pci_idr, pcr->id); + spin_unlock(&rtsx_pci_lock); free_handle: kfree(handle); free_pcr: diff --git a/drivers/misc/cxl/context.c b/drivers/misc/cxl/context.c index e627b4056623..acaa44809c58 100644 --- a/drivers/misc/cxl/context.c +++ b/drivers/misc/cxl/context.c @@ -331,7 +331,7 @@ static void reclaim_ctx(struct rcu_head *rcu) __free_page(ctx->ff_page); ctx->sstp = NULL; - kfree(ctx->irq_bitmap); + bitmap_free(ctx->irq_bitmap); /* Drop ref to the afu device taken during cxl_context_init */ cxl_afu_put(ctx->afu); diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h index 7a6dd91987fd..0562071cdd4a 100644 --- a/drivers/misc/cxl/cxl.h +++ b/drivers/misc/cxl/cxl.h @@ -1104,7 +1104,7 @@ extern const struct cxl_backend_ops cxl_native_ops; extern const struct cxl_backend_ops cxl_guest_ops; extern const struct cxl_backend_ops *cxl_ops; -/* check if the given pci_dev is on the the cxl vphb bus */ +/* check if the given pci_dev is on the cxl vphb bus */ bool cxl_pci_is_vphb_device(struct pci_dev *dev); /* decode AFU error bits in the PSL register PSL_SERR_An */ diff --git a/drivers/misc/cxl/guest.c b/drivers/misc/cxl/guest.c index 3321c014913c..375f692ae9d6 100644 --- a/drivers/misc/cxl/guest.c +++ b/drivers/misc/cxl/guest.c @@ -1053,7 +1053,7 @@ static void free_adapter(struct cxl *adapter) if (adapter->guest->irq_avail) { for (i = 0; i < adapter->guest->irq_nranges; i++) { cur = &adapter->guest->irq_avail[i]; - kfree(cur->bitmap); + bitmap_free(cur->bitmap); } kfree(adapter->guest->irq_avail); } diff --git a/drivers/misc/cxl/irq.c b/drivers/misc/cxl/irq.c index 5f0e2dcebb34..b730e022a48e 100644 --- a/drivers/misc/cxl/irq.c +++ b/drivers/misc/cxl/irq.c @@ -319,8 +319,7 @@ int afu_allocate_irqs(struct cxl_context *ctx, u32 count) } ctx->irq_count = count; - ctx->irq_bitmap = kcalloc(BITS_TO_LONGS(count), - sizeof(*ctx->irq_bitmap), GFP_KERNEL); + ctx->irq_bitmap = bitmap_zalloc(count, GFP_KERNEL); if (!ctx->irq_bitmap) goto out; @@ -350,6 +349,7 @@ int afu_allocate_irqs(struct cxl_context *ctx, u32 count) out: cxl_ops->release_irq_ranges(&ctx->irqs, ctx->afu->adapter); + bitmap_free(ctx->irq_bitmap); afu_irq_name_free(ctx); return -ENOMEM; } diff --git a/drivers/misc/cxl/of.c b/drivers/misc/cxl/of.c index 1cfecba42d01..25ce725035e7 100644 --- a/drivers/misc/cxl/of.c +++ b/drivers/misc/cxl/of.c @@ -308,8 +308,7 @@ static int read_adapter_irq_config(struct cxl *adapter, struct device_node *np) cur = &adapter->guest->irq_avail[i]; cur->offset = be32_to_cpu(ranges[i * 2]); cur->range = be32_to_cpu(ranges[i * 2 + 1]); - cur->bitmap = kcalloc(BITS_TO_LONGS(cur->range), - sizeof(*cur->bitmap), GFP_KERNEL); + cur->bitmap = bitmap_zalloc(cur->range, GFP_KERNEL); if (cur->bitmap == NULL) goto err; if (cur->offset < adapter->guest->irq_base_offset) @@ -326,7 +325,7 @@ static int read_adapter_irq_config(struct cxl *adapter, struct device_node *np) err: for (i--; i >= 0; i--) { cur = &adapter->guest->irq_avail[i]; - kfree(cur->bitmap); + bitmap_free(cur->bitmap); } kfree(adapter->guest->irq_avail); adapter->guest->irq_avail = NULL; diff --git a/drivers/misc/eeprom/idt_89hpesx.c b/drivers/misc/eeprom/idt_89hpesx.c index b0cff4b152da..9aec3338e37d 100644 --- a/drivers/misc/eeprom/idt_89hpesx.c +++ b/drivers/misc/eeprom/idt_89hpesx.c @@ -566,7 +566,7 @@ static int idt_eeprom_read_byte(struct idt_89hpesx_dev *pdev, u16 memaddr, eeseq.memaddr = cpu_to_le16(memaddr); ret = pdev->smb_write(pdev, &smbseq); if (ret != 0) { - dev_err(dev, "Failed to init eeprom addr 0x%02hhx", + dev_err(dev, "Failed to init eeprom addr 0x%02x", memaddr); break; } @@ -575,7 +575,7 @@ static int idt_eeprom_read_byte(struct idt_89hpesx_dev *pdev, u16 memaddr, smbseq.bytecnt = EEPROM_RD_CNT; ret = pdev->smb_read(pdev, &smbseq); if (ret != 0) { - dev_err(dev, "Failed to read eeprom data 0x%02hhx", + dev_err(dev, "Failed to read eeprom data 0x%02x", memaddr); break; } @@ -810,7 +810,7 @@ static int idt_csr_read(struct idt_89hpesx_dev *pdev, u16 csraddr, u32 *data) smbseq.bytecnt = CSR_RD_CNT; ret = pdev->smb_read(pdev, &smbseq); if (ret != 0) { - dev_err(dev, "Failed to read csr 0x%04hx", + dev_err(dev, "Failed to read csr 0x%04x", CSR_REAL_ADDR(csraddr)); goto err_mutex_unlock; } @@ -909,14 +909,18 @@ static ssize_t idt_dbgfs_csr_write(struct file *filep, const char __user *ubuf, u32 csraddr, csrval; char *buf; + if (*offp) + return 0; + /* Copy data from User-space */ buf = kmalloc(count + 1, GFP_KERNEL); if (!buf) return -ENOMEM; - ret = simple_write_to_buffer(buf, count, offp, ubuf, count); - if (ret < 0) + if (copy_from_user(buf, ubuf, count)) { + ret = -EFAULT; goto free_buf; + } buf[count] = 0; /* Find position of colon in the buffer */ diff --git a/drivers/misc/habanalabs/Makefile b/drivers/misc/habanalabs/Makefile index a786c0a7de9a..b35d7000c86b 100644 --- a/drivers/misc/habanalabs/Makefile +++ b/drivers/misc/habanalabs/Makefile @@ -14,4 +14,7 @@ habanalabs-y += $(HL_GOYA_FILES) include $(src)/gaudi/Makefile habanalabs-y += $(HL_GAUDI_FILES) +include $(src)/gaudi2/Makefile +habanalabs-y += $(HL_GAUDI2_FILES) + habanalabs-$(CONFIG_DEBUG_FS) += common/debugfs.o diff --git a/drivers/misc/habanalabs/common/Makefile b/drivers/misc/habanalabs/common/Makefile index 934a3a4aedc9..e6abffea9f87 100644 --- a/drivers/misc/habanalabs/common/Makefile +++ b/drivers/misc/habanalabs/common/Makefile @@ -11,4 +11,5 @@ HL_COMMON_FILES := common/habanalabs_drv.o common/device.o common/context.o \ common/command_buffer.o common/hw_queue.o common/irq.o \ common/sysfs.o common/hwmon.o common/memory.o \ common/command_submission.o common/firmware_if.o \ - common/state_dump.o common/memory_mgr.o + common/security.o common/state_dump.o \ + common/memory_mgr.o common/decoder.o diff --git a/drivers/misc/habanalabs/common/asid.c b/drivers/misc/habanalabs/common/asid.c index ede04c032b6e..c9c2619cc43d 100644 --- a/drivers/misc/habanalabs/common/asid.c +++ b/drivers/misc/habanalabs/common/asid.c @@ -11,8 +11,7 @@ int hl_asid_init(struct hl_device *hdev) { - hdev->asid_bitmap = kcalloc(BITS_TO_LONGS(hdev->asic_prop.max_asid), - sizeof(*hdev->asid_bitmap), GFP_KERNEL); + hdev->asid_bitmap = bitmap_zalloc(hdev->asic_prop.max_asid, GFP_KERNEL); if (!hdev->asid_bitmap) return -ENOMEM; @@ -27,7 +26,7 @@ int hl_asid_init(struct hl_device *hdev) void hl_asid_fini(struct hl_device *hdev) { mutex_destroy(&hdev->asid_mutex); - kfree(hdev->asid_bitmap); + bitmap_free(hdev->asid_bitmap); } unsigned long hl_asid_alloc(struct hl_device *hdev) diff --git a/drivers/misc/habanalabs/common/command_buffer.c b/drivers/misc/habanalabs/common/command_buffer.c index e13b2b39c058..b027f66f8bd4 100644 --- a/drivers/misc/habanalabs/common/command_buffer.c +++ b/drivers/misc/habanalabs/common/command_buffer.c @@ -143,8 +143,7 @@ static void cb_fini(struct hl_device *hdev, struct hl_cb *cb) gen_pool_free(hdev->internal_cb_pool, (uintptr_t)cb->kernel_address, cb->size); else - hdev->asic_funcs->asic_dma_free_coherent(hdev, cb->size, - cb->kernel_address, cb->bus_address); + hl_asic_dma_free_coherent(hdev, cb->size, cb->kernel_address, cb->bus_address); kfree(cb); } @@ -195,14 +194,11 @@ static struct hl_cb *hl_cb_alloc(struct hl_device *hdev, u32 cb_size, cb->is_internal = true; cb->bus_address = hdev->internal_cb_va_base + cb_offset; } else if (ctx_id == HL_KERNEL_ASID_ID) { - p = hdev->asic_funcs->asic_dma_alloc_coherent(hdev, cb_size, - &cb->bus_address, GFP_ATOMIC); + p = hl_asic_dma_alloc_coherent(hdev, cb_size, &cb->bus_address, GFP_ATOMIC); if (!p) - p = hdev->asic_funcs->asic_dma_alloc_coherent(hdev, - cb_size, &cb->bus_address, GFP_KERNEL); + p = hl_asic_dma_alloc_coherent(hdev, cb_size, &cb->bus_address, GFP_KERNEL); } else { - p = hdev->asic_funcs->asic_dma_alloc_coherent(hdev, cb_size, - &cb->bus_address, + p = hl_asic_dma_alloc_coherent(hdev, cb_size, &cb->bus_address, GFP_USER | __GFP_ZERO); } diff --git a/drivers/misc/habanalabs/common/command_submission.c b/drivers/misc/habanalabs/common/command_submission.c index fb30b7de4aab..90a4574cbe2d 100644 --- a/drivers/misc/habanalabs/common/command_submission.c +++ b/drivers/misc/habanalabs/common/command_submission.c @@ -12,7 +12,7 @@ #include #define HL_CS_FLAGS_TYPE_MASK (HL_CS_FLAGS_SIGNAL | HL_CS_FLAGS_WAIT | \ - HL_CS_FLAGS_COLLECTIVE_WAIT) + HL_CS_FLAGS_COLLECTIVE_WAIT) #define MAX_TS_ITER_NUM 10 @@ -29,11 +29,88 @@ enum hl_cs_wait_status { }; static void job_wq_completion(struct work_struct *work); -static int _hl_cs_wait_ioctl(struct hl_device *hdev, struct hl_ctx *ctx, - u64 timeout_us, u64 seq, +static int _hl_cs_wait_ioctl(struct hl_device *hdev, struct hl_ctx *ctx, u64 timeout_us, u64 seq, enum hl_cs_wait_status *status, s64 *timestamp); static void cs_do_release(struct kref *ref); +static void hl_push_cs_outcome(struct hl_device *hdev, + struct hl_cs_outcome_store *outcome_store, + u64 seq, ktime_t ts, int error) +{ + struct hl_cs_outcome *node; + unsigned long flags; + + /* + * CS outcome store supports the following operations: + * push outcome - store a recent CS outcome in the store + * pop outcome - retrieve a SPECIFIC (by seq) CS outcome from the store + * It uses 2 lists: used list and free list. + * It has a pre-allocated amount of nodes, each node stores + * a single CS outcome. + * Initially, all the nodes are in the free list. + * On push outcome, a node (any) is taken from the free list, its + * information is filled in, and the node is moved to the used list. + * It is possible, that there are no nodes left in the free list. + * In this case, we will lose some information about old outcomes. We + * will pop the OLDEST node from the used list, and make it free. + * On pop, the node is searched for in the used list (using a search + * index). + * If found, the node is then removed from the used list, and moved + * back to the free list. The outcome data that the node contained is + * returned back to the user. + */ + + spin_lock_irqsave(&outcome_store->db_lock, flags); + + if (list_empty(&outcome_store->free_list)) { + node = list_last_entry(&outcome_store->used_list, + struct hl_cs_outcome, list_link); + hash_del(&node->map_link); + dev_dbg(hdev->dev, "CS %llu outcome was lost\n", node->seq); + } else { + node = list_last_entry(&outcome_store->free_list, + struct hl_cs_outcome, list_link); + } + + list_del_init(&node->list_link); + + node->seq = seq; + node->ts = ts; + node->error = error; + + list_add(&node->list_link, &outcome_store->used_list); + hash_add(outcome_store->outcome_map, &node->map_link, node->seq); + + spin_unlock_irqrestore(&outcome_store->db_lock, flags); +} + +static bool hl_pop_cs_outcome(struct hl_cs_outcome_store *outcome_store, + u64 seq, ktime_t *ts, int *error) +{ + struct hl_cs_outcome *node; + unsigned long flags; + + spin_lock_irqsave(&outcome_store->db_lock, flags); + + hash_for_each_possible(outcome_store->outcome_map, node, map_link, seq) + if (node->seq == seq) { + *ts = node->ts; + *error = node->error; + + hash_del(&node->map_link); + list_del_init(&node->list_link); + list_add(&node->list_link, &outcome_store->free_list); + + spin_unlock_irqrestore(&outcome_store->db_lock, flags); + + return true; + } + + spin_unlock_irqrestore(&outcome_store->db_lock, flags); + + return false; +} + static void hl_sob_reset(struct kref *ref) { struct hl_hw_sob *hw_sob = container_of(ref, struct hl_hw_sob, @@ -171,7 +248,7 @@ static void cs_job_do_release(struct kref *ref) kfree(job); } -static void cs_job_put(struct hl_cs_job *job) +static void hl_cs_job_put(struct hl_cs_job *job) { kref_put(&job->refcount, cs_job_do_release); } @@ -266,7 +343,7 @@ static int cs_parser(struct hl_fpriv *hpriv, struct hl_cs_job *job) return rc; } -static void complete_job(struct hl_device *hdev, struct hl_cs_job *job) +static void hl_complete_job(struct hl_device *hdev, struct hl_cs_job *job) { struct hl_cs *cs = job->cs; @@ -285,12 +362,12 @@ static void complete_job(struct hl_device *hdev, struct hl_cs_job *job) /* For H/W queue jobs, if a user CB was allocated by driver and MMU is * enabled, the user CB isn't released in cs_parser() and thus should be - * released here. - * This is also true for INT queues jobs which were allocated by driver + * released here. This is also true for INT queues jobs which were + * allocated by driver. */ - if (job->is_kernel_allocated_cb && + if ((job->is_kernel_allocated_cb && ((job->queue_type == QUEUE_TYPE_HW && hdev->mmu_enable) || - job->queue_type == QUEUE_TYPE_INT)) { + job->queue_type == QUEUE_TYPE_INT))) { atomic_dec(&job->user_cb->cs_cnt); hl_cb_put(job->user_cb); } @@ -318,11 +395,10 @@ static void complete_job(struct hl_device *hdev, struct hl_cs_job *job) * flow by calling 'hl_hw_queue_update_ci'. */ if (cs_needs_completion(cs) && - (job->queue_type == QUEUE_TYPE_EXT || - job->queue_type == QUEUE_TYPE_HW)) + (job->queue_type == QUEUE_TYPE_EXT || job->queue_type == QUEUE_TYPE_HW)) cs_put(cs); - cs_job_put(job); + hl_cs_job_put(job); } /* @@ -612,7 +688,7 @@ static void cs_do_release(struct kref *ref) * still holds a pointer to them (but no reference). */ list_for_each_entry_safe(job, tmp, &cs->job_list, cs_node) - complete_job(hdev, job); + hl_complete_job(hdev, job); if (!cs->submitted) { /* @@ -642,9 +718,9 @@ static void cs_do_release(struct kref *ref) * staged submission */ if (cs->staged_last) { - struct hl_cs *staged_cs, *tmp; + struct hl_cs *staged_cs, *tmp_cs; - list_for_each_entry_safe(staged_cs, tmp, + list_for_each_entry_safe(staged_cs, tmp_cs, &cs->staged_cs_node, staged_cs_node) staged_cs_put(hdev, staged_cs); } @@ -678,7 +754,7 @@ out: */ hl_debugfs_remove_cs(cs); - hl_ctx_put(cs->ctx); + hdev->shadow_cs_queue[cs->sequence & (hdev->asic_prop.max_pending_cs - 1)] = NULL; /* We need to mark an error for not submitted because in that case * the hl fence release flow is different. Mainly, we don't need @@ -698,8 +774,14 @@ out: div_u64(jiffies - cs->submission_time_jiffies, HZ)); } - if (cs->timestamp) + if (cs->timestamp) { cs->fence->timestamp = ktime_get(); + hl_push_cs_outcome(hdev, &cs->ctx->outcome_store, cs->sequence, + cs->fence->timestamp, cs->fence->error); + } + + hl_ctx_put(cs->ctx); + complete_all(&cs->fence->completion); complete_multi_cs(hdev, cs); @@ -714,10 +796,11 @@ out: static void cs_timedout(struct work_struct *work) { struct hl_device *hdev; + u64 event_mask; int rc; struct hl_cs *cs = container_of(work, struct hl_cs, work_tdr.work); - bool skip_reset_on_timeout = cs->skip_reset_on_timeout; + bool skip_reset_on_timeout = cs->skip_reset_on_timeout, device_reset = false; rc = cs_get_unless_zero(cs); if (!rc) @@ -728,17 +811,28 @@ static void cs_timedout(struct work_struct *work) return; } - /* Mark the CS is timed out so we won't try to cancel its TDR */ - if (likely(!skip_reset_on_timeout)) - cs->timedout = true; - hdev = cs->ctx->hdev; + if (likely(!skip_reset_on_timeout)) { + if (hdev->reset_on_lockup) + device_reset = true; + else + hdev->reset_info.needs_reset = true; + + /* Mark the CS is timed out so we won't try to cancel its TDR */ + cs->timedout = true; + } + /* Save only the first CS timeout parameters */ - rc = atomic_cmpxchg(&hdev->last_error.cs_timeout.write_disable, 0, 1); - if (!rc) { + rc = atomic_cmpxchg(&hdev->last_error.cs_timeout.write_enable, 1, 0); + if (rc) { hdev->last_error.cs_timeout.timestamp = ktime_get(); hdev->last_error.cs_timeout.seq = cs->sequence; + + event_mask = device_reset ? (HL_NOTIFIER_EVENT_CS_TIMEOUT | + HL_NOTIFIER_EVENT_DEVICE_RESET) : HL_NOTIFIER_EVENT_CS_TIMEOUT; + + hl_notifier_event_send_all(hdev, event_mask); } switch (cs->type) { @@ -773,12 +867,8 @@ static void cs_timedout(struct work_struct *work) cs_put(cs); - if (likely(!skip_reset_on_timeout)) { - if (hdev->reset_on_lockup) - hl_device_reset(hdev, HL_DRV_RESET_TDR); - else - hdev->reset_info.needs_reset = true; - } + if (device_reset) + hl_device_reset(hdev, HL_DRV_RESET_TDR); } static int allocate_cs(struct hl_device *hdev, struct hl_ctx *ctx, @@ -916,7 +1006,7 @@ static void cs_rollback(struct hl_device *hdev, struct hl_cs *cs) staged_cs_put(hdev, cs); list_for_each_entry_safe(job, tmp, &cs->job_list, cs_node) - complete_job(hdev, job); + hl_complete_job(hdev, job); } void hl_cs_rollback_all(struct hl_device *hdev, bool skip_wq_flush) @@ -933,6 +1023,7 @@ void hl_cs_rollback_all(struct hl_device *hdev, bool skip_wq_flush) for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) flush_workqueue(hdev->cq_wq[i]); + flush_workqueue(hdev->cs_cmplt_wq); } /* Make sure we don't have leftovers in the CS mirror list */ @@ -940,7 +1031,7 @@ void hl_cs_rollback_all(struct hl_device *hdev, bool skip_wq_flush) cs_get(cs); cs->aborted = true; dev_warn_ratelimited(hdev->dev, "Killing CS %d.%llu\n", - cs->ctx->asid, cs->sequence); + cs->ctx->asid, cs->sequence); cs_rollback(hdev, cs); cs_put(cs); } @@ -989,7 +1080,10 @@ void hl_release_pending_user_interrupts(struct hl_device *hdev) wake_pending_user_interrupt_threads(interrupt); } - interrupt = &hdev->common_user_interrupt; + interrupt = &hdev->common_user_cq_interrupt; + wake_pending_user_interrupt_threads(interrupt); + + interrupt = &hdev->common_decoder_interrupt; wake_pending_user_interrupt_threads(interrupt); } @@ -1001,7 +1095,17 @@ static void job_wq_completion(struct work_struct *work) struct hl_device *hdev = cs->ctx->hdev; /* job is no longer needed */ - complete_job(hdev, job); + hl_complete_job(hdev, job); +} + +static void cs_completion(struct work_struct *work) +{ + struct hl_cs *cs = container_of(work, struct hl_cs, finish_work); + struct hl_device *hdev = cs->ctx->hdev; + struct hl_cs_job *job, *tmp; + + list_for_each_entry_safe(job, tmp, &cs->job_list, cs_node) + hl_complete_job(hdev, job); } static int validate_queue_index(struct hl_device *hdev, @@ -1024,7 +1128,13 @@ static int validate_queue_index(struct hl_device *hdev, hw_queue_prop = &asic->hw_queues_props[chunk->queue_index]; if (hw_queue_prop->type == QUEUE_TYPE_NA) { - dev_err(hdev->dev, "Queue index %d is invalid\n", + dev_err(hdev->dev, "Queue index %d is not applicable\n", + chunk->queue_index); + return -EINVAL; + } + + if (hw_queue_prop->binned) { + dev_err(hdev->dev, "Queue index %d is binned out\n", chunk->queue_index); return -EINVAL; } @@ -1166,17 +1276,16 @@ static int hl_cs_sanity_checks(struct hl_fpriv *hpriv, union hl_cs_args *args) cs_type = hl_cs_get_cs_type(cs_type_flags); num_chunks = args->in.num_chunks_execute; - if (unlikely((cs_type != CS_TYPE_DEFAULT) && - !hdev->supports_sync_stream)) { + if (unlikely((cs_type == CS_TYPE_SIGNAL || cs_type == CS_TYPE_WAIT || + cs_type == CS_TYPE_COLLECTIVE_WAIT) && + !hdev->supports_sync_stream)) { dev_err(hdev->dev, "Sync stream CS is not supported\n"); return -EINVAL; } if (cs_type == CS_TYPE_DEFAULT) { if (!num_chunks) { - dev_err(hdev->dev, - "Got execute CS with 0 chunks, context %d\n", - ctx->asid); + dev_err(hdev->dev, "Got execute CS with 0 chunks, context %d\n", ctx->asid); return -EINVAL; } } else if (num_chunks != 1) { @@ -1276,7 +1385,7 @@ static int cs_ioctl_default(struct hl_fpriv *hpriv, void __user *chunks, u32 encaps_signals_handle, u32 timeout, u16 *signal_initial_sob_count) { - bool staged_mid, int_queues_only = true; + bool staged_mid, int_queues_only = true, using_hw_queues = false; struct hl_device *hdev = hpriv->hdev; struct hl_cs_chunk *cs_chunk_array; struct hl_cs_counters_atomic *cntr; @@ -1365,6 +1474,9 @@ static int cs_ioctl_default(struct hl_fpriv *hpriv, void __user *chunks, chunk->queue_index); } + if (queue_type == QUEUE_TYPE_HW) + using_hw_queues = true; + job = hl_cs_allocate_job(hdev, queue_type, is_kernel_allocated_cb); if (!job) { @@ -1385,6 +1497,7 @@ static int cs_ioctl_default(struct hl_fpriv *hpriv, void __user *chunks, job->hw_queue_id = chunk->queue_index; cs->jobs_in_queue_cnt[job->hw_queue_id]++; + cs->jobs_cnt++; list_add_tail(&job->cs_node, &cs->job_list); @@ -1425,6 +1538,9 @@ static int cs_ioctl_default(struct hl_fpriv *hpriv, void __user *chunks, goto free_cs_object; } + if (using_hw_queues) + INIT_WORK(&cs->finish_work, cs_completion); + /* * store the (external/HW queues) streams used by the CS in the * fence object for multi-CS completion @@ -1773,6 +1889,7 @@ static int cs_ioctl_signal_wait_create_jobs(struct hl_device *hdev, cs_get(cs); cs->jobs_in_queue_cnt[job->hw_queue_id]++; + cs->jobs_cnt++; list_add_tail(&job->cs_node, &cs->job_list); @@ -2191,6 +2308,9 @@ static int cs_ioctl_signal_wait(struct hl_fpriv *hpriv, enum hl_cs_type cs_type, if (rc) goto free_cs_object; + if (q_type == QUEUE_TYPE_HW) + INIT_WORK(&cs->finish_work, cs_completion); + rc = hl_hw_queue_schedule_cs(cs); if (rc) { /* In case wait cs failed here, it means the signal cs @@ -2321,12 +2441,12 @@ out: } static int hl_wait_for_fence(struct hl_ctx *ctx, u64 seq, struct hl_fence *fence, - enum hl_cs_wait_status *status, u64 timeout_us, - s64 *timestamp) + enum hl_cs_wait_status *status, u64 timeout_us, s64 *timestamp) { struct hl_device *hdev = ctx->hdev; + ktime_t timestamp_kt; long completion_rc; - int rc = 0; + int rc = 0, error; if (IS_ERR(fence)) { rc = PTR_ERR(fence); @@ -2338,12 +2458,16 @@ static int hl_wait_for_fence(struct hl_ctx *ctx, u64 seq, struct hl_fence *fence } if (!fence) { - dev_dbg(hdev->dev, - "Can't wait on seq %llu because current CS is at seq %llu (Fence is gone)\n", + if (!hl_pop_cs_outcome(&ctx->outcome_store, seq, ×tamp_kt, &error)) { + dev_dbg(hdev->dev, + "Can't wait on seq %llu because current CS is at seq %llu (Fence is gone)\n", seq, ctx->cs_sequence); + *status = CS_WAIT_STATUS_GONE; + return 0; + } - *status = CS_WAIT_STATUS_GONE; - return 0; + completion_rc = 1; + goto report_results; } if (!timeout_us) { @@ -2358,18 +2482,20 @@ static int hl_wait_for_fence(struct hl_ctx *ctx, u64 seq, struct hl_fence *fence &fence->completion, timeout); } + error = fence->error; + timestamp_kt = fence->timestamp; + +report_results: if (completion_rc > 0) { *status = CS_WAIT_STATUS_COMPLETED; if (timestamp) - *timestamp = ktime_to_ns(fence->timestamp); + *timestamp = ktime_to_ns(timestamp_kt); } else { *status = CS_WAIT_STATUS_BUSY; } - if (fence->error == -ETIMEDOUT) - rc = -ETIMEDOUT; - else if (fence->error == -EIO) - rc = -EIO; + if (error == -ETIMEDOUT || error == -EIO) + rc = error; return rc; } @@ -2443,8 +2569,7 @@ static int hl_cs_poll_fences(struct multi_cs_data *mcs_data, struct multi_cs_com * function won't sleep as it is called with timeout 0 (i.e. * poll the fence) */ - rc = hl_wait_for_fence(mcs_data->ctx, seq_arr[i], fence, - &status, 0, NULL); + rc = hl_wait_for_fence(mcs_data->ctx, seq_arr[i], fence, &status, 0, NULL); if (rc) { dev_err(hdev->dev, "wait_for_fence error :%d for CS seq %llu\n", @@ -2482,7 +2607,7 @@ static int hl_cs_poll_fences(struct multi_cs_data *mcs_data, struct multi_cs_com * For this we have to validate that the timestamp is * earliest of all timestamps so far. */ - if (mcs_data->update_ts && + if (fence && mcs_data->update_ts && (ktime_compare(fence->timestamp, first_cs_time) < 0)) first_cs_time = fence->timestamp; break; @@ -2513,8 +2638,7 @@ static int hl_cs_poll_fences(struct multi_cs_data *mcs_data, struct multi_cs_com return rc; } -static int _hl_cs_wait_ioctl(struct hl_device *hdev, struct hl_ctx *ctx, - u64 timeout_us, u64 seq, +static int _hl_cs_wait_ioctl(struct hl_device *hdev, struct hl_ctx *ctx, u64 timeout_us, u64 seq, enum hl_cs_wait_status *status, s64 *timestamp) { struct hl_fence *fence; @@ -2815,8 +2939,7 @@ static int hl_cs_wait_ioctl(struct hl_fpriv *hpriv, void *data) s64 timestamp; int rc; - rc = _hl_cs_wait_ioctl(hdev, hpriv->ctx, args->in.timeout_us, seq, - &status, ×tamp); + rc = _hl_cs_wait_ioctl(hdev, hpriv->ctx, args->in.timeout_us, seq, &status, ×tamp); if (rc == -ERESTARTSYS) { dev_err_ratelimited(hdev->dev, @@ -2880,7 +3003,7 @@ static int ts_buff_get_kernel_ts_record(struct hl_mmap_mem_buf *buf, u64 current_cq_counter; /* Validate ts_offset not exceeding last max */ - if (requested_offset_record > cb_last) { + if (requested_offset_record >= cb_last) { dev_err(buf->mmg->dev, "Ts offset exceeds max CB offset(0x%llx)\n", (u64)(uintptr_t)cb_last); return -EINVAL; @@ -2936,8 +3059,8 @@ start_over: *pend = requested_offset_record; - dev_dbg(buf->mmg->dev, "Found available node in TS kernel CB(0x%llx)\n", - (u64)(uintptr_t)requested_offset_record); + dev_dbg(buf->mmg->dev, "Found available node in TS kernel CB %p\n", + requested_offset_record); return 0; } @@ -2965,6 +3088,13 @@ static int _hl_interrupt_wait_ioctl(struct hl_device *hdev, struct hl_ctx *ctx, goto put_ctx; } + /* Validate the cq offset */ + if (((u64 *) cq_cb->kernel_address + cq_counters_offset) >= + ((u64 *) cq_cb->kernel_address + (cq_cb->size / sizeof(u64)))) { + rc = -EINVAL; + goto put_cq_cb; + } + if (register_ts_record) { dev_dbg(hdev->dev, "Timestamp registration: interrupt id: %u, ts offset: %llu, cq_offset: %llu\n", interrupt->interrupt_id, ts_offset, cq_counters_offset); @@ -3094,7 +3224,6 @@ put_ctx: static int _hl_interrupt_wait_ioctl_user_addr(struct hl_device *hdev, struct hl_ctx *ctx, u64 timeout_us, u64 user_address, u64 target_value, struct hl_user_interrupt *interrupt, - u32 *status, u64 *timestamp) { @@ -3216,33 +3345,46 @@ static int hl_interrupt_wait_ioctl(struct hl_fpriv *hpriv, void *data) struct hl_user_interrupt *interrupt; union hl_wait_cs_args *args = data; u32 status = HL_WAIT_CS_STATUS_BUSY; - u64 timestamp; - int rc; + u64 timestamp = 0; + int rc, int_idx; prop = &hdev->asic_prop; - if (!prop->user_interrupt_count) { + if (!(prop->user_interrupt_count + prop->user_dec_intr_count)) { dev_err(hdev->dev, "no user interrupts allowed"); return -EPERM; } interrupt_id = FIELD_GET(HL_WAIT_CS_FLAGS_INTERRUPT_MASK, args->in.flags); - first_interrupt = prop->first_available_user_msix_interrupt; - last_interrupt = prop->first_available_user_msix_interrupt + - prop->user_interrupt_count - 1; + first_interrupt = prop->first_available_user_interrupt; + last_interrupt = prop->first_available_user_interrupt + prop->user_interrupt_count - 1; - if ((interrupt_id < first_interrupt || interrupt_id > last_interrupt) && - interrupt_id != HL_COMMON_USER_INTERRUPT_ID) { + if (interrupt_id < prop->user_dec_intr_count) { + + /* Check if the requested core is enabled */ + if (!(prop->decoder_enabled_mask & BIT(interrupt_id))) { + dev_err(hdev->dev, "interrupt on a disabled core(%u) not allowed", + interrupt_id); + return -EINVAL; + } + + interrupt = &hdev->user_interrupt[interrupt_id]; + + } else if (interrupt_id >= first_interrupt && interrupt_id <= last_interrupt) { + + int_idx = interrupt_id - first_interrupt + prop->user_dec_intr_count; + interrupt = &hdev->user_interrupt[int_idx]; + + } else if (interrupt_id == HL_COMMON_USER_CQ_INTERRUPT_ID) { + interrupt = &hdev->common_user_cq_interrupt; + } else if (interrupt_id == HL_COMMON_DEC_INTERRUPT_ID) { + interrupt = &hdev->common_decoder_interrupt; + } else { dev_err(hdev->dev, "invalid user interrupt %u", interrupt_id); return -EINVAL; } - if (interrupt_id == HL_COMMON_USER_INTERRUPT_ID) - interrupt = &hdev->common_user_interrupt; - else - interrupt = &hdev->user_interrupt[interrupt_id - first_interrupt]; - if (args->in.flags & HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ) rc = _hl_interrupt_wait_ioctl(hdev, hpriv->ctx, &hpriv->mem_mgr, &hpriv->mem_mgr, args->in.interrupt_timeout_us, args->in.cq_counters_handle, diff --git a/drivers/misc/habanalabs/common/context.c b/drivers/misc/habanalabs/common/context.c index ed2cfd0c6e99..2f4620b7990c 100644 --- a/drivers/misc/habanalabs/common/context.c +++ b/drivers/misc/habanalabs/common/context.c @@ -102,13 +102,13 @@ static void hl_ctx_fini(struct hl_ctx *ctx) hl_device_set_debug_mode(hdev, ctx, false); hdev->asic_funcs->ctx_fini(ctx); + + hl_dec_ctx_fini(ctx); + hl_cb_va_pool_fini(ctx); hl_vm_ctx_fini(ctx); hl_asid_free(hdev, ctx->asid); hl_encaps_sig_mgr_fini(hdev, &ctx->sig_mgr); - - /* Scrub both SRAM and DRAM */ - hdev->asic_funcs->scrub_device_mem(hdev, 0, 0); } else { dev_dbg(hdev->dev, "closing kernel context\n"); hdev->asic_funcs->ctx_fini(ctx); @@ -125,15 +125,22 @@ void hl_ctx_do_release(struct kref *ref) hl_ctx_fini(ctx); - if (ctx->hpriv) - hl_hpriv_put(ctx->hpriv); + if (ctx->hpriv) { + struct hl_fpriv *hpriv = ctx->hpriv; + + mutex_lock(&hpriv->ctx_lock); + hpriv->ctx = NULL; + mutex_unlock(&hpriv->ctx_lock); + + hl_hpriv_put(hpriv); + } kfree(ctx); } int hl_ctx_create(struct hl_device *hdev, struct hl_fpriv *hpriv) { - struct hl_ctx_mgr *mgr = &hpriv->ctx_mgr; + struct hl_ctx_mgr *ctx_mgr = &hpriv->ctx_mgr; struct hl_ctx *ctx; int rc; @@ -143,9 +150,9 @@ int hl_ctx_create(struct hl_device *hdev, struct hl_fpriv *hpriv) goto out_err; } - mutex_lock(&mgr->ctx_lock); - rc = idr_alloc(&mgr->ctx_handles, ctx, 1, 0, GFP_KERNEL); - mutex_unlock(&mgr->ctx_lock); + mutex_lock(&ctx_mgr->lock); + rc = idr_alloc(&ctx_mgr->handles, ctx, 1, 0, GFP_KERNEL); + mutex_unlock(&ctx_mgr->lock); if (rc < 0) { dev_err(hdev->dev, "Failed to allocate IDR for a new CTX\n"); @@ -170,9 +177,9 @@ int hl_ctx_create(struct hl_device *hdev, struct hl_fpriv *hpriv) return 0; remove_from_idr: - mutex_lock(&mgr->ctx_lock); - idr_remove(&mgr->ctx_handles, ctx->handle); - mutex_unlock(&mgr->ctx_lock); + mutex_lock(&ctx_mgr->lock); + idr_remove(&ctx_mgr->handles, ctx->handle); + mutex_unlock(&ctx_mgr->lock); free_ctx: kfree(ctx); out_err: @@ -181,7 +188,7 @@ out_err: int hl_ctx_init(struct hl_device *hdev, struct hl_ctx *ctx, bool is_kernel_ctx) { - int rc = 0; + int rc = 0, i; ctx->hdev = hdev; @@ -197,6 +204,13 @@ int hl_ctx_init(struct hl_device *hdev, struct hl_ctx *ctx, bool is_kernel_ctx) if (!ctx->cs_pending) return -ENOMEM; + INIT_LIST_HEAD(&ctx->outcome_store.used_list); + INIT_LIST_HEAD(&ctx->outcome_store.free_list); + hash_init(ctx->outcome_store.outcome_map); + for (i = 0; i < ARRAY_SIZE(ctx->outcome_store.nodes_pool); ++i) + list_add(&ctx->outcome_store.nodes_pool[i].list_link, + &ctx->outcome_store.free_list); + hl_hw_block_mem_init(ctx); if (is_kernel_ctx) { @@ -262,6 +276,11 @@ err_hw_block_mem_fini: return rc; } +static int hl_ctx_get_unless_zero(struct hl_ctx *ctx) +{ + return kref_get_unless_zero(&ctx->refcount); +} + void hl_ctx_get(struct hl_ctx *ctx) { kref_get(&ctx->refcount); @@ -280,11 +299,15 @@ struct hl_ctx *hl_get_compute_ctx(struct hl_device *hdev) mutex_lock(&hdev->fpriv_list_lock); list_for_each_entry(hpriv, &hdev->fpriv_list, dev_node) { - /* There can only be a single user which has opened the compute device, so exit - * immediately once we find him - */ + mutex_lock(&hpriv->ctx_lock); ctx = hpriv->ctx; - hl_ctx_get(ctx); + if (ctx && !hl_ctx_get_unless_zero(ctx)) + ctx = NULL; + mutex_unlock(&hpriv->ctx_lock); + + /* There can only be a single user which has opened the compute device, so exit + * immediately once we find its context or if we see that it has been released + */ break; } @@ -376,37 +399,37 @@ int hl_ctx_get_fences(struct hl_ctx *ctx, u64 *seq_arr, /* * hl_ctx_mgr_init - initialize the context manager * - * @mgr: pointer to context manager structure + * @ctx_mgr: pointer to context manager structure * * This manager is an object inside the hpriv object of the user process. * The function is called when a user process opens the FD. */ -void hl_ctx_mgr_init(struct hl_ctx_mgr *mgr) +void hl_ctx_mgr_init(struct hl_ctx_mgr *ctx_mgr) { - mutex_init(&mgr->ctx_lock); - idr_init(&mgr->ctx_handles); + mutex_init(&ctx_mgr->lock); + idr_init(&ctx_mgr->handles); } /* * hl_ctx_mgr_fini - finalize the context manager * * @hdev: pointer to device structure - * @mgr: pointer to context manager structure + * @ctx_mgr: pointer to context manager structure * * This function goes over all the contexts in the manager and frees them. * It is called when a process closes the FD. */ -void hl_ctx_mgr_fini(struct hl_device *hdev, struct hl_ctx_mgr *mgr) +void hl_ctx_mgr_fini(struct hl_device *hdev, struct hl_ctx_mgr *ctx_mgr) { struct hl_ctx *ctx; struct idr *idp; u32 id; - idp = &mgr->ctx_handles; + idp = &ctx_mgr->handles; idr_for_each_entry(idp, ctx, id) kref_put(&ctx->refcount, hl_ctx_do_release); - idr_destroy(&mgr->ctx_handles); - mutex_destroy(&mgr->ctx_lock); + idr_destroy(&ctx_mgr->handles); + mutex_destroy(&ctx_mgr->lock); } diff --git a/drivers/misc/habanalabs/common/debugfs.c b/drivers/misc/habanalabs/common/debugfs.c index c6744bfc6da4..64439f33a19b 100644 --- a/drivers/misc/habanalabs/common/debugfs.c +++ b/drivers/misc/habanalabs/common/debugfs.c @@ -152,12 +152,12 @@ static int command_submission_show(struct seq_file *s, void *data) if (first) { first = false; seq_puts(s, "\n"); - seq_puts(s, " CS ID CTX ASID CS RefCnt Submitted Completed\n"); - seq_puts(s, "------------------------------------------------------\n"); + seq_puts(s, " CS ID CS TYPE CTX ASID CS RefCnt Submitted Completed\n"); + seq_puts(s, "----------------------------------------------------------------\n"); } seq_printf(s, - " %llu %d %d %d %d\n", - cs->sequence, cs->ctx->asid, + " %llu %d %d %d %d %d\n", + cs->sequence, cs->type, cs->ctx->asid, kref_read(&cs->refcount), cs->submitted, cs->completed); } @@ -183,17 +183,18 @@ static int command_submission_jobs_show(struct seq_file *s, void *data) if (first) { first = false; seq_puts(s, "\n"); - seq_puts(s, " JOB ID CS ID CTX ASID JOB RefCnt H/W Queue\n"); - seq_puts(s, "----------------------------------------------------\n"); + seq_puts(s, " JOB ID CS ID CS TYPE CTX ASID JOB RefCnt H/W Queue\n"); + seq_puts(s, "---------------------------------------------------------------\n"); } if (job->cs) seq_printf(s, - " %02d %llu %d %d %d\n", - job->id, job->cs->sequence, job->cs->ctx->asid, - kref_read(&job->refcount), job->hw_queue_id); + " %02d %llu %d %d %d %d\n", + job->id, job->cs->sequence, job->cs->type, + job->cs->ctx->asid, kref_read(&job->refcount), + job->hw_queue_id); else seq_printf(s, - " %02d 0 %d %d %d\n", + " %02d 0 0 %d %d %d\n", job->id, HL_KERNEL_ASID_ID, kref_read(&job->refcount), job->hw_queue_id); } @@ -449,7 +450,7 @@ static int mmu_show(struct seq_file *s, void *data) if (hl_mmu_get_tlb_info(ctx, virt_addr, &hops_info)) { dev_err(hdev->dev, "virt addr 0x%llx is not mapped to phys addr\n", virt_addr); - return 0; + goto put_ctx; } hl_mmu_va_to_pa(ctx, virt_addr, &phys_addr); @@ -475,6 +476,10 @@ static int mmu_show(struct seq_file *s, void *data) i, hops_info.hop_info[i].hop_pte_val); } +put_ctx: + if (dev_entry->mmu_asid != HL_KERNEL_ASID_ID) + hl_ctx_put(ctx); + return 0; } @@ -521,6 +526,66 @@ err: return -EINVAL; } +static int mmu_ack_error(struct seq_file *s, void *data) +{ + struct hl_debugfs_entry *entry = s->private; + struct hl_dbg_device_entry *dev_entry = entry->dev_entry; + struct hl_device *hdev = dev_entry->hdev; + int rc; + + if (!hdev->mmu_enable) + return 0; + + if (!dev_entry->mmu_cap_mask) { + dev_err(hdev->dev, "mmu_cap_mask is not set\n"); + goto err; + } + + rc = hdev->asic_funcs->ack_mmu_errors(hdev, dev_entry->mmu_cap_mask); + if (rc) + goto err; + + return 0; +err: + return -EINVAL; +} + +static ssize_t mmu_ack_error_value_write(struct file *file, + const char __user *buf, + size_t count, loff_t *f_pos) +{ + struct seq_file *s = file->private_data; + struct hl_debugfs_entry *entry = s->private; + struct hl_dbg_device_entry *dev_entry = entry->dev_entry; + struct hl_device *hdev = dev_entry->hdev; + char kbuf[MMU_KBUF_SIZE]; + ssize_t rc; + + if (!hdev->mmu_enable) + return count; + + if (count > sizeof(kbuf) - 1) + goto err; + + if (copy_from_user(kbuf, buf, count)) + goto err; + + kbuf[count] = 0; + + if (strncmp(kbuf, "0x", 2)) + goto err; + + rc = kstrtoull(kbuf, 16, &dev_entry->mmu_cap_mask); + if (rc) + goto err; + + return count; +err: + dev_err(hdev->dev, "usage: echo <0xmmu_cap_mask > > mmu_error\n"); + + return -EINVAL; +} + static int engines_show(struct seq_file *s, void *data) { struct hl_debugfs_entry *entry = s->private; @@ -543,7 +608,7 @@ static ssize_t hl_memory_scrub(struct file *f, const char __user *buf, { struct hl_dbg_device_entry *entry = file_inode(f)->i_private; struct hl_device *hdev = entry->hdev; - u64 val = entry->memory_scrub_val; + u64 val = hdev->memory_scrub_val; int rc; if (!hl_device_operational(hdev, NULL)) { @@ -666,7 +731,8 @@ static int device_va_to_pa(struct hl_device *hdev, u64 virt_addr, u32 size, dev_err(hdev->dev, "virt addr 0x%llx is not mapped\n", virt_addr); - return -EINVAL; + rc = -EINVAL; + goto put_ctx; } rc = hl_mmu_va_to_pa(ctx, virt_addr, phys_addr); @@ -677,6 +743,9 @@ static int device_va_to_pa(struct hl_device *hdev, u64 virt_addr, u32 size, rc = -EINVAL; } +put_ctx: + hl_ctx_put(ctx); + return rc; } @@ -695,8 +764,7 @@ static int hl_access_dev_mem_by_region(struct hl_device *hdev, u64 addr, if (addr >= mem_reg->region_base && addr <= mem_reg->region_base + mem_reg->region_size - acc_size) { *found = true; - return hdev->asic_funcs->access_dev_mem(hdev, mem_reg, i, - addr, val, acc_type); + return hdev->asic_funcs->access_dev_mem(hdev, i, addr, val, acc_type); } } return 0; @@ -728,7 +796,7 @@ static void hl_access_host_mem(struct hl_device *hdev, u64 addr, u64 *val, } static int hl_access_mem(struct hl_device *hdev, u64 addr, u64 *val, - enum debugfs_access_type acc_type) + enum debugfs_access_type acc_type) { size_t acc_size = (acc_type == DEBUGFS_READ64 || acc_type == DEBUGFS_WRITE64) ? sizeof(u64) : sizeof(u32); @@ -1349,6 +1417,17 @@ static ssize_t hl_timeout_locked_write(struct file *f, const char __user *buf, return count; } +static ssize_t hl_check_razwi_happened(struct file *f, char __user *buf, + size_t count, loff_t *ppos) +{ + struct hl_dbg_device_entry *entry = file_inode(f)->i_private; + struct hl_device *hdev = entry->hdev; + + hdev->asic_funcs->check_if_razwi_happened(hdev); + + return 0; +} + static const struct file_operations hl_mem_scrub_fops = { .owner = THIS_MODULE, .write = hl_memory_scrub, @@ -1438,6 +1517,11 @@ static const struct file_operations hl_timeout_locked_fops = { .write = hl_timeout_locked_write }; +static const struct file_operations hl_razwi_check_fops = { + .owner = THIS_MODULE, + .read = hl_check_razwi_happened +}; + static const struct hl_info_list hl_debugfs_list[] = { {"command_buffers", command_buffers_show, NULL}, {"command_submission", command_submission_show, NULL}, @@ -1446,7 +1530,8 @@ static const struct hl_info_list hl_debugfs_list[] = { {"vm", vm_show, NULL}, {"userptr_lookup", userptr_lookup_show, userptr_lookup_write}, {"mmu", mmu_show, mmu_asid_va_write}, - {"engines", engines_show, NULL} + {"mmu_error", mmu_ack_error, mmu_ack_error_value_write}, + {"engines", engines_show, NULL}, }; static int hl_debugfs_open(struct inode *inode, struct file *file) @@ -1477,76 +1562,8 @@ static const struct file_operations hl_debugfs_fops = { .release = single_release, }; -void hl_debugfs_add_device(struct hl_device *hdev) +static void add_secured_nodes(struct hl_dbg_device_entry *dev_entry) { - struct hl_dbg_device_entry *dev_entry = &hdev->hl_debugfs; - int count = ARRAY_SIZE(hl_debugfs_list); - struct hl_debugfs_entry *entry; - int i; - - dev_entry->hdev = hdev; - dev_entry->entry_arr = kmalloc_array(count, - sizeof(struct hl_debugfs_entry), - GFP_KERNEL); - if (!dev_entry->entry_arr) - return; - - dev_entry->data_dma_blob_desc.size = 0; - dev_entry->data_dma_blob_desc.data = NULL; - dev_entry->mon_dump_blob_desc.size = 0; - dev_entry->mon_dump_blob_desc.data = NULL; - - INIT_LIST_HEAD(&dev_entry->file_list); - INIT_LIST_HEAD(&dev_entry->cb_list); - INIT_LIST_HEAD(&dev_entry->cs_list); - INIT_LIST_HEAD(&dev_entry->cs_job_list); - INIT_LIST_HEAD(&dev_entry->userptr_list); - INIT_LIST_HEAD(&dev_entry->ctx_mem_hash_list); - mutex_init(&dev_entry->file_mutex); - init_rwsem(&dev_entry->state_dump_sem); - spin_lock_init(&dev_entry->cb_spinlock); - spin_lock_init(&dev_entry->cs_spinlock); - spin_lock_init(&dev_entry->cs_job_spinlock); - spin_lock_init(&dev_entry->userptr_spinlock); - spin_lock_init(&dev_entry->ctx_mem_hash_spinlock); - - dev_entry->root = debugfs_create_dir(dev_name(hdev->dev), - hl_debug_root); - - debugfs_create_x64("memory_scrub_val", - 0644, - dev_entry->root, - &dev_entry->memory_scrub_val); - - debugfs_create_file("memory_scrub", - 0200, - dev_entry->root, - dev_entry, - &hl_mem_scrub_fops); - - debugfs_create_x64("addr", - 0644, - dev_entry->root, - &dev_entry->addr); - - debugfs_create_file("data32", - 0644, - dev_entry->root, - dev_entry, - &hl_data32b_fops); - - debugfs_create_file("data64", - 0644, - dev_entry->root, - dev_entry, - &hl_data64b_fops); - - debugfs_create_file("set_power_state", - 0200, - dev_entry->root, - dev_entry, - &hl_power_fops); - debugfs_create_u8("i2c_bus", 0644, dev_entry->root, @@ -1590,6 +1607,77 @@ void hl_debugfs_add_device(struct hl_device *hdev) dev_entry->root, dev_entry, &hl_led2_fops); +} + +void hl_debugfs_add_device(struct hl_device *hdev) +{ + struct hl_dbg_device_entry *dev_entry = &hdev->hl_debugfs; + int count = ARRAY_SIZE(hl_debugfs_list); + struct hl_debugfs_entry *entry; + int i; + + dev_entry->hdev = hdev; + dev_entry->entry_arr = kmalloc_array(count, + sizeof(struct hl_debugfs_entry), + GFP_KERNEL); + if (!dev_entry->entry_arr) + return; + + dev_entry->data_dma_blob_desc.size = 0; + dev_entry->data_dma_blob_desc.data = NULL; + dev_entry->mon_dump_blob_desc.size = 0; + dev_entry->mon_dump_blob_desc.data = NULL; + + INIT_LIST_HEAD(&dev_entry->file_list); + INIT_LIST_HEAD(&dev_entry->cb_list); + INIT_LIST_HEAD(&dev_entry->cs_list); + INIT_LIST_HEAD(&dev_entry->cs_job_list); + INIT_LIST_HEAD(&dev_entry->userptr_list); + INIT_LIST_HEAD(&dev_entry->ctx_mem_hash_list); + mutex_init(&dev_entry->file_mutex); + init_rwsem(&dev_entry->state_dump_sem); + spin_lock_init(&dev_entry->cb_spinlock); + spin_lock_init(&dev_entry->cs_spinlock); + spin_lock_init(&dev_entry->cs_job_spinlock); + spin_lock_init(&dev_entry->userptr_spinlock); + spin_lock_init(&dev_entry->ctx_mem_hash_spinlock); + + dev_entry->root = debugfs_create_dir(dev_name(hdev->dev), + hl_debug_root); + + debugfs_create_x64("memory_scrub_val", + 0644, + dev_entry->root, + &hdev->memory_scrub_val); + + debugfs_create_file("memory_scrub", + 0200, + dev_entry->root, + dev_entry, + &hl_mem_scrub_fops); + + debugfs_create_x64("addr", + 0644, + dev_entry->root, + &dev_entry->addr); + + debugfs_create_file("data32", + 0644, + dev_entry->root, + dev_entry, + &hl_data32b_fops); + + debugfs_create_file("data64", + 0644, + dev_entry->root, + dev_entry, + &hl_data64b_fops); + + debugfs_create_file("set_power_state", + 0200, + dev_entry->root, + dev_entry, + &hl_power_fops); debugfs_create_file("device", 0200, @@ -1615,6 +1703,12 @@ void hl_debugfs_add_device(struct hl_device *hdev) dev_entry, &hl_security_violations_fops); + debugfs_create_file("dump_razwi_events", + 0644, + dev_entry->root, + dev_entry, + &hl_razwi_check_fops); + debugfs_create_file("dma_size", 0200, dev_entry->root, @@ -1663,6 +1757,9 @@ void hl_debugfs_add_device(struct hl_device *hdev) entry->info_ent = &hl_debugfs_list[i]; entry->dev_entry = dev_entry; } + + if (!hdev->asic_prop.fw_security_enabled) + add_secured_nodes(dev_entry); } void hl_debugfs_remove_device(struct hl_device *hdev) diff --git a/drivers/misc/habanalabs/common/decoder.c b/drivers/misc/habanalabs/common/decoder.c new file mode 100644 index 000000000000..2aab14d74b53 --- /dev/null +++ b/drivers/misc/habanalabs/common/decoder.c @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2022 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "habanalabs.h" + +#define VCMD_CONTROL_OFFSET 0x40 /* SWREG16 */ +#define VCMD_IRQ_STATUS_OFFSET 0x44 /* SWREG17 */ + +#define VCMD_IRQ_STATUS_ENDCMD_MASK 0x1 +#define VCMD_IRQ_STATUS_BUSERR_MASK 0x2 +#define VCMD_IRQ_STATUS_TIMEOUT_MASK 0x4 +#define VCMD_IRQ_STATUS_CMDERR_MASK 0x8 +#define VCMD_IRQ_STATUS_ABORT_MASK 0x10 +#define VCMD_IRQ_STATUS_RESET_MASK 0x20 + +static void dec_print_abnrm_intr_source(struct hl_device *hdev, u32 irq_status) +{ + const char *format = "abnormal interrupt source:%s%s%s%s%s%s\n"; + char *intr_source[6] = {"Unknown", "", "", "", "", ""}; + int i = 0; + + if (!irq_status) + return; + + if (irq_status & VCMD_IRQ_STATUS_ENDCMD_MASK) + intr_source[i++] = " ENDCMD"; + if (irq_status & VCMD_IRQ_STATUS_BUSERR_MASK) + intr_source[i++] = " BUSERR"; + if (irq_status & VCMD_IRQ_STATUS_TIMEOUT_MASK) + intr_source[i++] = " TIMEOUT"; + if (irq_status & VCMD_IRQ_STATUS_CMDERR_MASK) + intr_source[i++] = " CMDERR"; + if (irq_status & VCMD_IRQ_STATUS_ABORT_MASK) + intr_source[i++] = " ABORT"; + if (irq_status & VCMD_IRQ_STATUS_RESET_MASK) + intr_source[i++] = " RESET"; + + dev_err(hdev->dev, format, intr_source[0], intr_source[1], + intr_source[2], intr_source[3], intr_source[4], intr_source[5]); +} + +static void dec_error_intr_work(struct hl_device *hdev, u32 base_addr, u32 core_id) +{ + bool reset_required = false; + u32 irq_status; + + irq_status = RREG32(base_addr + VCMD_IRQ_STATUS_OFFSET); + + dev_err(hdev->dev, "Decoder abnormal interrupt %#x, core %d\n", irq_status, core_id); + + dec_print_abnrm_intr_source(hdev, irq_status); + + if (irq_status & VCMD_IRQ_STATUS_TIMEOUT_MASK) + reset_required = true; + + /* Clear the interrupt */ + WREG32(base_addr + VCMD_IRQ_STATUS_OFFSET, irq_status); + + /* Flush the interrupt clear */ + RREG32(base_addr + VCMD_IRQ_STATUS_OFFSET); + + if (reset_required) + hl_device_reset(hdev, HL_DRV_RESET_HARD); +} + +static void dec_completion_abnrm(struct work_struct *work) +{ + struct hl_dec *dec = container_of(work, struct hl_dec, completion_abnrm_work); + struct hl_device *hdev = dec->hdev; + + dec_error_intr_work(hdev, dec->base_addr, dec->core_id); +} + +void hl_dec_fini(struct hl_device *hdev) +{ + kfree(hdev->dec); +} + +int hl_dec_init(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct hl_dec *dec; + int rc, j; + + /* if max core is 0, nothing to do*/ + if (!prop->max_dec) + return 0; + + hdev->dec = kcalloc(prop->max_dec, sizeof(struct hl_dec), GFP_KERNEL); + if (!hdev->dec) + return -ENOMEM; + + for (j = 0 ; j < prop->max_dec ; j++) { + dec = hdev->dec + j; + + dec->hdev = hdev; + INIT_WORK(&dec->completion_abnrm_work, dec_completion_abnrm); + dec->core_id = j; + dec->base_addr = hdev->asic_funcs->get_dec_base_addr(hdev, j); + if (!dec->base_addr) { + dev_err(hdev->dev, "Invalid base address of decoder %d\n", j); + rc = -EINVAL; + goto err_dec_fini; + } + } + + return 0; + +err_dec_fini: + hl_dec_fini(hdev); + + return rc; +} + +void hl_dec_ctx_fini(struct hl_ctx *ctx) +{ + struct hl_device *hdev = ctx->hdev; + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct hl_dec *dec; + int j; + + for (j = 0 ; j < prop->max_dec ; j++) { + if (!!(prop->decoder_enabled_mask & BIT(j))) { + dec = hdev->dec + j; + /* Stop the decoder */ + WREG32(dec->base_addr + VCMD_CONTROL_OFFSET, 0); + } + } +} diff --git a/drivers/misc/habanalabs/common/device.c b/drivers/misc/habanalabs/common/device.c index b4f14c6d3970..b30aeb1c657f 100644 --- a/drivers/misc/habanalabs/common/device.c +++ b/drivers/misc/habanalabs/common/device.c @@ -15,6 +15,14 @@ #define HL_RESET_DELAY_USEC 10000 /* 10ms */ +enum dma_alloc_type { + DMA_ALLOC_COHERENT, + DMA_ALLOC_CPU_ACCESSIBLE, + DMA_ALLOC_POOL, +}; + +#define MEM_SCRUB_DEFAULT_VAL 0x1122334455667788 + /* * hl_set_dram_bar- sets the bar to allow later access to address * @@ -44,7 +52,7 @@ static int hl_access_sram_dram_region(struct hl_device *hdev, u64 addr, u64 *val enum debugfs_access_type acc_type, enum pci_region region_type) { struct pci_mem_region *region = &hdev->pci_mem_region[region_type]; - u64 old_base, rc; + u64 old_base = 0, rc; if (region_type == PCI_REGION_DRAM) { old_base = hl_set_dram_bar(hdev, addr); @@ -88,6 +96,75 @@ static int hl_access_sram_dram_region(struct hl_device *hdev, u64 addr, u64 *val return 0; } +static void *hl_dma_alloc_common(struct hl_device *hdev, size_t size, dma_addr_t *dma_handle, + gfp_t flag, enum dma_alloc_type alloc_type) +{ + void *ptr; + + switch (alloc_type) { + case DMA_ALLOC_COHERENT: + ptr = hdev->asic_funcs->asic_dma_alloc_coherent(hdev, size, dma_handle, flag); + break; + case DMA_ALLOC_CPU_ACCESSIBLE: + ptr = hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev, size, dma_handle); + break; + case DMA_ALLOC_POOL: + ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, size, flag, dma_handle); + break; + } + + return ptr; +} + +static void hl_asic_dma_free_common(struct hl_device *hdev, size_t size, void *cpu_addr, + dma_addr_t dma_handle, enum dma_alloc_type alloc_type) +{ + switch (alloc_type) { + case DMA_ALLOC_COHERENT: + hdev->asic_funcs->asic_dma_free_coherent(hdev, size, cpu_addr, dma_handle); + break; + case DMA_ALLOC_CPU_ACCESSIBLE: + hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev, size, cpu_addr); + break; + case DMA_ALLOC_POOL: + hdev->asic_funcs->asic_dma_pool_free(hdev, cpu_addr, dma_handle); + break; + } +} + +void *hl_asic_dma_alloc_coherent(struct hl_device *hdev, size_t size, dma_addr_t *dma_handle, + gfp_t flag) +{ + return hl_dma_alloc_common(hdev, size, dma_handle, flag, DMA_ALLOC_COHERENT); +} + +void hl_asic_dma_free_coherent(struct hl_device *hdev, size_t size, void *cpu_addr, + dma_addr_t dma_handle) +{ + hl_asic_dma_free_common(hdev, size, cpu_addr, dma_handle, DMA_ALLOC_COHERENT); +} + +void *hl_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size, dma_addr_t *dma_handle) +{ + return hl_dma_alloc_common(hdev, size, dma_handle, 0, DMA_ALLOC_CPU_ACCESSIBLE); +} + +void hl_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size, void *vaddr) +{ + hl_asic_dma_free_common(hdev, size, vaddr, 0, DMA_ALLOC_CPU_ACCESSIBLE); +} + +void *hl_asic_dma_pool_zalloc(struct hl_device *hdev, size_t size, gfp_t mem_flags, + dma_addr_t *dma_handle) +{ + return hl_dma_alloc_common(hdev, size, dma_handle, mem_flags, DMA_ALLOC_POOL); +} + +void hl_asic_dma_pool_free(struct hl_device *hdev, void *vaddr, dma_addr_t dma_addr) +{ + hl_asic_dma_free_common(hdev, 0, vaddr, dma_addr, DMA_ALLOC_POOL); +} + int hl_dma_map_sgtable(struct hl_device *hdev, struct sg_table *sgt, enum dma_data_direction dir) { struct asic_fixed_properties *prop = &hdev->asic_prop; @@ -168,14 +245,13 @@ int hl_access_cfg_region(struct hl_device *hdev, u64 addr, u64 *val, * hl_access_dev_mem - access device memory * * @hdev: pointer to habanalabs device structure - * @region: the memory region the address belongs to * @region_type: the type of the region the address belongs to * @addr: the address to access * @val: the value to write from or read to * @acc_type: the type of access (r/w, 32/64) */ -int hl_access_dev_mem(struct hl_device *hdev, struct pci_mem_region *region, - enum pci_region region_type, u64 addr, u64 *val, enum debugfs_access_type acc_type) +int hl_access_dev_mem(struct hl_device *hdev, enum pci_region region_type, + u64 addr, u64 *val, enum debugfs_access_type acc_type) { switch (region_type) { case PCI_REGION_CFG: @@ -195,16 +271,20 @@ enum hl_device_status hl_device_status(struct hl_device *hdev) { enum hl_device_status status; - if (hdev->reset_info.in_reset) - status = HL_DEVICE_STATUS_IN_RESET; - else if (hdev->reset_info.needs_reset) + if (hdev->reset_info.in_reset) { + if (hdev->reset_info.in_compute_reset) + status = HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE; + else + status = HL_DEVICE_STATUS_IN_RESET; + } else if (hdev->reset_info.needs_reset) { status = HL_DEVICE_STATUS_NEEDS_RESET; - else if (hdev->disabled) + } else if (hdev->disabled) { status = HL_DEVICE_STATUS_MALFUNCTION; - else if (!hdev->init_done) + } else if (!hdev->init_done) { status = HL_DEVICE_STATUS_IN_DEVICE_CREATION; - else + } else { status = HL_DEVICE_STATUS_OPERATIONAL; + } return status; } @@ -220,6 +300,7 @@ bool hl_device_operational(struct hl_device *hdev, switch (current_status) { case HL_DEVICE_STATUS_IN_RESET: + case HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE: case HL_DEVICE_STATUS_MALFUNCTION: case HL_DEVICE_STATUS_NEEDS_RESET: return false; @@ -245,6 +326,7 @@ static void hpriv_release(struct kref *ref) hl_debugfs_remove_file(hpriv); + mutex_destroy(&hpriv->ctx_lock); mutex_destroy(&hpriv->restore_phase_mutex); if ((!hdev->pldm) && (hdev->pdev) && @@ -271,9 +353,14 @@ static void hpriv_release(struct kref *ref) list_del(&hpriv->dev_node); mutex_unlock(&hdev->fpriv_list_lock); - if ((hdev->reset_if_device_not_idle && !device_is_idle) - || hdev->reset_upon_device_release) + if (!device_is_idle || hdev->reset_upon_device_release) { hl_device_reset(hdev, HL_DRV_RESET_DEV_RELEASE); + } else { + int rc = hdev->asic_funcs->scrub_device_mem(hdev); + + if (rc) + dev_err(hdev->dev, "failed to scrub memory from hpriv release (%d)\n", rc); + } /* Now we can mark the compute_ctx as not active. Even if a reset is running in a different * thread, we don't care because the in_reset is marked so if a user will try to open @@ -330,8 +417,8 @@ static int hl_device_release(struct inode *inode, struct file *filp) */ hl_release_pending_user_interrupts(hpriv->hdev); - hl_mem_mgr_fini(&hpriv->mem_mgr); hl_ctx_mgr_fini(hdev, &hpriv->ctx_mgr); + hl_mem_mgr_fini(&hpriv->mem_mgr); hdev->compute_ctx_in_release = 1; @@ -379,7 +466,7 @@ out: * @*filp: pointer to file structure * @*vma: pointer to vm_area_struct of the process * - * Called when process does an mmap on habanalabs device. Call the device's mmap + * Called when process does an mmap on habanalabs device. Call the relevant mmap * function at the end of the common code. */ static int hl_mmap(struct file *filp, struct vm_area_struct *vma) @@ -404,7 +491,6 @@ static int hl_mmap(struct file *filp, struct vm_area_struct *vma) case HL_MMAP_TYPE_TS_BUFF: return hl_mem_mgr_mmap(&hpriv->mem_mgr, vma, NULL); } - return -EINVAL; } @@ -563,6 +649,14 @@ static int device_early_init(struct hl_device *hdev) gaudi_set_asic_funcs(hdev); strscpy(hdev->asic_name, "GAUDI SEC", sizeof(hdev->asic_name)); break; + case ASIC_GAUDI2: + gaudi2_set_asic_funcs(hdev); + strscpy(hdev->asic_name, "GAUDI2", sizeof(hdev->asic_name)); + break; + case ASIC_GAUDI2_SEC: + gaudi2_set_asic_funcs(hdev); + strscpy(hdev->asic_name, "GAUDI2 SEC", sizeof(hdev->asic_name)); + break; default: dev_err(hdev->dev, "Unrecognized ASIC type %d\n", hdev->asic_type); @@ -604,12 +698,20 @@ static int device_early_init(struct hl_device *hdev) goto free_cq_wq; } + hdev->cs_cmplt_wq = alloc_workqueue("hl-cs-completions", WQ_UNBOUND, 0); + if (!hdev->cs_cmplt_wq) { + dev_err(hdev->dev, + "Failed to allocate CS completions workqueue\n"); + rc = -ENOMEM; + goto free_eq_wq; + } + hdev->ts_free_obj_wq = alloc_workqueue("hl-ts-free-obj", WQ_UNBOUND, 0); if (!hdev->ts_free_obj_wq) { dev_err(hdev->dev, "Failed to allocate Timestamp registration free workqueue\n"); rc = -ENOMEM; - goto free_eq_wq; + goto free_cs_cmplt_wq; } hdev->pf_wq = alloc_workqueue("hl-prefetch", WQ_UNBOUND, 0); @@ -666,6 +768,8 @@ free_pf_wq: destroy_workqueue(hdev->pf_wq); free_ts_free_wq: destroy_workqueue(hdev->ts_free_obj_wq); +free_cs_cmplt_wq: + destroy_workqueue(hdev->cs_cmplt_wq); free_eq_wq: destroy_workqueue(hdev->eq_wq); free_cq_wq: @@ -706,6 +810,7 @@ static void device_early_fini(struct hl_device *hdev) destroy_workqueue(hdev->pf_wq); destroy_workqueue(hdev->ts_free_obj_wq); + destroy_workqueue(hdev->cs_cmplt_wq); destroy_workqueue(hdev->eq_wq); destroy_workqueue(hdev->device_reset_work.wq); @@ -1159,8 +1264,7 @@ static void handle_reset_trigger(struct hl_device *hdev, u32 flags) * of heartbeat, the device CPU is marked as disable * so this message won't be sent */ - if (hl_fw_send_pci_access_msg(hdev, - CPUCP_PACKET_DISABLE_PCI_ACCESS)) + if (hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS, 0x0)) dev_warn(hdev->dev, "Failed to disable PCI access by F/W\n"); } @@ -1202,7 +1306,7 @@ int hl_device_reset(struct hl_device *hdev, u32 flags) skip_wq_flush = !!(flags & HL_DRV_RESET_DEV_RELEASE); delay_reset = !!(flags & HL_DRV_RESET_DELAY); - if (!hard_reset && !hdev->asic_prop.supports_soft_reset) { + if (!hard_reset && !hdev->asic_prop.supports_compute_reset) { hard_instead_soft = true; hard_reset = true; } @@ -1225,7 +1329,7 @@ int hl_device_reset(struct hl_device *hdev, u32 flags) } if (hard_instead_soft) - dev_dbg(hdev->dev, "Doing hard-reset instead of soft-reset\n"); + dev_dbg(hdev->dev, "Doing hard-reset instead of compute reset\n"); do_reset: /* Re-entry of reset thread */ @@ -1241,13 +1345,20 @@ do_reset: /* Block future CS/VM/JOB completion operations */ spin_lock(&hdev->reset_info.lock); if (hdev->reset_info.in_reset) { - /* We only allow scheduling of a hard reset during soft reset */ - if (hard_reset && hdev->reset_info.is_in_soft_reset) + /* We only allow scheduling of a hard reset during compute reset */ + if (hard_reset && hdev->reset_info.in_compute_reset) hdev->reset_info.hard_reset_schedule_flags = flags; spin_unlock(&hdev->reset_info.lock); return 0; } + + /* This still allows the completion of some KDMA ops + * Update this before in_reset because in_compute_reset implies we are in reset + */ + hdev->reset_info.in_compute_reset = !hard_reset; + hdev->reset_info.in_reset = 1; + spin_unlock(&hdev->reset_info.lock); if (delay_reset) @@ -1255,9 +1366,6 @@ do_reset: handle_reset_trigger(hdev, flags); - /* This still allows the completion of some KDMA ops */ - hdev->reset_info.is_in_soft_reset = !hard_reset; - /* This also blocks future CS/VM/JOB completion operations */ hdev->disabled = true; @@ -1445,7 +1553,8 @@ kill_processes: goto out_err; } - hl_fw_set_max_power(hdev); + if (!hdev->asic_prop.fw_security_enabled) + hl_fw_set_max_power(hdev); } else { rc = hdev->asic_funcs->non_hard_reset_late_init(hdev); if (rc) { @@ -1453,13 +1562,19 @@ kill_processes: dev_err(hdev->dev, "Failed late init in reset after device release\n"); else - dev_err(hdev->dev, "Failed late init after soft reset\n"); + dev_err(hdev->dev, "Failed late init after compute reset\n"); goto out_err; } } + rc = hdev->asic_funcs->scrub_device_mem(hdev); + if (rc) { + dev_err(hdev->dev, "scrub mem failed from device reset (%d)\n", rc); + return rc; + } + spin_lock(&hdev->reset_info.lock); - hdev->reset_info.is_in_soft_reset = false; + hdev->reset_info.in_compute_reset = 0; /* Schedule hard reset only if requested and if not already in hard reset. * We keep 'in_reset' enabled, so no other reset can go in during the hard @@ -1489,11 +1604,11 @@ kill_processes: */ hdev->asic_funcs->enable_events_from_fw(hdev); } else if (!reset_upon_device_release) { - hdev->reset_info.soft_reset_cnt++; + hdev->reset_info.compute_reset_cnt++; } if (schedule_hard_reset) { - dev_info(hdev->dev, "Performing hard reset scheduled during soft reset\n"); + dev_info(hdev->dev, "Performing hard reset scheduled during compute reset\n"); flags = hdev->reset_info.hard_reset_schedule_flags; hdev->reset_info.hard_reset_schedule_flags = 0; hdev->disabled = true; @@ -1506,20 +1621,24 @@ kill_processes: out_err: hdev->disabled = true; - hdev->reset_info.is_in_soft_reset = false; + + spin_lock(&hdev->reset_info.lock); + hdev->reset_info.in_compute_reset = 0; if (hard_reset) { dev_err(hdev->dev, "Failed to reset! Device is NOT usable\n"); hdev->reset_info.hard_reset_cnt++; } else if (reset_upon_device_release) { + spin_unlock(&hdev->reset_info.lock); dev_err(hdev->dev, "Failed to reset device after user release\n"); flags |= HL_DRV_RESET_HARD; flags &= ~HL_DRV_RESET_DEV_RELEASE; hard_reset = true; goto again; } else { - dev_err(hdev->dev, "Failed to do soft-reset\n"); - hdev->reset_info.soft_reset_cnt++; + spin_unlock(&hdev->reset_info.lock); + dev_err(hdev->dev, "Failed to do compute reset\n"); + hdev->reset_info.compute_reset_cnt++; flags |= HL_DRV_RESET_HARD; hard_reset = true; goto again; @@ -1527,13 +1646,16 @@ out_err: hdev->reset_info.in_reset = 0; + spin_unlock(&hdev->reset_info.lock); + return rc; } -static void hl_notifier_event_send(struct hl_notifier_event *notifier_event, u64 event) +static void hl_notifier_event_send(struct hl_notifier_event *notifier_event, u64 event_mask) { mutex_lock(¬ifier_event->lock); - notifier_event->events_mask |= event; + notifier_event->events_mask |= event_mask; + if (notifier_event->eventfd) eventfd_signal(notifier_event->eventfd, 1); @@ -1544,17 +1666,17 @@ static void hl_notifier_event_send(struct hl_notifier_event *notifier_event, u64 * hl_notifier_event_send_all - notify all user processes via eventfd * * @hdev: pointer to habanalabs device structure - * @event: the occurred event + * @event_mask: the occurred event/s * Returns 0 for success or an error on failure. */ -void hl_notifier_event_send_all(struct hl_device *hdev, u64 event) +void hl_notifier_event_send_all(struct hl_device *hdev, u64 event_mask) { struct hl_fpriv *hpriv; mutex_lock(&hdev->fpriv_list_lock); list_for_each_entry(hpriv, &hdev->fpriv_list, dev_node) - hl_notifier_event_send(&hpriv->notifier_event, event); + hl_notifier_event_send(&hpriv->notifier_event, event_mask); mutex_unlock(&hdev->fpriv_list_lock); @@ -1562,7 +1684,7 @@ void hl_notifier_event_send_all(struct hl_device *hdev, u64 event) mutex_lock(&hdev->fpriv_ctrl_list_lock); list_for_each_entry(hpriv, &hdev->fpriv_ctrl_list, dev_node) - hl_notifier_event_send(&hpriv->notifier_event, event); + hl_notifier_event_send(&hpriv->notifier_event, event_mask); mutex_unlock(&hdev->fpriv_ctrl_list_lock); } @@ -1617,13 +1739,12 @@ int hl_device_init(struct hl_device *hdev, struct class *hclass) if (rc) goto free_dev_ctrl; - user_interrupt_cnt = hdev->asic_prop.user_interrupt_count; + user_interrupt_cnt = hdev->asic_prop.user_dec_intr_count + + hdev->asic_prop.user_interrupt_count; if (user_interrupt_cnt) { - hdev->user_interrupt = kcalloc(user_interrupt_cnt, - sizeof(*hdev->user_interrupt), - GFP_KERNEL); - + hdev->user_interrupt = kcalloc(user_interrupt_cnt, sizeof(*hdev->user_interrupt), + GFP_KERNEL); if (!hdev->user_interrupt) { rc = -ENOMEM; goto early_fini; @@ -1636,7 +1757,7 @@ int hl_device_init(struct hl_device *hdev, struct class *hclass) */ rc = hdev->asic_funcs->sw_init(hdev); if (rc) - goto user_interrupts_fini; + goto free_usr_intr_mem; /* initialize completion structure for multi CS wait */ @@ -1684,6 +1805,13 @@ int hl_device_init(struct hl_device *hdev, struct class *hclass) hdev->completion_queue[i].cq_idx = i; } + hdev->shadow_cs_queue = kcalloc(hdev->asic_prop.max_pending_cs, + sizeof(*hdev->shadow_cs_queue), GFP_KERNEL); + if (!hdev->shadow_cs_queue) { + rc = -ENOMEM; + goto cq_fini; + } + /* * Initialize the event queue. Must be done before hw_init, * because there the address of the event queue is being @@ -1692,7 +1820,7 @@ int hl_device_init(struct hl_device *hdev, struct class *hclass) rc = hl_eq_init(hdev, &hdev->event_queue); if (rc) { dev_err(hdev->dev, "failed to initialize event queue\n"); - goto cq_fini; + goto free_shadow_cs_queue; } /* MMU S/W must be initialized before kernel context is created */ @@ -1713,6 +1841,7 @@ int hl_device_init(struct hl_device *hdev, struct class *hclass) hdev->asic_funcs->state_dump_init(hdev); + hdev->memory_scrub_val = MEM_SCRUB_DEFAULT_VAL; hl_debugfs_add_device(hdev); /* debugfs nodes are created in hl_ctx_init so it must be called after @@ -1731,6 +1860,12 @@ int hl_device_init(struct hl_device *hdev, struct class *hclass) goto release_ctx; } + rc = hl_dec_init(hdev); + if (rc) { + dev_err(hdev->dev, "Failed to initialize the decoder module\n"); + goto cb_pool_fini; + } + /* * From this point, override rc (=0) in case of an error to allow * debugging (by adding char devices and create sysfs nodes as part of @@ -1794,7 +1929,8 @@ int hl_device_init(struct hl_device *hdev, struct class *hclass) /* Need to call this again because the max power might change, * depending on card type for certain ASICs */ - if (hdev->asic_prop.set_max_power_on_device_init) + if (hdev->asic_prop.set_max_power_on_device_init && + !hdev->asic_prop.fw_security_enabled) hl_fw_set_max_power(hdev); /* @@ -1824,6 +1960,8 @@ int hl_device_init(struct hl_device *hdev, struct class *hclass) return 0; +cb_pool_fini: + hl_cb_pool_fini(hdev); release_ctx: if (hl_ctx_put(hdev->kernel_ctx) != 1) dev_err(hdev->dev, @@ -1834,6 +1972,8 @@ mmu_fini: hl_mmu_fini(hdev); eq_fini: hl_eq_fini(hdev, &hdev->event_queue); +free_shadow_cs_queue: + kfree(hdev->shadow_cs_queue); cq_fini: for (i = 0 ; i < cq_ready_cnt ; i++) hl_cq_fini(hdev, &hdev->completion_queue[i]); @@ -1842,7 +1982,7 @@ hw_queues_destroy: hl_hw_queues_destroy(hdev); sw_fini: hdev->asic_funcs->sw_fini(hdev); -user_interrupts_fini: +free_usr_intr_mem: kfree(hdev->user_interrupt); early_fini: device_early_fini(hdev); @@ -1928,7 +2068,7 @@ void hl_device_fini(struct hl_device *hdev) * message won't be send. Also, in case of heartbeat, the device CPU is * marked as disable so this message won't be sent */ - hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS); + hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS, 0x0); /* Mark device as disabled */ hdev->disabled = true; @@ -1974,12 +2114,16 @@ void hl_device_fini(struct hl_device *hdev) hl_debugfs_remove_device(hdev); + hl_dec_fini(hdev); + hl_vm_fini(hdev); hl_mmu_fini(hdev); hl_eq_fini(hdev, &hdev->event_queue); + kfree(hdev->shadow_cs_queue); + for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) hl_cq_fini(hdev, &hdev->completion_queue[i]); kfree(hdev->completion_queue); diff --git a/drivers/misc/habanalabs/common/firmware_if.c b/drivers/misc/habanalabs/common/firmware_if.c index 828a36af5b14..608ca67527a5 100644 --- a/drivers/misc/habanalabs/common/firmware_if.c +++ b/drivers/misc/habanalabs/common/firmware_if.c @@ -15,6 +15,14 @@ #define FW_FILE_MAX_SIZE 0x1400000 /* maximum size of 20MB */ +struct fw_binning_conf { + u64 tpc_binning; + u32 dec_binning; + u32 hbm_binning; + u32 edma_binning; + u32 mme_redundancy; +}; + static char *extract_fw_ver_from_str(const char *fw_str) { char *str, *fw_ver, *whitespace; @@ -33,7 +41,7 @@ static char *extract_fw_ver_from_str(const char *fw_str) ver_offset = str - fw_str; /* Copy until the next whitespace */ - whitespace = strnstr(str, " ", VERSION_MAX_LEN - ver_offset); + whitespace = strnstr(str, " ", VERSION_MAX_LEN - ver_offset); if (!whitespace) goto free_fw_ver; @@ -46,6 +54,43 @@ free_fw_ver: return NULL; } +static int extract_fw_sub_versions(struct hl_device *hdev, char *preboot_ver) +{ + char major[8], minor[8], *first_dot, *second_dot; + int rc; + + first_dot = strnstr(preboot_ver, ".", 10); + if (first_dot) { + strscpy(major, preboot_ver, first_dot - preboot_ver + 1); + rc = kstrtou32(major, 10, &hdev->fw_major_version); + } else { + rc = -EINVAL; + } + + if (rc) { + dev_err(hdev->dev, "Error %d parsing preboot major version\n", rc); + goto out; + } + + /* skip the first dot */ + first_dot++; + + second_dot = strnstr(first_dot, ".", 10); + if (second_dot) { + strscpy(minor, first_dot, second_dot - first_dot + 1); + rc = kstrtou32(minor, 10, &hdev->fw_minor_version); + } else { + rc = -EINVAL; + } + + if (rc) + dev_err(hdev->dev, "Error %d parsing preboot minor version\n", rc); + +out: + kfree(preboot_ver); + return rc; +} + static int hl_request_fw(struct hl_device *hdev, const struct firmware **firmware_p, const char *fw_name) @@ -197,14 +242,14 @@ int hl_fw_load_fw_to_device(struct hl_device *hdev, const char *fw_name, return rc; } -int hl_fw_send_pci_access_msg(struct hl_device *hdev, u32 opcode) +int hl_fw_send_pci_access_msg(struct hl_device *hdev, u32 opcode, u64 value) { struct cpucp_packet pkt = {}; pkt.ctl = cpu_to_le32(opcode << CPUCP_PKT_CTL_OPCODE_SHIFT); + pkt.value = cpu_to_le64(value); - return hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, - sizeof(pkt), 0, NULL); + return hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), 0, NULL); } int hl_fw_send_cpu_message(struct hl_device *hdev, u32 hw_queue_id, u32 *msg, @@ -218,8 +263,7 @@ int hl_fw_send_cpu_message(struct hl_device *hdev, u32 hw_queue_id, u32 *msg, u32 tmp, expected_ack_val, pi; int rc; - pkt = hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev, len, - &pkt_dma_addr); + pkt = hl_cpu_accessible_dma_pool_alloc(hdev, len, &pkt_dma_addr); if (!pkt) { dev_err(hdev->dev, "Failed to allocate DMA memory for packet to CPU\n"); @@ -231,7 +275,7 @@ int hl_fw_send_cpu_message(struct hl_device *hdev, u32 hw_queue_id, u32 *msg, mutex_lock(&hdev->send_cpu_message_lock); /* CPU-CP messages can be sent during soft-reset */ - if (hdev->disabled && !hdev->reset_info.is_in_soft_reset) { + if (hdev->disabled && !hdev->reset_info.in_compute_reset) { rc = 0; goto out; } @@ -267,7 +311,14 @@ int hl_fw_send_cpu_message(struct hl_device *hdev, u32 hw_queue_id, u32 *msg, hl_hw_queue_inc_ci_kernel(hdev, hw_queue_id); if (rc == -ETIMEDOUT) { - dev_err(hdev->dev, "Device CPU packet timeout (0x%x)\n", tmp); + /* If FW performed reset just before sending it a packet, we will get a timeout. + * This is expected behavior, hence no need for error message. + */ + if (!hl_device_operational(hdev, NULL) && !hdev->reset_info.in_compute_reset) + dev_dbg(hdev->dev, "Device CPU packet timeout (0x%x) due to FW reset\n", + tmp); + else + dev_err(hdev->dev, "Device CPU packet timeout (0x%x)\n", tmp); hdev->device_cpu_disabled = true; goto out; } @@ -276,11 +327,15 @@ int hl_fw_send_cpu_message(struct hl_device *hdev, u32 hw_queue_id, u32 *msg, rc = (tmp & CPUCP_PKT_CTL_RC_MASK) >> CPUCP_PKT_CTL_RC_SHIFT; if (rc) { - dev_err(hdev->dev, "F/W ERROR %d for CPU packet %d\n", - rc, - (tmp & CPUCP_PKT_CTL_OPCODE_MASK) - >> CPUCP_PKT_CTL_OPCODE_SHIFT); + dev_dbg(hdev->dev, "F/W ERROR %d for CPU packet %d\n", + rc, (tmp & CPUCP_PKT_CTL_OPCODE_MASK) >> CPUCP_PKT_CTL_OPCODE_SHIFT); + + /* propagate the return code from the f/w to the callers who want to check it */ + if (result) + *result = rc; + rc = -EIO; + } else if (result) { *result = le64_to_cpu(pkt->result); } @@ -296,7 +351,7 @@ int hl_fw_send_cpu_message(struct hl_device *hdev, u32 hw_queue_id, u32 *msg, out: mutex_unlock(&hdev->send_cpu_message_lock); - hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev, len, pkt); + hl_cpu_accessible_dma_pool_free(hdev, len, pkt); return rc; } @@ -517,6 +572,11 @@ static bool fw_report_boot_dev0(struct hl_device *hdev, u32 err_val, err_val &= ~CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL; } + if (err_val & CPU_BOOT_ERR0_BINNING_FAIL) { + dev_err(hdev->dev, "Device boot error - binning failure\n"); + err_exists = true; + } + if (sts_val & CPU_BOOT_DEV_STS0_ENABLED) dev_dbg(hdev->dev, "Device status0 %#x\n", sts_val); @@ -637,10 +697,8 @@ int hl_fw_cpucp_info_get(struct hl_device *hdev, u64 result; int rc; - cpucp_info_cpu_addr = - hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev, - sizeof(struct cpucp_info), - &cpucp_info_dma_addr); + cpucp_info_cpu_addr = hl_cpu_accessible_dma_pool_alloc(hdev, sizeof(struct cpucp_info), + &cpucp_info_dma_addr); if (!cpucp_info_cpu_addr) { dev_err(hdev->dev, "Failed to allocate DMA memory for CPU-CP info packet\n"); @@ -701,8 +759,7 @@ int hl_fw_cpucp_info_get(struct hl_device *hdev, prop->fw_app_cpu_boot_dev_sts1 = RREG32(sts_boot_dev_sts1_reg); out: - hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev, - sizeof(struct cpucp_info), cpucp_info_cpu_addr); + hl_cpu_accessible_dma_pool_free(hdev, sizeof(struct cpucp_info), cpucp_info_cpu_addr); return rc; } @@ -785,9 +842,8 @@ int hl_fw_get_eeprom_data(struct hl_device *hdev, void *data, size_t max_size) u64 result; int rc; - eeprom_info_cpu_addr = - hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev, - max_size, &eeprom_info_dma_addr); + eeprom_info_cpu_addr = hl_cpu_accessible_dma_pool_alloc(hdev, max_size, + &eeprom_info_dma_addr); if (!eeprom_info_cpu_addr) { dev_err(hdev->dev, "Failed to allocate DMA memory for CPU-CP EEPROM packet\n"); @@ -815,8 +871,7 @@ int hl_fw_get_eeprom_data(struct hl_device *hdev, void *data, size_t max_size) memcpy(data, eeprom_info_cpu_addr, min((size_t)result, max_size)); out: - hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev, max_size, - eeprom_info_cpu_addr); + hl_cpu_accessible_dma_pool_free(hdev, max_size, eeprom_info_cpu_addr); return rc; } @@ -833,8 +888,7 @@ int hl_fw_get_monitor_dump(struct hl_device *hdev, void *data) int i, rc; data_size = sizeof(struct cpucp_monitor_dump); - mon_dump_cpu_addr = hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev, data_size, - &mon_dump_dma_addr); + mon_dump_cpu_addr = hl_cpu_accessible_dma_pool_alloc(hdev, data_size, &mon_dump_dma_addr); if (!mon_dump_cpu_addr) { dev_err(hdev->dev, "Failed to allocate DMA memory for CPU-CP monitor-dump packet\n"); @@ -864,7 +918,7 @@ int hl_fw_get_monitor_dump(struct hl_device *hdev, void *data) } out: - hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev, data_size, mon_dump_cpu_addr); + hl_cpu_accessible_dma_pool_free(hdev, data_size, mon_dump_cpu_addr); return rc; } @@ -1057,10 +1111,9 @@ int hl_fw_dram_replaced_row_get(struct hl_device *hdev, u64 result; int rc; - cpucp_repl_rows_info_cpu_addr = - hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev, - sizeof(struct cpucp_hbm_row_info), - &cpucp_repl_rows_info_dma_addr); + cpucp_repl_rows_info_cpu_addr = hl_cpu_accessible_dma_pool_alloc(hdev, + sizeof(struct cpucp_hbm_row_info), + &cpucp_repl_rows_info_dma_addr); if (!cpucp_repl_rows_info_cpu_addr) { dev_err(hdev->dev, "Failed to allocate DMA memory for CPU-CP replaced rows info packet\n"); @@ -1085,9 +1138,8 @@ int hl_fw_dram_replaced_row_get(struct hl_device *hdev, memcpy(info, cpucp_repl_rows_info_cpu_addr, sizeof(*info)); out: - hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev, - sizeof(struct cpucp_hbm_row_info), - cpucp_repl_rows_info_cpu_addr); + hl_cpu_accessible_dma_pool_free(hdev, sizeof(struct cpucp_hbm_row_info), + cpucp_repl_rows_info_cpu_addr); return rc; } @@ -1234,15 +1286,10 @@ static void detect_cpu_boot_status(struct hl_device *hdev, u32 status) } } -static int hl_fw_read_preboot_caps(struct hl_device *hdev, - u32 cpu_boot_status_reg, - u32 sts_boot_dev_sts0_reg, - u32 sts_boot_dev_sts1_reg, - u32 boot_err0_reg, u32 boot_err1_reg, - u32 timeout) +static int hl_fw_wait_preboot_ready(struct hl_device *hdev) { - struct asic_fixed_properties *prop = &hdev->asic_prop; - u32 status, reg_val; + struct pre_fw_load_props *pre_fw_load = &hdev->fw_loader.pre_fw_load; + u32 status; int rc; /* Need to check two possible scenarios: @@ -1255,13 +1302,13 @@ static int hl_fw_read_preboot_caps(struct hl_device *hdev, */ rc = hl_poll_timeout( hdev, - cpu_boot_status_reg, + pre_fw_load->cpu_boot_status_reg, status, (status == CPU_BOOT_STATUS_NIC_FW_RDY) || (status == CPU_BOOT_STATUS_READY_TO_BOOT) || (status == CPU_BOOT_STATUS_WAITING_FOR_BOOT_FIT), hdev->fw_poll_interval_usec, - timeout); + pre_fw_load->wait_for_preboot_timeout); if (rc) { dev_err(hdev->dev, "CPU boot ready status timeout\n"); @@ -1271,12 +1318,32 @@ static int hl_fw_read_preboot_caps(struct hl_device *hdev, * of reading specific errors */ if (status != -1) - fw_read_errors(hdev, boot_err0_reg, boot_err1_reg, - sts_boot_dev_sts0_reg, - sts_boot_dev_sts1_reg); + fw_read_errors(hdev, pre_fw_load->boot_err0_reg, + pre_fw_load->boot_err1_reg, + pre_fw_load->sts_boot_dev_sts0_reg, + pre_fw_load->sts_boot_dev_sts1_reg); return -EIO; } + hdev->fw_loader.fw_comp_loaded |= FW_TYPE_PREBOOT_CPU; + + return 0; +} + +static int hl_fw_read_preboot_caps(struct hl_device *hdev) +{ + struct pre_fw_load_props *pre_fw_load; + struct asic_fixed_properties *prop; + u32 reg_val; + int rc; + + prop = &hdev->asic_prop; + pre_fw_load = &hdev->fw_loader.pre_fw_load; + + rc = hl_fw_wait_preboot_ready(hdev); + if (rc) + return rc; + /* * the registers DEV_STS* contain FW capabilities/features. * We can rely on this registers only if bit CPU_BOOT_DEV_STS*_ENABLED @@ -1287,13 +1354,13 @@ static int hl_fw_read_preboot_caps(struct hl_device *hdev, * In case it is not enabled the stored value will be left 0- all * caps/features are off */ - reg_val = RREG32(sts_boot_dev_sts0_reg); + reg_val = RREG32(pre_fw_load->sts_boot_dev_sts0_reg); if (reg_val & CPU_BOOT_DEV_STS0_ENABLED) { prop->fw_cpu_boot_dev_sts0_valid = true; prop->fw_preboot_cpu_boot_dev_sts0 = reg_val; } - reg_val = RREG32(sts_boot_dev_sts1_reg); + reg_val = RREG32(pre_fw_load->sts_boot_dev_sts1_reg); if (reg_val & CPU_BOOT_DEV_STS1_ENABLED) { prop->fw_cpu_boot_dev_sts1_valid = true; prop->fw_preboot_cpu_boot_dev_sts1 = reg_val; @@ -1436,24 +1503,21 @@ static int hl_fw_static_read_preboot_status(struct hl_device *hdev) return 0; } -int hl_fw_read_preboot_status(struct hl_device *hdev, u32 cpu_boot_status_reg, - u32 sts_boot_dev_sts0_reg, - u32 sts_boot_dev_sts1_reg, u32 boot_err0_reg, - u32 boot_err1_reg, u32 timeout) +int hl_fw_read_preboot_status(struct hl_device *hdev) { int rc; if (!(hdev->fw_components & FW_TYPE_PREBOOT_CPU)) return 0; + /* get FW pre-load parameters */ + hdev->asic_funcs->init_firmware_preload_params(hdev); + /* * In order to determine boot method (static VS dymanic) we need to * read the boot caps register */ - rc = hl_fw_read_preboot_caps(hdev, cpu_boot_status_reg, - sts_boot_dev_sts0_reg, - sts_boot_dev_sts1_reg, boot_err0_reg, - boot_err1_reg, timeout); + rc = hl_fw_read_preboot_caps(hdev); if (rc) return rc; @@ -1989,18 +2053,14 @@ static int hl_fw_dynamic_read_device_fw_version(struct hl_device *hdev, preboot_ver = extract_fw_ver_from_str(prop->preboot_ver); if (preboot_ver) { - char major[8]; int rc; dev_info(hdev->dev, "preboot version %s\n", preboot_ver); - sprintf(major, "%.2s", preboot_ver); - kfree(preboot_ver); - rc = kstrtou32(major, 10, &hdev->fw_major_version); - if (rc) { - dev_err(hdev->dev, "Error %d parsing preboot major version\n", rc); + /* This function takes care of freeing preboot_ver */ + rc = extract_fw_sub_versions(hdev, preboot_ver); + if (rc) return rc; - } } break; @@ -2361,6 +2421,19 @@ static int hl_fw_dynamic_send_msg(struct hl_device *hdev, case HL_COMMS_RESET_CAUSE_TYPE: msg.reset_cause = *(__u8 *) data; break; + + case HL_COMMS_BINNING_CONF_TYPE: + { + struct fw_binning_conf *binning_conf = (struct fw_binning_conf *) data; + + msg.tpc_binning_conf = cpu_to_le64(binning_conf->tpc_binning); + msg.dec_binning_conf = cpu_to_le32(binning_conf->dec_binning); + msg.hbm_binning_conf = cpu_to_le32(binning_conf->hbm_binning); + msg.edma_binning_conf = cpu_to_le32(binning_conf->edma_binning); + msg.mme_redundancy_conf = cpu_to_le32(binning_conf->mme_redundancy); + break; + } + default: dev_err(hdev->dev, "Send COMMS message - invalid message type %u\n", @@ -2418,7 +2491,8 @@ static int hl_fw_dynamic_init_cpu(struct hl_device *hdev, int rc; dev_info(hdev->dev, - "Loading firmware to device, may take some time...\n"); + "Loading %sfirmware to device, may take some time...\n", + hdev->asic_prop.fw_security_enabled ? "secured " : ""); /* initialize FW descriptor as invalid */ fw_loader->dynamic_loader.fw_desc_valid = false; @@ -2429,6 +2503,13 @@ static int hl_fw_dynamic_init_cpu(struct hl_device *hdev, */ dyn_regs = &fw_loader->dynamic_loader.comm_desc.cpu_dyn_regs; + /* if no preboot loaded indication- wait for preboot */ + if (!(hdev->fw_loader.fw_comp_loaded & FW_TYPE_PREBOOT_CPU)) { + rc = hl_fw_wait_preboot_ready(hdev); + if (rc) + return -EIO; + } + rc = hl_fw_dynamic_send_protocol_cmd(hdev, fw_loader, COMMS_RST_STATE, 0, true, fw_loader->cpu_timeout); diff --git a/drivers/misc/habanalabs/common/habanalabs.h b/drivers/misc/habanalabs/common/habanalabs.h index b0b0f3f89865..d59bba9e55c9 100644 --- a/drivers/misc/habanalabs/common/habanalabs.h +++ b/drivers/misc/habanalabs/common/habanalabs.h @@ -31,6 +31,9 @@ #define HL_NAME "habanalabs" +struct hl_device; +struct hl_fpriv; + /* Use upper bits of mmap offset to store habana driver specific information. * bits[63:59] - Encode mmap type * bits[45:0] - mmap offset value @@ -69,9 +72,12 @@ #define HL_PCI_ELBI_TIMEOUT_MSEC 10 /* 10ms */ -#define HL_SIM_MAX_TIMEOUT_US 10000000 /* 10s */ +#define HL_SIM_MAX_TIMEOUT_US 100000000 /* 100s */ -#define HL_COMMON_USER_INTERRUPT_ID 0xFFF +#define HL_INVALID_QUEUE UINT_MAX + +#define HL_COMMON_USER_CQ_INTERRUPT_ID 0xFFF +#define HL_COMMON_DEC_INTERRUPT_ID 0xFFE #define HL_STATE_DUMP_HIST_LEN 5 @@ -99,6 +105,18 @@ enum hl_mmu_page_table_location { MMU_NUM_PGT_LOCATIONS /* num of PGT locations */ }; +/** + * enum hl_mmu_enablement - what mmu modules to enable + * @MMU_EN_NONE: mmu disabled. + * @MMU_EN_ALL: enable all. + * @MMU_EN_PMMU_ONLY: Enable only the PMMU leaving the DMMU disabled. + */ +enum hl_mmu_enablement { + MMU_EN_NONE = 0, + MMU_EN_ALL = 1, + MMU_EN_PMMU_ONLY = 3, /* N/A for Goya/Gaudi */ +}; + /* * HL_RSVD_SOBS 'sync stream' reserved sync objects per QMAN stream * HL_RSVD_MONS 'sync stream' reserved monitors per QMAN stream @@ -118,7 +136,12 @@ enum hl_mmu_page_table_location { #define HL_PCI_NUM_BARS 6 -#define HL_MAX_DCORES 4 +/* Completion queue entry relates to completed job */ +#define HL_COMPLETION_MODE_JOB 0 +/* Completion queue entry relates to completed command submission */ +#define HL_COMPLETION_MODE_CS 1 + +#define HL_MAX_DCORES 8 /* * Reset Flags @@ -159,6 +182,51 @@ enum hl_mmu_page_table_location { #define HL_DRV_RESET_FW_FATAL_ERR (1 << 6) #define HL_DRV_RESET_DELAY (1 << 7) +/* + * Security + */ + +#define HL_PB_SHARED 1 +#define HL_PB_NA 0 +#define HL_PB_SINGLE_INSTANCE 1 +#define HL_BLOCK_SIZE 0x1000 +#define HL_BLOCK_GLBL_ERR_MASK 0xF40 +#define HL_BLOCK_GLBL_ERR_ADDR 0xF44 +#define HL_BLOCK_GLBL_ERR_CAUSE 0xF48 +#define HL_BLOCK_GLBL_SEC_OFFS 0xF80 +#define HL_BLOCK_GLBL_SEC_SIZE (HL_BLOCK_SIZE - HL_BLOCK_GLBL_SEC_OFFS) +#define HL_BLOCK_GLBL_SEC_LEN (HL_BLOCK_GLBL_SEC_SIZE / sizeof(u32)) +#define UNSET_GLBL_SEC_BIT(array, b) ((array)[((b) / 32)] |= (1 << ((b) % 32))) + +enum hl_protection_levels { + SECURED_LVL, + PRIVILEGED_LVL, + NON_SECURED_LVL +}; + +/** + * struct iterate_module_ctx - HW module iterator + * @fn: function to apply to each HW module instance + * @data: optional internal data to the function iterator + */ +struct iterate_module_ctx { + /* + * callback for the HW module iterator + * @hdev: pointer to the habanalabs device structure + * @block: block (ASIC specific definition can be dcore/hdcore) + * @inst: HW module instance within the block + * @offset: current HW module instance offset from the 1-st HW module instance + * in the 1-st block + * @data: function specific data + */ + void (*fn)(struct hl_device *hdev, int block, int inst, u32 offset, void *data); + void *data; +}; + +struct hl_block_glbl_sec { + u32 sec_array[HL_BLOCK_GLBL_SEC_LEN]; +}; + #define HL_MAX_SOBS_PER_MONITOR 8 /** @@ -183,28 +251,32 @@ struct hl_gen_wait_properties { /** * struct pgt_info - MMU hop page info. - * @node: hash linked-list node for the pgts shadow hash of pgts. + * @node: hash linked-list node for the pgts on host (shadow pgts for device resident MMU and + * actual pgts for host resident MMU). * @phys_addr: physical address of the pgt. - * @shadow_addr: shadow hop in the host. + * @virt_addr: host virtual address of the pgt (see above device/host resident). + * @shadow_addr: shadow hop in the host for device resident MMU. * @ctx: pointer to the owner ctx. - * @num_of_ptes: indicates how many ptes are used in the pgt. + * @num_of_ptes: indicates how many ptes are used in the pgt. used only for dynamically + * allocated HOPs (all HOPs but HOP0) * - * The MMU page tables hierarchy is placed on the DRAM. When a new level (hop) - * is needed during mapping, a new page is allocated and this structure holds - * its essential information. During unmapping, if no valid PTEs remained in the - * page, it is freed with its pgt_info structure. + * The MMU page tables hierarchy can be placed either on the device's DRAM (in which case shadow + * pgts will be stored on host memory) or on host memory (in which case no shadow is required). + * + * When a new level (hop) is needed during mapping this structure will be used to describe + * the newly allocated hop as well as to track number of PTEs in it. + * During unmapping, if no valid PTEs remained in the page of a newly allocated hop, it is + * freed with its pgt_info structure. */ struct pgt_info { struct hlist_node node; u64 phys_addr; + u64 virt_addr; u64 shadow_addr; struct hl_ctx *ctx; int num_of_ptes; }; -struct hl_device; -struct hl_fpriv; - /** * enum hl_pci_match_mode - pci match mode per region * @PCI_ADDRESS_MATCH_MODE: address match mode @@ -337,21 +409,23 @@ enum hl_collective_mode { /** * struct hw_queue_properties - queue information. * @type: queue type. - * @queue_cb_alloc_flags: bitmap which indicates if the hw queue supports CB - * that allocated by the Kernel driver and therefore, - * a CB handle can be provided for jobs on this queue. - * Otherwise, a CB address must be provided. + * @cb_alloc_flags: bitmap which indicates if the hw queue supports CB + * that allocated by the Kernel driver and therefore, + * a CB handle can be provided for jobs on this queue. + * Otherwise, a CB address must be provided. * @collective_mode: collective mode of current queue * @driver_only: true if only the driver is allowed to send a job to this queue, * false otherwise. + * @binned: True if the queue is binned out and should not be used * @supports_sync_stream: True if queue supports sync stream */ struct hw_queue_properties { - enum hl_queue_type type; - enum queue_cb_alloc_flags cb_alloc_flags; - enum hl_collective_mode collective_mode; - u8 driver_only; - u8 supports_sync_stream; + enum hl_queue_type type; + enum queue_cb_alloc_flags cb_alloc_flags; + enum hl_collective_mode collective_mode; + u8 driver_only; + u8 binned; + u8 supports_sync_stream; }; /** @@ -401,6 +475,8 @@ enum hl_device_hw_state { * @hop_masks: array holds HOPs masks. * @last_mask: mask to get the bit indicating this is the last hop. * @pgt_size: size for page tables. + * @supported_pages_mask: bitmask for supported page size (relevant only for MMUs + * supporting multiple page size). * @page_size: default page size used to allocate memory. * @num_hops: The amount of hops supported by the translation table. * @hop_table_size: HOP table size. @@ -415,6 +491,7 @@ struct hl_mmu_properties { u64 hop_masks[MMU_HOP_MAX]; u64 last_mask; u64 pgt_size; + u64 supported_pages_mask; u32 page_size; u32 num_hops; u32 hop_table_size; @@ -455,7 +532,7 @@ struct hl_hints_range { * @dram_user_base_address: DRAM physical start address for user access. * @dram_size: DRAM total size. * @dram_pci_bar_size: size of PCI bar towards DRAM. - * @max_power_default: max power of the device after reset + * @max_power_default: max power of the device after reset. * @dc_power_default: power consumed by the device in mode idle. * @dram_size_for_default_page_mapping: DRAM size needed to map to avoid page * fault. @@ -463,12 +540,19 @@ struct hl_hints_range { * @pcie_aux_dbi_reg_addr: Address of the PCIE_AUX DBI register. * @mmu_pgt_addr: base physical address in DRAM of MMU page tables. * @mmu_dram_default_page_addr: DRAM default page physical address. + * @tpc_enabled_mask: which TPCs are enabled. + * @tpc_binning_mask: which TPCs are binned. 0 means usable and 1 means binned. + * @dram_enabled_mask: which DRAMs are enabled. + * @dram_binning_mask: which DRAMs are binned. 0 means usable, 1 means binned. * @cb_va_start_addr: virtual start address of command buffers which are mapped * to the device's MMU. * @cb_va_end_addr: virtual end address of command buffers which are mapped to * the device's MMU. * @dram_hints_align_mask: dram va hint addresses alignment mask which is used * for hints validity check. + * @cfg_base_address: config space base address. + * @mmu_cache_mng_addr: address of the MMU cache. + * @mmu_cache_mng_size: size of the MMU cache. * @device_dma_offset_for_host_access: the offset to add to host DMA addresses * to enable the device to access them. * @host_base_address: host physical start address for host DMA from device @@ -493,6 +577,12 @@ struct hl_hints_range { * @high_pll: high PLL frequency used by the device. * @cb_pool_cb_cnt: number of CBs in the CB pool. * @cb_pool_cb_size: size of each CB in the CB pool. + * @decoder_enabled_mask: which decoders are enabled. + * @decoder_binning_mask: which decoders are binned, 0 means usable and 1 + * means binned (at most one binned decoder per dcore). + * @edma_enabled_mask: which EDMAs are enabled. + * @edma_binning_mask: which EDMAs are binned, 0 means usable and 1 means + * binned (at most one binned DMA). * @max_pending_cs: maximum of concurrent pending command submissions * @max_queues: maximum amount of queues in the system * @fw_preboot_cpu_boot_dev_sts0: bitmap representation of preboot cpu @@ -513,6 +603,13 @@ struct hl_hints_range { * @fw_app_cpu_boot_dev_sts1: bitmap representation of application security * status reported by FW, bit description can be * found in CPU_BOOT_DEV_STS1 + * @max_dec: maximum number of decoders + * @hmmu_hif_enabled_mask: mask of HMMUs/HIFs that are not isolated (enabled) + * 1- enabled, 0- isolated. + * @faulty_dram_cluster_map: mask of faulty DRAM cluster. + * 1- faulty cluster, 0- good cluster. + * @xbar_edge_enabled_mask: mask of XBAR_EDGEs that are not isolated (enabled) + * 1- enabled, 0- isolated. * @device_mem_alloc_default_page_size: may be different than dram_page_size only for ASICs for * which the property supports_user_set_page_size is true * (i.e. the DRAM supports multiple page sizes), otherwise @@ -523,14 +620,17 @@ struct hl_hints_range { * @sync_stream_first_mon: first monitor available for sync stream use * @first_available_user_sob: first sob available for the user * @first_available_user_mon: first monitor available for the user - * @first_available_user_msix_interrupt: first available msix interrupt - * reserved for the user + * @first_available_user_interrupt: first available interrupt reserved for the user * @first_available_cq: first available CQ for the user. * @user_interrupt_count: number of user interrupts. + * @user_dec_intr_count: number of decoder interrupts exposed to user. + * @cache_line_size: device cache line size. * @server_type: Server type that the ASIC is currently installed in. * The value is according to enum hl_server_type in uapi file. - * @tpc_enabled_mask: which TPCs are enabled. * @completion_queues_count: number of completion queues. + * @completion_mode: 0 - job based completion, 1 - cs based completion + * @mme_master_slave_mode: 0 - Each MME works independently, 1 - MME works + * in Master/Slave mode * @fw_security_enabled: true if security measures are enabled in firmware, * false otherwise * @fw_cpu_boot_dev_sts0_valid: status bits are valid and can be fetched from @@ -547,7 +647,7 @@ struct hl_hints_range { * false otherwise. * @use_get_power_for_reset_history: To support backward compatibility for Goya * and Gaudi - * @supports_soft_reset: is soft reset supported. + * @supports_compute_reset: is a reset which is not a hard-reset supported by this asic. * @allow_inference_soft_reset: true if the ASIC supports soft reset that is * initiated by user or TDR. This is only true * in inference ASICs, as there is no real-world @@ -585,9 +685,16 @@ struct asic_fixed_properties { u64 pcie_aux_dbi_reg_addr; u64 mmu_pgt_addr; u64 mmu_dram_default_page_addr; + u64 tpc_enabled_mask; + u64 tpc_binning_mask; + u64 dram_enabled_mask; + u64 dram_binning_mask; u64 cb_va_start_addr; u64 cb_va_end_addr; u64 dram_hints_align_mask; + u64 cfg_base_address; + u64 mmu_cache_mng_addr; + u64 mmu_cache_mng_size; u64 device_dma_offset_for_host_access; u64 host_base_address; u64 host_end_address; @@ -610,6 +717,10 @@ struct asic_fixed_properties { u32 high_pll; u32 cb_pool_cb_cnt; u32 cb_pool_cb_size; + u32 decoder_enabled_mask; + u32 decoder_binning_mask; + u32 edma_enabled_mask; + u32 edma_binning_mask; u32 max_pending_cs; u32 max_queues; u32 fw_preboot_cpu_boot_dev_sts0; @@ -618,6 +729,10 @@ struct asic_fixed_properties { u32 fw_bootfit_cpu_boot_dev_sts1; u32 fw_app_cpu_boot_dev_sts0; u32 fw_app_cpu_boot_dev_sts1; + u32 max_dec; + u32 hmmu_hif_enabled_mask; + u32 faulty_dram_cluster_map; + u32 xbar_edge_enabled_mask; u32 device_mem_alloc_default_page_size; u16 collective_first_sob; u16 collective_first_mon; @@ -625,12 +740,15 @@ struct asic_fixed_properties { u16 sync_stream_first_mon; u16 first_available_user_sob[HL_MAX_DCORES]; u16 first_available_user_mon[HL_MAX_DCORES]; - u16 first_available_user_msix_interrupt; + u16 first_available_user_interrupt; u16 first_available_cq[HL_MAX_DCORES]; u16 user_interrupt_count; + u16 user_dec_intr_count; + u16 cache_line_size; u16 server_type; - u8 tpc_enabled_mask; u8 completion_queues_count; + u8 completion_mode; + u8 mme_master_slave_mode; u8 fw_security_enabled; u8 fw_cpu_boot_dev_sts0_valid; u8 fw_cpu_boot_dev_sts1_valid; @@ -642,7 +760,7 @@ struct asic_fixed_properties { u8 dynamic_fw_load; u8 gic_interrupts_enable; u8 use_get_power_for_reset_history; - u8 supports_soft_reset; + u8 supports_compute_reset; u8 allow_inference_soft_reset; u8 configurable_stop_on_err; u8 set_max_power_on_device_init; @@ -811,7 +929,6 @@ struct hl_cb { * QUEUES */ -struct hl_cs; struct hl_cs_job; /* Queue length of external and HW queues */ @@ -934,12 +1051,14 @@ struct hl_cq { * @wait_list_head: head to the list of user threads pending on this interrupt * @wait_list_lock: protects wait_list_head * @interrupt_id: msix interrupt id + * @is_decoder: whether this entry represents a decoder interrupt */ struct hl_user_interrupt { struct hl_device *hdev; struct list_head wait_list_head; spinlock_t wait_list_lock; u32 interrupt_id; + bool is_decoder; }; /** @@ -1025,23 +1144,36 @@ struct hl_eq { bool check_eqe_index; }; - -/* - * ASICs +/** + * struct hl_dec - describes a decoder sw instance. + * @hdev: pointer to the device structure. + * @completion_abnrm_work: workqueue object to run when decoder generates an error interrupt + * @core_id: ID of the decoder. + * @base_addr: base address of the decoder. */ +struct hl_dec { + struct hl_device *hdev; + struct work_struct completion_abnrm_work; + u32 core_id; + u32 base_addr; +}; /** * enum hl_asic_type - supported ASIC types. * @ASIC_INVALID: Invalid ASIC type. - * @ASIC_GOYA: Goya device. - * @ASIC_GAUDI: Gaudi device. + * @ASIC_GOYA: Goya device (HL-1000). + * @ASIC_GAUDI: Gaudi device (HL-2000). * @ASIC_GAUDI_SEC: Gaudi secured device (HL-2000). + * @ASIC_GAUDI2: Gaudi2 device. + * @ASIC_GAUDI2_SEC: Gaudi2 secured device. */ enum hl_asic_type { ASIC_INVALID, ASIC_GOYA, ASIC_GAUDI, - ASIC_GAUDI_SEC + ASIC_GAUDI_SEC, + ASIC_GAUDI2, + ASIC_GAUDI2_SEC, }; struct hl_cs_parser; @@ -1176,6 +1308,24 @@ struct dynamic_fw_load_mgr { bool fw_desc_valid; }; +/** + * struct pre_fw_load_props - needed properties for pre-FW load + * @cpu_boot_status_reg: cpu_boot_status register address + * @sts_boot_dev_sts0_reg: sts_boot_dev_sts0 register address + * @sts_boot_dev_sts1_reg: sts_boot_dev_sts1 register address + * @boot_err0_reg: boot_err0 register address + * @boot_err1_reg: boot_err1 register address + * @wait_for_preboot_timeout: timeout to poll for preboot ready + */ +struct pre_fw_load_props { + u32 cpu_boot_status_reg; + u32 sts_boot_dev_sts0_reg; + u32 sts_boot_dev_sts1_reg; + u32 boot_err0_reg; + u32 boot_err1_reg; + u32 wait_for_preboot_timeout; +}; + /** * struct fw_image_props - properties of FW image * @image_name: name of the image @@ -1192,6 +1342,7 @@ struct fw_image_props { * struct fw_load_mgr - manager FW loading process * @dynamic_loader: specific structure for dynamic load * @static_loader: specific structure for static load + * @pre_fw_load_props: parameter for pre FW load * @boot_fit_img: boot fit image properties * @linux_img: linux image properties * @cpu_timeout: CPU response timeout in usec @@ -1207,6 +1358,7 @@ struct fw_load_mgr { struct dynamic_fw_load_mgr dynamic_loader; struct static_fw_load_mgr static_loader; }; + struct pre_fw_load_props pre_fw_load; struct fw_image_props boot_fit_img; struct fw_image_props linux_img; u32 cpu_timeout; @@ -1217,6 +1369,8 @@ struct fw_load_mgr { u8 fw_comp_loaded; }; +struct hl_cs; + /** * struct hl_asic_funcs - ASIC specific functions that are can be called from * common code. @@ -1248,7 +1402,7 @@ struct fw_load_mgr { * dma_free_coherent(). This is ASIC function because * its implementation is not trivial when the driver * is loaded in simulation mode (not upstreamed). - * @scrub_device_mem: Scrub device memory given an address and size + * @scrub_device_mem: Scrub the entire SRAM and DRAM. * @scrub_device_dram: Scrub the dram memory of the device. * @get_int_queue_base: get the internal queue base address. * @test_queues: run simple test on all queues for sanity check. @@ -1257,10 +1411,11 @@ struct fw_load_mgr { * @asic_dma_pool_free: free small DMA allocation from pool. * @cpu_accessible_dma_pool_alloc: allocate CPU PQ packet from DMA pool. * @cpu_accessible_dma_pool_free: free CPU PQ packet from DMA pool. + * @asic_dma_unmap_single: unmap a single DMA buffer + * @asic_dma_map_single: map a single buffer to a DMA * @hl_dma_unmap_sgtable: DMA unmap scatter-gather table. * @cs_parser: parse Command Submission. * @asic_dma_map_sgtable: DMA map scatter-gather table. - * @get_dma_desc_list_size: get number of LIN_DMA packets required for CB. * @add_end_of_cb_packets: Add packets to the end of CB, if device requires it. * @update_eq_ci: update event queue CI. * @context_switch: called upon ASID context switch. @@ -1282,6 +1437,8 @@ struct fw_load_mgr { * @non_hard_reset_late_init: perform certain actions needed after a reset which is not hard-reset * @hw_queues_lock: acquire H/W queues lock. * @hw_queues_unlock: release H/W queues lock. + * @kdma_lock: acquire H/W queues lock. Relevant from GRECO ASIC + * @kdma_unlock: release H/W queues lock. Relevant from GRECO ASIC * @get_pci_id: retrieve PCI ID. * @get_eeprom_data: retrieve EEPROM data from F/W. * @get_monitor_dump: retrieve monitor registers dump from F/W. @@ -1298,6 +1455,7 @@ struct fw_load_mgr { * @halt_coresight: stop the ETF and ETR traces. * @ctx_init: context dependent initialization. * @ctx_fini: context dependent cleanup. + * @pre_schedule_cs: Perform pre-CS-scheduling operations. * @get_queue_id_for_cq: Get the H/W queue id related to the given CQ index. * @load_firmware_to_device: load the firmware to the device's memory * @load_boot_fit_to_device: load boot fit to device's memory @@ -1308,9 +1466,11 @@ struct fw_load_mgr { * @reset_sob: Reset a SOB. * @reset_sob_group: Reset SOB group * @get_device_time: Get the device time. + * @pb_print_security_errors: print security errors according block and cause * @collective_wait_init_cs: Generate collective master/slave packets * and place them in the relevant cs jobs * @collective_wait_create_jobs: allocate collective wait cs jobs + * @get_dec_base_addr: get the base address of a given decoder. * @scramble_addr: Routine to scramble the address prior of mapping it * in the MMU. * @descramble_addr: Routine to de-scramble the address prior of @@ -1324,18 +1484,18 @@ struct fw_load_mgr { * driver is ready to receive asynchronous events. This * function should be called during the first init and * after every hard-reset of the device + * @ack_mmu_errors: check and ack mmu errors, page fault, access violation. * @get_msi_info: Retrieve asic-specific MSI ID of the f/w async event * @map_pll_idx_to_fw_idx: convert driver specific per asic PLL index to * generic f/w compatible PLL Indexes + * @init_firmware_preload_params: initialize pre FW-load parameters. * @init_firmware_loader: initialize data for FW loader. * @init_cpu_scrambler_dram: Enable CPU specific DRAM scrambling * @state_dump_init: initialize constants required for state dump * @get_sob_addr: get SOB base address offset. * @set_pci_memory_regions: setting properties of PCI memory regions * @get_stream_master_qid_arr: get pointer to stream masters QID array - * @is_valid_dram_page_size: return true if page size is supported in device - * memory allocation, otherwise false. - * @get_valid_dram_page_orders: get valid device memory allocation page orders + * @check_if_razwi_happened: check if there was a razwi due to RR violation. * @access_dev_mem: access device memory * @set_dram_bar_base: set the base of the DRAM BAR */ @@ -1360,7 +1520,7 @@ struct hl_asic_funcs { dma_addr_t *dma_handle, gfp_t flag); void (*asic_dma_free_coherent)(struct hl_device *hdev, size_t size, void *cpu_addr, dma_addr_t dma_handle); - int (*scrub_device_mem)(struct hl_device *hdev, u64 addr, u64 size); + int (*scrub_device_mem)(struct hl_device *hdev); int (*scrub_device_dram)(struct hl_device *hdev, u64 val); void* (*get_int_queue_base)(struct hl_device *hdev, u32 queue_id, dma_addr_t *dma_handle, u16 *queue_len); @@ -1373,16 +1533,21 @@ struct hl_asic_funcs { size_t size, dma_addr_t *dma_handle); void (*cpu_accessible_dma_pool_free)(struct hl_device *hdev, size_t size, void *vaddr); + void (*asic_dma_unmap_single)(struct hl_device *hdev, + dma_addr_t dma_addr, int len, + enum dma_data_direction dir); + dma_addr_t (*asic_dma_map_single)(struct hl_device *hdev, + void *addr, int len, + enum dma_data_direction dir); void (*hl_dma_unmap_sgtable)(struct hl_device *hdev, struct sg_table *sgt, enum dma_data_direction dir); int (*cs_parser)(struct hl_device *hdev, struct hl_cs_parser *parser); int (*asic_dma_map_sgtable)(struct hl_device *hdev, struct sg_table *sgt, enum dma_data_direction dir); - u32 (*get_dma_desc_list_size)(struct hl_device *hdev, - struct sg_table *sgt); void (*add_end_of_cb_packets)(struct hl_device *hdev, void *kernel_address, u32 len, + u32 original_len, u64 cq_addr, u32 cq_val, u32 msix_num, bool eb); void (*update_eq_ci)(struct hl_device *hdev, u32 val); @@ -1410,6 +1575,8 @@ struct hl_asic_funcs { int (*non_hard_reset_late_init)(struct hl_device *hdev); void (*hw_queues_lock)(struct hl_device *hdev); void (*hw_queues_unlock)(struct hl_device *hdev); + void (*kdma_lock)(struct hl_device *hdev, int dcore_id); + void (*kdma_unlock)(struct hl_device *hdev, int dcore_id); u32 (*get_pci_id)(struct hl_device *hdev); int (*get_eeprom_data)(struct hl_device *hdev, void *data, size_t max_size); int (*get_monitor_dump)(struct hl_device *hdev, void *data); @@ -1422,6 +1589,7 @@ struct hl_asic_funcs { void (*halt_coresight)(struct hl_device *hdev, struct hl_ctx *ctx); int (*ctx_init)(struct hl_ctx *ctx); void (*ctx_fini)(struct hl_ctx *ctx); + int (*pre_schedule_cs)(struct hl_cs *cs); u32 (*get_queue_id_for_cq)(struct hl_device *hdev, u32 cq_idx); int (*load_firmware_to_device)(struct hl_device *hdev); int (*load_boot_fit_to_device)(struct hl_device *hdev); @@ -1434,11 +1602,14 @@ struct hl_asic_funcs { void (*reset_sob)(struct hl_device *hdev, void *data); void (*reset_sob_group)(struct hl_device *hdev, u16 sob_group); u64 (*get_device_time)(struct hl_device *hdev); + void (*pb_print_security_errors)(struct hl_device *hdev, + u32 block_addr, u32 cause, u32 offended_addr); int (*collective_wait_init_cs)(struct hl_cs *cs); int (*collective_wait_create_jobs)(struct hl_device *hdev, struct hl_ctx *ctx, struct hl_cs *cs, u32 wait_queue_id, u32 collective_engine_id, u32 encaps_signal_offset); + u32 (*get_dec_base_addr)(struct hl_device *hdev, u32 core_id); u64 (*scramble_addr)(struct hl_device *hdev, u64 addr); u64 (*descramble_addr)(struct hl_device *hdev, u64 addr); void (*ack_protection_bits_errors)(struct hl_device *hdev); @@ -1447,20 +1618,21 @@ struct hl_asic_funcs { int (*hw_block_mmap)(struct hl_device *hdev, struct vm_area_struct *vma, u32 block_id, u32 block_size); void (*enable_events_from_fw)(struct hl_device *hdev); + int (*ack_mmu_errors)(struct hl_device *hdev, u64 mmu_cap_mask); void (*get_msi_info)(__le32 *table); int (*map_pll_idx_to_fw_idx)(u32 pll_idx); + void (*init_firmware_preload_params)(struct hl_device *hdev); void (*init_firmware_loader)(struct hl_device *hdev); void (*init_cpu_scrambler_dram)(struct hl_device *hdev); void (*state_dump_init)(struct hl_device *hdev); u32 (*get_sob_addr)(struct hl_device *hdev, u32 sob_id); void (*set_pci_memory_regions)(struct hl_device *hdev); u32* (*get_stream_master_qid_arr)(void); - bool (*is_valid_dram_page_size)(u32 page_size); + void (*check_if_razwi_happened)(struct hl_device *hdev); int (*mmu_get_real_page_size)(struct hl_device *hdev, struct hl_mmu_properties *mmu_prop, u32 page_size, u32 *real_page_size, bool is_dram_addr); - void (*get_valid_dram_page_orders)(struct hl_info_dev_memalloc_page_sizes *info); - int (*access_dev_mem)(struct hl_device *hdev, struct pci_mem_region *region, - enum pci_region region_type, u64 addr, u64 *val, enum debugfs_access_type acc_type); + int (*access_dev_mem)(struct hl_device *hdev, enum pci_region region_type, + u64 addr, u64 *val, enum debugfs_access_type acc_type); u64 (*set_dram_bar_base)(struct hl_device *hdev, u64 addr); }; @@ -1535,16 +1707,55 @@ struct hl_dmabuf_priv { uint64_t device_address; }; +#define HL_CS_OUTCOME_HISTORY_LEN 256 + +/** + * struct hl_cs_outcome - represents a single completed CS outcome + * @list_link: link to either container's used list or free list + * @map_link: list to the container hash map + * @ts: completion ts + * @seq: the original cs sequence + * @error: error code cs completed with, if any + */ +struct hl_cs_outcome { + struct list_head list_link; + struct hlist_node map_link; + ktime_t ts; + u64 seq; + int error; +}; + +/** + * struct hl_cs_outcome_store - represents a limited store of completed CS outcomes + * @outcome_map: index of completed CS searcheable by sequence number + * @used_list: list of outcome objects currently in use + * @free_list: list of outcome objects currently not in use + * @nodes_pool: a static pool of preallocated outcome objects + * @db_lock: any operation on the store must take this lock + */ +struct hl_cs_outcome_store { + DECLARE_HASHTABLE(outcome_map, 8); + struct list_head used_list; + struct list_head free_list; + struct hl_cs_outcome nodes_pool[HL_CS_OUTCOME_HISTORY_LEN]; + spinlock_t db_lock; +}; + /** * struct hl_ctx - user/kernel context. * @mem_hash: holds mapping from virtual address to virtual memory area * descriptor (hl_vm_phys_pg_list or hl_userptr). * @mmu_shadow_hash: holds a mapping from shadow address to pgt_info structure. + * @hr_mmu_phys_hash: if host-resident MMU is used, holds a mapping from + * MMU-hop-page physical address to its host-resident + * pgt_info structure. * @hpriv: pointer to the private (Kernel Driver) data of the process (fd). * @hdev: pointer to the device structure. * @refcount: reference counter for the context. Context is released only when * this hits 0l. It is incremented on CS and CS_WAIT. * @cs_pending: array of hl fence objects representing pending CS. + * @outcome_store: storage data structure used to remember ouitcomes of completed + * command submissions for a long time after CS id wraparound. * @va_range: holds available virtual addresses for host and dram mappings. * @mem_hash_lock: protects the mem_hash. * @mmu_lock: protects the MMU page tables. Any change to the PGT, modifying the @@ -1576,10 +1787,12 @@ struct hl_dmabuf_priv { struct hl_ctx { DECLARE_HASHTABLE(mem_hash, MEM_HASH_TABLE_BITS); DECLARE_HASHTABLE(mmu_shadow_hash, MMU_HASH_TABLE_BITS); + DECLARE_HASHTABLE(hr_mmu_phys_hash, MMU_HASH_TABLE_BITS); struct hl_fpriv *hpriv; struct hl_device *hdev; struct kref refcount; struct hl_fence **cs_pending; + struct hl_cs_outcome_store outcome_store; struct hl_va_range *va_range[HL_VA_RANGE_TYPE_MAX]; struct mutex mem_hash_lock; struct mutex mmu_lock; @@ -1601,12 +1814,12 @@ struct hl_ctx { /** * struct hl_ctx_mgr - for handling multiple contexts. - * @ctx_lock: protects ctx_handles. - * @ctx_handles: idr to hold all ctx handles. + * @lock: protects ctx_handles. + * @handles: idr to hold all ctx handles. */ struct hl_ctx_mgr { - struct mutex ctx_lock; - struct idr ctx_handles; + struct mutex lock; + struct idr handles; }; @@ -1665,6 +1878,7 @@ struct hl_userptr { * @timeout_jiffies: cs timeout in jiffies. * @submission_time_jiffies: submission time of the cs * @type: CS_TYPE_*. + * @jobs_cnt: counter of submitted jobs on all queues. * @encaps_sig_hdl_id: encaps signals handle id, set for the first staged cs. * @sob_addr_offset: sob offset from the configuration base address. * @initial_sob_count: count of completed signals in SOB before current submission of signal or @@ -1703,6 +1917,7 @@ struct hl_cs { u64 timeout_jiffies; u64 submission_time_jiffies; enum hl_cs_type type; + u32 jobs_cnt; u32 encaps_sig_hdl_id; u32 sob_addr_offset; u16 initial_sob_count; @@ -1961,6 +2176,8 @@ struct hl_notifier_event { * @dev_node: node in the device list of file private data * @refcount: number of related contexts. * @restore_phase_mutex: lock for context switch and restore phase. + * @ctx_lock: protects the pointer to current executing context pointer. TODO: remove for multiple + * ctx per process. */ struct hl_fpriv { struct hl_device *hdev; @@ -1974,6 +2191,7 @@ struct hl_fpriv { struct list_head dev_node; struct kref refcount; struct mutex restore_phase_mutex; + struct mutex ctx_lock; }; @@ -2027,8 +2245,8 @@ struct hl_debugfs_entry { * @state_dump_sem: protects state_dump. * @addr: next address to read/write from/to in read/write32. * @mmu_addr: next virtual address to translate to physical address in mmu_show. + * @mmu_cap_mask: mmu hw capability mask, to be used in mmu_ack_error. * @userptr_lookup: the target user ptr to look up for on demand. - * @memory_scrub_val: the value to which the dram will be scrubbed to using cb scrub_device_dram * @mmu_asid: ASID to use while translating in mmu_show. * @state_dump_head: index of the latest state dump * @i2c_bus: generic u8 debugfs file for bus value to use in i2c_data_read. @@ -2058,8 +2276,8 @@ struct hl_dbg_device_entry { struct rw_semaphore state_dump_sem; u64 addr; u64 mmu_addr; + u64 mmu_cap_mask; u64 userptr_lookup; - u64 memory_scrub_val; u32 mmu_asid; u32 state_dump_head; u8 i2c_bus; @@ -2255,9 +2473,11 @@ void hl_wreg(struct hl_device *hdev, u32 reg, u32 val); /* Timeout should be longer when working with simulator but cap the * increased timeout to some maximum */ -#define hl_poll_timeout(hdev, addr, val, cond, sleep_us, timeout_us) \ +#define hl_poll_timeout_common(hdev, addr, val, cond, sleep_us, timeout_us, elbi) \ ({ \ ktime_t __timeout; \ + u32 __elbi_read; \ + int __rc = 0; \ if (hdev->pdev) \ __timeout = ktime_add_us(ktime_get(), timeout_us); \ else \ @@ -2266,19 +2486,103 @@ void hl_wreg(struct hl_device *hdev, u32 reg, u32 val); (u64) HL_SIM_MAX_TIMEOUT_US)); \ might_sleep_if(sleep_us); \ for (;;) { \ - (val) = RREG32(addr); \ + if (elbi) { \ + __rc = hl_pci_elbi_read(hdev, addr, &__elbi_read); \ + if (__rc) \ + break; \ + (val) = __elbi_read; \ + } else {\ + (val) = RREG32((u32)addr); \ + } \ if (cond) \ break; \ if (timeout_us && ktime_compare(ktime_get(), __timeout) > 0) { \ - (val) = RREG32(addr); \ + if (elbi) { \ + __rc = hl_pci_elbi_read(hdev, addr, &__elbi_read); \ + if (__rc) \ + break; \ + (val) = __elbi_read; \ + } else {\ + (val) = RREG32((u32)addr); \ + } \ break; \ } \ if (sleep_us) \ usleep_range((sleep_us >> 2) + 1, sleep_us); \ } \ - (cond) ? 0 : -ETIMEDOUT; \ + __rc ? __rc : ((cond) ? 0 : -ETIMEDOUT); \ }) +#define hl_poll_timeout(hdev, addr, val, cond, sleep_us, timeout_us) \ + hl_poll_timeout_common(hdev, addr, val, cond, sleep_us, timeout_us, false) + +#define hl_poll_timeout_elbi(hdev, addr, val, cond, sleep_us, timeout_us) \ + hl_poll_timeout_common(hdev, addr, val, cond, sleep_us, timeout_us, true) + +/* + * poll array of register addresses. + * condition is satisfied if all registers values match the expected value. + * once some register in the array satisfies the condition it will not be polled again, + * this is done both for efficiency and due to some registers are "clear on read". + * TODO: use read from PCI bar in other places in the code (SW-91406) + */ +#define hl_poll_reg_array_timeout_common(hdev, addr_arr, arr_size, expected_val, sleep_us, \ + timeout_us, elbi) \ +({ \ + ktime_t __timeout; \ + u64 __elem_bitmask; \ + u32 __read_val; \ + u8 __arr_idx; \ + int __rc = 0; \ + \ + if (hdev->pdev) \ + __timeout = ktime_add_us(ktime_get(), timeout_us); \ + else \ + __timeout = ktime_add_us(ktime_get(),\ + min(((u64)timeout_us * 10), \ + (u64) HL_SIM_MAX_TIMEOUT_US)); \ + \ + might_sleep_if(sleep_us); \ + if (arr_size >= 64) \ + __rc = -EINVAL; \ + else \ + __elem_bitmask = BIT_ULL(arr_size) - 1; \ + for (;;) { \ + if (__rc) \ + break; \ + for (__arr_idx = 0; __arr_idx < (arr_size); __arr_idx++) { \ + if (!(__elem_bitmask & BIT_ULL(__arr_idx))) \ + continue; \ + if (elbi) { \ + __rc = hl_pci_elbi_read(hdev, (addr_arr)[__arr_idx], &__read_val); \ + if (__rc) \ + break; \ + } else { \ + __read_val = RREG32((u32)(addr_arr)[__arr_idx]); \ + } \ + if (__read_val == (expected_val)) \ + __elem_bitmask &= ~BIT_ULL(__arr_idx); \ + } \ + if (__rc || (__elem_bitmask == 0)) \ + break; \ + if (timeout_us && ktime_compare(ktime_get(), __timeout) > 0) \ + break; \ + if (sleep_us) \ + usleep_range((sleep_us >> 2) + 1, sleep_us); \ + } \ + __rc ? __rc : ((__elem_bitmask == 0) ? 0 : -ETIMEDOUT); \ +}) + +#define hl_poll_reg_array_timeout(hdev, addr_arr, arr_size, expected_val, sleep_us, \ + timeout_us) \ + hl_poll_reg_array_timeout_common(hdev, addr_arr, arr_size, expected_val, sleep_us, \ + timeout_us, false) + +#define hl_poll_reg_array_timeout_elbi(hdev, addr_arr, arr_size, expected_val, sleep_us, \ + timeout_us) \ + hl_poll_reg_array_timeout_common(hdev, addr_arr, arr_size, expected_val, sleep_us, \ + timeout_us, true) + /* * address in this macro points always to a memory location in the * host's (server's) memory. That location is updated asynchronously @@ -2299,7 +2603,7 @@ void hl_wreg(struct hl_device *hdev, u32 reg, u32 val); __timeout = ktime_add_us(ktime_get(), timeout_us); \ else \ __timeout = ktime_add_us(ktime_get(),\ - min((u64)(timeout_us * 10), \ + min((u64)(timeout_us * 100), \ (u64) HL_SIM_MAX_TIMEOUT_US)); \ might_sleep_if(sleep_us); \ for (;;) { \ @@ -2322,29 +2626,21 @@ void hl_wreg(struct hl_device *hdev, u32 reg, u32 val); (cond) ? 0 : -ETIMEDOUT; \ }) -#define hl_poll_timeout_device_memory(hdev, addr, val, cond, sleep_us, \ - timeout_us) \ +#define HL_USR_MAPPED_BLK_INIT(blk, base, sz) \ ({ \ - ktime_t __timeout; \ - if (hdev->pdev) \ - __timeout = ktime_add_us(ktime_get(), timeout_us); \ - else \ - __timeout = ktime_add_us(ktime_get(),\ - min((u64)(timeout_us * 10), \ - (u64) HL_SIM_MAX_TIMEOUT_US)); \ - might_sleep_if(sleep_us); \ - for (;;) { \ - (val) = readl(addr); \ - if (cond) \ - break; \ - if (timeout_us && ktime_compare(ktime_get(), __timeout) > 0) { \ - (val) = readl(addr); \ - break; \ - } \ - if (sleep_us) \ - usleep_range((sleep_us >> 2) + 1, sleep_us); \ - } \ - (cond) ? 0 : -ETIMEDOUT; \ + struct user_mapped_block *p = blk; \ +\ + p->address = base; \ + p->size = sz; \ +}) + +#define HL_USR_INTR_STRUCT_INIT(usr_intr, hdev, intr_id, decoder) \ +({ \ + usr_intr.hdev = hdev; \ + usr_intr.interrupt_id = intr_id; \ + usr_intr.is_decoder = decoder; \ + INIT_LIST_HEAD(&usr_intr.wait_list_head); \ + spin_lock_init(&usr_intr.wait_list_lock); \ }) struct hwmon_chip_info; @@ -2363,28 +2659,16 @@ struct hl_device_reset_work { u32 flags; }; -/** - * struct hr_mmu_hop_addrs - used for holding per-device host-resident mmu hop - * information. - * @virt_addr: the virtual address of the hop. - * @phys-addr: the physical address of the hop (used by the device-mmu). - * @shadow_addr: The shadow of the hop used by the driver for walking the hops. - */ -struct hr_mmu_hop_addrs { - u64 virt_addr; - u64 phys_addr; - u64 shadow_addr; -}; - /** * struct hl_mmu_hr_pgt_priv - used for holding per-device mmu host-resident * page-table internal information. - * @mmu_pgt_pool: pool of page tables used by MMU for allocating hops. - * @mmu_shadow_hop0: shadow array of hop0 tables. + * @mmu_pgt_pool: pool of page tables used by a host-resident MMU for + * allocating hops. + * @mmu_asid_hop0: per-ASID array of host-resident hop0 tables. */ struct hl_mmu_hr_priv { - struct gen_pool *mmu_pgt_pool; - struct hr_mmu_hop_addrs *mmu_shadow_hop0; + struct gen_pool *mmu_pgt_pool; + struct pgt_info *mmu_asid_hop0; }; /** @@ -2437,11 +2721,27 @@ struct hl_mmu_per_hop_info { struct hl_mmu_hop_info { u64 scrambled_vaddr; u64 unscrambled_paddr; - struct hl_mmu_per_hop_info hop_info[MMU_ARCH_5_HOPS]; + struct hl_mmu_per_hop_info hop_info[MMU_ARCH_6_HOPS]; u32 used_hops; enum hl_va_range_type range_type; }; +/** + * struct hl_hr_mmu_funcs - Device related host resident MMU functions. + * @get_hop0_pgt_info: get page table info structure for HOP0. + * @get_pgt_info: get page table info structure for HOP other than HOP0. + * @add_pgt_info: add page table info structure to hash. + * @get_tlb_mapping_params: get mapping parameters needed for getting TLB info for specific mapping. + */ +struct hl_hr_mmu_funcs { + struct pgt_info *(*get_hop0_pgt_info)(struct hl_ctx *ctx); + struct pgt_info *(*get_pgt_info)(struct hl_ctx *ctx, u64 phys_hop_addr); + void (*add_pgt_info)(struct hl_ctx *ctx, struct pgt_info *pgt_info, dma_addr_t phys_addr); + int (*get_tlb_mapping_params)(struct hl_device *hdev, struct hl_mmu_properties **mmu_prop, + struct hl_mmu_hop_info *hops, + u64 virt_addr, bool *is_huge); +}; + /** * struct hl_mmu_funcs - Device related MMU functions. * @init: initialize the MMU module. @@ -2456,22 +2756,21 @@ struct hl_mmu_hop_info { * @get_tlb_info: returns the list of hops and hop-entries used that were * created in order to translate the giver virtual address to a * physical one. + * @hr_funcs: functions specific to host resident MMU. */ struct hl_mmu_funcs { int (*init)(struct hl_device *hdev); void (*fini)(struct hl_device *hdev); int (*ctx_init)(struct hl_ctx *ctx); void (*ctx_fini)(struct hl_ctx *ctx); - int (*map)(struct hl_ctx *ctx, - u64 virt_addr, u64 phys_addr, u32 page_size, - bool is_dram_addr); - int (*unmap)(struct hl_ctx *ctx, - u64 virt_addr, bool is_dram_addr); + int (*map)(struct hl_ctx *ctx, u64 virt_addr, u64 phys_addr, u32 page_size, + bool is_dram_addr); + int (*unmap)(struct hl_ctx *ctx, u64 virt_addr, bool is_dram_addr); void (*flush)(struct hl_ctx *ctx); void (*swap_out)(struct hl_ctx *ctx); void (*swap_in)(struct hl_ctx *ctx); - int (*get_tlb_info)(struct hl_ctx *ctx, - u64 virt_addr, struct hl_mmu_hop_info *hops); + int (*get_tlb_info)(struct hl_ctx *ctx, u64 virt_addr, struct hl_mmu_hop_info *hops); + struct hl_hr_mmu_funcs hr_funcs; }; /** @@ -2567,24 +2866,34 @@ struct hl_clk_throttle { u32 aggregated_reason; }; +/** + * struct user_mapped_block - describes a hw block allowed to be mmapped by user + * @address: physical HW block address + * @size: allowed size for mmap + */ +struct user_mapped_block { + u32 address; + u32 size; +}; + /** * struct cs_timeout_info - info of last CS timeout occurred. * @timestamp: CS timeout timestamp. - * @write_disable: if set writing to CS parameters in the structure is disabled so, - * the first (root cause) CS timeout will not be overwritten. + * @write_enable: if set writing to CS parameters in the structure is enabled. otherwise - disabled, + * so the first (root cause) CS timeout will not be overwritten. * @seq: CS timeout sequence number. */ struct cs_timeout_info { ktime_t timestamp; - atomic_t write_disable; + atomic_t write_enable; u64 seq; }; /** * struct razwi_info - info about last razwi error occurred. * @timestamp: razwi timestamp. - * @write_disable: if set writing to razwi parameters in the structure is disabled so the - * first (root cause) razwi will not be overwritten. + * @write_enable: if set writing to razwi parameters in the structure is enabled. + * otherwise - disabled, so the first (root cause) razwi will not be overwritten. * @addr: address that caused razwi. * @engine_id_1: engine id of the razwi initiator, if it was initiated by engine that does * not have engine id it will be set to U16_MAX. @@ -2596,7 +2905,7 @@ struct cs_timeout_info { */ struct razwi_info { ktime_t timestamp; - atomic_t write_disable; + atomic_t write_enable; u64 addr; u16 engine_id_1; u16 engine_id_2; @@ -2604,25 +2913,59 @@ struct razwi_info { u8 type; }; +#define MAX_QMAN_STREAMS_INFO 4 +#define OPCODE_INFO_MAX_ADDR_SIZE 8 +/** + * struct undefined_opcode_info - info about last undefined opcode error + * @timestamp: timestamp of the undefined opcode error + * @cb_addr_streams: CB addresses (per stream) that are currently exists in the PQ + * entiers. In case all streams array entries are + * filled with values, it means the execution was in Lower-CP. + * @cq_addr: the address of the current handled command buffer + * @cq_size: the size of the current handled command buffer + * @cb_addr_streams_len: num of streams - actual len of cb_addr_streams array. + * should be equal to 1 incase of undefined opcode + * in Upper-CP (specific stream) and equal to 4 incase + * of undefined opcode in Lower-CP. + * @engine_id: engine-id that the error occurred on + * @stream_id: the stream id the error occurred on. In case the stream equals to + * MAX_QMAN_STREAMS_INFO it means the error occurred on a Lower-CP. + * @write_enable: if set, writing to undefined opcode parameters in the structure + * is enable so the first (root cause) undefined opcode will not be + * overwritten. + */ +struct undefined_opcode_info { + ktime_t timestamp; + u64 cb_addr_streams[MAX_QMAN_STREAMS_INFO][OPCODE_INFO_MAX_ADDR_SIZE]; + u64 cq_addr; + u32 cq_size; + u32 cb_addr_streams_len; + u32 engine_id; + u32 stream_id; + bool write_enable; +}; + /** * struct last_error_session_info - info about last session errors occurred. * @cs_timeout: CS timeout error last information. * @razwi: razwi last information. + * @undef_opcode: undefined opcode information */ struct last_error_session_info { - struct cs_timeout_info cs_timeout; - struct razwi_info razwi; + struct cs_timeout_info cs_timeout; + struct razwi_info razwi; + struct undefined_opcode_info undef_opcode; }; /** * struct hl_reset_info - holds current device reset information. * @lock: lock to protect critical reset flows. - * @soft_reset_cnt: number of soft reset since the driver was loaded. - * @hard_reset_cnt: number of hard reset since the driver was loaded. - * @hard_reset_schedule_flags: hard reset is scheduled to after current soft reset, + * @compute_reset_cnt: number of compte resets since the driver was loaded. + * @hard_reset_cnt: number of hard resets since the driver was loaded. + * @hard_reset_schedule_flags: hard reset is scheduled to after current compute reset, * here we hold the hard reset flags. * @in_reset: is device in reset flow. - * @is_in_soft_reset: Device is currently in soft reset process. + * @in_compute_reset: Device is currently in reset but not in hard-reset. * @needs_reset: true if reset_on_lockup is false and device should be reset * due to lockup. * @hard_reset_pending: is there a hard reset work pending. @@ -2637,11 +2980,11 @@ struct last_error_session_info { */ struct hl_reset_info { spinlock_t lock; - u32 soft_reset_cnt; + u32 compute_reset_cnt; u32 hard_reset_cnt; u32 hard_reset_schedule_flags; u8 in_reset; - u8 is_in_soft_reset; + u8 in_compute_reset; u8 needs_reset; u8 hard_reset_pending; @@ -2671,12 +3014,17 @@ struct hl_reset_info { * @user_interrupt: array of hl_user_interrupt. upon the corresponding user * interrupt, driver will monitor the list of fences * registered to this interrupt. - * @common_user_interrupt: common user interrupt for all user interrupts. - * upon any user interrupt, driver will monitor the + * @common_user_cq_interrupt: common user CQ interrupt for all user CQ interrupts. + * upon any user CQ interrupt, driver will monitor the * list of fences registered to this common structure. + * @common_decoder_interrupt: common decoder interrupt for all user decoder interrupts. + * @shadow_cs_queue: pointer to a shadow queue that holds pointers to + * outstanding command submissions. * @cq_wq: work queues of completion queues for executing work in process * context. * @eq_wq: work queue of event queue for executing work in process context. + * @cs_cmplt_wq: work queue of CS completions for executing work in process + * context. * @ts_free_obj_wq: work queue for timestamp registration objects release. * @pf_wq: work queue for MMU pre-fetch operations. * @kernel_ctx: Kernel driver context structure. @@ -2716,6 +3064,7 @@ struct hl_reset_info { * @aggregated_cs_counters: aggregated cs counters among all contexts * @mmu_priv: device-specific MMU data. * @mmu_func: device-related MMU functions. + * @dec: list of decoder sw instance * @fw_loader: FW loader manager. * @pci_mem_region: array of memory regions in the PCI * @state_dump_specs: constants and dictionaries needed to dump system state. @@ -2724,8 +3073,10 @@ struct hl_reset_info { * @last_error: holds information about last session in which CS timeout or razwi error occurred. * @reset_info: holds current device reset information. * @stream_master_qid_arr: pointer to array with QIDs of master streams. - * @fw_major_version: major version of current loaded preboot + * @fw_major_version: major version of current loaded preboot. + * @fw_minor_version: minor version of current loaded preboot. * @dram_used_mem: current DRAM memory consumption. + * @memory_scrub_val: the value to which the dram will be scrubbed to using cb scrub_device_dram * @timeout_jiffies: device CS timeout value. * @max_power: the max power of the device, as configured by the sysadmin. This * value is saved so in case of hard-reset, the driver will restore @@ -2747,10 +3098,18 @@ struct hl_reset_info { * used for CPU boot status * @fw_comms_poll_interval_usec: FW comms/protocol poll interval in usec. * used for COMMs protocols cmds(COMMS_STS_*) + * @dram_binning: contains mask of drams that is received from the f/w which indicates which + * drams are binned-out + * @tpc_binning: contains mask of tpc engines that is received from the f/w which indicates which + * tpc engines are binned-out * @card_type: Various ASICs have several card types. This indicates the card * type of the current device. * @major: habanalabs kernel driver major. * @high_pll: high PLL profile frequency. + * @decoder_binning: contains mask of decoder engines that is received from the f/w which + * indicates which decoder engines are binned-out + * @edma_binning: contains mask of edma engines that is received from the f/w which + * indicates which edma engines are binned-out * @id: device minor. * @id_control: minor of the control device * @cpu_pci_msb_addr: 50-bit extension bits for the device CPU's 40-bit @@ -2759,7 +3118,6 @@ struct hl_reset_info { * @disabled: is device disabled. * @late_init_done: is late init stage was done during initialization. * @hwmon_initialized: is H/W monitor sensors was initialized. - * @heartbeat: is heartbeat sanity check towards CPU-CP enabled. * @reset_on_lockup: true if a reset should be done in case of stuck CS, false * otherwise. * @dram_default_page_mapping: is DRAM default page mapping enabled. @@ -2792,6 +3150,21 @@ struct hl_reset_info { * @is_compute_ctx_active: Whether there is an active compute context executing. * @compute_ctx_in_release: true if the current compute context is being released. * @supports_mmu_prefetch: true if prefetch is supported, otherwise false. + * @reset_upon_device_release: reset the device when the user closes the file descriptor of the + * device. + * @nic_ports_mask: Controls which NIC ports are enabled. Used only for testing. + * @fw_components: Controls which f/w components to load to the device. There are multiple f/w + * stages and sometimes we want to stop at a certain stage. Used only for testing. + * @mmu_enable: Whether to enable or disable the device MMU(s). Used only for testing. + * @cpu_queues_enable: Whether to enable queues communication vs. the f/w. Used only for testing. + * @pldm: Whether we are running in Palladium environment. Used only for testing. + * @hard_reset_on_fw_events: Whether to do device hard-reset when a fatal event is received from + * the f/w. Used only for testing. + * @bmc_enable: Whether we are running in a box with BMC. Used only for testing. + * @reset_on_preboot_fail: Whether to reset the device if preboot f/w fails to load. + * Used only for testing. + * @heartbeat: Controls if we want to enable the heartbeat mechanism vs. the f/w, which verifies + * that the f/w is always alive. Used only for testing. */ struct hl_device { struct pci_dev *pdev; @@ -2809,9 +3182,12 @@ struct hl_device { enum hl_asic_type asic_type; struct hl_cq *completion_queue; struct hl_user_interrupt *user_interrupt; - struct hl_user_interrupt common_user_interrupt; + struct hl_user_interrupt common_user_cq_interrupt; + struct hl_user_interrupt common_decoder_interrupt; + struct hl_cs **shadow_cs_queue; struct workqueue_struct **cq_wq; struct workqueue_struct *eq_wq; + struct workqueue_struct *cs_cmplt_wq; struct workqueue_struct *ts_free_obj_wq; struct workqueue_struct *pf_wq; struct hl_ctx *kernel_ctx; @@ -2855,6 +3231,8 @@ struct hl_device { struct hl_mmu_priv mmu_priv; struct hl_mmu_funcs mmu_func[MMU_NUM_PGT_LOCATIONS]; + struct hl_dec *dec; + struct fw_load_mgr fw_loader; struct pci_mem_region pci_mem_region[PCI_REGION_NUMBER]; @@ -2870,7 +3248,9 @@ struct hl_device { u32 *stream_master_qid_arr; u32 fw_major_version; + u32 fw_minor_version; atomic64_t dram_used_mem; + u64 memory_scrub_val; u64 timeout_jiffies; u64 max_power; u64 boot_error_status_mask; @@ -2881,10 +3261,14 @@ struct hl_device { u64 fw_poll_interval_usec; ktime_t last_successful_open_ktime; u64 fw_comms_poll_interval_usec; + u64 dram_binning; + u64 tpc_binning; enum cpucp_card_types card_type; u32 major; u32 high_pll; + u32 decoder_binning; + u32 edma_binning; u16 id; u16 id_control; u16 cpu_pci_msb_addr; @@ -2892,7 +3276,6 @@ struct hl_device { u8 disabled; u8 late_init_done; u8 hwmon_initialized; - u8 heartbeat; u8 reset_on_lockup; u8 dram_default_page_mapping; u8 memory_scrub; @@ -2916,24 +3299,18 @@ struct hl_device { u8 is_compute_ctx_active; u8 compute_ctx_in_release; u8 supports_mmu_prefetch; + u8 reset_upon_device_release; /* Parameters for bring-up */ u64 nic_ports_mask; u64 fw_components; u8 mmu_enable; - u8 mmu_huge_page_opt; - u8 reset_pcilink; u8 cpu_queues_enable; u8 pldm; - u8 axi_drain; - u8 sram_scrambler_enable; - u8 dram_scrambler_enable; u8 hard_reset_on_fw_events; u8 bmc_enable; - u8 rl_enable; u8 reset_on_preboot_fail; - u8 reset_upon_device_release; - u8 reset_if_device_not_idle; + u8 heartbeat; }; @@ -3049,13 +3426,22 @@ static inline bool hl_mem_area_crosses_range(u64 address, u32 size, } uint64_t hl_set_dram_bar_default(struct hl_device *hdev, u64 addr); +void *hl_asic_dma_alloc_coherent(struct hl_device *hdev, size_t size, dma_addr_t *dma_handle, + gfp_t flag); +void hl_asic_dma_free_coherent(struct hl_device *hdev, size_t size, void *cpu_addr, + dma_addr_t dma_handle); +void *hl_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size, dma_addr_t *dma_handle); +void hl_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size, void *vaddr); +void *hl_asic_dma_pool_zalloc(struct hl_device *hdev, size_t size, gfp_t mem_flags, + dma_addr_t *dma_handle); +void hl_asic_dma_pool_free(struct hl_device *hdev, void *vaddr, dma_addr_t dma_addr); int hl_dma_map_sgtable(struct hl_device *hdev, struct sg_table *sgt, enum dma_data_direction dir); void hl_dma_unmap_sgtable(struct hl_device *hdev, struct sg_table *sgt, enum dma_data_direction dir); int hl_access_cfg_region(struct hl_device *hdev, u64 addr, u64 *val, enum debugfs_access_type acc_type); -int hl_access_dev_mem(struct hl_device *hdev, struct pci_mem_region *region, - enum pci_region region_type, u64 addr, u64 *val, enum debugfs_access_type acc_type); +int hl_access_dev_mem(struct hl_device *hdev, enum pci_region region_type, + u64 addr, u64 *val, enum debugfs_access_type acc_type); int hl_device_open(struct inode *inode, struct file *filp); int hl_device_open_ctrl(struct inode *inode, struct file *filp); bool hl_device_operational(struct hl_device *hdev, @@ -3085,7 +3471,8 @@ void hl_cq_reset(struct hl_device *hdev, struct hl_cq *q); void hl_eq_reset(struct hl_device *hdev, struct hl_eq *q); irqreturn_t hl_irq_handler_cq(int irq, void *arg); irqreturn_t hl_irq_handler_eq(int irq, void *arg); -irqreturn_t hl_irq_handler_user_cq(int irq, void *arg); +irqreturn_t hl_irq_handler_dec_abnrm(int irq, void *arg); +irqreturn_t hl_irq_handler_user_interrupt(int irq, void *arg); irqreturn_t hl_irq_handler_default(int irq, void *arg); u32 hl_cq_inc_ptr(u32 ptr); @@ -3119,7 +3506,7 @@ int hl_device_utilization(struct hl_device *hdev, u32 *utilization); int hl_build_hwmon_channel_info(struct hl_device *hdev, struct cpucp_sensor *sensors_arr); -void hl_notifier_event_send_all(struct hl_device *hdev, u64 event); +void hl_notifier_event_send_all(struct hl_device *hdev, u64 event_mask); int hl_sysfs_init(struct hl_device *hdev); void hl_sysfs_fini(struct hl_device *hdev); @@ -3158,6 +3545,7 @@ void hl_multi_cs_completion_init(struct hl_device *hdev); void goya_set_asic_funcs(struct hl_device *hdev); void gaudi_set_asic_funcs(struct hl_device *hdev); +void gaudi2_set_asic_funcs(struct hl_device *hdev); int hl_vm_ctx_init(struct hl_ctx *ctx); void hl_vm_ctx_fini(struct hl_ctx *ctx); @@ -3201,10 +3589,39 @@ int hl_mmu_prefetch_cache_range(struct hl_ctx *ctx, u32 flags, u32 asid, u64 va, u64 hl_mmu_get_next_hop_addr(struct hl_ctx *ctx, u64 curr_pte); u64 hl_mmu_get_hop_pte_phys_addr(struct hl_ctx *ctx, struct hl_mmu_properties *mmu_prop, u8 hop_idx, u64 hop_addr, u64 virt_addr); +void hl_mmu_hr_flush(struct hl_ctx *ctx); +int hl_mmu_hr_init(struct hl_device *hdev, struct hl_mmu_hr_priv *hr_priv, u32 hop_table_size, + u64 pgt_size); +void hl_mmu_hr_fini(struct hl_device *hdev, struct hl_mmu_hr_priv *hr_priv, u32 hop_table_size); +void hl_mmu_hr_free_hop_remove_pgt(struct pgt_info *pgt_info, struct hl_mmu_hr_priv *hr_priv, + u32 hop_table_size); +u64 hl_mmu_hr_pte_phys_to_virt(struct hl_ctx *ctx, struct pgt_info *pgt, u64 phys_pte_addr, + u32 hop_table_size); +void hl_mmu_hr_write_pte(struct hl_ctx *ctx, struct pgt_info *pgt_info, u64 phys_pte_addr, + u64 val, u32 hop_table_size); +void hl_mmu_hr_clear_pte(struct hl_ctx *ctx, struct pgt_info *pgt_info, u64 phys_pte_addr, + u32 hop_table_size); +int hl_mmu_hr_put_pte(struct hl_ctx *ctx, struct pgt_info *pgt_info, struct hl_mmu_hr_priv *hr_priv, + u32 hop_table_size); +void hl_mmu_hr_get_pte(struct hl_ctx *ctx, struct hl_hr_mmu_funcs *hr_func, u64 phys_hop_addr); +struct pgt_info *hl_mmu_hr_get_next_hop_pgt_info(struct hl_ctx *ctx, + struct hl_hr_mmu_funcs *hr_func, + u64 curr_pte); +struct pgt_info *hl_mmu_hr_alloc_hop(struct hl_ctx *ctx, struct hl_mmu_hr_priv *hr_priv, + struct hl_hr_mmu_funcs *hr_func, + struct hl_mmu_properties *mmu_prop); +struct pgt_info *hl_mmu_hr_get_alloc_next_hop(struct hl_ctx *ctx, + struct hl_mmu_hr_priv *hr_priv, + struct hl_hr_mmu_funcs *hr_func, + struct hl_mmu_properties *mmu_prop, + u64 curr_pte, bool *is_new_hop); +int hl_mmu_hr_get_tlb_info(struct hl_ctx *ctx, u64 virt_addr, struct hl_mmu_hop_info *hops, + struct hl_hr_mmu_funcs *hr_func); void hl_mmu_swap_out(struct hl_ctx *ctx); void hl_mmu_swap_in(struct hl_ctx *ctx); int hl_mmu_if_set_funcs(struct hl_device *hdev); void hl_mmu_v1_set_funcs(struct hl_device *hdev, struct hl_mmu_funcs *mmu); +void hl_mmu_v2_hr_set_funcs(struct hl_device *hdev, struct hl_mmu_funcs *mmu); int hl_mmu_va_to_pa(struct hl_ctx *ctx, u64 virt_addr, u64 *phys_addr); int hl_mmu_get_tlb_info(struct hl_ctx *ctx, u64 virt_addr, struct hl_mmu_hop_info *hops); @@ -3214,7 +3631,7 @@ bool hl_is_dram_va(struct hl_device *hdev, u64 virt_addr); int hl_fw_load_fw_to_device(struct hl_device *hdev, const char *fw_name, void __iomem *dst, u32 src_offset, u32 size); -int hl_fw_send_pci_access_msg(struct hl_device *hdev, u32 opcode); +int hl_fw_send_pci_access_msg(struct hl_device *hdev, u32 opcode, u64 value); int hl_fw_send_cpu_message(struct hl_device *hdev, u32 hw_queue_id, u32 *msg, u16 len, u32 timeout, u64 *result); int hl_fw_unmask_irq(struct hl_device *hdev, u16 event_type); @@ -3248,10 +3665,7 @@ int hl_fw_cpucp_power_get(struct hl_device *hdev, u64 *power); void hl_fw_ask_hard_reset_without_linux(struct hl_device *hdev); void hl_fw_ask_halt_machine_without_linux(struct hl_device *hdev); int hl_fw_init_cpu(struct hl_device *hdev); -int hl_fw_read_preboot_status(struct hl_device *hdev, u32 cpu_boot_status_reg, - u32 sts_boot_dev_sts0_reg, - u32 sts_boot_dev_sts1_reg, u32 boot_err0_reg, - u32 boot_err1_reg, u32 timeout); +int hl_fw_read_preboot_status(struct hl_device *hdev); int hl_fw_dynamic_send_protocol_cmd(struct hl_device *hdev, struct fw_load_mgr *fw_loader, enum comms_cmd cmd, unsigned int size, @@ -3298,6 +3712,11 @@ void hl_encaps_handle_do_release(struct kref *ref); void hl_hw_queue_encaps_sig_set_sob_info(struct hl_device *hdev, struct hl_cs *cs, struct hl_cs_job *job, struct hl_cs_compl *cs_cmpl); + +int hl_dec_init(struct hl_device *hdev); +void hl_dec_fini(struct hl_device *hdev); +void hl_dec_ctx_fini(struct hl_ctx *ctx); + void hl_release_pending_user_interrupts(struct hl_device *hdev); int hl_cs_signal_sob_wraparound_handler(struct hl_device *hdev, u32 q_idx, struct hl_hw_sob **hw_sob, u32 count, bool encaps_sig); @@ -3426,6 +3845,55 @@ static inline void hl_debugfs_set_state_dump(struct hl_device *hdev, #endif +/* Security */ +int hl_unsecure_register(struct hl_device *hdev, u32 mm_reg_addr, int offset, + const u32 pb_blocks[], struct hl_block_glbl_sec sgs_array[], + int array_size); +int hl_unsecure_registers(struct hl_device *hdev, const u32 mm_reg_array[], + int mm_array_size, int offset, const u32 pb_blocks[], + struct hl_block_glbl_sec sgs_array[], int blocks_array_size); +void hl_config_glbl_sec(struct hl_device *hdev, const u32 pb_blocks[], + struct hl_block_glbl_sec sgs_array[], u32 block_offset, + int array_size); +void hl_secure_block(struct hl_device *hdev, + struct hl_block_glbl_sec sgs_array[], int array_size); +int hl_init_pb_with_mask(struct hl_device *hdev, u32 num_dcores, + u32 dcore_offset, u32 num_instances, u32 instance_offset, + const u32 pb_blocks[], u32 blocks_array_size, + const u32 *regs_array, u32 regs_array_size, u64 mask); +int hl_init_pb(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset, + u32 num_instances, u32 instance_offset, + const u32 pb_blocks[], u32 blocks_array_size, + const u32 *regs_array, u32 regs_array_size); +int hl_init_pb_ranges_with_mask(struct hl_device *hdev, u32 num_dcores, + u32 dcore_offset, u32 num_instances, u32 instance_offset, + const u32 pb_blocks[], u32 blocks_array_size, + const struct range *regs_range_array, u32 regs_range_array_size, + u64 mask); +int hl_init_pb_ranges(struct hl_device *hdev, u32 num_dcores, + u32 dcore_offset, u32 num_instances, u32 instance_offset, + const u32 pb_blocks[], u32 blocks_array_size, + const struct range *regs_range_array, + u32 regs_range_array_size); +int hl_init_pb_single_dcore(struct hl_device *hdev, u32 dcore_offset, + u32 num_instances, u32 instance_offset, + const u32 pb_blocks[], u32 blocks_array_size, + const u32 *regs_array, u32 regs_array_size); +int hl_init_pb_ranges_single_dcore(struct hl_device *hdev, u32 dcore_offset, + u32 num_instances, u32 instance_offset, + const u32 pb_blocks[], u32 blocks_array_size, + const struct range *regs_range_array, + u32 regs_range_array_size); +void hl_ack_pb(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset, + u32 num_instances, u32 instance_offset, + const u32 pb_blocks[], u32 blocks_array_size); +void hl_ack_pb_with_mask(struct hl_device *hdev, u32 num_dcores, + u32 dcore_offset, u32 num_instances, u32 instance_offset, + const u32 pb_blocks[], u32 blocks_array_size, u64 mask); +void hl_ack_pb_single_dcore(struct hl_device *hdev, u32 dcore_offset, + u32 num_instances, u32 instance_offset, + const u32 pb_blocks[], u32 blocks_array_size); + /* IOCTLs */ long hl_ioctl(struct file *filep, unsigned int cmd, unsigned long arg); long hl_ioctl_control(struct file *filep, unsigned int cmd, unsigned long arg); diff --git a/drivers/misc/habanalabs/common/habanalabs_drv.c b/drivers/misc/habanalabs/common/habanalabs_drv.c index 37edb69a7255..f733ead605e7 100644 --- a/drivers/misc/habanalabs/common/habanalabs_drv.c +++ b/drivers/misc/habanalabs/common/habanalabs_drv.c @@ -54,10 +54,15 @@ MODULE_PARM_DESC(boot_error_status_mask, #define PCI_IDS_GAUDI 0x1000 #define PCI_IDS_GAUDI_SEC 0x1010 +#define PCI_IDS_GAUDI2 0x1020 +#define PCI_IDS_GAUDI2_SEC 0x1030 + static const struct pci_device_id ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_HABANALABS, PCI_IDS_GOYA), }, { PCI_DEVICE(PCI_VENDOR_ID_HABANALABS, PCI_IDS_GAUDI), }, { PCI_DEVICE(PCI_VENDOR_ID_HABANALABS, PCI_IDS_GAUDI_SEC), }, + { PCI_DEVICE(PCI_VENDOR_ID_HABANALABS, PCI_IDS_GAUDI2), }, + { PCI_DEVICE(PCI_VENDOR_ID_HABANALABS, PCI_IDS_GAUDI2_SEC), }, { 0, } }; MODULE_DEVICE_TABLE(pci, ids); @@ -84,6 +89,12 @@ static enum hl_asic_type get_asic_type(u16 device) case PCI_IDS_GAUDI_SEC: asic_type = ASIC_GAUDI_SEC; break; + case PCI_IDS_GAUDI2: + asic_type = ASIC_GAUDI2; + break; + case PCI_IDS_GAUDI2_SEC: + asic_type = ASIC_GAUDI2_SEC; + break; default: asic_type = ASIC_INVALID; break; @@ -96,6 +107,7 @@ static bool is_asic_secured(enum hl_asic_type asic_type) { switch (asic_type) { case ASIC_GAUDI_SEC: + case ASIC_GAUDI2_SEC: return true; default: return false; @@ -137,6 +149,7 @@ int hl_device_open(struct inode *inode, struct file *filp) mutex_init(&hpriv->notifier_event.lock); mutex_init(&hpriv->restore_phase_mutex); + mutex_init(&hpriv->ctx_lock); kref_init(&hpriv->refcount); nonseekable_open(inode, filp); @@ -152,7 +165,8 @@ int hl_device_open(struct inode *inode, struct file *filp) "Can't open %s because it is %s\n", dev_name(hdev->dev), hdev->status[status]); - if (status == HL_DEVICE_STATUS_IN_RESET) + if (status == HL_DEVICE_STATUS_IN_RESET || + status == HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE) rc = -EAGAIN; else rc = -EPERM; @@ -195,8 +209,9 @@ int hl_device_open(struct inode *inode, struct file *filp) hl_debugfs_add_file(hpriv); - atomic_set(&hdev->last_error.cs_timeout.write_disable, 0); - atomic_set(&hdev->last_error.razwi.write_disable, 0); + atomic_set(&hdev->last_error.cs_timeout.write_enable, 1); + atomic_set(&hdev->last_error.razwi.write_enable, 1); + hdev->last_error.undef_opcode.write_enable = true; hdev->open_counter++; hdev->last_successful_open_jif = jiffies; @@ -209,6 +224,7 @@ out_err: hl_mem_mgr_fini(&hpriv->mem_mgr); hl_ctx_mgr_fini(hpriv->hdev, &hpriv->ctx_mgr); filp->private_data = NULL; + mutex_destroy(&hpriv->ctx_lock); mutex_destroy(&hpriv->restore_phase_mutex); mutex_destroy(&hpriv->notifier_event.lock); put_pid(hpriv->taskpid); @@ -277,43 +293,56 @@ out_err: static void set_driver_behavior_per_device(struct hl_device *hdev) { - hdev->pldm = 0; + hdev->nic_ports_mask = 0; hdev->fw_components = FW_TYPE_ALL_TYPES; + hdev->mmu_enable = MMU_EN_ALL; hdev->cpu_queues_enable = 1; - hdev->heartbeat = 1; - hdev->mmu_enable = 1; - hdev->sram_scrambler_enable = 1; - hdev->dram_scrambler_enable = 1; - hdev->bmc_enable = 1; + hdev->pldm = 0; hdev->hard_reset_on_fw_events = 1; + hdev->bmc_enable = 1; hdev->reset_on_preboot_fail = 1; - hdev->reset_if_device_not_idle = 1; - - hdev->reset_pcilink = 0; - hdev->axi_drain = 0; + hdev->heartbeat = 1; } static void copy_kernel_module_params_to_device(struct hl_device *hdev) { + hdev->asic_prop.fw_security_enabled = is_asic_secured(hdev->asic_type); + hdev->major = hl_major; hdev->memory_scrub = memory_scrub; hdev->reset_on_lockup = reset_on_lockup; hdev->boot_error_status_mask = boot_error_status_mask; +} - if (timeout_locked) - hdev->timeout_jiffies = msecs_to_jiffies(timeout_locked * 1000); - else - hdev->timeout_jiffies = MAX_SCHEDULE_TIMEOUT; +static void fixup_device_params_per_asic(struct hl_device *hdev) +{ + switch (hdev->asic_type) { + case ASIC_GOYA: + case ASIC_GAUDI: + case ASIC_GAUDI_SEC: + hdev->reset_upon_device_release = 0; + break; + default: + hdev->reset_upon_device_release = 1; + break; + } } static int fixup_device_params(struct hl_device *hdev) { - hdev->asic_prop.fw_security_enabled = is_asic_secured(hdev->asic_type); + int tmp_timeout; + + tmp_timeout = timeout_locked; hdev->fw_poll_interval_usec = HL_FW_STATUS_POLL_INTERVAL_USEC; hdev->fw_comms_poll_interval_usec = HL_FW_STATUS_POLL_INTERVAL_USEC; + if (tmp_timeout) + hdev->timeout_jiffies = msecs_to_jiffies(tmp_timeout * 1000); + else + hdev->timeout_jiffies = MAX_SCHEDULE_TIMEOUT; + hdev->stop_on_err = true; hdev->reset_info.curr_reset_cause = HL_RESET_CAUSE_UNKNOWN; hdev->reset_info.prev_reset_trigger = HL_RESET_TRIGGER_DEFAULT; @@ -321,6 +350,18 @@ static int fixup_device_params(struct hl_device *hdev) /* Enable only after the initialization of the device */ hdev->disabled = true; + if (!(hdev->fw_components & FW_TYPE_PREBOOT_CPU) && + (hdev->fw_components & ~FW_TYPE_PREBOOT_CPU)) { + pr_err("Preboot must be set along with other components"); + return -EINVAL; + } + + /* If CPU queues not enabled, no way to do heartbeat */ + if (!hdev->cpu_queues_enable) + hdev->heartbeat = 0; + + fixup_device_params_per_asic(hdev); + return 0; } @@ -345,7 +386,7 @@ static int create_hdev(struct hl_device **dev, struct pci_dev *pdev) if (!hdev) return -ENOMEM; - /* can be NULL in case of simulator device */ + /* Will be NULL in case of simulator device */ hdev->pdev = pdev; /* Assign status description string */ @@ -355,6 +396,9 @@ static int create_hdev(struct hl_device **dev, struct pci_dev *pdev) strncpy(hdev->status[HL_DEVICE_STATUS_NEEDS_RESET], "needs reset", HL_STR_MAX); strncpy(hdev->status[HL_DEVICE_STATUS_IN_DEVICE_CREATION], "in device creation", HL_STR_MAX); + strncpy(hdev->status[HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE], + "in reset after device release", HL_STR_MAX); + /* First, we must find out which ASIC are we handling. This is needed * to configure the behavior of the driver (kernel parameters) diff --git a/drivers/misc/habanalabs/common/habanalabs_ioctl.c b/drivers/misc/habanalabs/common/habanalabs_ioctl.c index c7864d6bb0a1..6a30bd98ab5e 100644 --- a/drivers/misc/habanalabs/common/habanalabs_ioctl.c +++ b/drivers/misc/habanalabs/common/habanalabs_ioctl.c @@ -47,7 +47,7 @@ static int hw_ip_info(struct hl_device *hdev, struct hl_info_args *args) u32 size = args->return_size; void __user *out = (void __user *) (uintptr_t) args->return_pointer; struct asic_fixed_properties *prop = &hdev->asic_prop; - u64 sram_kmd_size, dram_kmd_size; + u64 sram_kmd_size, dram_kmd_size, dram_available_size; if ((!size) || (!out)) return -EINVAL; @@ -62,19 +62,22 @@ static int hw_ip_info(struct hl_device *hdev, struct hl_info_args *args) hw_ip.dram_base_address = hdev->mmu_enable && prop->dram_supports_virtual_memory ? prop->dmmu.start_addr : prop->dram_user_base_address; - hw_ip.tpc_enabled_mask = prop->tpc_enabled_mask; + hw_ip.tpc_enabled_mask = prop->tpc_enabled_mask & 0xFF; + hw_ip.tpc_enabled_mask_ext = prop->tpc_enabled_mask; + hw_ip.sram_size = prop->sram_size - sram_kmd_size; - if (hdev->mmu_enable) - hw_ip.dram_size = - DIV_ROUND_DOWN_ULL(prop->dram_size - dram_kmd_size, - prop->dram_page_size) * - prop->dram_page_size; + dram_available_size = prop->dram_size - dram_kmd_size; + + if (hdev->mmu_enable == MMU_EN_ALL) + hw_ip.dram_size = DIV_ROUND_DOWN_ULL(dram_available_size, + prop->dram_page_size) * prop->dram_page_size; else - hw_ip.dram_size = prop->dram_size - dram_kmd_size; + hw_ip.dram_size = dram_available_size; if (hw_ip.dram_size > PAGE_SIZE) hw_ip.dram_enabled = 1; + hw_ip.dram_page_size = prop->dram_page_size; hw_ip.device_mem_alloc_default_page_size = prop->device_mem_alloc_default_page_size; hw_ip.num_of_events = prop->num_of_events; @@ -93,8 +96,12 @@ static int hw_ip_info(struct hl_device *hdev, struct hl_info_args *args) hw_ip.psoc_pci_pll_od = prop->psoc_pci_pll_od; hw_ip.psoc_pci_pll_div_factor = prop->psoc_pci_pll_div_factor; - hw_ip.first_available_interrupt_id = prop->first_available_user_msix_interrupt; + hw_ip.decoder_enabled_mask = prop->decoder_enabled_mask; + hw_ip.mme_master_slave_mode = prop->mme_master_slave_mode; + hw_ip.first_available_interrupt_id = prop->first_available_user_interrupt; hw_ip.number_of_user_interrupts = prop->user_interrupt_count; + + hw_ip.edma_enabled_mask = prop->edma_enabled_mask; hw_ip.server_type = prop->server_type; return copy_to_user(out, &hw_ip, @@ -287,7 +294,7 @@ static int get_reset_count(struct hl_device *hdev, struct hl_info_args *args) return -EINVAL; reset_count.hard_reset_cnt = hdev->reset_info.hard_reset_cnt; - reset_count.soft_reset_cnt = hdev->reset_info.soft_reset_cnt; + reset_count.soft_reset_cnt = hdev->reset_info.compute_reset_cnt; return copy_to_user(out, &reset_count, min((size_t) max_size, sizeof(reset_count))) ? -EFAULT : 0; @@ -610,6 +617,28 @@ static int razwi_info(struct hl_fpriv *hpriv, struct hl_info_args *args) return copy_to_user(out, &info, min_t(size_t, max_size, sizeof(info))) ? -EFAULT : 0; } +static int undefined_opcode_info(struct hl_fpriv *hpriv, struct hl_info_args *args) +{ + struct hl_device *hdev = hpriv->hdev; + u32 max_size = args->return_size; + struct hl_info_undefined_opcode_event info = {0}; + void __user *out = (void __user *) (uintptr_t) args->return_pointer; + + if ((!max_size) || (!out)) + return -EINVAL; + + info.timestamp = ktime_to_ns(hdev->last_error.undef_opcode.timestamp); + info.engine_id = hdev->last_error.undef_opcode.engine_id; + info.cq_addr = hdev->last_error.undef_opcode.cq_addr; + info.cq_size = hdev->last_error.undef_opcode.cq_size; + info.stream_id = hdev->last_error.undef_opcode.stream_id; + info.cb_addr_streams_len = hdev->last_error.undef_opcode.cb_addr_streams_len; + memcpy(info.cb_addr_streams, hdev->last_error.undef_opcode.cb_addr_streams, + sizeof(info.cb_addr_streams)); + + return copy_to_user(out, &info, min_t(size_t, max_size, sizeof(info))) ? -EFAULT : 0; +} + static int dev_mem_alloc_page_sizes_info(struct hl_fpriv *hpriv, struct hl_info_args *args) { void __user *out = (void __user *) (uintptr_t) args->return_pointer; @@ -626,7 +655,7 @@ static int dev_mem_alloc_page_sizes_info(struct hl_fpriv *hpriv, struct hl_info_ * For this reason for all ASICs that not support multiple page size the function will * return an empty bitmask indicating that multiple page sizes is not supported. */ - hdev->asic_funcs->get_valid_dram_page_orders(&info); + info.page_order_bitmask = hdev->asic_prop.dmmu.supported_pages_mask; return copy_to_user(out, &info, min_t(size_t, max_size, sizeof(info))) ? -EFAULT : 0; } @@ -718,6 +747,9 @@ static int _hl_info_ioctl(struct hl_fpriv *hpriv, void *data, case HL_INFO_RAZWI_EVENT: return razwi_info(hpriv, args); + case HL_INFO_UNDEFINED_OPCODE_EVENT: + return undefined_opcode_info(hpriv, args); + case HL_INFO_DEV_MEM_ALLOC_PAGE_SIZES: return dev_mem_alloc_page_sizes_info(hpriv, args); diff --git a/drivers/misc/habanalabs/common/hw_queue.c b/drivers/misc/habanalabs/common/hw_queue.c index 6103e479e855..3f15ab9d827f 100644 --- a/drivers/misc/habanalabs/common/hw_queue.c +++ b/drivers/misc/habanalabs/common/hw_queue.c @@ -308,6 +308,7 @@ static void ext_queue_schedule_job(struct hl_cs_job *job) cq_addr = cq->bus_address + cq->pi * sizeof(struct hl_cq_entry); hdev->asic_funcs->add_end_of_cb_packets(hdev, cb->kernel_address, len, + job->user_cb_size, cq_addr, le32_to_cpu(cq_pkt.data), q->msi_vec, @@ -695,6 +696,16 @@ int hl_hw_queue_schedule_cs(struct hl_cs *cs) goto unroll_cq_resv; } + rc = hdev->asic_funcs->pre_schedule_cs(cs); + if (rc) { + dev_err(hdev->dev, + "Failed in pre-submission operations of CS %d.%llu\n", + ctx->asid, cs->sequence); + goto unroll_cq_resv; + } + + hdev->shadow_cs_queue[cs->sequence & + (hdev->asic_prop.max_pending_cs - 1)] = cs; if (cs->encaps_signals && cs->staged_first) { rc = encaps_sig_first_staged_cs_handler(hdev, cs); @@ -806,13 +817,9 @@ static int ext_and_cpu_queue_init(struct hl_device *hdev, struct hl_hw_queue *q, int rc; if (is_cpu_queue) - p = hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev, - HL_QUEUE_SIZE_IN_BYTES, - &q->bus_address); + p = hl_cpu_accessible_dma_pool_alloc(hdev, HL_QUEUE_SIZE_IN_BYTES, &q->bus_address); else - p = hdev->asic_funcs->asic_dma_alloc_coherent(hdev, - HL_QUEUE_SIZE_IN_BYTES, - &q->bus_address, + p = hl_asic_dma_alloc_coherent(hdev, HL_QUEUE_SIZE_IN_BYTES, &q->bus_address, GFP_KERNEL | __GFP_ZERO); if (!p) return -ENOMEM; @@ -838,14 +845,10 @@ static int ext_and_cpu_queue_init(struct hl_device *hdev, struct hl_hw_queue *q, free_queue: if (is_cpu_queue) - hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev, - HL_QUEUE_SIZE_IN_BYTES, - q->kernel_address); + hl_cpu_accessible_dma_pool_free(hdev, HL_QUEUE_SIZE_IN_BYTES, q->kernel_address); else - hdev->asic_funcs->asic_dma_free_coherent(hdev, - HL_QUEUE_SIZE_IN_BYTES, - q->kernel_address, - q->bus_address); + hl_asic_dma_free_coherent(hdev, HL_QUEUE_SIZE_IN_BYTES, q->kernel_address, + q->bus_address); return rc; } @@ -884,10 +887,8 @@ static int hw_queue_init(struct hl_device *hdev, struct hl_hw_queue *q) { void *p; - p = hdev->asic_funcs->asic_dma_alloc_coherent(hdev, - HL_QUEUE_SIZE_IN_BYTES, - &q->bus_address, - GFP_KERNEL | __GFP_ZERO); + p = hl_asic_dma_alloc_coherent(hdev, HL_QUEUE_SIZE_IN_BYTES, &q->bus_address, + GFP_KERNEL | __GFP_ZERO); if (!p) return -ENOMEM; @@ -1060,14 +1061,10 @@ static void queue_fini(struct hl_device *hdev, struct hl_hw_queue *q) kfree(q->shadow_queue); if (q->queue_type == QUEUE_TYPE_CPU) - hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev, - HL_QUEUE_SIZE_IN_BYTES, - q->kernel_address); + hl_cpu_accessible_dma_pool_free(hdev, HL_QUEUE_SIZE_IN_BYTES, q->kernel_address); else - hdev->asic_funcs->asic_dma_free_coherent(hdev, - HL_QUEUE_SIZE_IN_BYTES, - q->kernel_address, - q->bus_address); + hl_asic_dma_free_coherent(hdev, HL_QUEUE_SIZE_IN_BYTES, q->kernel_address, + q->bus_address); } int hl_hw_queues_create(struct hl_device *hdev) diff --git a/drivers/misc/habanalabs/common/irq.c b/drivers/misc/habanalabs/common/irq.c index 8500e15ef743..94d537fd4fde 100644 --- a/drivers/misc/habanalabs/common/irq.c +++ b/drivers/misc/habanalabs/common/irq.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2016-2019 HabanaLabs, Ltd. + * Copyright 2016-2022 HabanaLabs, Ltd. * All Rights Reserved. */ @@ -66,6 +66,56 @@ static void irq_handle_eqe(struct work_struct *work) kfree(eqe_work); } +/** + * job_finish - queue job finish work + * + * @hdev: pointer to device structure + * @cs_seq: command submission sequence + * @cq: completion queue + * + */ +static void job_finish(struct hl_device *hdev, u32 cs_seq, struct hl_cq *cq) +{ + struct hl_hw_queue *queue; + struct hl_cs_job *job; + + queue = &hdev->kernel_queues[cq->hw_queue_id]; + job = queue->shadow_queue[hl_pi_2_offset(cs_seq)]; + queue_work(hdev->cq_wq[cq->cq_idx], &job->finish_work); + + atomic_inc(&queue->ci); +} + +/** + * cs_finish - queue all cs jobs finish work + * + * @hdev: pointer to device structure + * @cs_seq: command submission sequence + * + */ +static void cs_finish(struct hl_device *hdev, u16 cs_seq) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct hl_hw_queue *queue; + struct hl_cs *cs; + struct hl_cs_job *job; + + cs = hdev->shadow_cs_queue[cs_seq & (prop->max_pending_cs - 1)]; + if (!cs) { + dev_warn(hdev->dev, + "No pointer to CS in shadow array at index %d\n", + cs_seq); + return; + } + + list_for_each_entry(job, &cs->job_list, cs_node) { + queue = &hdev->kernel_queues[job->hw_queue_id]; + atomic_inc(&queue->ci); + } + + queue_work(hdev->cs_cmplt_wq, &cs->finish_work); +} + /** * hl_irq_handler_cq - irq handler for completion queue * @@ -77,9 +127,7 @@ irqreturn_t hl_irq_handler_cq(int irq, void *arg) { struct hl_cq *cq = arg; struct hl_device *hdev = cq->hdev; - struct hl_hw_queue *queue; - struct hl_cs_job *job; - bool shadow_index_valid; + bool shadow_index_valid, entry_ready; u16 shadow_index; struct hl_cq_entry *cq_entry, *cq_base; @@ -93,37 +141,41 @@ irqreturn_t hl_irq_handler_cq(int irq, void *arg) cq_base = cq->kernel_address; while (1) { - bool entry_ready = ((le32_to_cpu(cq_base[cq->ci].data) & - CQ_ENTRY_READY_MASK) - >> CQ_ENTRY_READY_SHIFT); + cq_entry = (struct hl_cq_entry *) &cq_base[cq->ci]; + entry_ready = !!FIELD_GET(CQ_ENTRY_READY_MASK, + le32_to_cpu(cq_entry->data)); if (!entry_ready) break; - cq_entry = (struct hl_cq_entry *) &cq_base[cq->ci]; - /* Make sure we read CQ entry contents after we've * checked the ownership bit. */ dma_rmb(); - shadow_index_valid = ((le32_to_cpu(cq_entry->data) & - CQ_ENTRY_SHADOW_INDEX_VALID_MASK) - >> CQ_ENTRY_SHADOW_INDEX_VALID_SHIFT); + shadow_index_valid = + !!FIELD_GET(CQ_ENTRY_SHADOW_INDEX_VALID_MASK, + le32_to_cpu(cq_entry->data)); - shadow_index = (u16) ((le32_to_cpu(cq_entry->data) & - CQ_ENTRY_SHADOW_INDEX_MASK) - >> CQ_ENTRY_SHADOW_INDEX_SHIFT); + shadow_index = FIELD_GET(CQ_ENTRY_SHADOW_INDEX_MASK, + le32_to_cpu(cq_entry->data)); - queue = &hdev->kernel_queues[cq->hw_queue_id]; - - if ((shadow_index_valid) && (!hdev->disabled)) { - job = queue->shadow_queue[hl_pi_2_offset(shadow_index)]; - queue_work(hdev->cq_wq[cq->cq_idx], &job->finish_work); + /* + * CQ interrupt handler has 2 modes of operation: + * 1. Interrupt per CS completion: (Single CQ for all queues) + * CQ entry represents a completed CS + * + * 2. Interrupt per CS job completion in queue: (CQ per queue) + * CQ entry represents a completed job in a certain queue + */ + if (shadow_index_valid && !hdev->disabled) { + if (hdev->asic_prop.completion_mode == + HL_COMPLETION_MODE_CS) + cs_finish(hdev, shadow_index); + else + job_finish(hdev, shadow_index, cq); } - atomic_inc(&queue->ci); - /* Clear CQ entry ready bit */ cq_entry->data = cpu_to_le32(le32_to_cpu(cq_entry->data) & ~CQ_ENTRY_READY_MASK); @@ -217,8 +269,7 @@ static int handle_registration_node(struct hl_device *hdev, struct hl_user_pendi return 0; } -static void handle_user_cq(struct hl_device *hdev, - struct hl_user_interrupt *user_cq) +static void handle_user_interrupt(struct hl_device *hdev, struct hl_user_interrupt *intr) { struct hl_user_pending_interrupt *pend, *temp_pend; struct list_head *ts_reg_free_list_head = NULL; @@ -240,8 +291,8 @@ static void handle_user_cq(struct hl_device *hdev, if (!job) return; - spin_lock(&user_cq->wait_list_lock); - list_for_each_entry_safe(pend, temp_pend, &user_cq->wait_list_head, wait_list_node) { + spin_lock(&intr->wait_list_lock); + list_for_each_entry_safe(pend, temp_pend, &intr->wait_list_head, wait_list_node) { if ((pend->cq_kernel_addr && *(pend->cq_kernel_addr) >= pend->cq_target_value) || !pend->cq_kernel_addr) { if (pend->ts_reg_info.buf) { @@ -258,7 +309,7 @@ static void handle_user_cq(struct hl_device *hdev, } } } - spin_unlock(&user_cq->wait_list_lock); + spin_unlock(&intr->wait_list_lock); if (ts_reg_free_list_head) { INIT_WORK(&job->free_obj, hl_ts_free_objects); @@ -271,22 +322,24 @@ static void handle_user_cq(struct hl_device *hdev, } /** - * hl_irq_handler_user_cq - irq handler for user completion queues + * hl_irq_handler_user_interrupt - irq handler for user interrupts * * @irq: irq number * @arg: pointer to user interrupt structure * */ -irqreturn_t hl_irq_handler_user_cq(int irq, void *arg) +irqreturn_t hl_irq_handler_user_interrupt(int irq, void *arg) { - struct hl_user_interrupt *user_cq = arg; - struct hl_device *hdev = user_cq->hdev; + struct hl_user_interrupt *user_int = arg; + struct hl_device *hdev = user_int->hdev; - /* Handle user cq interrupts registered on all interrupts */ - handle_user_cq(hdev, &hdev->common_user_interrupt); + if (user_int->is_decoder) + handle_user_interrupt(hdev, &hdev->common_decoder_interrupt); + else + handle_user_interrupt(hdev, &hdev->common_user_cq_interrupt); - /* Handle user cq interrupts registered on this specific interrupt */ - handle_user_cq(hdev, user_cq); + /* Handle user cq or decoder interrupts registered on this specific irq */ + handle_user_interrupt(hdev, user_int); return IRQ_HANDLED; } @@ -304,9 +357,7 @@ irqreturn_t hl_irq_handler_default(int irq, void *arg) struct hl_device *hdev = user_interrupt->hdev; u32 interrupt_id = user_interrupt->interrupt_id; - dev_err(hdev->dev, - "got invalid user interrupt %u", - interrupt_id); + dev_err(hdev->dev, "got invalid user interrupt %u", interrupt_id); return IRQ_HANDLED; } @@ -360,7 +411,7 @@ irqreturn_t hl_irq_handler_eq(int irq, void *arg) */ dma_rmb(); - if (hdev->disabled && !hdev->reset_info.is_in_soft_reset) { + if (hdev->disabled && !hdev->reset_info.in_compute_reset) { dev_warn(hdev->dev, "Device disabled but received an EQ event\n"); goto skip_irq; } @@ -389,12 +440,27 @@ skip_irq: return IRQ_HANDLED; } +/** + * hl_irq_handler_dec_abnrm - Decoder error interrupt handler + * @irq: IRQ number + * @arg: pointer to decoder structure. + */ +irqreturn_t hl_irq_handler_dec_abnrm(int irq, void *arg) +{ + struct hl_dec *dec = arg; + + schedule_work(&dec->completion_abnrm_work); + + return IRQ_HANDLED; +} + /** * hl_cq_init - main initialization function for an cq object * * @hdev: pointer to device structure * @q: pointer to cq structure * @hw_queue_id: The H/W queue ID this completion queue belongs to + * HL_INVALID_QUEUE if cq is not attached to any specific queue * * Allocate dma-able memory for the completion queue and initialize fields * Returns 0 on success @@ -403,8 +469,8 @@ int hl_cq_init(struct hl_device *hdev, struct hl_cq *q, u32 hw_queue_id) { void *p; - p = hdev->asic_funcs->asic_dma_alloc_coherent(hdev, HL_CQ_SIZE_IN_BYTES, - &q->bus_address, GFP_KERNEL | __GFP_ZERO); + p = hl_asic_dma_alloc_coherent(hdev, HL_CQ_SIZE_IN_BYTES, &q->bus_address, + GFP_KERNEL | __GFP_ZERO); if (!p) return -ENOMEM; @@ -429,9 +495,7 @@ int hl_cq_init(struct hl_device *hdev, struct hl_cq *q, u32 hw_queue_id) */ void hl_cq_fini(struct hl_device *hdev, struct hl_cq *q) { - hdev->asic_funcs->asic_dma_free_coherent(hdev, HL_CQ_SIZE_IN_BYTES, - q->kernel_address, - q->bus_address); + hl_asic_dma_free_coherent(hdev, HL_CQ_SIZE_IN_BYTES, q->kernel_address, q->bus_address); } void hl_cq_reset(struct hl_device *hdev, struct hl_cq *q) @@ -464,9 +528,7 @@ int hl_eq_init(struct hl_device *hdev, struct hl_eq *q) { void *p; - p = hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev, - HL_EQ_SIZE_IN_BYTES, - &q->bus_address); + p = hl_cpu_accessible_dma_pool_alloc(hdev, HL_EQ_SIZE_IN_BYTES, &q->bus_address); if (!p) return -ENOMEM; @@ -490,9 +552,7 @@ void hl_eq_fini(struct hl_device *hdev, struct hl_eq *q) { flush_workqueue(hdev->eq_wq); - hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev, - HL_EQ_SIZE_IN_BYTES, - q->kernel_address); + hl_cpu_accessible_dma_pool_free(hdev, HL_EQ_SIZE_IN_BYTES, q->kernel_address); } void hl_eq_reset(struct hl_device *hdev, struct hl_eq *q) diff --git a/drivers/misc/habanalabs/common/memory.c b/drivers/misc/habanalabs/common/memory.c index 663dd7e589d4..61bc1bfe984a 100644 --- a/drivers/misc/habanalabs/common/memory.c +++ b/drivers/misc/habanalabs/common/memory.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2016-2021 HabanaLabs, Ltd. + * Copyright 2016-2022 HabanaLabs, Ltd. * All Rights Reserved. */ @@ -27,7 +27,7 @@ static int allocate_timestamps_buffers(struct hl_fpriv *hpriv, static int set_alloc_page_size(struct hl_device *hdev, struct hl_mem_in *args, u32 *page_size) { struct asic_fixed_properties *prop = &hdev->asic_prop; - u32 psize; + u64 psize; /* * for ASIC that supports setting the allocation page size by user we will address @@ -36,8 +36,8 @@ static int set_alloc_page_size(struct hl_device *hdev, struct hl_mem_in *args, u if (prop->supports_user_set_page_size && args->alloc.page_size) { psize = args->alloc.page_size; - if (!hdev->asic_funcs->is_valid_dram_page_size(psize)) { - dev_err(hdev->dev, "user page size (%#x) is not valid\n", psize); + if (!is_power_of_2(psize)) { + dev_err(hdev->dev, "user page size (%#llx) is not power of 2\n", psize); return -EINVAL; } } else { @@ -305,33 +305,20 @@ static void dram_pg_pool_do_release(struct kref *ref) * * This function does the following: * - For DRAM memory only - * - iterate over the pack, scrub and free each physical block structure by + * - iterate over the pack, free each physical block structure by * returning it to the general pool. - * In case of error during scrubbing, initiate hard reset. - * Once hard reset is triggered, scrubbing is bypassed while freeing the - * memory continues. * - Free the hl_vm_phys_pg_pack structure. */ -static int free_phys_pg_pack(struct hl_device *hdev, +static void free_phys_pg_pack(struct hl_device *hdev, struct hl_vm_phys_pg_pack *phys_pg_pack) { struct hl_vm *vm = &hdev->vm; u64 i; - int rc = 0; if (phys_pg_pack->created_from_userptr) goto end; if (phys_pg_pack->contiguous) { - if (hdev->memory_scrub && !hdev->disabled) { - rc = hdev->asic_funcs->scrub_device_mem(hdev, - phys_pg_pack->pages[0], - phys_pg_pack->total_size); - if (rc) - dev_err(hdev->dev, - "Failed to scrub contiguous device memory\n"); - } - gen_pool_free(vm->dram_pg_pool, phys_pg_pack->pages[0], phys_pg_pack->total_size); @@ -340,15 +327,6 @@ static int free_phys_pg_pack(struct hl_device *hdev, dram_pg_pool_do_release); } else { for (i = 0 ; i < phys_pg_pack->npages ; i++) { - if (hdev->memory_scrub && !hdev->disabled && rc == 0) { - rc = hdev->asic_funcs->scrub_device_mem( - hdev, - phys_pg_pack->pages[i], - phys_pg_pack->page_size); - if (rc) - dev_err(hdev->dev, - "Failed to scrub device memory\n"); - } gen_pool_free(vm->dram_pg_pool, phys_pg_pack->pages[i], phys_pg_pack->page_size); @@ -357,14 +335,11 @@ static int free_phys_pg_pack(struct hl_device *hdev, } } - if (rc && !hdev->disabled) - hl_device_reset(hdev, HL_DRV_RESET_HARD); - end: kvfree(phys_pg_pack->pages); kfree(phys_pg_pack); - return rc; + return; } /** @@ -384,40 +359,35 @@ static int free_device_memory(struct hl_ctx *ctx, struct hl_mem_in *args) spin_lock(&vm->idr_lock); phys_pg_pack = idr_find(&vm->phys_pg_pack_handles, handle); - if (phys_pg_pack) { - if (atomic_read(&phys_pg_pack->mapping_cnt) > 0) { - dev_err(hdev->dev, "handle %u is mapped, cannot free\n", - handle); - spin_unlock(&vm->idr_lock); - return -EINVAL; - } - - if (phys_pg_pack->exporting_cnt) { - dev_dbg(hdev->dev, "handle %u is exported, cannot free\n", handle); - spin_unlock(&vm->idr_lock); - return -EINVAL; - } - - /* - * must remove from idr before the freeing of the physical - * pages as the refcount of the pool is also the trigger of the - * idr destroy - */ - idr_remove(&vm->phys_pg_pack_handles, handle); + if (!phys_pg_pack) { spin_unlock(&vm->idr_lock); - - atomic64_sub(phys_pg_pack->total_size, &ctx->dram_phys_mem); - atomic64_sub(phys_pg_pack->total_size, &hdev->dram_used_mem); - - return free_phys_pg_pack(hdev, phys_pg_pack); - } else { - spin_unlock(&vm->idr_lock); - dev_err(hdev->dev, - "free device memory failed, no match for handle %u\n", - handle); + dev_err(hdev->dev, "free device memory failed, no match for handle %u\n", handle); return -EINVAL; } + if (atomic_read(&phys_pg_pack->mapping_cnt) > 0) { + spin_unlock(&vm->idr_lock); + dev_err(hdev->dev, "handle %u is mapped, cannot free\n", handle); + return -EINVAL; + } + + if (phys_pg_pack->exporting_cnt) { + spin_unlock(&vm->idr_lock); + dev_dbg(hdev->dev, "handle %u is exported, cannot free\n", handle); + return -EINVAL; + } + + /* must remove from idr before the freeing of the physical pages as the refcount of the pool + * is also the trigger of the idr destroy + */ + idr_remove(&vm->phys_pg_pack_handles, handle); + spin_unlock(&vm->idr_lock); + + atomic64_sub(phys_pg_pack->total_size, &ctx->dram_phys_mem); + atomic64_sub(phys_pg_pack->total_size, &hdev->dram_used_mem); + + free_phys_pg_pack(hdev, phys_pg_pack); + return 0; } @@ -657,7 +627,7 @@ static u64 get_va_block(struct hl_device *hdev, /* Check if we need to ignore hint address */ if ((is_align_pow_2 && (hint_addr & (va_block_align - 1))) || - (!is_align_pow_2 && is_hint_dram_addr && + (!is_align_pow_2 && is_hint_dram_addr && do_div(tmp_hint_addr, va_range->page_size))) { if (force_hint) { @@ -1245,16 +1215,16 @@ static int map_device_va(struct hl_ctx *ctx, struct hl_mem_in *args, u64 *device rc = map_phys_pg_pack(ctx, ret_vaddr, phys_pg_pack); if (rc) { dev_err(hdev->dev, "mapping page pack failed for handle %u\n", handle); + mutex_unlock(&ctx->mmu_lock); goto map_err; } rc = hl_mmu_invalidate_cache_range(hdev, false, *vm_type | MMU_OP_SKIP_LOW_CACHE_INV, ctx->asid, ret_vaddr, phys_pg_pack->total_size); + mutex_unlock(&ctx->mmu_lock); if (rc) goto map_err; - mutex_unlock(&ctx->mmu_lock); - /* * prefetch is done upon user's request. it is performed in WQ as and so can * be outside the MMU lock. the operation itself is already protected by the mmu lock @@ -1278,13 +1248,11 @@ static int map_device_va(struct hl_ctx *ctx, struct hl_mem_in *args, u64 *device *device_addr = ret_vaddr; if (is_userptr) - rc = free_phys_pg_pack(hdev, phys_pg_pack); + free_phys_pg_pack(hdev, phys_pg_pack); return rc; map_err: - mutex_unlock(&ctx->mmu_lock); - if (add_va_block(hdev, va_range, ret_vaddr, ret_vaddr + phys_pg_pack->total_size - 1)) dev_warn(hdev->dev, @@ -2509,17 +2477,20 @@ bool hl_userptr_is_pinned(struct hl_device *hdev, u64 addr, * va_range_init() - initialize virtual addresses range. * @hdev: pointer to the habanalabs device structure. * @va_ranges: pointer to va_ranges array. - * @start: range start address. - * @end: range end address. + * @range_type: virtual address range type. + * @start: range start address, inclusive. + * @end: range end address, inclusive. * @page_size: page size for this va_range. * * This function does the following: * - Initializes the virtual addresses list of the given range with the given * addresses. */ -static int va_range_init(struct hl_device *hdev, struct hl_va_range *va_range, - u64 start, u64 end, u32 page_size) +static int va_range_init(struct hl_device *hdev, struct hl_va_range **va_ranges, + enum hl_va_range_type range_type, u64 start, + u64 end, u32 page_size) { + struct hl_va_range *va_range = va_ranges[range_type]; int rc; INIT_LIST_HEAD(&va_range->list); @@ -2637,7 +2608,7 @@ static int vm_ctx_init_with_ranges(struct hl_ctx *ctx, mutex_init(&ctx->va_range[HL_VA_RANGE_TYPE_HOST]->lock); - rc = va_range_init(hdev, ctx->va_range[HL_VA_RANGE_TYPE_HOST], + rc = va_range_init(hdev, ctx->va_range, HL_VA_RANGE_TYPE_HOST, host_range_start, host_range_end, host_page_size); if (rc) { dev_err(hdev->dev, "failed to init host vm range\n"); @@ -2648,7 +2619,7 @@ static int vm_ctx_init_with_ranges(struct hl_ctx *ctx, mutex_init(&ctx->va_range[HL_VA_RANGE_TYPE_HOST_HUGE]->lock); rc = va_range_init(hdev, - ctx->va_range[HL_VA_RANGE_TYPE_HOST_HUGE], + ctx->va_range, HL_VA_RANGE_TYPE_HOST_HUGE, host_huge_range_start, host_huge_range_end, host_huge_page_size); if (rc) { @@ -2664,7 +2635,7 @@ static int vm_ctx_init_with_ranges(struct hl_ctx *ctx, mutex_init(&ctx->va_range[HL_VA_RANGE_TYPE_DRAM]->lock); - rc = va_range_init(hdev, ctx->va_range[HL_VA_RANGE_TYPE_DRAM], + rc = va_range_init(hdev, ctx->va_range, HL_VA_RANGE_TYPE_DRAM, dram_range_start, dram_range_end, dram_page_size); if (rc) { dev_err(hdev->dev, "failed to init dram vm range\n"); diff --git a/drivers/misc/habanalabs/common/memory_mgr.c b/drivers/misc/habanalabs/common/memory_mgr.c index ea5f2bd31b0a..56df962d2f3c 100644 --- a/drivers/misc/habanalabs/common/memory_mgr.c +++ b/drivers/misc/habanalabs/common/memory_mgr.c @@ -135,7 +135,7 @@ int hl_mmap_mem_buf_put_handle(struct hl_mem_mgr *mmg, u64 handle) } /** - * @hl_mmap_mem_buf_alloc - allocate a new mappable buffer + * hl_mmap_mem_buf_alloc - allocate a new mappable buffer * * @mmg: parent unifed memory manager * @behavior: behavior object describing this buffer polymorphic behavior diff --git a/drivers/misc/habanalabs/common/mmu/Makefile b/drivers/misc/habanalabs/common/mmu/Makefile index d852c3874658..1806c524e04a 100644 --- a/drivers/misc/habanalabs/common/mmu/Makefile +++ b/drivers/misc/habanalabs/common/mmu/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only -HL_COMMON_MMU_FILES := common/mmu/mmu.o common/mmu/mmu_v1.o +HL_COMMON_MMU_FILES := common/mmu/mmu.o common/mmu/mmu_v1.o \ + common/mmu/mmu_v2_hr.o diff --git a/drivers/misc/habanalabs/common/mmu/mmu.c b/drivers/misc/habanalabs/common/mmu/mmu.c index f3734718d94f..60740de47b34 100644 --- a/drivers/misc/habanalabs/common/mmu/mmu.c +++ b/drivers/misc/habanalabs/common/mmu/mmu.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2016-2020 HabanaLabs, Ltd. + * Copyright 2016-2022 HabanaLabs, Ltd. * All Rights Reserved. */ @@ -51,8 +51,17 @@ int hl_mmu_init(struct hl_device *hdev) return rc; } - if (hdev->mmu_func[MMU_HR_PGT].init != NULL) + if (hdev->mmu_func[MMU_HR_PGT].init != NULL) { rc = hdev->mmu_func[MMU_HR_PGT].init(hdev); + if (rc) + goto fini_dr_mmu; + } + + return 0; + +fini_dr_mmu: + if (hdev->mmu_func[MMU_DR_PGT].fini != NULL) + hdev->mmu_func[MMU_DR_PGT].fini(hdev); return rc; } @@ -103,8 +112,17 @@ int hl_mmu_ctx_init(struct hl_ctx *ctx) return rc; } - if (hdev->mmu_func[MMU_HR_PGT].ctx_init != NULL) + if (hdev->mmu_func[MMU_HR_PGT].ctx_init != NULL) { rc = hdev->mmu_func[MMU_HR_PGT].ctx_init(ctx); + if (rc) + goto fini_dr_ctx; + } + + return 0; + +fini_dr_ctx: + if (hdev->mmu_func[MMU_DR_PGT].fini != NULL) + hdev->mmu_func[MMU_DR_PGT].fini(hdev); return rc; } @@ -607,6 +625,11 @@ int hl_mmu_if_set_funcs(struct hl_device *hdev) case ASIC_GAUDI_SEC: hl_mmu_v1_set_funcs(hdev, &hdev->mmu_func[MMU_DR_PGT]); break; + case ASIC_GAUDI2: + case ASIC_GAUDI2_SEC: + /* MMUs in Gaudi2 are always host resident */ + hl_mmu_v2_hr_set_funcs(hdev, &hdev->mmu_func[MMU_HR_PGT]); + break; default: dev_err(hdev->dev, "Unrecognized ASIC type %d\n", hdev->asic_type); @@ -745,3 +768,470 @@ u64 hl_mmu_get_hop_pte_phys_addr(struct hl_ctx *ctx, struct hl_mmu_properties *m return hop_addr + ctx->hdev->asic_prop.mmu_pte_size * ((virt_addr & mask) >> shift); } +static void mmu_dma_mem_free_from_chunk(struct gen_pool *pool, + struct gen_pool_chunk *chunk, + void *data) +{ + struct hl_device *hdev = (struct hl_device *)data; + + hl_asic_dma_free_coherent(hdev, (chunk->end_addr - chunk->start_addr) + 1, + (void *)chunk->start_addr, chunk->phys_addr); +} + +void hl_mmu_hr_flush(struct hl_ctx *ctx) +{ + /* a flush operation requires memory barrier */ + mb(); +} + +/** + * hl_mmu_hr_pool_destroy() - destroy genpool + * @hdev: habanalabs device structure. + * @hr_priv: MMU HR private data. + * @hop_table_size: HOP table size. + * + * This function does the following: + * - free entries allocated for shadow HOP0 + * - free pool chunks + * - free pool + */ +static void hl_mmu_hr_pool_destroy(struct hl_device *hdev, struct hl_mmu_hr_priv *hr_priv, + u32 hop_table_size) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct gen_pool **pool = &hr_priv->mmu_pgt_pool; + struct pgt_info *hop0_pgt; + int asid; + + if (ZERO_OR_NULL_PTR(*pool)) + return; + + /* Free the Fixed allocation of HOPs0 */ + if (hr_priv->mmu_asid_hop0) { + for (asid = 0 ; asid < prop->max_asid ; asid++) { + hop0_pgt = &hr_priv->mmu_asid_hop0[asid]; + if (ZERO_OR_NULL_PTR(hop0_pgt->virt_addr)) + continue; + + gen_pool_free(*pool, (uintptr_t) hop0_pgt->virt_addr, hop_table_size); + } + } + + gen_pool_for_each_chunk(*pool, mmu_dma_mem_free_from_chunk, hdev); + gen_pool_destroy(*pool); + + /* Make sure that if we arrive here again without init was called we + * won't cause kernel panic. This can happen for example if we fail + * during hard reset code at certain points + */ + *pool = NULL; +} + +/** + * hl_mmu_hr_init() - initialize the MMU module. + * @hdev: habanalabs device structure. + * @hr_priv: MMU HR private data. + * @hop_table_size: HOP table size. + * @pgt_size: memory size allocated for the page table + * + * @return 0 on success otherwise non-zero error code + * + * This function does the following: + * - Create a pool of pages for pgt_infos. + * - Create a shadow table for pgt + */ +int hl_mmu_hr_init(struct hl_device *hdev, struct hl_mmu_hr_priv *hr_priv, u32 hop_table_size, + u64 pgt_size) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + size_t pool_chunk_size = SZ_4M; + struct pgt_info *hop0_pgt; + dma_addr_t dma_addr; + u64 virt_addr; + int i, rc; + + /* + * we set alloc size as PAGE_SIZE (sine dma_alloc_coherent allocation order/size is + * PAGE_SHIFT/PAGE_SIZE) in order to be able to control the allocations alignment. + * This way we can call "DMA alloc align" according to dma_alloc granularity and supply + * allocations with higher-order alignment restrictions + */ + hr_priv->mmu_pgt_pool = gen_pool_create(PAGE_SHIFT, -1); + if (ZERO_OR_NULL_PTR(hr_priv->mmu_pgt_pool)) { + dev_err(hdev->dev, "Failed to create hr page pool\n"); + return -ENOMEM; + } + + hr_priv->mmu_asid_hop0 = kvcalloc(prop->max_asid, sizeof(struct pgt_info), GFP_KERNEL); + if (ZERO_OR_NULL_PTR(hr_priv->mmu_asid_hop0)) { + dev_err(hdev->dev, "Failed to allocate hr-mmu hop0 table\n"); + rc = -ENOMEM; + goto destroy_mmu_pgt_pool; + } + + for (i = 0 ; i < pgt_size ; i += pool_chunk_size) { + virt_addr = (uintptr_t) hl_asic_dma_alloc_coherent(hdev, pool_chunk_size, + &dma_addr, + GFP_KERNEL | __GFP_ZERO); + if (ZERO_OR_NULL_PTR(virt_addr)) { + dev_err(hdev->dev, + "Failed to allocate memory for host-resident page pool\n"); + rc = -ENOMEM; + goto destroy_mmu_pgt_pool; + } + + rc = gen_pool_add_virt(hr_priv->mmu_pgt_pool, virt_addr, (phys_addr_t) dma_addr, + pool_chunk_size, -1); + if (rc) { + dev_err(hdev->dev, "Failed to fill host-resident page pool\n"); + goto destroy_mmu_pgt_pool; + } + } + + for (i = 0 ; i < prop->max_asid ; i++) { + hop0_pgt = &hr_priv->mmu_asid_hop0[i]; + hop0_pgt->virt_addr = (uintptr_t) + gen_pool_dma_zalloc_align(hr_priv->mmu_pgt_pool, + hop_table_size, + (dma_addr_t *) &hop0_pgt->phys_addr, + hop_table_size); + if (!hop0_pgt->virt_addr) { + dev_err(hdev->dev, "Failed to allocate HOP from pgt pool\n"); + rc = -ENOMEM; + goto destroy_mmu_pgt_pool; + } + } + + /* MMU H/W init will be done in device hw_init() */ + + return 0; + +destroy_mmu_pgt_pool: + hl_mmu_hr_pool_destroy(hdev, hr_priv, hop_table_size); + if (!ZERO_OR_NULL_PTR(hr_priv->mmu_asid_hop0)) + kvfree(hr_priv->mmu_asid_hop0); + + return rc; +} + +/** + * hl_mmu_hr_fini() - release the MMU module. + * @hdev: habanalabs device structure. + * @hr_priv: MMU host resident private info. + * @hop_table_size: HOP table size + * + * This function does the following: + * - Disable MMU in H/W. + * - Free the pgt_infos pool. + * + * All contexts should be freed before calling this function. + */ +void hl_mmu_hr_fini(struct hl_device *hdev, struct hl_mmu_hr_priv *hr_priv, u32 hop_table_size) +{ + /* MMU H/W fini was already done in device hw_fini() */ + + hl_mmu_hr_pool_destroy(hdev, hr_priv, hop_table_size); + + if (!ZERO_OR_NULL_PTR(hr_priv->mmu_asid_hop0)) { + kvfree(hr_priv->mmu_asid_hop0); + + /* Make sure that if we arrive here again without init was + * called we won't cause kernel panic. This can happen for + * example if we fail during hard reset code at certain points + */ + hr_priv->mmu_asid_hop0 = NULL; + } +} + +/** + * hl_mmu_hr_free_hop_remove_pgt() - free HOP and remove PGT from hash + * @pgt_info: page table info structure. + * @hr_priv: MMU HR private data. + * @hop_table_size: HOP table size. + */ +void hl_mmu_hr_free_hop_remove_pgt(struct pgt_info *pgt_info, struct hl_mmu_hr_priv *hr_priv, + u32 hop_table_size) +{ + gen_pool_free(hr_priv->mmu_pgt_pool, pgt_info->virt_addr, hop_table_size); + hash_del(&pgt_info->node); + kfree(pgt_info); +} + +/** + * hl_mmu_hr_pte_phys_to_virt() - translate PTE phys addr to virt addr + * @ctx: pointer to the context structure + * @pgt: pgt_info for the HOP hosting the PTE + * @phys_pte_addr: phys address of the PTE + * @hop_table_size: HOP table size + * + * @return PTE virtual address + * + * The function use the pgt_info to get HOP base virt addr and obtain the PTE's virt addr + * by adding the PTE offset. + */ +u64 hl_mmu_hr_pte_phys_to_virt(struct hl_ctx *ctx, struct pgt_info *pgt, + u64 phys_pte_addr, u32 hop_table_size) +{ + u64 page_mask = (hop_table_size - 1); + u64 pte_offset = phys_pte_addr & page_mask; + + return pgt->virt_addr + pte_offset; +} + +/** + * hl_mmu_hr_write_pte() - write HR PTE + * @ctx: pointer to the context structure + * @pgt_info: HOP's page table info structure + * @phys_pte_addr: phys PTE address + * @val: raw PTE data + * @hop_table_size: HOP table size + */ +void hl_mmu_hr_write_pte(struct hl_ctx *ctx, struct pgt_info *pgt_info, u64 phys_pte_addr, + u64 val, u32 hop_table_size) +{ + /* + * The value to write is the phys address of the next hop + + * flags at the 12 LSBs. + */ + u64 virt_addr = hl_mmu_hr_pte_phys_to_virt(ctx, pgt_info, phys_pte_addr, hop_table_size); + + *((u64 *) (uintptr_t) virt_addr) = val; +} + +/** + * hl_mmu_hr_clear_pte() - clear HR PTE + * @ctx: pointer to the context structure + * @pgt_info: HOP's page table info structure + * @phys_pte_addr: phys PTE address + * @hop_table_size: HOP table size + */ +void hl_mmu_hr_clear_pte(struct hl_ctx *ctx, struct pgt_info *pgt_info, u64 phys_pte_addr, + u32 hop_table_size) +{ + /* no need to transform the value to physical address */ + hl_mmu_hr_write_pte(ctx, pgt_info, phys_pte_addr, 0, hop_table_size); +} + +/** + * hl_mmu_hr_put_pte() - put HR PTE and remove it if necessary (no more PTEs) + * @ctx: pointer to the context structure + * @pgt_info: HOP's page table info structure + * @hr_priv: HR MMU private info + * @hop_table_size: HOP table size + * + * @return number of PTEs still in the HOP + */ +int hl_mmu_hr_put_pte(struct hl_ctx *ctx, struct pgt_info *pgt_info, + struct hl_mmu_hr_priv *hr_priv, + u32 hop_table_size) +{ + int num_of_ptes_left; + + pgt_info->num_of_ptes--; + + /* + * Need to save the number of ptes left because free_hop might free + * the pgt_info + */ + num_of_ptes_left = pgt_info->num_of_ptes; + if (!num_of_ptes_left) + hl_mmu_hr_free_hop_remove_pgt(pgt_info, hr_priv, hop_table_size); + + return num_of_ptes_left; +} + +/** + * hl_mmu_hr_get_pte() - increase PGT PTE count + * @ctx: pointer to the context structure + * @hr_func: host resident functions + * @phys_hop_addr: HOP phys address + */ +void hl_mmu_hr_get_pte(struct hl_ctx *ctx, struct hl_hr_mmu_funcs *hr_func, u64 phys_hop_addr) +{ + hr_func->get_pgt_info(ctx, phys_hop_addr)->num_of_ptes++; +} + +/** + * hl_mmu_hr_get_next_hop_pgt_info() - get pgt_info structure for the next HOP + * @ctx: pointer to the context structure. + * @hr_func: host resident functions. + * @curr_pte: current PTE value. + * + * @return pgt_info structure on success, otherwise NULL. + */ +struct pgt_info *hl_mmu_hr_get_next_hop_pgt_info(struct hl_ctx *ctx, + struct hl_hr_mmu_funcs *hr_func, + u64 curr_pte) +{ + u64 next_hop_phys_addr = hl_mmu_get_next_hop_addr(ctx, curr_pte); + + if (next_hop_phys_addr == ULLONG_MAX) + return NULL; + + return hr_func->get_pgt_info(ctx, next_hop_phys_addr); +} + +/** + * hl_mmu_hr_alloc_hop() - allocate HOP + * @ctx: pointer to the context structure. + * @hr_priv: host resident private info structure. + * @hr_func: host resident functions. + * @mmu_prop: MMU properties. + * + * @return pgt_info structure associated with the allocated HOP on success, otherwise NULL. + */ +struct pgt_info *hl_mmu_hr_alloc_hop(struct hl_ctx *ctx, struct hl_mmu_hr_priv *hr_priv, + struct hl_hr_mmu_funcs *hr_func, + struct hl_mmu_properties *mmu_prop) +{ + struct hl_device *hdev = ctx->hdev; + struct pgt_info *pgt_info; + dma_addr_t phys_addr; + void *virt_addr; + int i, retry = 1; + + pgt_info = kmalloc(sizeof(*pgt_info), GFP_KERNEL); + if (!pgt_info) + return NULL; + + for (i = 0; i <= retry; i++) { + virt_addr = gen_pool_dma_zalloc_align(hr_priv->mmu_pgt_pool, + mmu_prop->hop_table_size, + &phys_addr, + mmu_prop->hop_table_size); + if (virt_addr) + break; + + /* No memory in pool - get some and try again */ + virt_addr = hl_asic_dma_alloc_coherent(hdev, SZ_2M, &phys_addr, + GFP_KERNEL | __GFP_ZERO); + if (ZERO_OR_NULL_PTR(virt_addr)) + break; + + if (gen_pool_add_virt(hr_priv->mmu_pgt_pool, (unsigned long)virt_addr, + phys_addr, SZ_2M, -1)) { + hl_asic_dma_free_coherent(hdev, SZ_2M, virt_addr, phys_addr); + virt_addr = NULL; + break; + } + } + + if (ZERO_OR_NULL_PTR(virt_addr)) { + dev_err(hdev->dev, "failed to allocate page\n"); + goto pool_alloc_err; + } + + pgt_info->phys_addr = phys_addr; + pgt_info->shadow_addr = (unsigned long) NULL; + pgt_info->virt_addr = (unsigned long)virt_addr; + pgt_info->ctx = ctx; + pgt_info->num_of_ptes = 0; + hr_func->add_pgt_info(ctx, pgt_info, phys_addr); + + return pgt_info; + +pool_alloc_err: + kfree(pgt_info); + + return NULL; +} + +/** + * hl_mmu_hr_get_alloc_next_hop() - get the next HOP, allocate it if it does not exist + * @ctx: pointer to the context structure. + * @hr_priv: host resident private info structure. + * @hr_func: host resident functions. + * @mmu_prop: MMU properties. + * @curr_pte: current PTE value. + * @is_new_hop: set to true if HOP is new (caller responsibility to set it to false). + * + * @return pgt_info structure associated with the allocated HOP on success, otherwise NULL. + */ +struct pgt_info *hl_mmu_hr_get_alloc_next_hop(struct hl_ctx *ctx, + struct hl_mmu_hr_priv *hr_priv, + struct hl_hr_mmu_funcs *hr_func, + struct hl_mmu_properties *mmu_prop, + u64 curr_pte, bool *is_new_hop) +{ + u64 hop_addr = hl_mmu_get_next_hop_addr(ctx, curr_pte); + + if (hop_addr != ULLONG_MAX) + return hr_func->get_pgt_info(ctx, hop_addr); + + *is_new_hop = true; + return hl_mmu_hr_alloc_hop(ctx, hr_priv, hr_func, mmu_prop); +} + +/** + * hl_mmu_hr_get_tlb_info() - get the TLB info (info for a specific mapping) + * @ctx: pointer to the context structure. + * @virt_addr: the virt address for which to get info. + * @hops: HOPs info structure. + * @hr_func: host resident functions. + * + * @return 0 on success, otherwise non 0 error code.. + */ +int hl_mmu_hr_get_tlb_info(struct hl_ctx *ctx, u64 virt_addr, struct hl_mmu_hop_info *hops, + struct hl_hr_mmu_funcs *hr_func) +{ + /* using 6 HOPs as this is the maximum number of HOPs */ + struct pgt_info *hops_pgt_info[MMU_ARCH_6_HOPS] = { NULL }; + struct hl_device *hdev = ctx->hdev; + struct hl_mmu_properties *mmu_prop; + int rc, i, used_hops; + bool is_huge; + + rc = hr_func->get_tlb_mapping_params(hdev, &mmu_prop, hops, virt_addr, &is_huge); + if (rc) + return rc; + + used_hops = mmu_prop->num_hops; + + /* huge pages use one less hop */ + if (is_huge) + used_hops--; + + hops->scrambled_vaddr = hdev->asic_funcs->scramble_addr(hdev, virt_addr); + + for (i = 0 ; i < used_hops ; i++) { + if (i == 0) + hops_pgt_info[i] = hr_func->get_hop0_pgt_info(ctx); + else + hops_pgt_info[i] = hl_mmu_hr_get_next_hop_pgt_info(ctx, hr_func, + hops->hop_info[i - 1].hop_pte_val); + + if (!hops_pgt_info[i]) + return -EFAULT; + + hops->hop_info[i].hop_addr = hops_pgt_info[i]->phys_addr; + hops->hop_info[i].hop_pte_addr = + hl_mmu_get_hop_pte_phys_addr(ctx, mmu_prop, i, + hops->hop_info[i].hop_addr, + hops->scrambled_vaddr); + hops->hop_info[i].hop_pte_val = *(u64 *) (uintptr_t) + hl_mmu_hr_pte_phys_to_virt(ctx, hops_pgt_info[i], + hops->hop_info[i].hop_pte_addr, + mmu_prop->hop_table_size); + + if (!(hops->hop_info[i].hop_pte_val & PAGE_PRESENT_MASK)) + return -EFAULT; + + if (hops->hop_info[i].hop_pte_val & mmu_prop->last_mask) + break; + } + + /* if passed over all hops then no last hop was found */ + if (i == mmu_prop->num_hops) + return -EFAULT; + + if (hops->scrambled_vaddr != virt_addr) + hops->unscrambled_paddr = hdev->asic_funcs->descramble_addr + (hdev, hops->hop_info[i].hop_pte_val); + else + hops->unscrambled_paddr = hops->hop_info[i].hop_pte_val; + + hops->used_hops = i + 1; + + return 0; +} + diff --git a/drivers/misc/habanalabs/common/mmu/mmu_v1.c b/drivers/misc/habanalabs/common/mmu/mmu_v1.c index e2d91a69acc2..8a40de4a4761 100644 --- a/drivers/misc/habanalabs/common/mmu/mmu_v1.c +++ b/drivers/misc/habanalabs/common/mmu/mmu_v1.c @@ -393,9 +393,8 @@ static int hl_mmu_v1_init(struct hl_device *hdev) goto err_pool_add; } - hdev->mmu_priv.dr.mmu_shadow_hop0 = kvmalloc_array(prop->max_asid, - prop->mmu_hop_table_size, - GFP_KERNEL | __GFP_ZERO); + hdev->mmu_priv.dr.mmu_shadow_hop0 = kvcalloc(prop->max_asid, prop->mmu_hop_table_size, + GFP_KERNEL); if (ZERO_OR_NULL_PTR(hdev->mmu_priv.dr.mmu_shadow_hop0)) { rc = -ENOMEM; goto err_pool_add; @@ -412,7 +411,7 @@ err_pool_add: } /** - * hl_mmu_fini() - release the MMU module. + * hl_mmu_v1_fini() - release the MMU module. * @hdev: habanalabs device structure. * * This function does the following: @@ -438,7 +437,7 @@ static void hl_mmu_v1_fini(struct hl_device *hdev) } /** - * hl_mmu_ctx_init() - initialize a context for using the MMU module. + * hl_mmu_v1_ctx_init() - initialize a context for using the MMU module. * @ctx: pointer to the context structure to initialize. * * Initialize a mutex to protect the concurrent mapping flow, a hash to hold all diff --git a/drivers/misc/habanalabs/common/mmu/mmu_v2_hr.c b/drivers/misc/habanalabs/common/mmu/mmu_v2_hr.c new file mode 100644 index 000000000000..afe7ef964f82 --- /dev/null +++ b/drivers/misc/habanalabs/common/mmu/mmu_v2_hr.c @@ -0,0 +1,399 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2020-2022 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "../habanalabs.h" +#include "../../include/hw_ip/mmu/mmu_general.h" + +#include + +static struct pgt_info *hl_mmu_v2_hr_get_pgt_info(struct hl_ctx *ctx, u64 phys_hop_addr) +{ + struct pgt_info *pgt_info = NULL; + + hash_for_each_possible(ctx->hr_mmu_phys_hash, pgt_info, node, + (unsigned long) phys_hop_addr) + if (phys_hop_addr == pgt_info->phys_addr) + break; + + return pgt_info; +} + +static void hl_mmu_v2_hr_add_pgt_info(struct hl_ctx *ctx, struct pgt_info *pgt_info, + dma_addr_t phys_addr) +{ + hash_add(ctx->hr_mmu_phys_hash, &pgt_info->node, phys_addr); +} + +static struct pgt_info *hl_mmu_v2_hr_get_hop0_pgt_info(struct hl_ctx *ctx) +{ + return &ctx->hdev->mmu_priv.hr.mmu_asid_hop0[ctx->asid]; +} + +/** + * hl_mmu_v2_hr_init() - initialize the MMU module. + * @hdev: habanalabs device structure. + * + * This function does the following: + * - Create a pool of pages for pgt_infos. + * - Create a shadow table for pgt + * + * Return: 0 for success, non-zero for failure. + */ +static inline int hl_mmu_v2_hr_init(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + + return hl_mmu_hr_init(hdev, &hdev->mmu_priv.hr, prop->mmu_hop_table_size, + prop->mmu_pgt_size); +} + +/** + * hl_mmu_v2_hr_fini() - release the MMU module. + * @hdev: habanalabs device structure. + * + * This function does the following: + * - Disable MMU in H/W. + * - Free the pgt_infos pool. + * + * All contexts should be freed before calling this function. + */ +static inline void hl_mmu_v2_hr_fini(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + + hl_mmu_hr_fini(hdev, &hdev->mmu_priv.hr, prop->mmu_hop_table_size); +} + +/** + * hl_mmu_v2_hr_ctx_init() - initialize a context for using the MMU module. + * @ctx: pointer to the context structure to initialize. + * + * Initialize a mutex to protect the concurrent mapping flow, a hash to hold all + * page tables hops related to this context. + * Return: 0 on success, non-zero otherwise. + */ +static int hl_mmu_v2_hr_ctx_init(struct hl_ctx *ctx) +{ + hash_init(ctx->hr_mmu_phys_hash); + return 0; +} + +/* + * hl_mmu_v2_hr_ctx_fini - disable a ctx from using the mmu module + * + * @ctx: pointer to the context structure + * + * This function does the following: + * - Free any pgts which were not freed yet + * - Free the mutex + * - Free DRAM default page mapping hops + */ +static void hl_mmu_v2_hr_ctx_fini(struct hl_ctx *ctx) +{ + struct hl_device *hdev = ctx->hdev; + struct pgt_info *pgt_info; + struct hlist_node *tmp; + int i; + + if (!hash_empty(ctx->hr_mmu_phys_hash)) + dev_err(hdev->dev, "ctx %d is freed while it has pgts in use\n", + ctx->asid); + + hash_for_each_safe(ctx->hr_mmu_phys_hash, i, tmp, pgt_info, node) { + dev_err_ratelimited(hdev->dev, + "pgt_info of addr 0x%llx of asid %d was not destroyed, num_ptes: %d\n", + pgt_info->phys_addr, ctx->asid, pgt_info->num_of_ptes); + hl_mmu_hr_free_hop_remove_pgt(pgt_info, &ctx->hdev->mmu_priv.hr, + ctx->hdev->asic_prop.mmu_hop_table_size); + } +} + +static int _hl_mmu_v2_hr_unmap(struct hl_ctx *ctx, + u64 virt_addr, bool is_dram_addr) +{ + u64 curr_pte, scrambled_virt_addr, hop_pte_phys_addr[MMU_ARCH_6_HOPS] = { 0 }; + struct pgt_info *hops_pgt_info[MMU_ARCH_6_HOPS] = { NULL }; + struct hl_device *hdev = ctx->hdev; + struct asic_fixed_properties *prop; + struct hl_mmu_properties *mmu_prop; + bool is_huge = false; + int i, hop_last; + + prop = &hdev->asic_prop; + + /* shifts and masks are the same in PMMU and HMMU, use one of them */ + mmu_prop = is_dram_addr ? &prop->dmmu : &prop->pmmu; + hop_last = mmu_prop->num_hops - 1; + + scrambled_virt_addr = hdev->asic_funcs->scramble_addr(hdev, virt_addr); + curr_pte = 0; + + for (i = 0 ; i < mmu_prop->num_hops ; i++) { + /* we get HOP0 differently, it doesn't need curr_pte */ + if (i == 0) + hops_pgt_info[i] = hl_mmu_v2_hr_get_hop0_pgt_info(ctx); + else + hops_pgt_info[i] = hl_mmu_hr_get_next_hop_pgt_info(ctx, + &ctx->hdev->mmu_func[MMU_HR_PGT].hr_funcs, curr_pte); + if (!hops_pgt_info[i]) + goto not_mapped; + + hop_pte_phys_addr[i] = hl_mmu_get_hop_pte_phys_addr(ctx, mmu_prop, i, + hops_pgt_info[i]->phys_addr, + scrambled_virt_addr); + if (hop_pte_phys_addr[i] == U64_MAX) + return -EFAULT; + + curr_pte = *(u64 *) (uintptr_t) hl_mmu_hr_pte_phys_to_virt(ctx, hops_pgt_info[i], + hop_pte_phys_addr[i], + ctx->hdev->asic_prop.mmu_hop_table_size); + + if ((i < hop_last) && (curr_pte & mmu_prop->last_mask)) { + hop_last = i; + is_huge = true; + break; + } + } + + if (is_dram_addr && !is_huge) { + dev_err(hdev->dev, "DRAM unmapping should use huge pages only\n"); + return -EFAULT; + } + + if (!(curr_pte & PAGE_PRESENT_MASK)) + goto not_mapped; + + for (i = hop_last ; i > 0 ; i--) { + hl_mmu_hr_clear_pte(ctx, hops_pgt_info[i], hop_pte_phys_addr[i], + ctx->hdev->asic_prop.mmu_hop_table_size); + + if (hl_mmu_hr_put_pte(ctx, hops_pgt_info[i], &ctx->hdev->mmu_priv.hr, + ctx->hdev->asic_prop.mmu_hop_table_size)) + goto mapped; + } + hl_mmu_hr_clear_pte(ctx, hops_pgt_info[0], hop_pte_phys_addr[0], + ctx->hdev->asic_prop.mmu_hop_table_size); + +mapped: + return 0; + +not_mapped: + dev_err(hdev->dev, "virt addr 0x%llx is not mapped to phys addr\n", virt_addr); + + return -EINVAL; +} + +static int hl_mmu_v2_get_last_hop(struct hl_mmu_properties *mmu_prop, u32 page_size) +{ + int hop; + + for (hop = (mmu_prop->num_hops - 1); hop; hop--) { + if (mmu_prop->hop_shifts[hop] == 0) + continue; + + if (page_size <= (1 << mmu_prop->hop_shifts[hop])) + break; + } + + return hop; +} + +static int _hl_mmu_v2_hr_map(struct hl_ctx *ctx, + u64 virt_addr, u64 phys_addr, + u32 page_size, bool is_dram_addr) +{ + u64 hop_pte_phys_addr[MMU_ARCH_6_HOPS] = { 0 }, + curr_pte = 0, scrambled_virt_addr, scrambled_phys_addr; + struct pgt_info *hops_pgt_info[MMU_ARCH_6_HOPS] = { NULL }; + bool hop_new[MMU_ARCH_6_HOPS] = { false }; + struct hl_device *hdev = ctx->hdev; + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct hl_mmu_properties *mmu_prop; + int i, hop_last, rc = -ENOMEM; + + /* + * This mapping function can map a page or a huge page. For huge page + * there are only 4 hops rather than 5. Currently the DRAM allocation + * uses huge pages only but user memory could have been allocated with + * one of the two page sizes. Since this is a common code for all the + * three cases, we need this hugs page check. + */ + if (is_dram_addr) + mmu_prop = &prop->dmmu; + else if (page_size == prop->pmmu_huge.page_size) + mmu_prop = &prop->pmmu_huge; + else + mmu_prop = &prop->pmmu; + + hop_last = hl_mmu_v2_get_last_hop(mmu_prop, page_size); + if (hop_last <= 0) { + dev_err(ctx->hdev->dev, "Invalid last HOP %d\n", hop_last); + return -EFAULT; + } + + scrambled_virt_addr = hdev->asic_funcs->scramble_addr(hdev, virt_addr); + scrambled_phys_addr = hdev->asic_funcs->scramble_addr(hdev, phys_addr); + + for (i = 0 ; i <= hop_last ; i++) { + + if (i == 0) + hops_pgt_info[i] = hl_mmu_v2_hr_get_hop0_pgt_info(ctx); + else + hops_pgt_info[i] = hl_mmu_hr_get_alloc_next_hop(ctx, + &ctx->hdev->mmu_priv.hr, + &ctx->hdev->mmu_func[MMU_HR_PGT].hr_funcs, + mmu_prop, curr_pte, &hop_new[i]); + if (!hops_pgt_info[i]) + goto err; + + hop_pte_phys_addr[i] = hl_mmu_get_hop_pte_phys_addr(ctx, mmu_prop, i, + hops_pgt_info[i]->phys_addr, + scrambled_virt_addr); + curr_pte = *(u64 *) (uintptr_t) hl_mmu_hr_pte_phys_to_virt(ctx, hops_pgt_info[i], + hop_pte_phys_addr[i], + ctx->hdev->asic_prop.mmu_hop_table_size); + } + + if (curr_pte & PAGE_PRESENT_MASK) { + dev_err(hdev->dev, "mapping already exists for virt_addr 0x%llx\n", + scrambled_virt_addr); + + for (i = 0 ; i <= hop_last ; i++) + dev_dbg(hdev->dev, "hop%d pte: 0x%llx (0x%llx)\n", + i, + *(u64 *) (uintptr_t) + hl_mmu_hr_pte_phys_to_virt(ctx, hops_pgt_info[i], + hop_pte_phys_addr[i], + ctx->hdev->asic_prop.mmu_hop_table_size), + hop_pte_phys_addr[i]); + rc = -EINVAL; + goto err; + } + + curr_pte = (scrambled_phys_addr & HOP_PHYS_ADDR_MASK) | mmu_prop->last_mask + | PAGE_PRESENT_MASK; + + /* Write the PTEs */ + hl_mmu_hr_write_pte(ctx, hops_pgt_info[hop_last], hop_pte_phys_addr[hop_last], curr_pte, + ctx->hdev->asic_prop.mmu_hop_table_size); + + /* for each new hop, add its address to the table of previous-hop */ + for (i = 1 ; i <= hop_last ; i++) { + if (hop_new[i]) { + curr_pte = (hops_pgt_info[i]->phys_addr & HOP_PHYS_ADDR_MASK) | + PAGE_PRESENT_MASK; + hl_mmu_hr_write_pte(ctx, hops_pgt_info[i - 1], hop_pte_phys_addr[i - 1], + curr_pte, ctx->hdev->asic_prop.mmu_hop_table_size); + if (i - 1) + hl_mmu_hr_get_pte(ctx, &ctx->hdev->mmu_func[MMU_HR_PGT].hr_funcs, + hops_pgt_info[i - 1]->phys_addr); + } + } + + hl_mmu_hr_get_pte(ctx, &ctx->hdev->mmu_func[MMU_HR_PGT].hr_funcs, + hops_pgt_info[hop_last]->phys_addr); + + return 0; + +err: + for (i = 1 ; i <= hop_last ; i++) + if (hop_new[i] && hops_pgt_info[i]) + hl_mmu_hr_free_hop_remove_pgt(hops_pgt_info[i], &ctx->hdev->mmu_priv.hr, + ctx->hdev->asic_prop.mmu_hop_table_size); + + return rc; +} + +/* + * hl_mmu_v2_swap_out - marks all mapping of the given ctx as swapped out + * + * @ctx: pointer to the context structure + * + */ +static void hl_mmu_v2_hr_swap_out(struct hl_ctx *ctx) +{ + +} + +/* + * hl_mmu_v2_swap_in - marks all mapping of the given ctx as swapped in + * + * @ctx: pointer to the context structure + * + */ +static void hl_mmu_v2_hr_swap_in(struct hl_ctx *ctx) +{ + +} + +static int hl_mmu_v2_hr_get_tlb_mapping_params(struct hl_device *hdev, + struct hl_mmu_properties **mmu_prop, + struct hl_mmu_hop_info *hops, + u64 virt_addr, bool *is_huge) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + bool is_dram_addr, is_pmmu_addr, is_pmmu_h_addr; + + is_dram_addr = hl_mem_area_inside_range(virt_addr, prop->dmmu.page_size, + prop->dmmu.start_addr, + prop->dmmu.end_addr); + is_pmmu_addr = hl_mem_area_inside_range(virt_addr, prop->pmmu.page_size, + prop->pmmu.start_addr, + prop->pmmu.end_addr); + is_pmmu_h_addr = hl_mem_area_inside_range(virt_addr, + prop->pmmu_huge.page_size, + prop->pmmu_huge.start_addr, + prop->pmmu_huge.end_addr); + if (is_dram_addr) { + *mmu_prop = &prop->dmmu; + *is_huge = true; + hops->range_type = HL_VA_RANGE_TYPE_DRAM; + } else if (is_pmmu_addr) { + *mmu_prop = &prop->pmmu; + *is_huge = false; + hops->range_type = HL_VA_RANGE_TYPE_HOST; + } else if (is_pmmu_h_addr) { + *mmu_prop = &prop->pmmu_huge; + *is_huge = true; + hops->range_type = HL_VA_RANGE_TYPE_HOST_HUGE; + } else { + return -EINVAL; + } + + return 0; +} + +static int hl_mmu_v2_hr_get_tlb_info(struct hl_ctx *ctx, u64 virt_addr, + struct hl_mmu_hop_info *hops) +{ + return hl_mmu_hr_get_tlb_info(ctx, virt_addr, hops, + &ctx->hdev->mmu_func[MMU_HR_PGT].hr_funcs); +} + +/* + * hl_mmu_v2_prepare - prepare mmu_if for working with mmu v2 + * + * @hdev: pointer to the device structure + * @mmu_if: pointer to the mmu interface structure + */ +void hl_mmu_v2_hr_set_funcs(struct hl_device *hdev, struct hl_mmu_funcs *mmu) +{ + mmu->init = hl_mmu_v2_hr_init; + mmu->fini = hl_mmu_v2_hr_fini; + mmu->ctx_init = hl_mmu_v2_hr_ctx_init; + mmu->ctx_fini = hl_mmu_v2_hr_ctx_fini; + mmu->map = _hl_mmu_v2_hr_map; + mmu->unmap = _hl_mmu_v2_hr_unmap; + mmu->flush = hl_mmu_hr_flush; + mmu->swap_out = hl_mmu_v2_hr_swap_out; + mmu->swap_in = hl_mmu_v2_hr_swap_in; + mmu->get_tlb_info = hl_mmu_v2_hr_get_tlb_info; + mmu->hr_funcs.get_hop0_pgt_info = hl_mmu_v2_hr_get_hop0_pgt_info; + mmu->hr_funcs.get_pgt_info = hl_mmu_v2_hr_get_pgt_info; + mmu->hr_funcs.add_pgt_info = hl_mmu_v2_hr_add_pgt_info; + mmu->hr_funcs.get_tlb_mapping_params = hl_mmu_v2_hr_get_tlb_mapping_params; +} diff --git a/drivers/misc/habanalabs/common/pci/pci.c b/drivers/misc/habanalabs/common/pci/pci.c index 610acd4a8057..5fe3da5fba30 100644 --- a/drivers/misc/habanalabs/common/pci/pci.c +++ b/drivers/misc/habanalabs/common/pci/pci.c @@ -224,27 +224,6 @@ int hl_pci_iatu_write(struct hl_device *hdev, u32 addr, u32 data) return 0; } -/** - * hl_pci_reset_link_through_bridge() - Reset PCI link. - * @hdev: Pointer to hl_device structure. - */ -static void hl_pci_reset_link_through_bridge(struct hl_device *hdev) -{ - struct pci_dev *pdev = hdev->pdev; - struct pci_dev *parent_port; - u16 val; - - parent_port = pdev->bus->self; - pci_read_config_word(parent_port, PCI_BRIDGE_CONTROL, &val); - val |= PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config_word(parent_port, PCI_BRIDGE_CONTROL, val); - ssleep(1); - - val &= ~(PCI_BRIDGE_CTL_BUS_RESET); - pci_write_config_word(parent_port, PCI_BRIDGE_CONTROL, val); - ssleep(3); -} - /** * hl_pci_set_inbound_region() - Configure inbound region * @hdev: Pointer to hl_device structure. @@ -280,21 +259,19 @@ int hl_pci_set_inbound_region(struct hl_device *hdev, u8 region, } /* Point to the specified address */ - rc |= hl_pci_iatu_write(hdev, offset + 0x14, - lower_32_bits(pci_region->addr)); - rc |= hl_pci_iatu_write(hdev, offset + 0x18, - upper_32_bits(pci_region->addr)); + rc |= hl_pci_iatu_write(hdev, offset + 0x14, lower_32_bits(pci_region->addr)); + rc |= hl_pci_iatu_write(hdev, offset + 0x18, upper_32_bits(pci_region->addr)); + + /* Set bar type as memory */ rc |= hl_pci_iatu_write(hdev, offset + 0x0, 0); /* Enable + bar/address match + match enable + bar number */ ctrl_reg_val = FIELD_PREP(IATU_REGION_CTRL_REGION_EN_MASK, 1); - ctrl_reg_val |= FIELD_PREP(IATU_REGION_CTRL_MATCH_MODE_MASK, - pci_region->mode); + ctrl_reg_val |= FIELD_PREP(IATU_REGION_CTRL_MATCH_MODE_MASK, pci_region->mode); ctrl_reg_val |= FIELD_PREP(IATU_REGION_CTRL_NUM_MATCH_EN_MASK, 1); if (pci_region->mode == PCI_BAR_MATCH_MODE) - ctrl_reg_val |= FIELD_PREP(IATU_REGION_CTRL_BAR_NUM_MASK, - pci_region->bar); + ctrl_reg_val |= FIELD_PREP(IATU_REGION_CTRL_BAR_NUM_MASK, pci_region->bar); rc |= hl_pci_iatu_write(hdev, offset + 0x4, ctrl_reg_val); @@ -396,9 +373,6 @@ int hl_pci_init(struct hl_device *hdev) struct pci_dev *pdev = hdev->pdev; int rc; - if (hdev->reset_pcilink) - hl_pci_reset_link_through_bridge(hdev); - rc = pci_enable_device_mem(pdev); if (rc) { dev_err(hdev->dev, "can't enable PCI device\n"); @@ -445,7 +419,7 @@ disable_device: } /** - * hl_fw_fini() - PCI finalization code. + * hl_pci_fini() - PCI finalization code. * @hdev: Pointer to hl_device structure * * Unmap PCI bars and disable PCI device. diff --git a/drivers/misc/habanalabs/common/security.c b/drivers/misc/habanalabs/common/security.c new file mode 100644 index 000000000000..6196c0487c8b --- /dev/null +++ b/drivers/misc/habanalabs/common/security.c @@ -0,0 +1,600 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2020 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "habanalabs.h" + +/** + * hl_get_pb_block - return the relevant block within the block array + * + * @hdev: pointer to hl_device structure + * @mm_reg_addr: register address in the desired block + * @pb_blocks: blocks array + * @array_size: blocks array size + * + */ +static int hl_get_pb_block(struct hl_device *hdev, u32 mm_reg_addr, + const u32 pb_blocks[], int array_size) +{ + int i; + u32 start_addr, end_addr; + + for (i = 0 ; i < array_size ; i++) { + start_addr = pb_blocks[i]; + end_addr = start_addr + HL_BLOCK_SIZE; + + if ((mm_reg_addr >= start_addr) && (mm_reg_addr < end_addr)) + return i; + } + + dev_err(hdev->dev, "No protection domain was found for 0x%x\n", + mm_reg_addr); + return -EDOM; +} + +/** + * hl_unset_pb_in_block - clear a specific protection bit in a block + * + * @hdev: pointer to hl_device structure + * @reg_offset: register offset will be converted to bit offset in pb block + * @sgs_entry: pb array + * + */ +static int hl_unset_pb_in_block(struct hl_device *hdev, u32 reg_offset, + struct hl_block_glbl_sec *sgs_entry) +{ + if ((reg_offset >= HL_BLOCK_SIZE) || (reg_offset & 0x3)) { + dev_err(hdev->dev, + "Register offset(%d) is out of range(%d) or invalid\n", + reg_offset, HL_BLOCK_SIZE); + return -EINVAL; + } + + UNSET_GLBL_SEC_BIT(sgs_entry->sec_array, + (reg_offset & (HL_BLOCK_SIZE - 1)) >> 2); + + return 0; +} + +/** + * hl_unsecure_register - locate the relevant block for this register and + * remove corresponding protection bit + * + * @hdev: pointer to hl_device structure + * @mm_reg_addr: register address to unsecure + * @offset: additional offset to the register address + * @pb_blocks: blocks array + * @sgs_array: pb array + * @array_size: blocks array size + * + */ +int hl_unsecure_register(struct hl_device *hdev, u32 mm_reg_addr, int offset, + const u32 pb_blocks[], struct hl_block_glbl_sec sgs_array[], + int array_size) +{ + u32 reg_offset; + int block_num; + + block_num = hl_get_pb_block(hdev, mm_reg_addr + offset, pb_blocks, + array_size); + if (block_num < 0) + return block_num; + + reg_offset = (mm_reg_addr + offset) - pb_blocks[block_num]; + + return hl_unset_pb_in_block(hdev, reg_offset, &sgs_array[block_num]); +} + +/** + * hl_unsecure_register_range - locate the relevant block for this register + * range and remove corresponding protection bit + * + * @hdev: pointer to hl_device structure + * @mm_reg_range: register address range to unsecure + * @offset: additional offset to the register address + * @pb_blocks: blocks array + * @sgs_array: pb array + * @array_size: blocks array size + * + */ +static int hl_unsecure_register_range(struct hl_device *hdev, + struct range mm_reg_range, int offset, const u32 pb_blocks[], + struct hl_block_glbl_sec sgs_array[], + int array_size) +{ + u32 reg_offset; + int i, block_num, rc = 0; + + block_num = hl_get_pb_block(hdev, + mm_reg_range.start + offset, pb_blocks, + array_size); + if (block_num < 0) + return block_num; + + for (i = mm_reg_range.start ; i <= mm_reg_range.end ; i += 4) { + reg_offset = (i + offset) - pb_blocks[block_num]; + rc |= hl_unset_pb_in_block(hdev, reg_offset, + &sgs_array[block_num]); + } + + return rc; +} + +/** + * hl_unsecure_registers - locate the relevant block for all registers and + * remove corresponding protection bit + * + * @hdev: pointer to hl_device structure + * @mm_reg_array: register address array to unsecure + * @mm_array_size: register array size + * @offset: additional offset to the register address + * @pb_blocks: blocks array + * @sgs_array: pb array + * @blocks_array_size: blocks array size + * + */ +int hl_unsecure_registers(struct hl_device *hdev, const u32 mm_reg_array[], + int mm_array_size, int offset, const u32 pb_blocks[], + struct hl_block_glbl_sec sgs_array[], int blocks_array_size) +{ + int i, rc = 0; + + for (i = 0 ; i < mm_array_size ; i++) { + rc = hl_unsecure_register(hdev, mm_reg_array[i], offset, + pb_blocks, sgs_array, blocks_array_size); + + if (rc) + return rc; + } + + return rc; +} + +/** + * hl_unsecure_registers_range - locate the relevant block for all register + * ranges and remove corresponding protection bit + * + * @hdev: pointer to hl_device structure + * @mm_reg_range_array: register address range array to unsecure + * @mm_array_size: register array size + * @offset: additional offset to the register address + * @pb_blocks: blocks array + * @sgs_array: pb array + * @blocks_array_size: blocks array size + * + */ +static int hl_unsecure_registers_range(struct hl_device *hdev, + const struct range mm_reg_range_array[], int mm_array_size, + int offset, const u32 pb_blocks[], + struct hl_block_glbl_sec sgs_array[], int blocks_array_size) +{ + int i, rc = 0; + + for (i = 0 ; i < mm_array_size ; i++) { + rc = hl_unsecure_register_range(hdev, mm_reg_range_array[i], + offset, pb_blocks, sgs_array, blocks_array_size); + + if (rc) + return rc; + } + + return rc; +} + +/** + * hl_ack_pb_security_violations - Ack security violation + * + * @hdev: pointer to hl_device structure + * @pb_blocks: blocks array + * @block_offset: additional offset to the block + * @array_size: blocks array size + * + */ +static void hl_ack_pb_security_violations(struct hl_device *hdev, + const u32 pb_blocks[], u32 block_offset, int array_size) +{ + int i; + u32 cause, addr, block_base; + + for (i = 0 ; i < array_size ; i++) { + block_base = pb_blocks[i] + block_offset; + cause = RREG32(block_base + HL_BLOCK_GLBL_ERR_CAUSE); + if (cause) { + addr = RREG32(block_base + HL_BLOCK_GLBL_ERR_ADDR); + hdev->asic_funcs->pb_print_security_errors(hdev, + block_base, cause, addr); + WREG32(block_base + HL_BLOCK_GLBL_ERR_CAUSE, cause); + } + } +} + +/** + * hl_config_glbl_sec - set pb in HW according to given pb array + * + * @hdev: pointer to hl_device structure + * @pb_blocks: blocks array + * @sgs_array: pb array + * @block_offset: additional offset to the block + * @array_size: blocks array size + * + */ +void hl_config_glbl_sec(struct hl_device *hdev, const u32 pb_blocks[], + struct hl_block_glbl_sec sgs_array[], u32 block_offset, + int array_size) +{ + int i, j; + u32 sgs_base; + + if (hdev->pldm) + usleep_range(100, 1000); + + for (i = 0 ; i < array_size ; i++) { + sgs_base = block_offset + pb_blocks[i] + + HL_BLOCK_GLBL_SEC_OFFS; + + for (j = 0 ; j < HL_BLOCK_GLBL_SEC_LEN ; j++) + WREG32(sgs_base + j * sizeof(u32), + sgs_array[i].sec_array[j]); + } +} + +/** + * hl_secure_block - locally memsets a block to 0 + * + * @hdev: pointer to hl_device structure + * @sgs_array: pb array to clear + * @array_size: blocks array size + * + */ +void hl_secure_block(struct hl_device *hdev, + struct hl_block_glbl_sec sgs_array[], int array_size) +{ + int i; + + for (i = 0 ; i < array_size ; i++) + memset((char *)(sgs_array[i].sec_array), 0, + HL_BLOCK_GLBL_SEC_SIZE); +} + +/** + * hl_init_pb_with_mask - set selected pb instances with mask in HW according + * to given configuration + * + * @hdev: pointer to hl_device structure + * @num_dcores: number of decores to apply configuration to + * set to HL_PB_SHARED if need to apply only once + * @dcore_offset: offset between dcores + * @num_instances: number of instances to apply configuration to + * @instance_offset: offset between instances + * @pb_blocks: blocks array + * @blocks_array_size: blocks array size + * @regs_array: register array + * @regs_array_size: register array size + * @mask: enabled instances mask: 1- enabled, 0- disabled + */ +int hl_init_pb_with_mask(struct hl_device *hdev, u32 num_dcores, + u32 dcore_offset, u32 num_instances, u32 instance_offset, + const u32 pb_blocks[], u32 blocks_array_size, + const u32 *regs_array, u32 regs_array_size, u64 mask) +{ + int i, j; + struct hl_block_glbl_sec *glbl_sec; + + glbl_sec = kcalloc(blocks_array_size, + sizeof(struct hl_block_glbl_sec), + GFP_KERNEL); + if (!glbl_sec) + return -ENOMEM; + + hl_secure_block(hdev, glbl_sec, blocks_array_size); + hl_unsecure_registers(hdev, regs_array, regs_array_size, 0, pb_blocks, + glbl_sec, blocks_array_size); + + /* Fill all blocks with the same configuration */ + for (i = 0 ; i < num_dcores ; i++) { + for (j = 0 ; j < num_instances ; j++) { + int seq = i * num_instances + j; + + if (!(mask & BIT_ULL(seq))) + continue; + + hl_config_glbl_sec(hdev, pb_blocks, glbl_sec, + i * dcore_offset + j * instance_offset, + blocks_array_size); + } + } + + kfree(glbl_sec); + + return 0; +} + +/** + * hl_init_pb - set pb in HW according to given configuration + * + * @hdev: pointer to hl_device structure + * @num_dcores: number of decores to apply configuration to + * set to HL_PB_SHARED if need to apply only once + * @dcore_offset: offset between dcores + * @num_instances: number of instances to apply configuration to + * @instance_offset: offset between instances + * @pb_blocks: blocks array + * @blocks_array_size: blocks array size + * @regs_array: register array + * @regs_array_size: register array size + * + */ +int hl_init_pb(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset, + u32 num_instances, u32 instance_offset, + const u32 pb_blocks[], u32 blocks_array_size, + const u32 *regs_array, u32 regs_array_size) +{ + return hl_init_pb_with_mask(hdev, num_dcores, dcore_offset, + num_instances, instance_offset, pb_blocks, + blocks_array_size, regs_array, regs_array_size, + ULLONG_MAX); +} + +/** + * hl_init_pb_ranges_with_mask - set pb instances using mask in HW according to + * given configuration unsecurring registers + * ranges instead of specific registers + * + * @hdev: pointer to hl_device structure + * @num_dcores: number of decores to apply configuration to + * set to HL_PB_SHARED if need to apply only once + * @dcore_offset: offset between dcores + * @num_instances: number of instances to apply configuration to + * @instance_offset: offset between instances + * @pb_blocks: blocks array + * @blocks_array_size: blocks array size + * @regs_range_array: register range array + * @regs_range_array_size: register range array size + * @mask: enabled instances mask: 1- enabled, 0- disabled + */ +int hl_init_pb_ranges_with_mask(struct hl_device *hdev, u32 num_dcores, + u32 dcore_offset, u32 num_instances, u32 instance_offset, + const u32 pb_blocks[], u32 blocks_array_size, + const struct range *regs_range_array, u32 regs_range_array_size, + u64 mask) +{ + int i, j, rc = 0; + struct hl_block_glbl_sec *glbl_sec; + + glbl_sec = kcalloc(blocks_array_size, + sizeof(struct hl_block_glbl_sec), + GFP_KERNEL); + if (!glbl_sec) + return -ENOMEM; + + hl_secure_block(hdev, glbl_sec, blocks_array_size); + rc = hl_unsecure_registers_range(hdev, regs_range_array, + regs_range_array_size, 0, pb_blocks, glbl_sec, + blocks_array_size); + if (rc) + goto free_glbl_sec; + + /* Fill all blocks with the same configuration */ + for (i = 0 ; i < num_dcores ; i++) { + for (j = 0 ; j < num_instances ; j++) { + int seq = i * num_instances + j; + + if (!(mask & BIT_ULL(seq))) + continue; + + hl_config_glbl_sec(hdev, pb_blocks, glbl_sec, + i * dcore_offset + j * instance_offset, + blocks_array_size); + } + } + +free_glbl_sec: + kfree(glbl_sec); + + return rc; +} + +/** + * hl_init_pb_ranges - set pb in HW according to given configuration unsecurring + * registers ranges instead of specific registers + * + * @hdev: pointer to hl_device structure + * @num_dcores: number of decores to apply configuration to + * set to HL_PB_SHARED if need to apply only once + * @dcore_offset: offset between dcores + * @num_instances: number of instances to apply configuration to + * @instance_offset: offset between instances + * @pb_blocks: blocks array + * @blocks_array_size: blocks array size + * @regs_range_array: register range array + * @regs_range_array_size: register range array size + * + */ +int hl_init_pb_ranges(struct hl_device *hdev, u32 num_dcores, + u32 dcore_offset, u32 num_instances, u32 instance_offset, + const u32 pb_blocks[], u32 blocks_array_size, + const struct range *regs_range_array, u32 regs_range_array_size) +{ + return hl_init_pb_ranges_with_mask(hdev, num_dcores, dcore_offset, + num_instances, instance_offset, pb_blocks, + blocks_array_size, regs_range_array, + regs_range_array_size, ULLONG_MAX); +} + +/** + * hl_init_pb_single_dcore - set pb for a single docre in HW + * according to given configuration + * + * @hdev: pointer to hl_device structure + * @dcore_offset: offset from the dcore0 + * @num_instances: number of instances to apply configuration to + * @instance_offset: offset between instances + * @pb_blocks: blocks array + * @blocks_array_size: blocks array size + * @regs_array: register array + * @regs_array_size: register array size + * + */ +int hl_init_pb_single_dcore(struct hl_device *hdev, u32 dcore_offset, + u32 num_instances, u32 instance_offset, + const u32 pb_blocks[], u32 blocks_array_size, + const u32 *regs_array, u32 regs_array_size) +{ + int i, rc = 0; + struct hl_block_glbl_sec *glbl_sec; + + glbl_sec = kcalloc(blocks_array_size, + sizeof(struct hl_block_glbl_sec), + GFP_KERNEL); + if (!glbl_sec) + return -ENOMEM; + + hl_secure_block(hdev, glbl_sec, blocks_array_size); + rc = hl_unsecure_registers(hdev, regs_array, regs_array_size, 0, + pb_blocks, glbl_sec, blocks_array_size); + if (rc) + goto free_glbl_sec; + + /* Fill all blocks with the same configuration */ + for (i = 0 ; i < num_instances ; i++) + hl_config_glbl_sec(hdev, pb_blocks, glbl_sec, + dcore_offset + i * instance_offset, + blocks_array_size); + +free_glbl_sec: + kfree(glbl_sec); + + return rc; +} + +/** + * hl_init_pb_ranges_single_dcore - set pb for a single docre in HW according + * to given configuration unsecurring + * registers ranges instead of specific + * registers + * + * @hdev: pointer to hl_device structure + * @dcore_offset: offset from the dcore0 + * @num_instances: number of instances to apply configuration to + * @instance_offset: offset between instances + * @pb_blocks: blocks array + * @blocks_array_size: blocks array size + * @regs_range_array: register range array + * @regs_range_array_size: register range array size + * + */ +int hl_init_pb_ranges_single_dcore(struct hl_device *hdev, u32 dcore_offset, + u32 num_instances, u32 instance_offset, + const u32 pb_blocks[], u32 blocks_array_size, + const struct range *regs_range_array, u32 regs_range_array_size) +{ + int i; + struct hl_block_glbl_sec *glbl_sec; + + glbl_sec = kcalloc(blocks_array_size, + sizeof(struct hl_block_glbl_sec), + GFP_KERNEL); + if (!glbl_sec) + return -ENOMEM; + + hl_secure_block(hdev, glbl_sec, blocks_array_size); + hl_unsecure_registers_range(hdev, regs_range_array, + regs_range_array_size, 0, pb_blocks, glbl_sec, + blocks_array_size); + + /* Fill all blocks with the same configuration */ + for (i = 0 ; i < num_instances ; i++) + hl_config_glbl_sec(hdev, pb_blocks, glbl_sec, + dcore_offset + i * instance_offset, + blocks_array_size); + + kfree(glbl_sec); + + return 0; +} + +/** + * hl_ack_pb_with_mask - ack pb with mask in HW according to given configuration + * + * @hdev: pointer to hl_device structure + * @num_dcores: number of decores to apply configuration to + * set to HL_PB_SHARED if need to apply only once + * @dcore_offset: offset between dcores + * @num_instances: number of instances to apply configuration to + * @instance_offset: offset between instances + * @pb_blocks: blocks array + * @blocks_array_size: blocks array size + * @mask: enabled instances mask: 1- enabled, 0- disabled + * + */ +void hl_ack_pb_with_mask(struct hl_device *hdev, u32 num_dcores, + u32 dcore_offset, u32 num_instances, u32 instance_offset, + const u32 pb_blocks[], u32 blocks_array_size, u64 mask) +{ + int i, j; + + /* ack all blocks */ + for (i = 0 ; i < num_dcores ; i++) { + for (j = 0 ; j < num_instances ; j++) { + int seq = i * num_instances + j; + + if (!(mask & BIT_ULL(seq))) + continue; + + hl_ack_pb_security_violations(hdev, pb_blocks, + i * dcore_offset + j * instance_offset, + blocks_array_size); + } + } +} + +/** + * hl_ack_pb - ack pb in HW according to given configuration + * + * @hdev: pointer to hl_device structure + * @num_dcores: number of decores to apply configuration to + * set to HL_PB_SHARED if need to apply only once + * @dcore_offset: offset between dcores + * @num_instances: number of instances to apply configuration to + * @instance_offset: offset between instances + * @pb_blocks: blocks array + * @blocks_array_size: blocks array size + * + */ +void hl_ack_pb(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset, + u32 num_instances, u32 instance_offset, + const u32 pb_blocks[], u32 blocks_array_size) +{ + hl_ack_pb_with_mask(hdev, num_dcores, dcore_offset, num_instances, + instance_offset, pb_blocks, blocks_array_size, + ULLONG_MAX); +} + +/** + * hl_ack_pb_single_dcore - ack pb for single docre in HW + * according to given configuration + * + * @hdev: pointer to hl_device structure + * @dcore_offset: offset from dcore0 + * @num_instances: number of instances to apply configuration to + * @instance_offset: offset between instances + * @pb_blocks: blocks array + * @blocks_array_size: blocks array size + * + */ +void hl_ack_pb_single_dcore(struct hl_device *hdev, u32 dcore_offset, + u32 num_instances, u32 instance_offset, + const u32 pb_blocks[], u32 blocks_array_size) +{ + int i; + + /* ack all blocks */ + for (i = 0 ; i < num_instances ; i++) + hl_ack_pb_security_violations(hdev, pb_blocks, + dcore_offset + i * instance_offset, + blocks_array_size); + +} diff --git a/drivers/misc/habanalabs/common/sysfs.c b/drivers/misc/habanalabs/common/sysfs.c index 9ebeb18ab85e..6c5271f01160 100644 --- a/drivers/misc/habanalabs/common/sysfs.c +++ b/drivers/misc/habanalabs/common/sysfs.c @@ -73,6 +73,7 @@ static DEVICE_ATTR_RO(clk_cur_freq_mhz); static struct attribute *hl_dev_clk_attrs[] = { &dev_attr_clk_max_freq_mhz.attr, &dev_attr_clk_cur_freq_mhz.attr, + NULL, }; static ssize_t vrm_ver_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -93,6 +94,7 @@ static DEVICE_ATTR_RO(vrm_ver); static struct attribute *hl_dev_vrm_attrs[] = { &dev_attr_vrm_ver.attr, + NULL, }; static ssize_t uboot_ver_show(struct device *dev, struct device_attribute *attr, @@ -243,6 +245,12 @@ static ssize_t device_type_show(struct device *dev, case ASIC_GAUDI_SEC: str = "GAUDI SEC"; break; + case ASIC_GAUDI2: + str = "GAUDI2"; + break; + case ASIC_GAUDI2_SEC: + str = "GAUDI2 SEC"; + break; default: dev_err(hdev->dev, "Unrecognized ASIC type %d\n", hdev->asic_type); @@ -283,7 +291,7 @@ static ssize_t soft_reset_cnt_show(struct device *dev, { struct hl_device *hdev = dev_get_drvdata(dev); - return sprintf(buf, "%d\n", hdev->reset_info.soft_reset_cnt); + return sprintf(buf, "%d\n", hdev->reset_info.compute_reset_cnt); } static ssize_t hard_reset_cnt_show(struct device *dev, diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c index fba322241096..cb2988e2c7a8 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi.c +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -97,15 +97,8 @@ #define GAUDI_ARB_WDT_TIMEOUT 0xEE6b27FF /* 8 seconds */ -#define GAUDI_CLK_GATE_DEBUGFS_MASK (\ - BIT(GAUDI_ENGINE_ID_MME_0) |\ - BIT(GAUDI_ENGINE_ID_MME_2) |\ - GENMASK_ULL(GAUDI_ENGINE_ID_TPC_7, GAUDI_ENGINE_ID_TPC_0)) - #define HBM_SCRUBBING_TIMEOUT_US 1000000 /* 1s */ -#define GAUDI_PLL_MAX 10 - #define BIN_REG_STRING_SIZE sizeof("0b10101010101010101010101010101010") #define MONITOR_SOB_STRING_SIZE 256 @@ -241,12 +234,6 @@ gaudi_qman_arb_error_cause[GAUDI_NUM_OF_QM_ARB_ERR_CAUSE] = { "MSG AXI LBW returned with error" }; -enum gaudi_sm_sei_cause { - GAUDI_SM_SEI_SO_OVERFLOW, - GAUDI_SM_SEI_LBW_4B_UNALIGNED, - GAUDI_SM_SEI_AXI_RESPONSE_ERR -}; - static enum hl_queue_type gaudi_queue_type[GAUDI_QUEUE_ID_SIZE] = { QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_0_0 */ QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_0_1 */ @@ -443,6 +430,38 @@ static s64 gaudi_state_dump_specs_props[] = { [SP_NUM_CORES] = 1, }; +static const int gaudi_queue_id_to_engine_id[] = { + [GAUDI_QUEUE_ID_DMA_0_0...GAUDI_QUEUE_ID_DMA_0_3] = GAUDI_ENGINE_ID_DMA_0, + [GAUDI_QUEUE_ID_DMA_1_0...GAUDI_QUEUE_ID_DMA_1_3] = GAUDI_ENGINE_ID_DMA_1, + [GAUDI_QUEUE_ID_CPU_PQ] = GAUDI_ENGINE_ID_SIZE, + [GAUDI_QUEUE_ID_DMA_2_0...GAUDI_QUEUE_ID_DMA_2_3] = GAUDI_ENGINE_ID_DMA_2, + [GAUDI_QUEUE_ID_DMA_3_0...GAUDI_QUEUE_ID_DMA_3_3] = GAUDI_ENGINE_ID_DMA_3, + [GAUDI_QUEUE_ID_DMA_4_0...GAUDI_QUEUE_ID_DMA_4_3] = GAUDI_ENGINE_ID_DMA_4, + [GAUDI_QUEUE_ID_DMA_5_0...GAUDI_QUEUE_ID_DMA_5_3] = GAUDI_ENGINE_ID_DMA_5, + [GAUDI_QUEUE_ID_DMA_6_0...GAUDI_QUEUE_ID_DMA_6_3] = GAUDI_ENGINE_ID_DMA_6, + [GAUDI_QUEUE_ID_DMA_7_0...GAUDI_QUEUE_ID_DMA_7_3] = GAUDI_ENGINE_ID_DMA_7, + [GAUDI_QUEUE_ID_MME_0_0...GAUDI_QUEUE_ID_MME_0_3] = GAUDI_ENGINE_ID_MME_0, + [GAUDI_QUEUE_ID_MME_1_0...GAUDI_QUEUE_ID_MME_1_3] = GAUDI_ENGINE_ID_MME_2, + [GAUDI_QUEUE_ID_TPC_0_0...GAUDI_QUEUE_ID_TPC_0_3] = GAUDI_ENGINE_ID_TPC_0, + [GAUDI_QUEUE_ID_TPC_1_0...GAUDI_QUEUE_ID_TPC_1_3] = GAUDI_ENGINE_ID_TPC_1, + [GAUDI_QUEUE_ID_TPC_2_0...GAUDI_QUEUE_ID_TPC_2_3] = GAUDI_ENGINE_ID_TPC_2, + [GAUDI_QUEUE_ID_TPC_3_0...GAUDI_QUEUE_ID_TPC_3_3] = GAUDI_ENGINE_ID_TPC_3, + [GAUDI_QUEUE_ID_TPC_4_0...GAUDI_QUEUE_ID_TPC_4_3] = GAUDI_ENGINE_ID_TPC_4, + [GAUDI_QUEUE_ID_TPC_5_0...GAUDI_QUEUE_ID_TPC_5_3] = GAUDI_ENGINE_ID_TPC_5, + [GAUDI_QUEUE_ID_TPC_6_0...GAUDI_QUEUE_ID_TPC_6_3] = GAUDI_ENGINE_ID_TPC_6, + [GAUDI_QUEUE_ID_TPC_7_0...GAUDI_QUEUE_ID_TPC_7_3] = GAUDI_ENGINE_ID_TPC_7, + [GAUDI_QUEUE_ID_NIC_0_0...GAUDI_QUEUE_ID_NIC_0_3] = GAUDI_ENGINE_ID_NIC_0, + [GAUDI_QUEUE_ID_NIC_1_0...GAUDI_QUEUE_ID_NIC_1_3] = GAUDI_ENGINE_ID_NIC_1, + [GAUDI_QUEUE_ID_NIC_2_0...GAUDI_QUEUE_ID_NIC_2_3] = GAUDI_ENGINE_ID_NIC_2, + [GAUDI_QUEUE_ID_NIC_3_0...GAUDI_QUEUE_ID_NIC_3_3] = GAUDI_ENGINE_ID_NIC_3, + [GAUDI_QUEUE_ID_NIC_4_0...GAUDI_QUEUE_ID_NIC_4_3] = GAUDI_ENGINE_ID_NIC_4, + [GAUDI_QUEUE_ID_NIC_5_0...GAUDI_QUEUE_ID_NIC_5_3] = GAUDI_ENGINE_ID_NIC_5, + [GAUDI_QUEUE_ID_NIC_6_0...GAUDI_QUEUE_ID_NIC_6_3] = GAUDI_ENGINE_ID_NIC_6, + [GAUDI_QUEUE_ID_NIC_7_0...GAUDI_QUEUE_ID_NIC_7_3] = GAUDI_ENGINE_ID_NIC_7, + [GAUDI_QUEUE_ID_NIC_8_0...GAUDI_QUEUE_ID_NIC_8_3] = GAUDI_ENGINE_ID_NIC_8, + [GAUDI_QUEUE_ID_NIC_9_0...GAUDI_QUEUE_ID_NIC_9_3] = GAUDI_ENGINE_ID_NIC_9, +}; + /* The order here is opposite to the order of the indexing in the h/w. * i.e. SYNC_MGR_W_S is actually 0, SYNC_MGR_E_S is 1, etc. */ @@ -556,10 +575,13 @@ static int gaudi_set_fixed_properties(struct hl_device *hdev) get_collective_mode(hdev, i); } + prop->cache_line_size = DEVICE_CACHE_LINE_SIZE; + prop->cfg_base_address = CFG_BASE; prop->device_dma_offset_for_host_access = HOST_PHYS_BASE; prop->host_base_address = HOST_PHYS_BASE; prop->host_end_address = prop->host_base_address + HOST_PHYS_SIZE; prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES; + prop->completion_mode = HL_COMPLETION_MODE_JOB; prop->collective_first_sob = 0; prop->collective_first_mon = 0; @@ -577,16 +599,17 @@ static int gaudi_set_fixed_properties(struct hl_device *hdev) prop->dram_base_address = DRAM_PHYS_BASE; prop->dram_size = GAUDI_HBM_SIZE_32GB; - prop->dram_end_address = prop->dram_base_address + - prop->dram_size; + prop->dram_end_address = prop->dram_base_address + prop->dram_size; prop->dram_user_base_address = DRAM_BASE_ADDR_USER; prop->sram_base_address = SRAM_BASE_ADDR; prop->sram_size = SRAM_SIZE; - prop->sram_end_address = prop->sram_base_address + - prop->sram_size; - prop->sram_user_base_address = prop->sram_base_address + - SRAM_USER_BASE_OFFSET; + prop->sram_end_address = prop->sram_base_address + prop->sram_size; + prop->sram_user_base_address = + prop->sram_base_address + SRAM_USER_BASE_OFFSET; + + prop->mmu_cache_mng_addr = MMU_CACHE_MNG_ADDR; + prop->mmu_cache_mng_size = MMU_CACHE_MNG_SIZE; prop->mmu_pgt_addr = MMU_PAGE_TABLES_ADDR; if (hdev->pldm) @@ -655,7 +678,7 @@ static int gaudi_set_fixed_properties(struct hl_device *hdev) prop->sync_stream_first_mon + (num_sync_stream_queues * HL_RSVD_MONS); - prop->first_available_user_msix_interrupt = USHRT_MAX; + prop->first_available_user_interrupt = USHRT_MAX; for (i = 0 ; i < HL_MAX_DCORES ; i++) prop->first_available_cq[i] = USHRT_MAX; @@ -777,6 +800,7 @@ static int gaudi_early_init(struct hl_device *hdev) { struct asic_fixed_properties *prop = &hdev->asic_prop; struct pci_dev *pdev = hdev->pdev; + resource_size_t pci_bar_size; u32 fw_boot_status; int rc; @@ -787,24 +811,20 @@ static int gaudi_early_init(struct hl_device *hdev) } /* Check BAR sizes */ - if (pci_resource_len(pdev, SRAM_BAR_ID) != SRAM_BAR_SIZE) { - dev_err(hdev->dev, - "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n", - SRAM_BAR_ID, - (unsigned long long) pci_resource_len(pdev, - SRAM_BAR_ID), - SRAM_BAR_SIZE); + pci_bar_size = pci_resource_len(pdev, SRAM_BAR_ID); + + if (pci_bar_size != SRAM_BAR_SIZE) { + dev_err(hdev->dev, "Not " HL_NAME "? BAR %d size %pa, expecting %llu\n", + SRAM_BAR_ID, &pci_bar_size, SRAM_BAR_SIZE); rc = -ENODEV; goto free_queue_props; } - if (pci_resource_len(pdev, CFG_BAR_ID) != CFG_BAR_SIZE) { - dev_err(hdev->dev, - "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n", - CFG_BAR_ID, - (unsigned long long) pci_resource_len(pdev, - CFG_BAR_ID), - CFG_BAR_SIZE); + pci_bar_size = pci_resource_len(pdev, CFG_BAR_ID); + + if (pci_bar_size != CFG_BAR_SIZE) { + dev_err(hdev->dev, "Not " HL_NAME "? BAR %d size %pa, expecting %llu\n", + CFG_BAR_ID, &pci_bar_size, CFG_BAR_SIZE); rc = -ENODEV; goto free_queue_props; } @@ -842,11 +862,7 @@ pci_init: /* Before continuing in the initialization, we need to read the preboot * version to determine whether we run with a security-enabled firmware */ - rc = hl_fw_read_preboot_status(hdev, mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS, - mmCPU_BOOT_DEV_STS0, - mmCPU_BOOT_DEV_STS1, mmCPU_BOOT_ERR0, - mmCPU_BOOT_ERR1, - GAUDI_BOOT_FIT_REQ_TIMEOUT_USEC); + rc = hl_fw_read_preboot_status(hdev); if (rc) { if (hdev->reset_on_preboot_fail) hdev->asic_funcs->hw_fini(hdev, true, false); @@ -854,8 +870,7 @@ pci_init: } if (gaudi_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) { - dev_info(hdev->dev, - "H/W state is dirty, must reset before initializing\n"); + dev_dbg(hdev->dev, "H/W state is dirty, must reset before initializing\n"); hdev->asic_funcs->hw_fini(hdev, true, false); } @@ -1046,8 +1061,7 @@ again: } fw_size = fw->size; - cpu_addr = hdev->asic_funcs->asic_dma_alloc_coherent(hdev, fw_size, - &dma_handle, GFP_KERNEL | __GFP_ZERO); + cpu_addr = hl_asic_dma_alloc_coherent(hdev, fw_size, &dma_handle, GFP_KERNEL | __GFP_ZERO); if (!cpu_addr) { dev_err(hdev->dev, "Failed to allocate %zu of dma memory for TPC kernel\n", @@ -1060,8 +1074,7 @@ again: rc = _gaudi_init_tpc_mem(hdev, dma_handle, fw_size); - hdev->asic_funcs->asic_dma_free_coherent(hdev, fw->size, cpu_addr, - dma_handle); + hl_asic_dma_free_coherent(hdev, fw->size, cpu_addr, dma_handle); out: release_firmware(fw); @@ -1391,6 +1404,19 @@ static int gaudi_collective_wait_init_cs(struct hl_cs *cs) return 0; } +static u32 gaudi_get_patched_cb_extra_size(u32 user_cb_size) +{ + u32 cacheline_end, additional_commands; + + cacheline_end = round_up(user_cb_size, DEVICE_CACHE_LINE_SIZE); + additional_commands = sizeof(struct packet_msg_prot) * 2; + + if (user_cb_size + additional_commands > cacheline_end) + return cacheline_end - user_cb_size + additional_commands; + else + return additional_commands; +} + static int gaudi_collective_wait_create_job(struct hl_device *hdev, struct hl_ctx *ctx, struct hl_cs *cs, enum hl_collective_mode mode, u32 queue_id, u32 wait_queue_id, @@ -1411,7 +1437,7 @@ static int gaudi_collective_wait_create_job(struct hl_device *hdev, * 1 fence packet * 4 msg short packets for monitor 2 configuration * 1 fence packet - * 2 msg prot packets for completion and MSI-X + * 2 msg prot packets for completion and MSI */ cb_size = sizeof(struct packet_msg_short) * 8 + sizeof(struct packet_fence) * 2 + @@ -1605,14 +1631,14 @@ static int gaudi_late_init(struct hl_device *hdev) gaudi->hw_cap_initialized &= ~(HW_CAP_NIC0 | HW_CAP_NIC1); } - rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_ENABLE_PCI_ACCESS); + rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_ENABLE_PCI_ACCESS, 0x0); if (rc) { dev_err(hdev->dev, "Failed to enable PCI access from CPU\n"); return rc; } /* Scrub both SRAM and DRAM */ - rc = hdev->asic_funcs->scrub_device_mem(hdev, 0, 0); + rc = hdev->asic_funcs->scrub_device_mem(hdev); if (rc) goto disable_pci_access; @@ -1650,7 +1676,7 @@ static int gaudi_late_init(struct hl_device *hdev) return 0; disable_pci_access: - hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS); + hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS, 0x0); return rc; } @@ -1692,11 +1718,9 @@ static int gaudi_alloc_cpu_accessible_dma_mem(struct hl_device *hdev) */ for (i = 0 ; i < GAUDI_ALLOC_CPU_MEM_RETRY_CNT ; i++) { - virt_addr_arr[i] = - hdev->asic_funcs->asic_dma_alloc_coherent(hdev, - HL_CPU_ACCESSIBLE_MEM_SIZE, - &dma_addr_arr[i], - GFP_KERNEL | __GFP_ZERO); + virt_addr_arr[i] = hl_asic_dma_alloc_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, + &dma_addr_arr[i], + GFP_KERNEL | __GFP_ZERO); if (!virt_addr_arr[i]) { rc = -ENOMEM; goto free_dma_mem_arr; @@ -1725,9 +1749,7 @@ static int gaudi_alloc_cpu_accessible_dma_mem(struct hl_device *hdev) free_dma_mem_arr: for (j = 0 ; j < i ; j++) - hdev->asic_funcs->asic_dma_free_coherent(hdev, - HL_CPU_ACCESSIBLE_MEM_SIZE, - virt_addr_arr[j], + hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, virt_addr_arr[j], dma_addr_arr[j]); return rc; @@ -1743,9 +1765,7 @@ static void gaudi_free_internal_qmans_pq_mem(struct hl_device *hdev) q = &gaudi->internal_qmans[i]; if (!q->pq_kernel_addr) continue; - hdev->asic_funcs->asic_dma_free_coherent(hdev, q->pq_size, - q->pq_kernel_addr, - q->pq_dma_addr); + hl_asic_dma_free_coherent(hdev, q->pq_size, q->pq_kernel_addr, q->pq_dma_addr); } } @@ -1780,10 +1800,8 @@ static int gaudi_alloc_internal_qmans_pq_mem(struct hl_device *hdev) goto free_internal_qmans_pq_mem; } - q->pq_kernel_addr = hdev->asic_funcs->asic_dma_alloc_coherent( - hdev, q->pq_size, - &q->pq_dma_addr, - GFP_KERNEL | __GFP_ZERO); + q->pq_kernel_addr = hl_asic_dma_alloc_coherent(hdev, q->pq_size, &q->pq_dma_addr, + GFP_KERNEL | __GFP_ZERO); if (!q->pq_kernel_addr) { rc = -ENOMEM; goto free_internal_qmans_pq_mem; @@ -1924,10 +1942,8 @@ free_cpu_dma_mem: if (!hdev->asic_prop.fw_security_enabled) GAUDI_CPU_TO_PCI_ADDR(hdev->cpu_accessible_dma_address, hdev->cpu_pci_msb_addr); - hdev->asic_funcs->asic_dma_free_coherent(hdev, - HL_CPU_ACCESSIBLE_MEM_SIZE, - hdev->cpu_accessible_dma_mem, - hdev->cpu_accessible_dma_address); + hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->cpu_accessible_dma_mem, + hdev->cpu_accessible_dma_address); free_dma_pool: dma_pool_destroy(hdev->dma_pool); free_gaudi_device: @@ -1947,10 +1963,8 @@ static int gaudi_sw_fini(struct hl_device *hdev) GAUDI_CPU_TO_PCI_ADDR(hdev->cpu_accessible_dma_address, hdev->cpu_pci_msb_addr); - hdev->asic_funcs->asic_dma_free_coherent(hdev, - HL_CPU_ACCESSIBLE_MEM_SIZE, - hdev->cpu_accessible_dma_mem, - hdev->cpu_accessible_dma_address); + hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->cpu_accessible_dma_mem, + hdev->cpu_accessible_dma_address); dma_pool_destroy(hdev->dma_pool); @@ -2139,9 +2153,6 @@ static void gaudi_init_scrambler_sram(struct hl_device *hdev) if (gaudi->hw_cap_initialized & HW_CAP_SRAM_SCRAMBLER) return; - if (!hdev->sram_scrambler_enable) - return; - WREG32(mmNIF_RTR_CTRL_0_SCRAM_SRAM_EN, 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); WREG32(mmNIF_RTR_CTRL_1_SCRAM_SRAM_EN, @@ -2210,9 +2221,6 @@ static void gaudi_init_scrambler_hbm(struct hl_device *hdev) if (gaudi->hw_cap_initialized & HW_CAP_HBM_SCRAMBLER) return; - if (!hdev->dram_scrambler_enable) - return; - WREG32(mmNIF_RTR_CTRL_0_SCRAM_HBM_EN, 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); WREG32(mmNIF_RTR_CTRL_1_SCRAM_HBM_EN, @@ -2396,128 +2404,6 @@ static void gaudi_init_e2e(struct hl_device *hdev) WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_WR_SIZE, 162); WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_RD_SIZE, 338); - if (!hdev->dram_scrambler_enable) { - WREG32(mmSIF_RTR_CTRL_0_NL_HBM_SEL_0, 0x21); - WREG32(mmSIF_RTR_CTRL_0_NL_HBM_SEL_1, 0x22); - WREG32(mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_18, 0x1F); - WREG32(mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_3, 0x20); - - WREG32(mmSIF_RTR_CTRL_1_NL_HBM_SEL_0, 0x21); - WREG32(mmSIF_RTR_CTRL_1_NL_HBM_SEL_1, 0x22); - WREG32(mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_18, 0x1F); - WREG32(mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_3, 0x20); - - WREG32(mmSIF_RTR_CTRL_2_NL_HBM_SEL_0, 0x21); - WREG32(mmSIF_RTR_CTRL_2_NL_HBM_SEL_1, 0x22); - WREG32(mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_18, 0x1F); - WREG32(mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_3, 0x20); - - WREG32(mmSIF_RTR_CTRL_3_NL_HBM_SEL_0, 0x21); - WREG32(mmSIF_RTR_CTRL_3_NL_HBM_SEL_1, 0x22); - WREG32(mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_18, 0x1F); - WREG32(mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_3, 0x20); - - WREG32(mmSIF_RTR_CTRL_4_NL_HBM_SEL_0, 0x21); - WREG32(mmSIF_RTR_CTRL_4_NL_HBM_SEL_1, 0x22); - WREG32(mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_18, 0x1F); - WREG32(mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_3, 0x20); - - WREG32(mmSIF_RTR_CTRL_5_NL_HBM_SEL_0, 0x21); - WREG32(mmSIF_RTR_CTRL_5_NL_HBM_SEL_1, 0x22); - WREG32(mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_18, 0x1F); - WREG32(mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_3, 0x20); - - WREG32(mmSIF_RTR_CTRL_6_NL_HBM_SEL_0, 0x21); - WREG32(mmSIF_RTR_CTRL_6_NL_HBM_SEL_1, 0x22); - WREG32(mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_18, 0x1F); - WREG32(mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_3, 0x20); - - WREG32(mmSIF_RTR_CTRL_7_NL_HBM_SEL_0, 0x21); - WREG32(mmSIF_RTR_CTRL_7_NL_HBM_SEL_1, 0x22); - WREG32(mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_18, 0x1F); - WREG32(mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_3, 0x20); - - WREG32(mmNIF_RTR_CTRL_0_NL_HBM_SEL_0, 0x21); - WREG32(mmNIF_RTR_CTRL_0_NL_HBM_SEL_1, 0x22); - WREG32(mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_18, 0x1F); - WREG32(mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_3, 0x20); - - WREG32(mmNIF_RTR_CTRL_1_NL_HBM_SEL_0, 0x21); - WREG32(mmNIF_RTR_CTRL_1_NL_HBM_SEL_1, 0x22); - WREG32(mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_18, 0x1F); - WREG32(mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_3, 0x20); - - WREG32(mmNIF_RTR_CTRL_2_NL_HBM_SEL_0, 0x21); - WREG32(mmNIF_RTR_CTRL_2_NL_HBM_SEL_1, 0x22); - WREG32(mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_18, 0x1F); - WREG32(mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_3, 0x20); - - WREG32(mmNIF_RTR_CTRL_3_NL_HBM_SEL_0, 0x21); - WREG32(mmNIF_RTR_CTRL_3_NL_HBM_SEL_1, 0x22); - WREG32(mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_18, 0x1F); - WREG32(mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_3, 0x20); - - WREG32(mmNIF_RTR_CTRL_4_NL_HBM_SEL_0, 0x21); - WREG32(mmNIF_RTR_CTRL_4_NL_HBM_SEL_1, 0x22); - WREG32(mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_18, 0x1F); - WREG32(mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_3, 0x20); - - WREG32(mmNIF_RTR_CTRL_5_NL_HBM_SEL_0, 0x21); - WREG32(mmNIF_RTR_CTRL_5_NL_HBM_SEL_1, 0x22); - WREG32(mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_18, 0x1F); - WREG32(mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_3, 0x20); - - WREG32(mmNIF_RTR_CTRL_6_NL_HBM_SEL_0, 0x21); - WREG32(mmNIF_RTR_CTRL_6_NL_HBM_SEL_1, 0x22); - WREG32(mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_18, 0x1F); - WREG32(mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_3, 0x20); - - WREG32(mmNIF_RTR_CTRL_7_NL_HBM_SEL_0, 0x21); - WREG32(mmNIF_RTR_CTRL_7_NL_HBM_SEL_1, 0x22); - WREG32(mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_18, 0x1F); - WREG32(mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_3, 0x20); - - WREG32(mmDMA_IF_E_N_DOWN_CH0_NL_HBM_SEL_0, 0x21); - WREG32(mmDMA_IF_E_N_DOWN_CH0_NL_HBM_SEL_1, 0x22); - WREG32(mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_18, 0x1F); - WREG32(mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_3, 0x20); - - WREG32(mmDMA_IF_E_N_DOWN_CH1_NL_HBM_SEL_0, 0x21); - WREG32(mmDMA_IF_E_N_DOWN_CH1_NL_HBM_SEL_1, 0x22); - WREG32(mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_18, 0x1F); - WREG32(mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_3, 0x20); - - WREG32(mmDMA_IF_E_S_DOWN_CH0_NL_HBM_SEL_0, 0x21); - WREG32(mmDMA_IF_E_S_DOWN_CH0_NL_HBM_SEL_1, 0x22); - WREG32(mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_18, 0x1F); - WREG32(mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_3, 0x20); - - WREG32(mmDMA_IF_E_S_DOWN_CH1_NL_HBM_SEL_0, 0x21); - WREG32(mmDMA_IF_E_S_DOWN_CH1_NL_HBM_SEL_1, 0x22); - WREG32(mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_18, 0x1F); - WREG32(mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_3, 0x20); - - WREG32(mmDMA_IF_W_N_DOWN_CH0_NL_HBM_SEL_0, 0x21); - WREG32(mmDMA_IF_W_N_DOWN_CH0_NL_HBM_SEL_1, 0x22); - WREG32(mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_18, 0x1F); - WREG32(mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_3, 0x20); - - WREG32(mmDMA_IF_W_N_DOWN_CH1_NL_HBM_SEL_0, 0x21); - WREG32(mmDMA_IF_W_N_DOWN_CH1_NL_HBM_SEL_1, 0x22); - WREG32(mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_18, 0x1F); - WREG32(mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_3, 0x20); - - WREG32(mmDMA_IF_W_S_DOWN_CH0_NL_HBM_SEL_0, 0x21); - WREG32(mmDMA_IF_W_S_DOWN_CH0_NL_HBM_SEL_1, 0x22); - WREG32(mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_18, 0x1F); - WREG32(mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_3, 0x20); - - WREG32(mmDMA_IF_W_S_DOWN_CH1_NL_HBM_SEL_0, 0x21); - WREG32(mmDMA_IF_W_S_DOWN_CH1_NL_HBM_SEL_1, 0x22); - WREG32(mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_18, 0x1F); - WREG32(mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_3, 0x20); - } - WREG32(mmSIF_RTR_CTRL_0_E2E_HBM_EN, 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); WREG32(mmSIF_RTR_CTRL_0_E2E_PCI_EN, @@ -3339,19 +3225,19 @@ static void gaudi_init_nic_qman(struct hl_device *hdev, u32 nic_offset, u32 nic_qm_err_cfg, irq_handler_offset; u32 q_off; - mtr_base_en_lo = lower_32_bits(CFG_BASE + + mtr_base_en_lo = lower_32_bits((CFG_BASE & U32_MAX) + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); mtr_base_en_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); - so_base_en_lo = lower_32_bits(CFG_BASE + + so_base_en_lo = lower_32_bits((CFG_BASE & U32_MAX) + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0); so_base_en_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0); - mtr_base_ws_lo = lower_32_bits(CFG_BASE + + mtr_base_ws_lo = lower_32_bits((CFG_BASE & U32_MAX) + mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); mtr_base_ws_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); - so_base_ws_lo = lower_32_bits(CFG_BASE + + so_base_ws_lo = lower_32_bits((CFG_BASE & U32_MAX) + mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0); so_base_ws_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0); @@ -3851,8 +3737,8 @@ static int gaudi_mmu_init(struct hl_device *hdev) } /* init MMU cache manage page */ - WREG32(mmSTLB_CACHE_INV_BASE_39_8, MMU_CACHE_MNG_ADDR >> 8); - WREG32(mmSTLB_CACHE_INV_BASE_49_40, MMU_CACHE_MNG_ADDR >> 40); + WREG32(mmSTLB_CACHE_INV_BASE_39_8, prop->mmu_cache_mng_addr >> 8); + WREG32(mmSTLB_CACHE_INV_BASE_49_40, prop->mmu_cache_mng_addr >> 40); /* mem cache invalidation */ WREG32(mmSTLB_MEM_CACHE_INVALIDATION, 1); @@ -3862,8 +3748,7 @@ static int gaudi_mmu_init(struct hl_device *hdev) WREG32(mmMMU_UP_MMU_ENABLE, 1); WREG32(mmMMU_UP_SPI_MASK, 0xF); - WREG32(mmSTLB_HOP_CONFIGURATION, - hdev->mmu_huge_page_opt ? 0x30440 : 0x40440); + WREG32(mmSTLB_HOP_CONFIGURATION, 0x30440); /* * The H/W expects the first PI after init to be 1. After wraparound @@ -3943,6 +3828,18 @@ static void gaudi_init_static_firmware_loader(struct hl_device *hdev) GAUDI_CPU_RESET_WAIT_MSEC; } +static void gaudi_init_firmware_preload_params(struct hl_device *hdev) +{ + struct pre_fw_load_props *pre_fw_load = &hdev->fw_loader.pre_fw_load; + + pre_fw_load->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS; + pre_fw_load->sts_boot_dev_sts0_reg = mmCPU_BOOT_DEV_STS0; + pre_fw_load->sts_boot_dev_sts1_reg = mmCPU_BOOT_DEV_STS1; + pre_fw_load->boot_err0_reg = mmCPU_BOOT_ERR0; + pre_fw_load->boot_err1_reg = mmCPU_BOOT_ERR1; + pre_fw_load->wait_for_preboot_timeout = GAUDI_BOOT_FIT_REQ_TIMEOUT_USEC; +} + static void gaudi_init_firmware_loader(struct hl_device *hdev) { struct asic_fixed_properties *prop = &hdev->asic_prop; @@ -4338,7 +4235,7 @@ static int gaudi_suspend(struct hl_device *hdev) { int rc; - rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS); + rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS, 0x0); if (rc) dev_err(hdev->dev, "Failed to disable PCI access from CPU\n"); @@ -4743,7 +4640,7 @@ static void gaudi_dma_free_coherent(struct hl_device *hdev, size_t size, static int gaudi_scrub_device_dram(struct hl_device *hdev, u64 val) { struct asic_fixed_properties *prop = &hdev->asic_prop; - u64 cur_addr = DRAM_BASE_ADDR_USER; + u64 cur_addr = prop->dram_user_base_address; u32 chunk_size, busy; int rc, dma_id; @@ -4801,51 +4698,47 @@ static int gaudi_scrub_device_dram(struct hl_device *hdev, u64 val) return 0; } -static int gaudi_scrub_device_mem(struct hl_device *hdev, u64 addr, u64 size) +static int gaudi_scrub_device_mem(struct hl_device *hdev) { struct asic_fixed_properties *prop = &hdev->asic_prop; + u64 wait_to_idle_time = hdev->pdev ? HBM_SCRUBBING_TIMEOUT_US : + min_t(u64, HBM_SCRUBBING_TIMEOUT_US * 10, HL_SIM_MAX_TIMEOUT_US); + u64 addr, size, val = hdev->memory_scrub_val; + ktime_t timeout; int rc = 0; - u64 val = 0; if (!hdev->memory_scrub) return 0; - if (!addr && !size) { - /* Wait till device is idle */ - rc = hl_poll_timeout( - hdev, - mmDMA0_CORE_STS0/* dummy */, - val/* dummy */, - (hdev->asic_funcs->is_device_idle(hdev, NULL, - 0, NULL)), - 1000, - HBM_SCRUBBING_TIMEOUT_US); - if (rc) { + timeout = ktime_add_us(ktime_get(), wait_to_idle_time); + while (!hdev->asic_funcs->is_device_idle(hdev, NULL, 0, NULL)) { + if (ktime_compare(ktime_get(), timeout) > 0) { dev_err(hdev->dev, "waiting for idle timeout\n"); - return -EIO; + return -ETIMEDOUT; } - - /* Scrub SRAM */ - addr = prop->sram_user_base_address; - size = hdev->pldm ? 0x10000 : - (prop->sram_size - SRAM_USER_BASE_OFFSET); - val = 0x7777777777777777ull; - - rc = gaudi_memset_device_memory(hdev, addr, size, val); - if (rc) { - dev_err(hdev->dev, - "Failed to clear SRAM in mem scrub all\n"); - return rc; - } - - /* Scrub HBM using all DMA channels in parallel */ - rc = gaudi_scrub_device_dram(hdev, 0xdeadbeaf); - if (rc) - dev_err(hdev->dev, - "Failed to clear HBM in mem scrub all\n"); + usleep_range((1000 >> 2) + 1, 1000); } - return rc; + /* Scrub SRAM */ + addr = prop->sram_user_base_address; + size = hdev->pldm ? 0x10000 : prop->sram_size - SRAM_USER_BASE_OFFSET; + + dev_dbg(hdev->dev, "Scrubing SRAM: 0x%09llx - 0x%09llx val: 0x%llx\n", + addr, addr + size, val); + rc = gaudi_memset_device_memory(hdev, addr, size, val); + if (rc) { + dev_err(hdev->dev, "Failed to clear SRAM (%d)\n", rc); + return rc; + } + + /* Scrub HBM using all DMA channels in parallel */ + rc = gaudi_scrub_device_dram(hdev, val); + if (rc) { + dev_err(hdev->dev, "Failed to clear HBM (%d)\n", rc); + return rc; + } + + return 0; } static void *gaudi_get_int_queue_base(struct hl_device *hdev, @@ -4902,8 +4795,7 @@ static int gaudi_test_queue(struct hl_device *hdev, u32 hw_queue_id) fence_val = GAUDI_QMAN0_FENCE_VAL; - fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL, - &fence_dma_addr); + fence_ptr = hl_asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL, &fence_dma_addr); if (!fence_ptr) { dev_err(hdev->dev, "Failed to allocate memory for H/W queue %d testing\n", @@ -4913,9 +4805,8 @@ static int gaudi_test_queue(struct hl_device *hdev, u32 hw_queue_id) *fence_ptr = 0; - fence_pkt = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, - sizeof(struct packet_msg_prot), - GFP_KERNEL, &pkt_dma_addr); + fence_pkt = hl_asic_dma_pool_zalloc(hdev, sizeof(struct packet_msg_prot), GFP_KERNEL, + &pkt_dma_addr); if (!fence_pkt) { dev_err(hdev->dev, "Failed to allocate packet for H/W queue %d testing\n", @@ -4955,11 +4846,9 @@ static int gaudi_test_queue(struct hl_device *hdev, u32 hw_queue_id) } free_pkt: - hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_pkt, - pkt_dma_addr); + hl_asic_dma_pool_free(hdev, (void *) fence_pkt, pkt_dma_addr); free_fence_ptr: - hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr, - fence_dma_addr); + hl_asic_dma_pool_free(hdev, (void *) fence_ptr, fence_dma_addr); return rc; } @@ -5305,11 +5194,13 @@ static int gaudi_validate_cb(struct hl_device *hdev, /* * The new CB should have space at the end for two MSG_PROT packets: - * 1. A packet that will act as a completion packet - * 2. A packet that will generate MSI-X interrupt + * 1. Optional NOP padding for cacheline alignment + * 2. A packet that will act as a completion packet + * 3. A packet that will generate MSI interrupt */ if (parser->completion) - parser->patched_cb_size += sizeof(struct packet_msg_prot) * 2; + parser->patched_cb_size += gaudi_get_patched_cb_extra_size( + parser->patched_cb_size); return rc; } @@ -5532,13 +5423,14 @@ static int gaudi_parse_cb_mmu(struct hl_device *hdev, int rc; /* - * The new CB should have space at the end for two MSG_PROT pkt: - * 1. A packet that will act as a completion packet - * 2. A packet that will generate MSI interrupt + * The new CB should have space at the end for two MSG_PROT packets: + * 1. Optional NOP padding for cacheline alignment + * 2. A packet that will act as a completion packet + * 3. A packet that will generate MSI interrupt */ if (parser->completion) parser->patched_cb_size = parser->user_cb_size + - sizeof(struct packet_msg_prot) * 2; + gaudi_get_patched_cb_extra_size(parser->user_cb_size); else parser->patched_cb_size = parser->user_cb_size; @@ -5562,8 +5454,14 @@ static int gaudi_parse_cb_mmu(struct hl_device *hdev, } /* - * The check that parser->user_cb_size <= parser->user_cb->size was done - * in validate_queue_index(). + * We are protected from overflow because the check + * "parser->user_cb_size <= parser->user_cb->size" was done in get_cb_from_cs_chunk() + * in the common code. That check is done only if is_kernel_allocated_cb is true. + * + * There is no option to reach here without going through that check because: + * 1. validate_queue_index() assigns true to is_kernel_allocated_cb for any submission to + * an external queue. + * 2. For Gaudi, we only parse CBs that were submitted to the external queues. */ memcpy(parser->patched_cb->kernel_address, parser->user_cb->kernel_address, @@ -5654,15 +5552,17 @@ static int gaudi_parse_cb_no_ext_queue(struct hl_device *hdev, { struct asic_fixed_properties *asic_prop = &hdev->asic_prop; struct gaudi_device *gaudi = hdev->asic_specific; - u32 nic_mask_q_id = 1 << (HW_CAP_NIC_SHIFT + - ((parser->hw_queue_id - GAUDI_QUEUE_ID_NIC_0_0) >> 2)); + u32 nic_queue_offset, nic_mask_q_id; if ((parser->hw_queue_id >= GAUDI_QUEUE_ID_NIC_0_0) && - (parser->hw_queue_id <= GAUDI_QUEUE_ID_NIC_9_3) && - (!(gaudi->hw_cap_initialized & nic_mask_q_id))) { - dev_err(hdev->dev, "h/w queue %d is disabled\n", - parser->hw_queue_id); - return -EINVAL; + (parser->hw_queue_id <= GAUDI_QUEUE_ID_NIC_9_3)) { + nic_queue_offset = parser->hw_queue_id - GAUDI_QUEUE_ID_NIC_0_0; + nic_mask_q_id = 1 << (HW_CAP_NIC_SHIFT + (nic_queue_offset >> 2)); + + if (!(gaudi->hw_cap_initialized & nic_mask_q_id)) { + dev_err(hdev->dev, "h/w queue %d is disabled\n", parser->hw_queue_id); + return -EINVAL; + } } /* For internal queue jobs just check if CB address is valid */ @@ -5705,18 +5605,24 @@ static int gaudi_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser) return gaudi_parse_cb_no_mmu(hdev, parser); } -static void gaudi_add_end_of_cb_packets(struct hl_device *hdev, - void *kernel_address, u32 len, - u64 cq_addr, u32 cq_val, u32 msi_vec, - bool eb) +static void gaudi_add_end_of_cb_packets(struct hl_device *hdev, void *kernel_address, + u32 len, u32 original_len, u64 cq_addr, u32 cq_val, + u32 msi_vec, bool eb) { struct gaudi_device *gaudi = hdev->asic_specific; struct packet_msg_prot *cq_pkt; + struct packet_nop *cq_padding; u64 msi_addr; u32 tmp; + cq_padding = kernel_address + original_len; cq_pkt = kernel_address + len - (sizeof(struct packet_msg_prot) * 2); + while ((void *)cq_padding < (void *)cq_pkt) { + cq_padding->ctl = cpu_to_le32(FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_NOP)); + cq_padding++; + } + tmp = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_PROT); tmp |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1); @@ -6039,10 +5945,10 @@ static int gaudi_context_switch(struct hl_device *hdev, u32 asid) static int gaudi_mmu_clear_pgt_range(struct hl_device *hdev) { - struct asic_fixed_properties *prop = &hdev->asic_prop; + u32 size = hdev->asic_prop.mmu_pgt_size + + hdev->asic_prop.mmu_cache_mng_size; struct gaudi_device *gaudi = hdev->asic_specific; - u64 addr = prop->mmu_pgt_addr; - u32 size = prop->mmu_pgt_size + MMU_CACHE_MNG_SIZE; + u64 addr = hdev->asic_prop.mmu_pgt_addr; if (!(gaudi->hw_cap_initialized & HW_CAP_MMU)) return 0; @@ -6113,10 +6019,7 @@ static int gaudi_debugfs_read_dma(struct hl_device *hdev, u64 addr, u32 size, bool is_eng_idle; int rc = 0, dma_id; - kernel_addr = hdev->asic_funcs->asic_dma_alloc_coherent( - hdev, SZ_2M, - &dma_addr, - GFP_KERNEL | __GFP_ZERO); + kernel_addr = hl_asic_dma_alloc_coherent(hdev, SZ_2M, &dma_addr, GFP_KERNEL | __GFP_ZERO); if (!kernel_addr) return -ENOMEM; @@ -6205,8 +6108,7 @@ static int gaudi_debugfs_read_dma(struct hl_device *hdev, u64 addr, u32 size, out: hdev->asic_funcs->hw_queues_unlock(hdev); - hdev->asic_funcs->asic_dma_free_coherent(hdev, SZ_2M, kernel_addr, - dma_addr); + hl_asic_dma_free_coherent(hdev, SZ_2M, kernel_addr, dma_addr); return rc; } @@ -6552,8 +6454,7 @@ static int gaudi_send_job_on_qman0(struct hl_device *hdev, return -EBUSY; } - fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL, - &fence_dma_addr); + fence_ptr = hl_asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL, &fence_dma_addr); if (!fence_ptr) { dev_err(hdev->dev, "Failed to allocate fence memory for QMAN0\n"); @@ -6599,8 +6500,7 @@ static int gaudi_send_job_on_qman0(struct hl_device *hdev, free_fence_ptr: WREG32(mmDMA0_CORE_PROT + dma_offset, BIT(DMA0_CORE_PROT_ERR_VAL_SHIFT)); - hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr, - fence_dma_addr); + hl_asic_dma_pool_free(hdev, (void *) fence_ptr, fence_dma_addr); return rc; } @@ -6983,14 +6883,15 @@ static inline u32 gaudi_queue_idx_dec(u32 idx, u32 q_len) } /** - * gaudi_print_sw_config_stream_data - print SW config stream data + * gaudi_handle_sw_config_stream_data - print SW config stream data * * @hdev: pointer to the habanalabs device structure * @stream: the QMAN's stream * @qman_base: base address of QMAN registers block + * @event_mask: mask of the last events occurred */ -static void gaudi_print_sw_config_stream_data(struct hl_device *hdev, u32 stream, - u64 qman_base) +static void gaudi_handle_sw_config_stream_data(struct hl_device *hdev, u32 stream, + u64 qman_base, u64 event_mask) { u64 cq_ptr_lo, cq_ptr_hi, cq_tsize, cq_ptr; u32 cq_ptr_lo_off, size; @@ -7008,24 +6909,32 @@ static void gaudi_print_sw_config_stream_data(struct hl_device *hdev, u32 stream size = RREG32(cq_tsize); dev_info(hdev->dev, "stop on err: stream: %u, addr: %#llx, size: %u\n", stream, cq_ptr, size); + + if (event_mask & HL_NOTIFIER_EVENT_UNDEFINED_OPCODE) { + hdev->last_error.undef_opcode.cq_addr = cq_ptr; + hdev->last_error.undef_opcode.cq_size = size; + hdev->last_error.undef_opcode.stream_id = stream; + } } /** - * gaudi_print_last_pqes_on_err - print last PQEs on error + * gaudi_handle_last_pqes_on_err - print last PQEs on error * * @hdev: pointer to the habanalabs device structure * @qid_base: first QID of the QMAN (out of 4 streams) * @stream: the QMAN's stream * @qman_base: base address of QMAN registers block + * @event_mask: mask of the last events occurred * @pr_sw_conf: if true print the SW config stream data (CQ PTR and SIZE) */ -static void gaudi_print_last_pqes_on_err(struct hl_device *hdev, u32 qid_base, +static void gaudi_handle_last_pqes_on_err(struct hl_device *hdev, u32 qid_base, u32 stream, u64 qman_base, + u64 event_mask, bool pr_sw_conf) { u32 ci, qm_ci_stream_off, queue_len; struct hl_hw_queue *q; - u64 pq_ci; + u64 pq_ci, addr[PQ_FETCHER_CACHE_SIZE]; int i; q = &hdev->kernel_queues[qid_base + stream]; @@ -7040,16 +6949,16 @@ static void gaudi_print_last_pqes_on_err(struct hl_device *hdev, u32 qid_base, hdev->asic_funcs->hw_queues_lock(hdev); if (pr_sw_conf) - gaudi_print_sw_config_stream_data(hdev, stream, qman_base); + gaudi_handle_sw_config_stream_data(hdev, stream, qman_base, event_mask); ci = RREG32(pq_ci); /* we should start printing form ci -1 */ ci = gaudi_queue_idx_dec(ci, queue_len); + memset(addr, 0, sizeof(addr)); for (i = 0; i < PQ_FETCHER_CACHE_SIZE; i++) { struct hl_bd *bd; - u64 addr; u32 len; bd = q->kernel_address; @@ -7060,52 +6969,68 @@ static void gaudi_print_last_pqes_on_err(struct hl_device *hdev, u32 qid_base, if (!len) break; - addr = le64_to_cpu(bd->ptr); + addr[i] = le64_to_cpu(bd->ptr); dev_info(hdev->dev, "stop on err PQE(stream %u): ci: %u, addr: %#llx, size: %u\n", - stream, ci, addr, len); + stream, ci, addr[i], len); /* get previous ci, wrap if needed */ ci = gaudi_queue_idx_dec(ci, queue_len); } + if (event_mask & HL_NOTIFIER_EVENT_UNDEFINED_OPCODE) { + struct undefined_opcode_info *undef_opcode = &hdev->last_error.undef_opcode; + u32 arr_idx = undef_opcode->cb_addr_streams_len; + + if (arr_idx == 0) { + undef_opcode->timestamp = ktime_get(); + undef_opcode->engine_id = gaudi_queue_id_to_engine_id[qid_base]; + } + + memcpy(undef_opcode->cb_addr_streams[arr_idx], addr, sizeof(addr)); + undef_opcode->cb_addr_streams_len++; + } + hdev->asic_funcs->hw_queues_unlock(hdev); } /** - * print_qman_data_on_err - extract QMAN data on error + * handle_qman_data_on_err - extract QMAN data on error * * @hdev: pointer to the habanalabs device structure * @qid_base: first QID of the QMAN (out of 4 streams) * @stream: the QMAN's stream * @qman_base: base address of QMAN registers block + * @event_mask: mask of the last events occurred * * This function attempt to exatract as much data as possible on QMAN error. * On upper CP print the SW config stream data and last 8 PQEs. * On lower CP print SW config data and last PQEs of ALL 4 upper CPs */ -static void print_qman_data_on_err(struct hl_device *hdev, u32 qid_base, - u32 stream, u64 qman_base) +static void handle_qman_data_on_err(struct hl_device *hdev, u32 qid_base, + u32 stream, u64 qman_base, u64 event_mask) { u32 i; if (stream != QMAN_STREAMS) { - gaudi_print_last_pqes_on_err(hdev, qid_base, stream, qman_base, - true); + gaudi_handle_last_pqes_on_err(hdev, qid_base, stream, + qman_base, event_mask, true); return; } - gaudi_print_sw_config_stream_data(hdev, stream, qman_base); + /* handle Lower-CP */ + gaudi_handle_sw_config_stream_data(hdev, stream, qman_base, event_mask); for (i = 0; i < QMAN_STREAMS; i++) - gaudi_print_last_pqes_on_err(hdev, qid_base, i, qman_base, - false); + gaudi_handle_last_pqes_on_err(hdev, qid_base, i, + qman_base, event_mask, false); } static void gaudi_handle_qman_err_generic(struct hl_device *hdev, const char *qm_name, u64 qman_base, - u32 qid_base) + u32 qid_base, + u64 *event_mask) { u32 i, j, glbl_sts_val, arb_err_val, glbl_sts_clr_val; u64 glbl_sts_addr, arb_err_addr; @@ -7136,12 +7061,21 @@ static void gaudi_handle_qman_err_generic(struct hl_device *hdev, glbl_sts_clr_val |= BIT(j); } } + /* check for undefined opcode */ + if (glbl_sts_val & TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK && + hdev->last_error.undef_opcode.write_enable) { + memset(&hdev->last_error.undef_opcode, 0, + sizeof(hdev->last_error.undef_opcode)); + + hdev->last_error.undef_opcode.write_enable = false; + *event_mask |= HL_NOTIFIER_EVENT_UNDEFINED_OPCODE; + } /* Write 1 clear errors */ if (!hdev->stop_on_err) WREG32(glbl_sts_addr + 4 * i, glbl_sts_clr_val); else - print_qman_data_on_err(hdev, qid_base, i, qman_base); + handle_qman_data_on_err(hdev, qid_base, i, qman_base, *event_mask); } arb_err_val = RREG32(arb_err_addr); @@ -7290,7 +7224,7 @@ extract_ecc_info: ecc_address, ecc_syndrom, memory_wrapper_idx); } -static void gaudi_handle_qman_err(struct hl_device *hdev, u16 event_type) +static void gaudi_handle_qman_err(struct hl_device *hdev, u16 event_type, u64 *event_mask) { u64 qman_base; char desc[32]; @@ -7299,14 +7233,25 @@ static void gaudi_handle_qman_err(struct hl_device *hdev, u16 event_type) switch (event_type) { case GAUDI_EVENT_TPC0_QM ... GAUDI_EVENT_TPC7_QM: + /* In TPC QM event, notify on TPC assertion. While there isn't + * a specific event for assertion yet, the FW generates QM event. + * The SW upper layer will inspect an internal mapped area to indicate + * if the event is a tpc assertion or tpc QM. + */ + *event_mask |= HL_NOTIFIER_EVENT_TPC_ASSERT; index = event_type - GAUDI_EVENT_TPC0_QM; qid_base = GAUDI_QUEUE_ID_TPC_0_0 + index * QMAN_STREAMS; qman_base = mmTPC0_QM_BASE + index * TPC_QMAN_OFFSET; snprintf(desc, ARRAY_SIZE(desc), "%s%d", "TPC_QM", index); break; case GAUDI_EVENT_MME0_QM ... GAUDI_EVENT_MME2_QM: - index = event_type - GAUDI_EVENT_MME0_QM; - qid_base = GAUDI_QUEUE_ID_MME_0_0 + index * QMAN_STREAMS; + if (event_type == GAUDI_EVENT_MME0_QM) { + index = 0; + qid_base = GAUDI_QUEUE_ID_MME_0_0; + } else { /* event_type == GAUDI_EVENT_MME2_QM */ + index = 2; + qid_base = GAUDI_QUEUE_ID_MME_1_0; + } qman_base = mmMME0_QM_BASE + index * MME_QMAN_OFFSET; snprintf(desc, ARRAY_SIZE(desc), "%s%d", "MME_QM", index); break; @@ -7373,7 +7318,7 @@ static void gaudi_handle_qman_err(struct hl_device *hdev, u16 event_type) return; } - gaudi_handle_qman_err_generic(hdev, desc, qman_base, qid_base); + gaudi_handle_qman_err_generic(hdev, desc, qman_base, qid_base, event_mask); } static void gaudi_print_irq_info(struct hl_device *hdev, u16 event_type, @@ -7404,8 +7349,8 @@ static void gaudi_print_irq_info(struct hl_device *hdev, u16 event_type, gaudi_print_and_get_mmu_error_info(hdev, &razwi_addr, &razwi_type); /* In case it's the first razwi, save its parameters*/ - rc = atomic_cmpxchg(&hdev->last_error.razwi.write_disable, 0, 1); - if (!rc) { + rc = atomic_cmpxchg(&hdev->last_error.razwi.write_enable, 1, 0); + if (rc) { hdev->last_error.razwi.timestamp = ktime_get(); hdev->last_error.razwi.addr = razwi_addr; hdev->last_error.razwi.engine_id_1 = engine_id_1; @@ -7662,8 +7607,7 @@ static int tpc_krn_event_to_tpc_id(u16 tpc_dec_event_type) return (tpc_dec_event_type - GAUDI_EVENT_TPC0_KRN_ERR) / 6; } -static void gaudi_print_clk_change_info(struct hl_device *hdev, - u16 event_type) +static void gaudi_print_clk_change_info(struct hl_device *hdev, u16 event_type) { ktime_t zero_time = ktime_set(0, 0); @@ -7711,16 +7655,15 @@ static void gaudi_print_clk_change_info(struct hl_device *hdev, mutex_unlock(&hdev->clk_throttling.lock); } -static void gaudi_handle_eqe(struct hl_device *hdev, - struct hl_eq_entry *eq_entry) +static void gaudi_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry) { struct gaudi_device *gaudi = hdev->asic_specific; - u64 data = le64_to_cpu(eq_entry->data[0]); + u64 data = le64_to_cpu(eq_entry->data[0]), event_mask = 0; u32 ctl = le32_to_cpu(eq_entry->hdr.ctl); - u32 fw_fatal_err_flag = 0; + u32 fw_fatal_err_flag = 0, flags = 0; u16 event_type = ((ctl & EQ_CTL_EVENT_TYPE_MASK) >> EQ_CTL_EVENT_TYPE_SHIFT); - bool reset_required; + bool reset_required, reset_direct = false; u8 cause; int rc; @@ -7808,7 +7751,8 @@ static void gaudi_handle_eqe(struct hl_device *hdev, dev_err(hdev->dev, "reset required due to %s\n", gaudi_irq_map_table[event_type].name); - hl_device_reset(hdev, 0); + reset_direct = true; + goto reset_device; } else { hl_fw_unmask_irq(hdev, event_type); } @@ -7830,7 +7774,8 @@ static void gaudi_handle_eqe(struct hl_device *hdev, dev_err(hdev->dev, "reset required due to %s\n", gaudi_irq_map_table[event_type].name); - hl_device_reset(hdev, 0); + reset_direct = true; + goto reset_device; } else { hl_fw_unmask_irq(hdev, event_type); } @@ -7892,22 +7837,10 @@ static void gaudi_handle_eqe(struct hl_device *hdev, case GAUDI_EVENT_NIC4_QM0: case GAUDI_EVENT_NIC4_QM1: case GAUDI_EVENT_DMA0_CORE ... GAUDI_EVENT_DMA7_CORE: - gaudi_print_irq_info(hdev, event_type, true); - gaudi_handle_qman_err(hdev, event_type); - hl_fw_unmask_irq(hdev, event_type); - break; - case GAUDI_EVENT_TPC0_QM ... GAUDI_EVENT_TPC7_QM: gaudi_print_irq_info(hdev, event_type, true); - gaudi_handle_qman_err(hdev, event_type); + gaudi_handle_qman_err(hdev, event_type, &event_mask); hl_fw_unmask_irq(hdev, event_type); - - /* In TPC QM event, notify on TPC assertion. While there isn't - * a specific event for assertion yet, the FW generates QM event. - * The SW upper layer will inspect an internal mapped area to indicate - * if the event is a tpc assertion or tpc QM. - */ - hl_notifier_event_send_all(hdev, HL_NOTIFIER_EVENT_TPC_ASSERT); break; case GAUDI_EVENT_RAZWI_OR_ADC_SW: @@ -7978,21 +7911,38 @@ static void gaudi_handle_eqe(struct hl_device *hdev, break; } + if (event_mask) + hl_notifier_event_send_all(hdev, event_mask); + return; reset_device: - if (hdev->asic_prop.fw_security_enabled) - hl_device_reset(hdev, HL_DRV_RESET_HARD - | HL_DRV_RESET_BYPASS_REQ_TO_FW - | fw_fatal_err_flag); - else if (hdev->hard_reset_on_fw_events) - hl_device_reset(hdev, HL_DRV_RESET_HARD | HL_DRV_RESET_DELAY | fw_fatal_err_flag); + reset_required = true; + + if (hdev->asic_prop.fw_security_enabled && !reset_direct) { + flags = HL_DRV_RESET_HARD | HL_DRV_RESET_BYPASS_REQ_TO_FW | fw_fatal_err_flag; + + /* notify on device unavailable while the reset triggered by fw */ + event_mask |= (HL_NOTIFIER_EVENT_DEVICE_RESET | + HL_NOTIFIER_EVENT_DEVICE_UNAVAILABLE); + } else if (hdev->hard_reset_on_fw_events) { + flags = HL_DRV_RESET_HARD | HL_DRV_RESET_DELAY | fw_fatal_err_flag; + event_mask |= HL_NOTIFIER_EVENT_DEVICE_RESET; + } else { + reset_required = false; + } + + /* despite reset doesn't execute. a notification on + * occurred event needs to be sent here + */ + hl_notifier_event_send_all(hdev, event_mask); + if (reset_required) + hl_device_reset(hdev, flags); else hl_fw_unmask_irq(hdev, event_type); } -static void *gaudi_get_events_stat(struct hl_device *hdev, bool aggregate, - u32 *size) +static void *gaudi_get_events_stat(struct hl_device *hdev, bool aggregate, u32 *size) { struct gaudi_device *gaudi = hdev->asic_specific; @@ -8005,8 +7955,7 @@ static void *gaudi_get_events_stat(struct hl_device *hdev, bool aggregate, return gaudi->events_stat; } -static int gaudi_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard, - u32 flags) +static int gaudi_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard, u32 flags) { struct gaudi_device *gaudi = hdev->asic_specific; u32 status, timeout_usec; @@ -8049,8 +7998,7 @@ static int gaudi_mmu_invalidate_cache_range(struct hl_device *hdev, return hdev->asic_funcs->mmu_invalidate_cache(hdev, is_hard, flags); } -static int gaudi_mmu_update_asid_hop0_addr(struct hl_device *hdev, - u32 asid, u64 phys_addr) +static int gaudi_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid, u64 phys_addr) { u32 status, timeout_usec; int rc; @@ -8405,11 +8353,10 @@ static int gaudi_internal_cb_pool_init(struct hl_device *hdev, if (!(gaudi->hw_cap_initialized & HW_CAP_MMU)) return 0; - hdev->internal_cb_pool_virt_addr = - hdev->asic_funcs->asic_dma_alloc_coherent(hdev, - HOST_SPACE_INTERNAL_CB_SZ, - &hdev->internal_cb_pool_dma_addr, - GFP_KERNEL | __GFP_ZERO); + hdev->internal_cb_pool_virt_addr = hl_asic_dma_alloc_coherent(hdev, + HOST_SPACE_INTERNAL_CB_SZ, + &hdev->internal_cb_pool_dma_addr, + GFP_KERNEL | __GFP_ZERO); if (!hdev->internal_cb_pool_virt_addr) return -ENOMEM; @@ -8464,10 +8411,8 @@ unreserve_internal_cb_pool: destroy_internal_cb_pool: gen_pool_destroy(hdev->internal_cb_pool); free_internal_cb_pool: - hdev->asic_funcs->asic_dma_free_coherent(hdev, - HOST_SPACE_INTERNAL_CB_SZ, - hdev->internal_cb_pool_virt_addr, - hdev->internal_cb_pool_dma_addr); + hl_asic_dma_free_coherent(hdev, HOST_SPACE_INTERNAL_CB_SZ, hdev->internal_cb_pool_virt_addr, + hdev->internal_cb_pool_dma_addr); return rc; } @@ -8490,10 +8435,8 @@ static void gaudi_internal_cb_pool_fini(struct hl_device *hdev, gen_pool_destroy(hdev->internal_cb_pool); - hdev->asic_funcs->asic_dma_free_coherent(hdev, - HOST_SPACE_INTERNAL_CB_SZ, - hdev->internal_cb_pool_virt_addr, - hdev->internal_cb_pool_dma_addr); + hl_asic_dma_free_coherent(hdev, HOST_SPACE_INTERNAL_CB_SZ, hdev->internal_cb_pool_virt_addr, + hdev->internal_cb_pool_dma_addr); } static int gaudi_ctx_init(struct hl_ctx *ctx) @@ -8522,6 +8465,11 @@ static void gaudi_ctx_fini(struct hl_ctx *ctx) gaudi_internal_cb_pool_fini(ctx->hdev, ctx); } +static int gaudi_pre_schedule_cs(struct hl_cs *cs) +{ + return 0; +} + static u32 gaudi_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx) { return gaudi_cq_assignment[cq_idx]; @@ -8893,6 +8841,11 @@ static void gaudi_enable_events_from_fw(struct hl_device *hdev) gaudi_irq_map_table[GAUDI_EVENT_INTS_REGISTER].cpu_id); } +static int gaudi_ack_mmu_page_fault_or_access_error(struct hl_device *hdev, u64 mmu_cap_mask) +{ + return -EINVAL; +} + static int gaudi_map_pll_idx_to_fw_idx(u32 pll_idx) { switch (pll_idx) { @@ -9167,10 +9120,8 @@ static u32 *gaudi_get_stream_master_qid_arr(void) return gaudi_stream_master; } -static void gaudi_get_valid_dram_page_orders(struct hl_info_dev_memalloc_page_sizes *info) +static void gaudi_check_if_razwi_happened(struct hl_device *hdev) { - /* set 0 since multiple pages are not supported */ - info->page_order_bitmask = 0; } static ssize_t infineon_ver_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -9187,6 +9138,7 @@ static DEVICE_ATTR_RO(infineon_ver); static struct attribute *gaudi_vrm_dev_attrs[] = { &dev_attr_infineon_ver.attr, + NULL, }; static void gaudi_add_device_attr(struct hl_device *hdev, struct attribute_group *dev_clk_attr_grp, @@ -9224,7 +9176,6 @@ static const struct hl_asic_funcs gaudi_funcs = { .hl_dma_unmap_sgtable = hl_dma_unmap_sgtable, .cs_parser = gaudi_cs_parser, .asic_dma_map_sgtable = hl_dma_map_sgtable, - .get_dma_desc_list_size = gaudi_get_dma_desc_list_size, .add_end_of_cb_packets = gaudi_add_end_of_cb_packets, .update_eq_ci = gaudi_update_eq_ci, .context_switch = gaudi_context_switch, @@ -9244,6 +9195,8 @@ static const struct hl_asic_funcs gaudi_funcs = { .non_hard_reset_late_init = gaudi_non_hard_reset_late_init, .hw_queues_lock = gaudi_hw_queues_lock, .hw_queues_unlock = gaudi_hw_queues_unlock, + .kdma_lock = NULL, + .kdma_unlock = NULL, .get_pci_id = gaudi_get_pci_id, .get_eeprom_data = gaudi_get_eeprom_data, .get_monitor_dump = gaudi_get_monitor_dump, @@ -9255,6 +9208,7 @@ static const struct hl_asic_funcs gaudi_funcs = { .halt_coresight = gaudi_halt_coresight, .ctx_init = gaudi_ctx_init, .ctx_fini = gaudi_ctx_fini, + .pre_schedule_cs = gaudi_pre_schedule_cs, .get_queue_id_for_cq = gaudi_get_queue_id_for_cq, .load_firmware_to_device = gaudi_load_firmware_to_device, .load_boot_fit_to_device = gaudi_load_boot_fit_to_device, @@ -9265,24 +9219,27 @@ static const struct hl_asic_funcs gaudi_funcs = { .reset_sob = gaudi_reset_sob, .reset_sob_group = gaudi_reset_sob_group, .get_device_time = gaudi_get_device_time, + .pb_print_security_errors = NULL, .collective_wait_init_cs = gaudi_collective_wait_init_cs, .collective_wait_create_jobs = gaudi_collective_wait_create_jobs, + .get_dec_base_addr = NULL, .scramble_addr = hl_mmu_scramble_addr, .descramble_addr = hl_mmu_descramble_addr, .ack_protection_bits_errors = gaudi_ack_protection_bits_errors, .get_hw_block_id = gaudi_get_hw_block_id, .hw_block_mmap = gaudi_block_mmap, .enable_events_from_fw = gaudi_enable_events_from_fw, + .ack_mmu_errors = gaudi_ack_mmu_page_fault_or_access_error, .map_pll_idx_to_fw_idx = gaudi_map_pll_idx_to_fw_idx, + .init_firmware_preload_params = gaudi_init_firmware_preload_params, .init_firmware_loader = gaudi_init_firmware_loader, .init_cpu_scrambler_dram = gaudi_init_scrambler_hbm, .state_dump_init = gaudi_state_dump_init, .get_sob_addr = gaudi_get_sob_addr, .set_pci_memory_regions = gaudi_set_pci_memory_regions, .get_stream_master_qid_arr = gaudi_get_stream_master_qid_arr, - .is_valid_dram_page_size = NULL, + .check_if_razwi_happened = gaudi_check_if_razwi_happened, .mmu_get_real_page_size = hl_mmu_get_real_page_size, - .get_valid_dram_page_orders = gaudi_get_valid_dram_page_orders, .access_dev_mem = hl_access_dev_mem, .set_dram_bar_base = gaudi_set_hbm_bar_base, }; diff --git a/drivers/misc/habanalabs/gaudi/gaudi_security.c b/drivers/misc/habanalabs/gaudi/gaudi_security.c index 25ac87cebd45..81a3c79a8bc6 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi_security.c +++ b/drivers/misc/habanalabs/gaudi/gaudi_security.c @@ -469,7 +469,7 @@ static u64 gaudi_rr_hbw_mask_high_ar_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = { }; /** - * gaudi_set_block_as_protected - set the given block as protected + * gaudi_pb_set_block - set the given block as protected * * @hdev: pointer to hl_device structure * @base: block base address diff --git a/drivers/misc/habanalabs/gaudi2/Makefile b/drivers/misc/habanalabs/gaudi2/Makefile new file mode 100644 index 000000000000..1e047883ba74 --- /dev/null +++ b/drivers/misc/habanalabs/gaudi2/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +HL_GAUDI2_FILES := gaudi2/gaudi2.o gaudi2/gaudi2_security.o \ + gaudi2/gaudi2_coresight.o diff --git a/drivers/misc/habanalabs/gaudi2/gaudi2.c b/drivers/misc/habanalabs/gaudi2/gaudi2.c new file mode 100644 index 000000000000..98336a1a84b0 --- /dev/null +++ b/drivers/misc/habanalabs/gaudi2/gaudi2.c @@ -0,0 +1,9986 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2020-2022 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "gaudi2P.h" +#include "gaudi2_masks.h" +#include "../include/hw_ip/mmu/mmu_general.h" +#include "../include/hw_ip/mmu/mmu_v2_0.h" +#include "../include/gaudi2/gaudi2_packets.h" +#include "../include/gaudi2/gaudi2_reg_map.h" +#include "../include/gaudi2/gaudi2_async_ids_map_extended.h" +#include "../include/gaudi2/arc/gaudi2_arc_common_packets.h" + +#include +#include +#include +#include + +#define GAUDI2_DMA_POOL_BLK_SIZE SZ_256 /* 256 bytes */ + +#define GAUDI2_RESET_TIMEOUT_MSEC 500 /* 500ms */ +#define GAUDI2_RESET_POLL_TIMEOUT_USEC 50000 /* 50ms */ +#define GAUDI2_PLDM_HRESET_TIMEOUT_MSEC 25000 /* 25s */ +#define GAUDI2_PLDM_SRESET_TIMEOUT_MSEC 25000 /* 25s */ +#define GAUDI2_PLDM_RESET_POLL_TIMEOUT_USEC 3000000 /* 3s */ +#define GAUDI2_RESET_POLL_CNT 3 +#define GAUDI2_RESET_WAIT_MSEC 1 /* 1ms */ +#define GAUDI2_CPU_RESET_WAIT_MSEC 100 /* 100ms */ +#define GAUDI2_PLDM_RESET_WAIT_MSEC 1000 /* 1s */ +#define GAUDI2_CB_POOL_CB_CNT 512 +#define GAUDI2_CB_POOL_CB_SIZE SZ_128K /* 128KB */ +#define GAUDI2_MSG_TO_CPU_TIMEOUT_USEC 4000000 /* 4s */ +#define GAUDI2_WAIT_FOR_BL_TIMEOUT_USEC 25000000 /* 25s */ +#define GAUDI2_TEST_QUEUE_WAIT_USEC 100000 /* 100ms */ +#define GAUDI2_PLDM_TEST_QUEUE_WAIT_USEC 1000000 /* 1s */ + +#define GAUDI2_ALLOC_CPU_MEM_RETRY_CNT 3 + +/* + * since the code already has built-in support for binning of up to MAX_FAULTY_TPCS TPCs + * and the code relies on that value (for array size etc..) we define another value + * for MAX faulty TPCs which reflects the cluster binning requirements + */ +#define MAX_CLUSTER_BINNING_FAULTY_TPCS 1 +#define MAX_FAULTY_XBARS 1 +#define MAX_FAULTY_EDMAS 1 +#define MAX_FAULTY_DECODERS 1 + +#define GAUDI2_TPC_FULL_MASK 0x1FFFFFF +#define GAUDI2_HIF_HMMU_FULL_MASK 0xFFFF +#define GAUDI2_DECODER_FULL_MASK 0x3FF + +#define GAUDI2_NUM_OF_QM_ERR_CAUSE 18 +#define GAUDI2_NUM_OF_QM_LCP_ERR_CAUSE 25 +#define GAUDI2_NUM_OF_QM_ARB_ERR_CAUSE 3 +#define GAUDI2_NUM_OF_ARC_SEI_ERR_CAUSE 14 +#define GAUDI2_NUM_OF_CPU_SEI_ERR_CAUSE 3 +#define GAUDI2_NUM_OF_QM_SEI_ERR_CAUSE 2 +#define GAUDI2_NUM_OF_ROT_ERR_CAUSE 22 +#define GAUDI2_NUM_OF_TPC_INTR_CAUSE 30 +#define GAUDI2_NUM_OF_DEC_ERR_CAUSE 25 +#define GAUDI2_NUM_OF_MME_ERR_CAUSE 16 +#define GAUDI2_NUM_OF_MME_SBTE_ERR_CAUSE 5 +#define GAUDI2_NUM_OF_MME_WAP_ERR_CAUSE 7 +#define GAUDI2_NUM_OF_DMA_CORE_INTR_CAUSE 8 +#define GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE 19 +#define GAUDI2_NUM_OF_HBM_SEI_CAUSE 9 +#define GAUDI2_NUM_OF_SM_SEI_ERR_CAUSE 3 +#define GAUDI2_NUM_OF_PCIE_ADDR_DEC_ERR_CAUSE 3 +#define GAUDI2_NUM_OF_PMMU_FATAL_ERR_CAUSE 2 +#define GAUDI2_NUM_OF_HIF_FATAL_ERR_CAUSE 2 +#define GAUDI2_NUM_OF_AXI_DRAIN_ERR_CAUSE 2 +#define GAUDI2_NUM_OF_HBM_MC_SPI_CAUSE 5 + +#define GAUDI2_MMU_CACHE_INV_TIMEOUT_USEC (MMU_CONFIG_TIMEOUT_USEC * 10) +#define GAUDI2_PLDM_MMU_TIMEOUT_USEC (MMU_CONFIG_TIMEOUT_USEC * 200) +#define GAUDI2_ARB_WDT_TIMEOUT (0x1000000) + +#define GAUDI2_VDEC_TIMEOUT_USEC 10000 /* 10ms */ +#define GAUDI2_PLDM_VDEC_TIMEOUT_USEC (GAUDI2_VDEC_TIMEOUT_USEC * 100) + +#define KDMA_TIMEOUT_USEC USEC_PER_SEC + +#define IS_DMA_IDLE(dma_core_idle_ind_mask) \ + (!((dma_core_idle_ind_mask) & \ + ((DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_CNT_STS_MASK) | \ + (DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_MASK)))) + +#define IS_MME_IDLE(mme_arch_sts) (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK) + +#define IS_TPC_IDLE(tpc_cfg_sts) (((tpc_cfg_sts) & (TPC_IDLE_MASK)) == (TPC_IDLE_MASK)) + +#define IS_QM_IDLE(qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts) \ + ((((qm_glbl_sts0) & (QM_IDLE_MASK)) == (QM_IDLE_MASK)) && \ + (((qm_glbl_sts1) & (QM_ARC_IDLE_MASK)) == (QM_ARC_IDLE_MASK)) && \ + (((qm_cgm_sts) & (CGM_IDLE_MASK)) == (CGM_IDLE_MASK))) + +#define PCIE_DEC_EN_MASK 0x300 +#define DEC_WORK_STATE_IDLE 0 +#define DEC_WORK_STATE_PEND 3 +#define IS_DEC_IDLE(dec_swreg15) \ + (((dec_swreg15) & DCORE0_DEC0_CMD_SWREG15_SW_WORK_STATE_MASK) == DEC_WORK_STATE_IDLE || \ + ((dec_swreg15) & DCORE0_DEC0_CMD_SWREG15_SW_WORK_STATE_MASK) == DEC_WORK_STATE_PEND) + +/* HBM MMU address scrambling parameters */ +#define GAUDI2_HBM_MMU_SCRM_MEM_SIZE SZ_8M +#define GAUDI2_HBM_MMU_SCRM_DIV_SHIFT 26 +#define GAUDI2_HBM_MMU_SCRM_MOD_SHIFT 0 +#define GAUDI2_HBM_MMU_SCRM_ADDRESS_MASK DRAM_VA_HINT_MASK +#define GAUDI2_COMPENSATE_TLB_PAGE_SIZE_FACTOR 16 +#define MMU_RANGE_INV_VA_LSB_SHIFT 12 +#define MMU_RANGE_INV_VA_MSB_SHIFT 44 +#define MMU_RANGE_INV_EN_SHIFT 0 +#define MMU_RANGE_INV_ASID_EN_SHIFT 1 +#define MMU_RANGE_INV_ASID_SHIFT 2 + +#define GAUDI2_MAX_STRING_LEN 64 + +#define GAUDI2_VDEC_MSIX_ENTRIES (GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM - \ + GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM + 1) + +enum hl_pmmu_fatal_cause { + LATENCY_RD_OUT_FIFO_OVERRUN, + LATENCY_WR_OUT_FIFO_OVERRUN, +}; + +enum hl_pcie_drain_ind_cause { + LBW_AXI_DRAIN_IND, + HBW_AXI_DRAIN_IND +}; + +static const u32 cluster_hmmu_hif_enabled_mask[GAUDI2_HBM_NUM] = { + [HBM_ID0] = 0xFFFC, + [HBM_ID1] = 0xFFCF, + [HBM_ID2] = 0xF7F7, + [HBM_ID3] = 0x7F7F, + [HBM_ID4] = 0xFCFF, + [HBM_ID5] = 0xCFFF, +}; + +static const u8 xbar_edge_to_hbm_cluster[EDMA_ID_SIZE] = { + [0] = HBM_ID0, + [1] = HBM_ID1, + [2] = HBM_ID4, + [3] = HBM_ID5, +}; + +static const u8 edma_to_hbm_cluster[EDMA_ID_SIZE] = { + [EDMA_ID_DCORE0_INSTANCE0] = HBM_ID0, + [EDMA_ID_DCORE0_INSTANCE1] = HBM_ID2, + [EDMA_ID_DCORE1_INSTANCE0] = HBM_ID1, + [EDMA_ID_DCORE1_INSTANCE1] = HBM_ID3, + [EDMA_ID_DCORE2_INSTANCE0] = HBM_ID2, + [EDMA_ID_DCORE2_INSTANCE1] = HBM_ID4, + [EDMA_ID_DCORE3_INSTANCE0] = HBM_ID3, + [EDMA_ID_DCORE3_INSTANCE1] = HBM_ID5, +}; + +static const int gaudi2_qman_async_event_id[] = { + [GAUDI2_QUEUE_ID_PDMA_0_0] = GAUDI2_EVENT_PDMA0_QM, + [GAUDI2_QUEUE_ID_PDMA_0_1] = GAUDI2_EVENT_PDMA0_QM, + [GAUDI2_QUEUE_ID_PDMA_0_2] = GAUDI2_EVENT_PDMA0_QM, + [GAUDI2_QUEUE_ID_PDMA_0_3] = GAUDI2_EVENT_PDMA0_QM, + [GAUDI2_QUEUE_ID_PDMA_1_0] = GAUDI2_EVENT_PDMA1_QM, + [GAUDI2_QUEUE_ID_PDMA_1_1] = GAUDI2_EVENT_PDMA1_QM, + [GAUDI2_QUEUE_ID_PDMA_1_2] = GAUDI2_EVENT_PDMA1_QM, + [GAUDI2_QUEUE_ID_PDMA_1_3] = GAUDI2_EVENT_PDMA1_QM, + [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0] = GAUDI2_EVENT_HDMA0_QM, + [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_1] = GAUDI2_EVENT_HDMA0_QM, + [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_2] = GAUDI2_EVENT_HDMA0_QM, + [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3] = GAUDI2_EVENT_HDMA0_QM, + [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0] = GAUDI2_EVENT_HDMA1_QM, + [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_1] = GAUDI2_EVENT_HDMA1_QM, + [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_2] = GAUDI2_EVENT_HDMA1_QM, + [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3] = GAUDI2_EVENT_HDMA1_QM, + [GAUDI2_QUEUE_ID_DCORE0_MME_0_0] = GAUDI2_EVENT_MME0_QM, + [GAUDI2_QUEUE_ID_DCORE0_MME_0_1] = GAUDI2_EVENT_MME0_QM, + [GAUDI2_QUEUE_ID_DCORE0_MME_0_2] = GAUDI2_EVENT_MME0_QM, + [GAUDI2_QUEUE_ID_DCORE0_MME_0_3] = GAUDI2_EVENT_MME0_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_0_0] = GAUDI2_EVENT_TPC0_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_0_1] = GAUDI2_EVENT_TPC0_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_0_2] = GAUDI2_EVENT_TPC0_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_0_3] = GAUDI2_EVENT_TPC0_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_1_0] = GAUDI2_EVENT_TPC1_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_1_1] = GAUDI2_EVENT_TPC1_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_1_2] = GAUDI2_EVENT_TPC1_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_1_3] = GAUDI2_EVENT_TPC1_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_2_0] = GAUDI2_EVENT_TPC2_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_2_1] = GAUDI2_EVENT_TPC2_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_2_2] = GAUDI2_EVENT_TPC2_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_2_3] = GAUDI2_EVENT_TPC2_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_3_0] = GAUDI2_EVENT_TPC3_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_3_1] = GAUDI2_EVENT_TPC3_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_3_2] = GAUDI2_EVENT_TPC3_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_3_3] = GAUDI2_EVENT_TPC3_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_4_0] = GAUDI2_EVENT_TPC4_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_4_1] = GAUDI2_EVENT_TPC4_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_4_2] = GAUDI2_EVENT_TPC4_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_4_3] = GAUDI2_EVENT_TPC4_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_5_0] = GAUDI2_EVENT_TPC5_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_5_1] = GAUDI2_EVENT_TPC5_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_5_2] = GAUDI2_EVENT_TPC5_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_5_3] = GAUDI2_EVENT_TPC5_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_6_0] = GAUDI2_EVENT_TPC24_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_6_1] = GAUDI2_EVENT_TPC24_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_6_2] = GAUDI2_EVENT_TPC24_QM, + [GAUDI2_QUEUE_ID_DCORE0_TPC_6_3] = GAUDI2_EVENT_TPC24_QM, + [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0] = GAUDI2_EVENT_HDMA2_QM, + [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_1] = GAUDI2_EVENT_HDMA2_QM, + [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_2] = GAUDI2_EVENT_HDMA2_QM, + [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3] = GAUDI2_EVENT_HDMA2_QM, + [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0] = GAUDI2_EVENT_HDMA3_QM, + [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_1] = GAUDI2_EVENT_HDMA3_QM, + [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_2] = GAUDI2_EVENT_HDMA3_QM, + [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3] = GAUDI2_EVENT_HDMA3_QM, + [GAUDI2_QUEUE_ID_DCORE1_MME_0_0] = GAUDI2_EVENT_MME1_QM, + [GAUDI2_QUEUE_ID_DCORE1_MME_0_1] = GAUDI2_EVENT_MME1_QM, + [GAUDI2_QUEUE_ID_DCORE1_MME_0_2] = GAUDI2_EVENT_MME1_QM, + [GAUDI2_QUEUE_ID_DCORE1_MME_0_3] = GAUDI2_EVENT_MME1_QM, + [GAUDI2_QUEUE_ID_DCORE1_TPC_0_0] = GAUDI2_EVENT_TPC6_QM, + [GAUDI2_QUEUE_ID_DCORE1_TPC_0_1] = GAUDI2_EVENT_TPC6_QM, + [GAUDI2_QUEUE_ID_DCORE1_TPC_0_2] = GAUDI2_EVENT_TPC6_QM, + [GAUDI2_QUEUE_ID_DCORE1_TPC_0_3] = GAUDI2_EVENT_TPC6_QM, + [GAUDI2_QUEUE_ID_DCORE1_TPC_1_0] = GAUDI2_EVENT_TPC7_QM, + [GAUDI2_QUEUE_ID_DCORE1_TPC_1_1] = GAUDI2_EVENT_TPC7_QM, + [GAUDI2_QUEUE_ID_DCORE1_TPC_1_2] = GAUDI2_EVENT_TPC7_QM, + [GAUDI2_QUEUE_ID_DCORE1_TPC_1_3] = GAUDI2_EVENT_TPC7_QM, + [GAUDI2_QUEUE_ID_DCORE1_TPC_2_0] = GAUDI2_EVENT_TPC8_QM, + [GAUDI2_QUEUE_ID_DCORE1_TPC_2_1] = GAUDI2_EVENT_TPC8_QM, + [GAUDI2_QUEUE_ID_DCORE1_TPC_2_2] = GAUDI2_EVENT_TPC8_QM, + [GAUDI2_QUEUE_ID_DCORE1_TPC_2_3] = GAUDI2_EVENT_TPC8_QM, + [GAUDI2_QUEUE_ID_DCORE1_TPC_3_0] = GAUDI2_EVENT_TPC9_QM, + [GAUDI2_QUEUE_ID_DCORE1_TPC_3_1] = GAUDI2_EVENT_TPC9_QM, + [GAUDI2_QUEUE_ID_DCORE1_TPC_3_2] = GAUDI2_EVENT_TPC9_QM, + [GAUDI2_QUEUE_ID_DCORE1_TPC_3_3] = GAUDI2_EVENT_TPC9_QM, + [GAUDI2_QUEUE_ID_DCORE1_TPC_4_0] = GAUDI2_EVENT_TPC10_QM, + [GAUDI2_QUEUE_ID_DCORE1_TPC_4_1] = GAUDI2_EVENT_TPC10_QM, + [GAUDI2_QUEUE_ID_DCORE1_TPC_4_2] = GAUDI2_EVENT_TPC10_QM, + [GAUDI2_QUEUE_ID_DCORE1_TPC_4_3] = GAUDI2_EVENT_TPC10_QM, + [GAUDI2_QUEUE_ID_DCORE1_TPC_5_0] = GAUDI2_EVENT_TPC11_QM, + [GAUDI2_QUEUE_ID_DCORE1_TPC_5_1] = GAUDI2_EVENT_TPC11_QM, + [GAUDI2_QUEUE_ID_DCORE1_TPC_5_2] = GAUDI2_EVENT_TPC11_QM, + [GAUDI2_QUEUE_ID_DCORE1_TPC_5_3] = GAUDI2_EVENT_TPC11_QM, + [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0] = GAUDI2_EVENT_HDMA4_QM, + [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_1] = GAUDI2_EVENT_HDMA4_QM, + [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_2] = GAUDI2_EVENT_HDMA4_QM, + [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3] = GAUDI2_EVENT_HDMA4_QM, + [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0] = GAUDI2_EVENT_HDMA5_QM, + [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_1] = GAUDI2_EVENT_HDMA5_QM, + [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_2] = GAUDI2_EVENT_HDMA5_QM, + [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3] = GAUDI2_EVENT_HDMA5_QM, + [GAUDI2_QUEUE_ID_DCORE2_MME_0_0] = GAUDI2_EVENT_MME2_QM, + [GAUDI2_QUEUE_ID_DCORE2_MME_0_1] = GAUDI2_EVENT_MME2_QM, + [GAUDI2_QUEUE_ID_DCORE2_MME_0_2] = GAUDI2_EVENT_MME2_QM, + [GAUDI2_QUEUE_ID_DCORE2_MME_0_3] = GAUDI2_EVENT_MME2_QM, + [GAUDI2_QUEUE_ID_DCORE2_TPC_0_0] = GAUDI2_EVENT_TPC12_QM, + [GAUDI2_QUEUE_ID_DCORE2_TPC_0_1] = GAUDI2_EVENT_TPC12_QM, + [GAUDI2_QUEUE_ID_DCORE2_TPC_0_2] = GAUDI2_EVENT_TPC12_QM, + [GAUDI2_QUEUE_ID_DCORE2_TPC_0_3] = GAUDI2_EVENT_TPC12_QM, + [GAUDI2_QUEUE_ID_DCORE2_TPC_1_0] = GAUDI2_EVENT_TPC13_QM, + [GAUDI2_QUEUE_ID_DCORE2_TPC_1_1] = GAUDI2_EVENT_TPC13_QM, + [GAUDI2_QUEUE_ID_DCORE2_TPC_1_2] = GAUDI2_EVENT_TPC13_QM, + [GAUDI2_QUEUE_ID_DCORE2_TPC_1_3] = GAUDI2_EVENT_TPC13_QM, + [GAUDI2_QUEUE_ID_DCORE2_TPC_2_0] = GAUDI2_EVENT_TPC14_QM, + [GAUDI2_QUEUE_ID_DCORE2_TPC_2_1] = GAUDI2_EVENT_TPC14_QM, + [GAUDI2_QUEUE_ID_DCORE2_TPC_2_2] = GAUDI2_EVENT_TPC14_QM, + [GAUDI2_QUEUE_ID_DCORE2_TPC_2_3] = GAUDI2_EVENT_TPC14_QM, + [GAUDI2_QUEUE_ID_DCORE2_TPC_3_0] = GAUDI2_EVENT_TPC15_QM, + [GAUDI2_QUEUE_ID_DCORE2_TPC_3_1] = GAUDI2_EVENT_TPC15_QM, + [GAUDI2_QUEUE_ID_DCORE2_TPC_3_2] = GAUDI2_EVENT_TPC15_QM, + [GAUDI2_QUEUE_ID_DCORE2_TPC_3_3] = GAUDI2_EVENT_TPC15_QM, + [GAUDI2_QUEUE_ID_DCORE2_TPC_4_0] = GAUDI2_EVENT_TPC16_QM, + [GAUDI2_QUEUE_ID_DCORE2_TPC_4_1] = GAUDI2_EVENT_TPC16_QM, + [GAUDI2_QUEUE_ID_DCORE2_TPC_4_2] = GAUDI2_EVENT_TPC16_QM, + [GAUDI2_QUEUE_ID_DCORE2_TPC_4_3] = GAUDI2_EVENT_TPC16_QM, + [GAUDI2_QUEUE_ID_DCORE2_TPC_5_0] = GAUDI2_EVENT_TPC17_QM, + [GAUDI2_QUEUE_ID_DCORE2_TPC_5_1] = GAUDI2_EVENT_TPC17_QM, + [GAUDI2_QUEUE_ID_DCORE2_TPC_5_2] = GAUDI2_EVENT_TPC17_QM, + [GAUDI2_QUEUE_ID_DCORE2_TPC_5_3] = GAUDI2_EVENT_TPC17_QM, + [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0] = GAUDI2_EVENT_HDMA6_QM, + [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_1] = GAUDI2_EVENT_HDMA6_QM, + [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_2] = GAUDI2_EVENT_HDMA6_QM, + [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3] = GAUDI2_EVENT_HDMA6_QM, + [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0] = GAUDI2_EVENT_HDMA7_QM, + [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_1] = GAUDI2_EVENT_HDMA7_QM, + [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_2] = GAUDI2_EVENT_HDMA7_QM, + [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3] = GAUDI2_EVENT_HDMA7_QM, + [GAUDI2_QUEUE_ID_DCORE3_MME_0_0] = GAUDI2_EVENT_MME3_QM, + [GAUDI2_QUEUE_ID_DCORE3_MME_0_1] = GAUDI2_EVENT_MME3_QM, + [GAUDI2_QUEUE_ID_DCORE3_MME_0_2] = GAUDI2_EVENT_MME3_QM, + [GAUDI2_QUEUE_ID_DCORE3_MME_0_3] = GAUDI2_EVENT_MME3_QM, + [GAUDI2_QUEUE_ID_DCORE3_TPC_0_0] = GAUDI2_EVENT_TPC18_QM, + [GAUDI2_QUEUE_ID_DCORE3_TPC_0_1] = GAUDI2_EVENT_TPC18_QM, + [GAUDI2_QUEUE_ID_DCORE3_TPC_0_2] = GAUDI2_EVENT_TPC18_QM, + [GAUDI2_QUEUE_ID_DCORE3_TPC_0_3] = GAUDI2_EVENT_TPC18_QM, + [GAUDI2_QUEUE_ID_DCORE3_TPC_1_0] = GAUDI2_EVENT_TPC19_QM, + [GAUDI2_QUEUE_ID_DCORE3_TPC_1_1] = GAUDI2_EVENT_TPC19_QM, + [GAUDI2_QUEUE_ID_DCORE3_TPC_1_2] = GAUDI2_EVENT_TPC19_QM, + [GAUDI2_QUEUE_ID_DCORE3_TPC_1_3] = GAUDI2_EVENT_TPC19_QM, + [GAUDI2_QUEUE_ID_DCORE3_TPC_2_0] = GAUDI2_EVENT_TPC20_QM, + [GAUDI2_QUEUE_ID_DCORE3_TPC_2_1] = GAUDI2_EVENT_TPC20_QM, + [GAUDI2_QUEUE_ID_DCORE3_TPC_2_2] = GAUDI2_EVENT_TPC20_QM, + [GAUDI2_QUEUE_ID_DCORE3_TPC_2_3] = GAUDI2_EVENT_TPC20_QM, + [GAUDI2_QUEUE_ID_DCORE3_TPC_3_0] = GAUDI2_EVENT_TPC21_QM, + [GAUDI2_QUEUE_ID_DCORE3_TPC_3_1] = GAUDI2_EVENT_TPC21_QM, + [GAUDI2_QUEUE_ID_DCORE3_TPC_3_2] = GAUDI2_EVENT_TPC21_QM, + [GAUDI2_QUEUE_ID_DCORE3_TPC_3_3] = GAUDI2_EVENT_TPC21_QM, + [GAUDI2_QUEUE_ID_DCORE3_TPC_4_0] = GAUDI2_EVENT_TPC22_QM, + [GAUDI2_QUEUE_ID_DCORE3_TPC_4_1] = GAUDI2_EVENT_TPC22_QM, + [GAUDI2_QUEUE_ID_DCORE3_TPC_4_2] = GAUDI2_EVENT_TPC22_QM, + [GAUDI2_QUEUE_ID_DCORE3_TPC_4_3] = GAUDI2_EVENT_TPC22_QM, + [GAUDI2_QUEUE_ID_DCORE3_TPC_5_0] = GAUDI2_EVENT_TPC23_QM, + [GAUDI2_QUEUE_ID_DCORE3_TPC_5_1] = GAUDI2_EVENT_TPC23_QM, + [GAUDI2_QUEUE_ID_DCORE3_TPC_5_2] = GAUDI2_EVENT_TPC23_QM, + [GAUDI2_QUEUE_ID_DCORE3_TPC_5_3] = GAUDI2_EVENT_TPC23_QM, + [GAUDI2_QUEUE_ID_NIC_0_0] = GAUDI2_EVENT_NIC0_QM0, + [GAUDI2_QUEUE_ID_NIC_0_1] = GAUDI2_EVENT_NIC0_QM0, + [GAUDI2_QUEUE_ID_NIC_0_2] = GAUDI2_EVENT_NIC0_QM0, + [GAUDI2_QUEUE_ID_NIC_0_3] = GAUDI2_EVENT_NIC0_QM0, + [GAUDI2_QUEUE_ID_NIC_1_0] = GAUDI2_EVENT_NIC0_QM1, + [GAUDI2_QUEUE_ID_NIC_1_1] = GAUDI2_EVENT_NIC0_QM1, + [GAUDI2_QUEUE_ID_NIC_1_2] = GAUDI2_EVENT_NIC0_QM1, + [GAUDI2_QUEUE_ID_NIC_1_3] = GAUDI2_EVENT_NIC0_QM1, + [GAUDI2_QUEUE_ID_NIC_2_0] = GAUDI2_EVENT_NIC1_QM0, + [GAUDI2_QUEUE_ID_NIC_2_1] = GAUDI2_EVENT_NIC1_QM0, + [GAUDI2_QUEUE_ID_NIC_2_2] = GAUDI2_EVENT_NIC1_QM0, + [GAUDI2_QUEUE_ID_NIC_2_3] = GAUDI2_EVENT_NIC1_QM0, + [GAUDI2_QUEUE_ID_NIC_3_0] = GAUDI2_EVENT_NIC1_QM1, + [GAUDI2_QUEUE_ID_NIC_3_1] = GAUDI2_EVENT_NIC1_QM1, + [GAUDI2_QUEUE_ID_NIC_3_2] = GAUDI2_EVENT_NIC1_QM1, + [GAUDI2_QUEUE_ID_NIC_3_3] = GAUDI2_EVENT_NIC1_QM1, + [GAUDI2_QUEUE_ID_NIC_4_0] = GAUDI2_EVENT_NIC2_QM0, + [GAUDI2_QUEUE_ID_NIC_4_1] = GAUDI2_EVENT_NIC2_QM0, + [GAUDI2_QUEUE_ID_NIC_4_2] = GAUDI2_EVENT_NIC2_QM0, + [GAUDI2_QUEUE_ID_NIC_4_3] = GAUDI2_EVENT_NIC2_QM0, + [GAUDI2_QUEUE_ID_NIC_5_0] = GAUDI2_EVENT_NIC2_QM1, + [GAUDI2_QUEUE_ID_NIC_5_1] = GAUDI2_EVENT_NIC2_QM1, + [GAUDI2_QUEUE_ID_NIC_5_2] = GAUDI2_EVENT_NIC2_QM1, + [GAUDI2_QUEUE_ID_NIC_5_3] = GAUDI2_EVENT_NIC2_QM1, + [GAUDI2_QUEUE_ID_NIC_6_0] = GAUDI2_EVENT_NIC3_QM0, + [GAUDI2_QUEUE_ID_NIC_6_1] = GAUDI2_EVENT_NIC3_QM0, + [GAUDI2_QUEUE_ID_NIC_6_2] = GAUDI2_EVENT_NIC3_QM0, + [GAUDI2_QUEUE_ID_NIC_6_3] = GAUDI2_EVENT_NIC3_QM0, + [GAUDI2_QUEUE_ID_NIC_7_0] = GAUDI2_EVENT_NIC3_QM1, + [GAUDI2_QUEUE_ID_NIC_7_1] = GAUDI2_EVENT_NIC3_QM1, + [GAUDI2_QUEUE_ID_NIC_7_2] = GAUDI2_EVENT_NIC3_QM1, + [GAUDI2_QUEUE_ID_NIC_7_3] = GAUDI2_EVENT_NIC3_QM1, + [GAUDI2_QUEUE_ID_NIC_8_0] = GAUDI2_EVENT_NIC4_QM0, + [GAUDI2_QUEUE_ID_NIC_8_1] = GAUDI2_EVENT_NIC4_QM0, + [GAUDI2_QUEUE_ID_NIC_8_2] = GAUDI2_EVENT_NIC4_QM0, + [GAUDI2_QUEUE_ID_NIC_8_3] = GAUDI2_EVENT_NIC4_QM0, + [GAUDI2_QUEUE_ID_NIC_9_0] = GAUDI2_EVENT_NIC4_QM1, + [GAUDI2_QUEUE_ID_NIC_9_1] = GAUDI2_EVENT_NIC4_QM1, + [GAUDI2_QUEUE_ID_NIC_9_2] = GAUDI2_EVENT_NIC4_QM1, + [GAUDI2_QUEUE_ID_NIC_9_3] = GAUDI2_EVENT_NIC4_QM1, + [GAUDI2_QUEUE_ID_NIC_10_0] = GAUDI2_EVENT_NIC5_QM0, + [GAUDI2_QUEUE_ID_NIC_10_1] = GAUDI2_EVENT_NIC5_QM0, + [GAUDI2_QUEUE_ID_NIC_10_2] = GAUDI2_EVENT_NIC5_QM0, + [GAUDI2_QUEUE_ID_NIC_10_3] = GAUDI2_EVENT_NIC5_QM0, + [GAUDI2_QUEUE_ID_NIC_11_0] = GAUDI2_EVENT_NIC5_QM1, + [GAUDI2_QUEUE_ID_NIC_11_1] = GAUDI2_EVENT_NIC5_QM1, + [GAUDI2_QUEUE_ID_NIC_11_2] = GAUDI2_EVENT_NIC5_QM1, + [GAUDI2_QUEUE_ID_NIC_11_3] = GAUDI2_EVENT_NIC5_QM1, + [GAUDI2_QUEUE_ID_NIC_12_0] = GAUDI2_EVENT_NIC6_QM0, + [GAUDI2_QUEUE_ID_NIC_12_1] = GAUDI2_EVENT_NIC6_QM0, + [GAUDI2_QUEUE_ID_NIC_12_2] = GAUDI2_EVENT_NIC6_QM0, + [GAUDI2_QUEUE_ID_NIC_12_3] = GAUDI2_EVENT_NIC6_QM0, + [GAUDI2_QUEUE_ID_NIC_13_0] = GAUDI2_EVENT_NIC6_QM1, + [GAUDI2_QUEUE_ID_NIC_13_1] = GAUDI2_EVENT_NIC6_QM1, + [GAUDI2_QUEUE_ID_NIC_13_2] = GAUDI2_EVENT_NIC6_QM1, + [GAUDI2_QUEUE_ID_NIC_13_3] = GAUDI2_EVENT_NIC6_QM1, + [GAUDI2_QUEUE_ID_NIC_14_0] = GAUDI2_EVENT_NIC7_QM0, + [GAUDI2_QUEUE_ID_NIC_14_1] = GAUDI2_EVENT_NIC7_QM0, + [GAUDI2_QUEUE_ID_NIC_14_2] = GAUDI2_EVENT_NIC7_QM0, + [GAUDI2_QUEUE_ID_NIC_14_3] = GAUDI2_EVENT_NIC7_QM0, + [GAUDI2_QUEUE_ID_NIC_15_0] = GAUDI2_EVENT_NIC7_QM1, + [GAUDI2_QUEUE_ID_NIC_15_1] = GAUDI2_EVENT_NIC7_QM1, + [GAUDI2_QUEUE_ID_NIC_15_2] = GAUDI2_EVENT_NIC7_QM1, + [GAUDI2_QUEUE_ID_NIC_15_3] = GAUDI2_EVENT_NIC7_QM1, + [GAUDI2_QUEUE_ID_NIC_16_0] = GAUDI2_EVENT_NIC8_QM0, + [GAUDI2_QUEUE_ID_NIC_16_1] = GAUDI2_EVENT_NIC8_QM0, + [GAUDI2_QUEUE_ID_NIC_16_2] = GAUDI2_EVENT_NIC8_QM0, + [GAUDI2_QUEUE_ID_NIC_16_3] = GAUDI2_EVENT_NIC8_QM0, + [GAUDI2_QUEUE_ID_NIC_17_0] = GAUDI2_EVENT_NIC8_QM1, + [GAUDI2_QUEUE_ID_NIC_17_1] = GAUDI2_EVENT_NIC8_QM1, + [GAUDI2_QUEUE_ID_NIC_17_2] = GAUDI2_EVENT_NIC8_QM1, + [GAUDI2_QUEUE_ID_NIC_17_3] = GAUDI2_EVENT_NIC8_QM1, + [GAUDI2_QUEUE_ID_NIC_18_0] = GAUDI2_EVENT_NIC9_QM0, + [GAUDI2_QUEUE_ID_NIC_18_1] = GAUDI2_EVENT_NIC9_QM0, + [GAUDI2_QUEUE_ID_NIC_18_2] = GAUDI2_EVENT_NIC9_QM0, + [GAUDI2_QUEUE_ID_NIC_18_3] = GAUDI2_EVENT_NIC9_QM0, + [GAUDI2_QUEUE_ID_NIC_19_0] = GAUDI2_EVENT_NIC9_QM1, + [GAUDI2_QUEUE_ID_NIC_19_1] = GAUDI2_EVENT_NIC9_QM1, + [GAUDI2_QUEUE_ID_NIC_19_2] = GAUDI2_EVENT_NIC9_QM1, + [GAUDI2_QUEUE_ID_NIC_19_3] = GAUDI2_EVENT_NIC9_QM1, + [GAUDI2_QUEUE_ID_NIC_20_0] = GAUDI2_EVENT_NIC10_QM0, + [GAUDI2_QUEUE_ID_NIC_20_1] = GAUDI2_EVENT_NIC10_QM0, + [GAUDI2_QUEUE_ID_NIC_20_2] = GAUDI2_EVENT_NIC10_QM0, + [GAUDI2_QUEUE_ID_NIC_20_3] = GAUDI2_EVENT_NIC10_QM0, + [GAUDI2_QUEUE_ID_NIC_21_0] = GAUDI2_EVENT_NIC10_QM1, + [GAUDI2_QUEUE_ID_NIC_21_1] = GAUDI2_EVENT_NIC10_QM1, + [GAUDI2_QUEUE_ID_NIC_21_2] = GAUDI2_EVENT_NIC10_QM1, + [GAUDI2_QUEUE_ID_NIC_21_3] = GAUDI2_EVENT_NIC10_QM1, + [GAUDI2_QUEUE_ID_NIC_22_0] = GAUDI2_EVENT_NIC11_QM0, + [GAUDI2_QUEUE_ID_NIC_22_1] = GAUDI2_EVENT_NIC11_QM0, + [GAUDI2_QUEUE_ID_NIC_22_2] = GAUDI2_EVENT_NIC11_QM0, + [GAUDI2_QUEUE_ID_NIC_22_3] = GAUDI2_EVENT_NIC11_QM0, + [GAUDI2_QUEUE_ID_NIC_23_0] = GAUDI2_EVENT_NIC11_QM1, + [GAUDI2_QUEUE_ID_NIC_23_1] = GAUDI2_EVENT_NIC11_QM1, + [GAUDI2_QUEUE_ID_NIC_23_2] = GAUDI2_EVENT_NIC11_QM1, + [GAUDI2_QUEUE_ID_NIC_23_3] = GAUDI2_EVENT_NIC11_QM1, + [GAUDI2_QUEUE_ID_ROT_0_0] = GAUDI2_EVENT_ROTATOR0_ROT0_QM, + [GAUDI2_QUEUE_ID_ROT_0_1] = GAUDI2_EVENT_ROTATOR0_ROT0_QM, + [GAUDI2_QUEUE_ID_ROT_0_2] = GAUDI2_EVENT_ROTATOR0_ROT0_QM, + [GAUDI2_QUEUE_ID_ROT_0_3] = GAUDI2_EVENT_ROTATOR0_ROT0_QM, + [GAUDI2_QUEUE_ID_ROT_1_0] = GAUDI2_EVENT_ROTATOR1_ROT1_QM, + [GAUDI2_QUEUE_ID_ROT_1_1] = GAUDI2_EVENT_ROTATOR1_ROT1_QM, + [GAUDI2_QUEUE_ID_ROT_1_2] = GAUDI2_EVENT_ROTATOR1_ROT1_QM, + [GAUDI2_QUEUE_ID_ROT_1_3] = GAUDI2_EVENT_ROTATOR1_ROT1_QM +}; + +static const int gaudi2_dma_core_async_event_id[] = { + [DMA_CORE_ID_EDMA0] = GAUDI2_EVENT_HDMA0_CORE, + [DMA_CORE_ID_EDMA1] = GAUDI2_EVENT_HDMA1_CORE, + [DMA_CORE_ID_EDMA2] = GAUDI2_EVENT_HDMA2_CORE, + [DMA_CORE_ID_EDMA3] = GAUDI2_EVENT_HDMA3_CORE, + [DMA_CORE_ID_EDMA4] = GAUDI2_EVENT_HDMA4_CORE, + [DMA_CORE_ID_EDMA5] = GAUDI2_EVENT_HDMA5_CORE, + [DMA_CORE_ID_EDMA6] = GAUDI2_EVENT_HDMA6_CORE, + [DMA_CORE_ID_EDMA7] = GAUDI2_EVENT_HDMA7_CORE, + [DMA_CORE_ID_PDMA0] = GAUDI2_EVENT_PDMA0_CORE, + [DMA_CORE_ID_PDMA1] = GAUDI2_EVENT_PDMA1_CORE, + [DMA_CORE_ID_KDMA] = GAUDI2_EVENT_KDMA0_CORE, +}; + +static const char * const gaudi2_qm_sei_error_cause[GAUDI2_NUM_OF_QM_SEI_ERR_CAUSE] = { + "qman sei intr", + "arc sei intr" +}; + +static const char * const gaudi2_cpu_sei_error_cause[GAUDI2_NUM_OF_CPU_SEI_ERR_CAUSE] = { + "AXI_TERMINATOR WR", + "AXI_TERMINATOR RD", + "AXI SPLIT SEI Status" +}; + +static const char * const gaudi2_arc_sei_error_cause[GAUDI2_NUM_OF_ARC_SEI_ERR_CAUSE] = { + "cbu_bresp_sei_intr_cause", + "cbu_rresp_sei_intr_cause", + "lbu_bresp_sei_intr_cause", + "lbu_rresp_sei_intr_cause", + "cbu_axi_split_intr_cause", + "lbu_axi_split_intr_cause", + "arc_ip_excptn_sei_intr_cause", + "dmi_bresp_sei_intr_cause", + "aux2apb_err_sei_intr_cause", + "cfg_lbw_wr_terminated_intr_cause", + "cfg_lbw_rd_terminated_intr_cause", + "cfg_dccm_wr_terminated_intr_cause", + "cfg_dccm_rd_terminated_intr_cause", + "cfg_hbw_rd_terminated_intr_cause" +}; + +static const char * const gaudi2_dec_error_cause[GAUDI2_NUM_OF_DEC_ERR_CAUSE] = { + "msix_vcd_hbw_sei", + "msix_l2c_hbw_sei", + "msix_nrm_hbw_sei", + "msix_abnrm_hbw_sei", + "msix_vcd_lbw_sei", + "msix_l2c_lbw_sei", + "msix_nrm_lbw_sei", + "msix_abnrm_lbw_sei", + "apb_vcd_lbw_sei", + "apb_l2c_lbw_sei", + "apb_nrm_lbw_sei", + "apb_abnrm_lbw_sei", + "dec_sei", + "dec_apb_sei", + "trc_apb_sei", + "lbw_mstr_if_sei", + "axi_split_bresp_err_sei", + "hbw_axi_wr_viol_sei", + "hbw_axi_rd_viol_sei", + "lbw_axi_wr_viol_sei", + "lbw_axi_rd_viol_sei", + "vcd_spi", + "l2c_spi", + "nrm_spi", + "abnrm_spi", +}; + +static const char * const gaudi2_qman_error_cause[GAUDI2_NUM_OF_QM_ERR_CAUSE] = { + "PQ AXI HBW error", + "CQ AXI HBW error", + "CP AXI HBW error", + "CP error due to undefined OPCODE", + "CP encountered STOP OPCODE", + "CP AXI LBW error", + "CP WRREG32 or WRBULK returned error", + "N/A", + "FENCE 0 inc over max value and clipped", + "FENCE 1 inc over max value and clipped", + "FENCE 2 inc over max value and clipped", + "FENCE 3 inc over max value and clipped", + "FENCE 0 dec under min value and clipped", + "FENCE 1 dec under min value and clipped", + "FENCE 2 dec under min value and clipped", + "FENCE 3 dec under min value and clipped", + "CPDMA Up overflow", + "PQC L2H error" +}; + +static const char * const gaudi2_qman_lower_cp_error_cause[GAUDI2_NUM_OF_QM_LCP_ERR_CAUSE] = { + "RSVD0", + "CQ AXI HBW error", + "CP AXI HBW error", + "CP error due to undefined OPCODE", + "CP encountered STOP OPCODE", + "CP AXI LBW error", + "CP WRREG32 or WRBULK returned error", + "N/A", + "FENCE 0 inc over max value and clipped", + "FENCE 1 inc over max value and clipped", + "FENCE 2 inc over max value and clipped", + "FENCE 3 inc over max value and clipped", + "FENCE 0 dec under min value and clipped", + "FENCE 1 dec under min value and clipped", + "FENCE 2 dec under min value and clipped", + "FENCE 3 dec under min value and clipped", + "CPDMA Up overflow", + "RSVD17", + "CQ_WR_IFIFO_CI_ERR", + "CQ_WR_CTL_CI_ERR", + "ARC_CQF_RD_ERR", + "ARC_CQ_WR_IFIFO_CI_ERR", + "ARC_CQ_WR_CTL_CI_ERR", + "ARC_AXI_ERR", + "CP_SWITCH_WDT_ERR" +}; + +static const char * const gaudi2_qman_arb_error_cause[GAUDI2_NUM_OF_QM_ARB_ERR_CAUSE] = { + "Choice push while full error", + "Choice Q watchdog error", + "MSG AXI LBW returned with error" +}; + +static const char * const guadi2_rot_error_cause[GAUDI2_NUM_OF_ROT_ERR_CAUSE] = { + "qm_axi_err", + "qm_trace_fence_events", + "qm_sw_err", + "qm_cp_sw_stop", + "lbw_mstr_rresp_err", + "lbw_mstr_bresp_err", + "lbw_msg_slverr", + "hbw_msg_slverr", + "wbc_slverr", + "hbw_mstr_rresp_err", + "hbw_mstr_bresp_err", + "sb_resp_intr", + "mrsb_resp_intr", + "core_dw_status_0", + "core_dw_status_1", + "core_dw_status_2", + "core_dw_status_3", + "core_dw_status_4", + "core_dw_status_5", + "core_dw_status_6", + "core_dw_status_7", + "async_arc2cpu_sei_intr", +}; + +static const char * const gaudi2_tpc_interrupts_cause[GAUDI2_NUM_OF_TPC_INTR_CAUSE] = { + "tpc_address_exceed_slm", + "tpc_div_by_0", + "tpc_spu_mac_overflow", + "tpc_spu_addsub_overflow", + "tpc_spu_abs_overflow", + "tpc_spu_fma_fp_dst_nan", + "tpc_spu_fma_fp_dst_inf", + "tpc_spu_convert_fp_dst_nan", + "tpc_spu_convert_fp_dst_inf", + "tpc_spu_fp_dst_denorm", + "tpc_vpu_mac_overflow", + "tpc_vpu_addsub_overflow", + "tpc_vpu_abs_overflow", + "tpc_vpu_convert_fp_dst_nan", + "tpc_vpu_convert_fp_dst_inf", + "tpc_vpu_fma_fp_dst_nan", + "tpc_vpu_fma_fp_dst_inf", + "tpc_vpu_fp_dst_denorm", + "tpc_assertions", + "tpc_illegal_instruction", + "tpc_pc_wrap_around", + "tpc_qm_sw_err", + "tpc_hbw_rresp_err", + "tpc_hbw_bresp_err", + "tpc_lbw_rresp_err", + "tpc_lbw_bresp_err", + "st_unlock_already_locked", + "invalid_lock_access", + "LD_L protection violation", + "ST_L protection violation", +}; + +static const char * const guadi2_mme_error_cause[GAUDI2_NUM_OF_MME_ERR_CAUSE] = { + "agu_resp_intr", + "qman_axi_err", + "wap sei (wbc axi err)", + "arc sei", + "mme_cfg_unalign_addr", + "qm_sw_err", + "sbte_dbg_intr_0", + "sbte_dbg_intr_1", + "sbte_dbg_intr_2", + "sbte_dbg_intr_3", + "sbte_dbg_intr_4", + "sbte_prtn_intr_0", + "sbte_prtn_intr_1", + "sbte_prtn_intr_2", + "sbte_prtn_intr_3", + "sbte_prtn_intr_4", +}; + +static const char * const guadi2_mme_sbte_error_cause[GAUDI2_NUM_OF_MME_SBTE_ERR_CAUSE] = { + "i0", + "i1", + "i2", + "i3", + "i4", +}; + +static const char * const guadi2_mme_wap_error_cause[GAUDI2_NUM_OF_MME_WAP_ERR_CAUSE] = { + "WBC ERR RESP_0", + "WBC ERR RESP_1", + "AP SOURCE POS INF", + "AP SOURCE NEG INF", + "AP SOURCE NAN", + "AP RESULT POS INF", + "AP RESULT NEG INF", +}; + +static const char * const gaudi2_dma_core_interrupts_cause[GAUDI2_NUM_OF_DMA_CORE_INTR_CAUSE] = { + "HBW Read returned with error RRESP", + "HBW write returned with error BRESP", + "LBW write returned with error BRESP", + "descriptor_fifo_overflow", + "KDMA SB LBW Read returned with error", + "KDMA WBC LBW Write returned with error", + "TRANSPOSE ENGINE DESC FIFO OVERFLOW", + "WRONG CFG FOR COMMIT IN LIN DMA" +}; + +static const char * const gaudi2_kdma_core_interrupts_cause[GAUDI2_NUM_OF_DMA_CORE_INTR_CAUSE] = { + "HBW/LBW Read returned with error RRESP", + "HBW/LBW write returned with error BRESP", + "LBW write returned with error BRESP", + "descriptor_fifo_overflow", + "KDMA SB LBW Read returned with error", + "KDMA WBC LBW Write returned with error", + "TRANSPOSE ENGINE DESC FIFO OVERFLOW", + "WRONG CFG FOR COMMIT IN LIN DMA" +}; + +struct gaudi2_sm_sei_cause_data { + const char *cause_name; + const char *log_name; + u32 log_mask; +}; + +static const struct gaudi2_sm_sei_cause_data +gaudi2_sm_sei_cause[GAUDI2_NUM_OF_SM_SEI_ERR_CAUSE] = { + {"calculated SO value overflow/underflow", "SOB group ID", 0x7FF}, + {"payload address of monitor is not aligned to 4B", "monitor addr", 0xFFFF}, + {"armed monitor write got BRESP (SLVERR or DECERR)", "AXI id", 0xFFFF}, +}; + +static const char * const +gaudi2_pmmu_fatal_interrupts_cause[GAUDI2_NUM_OF_PMMU_FATAL_ERR_CAUSE] = { + "LATENCY_RD_OUT_FIFO_OVERRUN", + "LATENCY_WR_OUT_FIFO_OVERRUN", +}; + +static const char * const +gaudi2_hif_fatal_interrupts_cause[GAUDI2_NUM_OF_HIF_FATAL_ERR_CAUSE] = { + "LATENCY_RD_OUT_FIFO_OVERRUN", + "LATENCY_WR_OUT_FIFO_OVERRUN", +}; + +static const char * const +gaudi2_psoc_axi_drain_interrupts_cause[GAUDI2_NUM_OF_AXI_DRAIN_ERR_CAUSE] = { + "AXI drain HBW", + "AXI drain LBW", +}; + +static const char * const +gaudi2_pcie_addr_dec_error_cause[GAUDI2_NUM_OF_PCIE_ADDR_DEC_ERR_CAUSE] = { + "HBW error response", + "LBW error response", + "TLP is blocked by RR" +}; + +const u32 gaudi2_qm_blocks_bases[GAUDI2_QUEUE_ID_SIZE] = { + [GAUDI2_QUEUE_ID_PDMA_0_0] = mmPDMA0_QM_BASE, + [GAUDI2_QUEUE_ID_PDMA_0_1] = mmPDMA0_QM_BASE, + [GAUDI2_QUEUE_ID_PDMA_0_2] = mmPDMA0_QM_BASE, + [GAUDI2_QUEUE_ID_PDMA_0_3] = mmPDMA0_QM_BASE, + [GAUDI2_QUEUE_ID_PDMA_1_0] = mmPDMA1_QM_BASE, + [GAUDI2_QUEUE_ID_PDMA_1_1] = mmPDMA1_QM_BASE, + [GAUDI2_QUEUE_ID_PDMA_1_2] = mmPDMA1_QM_BASE, + [GAUDI2_QUEUE_ID_PDMA_1_3] = mmPDMA1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0] = mmDCORE0_EDMA0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_1] = mmDCORE0_EDMA0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_2] = mmDCORE0_EDMA0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3] = mmDCORE0_EDMA0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0] = mmDCORE0_EDMA1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_1] = mmDCORE0_EDMA1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_2] = mmDCORE0_EDMA1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3] = mmDCORE0_EDMA1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_MME_0_0] = mmDCORE0_MME_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_MME_0_1] = mmDCORE0_MME_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_MME_0_2] = mmDCORE0_MME_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_MME_0_3] = mmDCORE0_MME_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_0_0] = mmDCORE0_TPC0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_0_1] = mmDCORE0_TPC0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_0_2] = mmDCORE0_TPC0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_0_3] = mmDCORE0_TPC0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_1_0] = mmDCORE0_TPC1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_1_1] = mmDCORE0_TPC1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_1_2] = mmDCORE0_TPC1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_1_3] = mmDCORE0_TPC1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_2_0] = mmDCORE0_TPC2_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_2_1] = mmDCORE0_TPC2_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_2_2] = mmDCORE0_TPC2_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_2_3] = mmDCORE0_TPC2_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_3_0] = mmDCORE0_TPC3_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_3_1] = mmDCORE0_TPC3_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_3_2] = mmDCORE0_TPC3_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_3_3] = mmDCORE0_TPC3_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_4_0] = mmDCORE0_TPC4_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_4_1] = mmDCORE0_TPC4_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_4_2] = mmDCORE0_TPC4_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_4_3] = mmDCORE0_TPC4_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_5_0] = mmDCORE0_TPC5_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_5_1] = mmDCORE0_TPC5_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_5_2] = mmDCORE0_TPC5_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_5_3] = mmDCORE0_TPC5_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_6_0] = mmDCORE0_TPC6_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_6_1] = mmDCORE0_TPC6_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_6_2] = mmDCORE0_TPC6_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE0_TPC_6_3] = mmDCORE0_TPC6_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0] = mmDCORE1_EDMA0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_1] = mmDCORE1_EDMA0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_2] = mmDCORE1_EDMA0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3] = mmDCORE1_EDMA0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0] = mmDCORE1_EDMA1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_1] = mmDCORE1_EDMA1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_2] = mmDCORE1_EDMA1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3] = mmDCORE1_EDMA1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_MME_0_0] = mmDCORE1_MME_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_MME_0_1] = mmDCORE1_MME_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_MME_0_2] = mmDCORE1_MME_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_MME_0_3] = mmDCORE1_MME_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_TPC_0_0] = mmDCORE1_TPC0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_TPC_0_1] = mmDCORE1_TPC0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_TPC_0_2] = mmDCORE1_TPC0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_TPC_0_3] = mmDCORE1_TPC0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_TPC_1_0] = mmDCORE1_TPC1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_TPC_1_1] = mmDCORE1_TPC1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_TPC_1_2] = mmDCORE1_TPC1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_TPC_1_3] = mmDCORE1_TPC1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_TPC_2_0] = mmDCORE1_TPC2_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_TPC_2_1] = mmDCORE1_TPC2_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_TPC_2_2] = mmDCORE1_TPC2_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_TPC_2_3] = mmDCORE1_TPC2_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_TPC_3_0] = mmDCORE1_TPC3_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_TPC_3_1] = mmDCORE1_TPC3_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_TPC_3_2] = mmDCORE1_TPC3_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_TPC_3_3] = mmDCORE1_TPC3_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_TPC_4_0] = mmDCORE1_TPC4_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_TPC_4_1] = mmDCORE1_TPC4_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_TPC_4_2] = mmDCORE1_TPC4_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_TPC_4_3] = mmDCORE1_TPC4_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_TPC_5_0] = mmDCORE1_TPC5_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_TPC_5_1] = mmDCORE1_TPC5_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_TPC_5_2] = mmDCORE1_TPC5_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE1_TPC_5_3] = mmDCORE1_TPC5_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0] = mmDCORE2_EDMA0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_1] = mmDCORE2_EDMA0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_2] = mmDCORE2_EDMA0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3] = mmDCORE2_EDMA0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0] = mmDCORE2_EDMA1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_1] = mmDCORE2_EDMA1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_2] = mmDCORE2_EDMA1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3] = mmDCORE2_EDMA1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_MME_0_0] = mmDCORE2_MME_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_MME_0_1] = mmDCORE2_MME_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_MME_0_2] = mmDCORE2_MME_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_MME_0_3] = mmDCORE2_MME_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_TPC_0_0] = mmDCORE2_TPC0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_TPC_0_1] = mmDCORE2_TPC0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_TPC_0_2] = mmDCORE2_TPC0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_TPC_0_3] = mmDCORE2_TPC0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_TPC_1_0] = mmDCORE2_TPC1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_TPC_1_1] = mmDCORE2_TPC1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_TPC_1_2] = mmDCORE2_TPC1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_TPC_1_3] = mmDCORE2_TPC1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_TPC_2_0] = mmDCORE2_TPC2_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_TPC_2_1] = mmDCORE2_TPC2_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_TPC_2_2] = mmDCORE2_TPC2_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_TPC_2_3] = mmDCORE2_TPC2_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_TPC_3_0] = mmDCORE2_TPC3_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_TPC_3_1] = mmDCORE2_TPC3_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_TPC_3_2] = mmDCORE2_TPC3_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_TPC_3_3] = mmDCORE2_TPC3_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_TPC_4_0] = mmDCORE2_TPC4_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_TPC_4_1] = mmDCORE2_TPC4_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_TPC_4_2] = mmDCORE2_TPC4_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_TPC_4_3] = mmDCORE2_TPC4_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_TPC_5_0] = mmDCORE2_TPC5_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_TPC_5_1] = mmDCORE2_TPC5_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_TPC_5_2] = mmDCORE2_TPC5_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE2_TPC_5_3] = mmDCORE2_TPC5_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0] = mmDCORE3_EDMA0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_1] = mmDCORE3_EDMA0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_2] = mmDCORE3_EDMA0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3] = mmDCORE3_EDMA0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0] = mmDCORE3_EDMA1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_1] = mmDCORE3_EDMA1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_2] = mmDCORE3_EDMA1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3] = mmDCORE3_EDMA1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_MME_0_0] = mmDCORE3_MME_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_MME_0_1] = mmDCORE3_MME_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_MME_0_2] = mmDCORE3_MME_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_MME_0_3] = mmDCORE3_MME_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_TPC_0_0] = mmDCORE3_TPC0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_TPC_0_1] = mmDCORE3_TPC0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_TPC_0_2] = mmDCORE3_TPC0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_TPC_0_3] = mmDCORE3_TPC0_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_TPC_1_0] = mmDCORE3_TPC1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_TPC_1_1] = mmDCORE3_TPC1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_TPC_1_2] = mmDCORE3_TPC1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_TPC_1_3] = mmDCORE3_TPC1_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_TPC_2_0] = mmDCORE3_TPC2_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_TPC_2_1] = mmDCORE3_TPC2_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_TPC_2_2] = mmDCORE3_TPC2_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_TPC_2_3] = mmDCORE3_TPC2_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_TPC_3_0] = mmDCORE3_TPC3_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_TPC_3_1] = mmDCORE3_TPC3_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_TPC_3_2] = mmDCORE3_TPC3_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_TPC_3_3] = mmDCORE3_TPC3_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_TPC_4_0] = mmDCORE3_TPC4_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_TPC_4_1] = mmDCORE3_TPC4_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_TPC_4_2] = mmDCORE3_TPC4_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_TPC_4_3] = mmDCORE3_TPC4_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_TPC_5_0] = mmDCORE3_TPC5_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_TPC_5_1] = mmDCORE3_TPC5_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_TPC_5_2] = mmDCORE3_TPC5_QM_BASE, + [GAUDI2_QUEUE_ID_DCORE3_TPC_5_3] = mmDCORE3_TPC5_QM_BASE, + [GAUDI2_QUEUE_ID_NIC_0_0] = mmNIC0_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_0_1] = mmNIC0_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_0_2] = mmNIC0_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_0_3] = mmNIC0_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_1_0] = mmNIC0_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_1_1] = mmNIC0_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_1_2] = mmNIC0_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_1_3] = mmNIC0_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_2_0] = mmNIC1_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_2_1] = mmNIC1_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_2_2] = mmNIC1_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_2_3] = mmNIC1_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_3_0] = mmNIC1_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_3_1] = mmNIC1_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_3_2] = mmNIC1_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_3_3] = mmNIC1_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_4_0] = mmNIC2_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_4_1] = mmNIC2_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_4_2] = mmNIC2_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_4_3] = mmNIC2_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_5_0] = mmNIC2_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_5_1] = mmNIC2_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_5_2] = mmNIC2_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_5_3] = mmNIC2_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_6_0] = mmNIC3_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_6_1] = mmNIC3_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_6_2] = mmNIC3_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_6_3] = mmNIC3_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_7_0] = mmNIC3_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_7_1] = mmNIC3_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_7_2] = mmNIC3_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_7_3] = mmNIC3_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_8_0] = mmNIC4_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_8_1] = mmNIC4_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_8_2] = mmNIC4_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_8_3] = mmNIC4_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_9_0] = mmNIC4_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_9_1] = mmNIC4_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_9_2] = mmNIC4_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_9_3] = mmNIC4_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_10_0] = mmNIC5_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_10_1] = mmNIC5_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_10_2] = mmNIC5_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_10_3] = mmNIC5_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_11_0] = mmNIC5_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_11_1] = mmNIC5_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_11_2] = mmNIC5_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_11_3] = mmNIC5_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_12_0] = mmNIC6_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_12_1] = mmNIC6_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_12_2] = mmNIC6_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_12_3] = mmNIC6_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_13_0] = mmNIC6_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_13_1] = mmNIC6_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_13_2] = mmNIC6_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_13_3] = mmNIC6_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_14_0] = mmNIC7_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_14_1] = mmNIC7_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_14_2] = mmNIC7_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_14_3] = mmNIC7_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_15_0] = mmNIC7_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_15_1] = mmNIC7_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_15_2] = mmNIC7_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_15_3] = mmNIC7_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_16_0] = mmNIC8_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_16_1] = mmNIC8_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_16_2] = mmNIC8_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_16_3] = mmNIC8_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_17_0] = mmNIC8_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_17_1] = mmNIC8_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_17_2] = mmNIC8_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_17_3] = mmNIC8_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_18_0] = mmNIC9_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_18_1] = mmNIC9_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_18_2] = mmNIC9_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_18_3] = mmNIC9_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_19_0] = mmNIC9_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_19_1] = mmNIC9_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_19_2] = mmNIC9_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_19_3] = mmNIC9_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_20_0] = mmNIC10_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_20_1] = mmNIC10_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_20_2] = mmNIC10_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_20_3] = mmNIC10_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_21_0] = mmNIC10_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_21_1] = mmNIC10_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_21_2] = mmNIC10_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_21_3] = mmNIC10_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_22_0] = mmNIC11_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_22_1] = mmNIC11_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_22_2] = mmNIC11_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_22_3] = mmNIC11_QM0_BASE, + [GAUDI2_QUEUE_ID_NIC_23_0] = mmNIC11_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_23_1] = mmNIC11_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_23_2] = mmNIC11_QM1_BASE, + [GAUDI2_QUEUE_ID_NIC_23_3] = mmNIC11_QM1_BASE, + [GAUDI2_QUEUE_ID_ROT_0_0] = mmROT0_QM_BASE, + [GAUDI2_QUEUE_ID_ROT_0_1] = mmROT0_QM_BASE, + [GAUDI2_QUEUE_ID_ROT_0_2] = mmROT0_QM_BASE, + [GAUDI2_QUEUE_ID_ROT_0_3] = mmROT0_QM_BASE, + [GAUDI2_QUEUE_ID_ROT_1_0] = mmROT1_QM_BASE, + [GAUDI2_QUEUE_ID_ROT_1_1] = mmROT1_QM_BASE, + [GAUDI2_QUEUE_ID_ROT_1_2] = mmROT1_QM_BASE, + [GAUDI2_QUEUE_ID_ROT_1_3] = mmROT1_QM_BASE +}; + +static const u32 gaudi2_arc_blocks_bases[NUM_ARC_CPUS] = { + [CPU_ID_SCHED_ARC0] = mmARC_FARM_ARC0_AUX_BASE, + [CPU_ID_SCHED_ARC1] = mmARC_FARM_ARC1_AUX_BASE, + [CPU_ID_SCHED_ARC2] = mmARC_FARM_ARC2_AUX_BASE, + [CPU_ID_SCHED_ARC3] = mmARC_FARM_ARC3_AUX_BASE, + [CPU_ID_SCHED_ARC4] = mmDCORE1_MME_QM_ARC_AUX_BASE, + [CPU_ID_SCHED_ARC5] = mmDCORE3_MME_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC0] = mmDCORE0_TPC0_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC1] = mmDCORE0_TPC1_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC2] = mmDCORE0_TPC2_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC3] = mmDCORE0_TPC3_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC4] = mmDCORE0_TPC4_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC5] = mmDCORE0_TPC5_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC6] = mmDCORE1_TPC0_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC7] = mmDCORE1_TPC1_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC8] = mmDCORE1_TPC2_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC9] = mmDCORE1_TPC3_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC10] = mmDCORE1_TPC4_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC11] = mmDCORE1_TPC5_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC12] = mmDCORE2_TPC0_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC13] = mmDCORE2_TPC1_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC14] = mmDCORE2_TPC2_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC15] = mmDCORE2_TPC3_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC16] = mmDCORE2_TPC4_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC17] = mmDCORE2_TPC5_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC18] = mmDCORE3_TPC0_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC19] = mmDCORE3_TPC1_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC20] = mmDCORE3_TPC2_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC21] = mmDCORE3_TPC3_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC22] = mmDCORE3_TPC4_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC23] = mmDCORE3_TPC5_QM_ARC_AUX_BASE, + [CPU_ID_TPC_QMAN_ARC24] = mmDCORE0_TPC6_QM_ARC_AUX_BASE, + [CPU_ID_MME_QMAN_ARC0] = mmDCORE0_MME_QM_ARC_AUX_BASE, + [CPU_ID_MME_QMAN_ARC1] = mmDCORE2_MME_QM_ARC_AUX_BASE, + [CPU_ID_EDMA_QMAN_ARC0] = mmDCORE0_EDMA0_QM_ARC_AUX_BASE, + [CPU_ID_EDMA_QMAN_ARC1] = mmDCORE0_EDMA1_QM_ARC_AUX_BASE, + [CPU_ID_EDMA_QMAN_ARC2] = mmDCORE1_EDMA0_QM_ARC_AUX_BASE, + [CPU_ID_EDMA_QMAN_ARC3] = mmDCORE1_EDMA1_QM_ARC_AUX_BASE, + [CPU_ID_EDMA_QMAN_ARC4] = mmDCORE2_EDMA0_QM_ARC_AUX_BASE, + [CPU_ID_EDMA_QMAN_ARC5] = mmDCORE2_EDMA1_QM_ARC_AUX_BASE, + [CPU_ID_EDMA_QMAN_ARC6] = mmDCORE3_EDMA0_QM_ARC_AUX_BASE, + [CPU_ID_EDMA_QMAN_ARC7] = mmDCORE3_EDMA1_QM_ARC_AUX_BASE, + [CPU_ID_PDMA_QMAN_ARC0] = mmPDMA0_QM_ARC_AUX_BASE, + [CPU_ID_PDMA_QMAN_ARC1] = mmPDMA1_QM_ARC_AUX_BASE, + [CPU_ID_ROT_QMAN_ARC0] = mmROT0_QM_ARC_AUX_BASE, + [CPU_ID_ROT_QMAN_ARC1] = mmROT1_QM_ARC_AUX_BASE, + [CPU_ID_NIC_QMAN_ARC0] = mmNIC0_QM_ARC_AUX0_BASE, + [CPU_ID_NIC_QMAN_ARC1] = mmNIC0_QM_ARC_AUX1_BASE, + [CPU_ID_NIC_QMAN_ARC2] = mmNIC1_QM_ARC_AUX0_BASE, + [CPU_ID_NIC_QMAN_ARC3] = mmNIC1_QM_ARC_AUX1_BASE, + [CPU_ID_NIC_QMAN_ARC4] = mmNIC2_QM_ARC_AUX0_BASE, + [CPU_ID_NIC_QMAN_ARC5] = mmNIC2_QM_ARC_AUX1_BASE, + [CPU_ID_NIC_QMAN_ARC6] = mmNIC3_QM_ARC_AUX0_BASE, + [CPU_ID_NIC_QMAN_ARC7] = mmNIC3_QM_ARC_AUX1_BASE, + [CPU_ID_NIC_QMAN_ARC8] = mmNIC4_QM_ARC_AUX0_BASE, + [CPU_ID_NIC_QMAN_ARC9] = mmNIC4_QM_ARC_AUX1_BASE, + [CPU_ID_NIC_QMAN_ARC10] = mmNIC5_QM_ARC_AUX0_BASE, + [CPU_ID_NIC_QMAN_ARC11] = mmNIC5_QM_ARC_AUX1_BASE, + [CPU_ID_NIC_QMAN_ARC12] = mmNIC6_QM_ARC_AUX0_BASE, + [CPU_ID_NIC_QMAN_ARC13] = mmNIC6_QM_ARC_AUX1_BASE, + [CPU_ID_NIC_QMAN_ARC14] = mmNIC7_QM_ARC_AUX0_BASE, + [CPU_ID_NIC_QMAN_ARC15] = mmNIC7_QM_ARC_AUX1_BASE, + [CPU_ID_NIC_QMAN_ARC16] = mmNIC8_QM_ARC_AUX0_BASE, + [CPU_ID_NIC_QMAN_ARC17] = mmNIC8_QM_ARC_AUX1_BASE, + [CPU_ID_NIC_QMAN_ARC18] = mmNIC9_QM_ARC_AUX0_BASE, + [CPU_ID_NIC_QMAN_ARC19] = mmNIC9_QM_ARC_AUX1_BASE, + [CPU_ID_NIC_QMAN_ARC20] = mmNIC10_QM_ARC_AUX0_BASE, + [CPU_ID_NIC_QMAN_ARC21] = mmNIC10_QM_ARC_AUX1_BASE, + [CPU_ID_NIC_QMAN_ARC22] = mmNIC11_QM_ARC_AUX0_BASE, + [CPU_ID_NIC_QMAN_ARC23] = mmNIC11_QM_ARC_AUX1_BASE, +}; + +static const u32 gaudi2_arc_dccm_bases[NUM_ARC_CPUS] = { + [CPU_ID_SCHED_ARC0] = mmARC_FARM_ARC0_DCCM0_BASE, + [CPU_ID_SCHED_ARC1] = mmARC_FARM_ARC1_DCCM0_BASE, + [CPU_ID_SCHED_ARC2] = mmARC_FARM_ARC2_DCCM0_BASE, + [CPU_ID_SCHED_ARC3] = mmARC_FARM_ARC3_DCCM0_BASE, + [CPU_ID_SCHED_ARC4] = mmDCORE1_MME_QM_ARC_DCCM_BASE, + [CPU_ID_SCHED_ARC5] = mmDCORE3_MME_QM_ARC_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC0] = mmDCORE0_TPC0_QM_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC1] = mmDCORE0_TPC1_QM_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC2] = mmDCORE0_TPC2_QM_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC3] = mmDCORE0_TPC3_QM_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC4] = mmDCORE0_TPC4_QM_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC5] = mmDCORE0_TPC5_QM_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC6] = mmDCORE1_TPC0_QM_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC7] = mmDCORE1_TPC1_QM_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC8] = mmDCORE1_TPC2_QM_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC9] = mmDCORE1_TPC3_QM_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC10] = mmDCORE1_TPC4_QM_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC11] = mmDCORE1_TPC5_QM_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC12] = mmDCORE2_TPC0_QM_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC13] = mmDCORE2_TPC1_QM_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC14] = mmDCORE2_TPC2_QM_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC15] = mmDCORE2_TPC3_QM_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC16] = mmDCORE2_TPC4_QM_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC17] = mmDCORE2_TPC5_QM_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC18] = mmDCORE3_TPC0_QM_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC19] = mmDCORE3_TPC1_QM_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC20] = mmDCORE3_TPC2_QM_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC21] = mmDCORE3_TPC3_QM_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC22] = mmDCORE3_TPC4_QM_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC23] = mmDCORE3_TPC5_QM_DCCM_BASE, + [CPU_ID_TPC_QMAN_ARC24] = mmDCORE0_TPC6_QM_DCCM_BASE, + [CPU_ID_MME_QMAN_ARC0] = mmDCORE0_MME_QM_ARC_DCCM_BASE, + [CPU_ID_MME_QMAN_ARC1] = mmDCORE2_MME_QM_ARC_DCCM_BASE, + [CPU_ID_EDMA_QMAN_ARC0] = mmDCORE0_EDMA0_QM_DCCM_BASE, + [CPU_ID_EDMA_QMAN_ARC1] = mmDCORE0_EDMA1_QM_DCCM_BASE, + [CPU_ID_EDMA_QMAN_ARC2] = mmDCORE1_EDMA0_QM_DCCM_BASE, + [CPU_ID_EDMA_QMAN_ARC3] = mmDCORE1_EDMA1_QM_DCCM_BASE, + [CPU_ID_EDMA_QMAN_ARC4] = mmDCORE2_EDMA0_QM_DCCM_BASE, + [CPU_ID_EDMA_QMAN_ARC5] = mmDCORE2_EDMA1_QM_DCCM_BASE, + [CPU_ID_EDMA_QMAN_ARC6] = mmDCORE3_EDMA0_QM_DCCM_BASE, + [CPU_ID_EDMA_QMAN_ARC7] = mmDCORE3_EDMA1_QM_DCCM_BASE, + [CPU_ID_PDMA_QMAN_ARC0] = mmPDMA0_QM_ARC_DCCM_BASE, + [CPU_ID_PDMA_QMAN_ARC1] = mmPDMA1_QM_ARC_DCCM_BASE, + [CPU_ID_ROT_QMAN_ARC0] = mmROT0_QM_ARC_DCCM_BASE, + [CPU_ID_ROT_QMAN_ARC1] = mmROT1_QM_ARC_DCCM_BASE, + [CPU_ID_NIC_QMAN_ARC0] = mmNIC0_QM_DCCM0_BASE, + [CPU_ID_NIC_QMAN_ARC1] = mmNIC0_QM_DCCM1_BASE, + [CPU_ID_NIC_QMAN_ARC2] = mmNIC1_QM_DCCM0_BASE, + [CPU_ID_NIC_QMAN_ARC3] = mmNIC1_QM_DCCM1_BASE, + [CPU_ID_NIC_QMAN_ARC4] = mmNIC2_QM_DCCM0_BASE, + [CPU_ID_NIC_QMAN_ARC5] = mmNIC2_QM_DCCM1_BASE, + [CPU_ID_NIC_QMAN_ARC6] = mmNIC3_QM_DCCM0_BASE, + [CPU_ID_NIC_QMAN_ARC7] = mmNIC3_QM_DCCM1_BASE, + [CPU_ID_NIC_QMAN_ARC8] = mmNIC4_QM_DCCM0_BASE, + [CPU_ID_NIC_QMAN_ARC9] = mmNIC4_QM_DCCM1_BASE, + [CPU_ID_NIC_QMAN_ARC10] = mmNIC5_QM_DCCM0_BASE, + [CPU_ID_NIC_QMAN_ARC11] = mmNIC5_QM_DCCM1_BASE, + [CPU_ID_NIC_QMAN_ARC12] = mmNIC6_QM_DCCM0_BASE, + [CPU_ID_NIC_QMAN_ARC13] = mmNIC6_QM_DCCM1_BASE, + [CPU_ID_NIC_QMAN_ARC14] = mmNIC7_QM_DCCM0_BASE, + [CPU_ID_NIC_QMAN_ARC15] = mmNIC7_QM_DCCM1_BASE, + [CPU_ID_NIC_QMAN_ARC16] = mmNIC8_QM_DCCM0_BASE, + [CPU_ID_NIC_QMAN_ARC17] = mmNIC8_QM_DCCM1_BASE, + [CPU_ID_NIC_QMAN_ARC18] = mmNIC9_QM_DCCM0_BASE, + [CPU_ID_NIC_QMAN_ARC19] = mmNIC9_QM_DCCM1_BASE, + [CPU_ID_NIC_QMAN_ARC20] = mmNIC10_QM_DCCM0_BASE, + [CPU_ID_NIC_QMAN_ARC21] = mmNIC10_QM_DCCM1_BASE, + [CPU_ID_NIC_QMAN_ARC22] = mmNIC11_QM_DCCM0_BASE, + [CPU_ID_NIC_QMAN_ARC23] = mmNIC11_QM_DCCM1_BASE, +}; + +const u32 gaudi2_mme_ctrl_lo_blocks_bases[MME_ID_SIZE] = { + [MME_ID_DCORE0] = mmDCORE0_MME_CTRL_LO_BASE, + [MME_ID_DCORE1] = mmDCORE1_MME_CTRL_LO_BASE, + [MME_ID_DCORE2] = mmDCORE2_MME_CTRL_LO_BASE, + [MME_ID_DCORE3] = mmDCORE3_MME_CTRL_LO_BASE, +}; + +static const u32 gaudi2_queue_id_to_arc_id[GAUDI2_QUEUE_ID_SIZE] = { + [GAUDI2_QUEUE_ID_PDMA_0_0] = CPU_ID_PDMA_QMAN_ARC0, + [GAUDI2_QUEUE_ID_PDMA_0_1] = CPU_ID_PDMA_QMAN_ARC0, + [GAUDI2_QUEUE_ID_PDMA_0_2] = CPU_ID_PDMA_QMAN_ARC0, + [GAUDI2_QUEUE_ID_PDMA_0_3] = CPU_ID_PDMA_QMAN_ARC0, + [GAUDI2_QUEUE_ID_PDMA_1_0] = CPU_ID_PDMA_QMAN_ARC1, + [GAUDI2_QUEUE_ID_PDMA_1_1] = CPU_ID_PDMA_QMAN_ARC1, + [GAUDI2_QUEUE_ID_PDMA_1_2] = CPU_ID_PDMA_QMAN_ARC1, + [GAUDI2_QUEUE_ID_PDMA_1_3] = CPU_ID_PDMA_QMAN_ARC1, + [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0] = CPU_ID_EDMA_QMAN_ARC0, + [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_1] = CPU_ID_EDMA_QMAN_ARC0, + [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_2] = CPU_ID_EDMA_QMAN_ARC0, + [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3] = CPU_ID_EDMA_QMAN_ARC0, + [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0] = CPU_ID_EDMA_QMAN_ARC1, + [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_1] = CPU_ID_EDMA_QMAN_ARC1, + [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_2] = CPU_ID_EDMA_QMAN_ARC1, + [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3] = CPU_ID_EDMA_QMAN_ARC1, + [GAUDI2_QUEUE_ID_DCORE0_MME_0_0] = CPU_ID_MME_QMAN_ARC0, + [GAUDI2_QUEUE_ID_DCORE0_MME_0_1] = CPU_ID_MME_QMAN_ARC0, + [GAUDI2_QUEUE_ID_DCORE0_MME_0_2] = CPU_ID_MME_QMAN_ARC0, + [GAUDI2_QUEUE_ID_DCORE0_MME_0_3] = CPU_ID_MME_QMAN_ARC0, + [GAUDI2_QUEUE_ID_DCORE0_TPC_0_0] = CPU_ID_TPC_QMAN_ARC0, + [GAUDI2_QUEUE_ID_DCORE0_TPC_0_1] = CPU_ID_TPC_QMAN_ARC0, + [GAUDI2_QUEUE_ID_DCORE0_TPC_0_2] = CPU_ID_TPC_QMAN_ARC0, + [GAUDI2_QUEUE_ID_DCORE0_TPC_0_3] = CPU_ID_TPC_QMAN_ARC0, + [GAUDI2_QUEUE_ID_DCORE0_TPC_1_0] = CPU_ID_TPC_QMAN_ARC1, + [GAUDI2_QUEUE_ID_DCORE0_TPC_1_1] = CPU_ID_TPC_QMAN_ARC1, + [GAUDI2_QUEUE_ID_DCORE0_TPC_1_2] = CPU_ID_TPC_QMAN_ARC1, + [GAUDI2_QUEUE_ID_DCORE0_TPC_1_3] = CPU_ID_TPC_QMAN_ARC1, + [GAUDI2_QUEUE_ID_DCORE0_TPC_2_0] = CPU_ID_TPC_QMAN_ARC2, + [GAUDI2_QUEUE_ID_DCORE0_TPC_2_1] = CPU_ID_TPC_QMAN_ARC2, + [GAUDI2_QUEUE_ID_DCORE0_TPC_2_2] = CPU_ID_TPC_QMAN_ARC2, + [GAUDI2_QUEUE_ID_DCORE0_TPC_2_3] = CPU_ID_TPC_QMAN_ARC2, + [GAUDI2_QUEUE_ID_DCORE0_TPC_3_0] = CPU_ID_TPC_QMAN_ARC3, + [GAUDI2_QUEUE_ID_DCORE0_TPC_3_1] = CPU_ID_TPC_QMAN_ARC3, + [GAUDI2_QUEUE_ID_DCORE0_TPC_3_2] = CPU_ID_TPC_QMAN_ARC3, + [GAUDI2_QUEUE_ID_DCORE0_TPC_3_3] = CPU_ID_TPC_QMAN_ARC3, + [GAUDI2_QUEUE_ID_DCORE0_TPC_4_0] = CPU_ID_TPC_QMAN_ARC4, + [GAUDI2_QUEUE_ID_DCORE0_TPC_4_1] = CPU_ID_TPC_QMAN_ARC4, + [GAUDI2_QUEUE_ID_DCORE0_TPC_4_2] = CPU_ID_TPC_QMAN_ARC4, + [GAUDI2_QUEUE_ID_DCORE0_TPC_4_3] = CPU_ID_TPC_QMAN_ARC4, + [GAUDI2_QUEUE_ID_DCORE0_TPC_5_0] = CPU_ID_TPC_QMAN_ARC5, + [GAUDI2_QUEUE_ID_DCORE0_TPC_5_1] = CPU_ID_TPC_QMAN_ARC5, + [GAUDI2_QUEUE_ID_DCORE0_TPC_5_2] = CPU_ID_TPC_QMAN_ARC5, + [GAUDI2_QUEUE_ID_DCORE0_TPC_5_3] = CPU_ID_TPC_QMAN_ARC5, + [GAUDI2_QUEUE_ID_DCORE0_TPC_6_0] = CPU_ID_TPC_QMAN_ARC24, + [GAUDI2_QUEUE_ID_DCORE0_TPC_6_1] = CPU_ID_TPC_QMAN_ARC24, + [GAUDI2_QUEUE_ID_DCORE0_TPC_6_2] = CPU_ID_TPC_QMAN_ARC24, + [GAUDI2_QUEUE_ID_DCORE0_TPC_6_3] = CPU_ID_TPC_QMAN_ARC24, + [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0] = CPU_ID_EDMA_QMAN_ARC2, + [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_1] = CPU_ID_EDMA_QMAN_ARC2, + [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_2] = CPU_ID_EDMA_QMAN_ARC2, + [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3] = CPU_ID_EDMA_QMAN_ARC2, + [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0] = CPU_ID_EDMA_QMAN_ARC3, + [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_1] = CPU_ID_EDMA_QMAN_ARC3, + [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_2] = CPU_ID_EDMA_QMAN_ARC3, + [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3] = CPU_ID_EDMA_QMAN_ARC3, + [GAUDI2_QUEUE_ID_DCORE1_MME_0_0] = CPU_ID_SCHED_ARC4, + [GAUDI2_QUEUE_ID_DCORE1_MME_0_1] = CPU_ID_SCHED_ARC4, + [GAUDI2_QUEUE_ID_DCORE1_MME_0_2] = CPU_ID_SCHED_ARC4, + [GAUDI2_QUEUE_ID_DCORE1_MME_0_3] = CPU_ID_SCHED_ARC4, + [GAUDI2_QUEUE_ID_DCORE1_TPC_0_0] = CPU_ID_TPC_QMAN_ARC6, + [GAUDI2_QUEUE_ID_DCORE1_TPC_0_1] = CPU_ID_TPC_QMAN_ARC6, + [GAUDI2_QUEUE_ID_DCORE1_TPC_0_2] = CPU_ID_TPC_QMAN_ARC6, + [GAUDI2_QUEUE_ID_DCORE1_TPC_0_3] = CPU_ID_TPC_QMAN_ARC6, + [GAUDI2_QUEUE_ID_DCORE1_TPC_1_0] = CPU_ID_TPC_QMAN_ARC7, + [GAUDI2_QUEUE_ID_DCORE1_TPC_1_1] = CPU_ID_TPC_QMAN_ARC7, + [GAUDI2_QUEUE_ID_DCORE1_TPC_1_2] = CPU_ID_TPC_QMAN_ARC7, + [GAUDI2_QUEUE_ID_DCORE1_TPC_1_3] = CPU_ID_TPC_QMAN_ARC7, + [GAUDI2_QUEUE_ID_DCORE1_TPC_2_0] = CPU_ID_TPC_QMAN_ARC8, + [GAUDI2_QUEUE_ID_DCORE1_TPC_2_1] = CPU_ID_TPC_QMAN_ARC8, + [GAUDI2_QUEUE_ID_DCORE1_TPC_2_2] = CPU_ID_TPC_QMAN_ARC8, + [GAUDI2_QUEUE_ID_DCORE1_TPC_2_3] = CPU_ID_TPC_QMAN_ARC8, + [GAUDI2_QUEUE_ID_DCORE1_TPC_3_0] = CPU_ID_TPC_QMAN_ARC9, + [GAUDI2_QUEUE_ID_DCORE1_TPC_3_1] = CPU_ID_TPC_QMAN_ARC9, + [GAUDI2_QUEUE_ID_DCORE1_TPC_3_2] = CPU_ID_TPC_QMAN_ARC9, + [GAUDI2_QUEUE_ID_DCORE1_TPC_3_3] = CPU_ID_TPC_QMAN_ARC9, + [GAUDI2_QUEUE_ID_DCORE1_TPC_4_0] = CPU_ID_TPC_QMAN_ARC10, + [GAUDI2_QUEUE_ID_DCORE1_TPC_4_1] = CPU_ID_TPC_QMAN_ARC10, + [GAUDI2_QUEUE_ID_DCORE1_TPC_4_2] = CPU_ID_TPC_QMAN_ARC10, + [GAUDI2_QUEUE_ID_DCORE1_TPC_4_3] = CPU_ID_TPC_QMAN_ARC10, + [GAUDI2_QUEUE_ID_DCORE1_TPC_5_0] = CPU_ID_TPC_QMAN_ARC11, + [GAUDI2_QUEUE_ID_DCORE1_TPC_5_1] = CPU_ID_TPC_QMAN_ARC11, + [GAUDI2_QUEUE_ID_DCORE1_TPC_5_2] = CPU_ID_TPC_QMAN_ARC11, + [GAUDI2_QUEUE_ID_DCORE1_TPC_5_3] = CPU_ID_TPC_QMAN_ARC11, + [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0] = CPU_ID_EDMA_QMAN_ARC4, + [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_1] = CPU_ID_EDMA_QMAN_ARC4, + [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_2] = CPU_ID_EDMA_QMAN_ARC4, + [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3] = CPU_ID_EDMA_QMAN_ARC4, + [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0] = CPU_ID_EDMA_QMAN_ARC5, + [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_1] = CPU_ID_EDMA_QMAN_ARC5, + [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_2] = CPU_ID_EDMA_QMAN_ARC5, + [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3] = CPU_ID_EDMA_QMAN_ARC5, + [GAUDI2_QUEUE_ID_DCORE2_MME_0_0] = CPU_ID_MME_QMAN_ARC1, + [GAUDI2_QUEUE_ID_DCORE2_MME_0_1] = CPU_ID_MME_QMAN_ARC1, + [GAUDI2_QUEUE_ID_DCORE2_MME_0_2] = CPU_ID_MME_QMAN_ARC1, + [GAUDI2_QUEUE_ID_DCORE2_MME_0_3] = CPU_ID_MME_QMAN_ARC1, + [GAUDI2_QUEUE_ID_DCORE2_TPC_0_0] = CPU_ID_TPC_QMAN_ARC12, + [GAUDI2_QUEUE_ID_DCORE2_TPC_0_1] = CPU_ID_TPC_QMAN_ARC12, + [GAUDI2_QUEUE_ID_DCORE2_TPC_0_2] = CPU_ID_TPC_QMAN_ARC12, + [GAUDI2_QUEUE_ID_DCORE2_TPC_0_3] = CPU_ID_TPC_QMAN_ARC12, + [GAUDI2_QUEUE_ID_DCORE2_TPC_1_0] = CPU_ID_TPC_QMAN_ARC13, + [GAUDI2_QUEUE_ID_DCORE2_TPC_1_1] = CPU_ID_TPC_QMAN_ARC13, + [GAUDI2_QUEUE_ID_DCORE2_TPC_1_2] = CPU_ID_TPC_QMAN_ARC13, + [GAUDI2_QUEUE_ID_DCORE2_TPC_1_3] = CPU_ID_TPC_QMAN_ARC13, + [GAUDI2_QUEUE_ID_DCORE2_TPC_2_0] = CPU_ID_TPC_QMAN_ARC14, + [GAUDI2_QUEUE_ID_DCORE2_TPC_2_1] = CPU_ID_TPC_QMAN_ARC14, + [GAUDI2_QUEUE_ID_DCORE2_TPC_2_2] = CPU_ID_TPC_QMAN_ARC14, + [GAUDI2_QUEUE_ID_DCORE2_TPC_2_3] = CPU_ID_TPC_QMAN_ARC14, + [GAUDI2_QUEUE_ID_DCORE2_TPC_3_0] = CPU_ID_TPC_QMAN_ARC15, + [GAUDI2_QUEUE_ID_DCORE2_TPC_3_1] = CPU_ID_TPC_QMAN_ARC15, + [GAUDI2_QUEUE_ID_DCORE2_TPC_3_2] = CPU_ID_TPC_QMAN_ARC15, + [GAUDI2_QUEUE_ID_DCORE2_TPC_3_3] = CPU_ID_TPC_QMAN_ARC15, + [GAUDI2_QUEUE_ID_DCORE2_TPC_4_0] = CPU_ID_TPC_QMAN_ARC16, + [GAUDI2_QUEUE_ID_DCORE2_TPC_4_1] = CPU_ID_TPC_QMAN_ARC16, + [GAUDI2_QUEUE_ID_DCORE2_TPC_4_2] = CPU_ID_TPC_QMAN_ARC16, + [GAUDI2_QUEUE_ID_DCORE2_TPC_4_3] = CPU_ID_TPC_QMAN_ARC16, + [GAUDI2_QUEUE_ID_DCORE2_TPC_5_0] = CPU_ID_TPC_QMAN_ARC17, + [GAUDI2_QUEUE_ID_DCORE2_TPC_5_1] = CPU_ID_TPC_QMAN_ARC17, + [GAUDI2_QUEUE_ID_DCORE2_TPC_5_2] = CPU_ID_TPC_QMAN_ARC17, + [GAUDI2_QUEUE_ID_DCORE2_TPC_5_3] = CPU_ID_TPC_QMAN_ARC17, + [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0] = CPU_ID_EDMA_QMAN_ARC6, + [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_1] = CPU_ID_EDMA_QMAN_ARC6, + [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_2] = CPU_ID_EDMA_QMAN_ARC6, + [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3] = CPU_ID_EDMA_QMAN_ARC6, + [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0] = CPU_ID_EDMA_QMAN_ARC7, + [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_1] = CPU_ID_EDMA_QMAN_ARC7, + [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_2] = CPU_ID_EDMA_QMAN_ARC7, + [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3] = CPU_ID_EDMA_QMAN_ARC7, + [GAUDI2_QUEUE_ID_DCORE3_MME_0_0] = CPU_ID_SCHED_ARC5, + [GAUDI2_QUEUE_ID_DCORE3_MME_0_1] = CPU_ID_SCHED_ARC5, + [GAUDI2_QUEUE_ID_DCORE3_MME_0_2] = CPU_ID_SCHED_ARC5, + [GAUDI2_QUEUE_ID_DCORE3_MME_0_3] = CPU_ID_SCHED_ARC5, + [GAUDI2_QUEUE_ID_DCORE3_TPC_0_0] = CPU_ID_TPC_QMAN_ARC18, + [GAUDI2_QUEUE_ID_DCORE3_TPC_0_1] = CPU_ID_TPC_QMAN_ARC18, + [GAUDI2_QUEUE_ID_DCORE3_TPC_0_2] = CPU_ID_TPC_QMAN_ARC18, + [GAUDI2_QUEUE_ID_DCORE3_TPC_0_3] = CPU_ID_TPC_QMAN_ARC18, + [GAUDI2_QUEUE_ID_DCORE3_TPC_1_0] = CPU_ID_TPC_QMAN_ARC19, + [GAUDI2_QUEUE_ID_DCORE3_TPC_1_1] = CPU_ID_TPC_QMAN_ARC19, + [GAUDI2_QUEUE_ID_DCORE3_TPC_1_2] = CPU_ID_TPC_QMAN_ARC19, + [GAUDI2_QUEUE_ID_DCORE3_TPC_1_3] = CPU_ID_TPC_QMAN_ARC19, + [GAUDI2_QUEUE_ID_DCORE3_TPC_2_0] = CPU_ID_TPC_QMAN_ARC20, + [GAUDI2_QUEUE_ID_DCORE3_TPC_2_1] = CPU_ID_TPC_QMAN_ARC20, + [GAUDI2_QUEUE_ID_DCORE3_TPC_2_2] = CPU_ID_TPC_QMAN_ARC20, + [GAUDI2_QUEUE_ID_DCORE3_TPC_2_3] = CPU_ID_TPC_QMAN_ARC20, + [GAUDI2_QUEUE_ID_DCORE3_TPC_3_0] = CPU_ID_TPC_QMAN_ARC21, + [GAUDI2_QUEUE_ID_DCORE3_TPC_3_1] = CPU_ID_TPC_QMAN_ARC21, + [GAUDI2_QUEUE_ID_DCORE3_TPC_3_2] = CPU_ID_TPC_QMAN_ARC21, + [GAUDI2_QUEUE_ID_DCORE3_TPC_3_3] = CPU_ID_TPC_QMAN_ARC21, + [GAUDI2_QUEUE_ID_DCORE3_TPC_4_0] = CPU_ID_TPC_QMAN_ARC22, + [GAUDI2_QUEUE_ID_DCORE3_TPC_4_1] = CPU_ID_TPC_QMAN_ARC22, + [GAUDI2_QUEUE_ID_DCORE3_TPC_4_2] = CPU_ID_TPC_QMAN_ARC22, + [GAUDI2_QUEUE_ID_DCORE3_TPC_4_3] = CPU_ID_TPC_QMAN_ARC22, + [GAUDI2_QUEUE_ID_DCORE3_TPC_5_0] = CPU_ID_TPC_QMAN_ARC23, + [GAUDI2_QUEUE_ID_DCORE3_TPC_5_1] = CPU_ID_TPC_QMAN_ARC23, + [GAUDI2_QUEUE_ID_DCORE3_TPC_5_2] = CPU_ID_TPC_QMAN_ARC23, + [GAUDI2_QUEUE_ID_DCORE3_TPC_5_3] = CPU_ID_TPC_QMAN_ARC23, + [GAUDI2_QUEUE_ID_NIC_0_0] = CPU_ID_NIC_QMAN_ARC0, + [GAUDI2_QUEUE_ID_NIC_0_1] = CPU_ID_NIC_QMAN_ARC0, + [GAUDI2_QUEUE_ID_NIC_0_2] = CPU_ID_NIC_QMAN_ARC0, + [GAUDI2_QUEUE_ID_NIC_0_3] = CPU_ID_NIC_QMAN_ARC0, + [GAUDI2_QUEUE_ID_NIC_1_0] = CPU_ID_NIC_QMAN_ARC1, + [GAUDI2_QUEUE_ID_NIC_1_1] = CPU_ID_NIC_QMAN_ARC1, + [GAUDI2_QUEUE_ID_NIC_1_2] = CPU_ID_NIC_QMAN_ARC1, + [GAUDI2_QUEUE_ID_NIC_1_3] = CPU_ID_NIC_QMAN_ARC1, + [GAUDI2_QUEUE_ID_NIC_2_0] = CPU_ID_NIC_QMAN_ARC2, + [GAUDI2_QUEUE_ID_NIC_2_1] = CPU_ID_NIC_QMAN_ARC2, + [GAUDI2_QUEUE_ID_NIC_2_2] = CPU_ID_NIC_QMAN_ARC2, + [GAUDI2_QUEUE_ID_NIC_2_3] = CPU_ID_NIC_QMAN_ARC2, + [GAUDI2_QUEUE_ID_NIC_3_0] = CPU_ID_NIC_QMAN_ARC3, + [GAUDI2_QUEUE_ID_NIC_3_1] = CPU_ID_NIC_QMAN_ARC3, + [GAUDI2_QUEUE_ID_NIC_3_2] = CPU_ID_NIC_QMAN_ARC3, + [GAUDI2_QUEUE_ID_NIC_3_3] = CPU_ID_NIC_QMAN_ARC3, + [GAUDI2_QUEUE_ID_NIC_4_0] = CPU_ID_NIC_QMAN_ARC4, + [GAUDI2_QUEUE_ID_NIC_4_1] = CPU_ID_NIC_QMAN_ARC4, + [GAUDI2_QUEUE_ID_NIC_4_2] = CPU_ID_NIC_QMAN_ARC4, + [GAUDI2_QUEUE_ID_NIC_4_3] = CPU_ID_NIC_QMAN_ARC4, + [GAUDI2_QUEUE_ID_NIC_5_0] = CPU_ID_NIC_QMAN_ARC5, + [GAUDI2_QUEUE_ID_NIC_5_1] = CPU_ID_NIC_QMAN_ARC5, + [GAUDI2_QUEUE_ID_NIC_5_2] = CPU_ID_NIC_QMAN_ARC5, + [GAUDI2_QUEUE_ID_NIC_5_3] = CPU_ID_NIC_QMAN_ARC5, + [GAUDI2_QUEUE_ID_NIC_6_0] = CPU_ID_NIC_QMAN_ARC6, + [GAUDI2_QUEUE_ID_NIC_6_1] = CPU_ID_NIC_QMAN_ARC6, + [GAUDI2_QUEUE_ID_NIC_6_2] = CPU_ID_NIC_QMAN_ARC6, + [GAUDI2_QUEUE_ID_NIC_6_3] = CPU_ID_NIC_QMAN_ARC6, + [GAUDI2_QUEUE_ID_NIC_7_0] = CPU_ID_NIC_QMAN_ARC7, + [GAUDI2_QUEUE_ID_NIC_7_1] = CPU_ID_NIC_QMAN_ARC7, + [GAUDI2_QUEUE_ID_NIC_7_2] = CPU_ID_NIC_QMAN_ARC7, + [GAUDI2_QUEUE_ID_NIC_7_3] = CPU_ID_NIC_QMAN_ARC7, + [GAUDI2_QUEUE_ID_NIC_8_0] = CPU_ID_NIC_QMAN_ARC8, + [GAUDI2_QUEUE_ID_NIC_8_1] = CPU_ID_NIC_QMAN_ARC8, + [GAUDI2_QUEUE_ID_NIC_8_2] = CPU_ID_NIC_QMAN_ARC8, + [GAUDI2_QUEUE_ID_NIC_8_3] = CPU_ID_NIC_QMAN_ARC8, + [GAUDI2_QUEUE_ID_NIC_9_0] = CPU_ID_NIC_QMAN_ARC9, + [GAUDI2_QUEUE_ID_NIC_9_1] = CPU_ID_NIC_QMAN_ARC9, + [GAUDI2_QUEUE_ID_NIC_9_2] = CPU_ID_NIC_QMAN_ARC9, + [GAUDI2_QUEUE_ID_NIC_9_3] = CPU_ID_NIC_QMAN_ARC9, + [GAUDI2_QUEUE_ID_NIC_10_0] = CPU_ID_NIC_QMAN_ARC10, + [GAUDI2_QUEUE_ID_NIC_10_1] = CPU_ID_NIC_QMAN_ARC10, + [GAUDI2_QUEUE_ID_NIC_10_2] = CPU_ID_NIC_QMAN_ARC10, + [GAUDI2_QUEUE_ID_NIC_10_3] = CPU_ID_NIC_QMAN_ARC10, + [GAUDI2_QUEUE_ID_NIC_11_0] = CPU_ID_NIC_QMAN_ARC11, + [GAUDI2_QUEUE_ID_NIC_11_1] = CPU_ID_NIC_QMAN_ARC11, + [GAUDI2_QUEUE_ID_NIC_11_2] = CPU_ID_NIC_QMAN_ARC11, + [GAUDI2_QUEUE_ID_NIC_11_3] = CPU_ID_NIC_QMAN_ARC11, + [GAUDI2_QUEUE_ID_NIC_12_0] = CPU_ID_NIC_QMAN_ARC12, + [GAUDI2_QUEUE_ID_NIC_12_1] = CPU_ID_NIC_QMAN_ARC12, + [GAUDI2_QUEUE_ID_NIC_12_2] = CPU_ID_NIC_QMAN_ARC12, + [GAUDI2_QUEUE_ID_NIC_12_3] = CPU_ID_NIC_QMAN_ARC12, + [GAUDI2_QUEUE_ID_NIC_13_0] = CPU_ID_NIC_QMAN_ARC13, + [GAUDI2_QUEUE_ID_NIC_13_1] = CPU_ID_NIC_QMAN_ARC13, + [GAUDI2_QUEUE_ID_NIC_13_2] = CPU_ID_NIC_QMAN_ARC13, + [GAUDI2_QUEUE_ID_NIC_13_3] = CPU_ID_NIC_QMAN_ARC13, + [GAUDI2_QUEUE_ID_NIC_14_0] = CPU_ID_NIC_QMAN_ARC14, + [GAUDI2_QUEUE_ID_NIC_14_1] = CPU_ID_NIC_QMAN_ARC14, + [GAUDI2_QUEUE_ID_NIC_14_2] = CPU_ID_NIC_QMAN_ARC14, + [GAUDI2_QUEUE_ID_NIC_14_3] = CPU_ID_NIC_QMAN_ARC14, + [GAUDI2_QUEUE_ID_NIC_15_0] = CPU_ID_NIC_QMAN_ARC15, + [GAUDI2_QUEUE_ID_NIC_15_1] = CPU_ID_NIC_QMAN_ARC15, + [GAUDI2_QUEUE_ID_NIC_15_2] = CPU_ID_NIC_QMAN_ARC15, + [GAUDI2_QUEUE_ID_NIC_15_3] = CPU_ID_NIC_QMAN_ARC15, + [GAUDI2_QUEUE_ID_NIC_16_0] = CPU_ID_NIC_QMAN_ARC16, + [GAUDI2_QUEUE_ID_NIC_16_1] = CPU_ID_NIC_QMAN_ARC16, + [GAUDI2_QUEUE_ID_NIC_16_2] = CPU_ID_NIC_QMAN_ARC16, + [GAUDI2_QUEUE_ID_NIC_16_3] = CPU_ID_NIC_QMAN_ARC16, + [GAUDI2_QUEUE_ID_NIC_17_0] = CPU_ID_NIC_QMAN_ARC17, + [GAUDI2_QUEUE_ID_NIC_17_1] = CPU_ID_NIC_QMAN_ARC17, + [GAUDI2_QUEUE_ID_NIC_17_2] = CPU_ID_NIC_QMAN_ARC17, + [GAUDI2_QUEUE_ID_NIC_17_3] = CPU_ID_NIC_QMAN_ARC17, + [GAUDI2_QUEUE_ID_NIC_18_0] = CPU_ID_NIC_QMAN_ARC18, + [GAUDI2_QUEUE_ID_NIC_18_1] = CPU_ID_NIC_QMAN_ARC18, + [GAUDI2_QUEUE_ID_NIC_18_2] = CPU_ID_NIC_QMAN_ARC18, + [GAUDI2_QUEUE_ID_NIC_18_3] = CPU_ID_NIC_QMAN_ARC18, + [GAUDI2_QUEUE_ID_NIC_19_0] = CPU_ID_NIC_QMAN_ARC19, + [GAUDI2_QUEUE_ID_NIC_19_1] = CPU_ID_NIC_QMAN_ARC19, + [GAUDI2_QUEUE_ID_NIC_19_2] = CPU_ID_NIC_QMAN_ARC19, + [GAUDI2_QUEUE_ID_NIC_19_3] = CPU_ID_NIC_QMAN_ARC19, + [GAUDI2_QUEUE_ID_NIC_20_0] = CPU_ID_NIC_QMAN_ARC20, + [GAUDI2_QUEUE_ID_NIC_20_1] = CPU_ID_NIC_QMAN_ARC20, + [GAUDI2_QUEUE_ID_NIC_20_2] = CPU_ID_NIC_QMAN_ARC20, + [GAUDI2_QUEUE_ID_NIC_20_3] = CPU_ID_NIC_QMAN_ARC20, + [GAUDI2_QUEUE_ID_NIC_21_0] = CPU_ID_NIC_QMAN_ARC21, + [GAUDI2_QUEUE_ID_NIC_21_1] = CPU_ID_NIC_QMAN_ARC21, + [GAUDI2_QUEUE_ID_NIC_21_2] = CPU_ID_NIC_QMAN_ARC21, + [GAUDI2_QUEUE_ID_NIC_21_3] = CPU_ID_NIC_QMAN_ARC21, + [GAUDI2_QUEUE_ID_NIC_22_0] = CPU_ID_NIC_QMAN_ARC22, + [GAUDI2_QUEUE_ID_NIC_22_1] = CPU_ID_NIC_QMAN_ARC22, + [GAUDI2_QUEUE_ID_NIC_22_2] = CPU_ID_NIC_QMAN_ARC22, + [GAUDI2_QUEUE_ID_NIC_22_3] = CPU_ID_NIC_QMAN_ARC22, + [GAUDI2_QUEUE_ID_NIC_23_0] = CPU_ID_NIC_QMAN_ARC23, + [GAUDI2_QUEUE_ID_NIC_23_1] = CPU_ID_NIC_QMAN_ARC23, + [GAUDI2_QUEUE_ID_NIC_23_2] = CPU_ID_NIC_QMAN_ARC23, + [GAUDI2_QUEUE_ID_NIC_23_3] = CPU_ID_NIC_QMAN_ARC23, + [GAUDI2_QUEUE_ID_ROT_0_0] = CPU_ID_ROT_QMAN_ARC0, + [GAUDI2_QUEUE_ID_ROT_0_1] = CPU_ID_ROT_QMAN_ARC0, + [GAUDI2_QUEUE_ID_ROT_0_2] = CPU_ID_ROT_QMAN_ARC0, + [GAUDI2_QUEUE_ID_ROT_0_3] = CPU_ID_ROT_QMAN_ARC0, + [GAUDI2_QUEUE_ID_ROT_1_0] = CPU_ID_ROT_QMAN_ARC1, + [GAUDI2_QUEUE_ID_ROT_1_1] = CPU_ID_ROT_QMAN_ARC1, + [GAUDI2_QUEUE_ID_ROT_1_2] = CPU_ID_ROT_QMAN_ARC1, + [GAUDI2_QUEUE_ID_ROT_1_3] = CPU_ID_ROT_QMAN_ARC1 +}; + +const u32 gaudi2_dma_core_blocks_bases[DMA_CORE_ID_SIZE] = { + [DMA_CORE_ID_PDMA0] = mmPDMA0_CORE_BASE, + [DMA_CORE_ID_PDMA1] = mmPDMA1_CORE_BASE, + [DMA_CORE_ID_EDMA0] = mmDCORE0_EDMA0_CORE_BASE, + [DMA_CORE_ID_EDMA1] = mmDCORE0_EDMA1_CORE_BASE, + [DMA_CORE_ID_EDMA2] = mmDCORE1_EDMA0_CORE_BASE, + [DMA_CORE_ID_EDMA3] = mmDCORE1_EDMA1_CORE_BASE, + [DMA_CORE_ID_EDMA4] = mmDCORE2_EDMA0_CORE_BASE, + [DMA_CORE_ID_EDMA5] = mmDCORE2_EDMA1_CORE_BASE, + [DMA_CORE_ID_EDMA6] = mmDCORE3_EDMA0_CORE_BASE, + [DMA_CORE_ID_EDMA7] = mmDCORE3_EDMA1_CORE_BASE, + [DMA_CORE_ID_KDMA] = mmARC_FARM_KDMA_BASE +}; + +const u32 gaudi2_mme_acc_blocks_bases[MME_ID_SIZE] = { + [MME_ID_DCORE0] = mmDCORE0_MME_ACC_BASE, + [MME_ID_DCORE1] = mmDCORE1_MME_ACC_BASE, + [MME_ID_DCORE2] = mmDCORE2_MME_ACC_BASE, + [MME_ID_DCORE3] = mmDCORE3_MME_ACC_BASE +}; + +static const u32 gaudi2_tpc_cfg_blocks_bases[TPC_ID_SIZE] = { + [TPC_ID_DCORE0_TPC0] = mmDCORE0_TPC0_CFG_BASE, + [TPC_ID_DCORE0_TPC1] = mmDCORE0_TPC1_CFG_BASE, + [TPC_ID_DCORE0_TPC2] = mmDCORE0_TPC2_CFG_BASE, + [TPC_ID_DCORE0_TPC3] = mmDCORE0_TPC3_CFG_BASE, + [TPC_ID_DCORE0_TPC4] = mmDCORE0_TPC4_CFG_BASE, + [TPC_ID_DCORE0_TPC5] = mmDCORE0_TPC5_CFG_BASE, + [TPC_ID_DCORE1_TPC0] = mmDCORE1_TPC0_CFG_BASE, + [TPC_ID_DCORE1_TPC1] = mmDCORE1_TPC1_CFG_BASE, + [TPC_ID_DCORE1_TPC2] = mmDCORE1_TPC2_CFG_BASE, + [TPC_ID_DCORE1_TPC3] = mmDCORE1_TPC3_CFG_BASE, + [TPC_ID_DCORE1_TPC4] = mmDCORE1_TPC4_CFG_BASE, + [TPC_ID_DCORE1_TPC5] = mmDCORE1_TPC5_CFG_BASE, + [TPC_ID_DCORE2_TPC0] = mmDCORE2_TPC0_CFG_BASE, + [TPC_ID_DCORE2_TPC1] = mmDCORE2_TPC1_CFG_BASE, + [TPC_ID_DCORE2_TPC2] = mmDCORE2_TPC2_CFG_BASE, + [TPC_ID_DCORE2_TPC3] = mmDCORE2_TPC3_CFG_BASE, + [TPC_ID_DCORE2_TPC4] = mmDCORE2_TPC4_CFG_BASE, + [TPC_ID_DCORE2_TPC5] = mmDCORE2_TPC5_CFG_BASE, + [TPC_ID_DCORE3_TPC0] = mmDCORE3_TPC0_CFG_BASE, + [TPC_ID_DCORE3_TPC1] = mmDCORE3_TPC1_CFG_BASE, + [TPC_ID_DCORE3_TPC2] = mmDCORE3_TPC2_CFG_BASE, + [TPC_ID_DCORE3_TPC3] = mmDCORE3_TPC3_CFG_BASE, + [TPC_ID_DCORE3_TPC4] = mmDCORE3_TPC4_CFG_BASE, + [TPC_ID_DCORE3_TPC5] = mmDCORE3_TPC5_CFG_BASE, + [TPC_ID_DCORE0_TPC6] = mmDCORE0_TPC6_CFG_BASE, +}; + +const u32 gaudi2_rot_blocks_bases[ROTATOR_ID_SIZE] = { + [ROTATOR_ID_0] = mmROT0_BASE, + [ROTATOR_ID_1] = mmROT1_BASE +}; + +static const u32 gaudi2_tpc_id_to_queue_id[TPC_ID_SIZE] = { + [TPC_ID_DCORE0_TPC0] = GAUDI2_QUEUE_ID_DCORE0_TPC_0_0, + [TPC_ID_DCORE0_TPC1] = GAUDI2_QUEUE_ID_DCORE0_TPC_1_0, + [TPC_ID_DCORE0_TPC2] = GAUDI2_QUEUE_ID_DCORE0_TPC_2_0, + [TPC_ID_DCORE0_TPC3] = GAUDI2_QUEUE_ID_DCORE0_TPC_3_0, + [TPC_ID_DCORE0_TPC4] = GAUDI2_QUEUE_ID_DCORE0_TPC_4_0, + [TPC_ID_DCORE0_TPC5] = GAUDI2_QUEUE_ID_DCORE0_TPC_5_0, + [TPC_ID_DCORE1_TPC0] = GAUDI2_QUEUE_ID_DCORE1_TPC_0_0, + [TPC_ID_DCORE1_TPC1] = GAUDI2_QUEUE_ID_DCORE1_TPC_1_0, + [TPC_ID_DCORE1_TPC2] = GAUDI2_QUEUE_ID_DCORE1_TPC_2_0, + [TPC_ID_DCORE1_TPC3] = GAUDI2_QUEUE_ID_DCORE1_TPC_3_0, + [TPC_ID_DCORE1_TPC4] = GAUDI2_QUEUE_ID_DCORE1_TPC_4_0, + [TPC_ID_DCORE1_TPC5] = GAUDI2_QUEUE_ID_DCORE1_TPC_5_0, + [TPC_ID_DCORE2_TPC0] = GAUDI2_QUEUE_ID_DCORE2_TPC_0_0, + [TPC_ID_DCORE2_TPC1] = GAUDI2_QUEUE_ID_DCORE2_TPC_1_0, + [TPC_ID_DCORE2_TPC2] = GAUDI2_QUEUE_ID_DCORE2_TPC_2_0, + [TPC_ID_DCORE2_TPC3] = GAUDI2_QUEUE_ID_DCORE2_TPC_3_0, + [TPC_ID_DCORE2_TPC4] = GAUDI2_QUEUE_ID_DCORE2_TPC_4_0, + [TPC_ID_DCORE2_TPC5] = GAUDI2_QUEUE_ID_DCORE2_TPC_5_0, + [TPC_ID_DCORE3_TPC0] = GAUDI2_QUEUE_ID_DCORE3_TPC_0_0, + [TPC_ID_DCORE3_TPC1] = GAUDI2_QUEUE_ID_DCORE3_TPC_1_0, + [TPC_ID_DCORE3_TPC2] = GAUDI2_QUEUE_ID_DCORE3_TPC_2_0, + [TPC_ID_DCORE3_TPC3] = GAUDI2_QUEUE_ID_DCORE3_TPC_3_0, + [TPC_ID_DCORE3_TPC4] = GAUDI2_QUEUE_ID_DCORE3_TPC_4_0, + [TPC_ID_DCORE3_TPC5] = GAUDI2_QUEUE_ID_DCORE3_TPC_5_0, + [TPC_ID_DCORE0_TPC6] = GAUDI2_QUEUE_ID_DCORE0_TPC_6_0, +}; + +static const u32 gaudi2_rot_id_to_queue_id[ROTATOR_ID_SIZE] = { + [ROTATOR_ID_0] = GAUDI2_QUEUE_ID_ROT_0_0, + [ROTATOR_ID_1] = GAUDI2_QUEUE_ID_ROT_1_0, +}; + +const u32 edma_stream_base[NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES] = { + GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0, + GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0, + GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0, + GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0, + GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0, + GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0, + GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0, + GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0, +}; + +static const char gaudi2_vdec_irq_name[GAUDI2_VDEC_MSIX_ENTRIES][GAUDI2_MAX_STRING_LEN] = { + "gaudi2 vdec 0_0", "gaudi2 vdec 0_0 abnormal", + "gaudi2 vdec 0_1", "gaudi2 vdec 0_1 abnormal", + "gaudi2 vdec 1_0", "gaudi2 vdec 1_0 abnormal", + "gaudi2 vdec 1_1", "gaudi2 vdec 1_1 abnormal", + "gaudi2 vdec 2_0", "gaudi2 vdec 2_0 abnormal", + "gaudi2 vdec 2_1", "gaudi2 vdec 2_1 abnormal", + "gaudi2 vdec 3_0", "gaudi2 vdec 3_0 abnormal", + "gaudi2 vdec 3_1", "gaudi2 vdec 3_1 abnormal", + "gaudi2 vdec s_0", "gaudi2 vdec s_0 abnormal", + "gaudi2 vdec s_1", "gaudi2 vdec s_1 abnormal" +}; + +static const u32 rtr_coordinates_to_rtr_id[NUM_OF_RTR_PER_DCORE * NUM_OF_DCORES] = { + RTR_ID_X_Y(2, 4), + RTR_ID_X_Y(3, 4), + RTR_ID_X_Y(4, 4), + RTR_ID_X_Y(5, 4), + RTR_ID_X_Y(6, 4), + RTR_ID_X_Y(7, 4), + RTR_ID_X_Y(8, 4), + RTR_ID_X_Y(9, 4), + RTR_ID_X_Y(10, 4), + RTR_ID_X_Y(11, 4), + RTR_ID_X_Y(12, 4), + RTR_ID_X_Y(13, 4), + RTR_ID_X_Y(14, 4), + RTR_ID_X_Y(15, 4), + RTR_ID_X_Y(16, 4), + RTR_ID_X_Y(17, 4), + RTR_ID_X_Y(2, 11), + RTR_ID_X_Y(3, 11), + RTR_ID_X_Y(4, 11), + RTR_ID_X_Y(5, 11), + RTR_ID_X_Y(6, 11), + RTR_ID_X_Y(7, 11), + RTR_ID_X_Y(8, 11), + RTR_ID_X_Y(9, 11), + RTR_ID_X_Y(0, 0),/* 24 no id */ + RTR_ID_X_Y(0, 0),/* 25 no id */ + RTR_ID_X_Y(0, 0),/* 26 no id */ + RTR_ID_X_Y(0, 0),/* 27 no id */ + RTR_ID_X_Y(14, 11), + RTR_ID_X_Y(15, 11), + RTR_ID_X_Y(16, 11), + RTR_ID_X_Y(17, 11) +}; + +static const u32 gaudi2_tpc_initiator_rtr_id[NUM_OF_TPC_PER_DCORE * NUM_OF_DCORES + 1] = { + 1, 1, 2, 2, 3, 3, 14, 14, 13, 13, 12, 12, 19, 19, 18, 18, 17, + 17, 28, 28, 29, 29, 30, 30, 0 +}; + +static const u32 gaudi2_dec_initiator_rtr_id[NUMBER_OF_DEC] = { + 0, 0, 15, 15, 16, 16, 31, 31, 0, 0 +}; + +static const u32 gaudi2_nic_initiator_rtr_id[NIC_NUMBER_OF_MACROS] = { + 15, 15, 15, 15, 15, 16, 16, 16, 16, 31, 31, 31 +}; + +struct sft_info { + u8 interface_id; + u8 dcore_id; +}; + +static const struct sft_info gaudi2_edma_initiator_sft_id[NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES] = { + {0, 0}, {1, 0}, {0, 1}, {1, 1}, {1, 2}, {1, 3}, {0, 2}, {0, 3}, +}; + +static const u32 gaudi2_pdma_initiator_rtr_id[NUM_OF_PDMA] = { + 0, 0 +}; + +static const u32 gaudi2_rot_initiator_rtr_id[NUM_OF_ROT] = { + 16, 31 +}; + +struct mme_initiators_rtr_id { + u32 wap0; + u32 wap1; + u32 write; + u32 read; + u32 sbte0; + u32 sbte1; + u32 sbte2; + u32 sbte3; + u32 sbte4; +}; + +enum mme_initiators { + MME_WAP0 = 0, + MME_WAP1, + MME_WRITE, + MME_READ, + MME_SBTE0, + MME_SBTE1, + MME_SBTE2, + MME_SBTE3, + MME_SBTE4, + MME_INITIATORS_MAX +}; + +static const struct mme_initiators_rtr_id +gaudi2_mme_initiator_rtr_id[NUM_OF_MME_PER_DCORE * NUM_OF_DCORES] = { + { .wap0 = 5, .wap1 = 7, .write = 6, .read = 7, + .sbte0 = 7, .sbte1 = 4, .sbte2 = 4, .sbte3 = 5, .sbte4 = 6}, + { .wap0 = 10, .wap1 = 8, .write = 9, .read = 8, + .sbte0 = 11, .sbte1 = 11, .sbte2 = 10, .sbte3 = 9, .sbte4 = 8}, + { .wap0 = 21, .wap1 = 23, .write = 22, .read = 23, + .sbte0 = 20, .sbte1 = 20, .sbte2 = 21, .sbte3 = 22, .sbte4 = 23}, + { .wap0 = 30, .wap1 = 28, .write = 29, .read = 30, + .sbte0 = 31, .sbte1 = 31, .sbte2 = 30, .sbte3 = 29, .sbte4 = 28}, +}; + +enum razwi_event_sources { + RAZWI_TPC, + RAZWI_MME, + RAZWI_EDMA, + RAZWI_PDMA, + RAZWI_NIC, + RAZWI_DEC, + RAZWI_ROT +}; + +struct hbm_mc_error_causes { + u32 mask; + char cause[50]; +}; + +static struct hbm_mc_error_causes hbm_mc_spi[GAUDI2_NUM_OF_HBM_MC_SPI_CAUSE] = { + {HBM_MC_SPI_TEMP_PIN_CHG_MASK, "temperature pins changed"}, + {HBM_MC_SPI_THR_ENG_MASK, "temperature-based throttling engaged"}, + {HBM_MC_SPI_THR_DIS_ENG_MASK, "temperature-based throttling disengaged"}, + {HBM_MC_SPI_IEEE1500_COMP_MASK, "IEEE1500 op comp"}, + {HBM_MC_SPI_IEEE1500_PAUSED_MASK, "IEEE1500 op paused"}, +}; + +static const char * const hbm_mc_sei_cause[GAUDI2_NUM_OF_HBM_SEI_CAUSE] = { + [HBM_SEI_CMD_PARITY_EVEN] = "SEI C/A parity even", + [HBM_SEI_CMD_PARITY_ODD] = "SEI C/A parity odd", + [HBM_SEI_READ_ERR] = "SEI read data error", + [HBM_SEI_WRITE_DATA_PARITY_ERR] = "SEI write data parity error", + [HBM_SEI_CATTRIP] = "SEI CATTRIP asserted", + [HBM_SEI_MEM_BIST_FAIL] = "SEI memory BIST fail", + [HBM_SEI_DFI] = "SEI DFI error", + [HBM_SEI_INV_TEMP_READ_OUT] = "SEI invalid temp read", + [HBM_SEI_BIST_FAIL] = "SEI BIST fail" +}; + +struct mmu_spi_sei_cause { + char cause[50]; + int clear_bit; +}; + +static const struct mmu_spi_sei_cause gaudi2_mmu_spi_sei[GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE] = { + {"page fault", 1}, /* INTERRUPT_CLR[1] */ + {"page access", 1}, /* INTERRUPT_CLR[1] */ + {"bypass ddr", 2}, /* INTERRUPT_CLR[2] */ + {"multi hit", 2}, /* INTERRUPT_CLR[2] */ + {"mmu rei0", -1}, /* no clear register bit */ + {"mmu rei1", -1}, /* no clear register bit */ + {"stlb rei0", -1}, /* no clear register bit */ + {"stlb rei1", -1}, /* no clear register bit */ + {"rr privileged write hit", 2}, /* INTERRUPT_CLR[2] */ + {"rr privileged read hit", 2}, /* INTERRUPT_CLR[2] */ + {"rr secure write hit", 2}, /* INTERRUPT_CLR[2] */ + {"rr secure read hit", 2}, /* INTERRUPT_CLR[2] */ + {"bist_fail no use", 2}, /* INTERRUPT_CLR[2] */ + {"bist_fail no use", 2}, /* INTERRUPT_CLR[2] */ + {"bist_fail no use", 2}, /* INTERRUPT_CLR[2] */ + {"bist_fail no use", 2}, /* INTERRUPT_CLR[2] */ + {"slave error", 16}, /* INTERRUPT_CLR[16] */ + {"dec error", 17}, /* INTERRUPT_CLR[17] */ + {"burst fifo full", 2} /* INTERRUPT_CLR[2] */ +}; + +struct gaudi2_cache_invld_params { + u64 start_va; + u64 end_va; + u32 inv_start_val; + u32 flags; + bool range_invalidation; +}; + +struct gaudi2_tpc_idle_data { + struct seq_file *s; + unsigned long *mask; + bool *is_idle; + const char *tpc_fmt; +}; + +struct gaudi2_tpc_mmu_data { + u32 rw_asid; +}; + +static s64 gaudi2_state_dump_specs_props[SP_MAX] = {0}; + +static int gaudi2_memset_device_memory(struct hl_device *hdev, u64 addr, u64 size, u64 val); +static bool gaudi2_is_queue_enabled(struct hl_device *hdev, u32 hw_queue_id); +static bool gaudi2_is_arc_enabled(struct hl_device *hdev, u64 arc_id); +static void gaudi2_clr_arc_id_cap(struct hl_device *hdev, u64 arc_id); +static void gaudi2_set_arc_id_cap(struct hl_device *hdev, u64 arc_id); +static void gaudi2_memset_device_lbw(struct hl_device *hdev, u32 addr, u32 size, u32 val); +static int gaudi2_send_job_to_kdma(struct hl_device *hdev, u64 src_addr, u64 dst_addr, u32 size, + bool is_memset); +static u64 gaudi2_mmu_scramble_addr(struct hl_device *hdev, u64 raw_addr); + +static void gaudi2_init_scrambler_hbm(struct hl_device *hdev) +{ + +} + +static u32 gaudi2_get_signal_cb_size(struct hl_device *hdev) +{ + return sizeof(struct packet_msg_short); +} + +static u32 gaudi2_get_wait_cb_size(struct hl_device *hdev) +{ + return sizeof(struct packet_msg_short) * 4 + sizeof(struct packet_fence); +} + +void gaudi2_iterate_tpcs(struct hl_device *hdev, struct iterate_module_ctx *ctx) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + int dcore, inst, tpc_seq; + u32 offset; + + for (dcore = 0; dcore < NUM_OF_DCORES; dcore++) { + for (inst = 0; inst < NUM_OF_TPC_PER_DCORE; inst++) { + tpc_seq = dcore * NUM_OF_TPC_PER_DCORE + inst; + + if (!(prop->tpc_enabled_mask & BIT(tpc_seq))) + continue; + + offset = (DCORE_OFFSET * dcore) + (DCORE_TPC_OFFSET * inst); + + ctx->fn(hdev, dcore, inst, offset, ctx->data); + } + } + + if (!(prop->tpc_enabled_mask & BIT(TPC_ID_DCORE0_TPC6))) + return; + + /* special check for PCI TPC (DCORE0_TPC6) */ + offset = DCORE_TPC_OFFSET * (NUM_DCORE0_TPC - 1); + ctx->fn(hdev, 0, NUM_DCORE0_TPC - 1, offset, ctx->data); +} + +static bool gaudi2_host_phys_addr_valid(u64 addr) +{ + if ((addr < HOST_PHYS_BASE_0 + HOST_PHYS_SIZE_0) || (addr >= HOST_PHYS_BASE_1)) + return true; + + return false; +} + +static int set_number_of_functional_hbms(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + u8 faulty_hbms = hweight64(hdev->dram_binning); + + /* check if all HBMs should be used */ + if (!faulty_hbms) { + dev_dbg(hdev->dev, "All HBM are in use (no binning)\n"); + prop->num_functional_hbms = GAUDI2_HBM_NUM; + return 0; + } + + /* + * check for error condition in which number of binning + * candidates is higher than the maximum supported by the + * driver (in which case binning mask shall be ignored and driver will + * set the default) + */ + if (faulty_hbms > MAX_FAULTY_HBMS) { + dev_err(hdev->dev, + "HBM binning supports max of %d faulty HBMs, supplied mask 0x%llx.\n", + MAX_FAULTY_HBMS, hdev->dram_binning); + return -EINVAL; + } + + /* + * by default, number of functional HBMs in Gaudi2 is always + * GAUDI2_HBM_NUM - 1. + */ + prop->num_functional_hbms = GAUDI2_HBM_NUM - faulty_hbms; + return 0; +} + +static int gaudi2_set_dram_properties(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + u32 basic_hbm_page_size; + int rc; + + rc = set_number_of_functional_hbms(hdev); + if (rc) + return -EINVAL; + + /* + * Due to HW bug in which TLB size is x16 smaller than expected we use a workaround + * in which we are using x16 bigger page size to be able to populate the entire + * HBM mappings in the TLB + */ + basic_hbm_page_size = prop->num_functional_hbms * SZ_8M; + prop->dram_page_size = GAUDI2_COMPENSATE_TLB_PAGE_SIZE_FACTOR * basic_hbm_page_size; + prop->device_mem_alloc_default_page_size = prop->dram_page_size; + prop->dram_size = prop->num_functional_hbms * SZ_16G; + prop->dram_base_address = DRAM_PHYS_BASE; + prop->dram_end_address = prop->dram_base_address + prop->dram_size; + prop->dram_supports_virtual_memory = true; + + prop->dram_user_base_address = DRAM_PHYS_BASE + prop->dram_page_size; + prop->dram_hints_align_mask = ~GAUDI2_HBM_MMU_SCRM_ADDRESS_MASK; + prop->hints_dram_reserved_va_range.start_addr = RESERVED_VA_RANGE_FOR_ARC_ON_HBM_START; + prop->hints_dram_reserved_va_range.end_addr = RESERVED_VA_RANGE_FOR_ARC_ON_HBM_END; + + /* since DRAM page size differs from DMMU page size we need to allocate + * DRAM memory in units of dram_page size and mapping this memory in + * units of DMMU page size. we overcome this size mismatch using a + * scrambling routine which takes a DRAM page and converts it to a DMMU + * page. + * We therefore: + * 1. partition the virtual address space to DRAM-page (whole) pages. + * (suppose we get n such pages) + * 2. limit the amount of virtual address space we got from 1 above to + * a multiple of 64M as we don't want the scrambled address to cross + * the DRAM virtual address space. + * ( m = (n * DRAM_page_size) / DMMU_page_size). + * 3. determine the and address accordingly + * end_addr = start_addr + m * 48M + * + * the DRAM address MSBs (63:48) are not part of the roundup calculation + */ + prop->dmmu.start_addr = prop->dram_base_address + + (prop->dram_page_size * + DIV_ROUND_UP_SECTOR_T(prop->dram_size, prop->dram_page_size)); + + prop->dmmu.end_addr = prop->dmmu.start_addr + prop->dram_page_size * + div_u64((VA_HBM_SPACE_END - prop->dmmu.start_addr), prop->dmmu.page_size); + + return 0; +} + +static int gaudi2_set_fixed_properties(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct hw_queue_properties *q_props; + u32 num_sync_stream_queues = 0; + int i; + + prop->max_queues = GAUDI2_QUEUE_ID_SIZE; + prop->hw_queues_props = kcalloc(prop->max_queues, sizeof(struct hw_queue_properties), + GFP_KERNEL); + + if (!prop->hw_queues_props) + return -ENOMEM; + + q_props = prop->hw_queues_props; + + for (i = 0 ; i < GAUDI2_QUEUE_ID_CPU_PQ ; i++) { + q_props[i].type = QUEUE_TYPE_HW; + q_props[i].driver_only = 0; + + if (i >= GAUDI2_QUEUE_ID_NIC_0_0 && i <= GAUDI2_QUEUE_ID_NIC_23_3) { + q_props[i].supports_sync_stream = 0; + } else { + q_props[i].supports_sync_stream = 1; + num_sync_stream_queues++; + } + + q_props[i].cb_alloc_flags = CB_ALLOC_USER; + } + + q_props[GAUDI2_QUEUE_ID_CPU_PQ].type = QUEUE_TYPE_CPU; + q_props[GAUDI2_QUEUE_ID_CPU_PQ].driver_only = 1; + q_props[GAUDI2_QUEUE_ID_CPU_PQ].cb_alloc_flags = CB_ALLOC_KERNEL; + + prop->cache_line_size = DEVICE_CACHE_LINE_SIZE; + prop->cfg_base_address = CFG_BASE; + prop->device_dma_offset_for_host_access = HOST_PHYS_BASE_0; + prop->host_base_address = HOST_PHYS_BASE_0; + prop->host_end_address = prop->host_base_address + HOST_PHYS_SIZE_0; + prop->max_pending_cs = GAUDI2_MAX_PENDING_CS; + prop->completion_queues_count = GAUDI2_RESERVED_CQ_NUMBER; + prop->user_dec_intr_count = NUMBER_OF_DEC; + prop->user_interrupt_count = GAUDI2_IRQ_NUM_USER_LAST - GAUDI2_IRQ_NUM_USER_FIRST + 1; + prop->completion_mode = HL_COMPLETION_MODE_CS; + prop->sync_stream_first_sob = GAUDI2_RESERVED_SOB_NUMBER; + prop->sync_stream_first_mon = GAUDI2_RESERVED_MON_NUMBER; + + prop->sram_base_address = SRAM_BASE_ADDR; + prop->sram_size = SRAM_SIZE; + prop->sram_end_address = prop->sram_base_address + prop->sram_size; + prop->sram_user_base_address = prop->sram_base_address + SRAM_USER_BASE_OFFSET; + + prop->hints_range_reservation = true; + + if (hdev->pldm) + prop->mmu_pgt_size = 0x800000; /* 8MB */ + else + prop->mmu_pgt_size = MMU_PAGE_TABLES_INITIAL_SIZE; + + prop->mmu_pte_size = HL_PTE_SIZE; + prop->mmu_hop_table_size = HOP_TABLE_SIZE_512_PTE; + prop->mmu_hop0_tables_total_size = HOP0_512_PTE_TABLES_TOTAL_SIZE; + + prop->dmmu.hop_shifts[MMU_HOP0] = DHOP0_SHIFT; + prop->dmmu.hop_shifts[MMU_HOP1] = DHOP1_SHIFT; + prop->dmmu.hop_shifts[MMU_HOP2] = DHOP2_SHIFT; + prop->dmmu.hop_shifts[MMU_HOP3] = DHOP3_SHIFT; + prop->dmmu.hop_shifts[MMU_HOP4] = DHOP4_SHIFT; + prop->dmmu.hop_masks[MMU_HOP0] = DHOP0_MASK; + prop->dmmu.hop_masks[MMU_HOP1] = DHOP1_MASK; + prop->dmmu.hop_masks[MMU_HOP2] = DHOP2_MASK; + prop->dmmu.hop_masks[MMU_HOP3] = DHOP3_MASK; + prop->dmmu.hop_masks[MMU_HOP4] = DHOP4_MASK; + prop->dmmu.page_size = PAGE_SIZE_1GB; + prop->dmmu.num_hops = MMU_ARCH_6_HOPS; + prop->dmmu.last_mask = LAST_MASK; + prop->dmmu.host_resident = 1; + /* TODO: will be duplicated until implementing per-MMU props */ + prop->dmmu.hop_table_size = prop->mmu_hop_table_size; + prop->dmmu.hop0_tables_total_size = prop->mmu_hop0_tables_total_size; + + /* + * this is done in order to be able to validate FW descriptor (i.e. validating that + * the addresses and allocated space for FW image does not cross memory bounds). + * for this reason we set the DRAM size to the minimum possible and later it will + * be modified according to what reported in the cpucp info packet + */ + prop->dram_size = (GAUDI2_HBM_NUM - 1) * SZ_16G; + + hdev->pmmu_huge_range = true; + prop->pmmu.host_resident = 1; + prop->pmmu.num_hops = MMU_ARCH_6_HOPS; + prop->pmmu.last_mask = LAST_MASK; + /* TODO: will be duplicated until implementing per-MMU props */ + prop->pmmu.hop_table_size = prop->mmu_hop_table_size; + prop->pmmu.hop0_tables_total_size = prop->mmu_hop0_tables_total_size; + + prop->hints_host_reserved_va_range.start_addr = RESERVED_VA_FOR_VIRTUAL_MSIX_DOORBELL_START; + prop->hints_host_reserved_va_range.end_addr = RESERVED_VA_RANGE_FOR_ARC_ON_HOST_END; + prop->hints_host_hpage_reserved_va_range.start_addr = + RESERVED_VA_RANGE_FOR_ARC_ON_HOST_HPAGE_START; + prop->hints_host_hpage_reserved_va_range.end_addr = + RESERVED_VA_RANGE_FOR_ARC_ON_HOST_HPAGE_END; + + if (PAGE_SIZE == SZ_64K) { + prop->pmmu.hop_shifts[MMU_HOP0] = HOP0_SHIFT_64K; + prop->pmmu.hop_shifts[MMU_HOP1] = HOP1_SHIFT_64K; + prop->pmmu.hop_shifts[MMU_HOP2] = HOP2_SHIFT_64K; + prop->pmmu.hop_shifts[MMU_HOP3] = HOP3_SHIFT_64K; + prop->pmmu.hop_shifts[MMU_HOP4] = HOP4_SHIFT_64K; + prop->pmmu.hop_shifts[MMU_HOP5] = HOP5_SHIFT_64K; + prop->pmmu.hop_masks[MMU_HOP0] = HOP0_MASK_64K; + prop->pmmu.hop_masks[MMU_HOP1] = HOP1_MASK_64K; + prop->pmmu.hop_masks[MMU_HOP2] = HOP2_MASK_64K; + prop->pmmu.hop_masks[MMU_HOP3] = HOP3_MASK_64K; + prop->pmmu.hop_masks[MMU_HOP4] = HOP4_MASK_64K; + prop->pmmu.hop_masks[MMU_HOP5] = HOP5_MASK_64K; + prop->pmmu.start_addr = VA_HOST_SPACE_PAGE_START; + prop->pmmu.end_addr = VA_HOST_SPACE_PAGE_END; + prop->pmmu.page_size = PAGE_SIZE_64KB; + + /* shifts and masks are the same in PMMU and HPMMU */ + memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu)); + prop->pmmu_huge.page_size = PAGE_SIZE_16MB; + prop->pmmu_huge.start_addr = VA_HOST_SPACE_HPAGE_START; + prop->pmmu_huge.end_addr = VA_HOST_SPACE_HPAGE_END; + } else { + prop->pmmu.hop_shifts[MMU_HOP0] = HOP0_SHIFT_4K; + prop->pmmu.hop_shifts[MMU_HOP1] = HOP1_SHIFT_4K; + prop->pmmu.hop_shifts[MMU_HOP2] = HOP2_SHIFT_4K; + prop->pmmu.hop_shifts[MMU_HOP3] = HOP3_SHIFT_4K; + prop->pmmu.hop_shifts[MMU_HOP4] = HOP4_SHIFT_4K; + prop->pmmu.hop_shifts[MMU_HOP5] = HOP5_SHIFT_4K; + prop->pmmu.hop_masks[MMU_HOP0] = HOP0_MASK_4K; + prop->pmmu.hop_masks[MMU_HOP1] = HOP1_MASK_4K; + prop->pmmu.hop_masks[MMU_HOP2] = HOP2_MASK_4K; + prop->pmmu.hop_masks[MMU_HOP3] = HOP3_MASK_4K; + prop->pmmu.hop_masks[MMU_HOP4] = HOP4_MASK_4K; + prop->pmmu.hop_masks[MMU_HOP5] = HOP5_MASK_4K; + prop->pmmu.start_addr = VA_HOST_SPACE_PAGE_START; + prop->pmmu.end_addr = VA_HOST_SPACE_PAGE_END; + prop->pmmu.page_size = PAGE_SIZE_4KB; + + /* shifts and masks are the same in PMMU and HPMMU */ + memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu)); + prop->pmmu_huge.page_size = PAGE_SIZE_2MB; + prop->pmmu_huge.start_addr = VA_HOST_SPACE_HPAGE_START; + prop->pmmu_huge.end_addr = VA_HOST_SPACE_HPAGE_END; + } + + prop->cfg_size = CFG_SIZE; + prop->max_asid = MAX_ASID; + prop->num_of_events = GAUDI2_EVENT_SIZE; + + prop->dc_power_default = DC_POWER_DEFAULT; + + prop->cb_pool_cb_cnt = GAUDI2_CB_POOL_CB_CNT; + prop->cb_pool_cb_size = GAUDI2_CB_POOL_CB_SIZE; + prop->pcie_dbi_base_address = CFG_BASE + mmPCIE_DBI_BASE; + prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI; + + strncpy(prop->cpucp_info.card_name, GAUDI2_DEFAULT_CARD_NAME, CARD_NAME_MAX_LEN); + + prop->mme_master_slave_mode = 1; + + prop->first_available_user_sob[0] = GAUDI2_RESERVED_SOB_NUMBER + + (num_sync_stream_queues * HL_RSVD_SOBS); + + prop->first_available_user_mon[0] = GAUDI2_RESERVED_MON_NUMBER + + (num_sync_stream_queues * HL_RSVD_MONS); + + prop->first_available_user_interrupt = GAUDI2_IRQ_NUM_USER_FIRST; + + prop->first_available_cq[0] = GAUDI2_RESERVED_CQ_NUMBER; + + prop->fw_cpu_boot_dev_sts0_valid = false; + prop->fw_cpu_boot_dev_sts1_valid = false; + prop->hard_reset_done_by_fw = false; + prop->gic_interrupts_enable = true; + + prop->server_type = HL_SERVER_TYPE_UNKNOWN; + + prop->cb_va_start_addr = VA_HOST_SPACE_USER_MAPPED_CB_START; + prop->cb_va_end_addr = VA_HOST_SPACE_USER_MAPPED_CB_END; + + prop->max_dec = NUMBER_OF_DEC; + + prop->clk_pll_index = HL_GAUDI2_MME_PLL; + + prop->dma_mask = 64; + + return 0; +} + +static int gaudi2_pci_bars_map(struct hl_device *hdev) +{ + static const char * const name[] = {"CFG_SRAM", "MSIX", "DRAM"}; + bool is_wc[3] = {false, false, true}; + int rc; + + rc = hl_pci_bars_map(hdev, name, is_wc); + if (rc) + return rc; + + hdev->rmmio = hdev->pcie_bar[SRAM_CFG_BAR_ID] + (CFG_BASE - STM_FLASH_BASE_ADDR); + + return 0; +} + +static u64 gaudi2_set_hbm_bar_base(struct hl_device *hdev, u64 addr) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + struct hl_inbound_pci_region pci_region; + u64 old_addr = addr; + int rc; + + if ((gaudi2) && (gaudi2->dram_bar_cur_addr == addr)) + return old_addr; + + if (hdev->asic_prop.iatu_done_by_fw) + return U64_MAX; + + /* Inbound Region 2 - Bar 4 - Point to DRAM */ + pci_region.mode = PCI_BAR_MATCH_MODE; + pci_region.bar = DRAM_BAR_ID; + pci_region.addr = addr; + rc = hl_pci_set_inbound_region(hdev, 2, &pci_region); + if (rc) + return U64_MAX; + + if (gaudi2) { + old_addr = gaudi2->dram_bar_cur_addr; + gaudi2->dram_bar_cur_addr = addr; + } + + return old_addr; +} + +static int gaudi2_init_iatu(struct hl_device *hdev) +{ + struct hl_inbound_pci_region inbound_region; + struct hl_outbound_pci_region outbound_region; + u32 bar_addr_low, bar_addr_high; + int rc; + + if (hdev->asic_prop.iatu_done_by_fw) + return 0; + + /* Temporary inbound Region 0 - Bar 0 - Point to CFG + * We must map this region in BAR match mode in order to + * fetch BAR physical base address + */ + inbound_region.mode = PCI_BAR_MATCH_MODE; + inbound_region.bar = SRAM_CFG_BAR_ID; + /* Base address must be aligned to Bar size which is 256 MB */ + inbound_region.addr = STM_FLASH_BASE_ADDR - STM_FLASH_ALIGNED_OFF; + rc = hl_pci_set_inbound_region(hdev, 0, &inbound_region); + if (rc) + return rc; + + /* Fetch physical BAR address */ + bar_addr_high = RREG32(mmPCIE_DBI_BAR1_REG + STM_FLASH_ALIGNED_OFF); + bar_addr_low = RREG32(mmPCIE_DBI_BAR0_REG + STM_FLASH_ALIGNED_OFF) & ~0xF; + + hdev->pcie_bar_phys[SRAM_CFG_BAR_ID] = (u64)bar_addr_high << 32 | bar_addr_low; + + /* Inbound Region 0 - Bar 0 - Point to CFG */ + inbound_region.mode = PCI_ADDRESS_MATCH_MODE; + inbound_region.bar = SRAM_CFG_BAR_ID; + inbound_region.offset_in_bar = 0; + inbound_region.addr = STM_FLASH_BASE_ADDR; + inbound_region.size = CFG_REGION_SIZE; + rc = hl_pci_set_inbound_region(hdev, 0, &inbound_region); + if (rc) + return rc; + + /* Inbound Region 1 - Bar 0 - Point to BAR0_RESERVED + SRAM */ + inbound_region.mode = PCI_ADDRESS_MATCH_MODE; + inbound_region.bar = SRAM_CFG_BAR_ID; + inbound_region.offset_in_bar = CFG_REGION_SIZE; + inbound_region.addr = BAR0_RSRVD_BASE_ADDR; + inbound_region.size = BAR0_RSRVD_SIZE + SRAM_SIZE; + rc = hl_pci_set_inbound_region(hdev, 1, &inbound_region); + if (rc) + return rc; + + /* Inbound Region 2 - Bar 4 - Point to DRAM */ + inbound_region.mode = PCI_BAR_MATCH_MODE; + inbound_region.bar = DRAM_BAR_ID; + inbound_region.addr = DRAM_PHYS_BASE; + rc = hl_pci_set_inbound_region(hdev, 2, &inbound_region); + if (rc) + return rc; + + /* Outbound Region 0 - Point to Host */ + outbound_region.addr = HOST_PHYS_BASE_0; + outbound_region.size = HOST_PHYS_SIZE_0; + rc = hl_pci_set_outbound_region(hdev, &outbound_region); + + return rc; +} + +static enum hl_device_hw_state gaudi2_get_hw_state(struct hl_device *hdev) +{ + return RREG32(mmHW_STATE); +} + +static int gaudi2_tpc_binning_init_prop(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + + /* + * check for error condition in which number of binning candidates + * is higher than the maximum supported by the driver + */ + if (hweight64(hdev->tpc_binning) > MAX_CLUSTER_BINNING_FAULTY_TPCS) { + dev_err(hdev->dev, "TPC binning is supported for max of %d faulty TPCs, provided mask 0x%llx\n", + MAX_CLUSTER_BINNING_FAULTY_TPCS, + hdev->tpc_binning); + return -EINVAL; + } + + prop->tpc_binning_mask = hdev->tpc_binning; + prop->tpc_enabled_mask = GAUDI2_TPC_FULL_MASK; + + return 0; +} + +static int gaudi2_set_tpc_binning_masks(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct hw_queue_properties *q_props = prop->hw_queues_props; + u64 tpc_binning_mask; + u8 subst_idx = 0; + int i, rc; + + rc = gaudi2_tpc_binning_init_prop(hdev); + if (rc) + return rc; + + tpc_binning_mask = prop->tpc_binning_mask; + + for (i = 0 ; i < MAX_FAULTY_TPCS ; i++) { + u8 subst_seq, binned, qid_base; + + if (tpc_binning_mask == 0) + break; + + if (subst_idx == 0) { + subst_seq = TPC_ID_DCORE0_TPC6; + qid_base = GAUDI2_QUEUE_ID_DCORE0_TPC_6_0; + } else { + subst_seq = TPC_ID_DCORE3_TPC5; + qid_base = GAUDI2_QUEUE_ID_DCORE3_TPC_5_0; + } + + + /* clear bit from mask */ + binned = __ffs(tpc_binning_mask); + /* + * Coverity complains about possible out-of-bound access in + * clear_bit + */ + if (binned >= TPC_ID_SIZE) { + dev_err(hdev->dev, + "Invalid binned TPC (binning mask: %llx)\n", + tpc_binning_mask); + return -EINVAL; + } + clear_bit(binned, (unsigned long *)&tpc_binning_mask); + + /* also clear replacing TPC bit from enabled mask */ + clear_bit(subst_seq, (unsigned long *)&prop->tpc_enabled_mask); + + /* bin substite TPC's Qs */ + q_props[qid_base].binned = 1; + q_props[qid_base + 1].binned = 1; + q_props[qid_base + 2].binned = 1; + q_props[qid_base + 3].binned = 1; + + subst_idx++; + } + + return 0; +} + +static int gaudi2_set_dec_binning_masks(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + u8 num_faulty; + + num_faulty = hweight32(hdev->decoder_binning); + + /* + * check for error condition in which number of binning candidates + * is higher than the maximum supported by the driver + */ + if (num_faulty > MAX_FAULTY_DECODERS) { + dev_err(hdev->dev, "decoder binning is supported for max of single faulty decoder, provided mask 0x%x\n", + hdev->decoder_binning); + return -EINVAL; + } + + prop->decoder_binning_mask = (hdev->decoder_binning & GAUDI2_DECODER_FULL_MASK); + + if (prop->decoder_binning_mask) + prop->decoder_enabled_mask = (GAUDI2_DECODER_FULL_MASK & ~BIT(DEC_ID_PCIE_VDEC1)); + else + prop->decoder_enabled_mask = GAUDI2_DECODER_FULL_MASK; + + return 0; +} + +static void gaudi2_set_dram_binning_masks(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + + /* check if we should override default binning */ + if (!hdev->dram_binning) { + prop->dram_binning_mask = 0; + prop->dram_enabled_mask = GAUDI2_DRAM_FULL_MASK; + return; + } + + /* set DRAM binning constraints */ + prop->faulty_dram_cluster_map |= hdev->dram_binning; + prop->dram_binning_mask = hdev->dram_binning; + prop->dram_enabled_mask = GAUDI2_DRAM_FULL_MASK & ~BIT(HBM_ID5); +} + +static int gaudi2_set_edma_binning_masks(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct hw_queue_properties *q_props; + u8 seq, num_faulty; + + num_faulty = hweight32(hdev->edma_binning); + + /* + * check for error condition in which number of binning candidates + * is higher than the maximum supported by the driver + */ + if (num_faulty > MAX_FAULTY_EDMAS) { + dev_err(hdev->dev, + "EDMA binning is supported for max of single faulty EDMA, provided mask 0x%x\n", + hdev->edma_binning); + return -EINVAL; + } + + if (!hdev->edma_binning) { + prop->edma_binning_mask = 0; + prop->edma_enabled_mask = GAUDI2_EDMA_FULL_MASK; + return 0; + } + + seq = __ffs((unsigned long)hdev->edma_binning); + + /* set binning constraints */ + prop->faulty_dram_cluster_map |= BIT(edma_to_hbm_cluster[seq]); + prop->edma_binning_mask = hdev->edma_binning; + prop->edma_enabled_mask = GAUDI2_EDMA_FULL_MASK & ~BIT(EDMA_ID_DCORE3_INSTANCE1); + + /* bin substitute EDMA's queue */ + q_props = prop->hw_queues_props; + q_props[GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0].binned = 1; + q_props[GAUDI2_QUEUE_ID_DCORE3_EDMA_1_1].binned = 1; + q_props[GAUDI2_QUEUE_ID_DCORE3_EDMA_1_2].binned = 1; + q_props[GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3].binned = 1; + + return 0; +} + +static int gaudi2_set_xbar_edge_enable_mask(struct hl_device *hdev, u32 xbar_edge_iso_mask) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + u8 num_faulty, seq; + + /* check if we should override default binning */ + if (!xbar_edge_iso_mask) { + prop->xbar_edge_enabled_mask = GAUDI2_XBAR_EDGE_FULL_MASK; + return 0; + } + + /* + * note that it can be set to value other than 0 only after cpucp packet (i.e. + * only the FW can set a redundancy value). for user it'll always be 0. + */ + num_faulty = hweight32(xbar_edge_iso_mask); + + /* + * check for error condition in which number of binning candidates + * is higher than the maximum supported by the driver + */ + if (num_faulty > MAX_FAULTY_XBARS) { + dev_err(hdev->dev, "we cannot have more than %d faulty XBAR EDGE\n", + MAX_FAULTY_XBARS); + return -EINVAL; + } + + seq = __ffs((unsigned long)xbar_edge_iso_mask); + + /* set binning constraints */ + prop->faulty_dram_cluster_map |= BIT(xbar_edge_to_hbm_cluster[seq]); + prop->xbar_edge_enabled_mask = (~xbar_edge_iso_mask) & GAUDI2_XBAR_EDGE_FULL_MASK; + + return 0; +} + +static int gaudi2_set_cluster_binning_masks_common(struct hl_device *hdev, u8 xbar_edge_iso_mask) +{ + int rc; + + /* + * mark all clusters as good, each component will "fail" cluster + * based on eFuse/user values. + * If more than single cluster is faulty- the chip is unusable + */ + hdev->asic_prop.faulty_dram_cluster_map = 0; + + gaudi2_set_dram_binning_masks(hdev); + + rc = gaudi2_set_edma_binning_masks(hdev); + if (rc) + return rc; + + rc = gaudi2_set_xbar_edge_enable_mask(hdev, xbar_edge_iso_mask); + if (rc) + return rc; + + + /* always initially set to full mask */ + hdev->asic_prop.hmmu_hif_enabled_mask = GAUDI2_HIF_HMMU_FULL_MASK; + + return 0; +} + +static int gaudi2_set_cluster_binning_masks(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + int rc; + + rc = gaudi2_set_cluster_binning_masks_common(hdev, prop->cpucp_info.xbar_binning_mask); + if (rc) + return rc; + + /* if we have DRAM binning reported by FW we should perform cluster config */ + if (prop->faulty_dram_cluster_map) { + u8 cluster_seq = __ffs((unsigned long)prop->faulty_dram_cluster_map); + + prop->hmmu_hif_enabled_mask = cluster_hmmu_hif_enabled_mask[cluster_seq]; + } + + return 0; +} + +static int gaudi2_cpucp_info_get(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + struct asic_fixed_properties *prop = &hdev->asic_prop; + long max_power; + u64 dram_size; + int rc; + + if (!(gaudi2->hw_cap_initialized & HW_CAP_CPU_Q)) + return 0; + + /* No point of asking this information again when not doing hard reset, as the device + * CPU hasn't been reset + */ + if (hdev->reset_info.in_compute_reset) + return 0; + + rc = hl_fw_cpucp_handshake(hdev, mmCPU_BOOT_DEV_STS0, mmCPU_BOOT_DEV_STS1, mmCPU_BOOT_ERR0, + mmCPU_BOOT_ERR1); + if (rc) + return rc; + + dram_size = le64_to_cpu(prop->cpucp_info.dram_size); + if (dram_size) { + /* we can have wither 5 or 6 HBMs. other values are invalid */ + + if ((dram_size != ((GAUDI2_HBM_NUM - 1) * SZ_16G)) && + (dram_size != (GAUDI2_HBM_NUM * SZ_16G))) { + dev_err(hdev->dev, + "F/W reported invalid DRAM size %llu. Trying to use default size %llu\n", + dram_size, prop->dram_size); + dram_size = prop->dram_size; + } + + prop->dram_size = dram_size; + prop->dram_end_address = prop->dram_base_address + dram_size; + } + + if (!strlen(prop->cpucp_info.card_name)) + strncpy(prop->cpucp_info.card_name, GAUDI2_DEFAULT_CARD_NAME, CARD_NAME_MAX_LEN); + + /* Overwrite binning masks with the actual binning values from F/W */ + hdev->dram_binning = prop->cpucp_info.dram_binning_mask; + hdev->edma_binning = prop->cpucp_info.edma_binning_mask; + hdev->tpc_binning = le64_to_cpu(prop->cpucp_info.tpc_binning_mask); + hdev->decoder_binning = lower_32_bits(le64_to_cpu(prop->cpucp_info.decoder_binning_mask)); + + /* + * at this point the DRAM parameters need to be updated according to data obtained + * from the FW + */ + rc = gaudi2_set_dram_properties(hdev); + if (rc) + return rc; + + rc = gaudi2_set_cluster_binning_masks(hdev); + if (rc) + return rc; + + rc = gaudi2_set_tpc_binning_masks(hdev); + if (rc) + return rc; + + rc = gaudi2_set_dec_binning_masks(hdev); + if (rc) + return rc; + + max_power = hl_fw_get_max_power(hdev); + if (max_power < 0) + return max_power; + + prop->max_power_default = (u64) max_power; + + return 0; +} + +static int gaudi2_fetch_psoc_frequency(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u16 pll_freq_arr[HL_PLL_NUM_OUTPUTS]; + int rc; + + if (!(gaudi2->hw_cap_initialized & HW_CAP_CPU_Q)) + return 0; + + rc = hl_fw_cpucp_pll_info_get(hdev, HL_GAUDI2_CPU_PLL, pll_freq_arr); + if (rc) + return rc; + + hdev->asic_prop.psoc_timestamp_frequency = pll_freq_arr[3]; + + return 0; +} + +static int gaudi2_early_init(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct pci_dev *pdev = hdev->pdev; + resource_size_t pci_bar_size; + u32 fw_boot_status; + int rc; + + rc = gaudi2_set_fixed_properties(hdev); + if (rc) + return rc; + + /* Check BAR sizes */ + pci_bar_size = pci_resource_len(pdev, SRAM_CFG_BAR_ID); + + if (pci_bar_size != CFG_BAR_SIZE) { + dev_err(hdev->dev, "Not " HL_NAME "? BAR %d size %pa, expecting %llu\n", + SRAM_CFG_BAR_ID, &pci_bar_size, CFG_BAR_SIZE); + rc = -ENODEV; + goto free_queue_props; + } + + pci_bar_size = pci_resource_len(pdev, MSIX_BAR_ID); + if (pci_bar_size != MSIX_BAR_SIZE) { + dev_err(hdev->dev, "Not " HL_NAME "? BAR %d size %pa, expecting %llu\n", + MSIX_BAR_ID, &pci_bar_size, MSIX_BAR_SIZE); + rc = -ENODEV; + goto free_queue_props; + } + + prop->dram_pci_bar_size = pci_resource_len(pdev, DRAM_BAR_ID); + hdev->dram_pci_bar_start = pci_resource_start(pdev, DRAM_BAR_ID); + + /* If FW security is enabled at this point it means no access to ELBI */ + if (hdev->asic_prop.fw_security_enabled) { + hdev->asic_prop.iatu_done_by_fw = true; + goto pci_init; + } + + rc = hl_pci_elbi_read(hdev, CFG_BASE + mmCPU_BOOT_DEV_STS0, &fw_boot_status); + if (rc) + goto free_queue_props; + + /* Check whether FW is configuring iATU */ + if ((fw_boot_status & CPU_BOOT_DEV_STS0_ENABLED) && + (fw_boot_status & CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN)) + hdev->asic_prop.iatu_done_by_fw = true; + +pci_init: + rc = hl_pci_init(hdev); + if (rc) + goto free_queue_props; + + /* Before continuing in the initialization, we need to read the preboot + * version to determine whether we run with a security-enabled firmware + */ + rc = hl_fw_read_preboot_status(hdev); + if (rc) { + if (hdev->reset_on_preboot_fail) + hdev->asic_funcs->hw_fini(hdev, true, false); + goto pci_fini; + } + + if (gaudi2_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) { + dev_dbg(hdev->dev, "H/W state is dirty, must reset before initializing\n"); + hdev->asic_funcs->hw_fini(hdev, true, false); + } + + return 0; + +pci_fini: + hl_pci_fini(hdev); +free_queue_props: + kfree(hdev->asic_prop.hw_queues_props); + return rc; +} + +static int gaudi2_early_fini(struct hl_device *hdev) +{ + kfree(hdev->asic_prop.hw_queues_props); + hl_pci_fini(hdev); + + return 0; +} + +static bool gaudi2_is_arc_nic_owned(u64 arc_id) +{ + switch (arc_id) { + case CPU_ID_NIC_QMAN_ARC0...CPU_ID_NIC_QMAN_ARC23: + return true; + default: + return false; + } +} + +static bool gaudi2_is_arc_tpc_owned(u64 arc_id) +{ + switch (arc_id) { + case CPU_ID_TPC_QMAN_ARC0...CPU_ID_TPC_QMAN_ARC24: + return true; + default: + return false; + } +} + +static void gaudi2_init_arcs(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u64 arc_id; + u32 i; + + for (i = CPU_ID_SCHED_ARC0 ; i <= CPU_ID_SCHED_ARC3 ; i++) { + if (gaudi2_is_arc_enabled(hdev, i)) + continue; + + gaudi2_set_arc_id_cap(hdev, i); + } + + for (i = GAUDI2_QUEUE_ID_PDMA_0_0 ; i < GAUDI2_QUEUE_ID_CPU_PQ ; i += 4) { + if (!gaudi2_is_queue_enabled(hdev, i)) + continue; + + arc_id = gaudi2_queue_id_to_arc_id[i]; + if (gaudi2_is_arc_enabled(hdev, arc_id)) + continue; + + if (gaudi2_is_arc_nic_owned(arc_id) && + !(hdev->nic_ports_mask & BIT_ULL(arc_id - CPU_ID_NIC_QMAN_ARC0))) + continue; + + if (gaudi2_is_arc_tpc_owned(arc_id) && !(gaudi2->tpc_hw_cap_initialized & + BIT_ULL(arc_id - CPU_ID_TPC_QMAN_ARC0))) + continue; + + gaudi2_set_arc_id_cap(hdev, arc_id); + } +} + +static int gaudi2_scrub_arc_dccm(struct hl_device *hdev, u32 cpu_id) +{ + u32 reg_base, reg_val; + int rc; + + switch (cpu_id) { + case CPU_ID_SCHED_ARC0 ... CPU_ID_SCHED_ARC3: + /* Each ARC scheduler has 2 consecutive DCCM blocks */ + rc = gaudi2_send_job_to_kdma(hdev, 0, CFG_BASE + gaudi2_arc_dccm_bases[cpu_id], + ARC_DCCM_BLOCK_SIZE * 2, true); + if (rc) + return rc; + break; + case CPU_ID_SCHED_ARC4: + case CPU_ID_SCHED_ARC5: + case CPU_ID_MME_QMAN_ARC0: + case CPU_ID_MME_QMAN_ARC1: + reg_base = gaudi2_arc_blocks_bases[cpu_id]; + + /* Scrub lower DCCM block */ + rc = gaudi2_send_job_to_kdma(hdev, 0, CFG_BASE + gaudi2_arc_dccm_bases[cpu_id], + ARC_DCCM_BLOCK_SIZE, true); + if (rc) + return rc; + + /* Switch to upper DCCM block */ + reg_val = FIELD_PREP(ARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN_VAL_MASK, 1); + WREG32(reg_base + ARC_DCCM_UPPER_EN_OFFSET, reg_val); + + /* Scrub upper DCCM block */ + rc = gaudi2_send_job_to_kdma(hdev, 0, CFG_BASE + gaudi2_arc_dccm_bases[cpu_id], + ARC_DCCM_BLOCK_SIZE, true); + if (rc) + return rc; + + /* Switch to lower DCCM block */ + reg_val = FIELD_PREP(ARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN_VAL_MASK, 0); + WREG32(reg_base + ARC_DCCM_UPPER_EN_OFFSET, reg_val); + break; + default: + rc = gaudi2_send_job_to_kdma(hdev, 0, CFG_BASE + gaudi2_arc_dccm_bases[cpu_id], + ARC_DCCM_BLOCK_SIZE, true); + if (rc) + return rc; + } + + return 0; +} + +static void gaudi2_scrub_arcs_dccm(struct hl_device *hdev) +{ + u16 arc_id; + + for (arc_id = CPU_ID_SCHED_ARC0 ; arc_id < CPU_ID_MAX ; arc_id++) { + if (!gaudi2_is_arc_enabled(hdev, arc_id)) + continue; + + gaudi2_scrub_arc_dccm(hdev, arc_id); + } +} + +static int gaudi2_late_init(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + int rc; + + rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_ENABLE_PCI_ACCESS, + gaudi2->virt_msix_db_dma_addr); + if (rc) { + dev_err(hdev->dev, "Failed to enable PCI access from CPU\n"); + return rc; + } + + rc = gaudi2_fetch_psoc_frequency(hdev); + if (rc) { + dev_err(hdev->dev, "Failed to fetch psoc frequency\n"); + goto disable_pci_access; + } + + gaudi2_init_arcs(hdev); + gaudi2_scrub_arcs_dccm(hdev); + gaudi2_init_security(hdev); + + return 0; + +disable_pci_access: + hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS, 0x0); + + return rc; +} + +static void gaudi2_late_fini(struct hl_device *hdev) +{ + const struct hwmon_channel_info **channel_info_arr; + int i = 0; + + if (!hdev->hl_chip_info->info) + return; + + channel_info_arr = hdev->hl_chip_info->info; + + while (channel_info_arr[i]) { + kfree(channel_info_arr[i]->config); + kfree(channel_info_arr[i]); + i++; + } + + kfree(channel_info_arr); + + hdev->hl_chip_info->info = NULL; +} + +static void gaudi2_user_mapped_dec_init(struct gaudi2_device *gaudi2, u32 start_idx) +{ + struct user_mapped_block *blocks = gaudi2->mapped_blocks; + + HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE0_DEC0_CMD_BASE, HL_BLOCK_SIZE); + HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE0_DEC1_CMD_BASE, HL_BLOCK_SIZE); + HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE1_DEC0_CMD_BASE, HL_BLOCK_SIZE); + HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE1_DEC1_CMD_BASE, HL_BLOCK_SIZE); + HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE2_DEC0_CMD_BASE, HL_BLOCK_SIZE); + HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE2_DEC1_CMD_BASE, HL_BLOCK_SIZE); + HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE3_DEC0_CMD_BASE, HL_BLOCK_SIZE); + HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE3_DEC1_CMD_BASE, HL_BLOCK_SIZE); + HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmPCIE_DEC0_CMD_BASE, HL_BLOCK_SIZE); + HL_USR_MAPPED_BLK_INIT(&blocks[start_idx], mmPCIE_DEC1_CMD_BASE, HL_BLOCK_SIZE); +} + +static void gaudi2_user_mapped_blocks_init(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + struct user_mapped_block *blocks = gaudi2->mapped_blocks; + u32 block_size, umr_start_idx, num_umr_blocks; + int i; + + for (i = 0 ; i < NUM_ARC_CPUS ; i++) { + if (i >= CPU_ID_SCHED_ARC0 && i <= CPU_ID_SCHED_ARC3) + block_size = ARC_DCCM_BLOCK_SIZE * 2; + else + block_size = ARC_DCCM_BLOCK_SIZE; + + blocks[i].address = gaudi2_arc_dccm_bases[i]; + blocks[i].size = block_size; + } + + blocks[NUM_ARC_CPUS].address = mmARC_FARM_ARC0_ACP_ENG_BASE; + blocks[NUM_ARC_CPUS].size = HL_BLOCK_SIZE; + + blocks[NUM_ARC_CPUS + 1].address = mmARC_FARM_ARC1_ACP_ENG_BASE; + blocks[NUM_ARC_CPUS + 1].size = HL_BLOCK_SIZE; + + blocks[NUM_ARC_CPUS + 2].address = mmARC_FARM_ARC2_ACP_ENG_BASE; + blocks[NUM_ARC_CPUS + 2].size = HL_BLOCK_SIZE; + + blocks[NUM_ARC_CPUS + 3].address = mmARC_FARM_ARC3_ACP_ENG_BASE; + blocks[NUM_ARC_CPUS + 3].size = HL_BLOCK_SIZE; + + blocks[NUM_ARC_CPUS + 4].address = mmDCORE0_MME_QM_ARC_ACP_ENG_BASE; + blocks[NUM_ARC_CPUS + 4].size = HL_BLOCK_SIZE; + + blocks[NUM_ARC_CPUS + 5].address = mmDCORE1_MME_QM_ARC_ACP_ENG_BASE; + blocks[NUM_ARC_CPUS + 5].size = HL_BLOCK_SIZE; + + blocks[NUM_ARC_CPUS + 6].address = mmDCORE2_MME_QM_ARC_ACP_ENG_BASE; + blocks[NUM_ARC_CPUS + 6].size = HL_BLOCK_SIZE; + + blocks[NUM_ARC_CPUS + 7].address = mmDCORE3_MME_QM_ARC_ACP_ENG_BASE; + blocks[NUM_ARC_CPUS + 7].size = HL_BLOCK_SIZE; + + umr_start_idx = NUM_ARC_CPUS + NUM_OF_USER_ACP_BLOCKS; + num_umr_blocks = NIC_NUMBER_OF_ENGINES * NUM_OF_USER_NIC_UMR_BLOCKS; + for (i = 0 ; i < num_umr_blocks ; i++) { + u8 nic_id, umr_block_id; + + nic_id = i / NUM_OF_USER_NIC_UMR_BLOCKS; + umr_block_id = i % NUM_OF_USER_NIC_UMR_BLOCKS; + + blocks[umr_start_idx + i].address = + mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + + (nic_id / NIC_NUMBER_OF_QM_PER_MACRO) * NIC_OFFSET + + (nic_id % NIC_NUMBER_OF_QM_PER_MACRO) * NIC_QM_OFFSET + + umr_block_id * NIC_UMR_OFFSET; + blocks[umr_start_idx + i].size = HL_BLOCK_SIZE; + } + + /* Expose decoder HW configuration block to user */ + gaudi2_user_mapped_dec_init(gaudi2, USR_MAPPED_BLK_DEC_START_IDX); + + for (i = 1; i < NUM_OF_DCORES; ++i) { + blocks[USR_MAPPED_BLK_SM_START_IDX + 2 * (i - 1)].size = SM_OBJS_BLOCK_SIZE; + blocks[USR_MAPPED_BLK_SM_START_IDX + 2 * (i - 1) + 1].size = HL_BLOCK_SIZE; + + blocks[USR_MAPPED_BLK_SM_START_IDX + 2 * (i - 1)].address = + mmDCORE0_SYNC_MNGR_OBJS_BASE + i * DCORE_OFFSET; + + blocks[USR_MAPPED_BLK_SM_START_IDX + 2 * (i - 1) + 1].address = + mmDCORE0_SYNC_MNGR_GLBL_BASE + i * DCORE_OFFSET; + } +} + +static int gaudi2_alloc_cpu_accessible_dma_mem(struct hl_device *hdev) +{ + dma_addr_t dma_addr_arr[GAUDI2_ALLOC_CPU_MEM_RETRY_CNT] = {}, end_addr; + void *virt_addr_arr[GAUDI2_ALLOC_CPU_MEM_RETRY_CNT] = {}; + int i, j, rc = 0; + + /* The device ARC works with 32-bits addresses, and because there is a single HW register + * that holds the extension bits (49..28), these bits must be identical in all the allocated + * range. + */ + + for (i = 0 ; i < GAUDI2_ALLOC_CPU_MEM_RETRY_CNT ; i++) { + virt_addr_arr[i] = hl_asic_dma_alloc_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, + &dma_addr_arr[i], GFP_KERNEL | __GFP_ZERO); + if (!virt_addr_arr[i]) { + rc = -ENOMEM; + goto free_dma_mem_arr; + } + + end_addr = dma_addr_arr[i] + HL_CPU_ACCESSIBLE_MEM_SIZE - 1; + if (GAUDI2_ARC_PCI_MSB_ADDR(dma_addr_arr[i]) == GAUDI2_ARC_PCI_MSB_ADDR(end_addr)) + break; + } + + if (i == GAUDI2_ALLOC_CPU_MEM_RETRY_CNT) { + dev_err(hdev->dev, + "MSB of ARC accessible DMA memory are not identical in all range\n"); + rc = -EFAULT; + goto free_dma_mem_arr; + } + + hdev->cpu_accessible_dma_mem = virt_addr_arr[i]; + hdev->cpu_accessible_dma_address = dma_addr_arr[i]; + +free_dma_mem_arr: + for (j = 0 ; j < i ; j++) + hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, virt_addr_arr[j], + dma_addr_arr[j]); + + return rc; +} + +static void gaudi2_set_pci_memory_regions(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct pci_mem_region *region; + + /* CFG */ + region = &hdev->pci_mem_region[PCI_REGION_CFG]; + region->region_base = CFG_BASE; + region->region_size = CFG_SIZE; + region->offset_in_bar = CFG_BASE - STM_FLASH_BASE_ADDR; + region->bar_size = CFG_BAR_SIZE; + region->bar_id = SRAM_CFG_BAR_ID; + region->used = 1; + + /* SRAM */ + region = &hdev->pci_mem_region[PCI_REGION_SRAM]; + region->region_base = SRAM_BASE_ADDR; + region->region_size = SRAM_SIZE; + region->offset_in_bar = CFG_REGION_SIZE + BAR0_RSRVD_SIZE; + region->bar_size = CFG_BAR_SIZE; + region->bar_id = SRAM_CFG_BAR_ID; + region->used = 1; + + /* DRAM */ + region = &hdev->pci_mem_region[PCI_REGION_DRAM]; + region->region_base = DRAM_PHYS_BASE; + region->region_size = hdev->asic_prop.dram_size; + region->offset_in_bar = 0; + region->bar_size = prop->dram_pci_bar_size; + region->bar_id = DRAM_BAR_ID; + region->used = 1; +} + +static void gaudi2_user_interrupt_setup(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + int i, j, k; + + /* Initialize common user CQ interrupt */ + HL_USR_INTR_STRUCT_INIT(hdev->common_user_cq_interrupt, hdev, + HL_COMMON_USER_CQ_INTERRUPT_ID, false); + + /* Initialize common decoder interrupt */ + HL_USR_INTR_STRUCT_INIT(hdev->common_decoder_interrupt, hdev, + HL_COMMON_DEC_INTERRUPT_ID, true); + + /* User interrupts structure holds both decoder and user interrupts from various engines. + * We first initialize the decoder interrupts and then we add the user interrupts. + * The only limitation is that the last decoder interrupt id must be smaller + * then GAUDI2_IRQ_NUM_USER_FIRST. This is checked at compilation time. + */ + + /* Initialize decoder interrupts, expose only normal interrupts, + * error interrupts to be handled by driver + */ + for (i = GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM, j = 0 ; i <= GAUDI2_IRQ_NUM_SHARED_DEC1_NRM; + i += 2, j++) + HL_USR_INTR_STRUCT_INIT(hdev->user_interrupt[j], hdev, i, true); + + for (i = GAUDI2_IRQ_NUM_USER_FIRST, k = 0 ; k < prop->user_interrupt_count; i++, j++, k++) + HL_USR_INTR_STRUCT_INIT(hdev->user_interrupt[j], hdev, i, false); +} + +static inline int gaudi2_get_non_zero_random_int(void) +{ + int rand = get_random_int(); + + return rand ? rand : 1; +} + +static int gaudi2_sw_init(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct gaudi2_device *gaudi2; + int i, rc; + + /* Allocate device structure */ + gaudi2 = kzalloc(sizeof(*gaudi2), GFP_KERNEL); + if (!gaudi2) + return -ENOMEM; + + for (i = 0 ; i < ARRAY_SIZE(gaudi2_irq_map_table) ; i++) { + if (gaudi2_irq_map_table[i].msg || !gaudi2_irq_map_table[i].valid) + continue; + + if (gaudi2->num_of_valid_hw_events == GAUDI2_EVENT_SIZE) { + dev_err(hdev->dev, "H/W events array exceeds the limit of %u events\n", + GAUDI2_EVENT_SIZE); + rc = -EINVAL; + goto free_gaudi2_device; + } + + gaudi2->hw_events[gaudi2->num_of_valid_hw_events++] = gaudi2_irq_map_table[i].fc_id; + } + + for (i = 0 ; i < MME_NUM_OF_LFSR_SEEDS ; i++) + gaudi2->lfsr_rand_seeds[i] = gaudi2_get_non_zero_random_int(); + + gaudi2->cpucp_info_get = gaudi2_cpucp_info_get; + + hdev->asic_specific = gaudi2; + + /* Create DMA pool for small allocations. + * Use DEVICE_CACHE_LINE_SIZE for alignment since the NIC memory-mapped + * PI/CI registers allocated from this pool have this restriction + */ + hdev->dma_pool = dma_pool_create(dev_name(hdev->dev), &hdev->pdev->dev, + GAUDI2_DMA_POOL_BLK_SIZE, DEVICE_CACHE_LINE_SIZE, 0); + if (!hdev->dma_pool) { + dev_err(hdev->dev, "failed to create DMA pool\n"); + rc = -ENOMEM; + goto free_gaudi2_device; + } + + rc = gaudi2_alloc_cpu_accessible_dma_mem(hdev); + if (rc) + goto free_dma_pool; + + hdev->cpu_accessible_dma_pool = gen_pool_create(ilog2(32), -1); + if (!hdev->cpu_accessible_dma_pool) { + dev_err(hdev->dev, "Failed to create CPU accessible DMA pool\n"); + rc = -ENOMEM; + goto free_cpu_dma_mem; + } + + rc = gen_pool_add(hdev->cpu_accessible_dma_pool, (uintptr_t) hdev->cpu_accessible_dma_mem, + HL_CPU_ACCESSIBLE_MEM_SIZE, -1); + if (rc) { + dev_err(hdev->dev, "Failed to add memory to CPU accessible DMA pool\n"); + rc = -EFAULT; + goto free_cpu_accessible_dma_pool; + } + + gaudi2->virt_msix_db_cpu_addr = hl_cpu_accessible_dma_pool_alloc(hdev, prop->pmmu.page_size, + &gaudi2->virt_msix_db_dma_addr); + if (!gaudi2->virt_msix_db_cpu_addr) { + dev_err(hdev->dev, "Failed to allocate DMA memory for virtual MSI-X doorbell\n"); + rc = -ENOMEM; + goto free_cpu_accessible_dma_pool; + } + + spin_lock_init(&gaudi2->hw_queues_lock); + spin_lock_init(&gaudi2->kdma_lock); + + gaudi2->scratchpad_kernel_address = hl_asic_dma_alloc_coherent(hdev, PAGE_SIZE, + &gaudi2->scratchpad_bus_address, + GFP_KERNEL | __GFP_ZERO); + if (!gaudi2->scratchpad_kernel_address) { + rc = -ENOMEM; + goto free_virt_msix_db_mem; + } + + gaudi2_user_mapped_blocks_init(hdev); + + /* Initialize user interrupts */ + gaudi2_user_interrupt_setup(hdev); + + hdev->supports_coresight = true; + hdev->supports_sync_stream = true; + hdev->supports_cb_mapping = true; + hdev->supports_wait_for_multi_cs = false; + + prop->supports_compute_reset = true; + + hdev->asic_funcs->set_pci_memory_regions(hdev); + + return 0; + +free_virt_msix_db_mem: + hl_cpu_accessible_dma_pool_free(hdev, prop->pmmu.page_size, gaudi2->virt_msix_db_cpu_addr); +free_cpu_accessible_dma_pool: + gen_pool_destroy(hdev->cpu_accessible_dma_pool); +free_cpu_dma_mem: + hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->cpu_accessible_dma_mem, + hdev->cpu_accessible_dma_address); +free_dma_pool: + dma_pool_destroy(hdev->dma_pool); +free_gaudi2_device: + kfree(gaudi2); + return rc; +} + +static int gaudi2_sw_fini(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct gaudi2_device *gaudi2 = hdev->asic_specific; + + hl_cpu_accessible_dma_pool_free(hdev, prop->pmmu.page_size, gaudi2->virt_msix_db_cpu_addr); + + gen_pool_destroy(hdev->cpu_accessible_dma_pool); + + hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->cpu_accessible_dma_mem, + hdev->cpu_accessible_dma_address); + + hl_asic_dma_free_coherent(hdev, PAGE_SIZE, gaudi2->scratchpad_kernel_address, + gaudi2->scratchpad_bus_address); + + dma_pool_destroy(hdev->dma_pool); + + kfree(gaudi2); + + return 0; +} + +static void gaudi2_stop_qman_common(struct hl_device *hdev, u32 reg_base) +{ + WREG32(reg_base + QM_GLBL_CFG1_OFFSET, QM_GLBL_CFG1_PQF_STOP | + QM_GLBL_CFG1_CQF_STOP | + QM_GLBL_CFG1_CP_STOP); + + /* stop also the ARC */ + WREG32(reg_base + QM_GLBL_CFG2_OFFSET, QM_GLBL_CFG2_ARC_CQF_STOP); +} + +static void gaudi2_flush_qman_common(struct hl_device *hdev, u32 reg_base) +{ + WREG32(reg_base + QM_GLBL_CFG1_OFFSET, QM_GLBL_CFG1_PQF_FLUSH | + QM_GLBL_CFG1_CQF_FLUSH | + QM_GLBL_CFG1_CP_FLUSH); +} + +static void gaudi2_flush_qman_arc_common(struct hl_device *hdev, u32 reg_base) +{ + WREG32(reg_base + QM_GLBL_CFG2_OFFSET, QM_GLBL_CFG2_ARC_CQF_FLUSH); +} + +/** + * gaudi2_clear_qm_fence_counters_common - clear QM's fence counters + * + * @hdev: pointer to the habanalabs device structure + * @queue_id: queue to clear fence counters to + * @skip_fence: if true set maximum fence value to all fence counters to avoid + * getting stuck on any fence value. otherwise set all fence + * counters to 0 (standard clear of fence counters) + */ +static void gaudi2_clear_qm_fence_counters_common(struct hl_device *hdev, u32 queue_id, + bool skip_fence) +{ + u32 size, reg_base; + u32 addr, val; + + reg_base = gaudi2_qm_blocks_bases[queue_id]; + + addr = reg_base + QM_CP_FENCE0_CNT_0_OFFSET; + size = mmPDMA0_QM_CP_BARRIER_CFG - mmPDMA0_QM_CP_FENCE0_CNT_0; + + /* + * in case we want to make sure that QM that is stuck on a fence will + * be released we should set the fence counter to a higher value that + * the value the QM waiting for. to comply with any fence counter of + * any value we set maximum fence value to all counters + */ + val = skip_fence ? U32_MAX : 0; + gaudi2_memset_device_lbw(hdev, addr, size, val); +} + +static void gaudi2_qman_manual_flush_common(struct hl_device *hdev, u32 queue_id) +{ + u32 reg_base = gaudi2_qm_blocks_bases[queue_id]; + + gaudi2_clear_qm_fence_counters_common(hdev, queue_id, true); + gaudi2_flush_qman_common(hdev, reg_base); + gaudi2_flush_qman_arc_common(hdev, reg_base); +} + +static void gaudi2_stop_dma_qmans(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + int dcore, inst; + + if (!(gaudi2->hw_cap_initialized & HW_CAP_PDMA_MASK)) + goto stop_edma_qmans; + + /* Stop CPs of PDMA QMANs */ + gaudi2_stop_qman_common(hdev, mmPDMA0_QM_BASE); + gaudi2_stop_qman_common(hdev, mmPDMA1_QM_BASE); + +stop_edma_qmans: + if (!(gaudi2->hw_cap_initialized & HW_CAP_EDMA_MASK)) + return; + + for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) { + for (inst = 0 ; inst < NUM_OF_EDMA_PER_DCORE ; inst++) { + u8 seq = dcore * NUM_OF_EDMA_PER_DCORE + inst; + u32 qm_base; + + if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_EDMA_SHIFT + seq))) + continue; + + qm_base = mmDCORE0_EDMA0_QM_BASE + dcore * DCORE_OFFSET + + inst * DCORE_EDMA_OFFSET; + + /* Stop CPs of EDMA QMANs */ + gaudi2_stop_qman_common(hdev, qm_base); + } + } +} + +static void gaudi2_stop_mme_qmans(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 offset, i; + + offset = mmDCORE1_MME_QM_BASE - mmDCORE0_MME_QM_BASE; + + for (i = 0 ; i < NUM_OF_DCORES ; i++) { + if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_MME_SHIFT + i))) + continue; + + gaudi2_stop_qman_common(hdev, mmDCORE0_MME_QM_BASE + (i * offset)); + } +} + +static void gaudi2_stop_tpc_qmans(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 reg_base; + int i; + + if (!(gaudi2->tpc_hw_cap_initialized & HW_CAP_TPC_MASK)) + return; + + for (i = 0 ; i < TPC_ID_SIZE ; i++) { + if (!(gaudi2->tpc_hw_cap_initialized & BIT_ULL(HW_CAP_TPC_SHIFT + i))) + continue; + + reg_base = gaudi2_qm_blocks_bases[gaudi2_tpc_id_to_queue_id[i]]; + gaudi2_stop_qman_common(hdev, reg_base); + } +} + +static void gaudi2_stop_rot_qmans(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 reg_base; + int i; + + if (!(gaudi2->hw_cap_initialized & HW_CAP_ROT_MASK)) + return; + + for (i = 0 ; i < ROTATOR_ID_SIZE ; i++) { + if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_ROT_SHIFT + i))) + continue; + + reg_base = gaudi2_qm_blocks_bases[gaudi2_rot_id_to_queue_id[i]]; + gaudi2_stop_qman_common(hdev, reg_base); + } +} + +static void gaudi2_stop_nic_qmans(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 reg_base, queue_id; + int i; + + if (!(gaudi2->nic_hw_cap_initialized & HW_CAP_NIC_MASK)) + return; + + queue_id = GAUDI2_QUEUE_ID_NIC_0_0; + + for (i = 0 ; i < NIC_NUMBER_OF_ENGINES ; i++, queue_id += NUM_OF_PQ_PER_QMAN) { + if (!(hdev->nic_ports_mask & BIT(i))) + continue; + + reg_base = gaudi2_qm_blocks_bases[queue_id]; + gaudi2_stop_qman_common(hdev, reg_base); + } +} + +static void gaudi2_stall_dma_common(struct hl_device *hdev, u32 reg_base) +{ + u32 reg_val; + + reg_val = FIELD_PREP(PDMA0_CORE_CFG_1_HALT_MASK, 0x1); + WREG32(reg_base + DMA_CORE_CFG_1_OFFSET, reg_val); +} + +static void gaudi2_dma_stall(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + int dcore, inst; + + if (!(gaudi2->hw_cap_initialized & HW_CAP_PDMA_MASK)) + goto stall_edma; + + gaudi2_stall_dma_common(hdev, mmPDMA0_CORE_BASE); + gaudi2_stall_dma_common(hdev, mmPDMA1_CORE_BASE); + +stall_edma: + if (!(gaudi2->hw_cap_initialized & HW_CAP_EDMA_MASK)) + return; + + for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) { + for (inst = 0 ; inst < NUM_OF_EDMA_PER_DCORE ; inst++) { + u8 seq = dcore * NUM_OF_EDMA_PER_DCORE + inst; + u32 core_base; + + if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_EDMA_SHIFT + seq))) + continue; + + core_base = mmDCORE0_EDMA0_CORE_BASE + dcore * DCORE_OFFSET + + inst * DCORE_EDMA_OFFSET; + + /* Stall CPs of EDMA QMANs */ + gaudi2_stall_dma_common(hdev, core_base); + } + } +} + +static void gaudi2_mme_stall(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 offset, i; + + offset = mmDCORE1_MME_CTRL_LO_QM_STALL - mmDCORE0_MME_CTRL_LO_QM_STALL; + + for (i = 0 ; i < NUM_OF_DCORES ; i++) + if (gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_MME_SHIFT + i)) + WREG32(mmDCORE0_MME_CTRL_LO_QM_STALL + (i * offset), 1); +} + +static void gaudi2_tpc_stall(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 reg_base; + int i; + + if (!(gaudi2->tpc_hw_cap_initialized & HW_CAP_TPC_MASK)) + return; + + for (i = 0 ; i < TPC_ID_SIZE ; i++) { + if (!(gaudi2->tpc_hw_cap_initialized & BIT_ULL(HW_CAP_TPC_SHIFT + i))) + continue; + + reg_base = gaudi2_tpc_cfg_blocks_bases[i]; + WREG32(reg_base + TPC_CFG_STALL_OFFSET, 1); + } +} + +static void gaudi2_rotator_stall(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 reg_val; + int i; + + if (!(gaudi2->hw_cap_initialized & HW_CAP_ROT_MASK)) + return; + + reg_val = FIELD_PREP(ROT_MSS_HALT_WBC_MASK, 0x1) | + FIELD_PREP(ROT_MSS_HALT_RSB_MASK, 0x1) | + FIELD_PREP(ROT_MSS_HALT_MRSB_MASK, 0x1); + + for (i = 0 ; i < ROTATOR_ID_SIZE ; i++) { + if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_ROT_SHIFT + i))) + continue; + + WREG32(mmROT0_MSS_HALT + i * ROT_OFFSET, reg_val); + } +} + +static void gaudi2_disable_qman_common(struct hl_device *hdev, u32 reg_base) +{ + WREG32(reg_base + QM_GLBL_CFG0_OFFSET, 0); +} + +static void gaudi2_disable_dma_qmans(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + int dcore, inst; + + if (!(gaudi2->hw_cap_initialized & HW_CAP_PDMA_MASK)) + goto stop_edma_qmans; + + gaudi2_disable_qman_common(hdev, mmPDMA0_QM_BASE); + gaudi2_disable_qman_common(hdev, mmPDMA1_QM_BASE); + +stop_edma_qmans: + if (!(gaudi2->hw_cap_initialized & HW_CAP_EDMA_MASK)) + return; + + for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) { + for (inst = 0 ; inst < NUM_OF_EDMA_PER_DCORE ; inst++) { + u8 seq = dcore * NUM_OF_EDMA_PER_DCORE + inst; + u32 qm_base; + + if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_EDMA_SHIFT + seq))) + continue; + + qm_base = mmDCORE0_EDMA0_QM_BASE + dcore * DCORE_OFFSET + + inst * DCORE_EDMA_OFFSET; + + /* Disable CPs of EDMA QMANs */ + gaudi2_disable_qman_common(hdev, qm_base); + } + } +} + +static void gaudi2_disable_mme_qmans(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 offset, i; + + offset = mmDCORE1_MME_QM_BASE - mmDCORE0_MME_QM_BASE; + + for (i = 0 ; i < NUM_OF_DCORES ; i++) + if (gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_MME_SHIFT + i)) + gaudi2_disable_qman_common(hdev, mmDCORE0_MME_QM_BASE + (i * offset)); +} + +static void gaudi2_disable_tpc_qmans(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 reg_base; + int i; + + if (!(gaudi2->tpc_hw_cap_initialized & HW_CAP_TPC_MASK)) + return; + + for (i = 0 ; i < TPC_ID_SIZE ; i++) { + if (!(gaudi2->tpc_hw_cap_initialized & BIT_ULL(HW_CAP_TPC_SHIFT + i))) + continue; + + reg_base = gaudi2_qm_blocks_bases[gaudi2_tpc_id_to_queue_id[i]]; + gaudi2_disable_qman_common(hdev, reg_base); + } +} + +static void gaudi2_disable_rot_qmans(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 reg_base; + int i; + + if (!(gaudi2->hw_cap_initialized & HW_CAP_ROT_MASK)) + return; + + for (i = 0 ; i < ROTATOR_ID_SIZE ; i++) { + if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_ROT_SHIFT + i))) + continue; + + reg_base = gaudi2_qm_blocks_bases[gaudi2_rot_id_to_queue_id[i]]; + gaudi2_disable_qman_common(hdev, reg_base); + } +} + +static void gaudi2_disable_nic_qmans(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 reg_base, queue_id; + int i; + + if (!(gaudi2->nic_hw_cap_initialized & HW_CAP_NIC_MASK)) + return; + + queue_id = GAUDI2_QUEUE_ID_NIC_0_0; + + for (i = 0 ; i < NIC_NUMBER_OF_ENGINES ; i++, queue_id += NUM_OF_PQ_PER_QMAN) { + if (!(hdev->nic_ports_mask & BIT(i))) + continue; + + reg_base = gaudi2_qm_blocks_bases[queue_id]; + gaudi2_disable_qman_common(hdev, reg_base); + } +} + +static void gaudi2_enable_timestamp(struct hl_device *hdev) +{ + /* Disable the timestamp counter */ + WREG32(mmPSOC_TIMESTAMP_BASE, 0); + + /* Zero the lower/upper parts of the 64-bit counter */ + WREG32(mmPSOC_TIMESTAMP_BASE + 0xC, 0); + WREG32(mmPSOC_TIMESTAMP_BASE + 0x8, 0); + + /* Enable the counter */ + WREG32(mmPSOC_TIMESTAMP_BASE, 1); +} + +static void gaudi2_disable_timestamp(struct hl_device *hdev) +{ + /* Disable the timestamp counter */ + WREG32(mmPSOC_TIMESTAMP_BASE, 0); +} + +static const char *gaudi2_irq_name(u16 irq_number) +{ + switch (irq_number) { + case GAUDI2_IRQ_NUM_EVENT_QUEUE: + return "gaudi2 cpu eq"; + case GAUDI2_IRQ_NUM_COMPLETION: + return "gaudi2 completion"; + case GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM ... GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM: + return gaudi2_vdec_irq_name[irq_number - GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM]; + case GAUDI2_IRQ_NUM_USER_FIRST ... GAUDI2_IRQ_NUM_USER_LAST: + return "gaudi2 user completion"; + default: + return "invalid"; + } +} + +static void gaudi2_dec_disable_msix(struct hl_device *hdev, u32 max_irq_num) +{ + int i, irq, relative_idx; + struct hl_dec *dec; + + for (i = GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM ; i < max_irq_num ; i++) { + irq = pci_irq_vector(hdev->pdev, i); + relative_idx = i - GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM; + + dec = hdev->dec + relative_idx / 2; + + /* We pass different structures depending on the irq handler. For the abnormal + * interrupt we pass hl_dec and for the regular interrupt we pass the relevant + * user_interrupt entry + */ + free_irq(irq, ((relative_idx % 2) ? + (void *) dec : + (void *) &hdev->user_interrupt[dec->core_id])); + } +} + +static int gaudi2_dec_enable_msix(struct hl_device *hdev) +{ + int rc, i, irq_init_cnt, irq, relative_idx; + irq_handler_t irq_handler; + struct hl_dec *dec; + + for (i = GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM, irq_init_cnt = 0; + i <= GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM; + i++, irq_init_cnt++) { + + irq = pci_irq_vector(hdev->pdev, i); + relative_idx = i - GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM; + + irq_handler = (relative_idx % 2) ? + hl_irq_handler_dec_abnrm : + hl_irq_handler_user_interrupt; + + dec = hdev->dec + relative_idx / 2; + + /* We pass different structures depending on the irq handler. For the abnormal + * interrupt we pass hl_dec and for the regular interrupt we pass the relevant + * user_interrupt entry + */ + rc = request_irq(irq, irq_handler, 0, gaudi2_irq_name(i), + ((relative_idx % 2) ? + (void *) dec : + (void *) &hdev->user_interrupt[dec->core_id])); + if (rc) { + dev_err(hdev->dev, "Failed to request IRQ %d", irq); + goto free_dec_irqs; + } + } + + return 0; + +free_dec_irqs: + gaudi2_dec_disable_msix(hdev, (GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM + irq_init_cnt)); + return rc; +} + +static int gaudi2_enable_msix(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct gaudi2_device *gaudi2 = hdev->asic_specific; + int rc, irq, i, j, user_irq_init_cnt; + irq_handler_t irq_handler; + struct hl_cq *cq; + + if (gaudi2->hw_cap_initialized & HW_CAP_MSIX) + return 0; + + rc = pci_alloc_irq_vectors(hdev->pdev, GAUDI2_MSIX_ENTRIES, GAUDI2_MSIX_ENTRIES, + PCI_IRQ_MSIX); + if (rc < 0) { + dev_err(hdev->dev, "MSI-X: Failed to enable support -- %d/%d\n", + GAUDI2_MSIX_ENTRIES, rc); + return rc; + } + + irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_COMPLETION); + cq = &hdev->completion_queue[GAUDI2_RESERVED_CQ_CS_COMPLETION]; + rc = request_irq(irq, hl_irq_handler_cq, 0, gaudi2_irq_name(GAUDI2_IRQ_NUM_COMPLETION), cq); + if (rc) { + dev_err(hdev->dev, "Failed to request IRQ %d", irq); + goto free_irq_vectors; + } + + irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_EVENT_QUEUE); + rc = request_irq(irq, hl_irq_handler_eq, 0, gaudi2_irq_name(GAUDI2_IRQ_NUM_EVENT_QUEUE), + &hdev->event_queue); + if (rc) { + dev_err(hdev->dev, "Failed to request IRQ %d", irq); + goto free_completion_irq; + } + + rc = gaudi2_dec_enable_msix(hdev); + if (rc) { + dev_err(hdev->dev, "Failed to enable decoder IRQ"); + goto free_completion_irq; + } + + for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = prop->user_dec_intr_count, user_irq_init_cnt = 0; + user_irq_init_cnt < prop->user_interrupt_count; + i++, j++, user_irq_init_cnt++) { + + irq = pci_irq_vector(hdev->pdev, i); + irq_handler = hl_irq_handler_user_interrupt; + + rc = request_irq(irq, irq_handler, 0, gaudi2_irq_name(i), &hdev->user_interrupt[j]); + if (rc) { + dev_err(hdev->dev, "Failed to request IRQ %d", irq); + goto free_user_irq; + } + } + + gaudi2->hw_cap_initialized |= HW_CAP_MSIX; + + return 0; + +free_user_irq: + for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = prop->user_dec_intr_count; + i < GAUDI2_IRQ_NUM_USER_FIRST + user_irq_init_cnt ; i++, j++) { + + irq = pci_irq_vector(hdev->pdev, i); + free_irq(irq, &hdev->user_interrupt[j]); + } + + gaudi2_dec_disable_msix(hdev, GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM + 1); + +free_completion_irq: + irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_COMPLETION); + free_irq(irq, cq); + +free_irq_vectors: + pci_free_irq_vectors(hdev->pdev); + + return rc; +} + +static void gaudi2_sync_irqs(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + int i, j; + int irq; + + if (!(gaudi2->hw_cap_initialized & HW_CAP_MSIX)) + return; + + /* Wait for all pending IRQs to be finished */ + synchronize_irq(pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_COMPLETION)); + + for (i = GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM ; i <= GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM ; i++) { + irq = pci_irq_vector(hdev->pdev, i); + synchronize_irq(irq); + } + + for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = 0 ; j < hdev->asic_prop.user_interrupt_count; + i++, j++) { + irq = pci_irq_vector(hdev->pdev, i); + synchronize_irq(irq); + } + + synchronize_irq(pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_EVENT_QUEUE)); +} + +static void gaudi2_disable_msix(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct gaudi2_device *gaudi2 = hdev->asic_specific; + struct hl_cq *cq; + int irq, i, j, k; + + if (!(gaudi2->hw_cap_initialized & HW_CAP_MSIX)) + return; + + gaudi2_sync_irqs(hdev); + + irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_EVENT_QUEUE); + free_irq(irq, &hdev->event_queue); + + gaudi2_dec_disable_msix(hdev, GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM + 1); + + for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = prop->user_dec_intr_count, k = 0; + k < hdev->asic_prop.user_interrupt_count ; i++, j++, k++) { + + irq = pci_irq_vector(hdev->pdev, i); + free_irq(irq, &hdev->user_interrupt[j]); + } + + irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_COMPLETION); + cq = &hdev->completion_queue[GAUDI2_RESERVED_CQ_CS_COMPLETION]; + free_irq(irq, cq); + + pci_free_irq_vectors(hdev->pdev); + + gaudi2->hw_cap_initialized &= ~HW_CAP_MSIX; +} + +static void gaudi2_stop_dcore_dec(struct hl_device *hdev, int dcore_id) +{ + u32 reg_val = FIELD_PREP(DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK, 0x1); + u32 graceful_pend_mask = DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_PEND_MASK; + u32 timeout_usec, dec_id, dec_bit, offset, graceful; + int rc; + + if (hdev->pldm) + timeout_usec = GAUDI2_PLDM_VDEC_TIMEOUT_USEC; + else + timeout_usec = GAUDI2_VDEC_TIMEOUT_USEC; + + for (dec_id = 0 ; dec_id < NUM_OF_DEC_PER_DCORE ; dec_id++) { + dec_bit = dcore_id * NUM_OF_DEC_PER_DCORE + dec_id; + if (!(hdev->asic_prop.decoder_enabled_mask & BIT(dec_bit))) + continue; + + offset = dcore_id * DCORE_OFFSET + dec_id * DCORE_VDEC_OFFSET; + + WREG32(mmDCORE0_DEC0_CMD_SWREG16 + offset, 0); + + WREG32(mmDCORE0_VDEC0_BRDG_CTRL_GRACEFUL + offset, reg_val); + + /* Wait till all traffic from decoder stops + * before apply core reset. + */ + rc = hl_poll_timeout( + hdev, + mmDCORE0_VDEC0_BRDG_CTRL_GRACEFUL + offset, + graceful, + (graceful & graceful_pend_mask), + 100, + timeout_usec); + if (rc) + dev_err(hdev->dev, + "Failed to stop traffic from DCORE%d Decoder %d\n", + dcore_id, dec_id); + } +} + +static void gaudi2_stop_pcie_dec(struct hl_device *hdev) +{ + u32 reg_val = FIELD_PREP(DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK, 0x1); + u32 graceful_pend_mask = PCIE_VDEC0_BRDG_CTRL_GRACEFUL_PEND_MASK; + u32 timeout_usec, dec_id, dec_bit, offset, graceful; + int rc; + + if (hdev->pldm) + timeout_usec = GAUDI2_PLDM_VDEC_TIMEOUT_USEC; + else + timeout_usec = GAUDI2_VDEC_TIMEOUT_USEC; + + for (dec_id = 0 ; dec_id < NUM_OF_DEC_PER_DCORE ; dec_id++) { + dec_bit = PCIE_DEC_SHIFT + dec_id; + if (!(hdev->asic_prop.decoder_enabled_mask & BIT(dec_bit))) + continue; + + offset = dec_id * PCIE_VDEC_OFFSET; + + WREG32(mmPCIE_DEC0_CMD_SWREG16 + offset, 0); + + WREG32(mmPCIE_VDEC0_BRDG_CTRL_GRACEFUL + offset, reg_val); + + /* Wait till all traffic from decoder stops + * before apply core reset. + */ + rc = hl_poll_timeout( + hdev, + mmPCIE_VDEC0_BRDG_CTRL_GRACEFUL + offset, + graceful, + (graceful & graceful_pend_mask), + 100, + timeout_usec); + if (rc) + dev_err(hdev->dev, + "Failed to stop traffic from PCIe Decoder %d\n", + dec_id); + } +} + +static void gaudi2_stop_dec(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + int dcore_id; + + if ((gaudi2->dec_hw_cap_initialized & HW_CAP_DEC_MASK) == 0) + return; + + for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++) + gaudi2_stop_dcore_dec(hdev, dcore_id); + + gaudi2_stop_pcie_dec(hdev); +} + +static void gaudi2_halt_arc(struct hl_device *hdev, u32 cpu_id) +{ + u32 reg_base, reg_val; + + reg_base = gaudi2_arc_blocks_bases[cpu_id]; + + /* Halt ARC */ + reg_val = FIELD_PREP(ARC_FARM_ARC0_AUX_RUN_HALT_REQ_HALT_REQ_MASK, 1); + WREG32(reg_base + ARC_HALT_REQ_OFFSET, reg_val); +} + +static void gaudi2_halt_arcs(struct hl_device *hdev) +{ + u16 arc_id; + + for (arc_id = CPU_ID_SCHED_ARC0; arc_id < CPU_ID_MAX; arc_id++) { + if (gaudi2_is_arc_enabled(hdev, arc_id)) + gaudi2_halt_arc(hdev, arc_id); + } +} + +static void gaudi2_reset_arcs(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u16 arc_id; + + if (!gaudi2) + return; + + for (arc_id = CPU_ID_SCHED_ARC0; arc_id < CPU_ID_MAX; arc_id++) + if (gaudi2_is_arc_enabled(hdev, arc_id)) + gaudi2_clr_arc_id_cap(hdev, arc_id); +} + +static void gaudi2_nic_qmans_manual_flush(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 queue_id; + int i; + + if (!(gaudi2->nic_hw_cap_initialized & HW_CAP_NIC_MASK)) + return; + + queue_id = GAUDI2_QUEUE_ID_NIC_0_0; + + for (i = 0 ; i < NIC_NUMBER_OF_ENGINES ; i++, queue_id += NUM_OF_PQ_PER_QMAN) + gaudi2_qman_manual_flush_common(hdev, queue_id); +} + +static void gaudi2_halt_engines(struct hl_device *hdev, bool hard_reset, bool fw_reset) +{ + u32 wait_timeout_ms; + + if (hdev->pldm) + wait_timeout_ms = GAUDI2_PLDM_RESET_WAIT_MSEC; + else + wait_timeout_ms = GAUDI2_RESET_WAIT_MSEC; + + if (fw_reset) + goto skip_engines; + + gaudi2_stop_dma_qmans(hdev); + gaudi2_stop_mme_qmans(hdev); + gaudi2_stop_tpc_qmans(hdev); + gaudi2_stop_rot_qmans(hdev); + gaudi2_stop_nic_qmans(hdev); + msleep(wait_timeout_ms); + + gaudi2_halt_arcs(hdev); + gaudi2_dma_stall(hdev); + gaudi2_mme_stall(hdev); + gaudi2_tpc_stall(hdev); + gaudi2_rotator_stall(hdev); + + msleep(wait_timeout_ms); + + gaudi2_stop_dec(hdev); + + /* + * in case of soft reset do a manual flush for QMANs (currently called + * only for NIC QMANs + */ + if (!hard_reset) + gaudi2_nic_qmans_manual_flush(hdev); + + gaudi2_disable_dma_qmans(hdev); + gaudi2_disable_mme_qmans(hdev); + gaudi2_disable_tpc_qmans(hdev); + gaudi2_disable_rot_qmans(hdev); + gaudi2_disable_nic_qmans(hdev); + gaudi2_disable_timestamp(hdev); + +skip_engines: + if (hard_reset) { + gaudi2_disable_msix(hdev); + return; + } + + gaudi2_sync_irqs(hdev); +} + +static void gaudi2_init_firmware_preload_params(struct hl_device *hdev) +{ + struct pre_fw_load_props *pre_fw_load = &hdev->fw_loader.pre_fw_load; + + pre_fw_load->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS; + pre_fw_load->sts_boot_dev_sts0_reg = mmCPU_BOOT_DEV_STS0; + pre_fw_load->sts_boot_dev_sts1_reg = mmCPU_BOOT_DEV_STS1; + pre_fw_load->boot_err0_reg = mmCPU_BOOT_ERR0; + pre_fw_load->boot_err1_reg = mmCPU_BOOT_ERR1; + pre_fw_load->wait_for_preboot_timeout = GAUDI2_PREBOOT_REQ_TIMEOUT_USEC; +} + +static void gaudi2_init_firmware_loader(struct hl_device *hdev) +{ + struct fw_load_mgr *fw_loader = &hdev->fw_loader; + struct dynamic_fw_load_mgr *dynamic_loader; + struct cpu_dyn_regs *dyn_regs; + + /* fill common fields */ + fw_loader->fw_comp_loaded = FW_TYPE_NONE; + fw_loader->boot_fit_img.image_name = GAUDI2_BOOT_FIT_FILE; + fw_loader->linux_img.image_name = GAUDI2_LINUX_FW_FILE; + fw_loader->boot_fit_timeout = GAUDI2_BOOT_FIT_REQ_TIMEOUT_USEC; + fw_loader->skip_bmc = false; + fw_loader->sram_bar_id = SRAM_CFG_BAR_ID; + fw_loader->dram_bar_id = DRAM_BAR_ID; + + if (hdev->asic_type == ASIC_GAUDI2 || hdev->asic_type == ASIC_GAUDI2_SEC) + fw_loader->cpu_timeout = GAUDI2_CPU_TIMEOUT_USEC; + else /* ASIC_GAUDI2_FPGA */ + fw_loader->cpu_timeout = GAUDI2_FPGA_CPU_TIMEOUT; + + /* here we update initial values for few specific dynamic regs (as + * before reading the first descriptor from FW those value has to be + * hard-coded). in later stages of the protocol those values will be + * updated automatically by reading the FW descriptor so data there + * will always be up-to-date + */ + dynamic_loader = &hdev->fw_loader.dynamic_loader; + dyn_regs = &dynamic_loader->comm_desc.cpu_dyn_regs; + dyn_regs->kmd_msg_to_cpu = cpu_to_le32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU); + dyn_regs->cpu_cmd_status_to_host = cpu_to_le32(mmCPU_CMD_STATUS_TO_HOST); + dynamic_loader->wait_for_bl_timeout = GAUDI2_WAIT_FOR_BL_TIMEOUT_USEC; +} + +static int gaudi2_init_cpu(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + int rc; + + if (!(hdev->fw_components & FW_TYPE_PREBOOT_CPU)) + return 0; + + if (gaudi2->hw_cap_initialized & HW_CAP_CPU) + return 0; + + rc = hl_fw_init_cpu(hdev); + if (rc) + return rc; + + gaudi2->hw_cap_initialized |= HW_CAP_CPU; + + return 0; +} + +static int gaudi2_init_cpu_queues(struct hl_device *hdev, u32 cpu_timeout) +{ + struct hl_hw_queue *cpu_pq = &hdev->kernel_queues[GAUDI2_QUEUE_ID_CPU_PQ]; + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct gaudi2_device *gaudi2 = hdev->asic_specific; + struct cpu_dyn_regs *dyn_regs; + struct hl_eq *eq; + u32 status; + int err; + + if (!hdev->cpu_queues_enable) + return 0; + + if (gaudi2->hw_cap_initialized & HW_CAP_CPU_Q) + return 0; + + eq = &hdev->event_queue; + + dyn_regs = &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs; + + WREG32(mmCPU_IF_PQ_BASE_ADDR_LOW, lower_32_bits(cpu_pq->bus_address)); + WREG32(mmCPU_IF_PQ_BASE_ADDR_HIGH, upper_32_bits(cpu_pq->bus_address)); + + WREG32(mmCPU_IF_EQ_BASE_ADDR_LOW, lower_32_bits(eq->bus_address)); + WREG32(mmCPU_IF_EQ_BASE_ADDR_HIGH, upper_32_bits(eq->bus_address)); + + WREG32(mmCPU_IF_CQ_BASE_ADDR_LOW, lower_32_bits(hdev->cpu_accessible_dma_address)); + WREG32(mmCPU_IF_CQ_BASE_ADDR_HIGH, upper_32_bits(hdev->cpu_accessible_dma_address)); + + WREG32(mmCPU_IF_PQ_LENGTH, HL_QUEUE_SIZE_IN_BYTES); + WREG32(mmCPU_IF_EQ_LENGTH, HL_EQ_SIZE_IN_BYTES); + WREG32(mmCPU_IF_CQ_LENGTH, HL_CPU_ACCESSIBLE_MEM_SIZE); + + /* Used for EQ CI */ + WREG32(mmCPU_IF_EQ_RD_OFFS, 0); + + WREG32(mmCPU_IF_PF_PQ_PI, 0); + + WREG32(mmCPU_IF_QUEUE_INIT, PQ_INIT_STATUS_READY_FOR_CP); + + /* Let the ARC know we are ready as it is now handling those queues */ + + WREG32(le32_to_cpu(dyn_regs->gic_host_pi_upd_irq), + gaudi2_irq_map_table[GAUDI2_EVENT_CPU_PI_UPDATE].cpu_id); + + err = hl_poll_timeout( + hdev, + mmCPU_IF_QUEUE_INIT, + status, + (status == PQ_INIT_STATUS_READY_FOR_HOST), + 1000, + cpu_timeout); + + if (err) { + dev_err(hdev->dev, "Failed to communicate with device CPU (timeout)\n"); + return -EIO; + } + + /* update FW application security bits */ + if (prop->fw_cpu_boot_dev_sts0_valid) + prop->fw_app_cpu_boot_dev_sts0 = RREG32(mmCPU_BOOT_DEV_STS0); + + if (prop->fw_cpu_boot_dev_sts1_valid) + prop->fw_app_cpu_boot_dev_sts1 = RREG32(mmCPU_BOOT_DEV_STS1); + + gaudi2->hw_cap_initialized |= HW_CAP_CPU_Q; + return 0; +} + +static void gaudi2_init_qman_pq(struct hl_device *hdev, u32 reg_base, + u32 queue_id_base) +{ + struct hl_hw_queue *q; + u32 pq_id, pq_offset; + + for (pq_id = 0 ; pq_id < NUM_OF_PQ_PER_QMAN ; pq_id++) { + q = &hdev->kernel_queues[queue_id_base + pq_id]; + pq_offset = pq_id * 4; + + WREG32(reg_base + QM_PQ_BASE_LO_0_OFFSET + pq_offset, + lower_32_bits(q->bus_address)); + WREG32(reg_base + QM_PQ_BASE_HI_0_OFFSET + pq_offset, + upper_32_bits(q->bus_address)); + WREG32(reg_base + QM_PQ_SIZE_0_OFFSET + pq_offset, ilog2(HL_QUEUE_LENGTH)); + WREG32(reg_base + QM_PQ_PI_0_OFFSET + pq_offset, 0); + WREG32(reg_base + QM_PQ_CI_0_OFFSET + pq_offset, 0); + } +} + +static void gaudi2_init_qman_cp(struct hl_device *hdev, u32 reg_base) +{ + u32 cp_id, cp_offset, mtr_base_lo, mtr_base_hi, so_base_lo, so_base_hi; + + mtr_base_lo = lower_32_bits(CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); + mtr_base_hi = upper_32_bits(CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); + so_base_lo = lower_32_bits(CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0); + so_base_hi = upper_32_bits(CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0); + + for (cp_id = 0 ; cp_id < NUM_OF_CP_PER_QMAN; cp_id++) { + cp_offset = cp_id * 4; + + WREG32(reg_base + QM_CP_MSG_BASE0_ADDR_LO_0_OFFSET + cp_offset, mtr_base_lo); + WREG32(reg_base + QM_CP_MSG_BASE0_ADDR_HI_0_OFFSET + cp_offset, mtr_base_hi); + WREG32(reg_base + QM_CP_MSG_BASE1_ADDR_LO_0_OFFSET + cp_offset, so_base_lo); + WREG32(reg_base + QM_CP_MSG_BASE1_ADDR_HI_0_OFFSET + cp_offset, so_base_hi); + } + + /* allow QMANs to accept work from ARC CQF */ + WREG32(reg_base + QM_CP_CFG_OFFSET, FIELD_PREP(PDMA0_QM_CP_CFG_SWITCH_EN_MASK, 0x1)); +} + +static void gaudi2_init_qman_pqc(struct hl_device *hdev, u32 reg_base, + u32 queue_id_base) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 pq_id, pq_offset, so_base_lo, so_base_hi; + + so_base_lo = lower_32_bits(CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0); + so_base_hi = upper_32_bits(CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0); + + for (pq_id = 0 ; pq_id < NUM_OF_PQ_PER_QMAN ; pq_id++) { + pq_offset = pq_id * 4; + + /* Configure QMAN HBW to scratchpad as it is not needed */ + WREG32(reg_base + QM_PQC_HBW_BASE_LO_0_OFFSET + pq_offset, + lower_32_bits(gaudi2->scratchpad_bus_address)); + WREG32(reg_base + QM_PQC_HBW_BASE_HI_0_OFFSET + pq_offset, + upper_32_bits(gaudi2->scratchpad_bus_address)); + WREG32(reg_base + QM_PQC_SIZE_0_OFFSET + pq_offset, + ilog2(PAGE_SIZE / sizeof(struct hl_cq_entry))); + + WREG32(reg_base + QM_PQC_PI_0_OFFSET + pq_offset, 0); + WREG32(reg_base + QM_PQC_LBW_WDATA_0_OFFSET + pq_offset, QM_PQC_LBW_WDATA); + WREG32(reg_base + QM_PQC_LBW_BASE_LO_0_OFFSET + pq_offset, so_base_lo); + WREG32(reg_base + QM_PQC_LBW_BASE_HI_0_OFFSET + pq_offset, so_base_hi); + } + + /* Enable QMAN H/W completion */ + WREG32(reg_base + QM_PQC_CFG_OFFSET, 1 << PDMA0_QM_PQC_CFG_EN_SHIFT); +} + +static u32 gaudi2_get_dyn_sp_reg(struct hl_device *hdev, u32 queue_id_base) +{ + struct cpu_dyn_regs *dyn_regs = &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs; + u32 sp_reg_addr; + + switch (queue_id_base) { + case GAUDI2_QUEUE_ID_PDMA_0_0...GAUDI2_QUEUE_ID_PDMA_1_3: + fallthrough; + case GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3: + fallthrough; + case GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3: + fallthrough; + case GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3: + fallthrough; + case GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3: + sp_reg_addr = le32_to_cpu(dyn_regs->gic_dma_qm_irq_ctrl); + break; + case GAUDI2_QUEUE_ID_DCORE0_MME_0_0...GAUDI2_QUEUE_ID_DCORE0_MME_0_3: + fallthrough; + case GAUDI2_QUEUE_ID_DCORE1_MME_0_0...GAUDI2_QUEUE_ID_DCORE1_MME_0_3: + fallthrough; + case GAUDI2_QUEUE_ID_DCORE2_MME_0_0...GAUDI2_QUEUE_ID_DCORE2_MME_0_3: + fallthrough; + case GAUDI2_QUEUE_ID_DCORE3_MME_0_0...GAUDI2_QUEUE_ID_DCORE3_MME_0_3: + sp_reg_addr = le32_to_cpu(dyn_regs->gic_mme_qm_irq_ctrl); + break; + case GAUDI2_QUEUE_ID_DCORE0_TPC_0_0 ... GAUDI2_QUEUE_ID_DCORE0_TPC_6_3: + fallthrough; + case GAUDI2_QUEUE_ID_DCORE1_TPC_0_0 ... GAUDI2_QUEUE_ID_DCORE1_TPC_5_3: + fallthrough; + case GAUDI2_QUEUE_ID_DCORE2_TPC_0_0 ... GAUDI2_QUEUE_ID_DCORE2_TPC_5_3: + fallthrough; + case GAUDI2_QUEUE_ID_DCORE3_TPC_0_0 ... GAUDI2_QUEUE_ID_DCORE3_TPC_5_3: + sp_reg_addr = le32_to_cpu(dyn_regs->gic_tpc_qm_irq_ctrl); + break; + case GAUDI2_QUEUE_ID_ROT_0_0...GAUDI2_QUEUE_ID_ROT_1_3: + sp_reg_addr = le32_to_cpu(dyn_regs->gic_rot_qm_irq_ctrl); + break; + case GAUDI2_QUEUE_ID_NIC_0_0...GAUDI2_QUEUE_ID_NIC_23_3: + sp_reg_addr = le32_to_cpu(dyn_regs->gic_nic_qm_irq_ctrl); + break; + default: + dev_err(hdev->dev, "Unexpected h/w queue %d\n", queue_id_base); + return 0; + } + + return sp_reg_addr; +} + +static void gaudi2_init_qman_common(struct hl_device *hdev, u32 reg_base, + u32 queue_id_base) +{ + u32 glbl_prot = QMAN_MAKE_TRUSTED, irq_handler_offset; + int map_table_entry; + + WREG32(reg_base + QM_GLBL_PROT_OFFSET, glbl_prot); + + irq_handler_offset = gaudi2_get_dyn_sp_reg(hdev, queue_id_base); + WREG32(reg_base + QM_GLBL_ERR_ADDR_LO_OFFSET, lower_32_bits(CFG_BASE + irq_handler_offset)); + WREG32(reg_base + QM_GLBL_ERR_ADDR_HI_OFFSET, upper_32_bits(CFG_BASE + irq_handler_offset)); + + map_table_entry = gaudi2_qman_async_event_id[queue_id_base]; + WREG32(reg_base + QM_GLBL_ERR_WDATA_OFFSET, + gaudi2_irq_map_table[map_table_entry].cpu_id); + + WREG32(reg_base + QM_ARB_ERR_MSG_EN_OFFSET, QM_ARB_ERR_MSG_EN_MASK); + + WREG32(reg_base + QM_ARB_SLV_CHOISE_WDT_OFFSET, GAUDI2_ARB_WDT_TIMEOUT); + WREG32(reg_base + QM_GLBL_CFG1_OFFSET, 0); + WREG32(reg_base + QM_GLBL_CFG2_OFFSET, 0); + + /* Enable the QMAN channel. + * PDMA1 QMAN configuration is different, as we do not allow user to + * access CP2/3, it is reserved for the ARC usage. + */ + if (reg_base == gaudi2_qm_blocks_bases[GAUDI2_QUEUE_ID_PDMA_1_0]) + WREG32(reg_base + QM_GLBL_CFG0_OFFSET, PDMA1_QMAN_ENABLE); + else + WREG32(reg_base + QM_GLBL_CFG0_OFFSET, QMAN_ENABLE); +} + +static void gaudi2_init_qman(struct hl_device *hdev, u32 reg_base, + u32 queue_id_base) +{ + u32 pq_id; + + for (pq_id = 0 ; pq_id < NUM_OF_PQ_PER_QMAN ; pq_id++) + hdev->kernel_queues[queue_id_base + pq_id].cq_id = GAUDI2_RESERVED_CQ_CS_COMPLETION; + + gaudi2_init_qman_pq(hdev, reg_base, queue_id_base); + gaudi2_init_qman_cp(hdev, reg_base); + gaudi2_init_qman_pqc(hdev, reg_base, queue_id_base); + gaudi2_init_qman_common(hdev, reg_base, queue_id_base); +} + +static void gaudi2_init_dma_core(struct hl_device *hdev, u32 reg_base, + u32 dma_core_id, bool is_secure) +{ + u32 prot, irq_handler_offset; + struct cpu_dyn_regs *dyn_regs; + int map_table_entry; + + prot = 1 << ARC_FARM_KDMA_PROT_ERR_VAL_SHIFT; + if (is_secure) + prot |= 1 << ARC_FARM_KDMA_PROT_VAL_SHIFT; + + WREG32(reg_base + DMA_CORE_PROT_OFFSET, prot); + + dyn_regs = &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs; + irq_handler_offset = le32_to_cpu(dyn_regs->gic_dma_core_irq_ctrl); + + WREG32(reg_base + DMA_CORE_ERRMSG_ADDR_LO_OFFSET, + lower_32_bits(CFG_BASE + irq_handler_offset)); + + WREG32(reg_base + DMA_CORE_ERRMSG_ADDR_HI_OFFSET, + upper_32_bits(CFG_BASE + irq_handler_offset)); + + map_table_entry = gaudi2_dma_core_async_event_id[dma_core_id]; + WREG32(reg_base + DMA_CORE_ERRMSG_WDATA_OFFSET, + gaudi2_irq_map_table[map_table_entry].cpu_id); + + /* Enable the DMA channel */ + WREG32(reg_base + DMA_CORE_CFG_0_OFFSET, 1 << ARC_FARM_KDMA_CFG_0_EN_SHIFT); +} + +static void gaudi2_init_kdma(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 reg_base; + + if ((gaudi2->hw_cap_initialized & HW_CAP_KDMA) == HW_CAP_KDMA) + return; + + reg_base = gaudi2_dma_core_blocks_bases[DMA_CORE_ID_KDMA]; + + gaudi2_init_dma_core(hdev, reg_base, DMA_CORE_ID_KDMA, true); + + gaudi2->hw_cap_initialized |= HW_CAP_KDMA; +} + +static void gaudi2_init_pdma(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 reg_base; + + if ((gaudi2->hw_cap_initialized & HW_CAP_PDMA_MASK) == HW_CAP_PDMA_MASK) + return; + + reg_base = gaudi2_dma_core_blocks_bases[DMA_CORE_ID_PDMA0]; + gaudi2_init_dma_core(hdev, reg_base, DMA_CORE_ID_PDMA0, false); + + reg_base = gaudi2_qm_blocks_bases[GAUDI2_QUEUE_ID_PDMA_0_0]; + gaudi2_init_qman(hdev, reg_base, GAUDI2_QUEUE_ID_PDMA_0_0); + + reg_base = gaudi2_dma_core_blocks_bases[DMA_CORE_ID_PDMA1]; + gaudi2_init_dma_core(hdev, reg_base, DMA_CORE_ID_PDMA1, false); + + reg_base = gaudi2_qm_blocks_bases[GAUDI2_QUEUE_ID_PDMA_1_0]; + gaudi2_init_qman(hdev, reg_base, GAUDI2_QUEUE_ID_PDMA_1_0); + + gaudi2->hw_cap_initialized |= HW_CAP_PDMA_MASK; +} + +static void gaudi2_init_edma_instance(struct hl_device *hdev, u8 seq) +{ + u32 reg_base, base_edma_core_id, base_edma_qman_id; + + base_edma_core_id = DMA_CORE_ID_EDMA0 + seq; + base_edma_qman_id = edma_stream_base[seq]; + + reg_base = gaudi2_dma_core_blocks_bases[base_edma_core_id]; + gaudi2_init_dma_core(hdev, reg_base, base_edma_core_id, false); + + reg_base = gaudi2_qm_blocks_bases[base_edma_qman_id]; + gaudi2_init_qman(hdev, reg_base, base_edma_qman_id); +} + +static void gaudi2_init_edma(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct gaudi2_device *gaudi2 = hdev->asic_specific; + int dcore, inst; + + if ((gaudi2->hw_cap_initialized & HW_CAP_EDMA_MASK) == HW_CAP_EDMA_MASK) + return; + + for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) { + for (inst = 0 ; inst < NUM_OF_EDMA_PER_DCORE ; inst++) { + u8 seq = dcore * NUM_OF_EDMA_PER_DCORE + inst; + + if (!(prop->edma_enabled_mask & BIT(seq))) + continue; + + gaudi2_init_edma_instance(hdev, seq); + + gaudi2->hw_cap_initialized |= BIT_ULL(HW_CAP_EDMA_SHIFT + seq); + } + } +} + +/* + * gaudi2_arm_monitors_for_virt_msix_db() - Arm monitors for writing to the virtual MSI-X doorbell. + * @hdev: pointer to habanalabs device structure. + * @sob_id: sync object ID. + * @first_mon_id: ID of first monitor out of 3 consecutive monitors. + * @interrupt_id: interrupt ID. + * + * Some initiators cannot have HBW address in their completion address registers, and thus cannot + * write directly to the HBW host memory of the virtual MSI-X doorbell. + * Instead, they are configured to LBW write to a sync object, and a monitor will do the HBW write. + * + * The mechanism in the sync manager block is composed of a master monitor with 3 messages. + * In addition to the HBW write, the other 2 messages are for preparing the monitor to next + * completion, by decrementing the sync object value and re-arming the monitor. + */ +static void gaudi2_arm_monitors_for_virt_msix_db(struct hl_device *hdev, u32 sob_id, + u32 first_mon_id, u32 interrupt_id) +{ + u32 sob_offset, first_mon_offset, mon_offset, payload, sob_group, mode, arm, config; + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u64 addr; + u8 mask; + + /* Reset the SOB value */ + sob_offset = sob_id * sizeof(u32); + WREG32(mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + sob_offset, 0); + + /* Configure 3 monitors: + * 1. Write interrupt ID to the virtual MSI-X doorbell (master monitor) + * 2. Decrement SOB value by 1. + * 3. Re-arm the master monitor. + */ + + first_mon_offset = first_mon_id * sizeof(u32); + + /* 2nd monitor: Decrement SOB value by 1 */ + mon_offset = first_mon_offset + sizeof(u32); + + addr = CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + sob_offset; + WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 + mon_offset, lower_32_bits(addr)); + WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 + mon_offset, upper_32_bits(addr)); + + payload = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_MASK, 0x7FFF) | /* "-1" */ + FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_SIGN_MASK, 1) | + FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_MASK, 1); + WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_0 + mon_offset, payload); + + /* 3rd monitor: Re-arm the master monitor */ + mon_offset = first_mon_offset + 2 * sizeof(u32); + + addr = CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_0 + first_mon_offset; + WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 + mon_offset, lower_32_bits(addr)); + WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 + mon_offset, upper_32_bits(addr)); + + sob_group = sob_id / 8; + mask = ~BIT(sob_id & 0x7); + mode = 0; /* comparison mode is "greater than or equal to" */ + arm = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_ARM_SID_MASK, sob_group) | + FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_ARM_MASK_MASK, mask) | + FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_ARM_SOP_MASK, mode) | + FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_ARM_SOD_MASK, 1); + + payload = arm; + WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_0 + mon_offset, payload); + + /* 1st monitor (master): Write interrupt ID to the virtual MSI-X doorbell */ + mon_offset = first_mon_offset; + + config = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_WR_NUM_MASK, 2); /* "2": 3 writes */ + WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_0 + mon_offset, config); + + addr = gaudi2->virt_msix_db_dma_addr; + WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 + mon_offset, lower_32_bits(addr)); + WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 + mon_offset, upper_32_bits(addr)); + + payload = interrupt_id; + WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_0 + mon_offset, payload); + + WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_0 + mon_offset, arm); +} + +static void gaudi2_prepare_sm_for_virt_msix_db(struct hl_device *hdev) +{ + u32 decoder_id, sob_id, first_mon_id, interrupt_id; + struct asic_fixed_properties *prop = &hdev->asic_prop; + + /* Decoder normal/abnormal interrupts */ + for (decoder_id = 0 ; decoder_id < NUMBER_OF_DEC ; ++decoder_id) { + if (!(prop->decoder_enabled_mask & BIT(decoder_id))) + continue; + + sob_id = GAUDI2_RESERVED_SOB_DEC_NRM_FIRST + decoder_id; + first_mon_id = GAUDI2_RESERVED_MON_DEC_NRM_FIRST + 3 * decoder_id; + interrupt_id = GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM + 2 * decoder_id; + gaudi2_arm_monitors_for_virt_msix_db(hdev, sob_id, first_mon_id, interrupt_id); + + sob_id = GAUDI2_RESERVED_SOB_DEC_ABNRM_FIRST + decoder_id; + first_mon_id = GAUDI2_RESERVED_MON_DEC_ABNRM_FIRST + 3 * decoder_id; + interrupt_id += 1; + gaudi2_arm_monitors_for_virt_msix_db(hdev, sob_id, first_mon_id, interrupt_id); + } +} + +static void gaudi2_init_sm(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u64 cq_address; + u32 reg_val; + int i; + + /* Enable HBW/LBW CQ for completion monitors */ + reg_val = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_CQ_EN_MASK, 1); + reg_val |= FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_LBW_EN_MASK, 1); + + for (i = 0 ; i < GAUDI2_MAX_PENDING_CS ; i++) + WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_0 + (4 * i), reg_val); + + /* Enable only HBW CQ for KDMA completion monitor */ + reg_val = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_CQ_EN_MASK, 1); + WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_0 + (4 * i), reg_val); + + /* Init CQ0 DB */ + /* Configure the monitor to trigger MSI-X interrupt */ + /* TODO: + * Remove the if statement when virtual MSI-X doorbell is supported in simulator (SW-93022) + * and in F/W (SW-93024). + */ + if (!hdev->pdev || hdev->asic_prop.fw_security_enabled) { + u64 msix_db_reg = CFG_BASE + mmPCIE_DBI_MSIX_DOORBELL_OFF; + + WREG32(mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_0, lower_32_bits(msix_db_reg)); + WREG32(mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0, upper_32_bits(msix_db_reg)); + } else { + WREG32(mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_0, + lower_32_bits(gaudi2->virt_msix_db_dma_addr)); + WREG32(mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0, + upper_32_bits(gaudi2->virt_msix_db_dma_addr)); + } + WREG32(mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_0, GAUDI2_IRQ_NUM_COMPLETION); + + for (i = 0 ; i < GAUDI2_RESERVED_CQ_NUMBER ; i++) { + cq_address = + hdev->completion_queue[i].bus_address; + + WREG32(mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0 + (4 * i), + lower_32_bits(cq_address)); + WREG32(mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0 + (4 * i), + upper_32_bits(cq_address)); + WREG32(mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0 + (4 * i), + ilog2(HL_CQ_SIZE_IN_BYTES)); + } + + /* Configure kernel ASID and MMU BP*/ + WREG32(mmDCORE0_SYNC_MNGR_GLBL_ASID_SEC, 0x10000); + WREG32(mmDCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV, 0); + + /* Initialize sync objects and monitors which are used for the virtual MSI-X doorbell */ + gaudi2_prepare_sm_for_virt_msix_db(hdev); +} + +static void gaudi2_init_mme_acc(struct hl_device *hdev, u32 reg_base) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 reg_val; + int i; + + reg_val = FIELD_PREP(MME_ACC_INTR_MASK_WBC_ERR_RESP_MASK, 0); + reg_val |= FIELD_PREP(MME_ACC_INTR_MASK_AP_SRC_POS_INF_MASK, 1); + reg_val |= FIELD_PREP(MME_ACC_INTR_MASK_AP_SRC_NEG_INF_MASK, 1); + reg_val |= FIELD_PREP(MME_ACC_INTR_MASK_AP_SRC_NAN_MASK, 1); + reg_val |= FIELD_PREP(MME_ACC_INTR_MASK_AP_RESULT_POS_INF_MASK, 1); + reg_val |= FIELD_PREP(MME_ACC_INTR_MASK_AP_RESULT_NEG_INF_MASK, 1); + + WREG32(reg_base + MME_ACC_INTR_MASK_OFFSET, reg_val); + WREG32(reg_base + MME_ACC_AP_LFSR_POLY_OFFSET, 0x80DEADAF); + + for (i = 0 ; i < MME_NUM_OF_LFSR_SEEDS ; i++) { + WREG32(reg_base + MME_ACC_AP_LFSR_SEED_SEL_OFFSET, i); + WREG32(reg_base + MME_ACC_AP_LFSR_SEED_WDATA_OFFSET, gaudi2->lfsr_rand_seeds[i]); + } +} + +static void gaudi2_init_dcore_mme(struct hl_device *hdev, int dcore_id, + bool config_qman_only) +{ + u32 queue_id_base, reg_base, clk_en_addr = 0; + + switch (dcore_id) { + case 0: + queue_id_base = GAUDI2_QUEUE_ID_DCORE0_MME_0_0; + break; + case 1: + queue_id_base = GAUDI2_QUEUE_ID_DCORE1_MME_0_0; + clk_en_addr = mmDCORE1_MME_CTRL_LO_QM_SLV_CLK_EN; + break; + case 2: + queue_id_base = GAUDI2_QUEUE_ID_DCORE2_MME_0_0; + break; + case 3: + queue_id_base = GAUDI2_QUEUE_ID_DCORE3_MME_0_0; + clk_en_addr = mmDCORE3_MME_CTRL_LO_QM_SLV_CLK_EN; + break; + default: + dev_err(hdev->dev, "Invalid dcore id %u\n", dcore_id); + return; + } + + if (clk_en_addr && !(hdev->fw_components & FW_TYPE_BOOT_CPU)) + WREG32(clk_en_addr, 0x1); + + if (!config_qman_only) { + reg_base = gaudi2_mme_acc_blocks_bases[dcore_id]; + gaudi2_init_mme_acc(hdev, reg_base); + } + + reg_base = gaudi2_qm_blocks_bases[queue_id_base]; + gaudi2_init_qman(hdev, reg_base, queue_id_base); +} + +static void gaudi2_init_mme(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + int i; + + if ((gaudi2->hw_cap_initialized & HW_CAP_MME_MASK) == HW_CAP_MME_MASK) + return; + + for (i = 0 ; i < NUM_OF_DCORES ; i++) { + gaudi2_init_dcore_mme(hdev, i, false); + + gaudi2->hw_cap_initialized |= BIT_ULL(HW_CAP_MME_SHIFT + i); + } +} + +static void gaudi2_init_tpc_cfg(struct hl_device *hdev, u32 reg_base) +{ + /* Mask arithmetic and QM interrupts in TPC */ + WREG32(reg_base + TPC_CFG_TPC_INTR_MASK_OFFSET, 0x23FFFE); + + /* Set 16 cache lines */ + WREG32(reg_base + TPC_CFG_MSS_CONFIG_OFFSET, + 2 << DCORE0_TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_SHIFT); +} + +struct gaudi2_tpc_init_cfg_data { + enum gaudi2_queue_id dcore_tpc_qid_base[NUM_OF_DCORES]; +}; + +static void gaudi2_init_tpc_config(struct hl_device *hdev, int dcore, int inst, + u32 offset, void *data) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + struct gaudi2_tpc_init_cfg_data *cfg_data = data; + u32 queue_id_base; + u8 seq; + + queue_id_base = cfg_data->dcore_tpc_qid_base[dcore] + (inst * NUM_OF_PQ_PER_QMAN); + + if (dcore == 0 && inst == (NUM_DCORE0_TPC - 1)) + /* gets last sequence number */ + seq = NUM_OF_DCORES * NUM_OF_TPC_PER_DCORE; + else + seq = dcore * NUM_OF_TPC_PER_DCORE + inst; + + gaudi2_init_tpc_cfg(hdev, mmDCORE0_TPC0_CFG_BASE + offset); + gaudi2_init_qman(hdev, mmDCORE0_TPC0_QM_BASE + offset, queue_id_base); + + gaudi2->tpc_hw_cap_initialized |= BIT_ULL(HW_CAP_TPC_SHIFT + seq); +} + +static void gaudi2_init_tpc(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + struct gaudi2_tpc_init_cfg_data init_cfg_data; + struct iterate_module_ctx tpc_iter; + + if (!hdev->asic_prop.tpc_enabled_mask) + return; + + if ((gaudi2->tpc_hw_cap_initialized & HW_CAP_TPC_MASK) == HW_CAP_TPC_MASK) + return; + + init_cfg_data.dcore_tpc_qid_base[0] = GAUDI2_QUEUE_ID_DCORE0_TPC_0_0; + init_cfg_data.dcore_tpc_qid_base[1] = GAUDI2_QUEUE_ID_DCORE1_TPC_0_0; + init_cfg_data.dcore_tpc_qid_base[2] = GAUDI2_QUEUE_ID_DCORE2_TPC_0_0; + init_cfg_data.dcore_tpc_qid_base[3] = GAUDI2_QUEUE_ID_DCORE3_TPC_0_0; + tpc_iter.fn = &gaudi2_init_tpc_config; + tpc_iter.data = &init_cfg_data; + gaudi2_iterate_tpcs(hdev, &tpc_iter); +} + +static void gaudi2_init_rotator(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 i, reg_base, queue_id; + + queue_id = GAUDI2_QUEUE_ID_ROT_0_0; + + for (i = 0 ; i < NUM_OF_ROT ; i++, queue_id += NUM_OF_PQ_PER_QMAN) { + reg_base = gaudi2_qm_blocks_bases[queue_id]; + gaudi2_init_qman(hdev, reg_base, queue_id); + + gaudi2->hw_cap_initialized |= BIT_ULL(HW_CAP_ROT_SHIFT + i); + } +} + +static void gaudi2_init_vdec_brdg_ctrl(struct hl_device *hdev, u64 base_addr, u32 decoder_id) +{ + u32 sob_id; + + /* TODO: + * Remove when virtual MSI-X doorbell is supported in simulator (SW-93022) and in F/W + * (SW-93024). + */ + if (!hdev->pdev || hdev->asic_prop.fw_security_enabled) { + u32 interrupt_id = GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM + 2 * decoder_id; + + WREG32(base_addr + BRDG_CTRL_NRM_MSIX_LBW_AWADDR, mmPCIE_DBI_MSIX_DOORBELL_OFF); + WREG32(base_addr + BRDG_CTRL_NRM_MSIX_LBW_WDATA, interrupt_id); + WREG32(base_addr + BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR, mmPCIE_DBI_MSIX_DOORBELL_OFF); + WREG32(base_addr + BRDG_CTRL_ABNRM_MSIX_LBW_WDATA, interrupt_id + 1); + return; + } + + /* VCMD normal interrupt */ + sob_id = GAUDI2_RESERVED_SOB_DEC_NRM_FIRST + decoder_id; + WREG32(base_addr + BRDG_CTRL_NRM_MSIX_LBW_AWADDR, + mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + sob_id * sizeof(u32)); + WREG32(base_addr + BRDG_CTRL_NRM_MSIX_LBW_WDATA, GAUDI2_SOB_INCREMENT_BY_ONE); + + /* VCMD abnormal interrupt */ + sob_id = GAUDI2_RESERVED_SOB_DEC_ABNRM_FIRST + decoder_id; + WREG32(base_addr + BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR, + mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + sob_id * sizeof(u32)); + WREG32(base_addr + BRDG_CTRL_ABNRM_MSIX_LBW_WDATA, GAUDI2_SOB_INCREMENT_BY_ONE); +} + +static void gaudi2_init_dec(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 dcore_id, dec_id, dec_bit; + u64 base_addr; + + if (!hdev->asic_prop.decoder_enabled_mask) + return; + + if ((gaudi2->dec_hw_cap_initialized & HW_CAP_DEC_MASK) == HW_CAP_DEC_MASK) + return; + + for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++) + for (dec_id = 0 ; dec_id < NUM_OF_DEC_PER_DCORE ; dec_id++) { + dec_bit = dcore_id * NUM_OF_DEC_PER_DCORE + dec_id; + + if (!(hdev->asic_prop.decoder_enabled_mask & BIT(dec_bit))) + continue; + + base_addr = mmDCORE0_DEC0_CMD_BASE + + BRDG_CTRL_BLOCK_OFFSET + + dcore_id * DCORE_OFFSET + + dec_id * DCORE_VDEC_OFFSET; + + gaudi2_init_vdec_brdg_ctrl(hdev, base_addr, dec_bit); + + gaudi2->dec_hw_cap_initialized |= BIT_ULL(HW_CAP_DEC_SHIFT + dec_bit); + } + + for (dec_id = 0 ; dec_id < NUM_OF_PCIE_VDEC ; dec_id++) { + dec_bit = PCIE_DEC_SHIFT + dec_id; + if (!(hdev->asic_prop.decoder_enabled_mask & BIT(dec_bit))) + continue; + + base_addr = mmPCIE_DEC0_CMD_BASE + BRDG_CTRL_BLOCK_OFFSET + + dec_id * DCORE_VDEC_OFFSET; + + gaudi2_init_vdec_brdg_ctrl(hdev, base_addr, dec_bit); + + gaudi2->dec_hw_cap_initialized |= BIT_ULL(HW_CAP_DEC_SHIFT + dec_bit); + } +} + +static void gaudi2_init_msix_gw_table(struct hl_device *hdev) +{ + u32 first_reg_offset, last_reg_offset, msix_gw_table_base; + u8 first_bit, last_bit; + int i; + + msix_gw_table_base = mmPCIE_WRAP_MSIX_GW_TABLE_0; + first_reg_offset = (GAUDI2_IRQ_NUM_USER_FIRST >> 5) << 2; + first_bit = GAUDI2_IRQ_NUM_USER_FIRST % 32; + last_reg_offset = (GAUDI2_IRQ_NUM_USER_LAST >> 5) << 2; + last_bit = GAUDI2_IRQ_NUM_USER_LAST % 32; + + if (first_reg_offset == last_reg_offset) { + WREG32(msix_gw_table_base + first_reg_offset, GENMASK(last_bit, first_bit)); + return; + } + + WREG32(msix_gw_table_base + first_reg_offset, GENMASK(31, first_bit)); + WREG32(msix_gw_table_base + last_reg_offset, GENMASK(last_bit, 0)); + + for (i = first_reg_offset + 4; i < last_reg_offset ; i += 4) + WREG32(msix_gw_table_base + i, 0xFFFFFFFF); +} + +static int gaudi2_mmu_update_asid_hop0_addr(struct hl_device *hdev, + u32 stlb_base, u32 asid, u64 phys_addr) +{ + u32 status, timeout_usec; + int rc; + + if (hdev->pldm || !hdev->pdev) + timeout_usec = GAUDI2_PLDM_MMU_TIMEOUT_USEC; + else + timeout_usec = MMU_CONFIG_TIMEOUT_USEC; + + WREG32(stlb_base + STLB_ASID_OFFSET, asid); + WREG32(stlb_base + STLB_HOP0_PA43_12_OFFSET, phys_addr >> MMU_HOP0_PA43_12_SHIFT); + WREG32(stlb_base + STLB_HOP0_PA63_44_OFFSET, phys_addr >> MMU_HOP0_PA63_44_SHIFT); + WREG32(stlb_base + STLB_BUSY_OFFSET, 0x80000000); + + rc = hl_poll_timeout( + hdev, + stlb_base + STLB_BUSY_OFFSET, + status, + !(status & 0x80000000), + 1000, + timeout_usec); + + if (rc) { + dev_err(hdev->dev, "Timeout during MMU hop0 config of asid %d\n", asid); + return rc; + } + + return 0; +} + +static void gaudi2_mmu_send_invalidate_cache_cmd(struct hl_device *hdev, u32 stlb_base, + u32 start_offset, u32 inv_start_val, + u32 flags) +{ + /* clear PMMU mem line cache (only needed in mmu range invalidation) */ + if (flags & MMU_OP_CLEAR_MEMCACHE) + WREG32(mmPMMU_HBW_STLB_MEM_CACHE_INVALIDATION, 0x1); + + if (flags & MMU_OP_SKIP_LOW_CACHE_INV) + return; + + WREG32(stlb_base + start_offset, inv_start_val); +} + +static int gaudi2_mmu_invalidate_cache_status_poll(struct hl_device *hdev, u32 stlb_base, + struct gaudi2_cache_invld_params *inv_params) +{ + u32 status, timeout_usec, start_offset; + int rc; + + timeout_usec = (hdev->pldm) ? GAUDI2_PLDM_MMU_TIMEOUT_USEC : + GAUDI2_MMU_CACHE_INV_TIMEOUT_USEC; + + /* poll PMMU mem line cache (only needed in mmu range invalidation) */ + if (inv_params->flags & MMU_OP_CLEAR_MEMCACHE) { + rc = hl_poll_timeout( + hdev, + mmPMMU_HBW_STLB_MEM_CACHE_INV_STATUS, + status, + status & 0x1, + 1000, + timeout_usec); + + if (rc) + return rc; + + /* Need to manually reset the status to 0 */ + WREG32(mmPMMU_HBW_STLB_MEM_CACHE_INV_STATUS, 0x0); + } + + /* Lower cache does not work with cache lines, hence we can skip its + * invalidation upon map and invalidate only upon unmap + */ + if (inv_params->flags & MMU_OP_SKIP_LOW_CACHE_INV) + return 0; + + start_offset = inv_params->range_invalidation ? + STLB_RANGE_CACHE_INVALIDATION_OFFSET : STLB_INV_ALL_START_OFFSET; + + rc = hl_poll_timeout( + hdev, + stlb_base + start_offset, + status, + !(status & 0x1), + 1000, + timeout_usec); + + return rc; +} + +bool gaudi2_is_hmmu_enabled(struct hl_device *hdev, int dcore_id, int hmmu_id) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 hw_cap; + + hw_cap = HW_CAP_DCORE0_DMMU0 << (NUM_OF_HMMU_PER_DCORE * dcore_id + hmmu_id); + + if (gaudi2->hw_cap_initialized & hw_cap) + return true; + + return false; +} + +/* this function shall be called only for HMMUs for which capability bit is set */ +static inline u32 get_hmmu_stlb_base(int dcore_id, int hmmu_id) +{ + u32 offset; + + offset = (u32) (dcore_id * DCORE_OFFSET + hmmu_id * DCORE_HMMU_OFFSET); + return (u32)(mmDCORE0_HMMU0_STLB_BASE + offset); +} + +static void gaudi2_mmu_invalidate_cache_trigger(struct hl_device *hdev, u32 stlb_base, + struct gaudi2_cache_invld_params *inv_params) +{ + u32 start_offset; + + if (inv_params->range_invalidation) { + /* Set the addresses range + * Note: that the start address we set in register, is not included in + * the range of the invalidation, by design. + * that's why we need to set lower address than the one we actually + * want to be included in the range invalidation. + */ + u64 start = inv_params->start_va - 1; + + start_offset = STLB_RANGE_CACHE_INVALIDATION_OFFSET; + + WREG32(stlb_base + STLB_RANGE_INV_START_LSB_OFFSET, + start >> MMU_RANGE_INV_VA_LSB_SHIFT); + + WREG32(stlb_base + STLB_RANGE_INV_START_MSB_OFFSET, + start >> MMU_RANGE_INV_VA_MSB_SHIFT); + + WREG32(stlb_base + STLB_RANGE_INV_END_LSB_OFFSET, + inv_params->end_va >> MMU_RANGE_INV_VA_LSB_SHIFT); + + WREG32(stlb_base + STLB_RANGE_INV_END_MSB_OFFSET, + inv_params->end_va >> MMU_RANGE_INV_VA_MSB_SHIFT); + } else { + start_offset = STLB_INV_ALL_START_OFFSET; + } + + gaudi2_mmu_send_invalidate_cache_cmd(hdev, stlb_base, start_offset, + inv_params->inv_start_val, inv_params->flags); +} + +static inline void gaudi2_hmmu_invalidate_cache_trigger(struct hl_device *hdev, + int dcore_id, int hmmu_id, + struct gaudi2_cache_invld_params *inv_params) +{ + u32 stlb_base = get_hmmu_stlb_base(dcore_id, hmmu_id); + + gaudi2_mmu_invalidate_cache_trigger(hdev, stlb_base, inv_params); +} + +static inline int gaudi2_hmmu_invalidate_cache_status_poll(struct hl_device *hdev, + int dcore_id, int hmmu_id, + struct gaudi2_cache_invld_params *inv_params) +{ + u32 stlb_base = get_hmmu_stlb_base(dcore_id, hmmu_id); + + return gaudi2_mmu_invalidate_cache_status_poll(hdev, stlb_base, inv_params); +} + +static int gaudi2_hmmus_invalidate_cache(struct hl_device *hdev, + struct gaudi2_cache_invld_params *inv_params) +{ + int dcore_id, hmmu_id; + + /* first send all invalidation commands */ + for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++) { + for (hmmu_id = 0 ; hmmu_id < NUM_OF_HMMU_PER_DCORE ; hmmu_id++) { + if (!gaudi2_is_hmmu_enabled(hdev, dcore_id, hmmu_id)) + continue; + + gaudi2_hmmu_invalidate_cache_trigger(hdev, dcore_id, hmmu_id, inv_params); + } + } + + /* next, poll all invalidations status */ + for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++) { + for (hmmu_id = 0 ; hmmu_id < NUM_OF_HMMU_PER_DCORE ; hmmu_id++) { + int rc; + + if (!gaudi2_is_hmmu_enabled(hdev, dcore_id, hmmu_id)) + continue; + + rc = gaudi2_hmmu_invalidate_cache_status_poll(hdev, dcore_id, hmmu_id, + inv_params); + if (rc) + return rc; + } + } + + return 0; +} + +static int gaudi2_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard, u32 flags) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + struct gaudi2_cache_invld_params invld_params; + int rc = 0; + + if (hdev->reset_info.hard_reset_pending) + return rc; + + invld_params.range_invalidation = false; + invld_params.inv_start_val = 1; + + if ((flags & MMU_OP_USERPTR) && (gaudi2->hw_cap_initialized & HW_CAP_PMMU)) { + invld_params.flags = flags; + gaudi2_mmu_invalidate_cache_trigger(hdev, mmPMMU_HBW_STLB_BASE, &invld_params); + rc = gaudi2_mmu_invalidate_cache_status_poll(hdev, mmPMMU_HBW_STLB_BASE, + &invld_params); + } else if (flags & MMU_OP_PHYS_PACK) { + invld_params.flags = 0; + rc = gaudi2_hmmus_invalidate_cache(hdev, &invld_params); + } + + return rc; +} + +static int gaudi2_mmu_invalidate_cache_range(struct hl_device *hdev, bool is_hard, + u32 flags, u32 asid, u64 va, u64 size) +{ + struct gaudi2_cache_invld_params invld_params = {0}; + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u64 start_va, end_va; + u32 inv_start_val; + int rc = 0; + + if (hdev->reset_info.hard_reset_pending) + return 0; + + inv_start_val = (1 << MMU_RANGE_INV_EN_SHIFT | + 1 << MMU_RANGE_INV_ASID_EN_SHIFT | + asid << MMU_RANGE_INV_ASID_SHIFT); + start_va = va; + end_va = start_va + size; + + if ((flags & MMU_OP_USERPTR) && (gaudi2->hw_cap_initialized & HW_CAP_PMMU)) { + /* As range invalidation does not support zero address we will + * do full invalidation in this case + */ + if (start_va) { + invld_params.range_invalidation = true; + invld_params.start_va = start_va; + invld_params.end_va = end_va; + invld_params.inv_start_val = inv_start_val; + invld_params.flags = flags | MMU_OP_CLEAR_MEMCACHE; + } else { + invld_params.range_invalidation = false; + invld_params.inv_start_val = 1; + invld_params.flags = flags; + } + + + gaudi2_mmu_invalidate_cache_trigger(hdev, mmPMMU_HBW_STLB_BASE, &invld_params); + rc = gaudi2_mmu_invalidate_cache_status_poll(hdev, mmPMMU_HBW_STLB_BASE, + &invld_params); + if (rc) + return rc; + + } else if (flags & MMU_OP_PHYS_PACK) { + invld_params.start_va = gaudi2_mmu_scramble_addr(hdev, start_va); + invld_params.end_va = gaudi2_mmu_scramble_addr(hdev, end_va); + invld_params.inv_start_val = inv_start_val; + invld_params.flags = flags; + rc = gaudi2_hmmus_invalidate_cache(hdev, &invld_params); + } + + return rc; +} + +static int gaudi2_mmu_update_hop0_addr(struct hl_device *hdev, u32 stlb_base) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + u64 hop0_addr; + u32 asid, max_asid = prop->max_asid; + int rc; + + /* it takes too much time to init all of the ASIDs on palladium */ + if (hdev->pldm) + max_asid = min((u32) 8, max_asid); + + for (asid = 0 ; asid < max_asid ; asid++) { + hop0_addr = hdev->mmu_priv.hr.mmu_asid_hop0[asid].phys_addr; + rc = gaudi2_mmu_update_asid_hop0_addr(hdev, stlb_base, asid, hop0_addr); + if (rc) { + dev_err(hdev->dev, "failed to set hop0 addr for asid %d\n", asid); + return rc; + } + } + + return 0; +} + +static int gaudi2_mmu_init_common(struct hl_device *hdev, u32 mmu_base, + u32 stlb_base) +{ + u32 status, timeout_usec; + int rc; + + if (hdev->pldm || !hdev->pdev) + timeout_usec = GAUDI2_PLDM_MMU_TIMEOUT_USEC; + else + timeout_usec = GAUDI2_MMU_CACHE_INV_TIMEOUT_USEC; + + WREG32(stlb_base + STLB_INV_ALL_START_OFFSET, 1); + + rc = hl_poll_timeout( + hdev, + stlb_base + STLB_SRAM_INIT_OFFSET, + status, + !status, + 1000, + timeout_usec); + + if (rc) + dev_notice_ratelimited(hdev->dev, "Timeout when waiting for MMU SRAM init\n"); + + rc = gaudi2_mmu_update_hop0_addr(hdev, stlb_base); + if (rc) + return rc; + + WREG32(mmu_base + MMU_BYPASS_OFFSET, 0); + WREG32(mmu_base + MMU_SPI_SEI_MASK_OFFSET, 0xF); + + rc = hl_poll_timeout( + hdev, + stlb_base + STLB_INV_ALL_START_OFFSET, + status, + !status, + 1000, + timeout_usec); + + if (rc) + dev_notice_ratelimited(hdev->dev, "Timeout when waiting for MMU invalidate all\n"); + + WREG32(mmu_base + MMU_ENABLE_OFFSET, 1); + + return rc; +} + +static int gaudi2_pci_mmu_init(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 mmu_base, stlb_base; + int rc; + + if (gaudi2->hw_cap_initialized & HW_CAP_PMMU) + return 0; + + mmu_base = mmPMMU_HBW_MMU_BASE; + stlb_base = mmPMMU_HBW_STLB_BASE; + + RMWREG32(stlb_base + STLB_HOP_CONFIGURATION_OFFSET, + (0 << PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_HOP_SHIFT) | + (5 << PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_SHIFT) | + (4 << PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_SHIFT) | + (5 << PMMU_HBW_STLB_HOP_CONFIGURATION_LAST_HOP_SHIFT) | + (5 << PMMU_HBW_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_SHIFT), + PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_HOP_MASK | + PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_MASK | + PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_MASK | + PMMU_HBW_STLB_HOP_CONFIGURATION_LAST_HOP_MASK | + PMMU_HBW_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_MASK); + + WREG32(stlb_base + STLB_LL_LOOKUP_MASK_63_32_OFFSET, 0); + + if (PAGE_SIZE == SZ_64K) { + /* Set page sizes to 64K on hop5 and 16M on hop4 + enable 8 bit hops */ + RMWREG32(mmu_base + MMU_STATIC_MULTI_PAGE_SIZE_OFFSET, + FIELD_PREP(DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP5_PAGE_SIZE_MASK, 4) | + FIELD_PREP(DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP4_PAGE_SIZE_MASK, 3) | + FIELD_PREP( + DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_CFG_8_BITS_HOP_MODE_EN_MASK, + 1), + DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP5_PAGE_SIZE_MASK | + DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP4_PAGE_SIZE_MASK | + DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_CFG_8_BITS_HOP_MODE_EN_MASK); + } + + rc = gaudi2_mmu_init_common(hdev, mmu_base, stlb_base); + if (rc) + return rc; + + gaudi2->hw_cap_initialized |= HW_CAP_PMMU; + + return 0; +} + +static int gaudi2_dcore_hmmu_init(struct hl_device *hdev, int dcore_id, + int hmmu_id) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 offset, mmu_base, stlb_base, hw_cap; + u8 dmmu_seq; + int rc; + + dmmu_seq = NUM_OF_HMMU_PER_DCORE * dcore_id + hmmu_id; + hw_cap = HW_CAP_DCORE0_DMMU0 << dmmu_seq; + + /* + * return if DMMU is already initialized or if it's not out of + * isolation (due to cluster binning) + */ + if ((gaudi2->hw_cap_initialized & hw_cap) || !(prop->hmmu_hif_enabled_mask & BIT(dmmu_seq))) + return 0; + + offset = (u32) (dcore_id * DCORE_OFFSET + hmmu_id * DCORE_HMMU_OFFSET); + mmu_base = mmDCORE0_HMMU0_MMU_BASE + offset; + stlb_base = mmDCORE0_HMMU0_STLB_BASE + offset; + + RMWREG32(mmu_base + MMU_STATIC_MULTI_PAGE_SIZE_OFFSET, 5 /* 64MB */, + MMU_STATIC_MULTI_PAGE_SIZE_HOP4_PAGE_SIZE_MASK); + + RMWREG32(stlb_base + STLB_HOP_CONFIGURATION_OFFSET, + FIELD_PREP(DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_HOP_MASK, 0) | + FIELD_PREP(DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_MASK, 3) | + FIELD_PREP(DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_MASK, 3) | + FIELD_PREP(DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LAST_HOP_MASK, 3) | + FIELD_PREP(DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_MASK, 3), + DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_HOP_MASK | + DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_MASK | + DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_MASK | + DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LAST_HOP_MASK | + DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_MASK); + + RMWREG32(stlb_base + STLB_HOP_CONFIGURATION_OFFSET, 1, + STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_MASK); + + rc = gaudi2_mmu_init_common(hdev, mmu_base, stlb_base); + if (rc) + return rc; + + gaudi2->hw_cap_initialized |= hw_cap; + + return 0; +} + +static int gaudi2_hbm_mmu_init(struct hl_device *hdev) +{ + int rc, dcore_id, hmmu_id; + + for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++) + for (hmmu_id = 0 ; hmmu_id < NUM_OF_HMMU_PER_DCORE; hmmu_id++) { + rc = gaudi2_dcore_hmmu_init(hdev, dcore_id, hmmu_id); + if (rc) + return rc; + } + + return 0; +} + +static int gaudi2_mmu_init(struct hl_device *hdev) +{ + int rc; + + rc = gaudi2_pci_mmu_init(hdev); + if (rc) + return rc; + + rc = gaudi2_hbm_mmu_init(hdev); + if (rc) + return rc; + + return 0; +} + +static int gaudi2_hw_init(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + int rc; + + /* Let's mark in the H/W that we have reached this point. We check + * this value in the reset_before_init function to understand whether + * we need to reset the chip before doing H/W init. This register is + * cleared by the H/W upon H/W reset + */ + WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY); + + /* Perform read from the device to make sure device is up */ + RREG32(mmHW_STATE); + + /* If iATU is done by FW, the HBM bar ALWAYS points to DRAM_PHYS_BASE. + * So we set it here and if anyone tries to move it later to + * a different address, there will be an error + */ + if (hdev->asic_prop.iatu_done_by_fw) + gaudi2->dram_bar_cur_addr = DRAM_PHYS_BASE; + + /* + * Before pushing u-boot/linux to device, need to set the hbm bar to + * base address of dram + */ + if (gaudi2_set_hbm_bar_base(hdev, DRAM_PHYS_BASE) == U64_MAX) { + dev_err(hdev->dev, "failed to map HBM bar to DRAM base address\n"); + return -EIO; + } + + rc = gaudi2_init_cpu(hdev); + if (rc) { + dev_err(hdev->dev, "failed to initialize CPU\n"); + return rc; + } + + gaudi2_init_msix_gw_table(hdev); + + gaudi2_init_scrambler_hbm(hdev); + gaudi2_init_kdma(hdev); + + rc = gaudi2_init_cpu_queues(hdev, GAUDI2_CPU_TIMEOUT_USEC); + if (rc) { + dev_err(hdev->dev, "failed to initialize CPU H/W queues %d\n", rc); + return rc; + } + + rc = gaudi2->cpucp_info_get(hdev); + if (rc) { + dev_err(hdev->dev, "Failed to get cpucp info\n"); + return rc; + } + + rc = gaudi2_mmu_init(hdev); + if (rc) + return rc; + + gaudi2_init_pdma(hdev); + gaudi2_init_edma(hdev); + gaudi2_init_sm(hdev); + gaudi2_init_tpc(hdev); + gaudi2_init_mme(hdev); + gaudi2_init_rotator(hdev); + gaudi2_init_dec(hdev); + gaudi2_enable_timestamp(hdev); + + rc = gaudi2_coresight_init(hdev); + if (rc) + goto disable_queues; + + rc = gaudi2_enable_msix(hdev); + if (rc) + goto disable_queues; + + /* Perform read from the device to flush all configuration */ + RREG32(mmHW_STATE); + + return 0; + +disable_queues: + gaudi2_disable_dma_qmans(hdev); + gaudi2_disable_mme_qmans(hdev); + gaudi2_disable_tpc_qmans(hdev); + gaudi2_disable_rot_qmans(hdev); + gaudi2_disable_nic_qmans(hdev); + + gaudi2_disable_timestamp(hdev); + + return rc; +} + +/** + * gaudi2_send_hard_reset_cmd - common function to handle reset + * + * @hdev: pointer to the habanalabs device structure + * + * This function handles the various possible scenarios for reset. + * It considers if reset is handled by driver\FW and what FW components are loaded + */ +static void gaudi2_send_hard_reset_cmd(struct hl_device *hdev) +{ + struct cpu_dyn_regs *dyn_regs = &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs; + bool heartbeat_reset, preboot_only, cpu_initialized = false; + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 cpu_boot_status; + + preboot_only = (hdev->fw_loader.fw_comp_loaded == FW_TYPE_PREBOOT_CPU); + heartbeat_reset = (hdev->reset_info.curr_reset_cause == HL_RESET_CAUSE_HEARTBEAT); + + /* + * Handle corner case where failure was at cpu management app load, + * and driver didn't detect any failure while loading the FW, + * then at such scenario driver will send only HALT_MACHINE + * and no one will respond to this request since FW already back to preboot + * and it cannot handle such cmd. + * In this case next time the management app loads it'll check on events register + * which will still have the halt indication, and will reboot the device. + * The solution is to let preboot clear all relevant registers before next boot + * once driver send COMMS_RST_DEV. + */ + cpu_boot_status = RREG32(mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS); + + if (gaudi2 && (gaudi2->hw_cap_initialized & HW_CAP_CPU) && + (cpu_boot_status == CPU_BOOT_STATUS_SRAM_AVAIL)) + cpu_initialized = true; + + /* + * when Linux/Bootfit exist this write to the SP can be interpreted in 2 ways: + * 1. FW reset: FW initiate the reset sequence + * 2. driver reset: FW will start HALT sequence (the preparations for the + * reset but not the reset itself as it is not implemented + * on their part) and LKD will wait to let FW complete the + * sequence before issuing the reset + */ + if (!preboot_only && cpu_initialized) { + WREG32(le32_to_cpu(dyn_regs->gic_host_halt_irq), + gaudi2_irq_map_table[GAUDI2_EVENT_CPU_HALT_MACHINE].cpu_id); + + msleep(GAUDI2_CPU_RESET_WAIT_MSEC); + } + + /* + * When working with preboot (without Linux/Boot fit) we can + * communicate only using the COMMS commands to issue halt/reset. + * + * For the case in which we are working with Linux/Bootfit this is a hail-mary + * attempt to revive the card in the small chance that the f/w has + * experienced a watchdog event, which caused it to return back to preboot. + * In that case, triggering reset through GIC won't help. We need to + * trigger the reset as if Linux wasn't loaded. + * + * We do it only if the reset cause was HB, because that would be the + * indication of such an event. + * + * In case watchdog hasn't expired but we still got HB, then this won't + * do any damage. + */ + + if (heartbeat_reset || preboot_only || !cpu_initialized) { + if (hdev->asic_prop.hard_reset_done_by_fw) + hl_fw_ask_hard_reset_without_linux(hdev); + else + hl_fw_ask_halt_machine_without_linux(hdev); + } +} + +/** + * gaudi2_execute_hard_reset - execute hard reset by driver/FW + * + * @hdev: pointer to the habanalabs device structure + * @reset_sleep_ms: sleep time in msec after reset + * + * This function executes hard reset based on if driver/FW should do the reset + */ +static void gaudi2_execute_hard_reset(struct hl_device *hdev, u32 reset_sleep_ms) +{ + if (hdev->asic_prop.hard_reset_done_by_fw) { + gaudi2_send_hard_reset_cmd(hdev); + return; + } + + /* Set device to handle FLR by H/W as we will put the device + * CPU to halt mode + */ + WREG32(mmPCIE_AUX_FLR_CTRL, + (PCIE_AUX_FLR_CTRL_HW_CTRL_MASK | PCIE_AUX_FLR_CTRL_INT_MASK_MASK)); + + gaudi2_send_hard_reset_cmd(hdev); + + WREG32(mmPSOC_RESET_CONF_SW_ALL_RST, 1); +} + +/** + * gaudi2_execute_soft_reset - execute soft reset by driver/FW + * + * @hdev: pointer to the habanalabs device structure + * @reset_sleep_ms: sleep time in msec after reset + * @driver_performs_reset: true if driver should perform reset instead of f/w. + * + * This function executes soft reset based on if driver/FW should do the reset + */ +static void gaudi2_execute_soft_reset(struct hl_device *hdev, u32 reset_sleep_ms, + bool driver_performs_reset) +{ + struct cpu_dyn_regs *dyn_regs = &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs; + + if (!driver_performs_reset) { + /* set SP to indicate reset request sent to FW */ + WREG32(mmCPU_RST_STATUS_TO_HOST, CPU_RST_STATUS_NA); + + WREG32(le32_to_cpu(dyn_regs->gic_host_soft_rst_irq), + gaudi2_irq_map_table[GAUDI2_EVENT_CPU_SOFT_RESET].cpu_id); + return; + } + + /* Block access to engines, QMANs and SM during reset, these + * RRs will be reconfigured after soft reset. + * PCIE_MSIX is left unsecured to allow NIC packets processing during the reset. + */ + gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_LONG, NUM_LONG_LBW_RR - 1, + mmDCORE0_TPC0_QM_DCCM_BASE, mmPCIE_MSIX_BASE); + + gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_LONG, NUM_LONG_LBW_RR - 2, + mmPCIE_MSIX_BASE + HL_BLOCK_SIZE, + mmPCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE + HL_BLOCK_SIZE); + + WREG32(mmPSOC_RESET_CONF_SOFT_RST, 1); +} + +static void gaudi2_poll_btm_indication(struct hl_device *hdev, u32 reset_sleep_ms, + u32 poll_timeout_us) +{ + int i, rc = 0; + u32 reg_val; + + /* without this sleep reset will not work */ + msleep(reset_sleep_ms); + + /* We poll the BTM done indication multiple times after reset due to + * a HW errata 'GAUDI2_0300' + */ + for (i = 0 ; i < GAUDI2_RESET_POLL_CNT ; i++) + rc = hl_poll_timeout( + hdev, + mmPSOC_GLOBAL_CONF_BTM_FSM, + reg_val, + reg_val == 0, + 1000, + poll_timeout_us); + + if (rc) + dev_err(hdev->dev, "Timeout while waiting for device to reset 0x%x\n", reg_val); +} + +static void gaudi2_get_soft_rst_done_indication(struct hl_device *hdev, u32 poll_timeout_us) +{ + int i, rc = 0; + u32 reg_val; + + for (i = 0 ; i < GAUDI2_RESET_POLL_CNT ; i++) + rc = hl_poll_timeout( + hdev, + mmCPU_RST_STATUS_TO_HOST, + reg_val, + reg_val == CPU_RST_STATUS_SOFT_RST_DONE, + 1000, + poll_timeout_us); + + if (rc) + dev_err(hdev->dev, "Timeout while waiting for FW to complete soft reset (0x%x)\n", + reg_val); +} + +static void gaudi2_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 poll_timeout_us, reset_sleep_ms; + bool driver_performs_reset = false; + + if (hdev->pldm) { + reset_sleep_ms = hard_reset ? GAUDI2_PLDM_HRESET_TIMEOUT_MSEC : + GAUDI2_PLDM_SRESET_TIMEOUT_MSEC; + poll_timeout_us = GAUDI2_PLDM_RESET_POLL_TIMEOUT_USEC; + } else { + reset_sleep_ms = GAUDI2_RESET_TIMEOUT_MSEC; + poll_timeout_us = GAUDI2_RESET_POLL_TIMEOUT_USEC; + } + + if (fw_reset) + goto skip_reset; + + gaudi2_reset_arcs(hdev); + + if (hard_reset) { + driver_performs_reset = !hdev->asic_prop.hard_reset_done_by_fw; + gaudi2_execute_hard_reset(hdev, reset_sleep_ms); + } else { + /* + * As we have to support also work with preboot only (which does not supports + * soft reset) we have to make sure that security is disabled before letting driver + * do the reset. user shall control the BFE flags to avoid asking soft reset in + * secured device with preboot only. + */ + driver_performs_reset = (hdev->fw_components == FW_TYPE_PREBOOT_CPU && + !hdev->asic_prop.fw_security_enabled); + gaudi2_execute_soft_reset(hdev, reset_sleep_ms, driver_performs_reset); + } + +skip_reset: + if (driver_performs_reset || hard_reset) + gaudi2_poll_btm_indication(hdev, reset_sleep_ms, poll_timeout_us); + else + gaudi2_get_soft_rst_done_indication(hdev, poll_timeout_us); + + if (!gaudi2) + return; + + gaudi2->dec_hw_cap_initialized &= ~(HW_CAP_DEC_MASK); + gaudi2->tpc_hw_cap_initialized &= ~(HW_CAP_TPC_MASK); + + /* + * Clear NIC capability mask in order for driver to re-configure + * NIC QMANs. NIC ports will not be re-configured during soft + * reset as we call gaudi2_nic_init only during hard reset + */ + gaudi2->nic_hw_cap_initialized &= ~(HW_CAP_NIC_MASK); + + if (hard_reset) { + gaudi2->hw_cap_initialized &= + ~(HW_CAP_DRAM | HW_CAP_CLK_GATE | HW_CAP_HBM_SCRAMBLER_MASK | + HW_CAP_PMMU | HW_CAP_CPU | HW_CAP_CPU_Q | + HW_CAP_SRAM_SCRAMBLER | HW_CAP_DMMU_MASK | + HW_CAP_PDMA_MASK | HW_CAP_EDMA_MASK | HW_CAP_KDMA | + HW_CAP_MME_MASK | HW_CAP_ROT_MASK); + + memset(gaudi2->events_stat, 0, sizeof(gaudi2->events_stat)); + } else { + gaudi2->hw_cap_initialized &= + ~(HW_CAP_CLK_GATE | HW_CAP_HBM_SCRAMBLER_SW_RESET | + HW_CAP_PDMA_MASK | HW_CAP_EDMA_MASK | HW_CAP_MME_MASK | + HW_CAP_ROT_MASK); + } +} + +static int gaudi2_suspend(struct hl_device *hdev) +{ + int rc; + + rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS, 0x0); + if (rc) + dev_err(hdev->dev, "Failed to disable PCI access from CPU\n"); + + return rc; +} + +static int gaudi2_resume(struct hl_device *hdev) +{ + return gaudi2_init_iatu(hdev); +} + +static int gaudi2_mmap(struct hl_device *hdev, struct vm_area_struct *vma, + void *cpu_addr, dma_addr_t dma_addr, size_t size) +{ + int rc; + + vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP | + VM_DONTCOPY | VM_NORESERVE; + +#ifdef _HAS_DMA_MMAP_COHERENT + + rc = dma_mmap_coherent(hdev->dev, vma, cpu_addr, dma_addr, size); + if (rc) + dev_err(hdev->dev, "dma_mmap_coherent error %d", rc); + +#else + + rc = remap_pfn_range(vma, vma->vm_start, + virt_to_phys(cpu_addr) >> PAGE_SHIFT, + size, vma->vm_page_prot); + if (rc) + dev_err(hdev->dev, "remap_pfn_range error %d", rc); + +#endif + + return rc; +} + +static bool gaudi2_is_queue_enabled(struct hl_device *hdev, u32 hw_queue_id) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u64 hw_cap_mask = 0; + u64 hw_tpc_cap_bit = 0; + u64 hw_nic_cap_bit = 0; + u64 hw_test_cap_bit = 0; + + switch (hw_queue_id) { + case GAUDI2_QUEUE_ID_PDMA_0_0 ... GAUDI2_QUEUE_ID_PDMA_1_1: + hw_cap_mask = HW_CAP_PDMA_MASK; + break; + + case GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3: + hw_test_cap_bit = HW_CAP_EDMA_SHIFT + + ((hw_queue_id - GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0) >> 2); + break; + case GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3: + hw_test_cap_bit = HW_CAP_EDMA_SHIFT + NUM_OF_EDMA_PER_DCORE + + ((hw_queue_id - GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0) >> 2); + break; + case GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3: + hw_test_cap_bit = HW_CAP_EDMA_SHIFT + 2 * NUM_OF_EDMA_PER_DCORE + + ((hw_queue_id - GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0) >> 2); + break; + case GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3: + hw_test_cap_bit = HW_CAP_EDMA_SHIFT + 3 * NUM_OF_EDMA_PER_DCORE + + ((hw_queue_id - GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0) >> 2); + break; + + case GAUDI2_QUEUE_ID_DCORE0_MME_0_0 ... GAUDI2_QUEUE_ID_DCORE0_MME_0_3: + hw_test_cap_bit = HW_CAP_MME_SHIFT; + break; + + case GAUDI2_QUEUE_ID_DCORE1_MME_0_0 ... GAUDI2_QUEUE_ID_DCORE1_MME_0_3: + hw_test_cap_bit = HW_CAP_MME_SHIFT + 1; + break; + + case GAUDI2_QUEUE_ID_DCORE2_MME_0_0 ... GAUDI2_QUEUE_ID_DCORE2_MME_0_3: + hw_test_cap_bit = HW_CAP_MME_SHIFT + 2; + break; + + case GAUDI2_QUEUE_ID_DCORE3_MME_0_0 ... GAUDI2_QUEUE_ID_DCORE3_MME_0_3: + hw_test_cap_bit = HW_CAP_MME_SHIFT + 3; + break; + + case GAUDI2_QUEUE_ID_DCORE0_TPC_0_0 ... GAUDI2_QUEUE_ID_DCORE0_TPC_5_3: + hw_tpc_cap_bit = HW_CAP_TPC_SHIFT + + ((hw_queue_id - GAUDI2_QUEUE_ID_DCORE0_TPC_0_0) >> 2); + + /* special case where cap bit refers to the first queue id */ + if (!hw_tpc_cap_bit) + return !!(gaudi2->tpc_hw_cap_initialized & BIT_ULL(0)); + break; + + case GAUDI2_QUEUE_ID_DCORE1_TPC_0_0 ... GAUDI2_QUEUE_ID_DCORE1_TPC_5_3: + hw_tpc_cap_bit = HW_CAP_TPC_SHIFT + NUM_OF_TPC_PER_DCORE + + ((hw_queue_id - GAUDI2_QUEUE_ID_DCORE1_TPC_0_0) >> 2); + break; + + case GAUDI2_QUEUE_ID_DCORE2_TPC_0_0 ... GAUDI2_QUEUE_ID_DCORE2_TPC_5_3: + hw_tpc_cap_bit = HW_CAP_TPC_SHIFT + (2 * NUM_OF_TPC_PER_DCORE) + + ((hw_queue_id - GAUDI2_QUEUE_ID_DCORE2_TPC_0_0) >> 2); + break; + + case GAUDI2_QUEUE_ID_DCORE3_TPC_0_0 ... GAUDI2_QUEUE_ID_DCORE3_TPC_5_3: + hw_tpc_cap_bit = HW_CAP_TPC_SHIFT + (3 * NUM_OF_TPC_PER_DCORE) + + ((hw_queue_id - GAUDI2_QUEUE_ID_DCORE3_TPC_0_0) >> 2); + break; + + case GAUDI2_QUEUE_ID_DCORE0_TPC_6_0 ... GAUDI2_QUEUE_ID_DCORE0_TPC_6_3: + hw_tpc_cap_bit = HW_CAP_TPC_SHIFT + (4 * NUM_OF_TPC_PER_DCORE); + break; + + case GAUDI2_QUEUE_ID_ROT_0_0 ... GAUDI2_QUEUE_ID_ROT_1_3: + hw_test_cap_bit = HW_CAP_ROT_SHIFT + ((hw_queue_id - GAUDI2_QUEUE_ID_ROT_0_0) >> 2); + break; + + case GAUDI2_QUEUE_ID_NIC_0_0 ... GAUDI2_QUEUE_ID_NIC_23_3: + hw_nic_cap_bit = HW_CAP_NIC_SHIFT + ((hw_queue_id - GAUDI2_QUEUE_ID_NIC_0_0) >> 2); + + /* special case where cap bit refers to the first queue id */ + if (!hw_nic_cap_bit) + return !!(gaudi2->nic_hw_cap_initialized & BIT_ULL(0)); + break; + + case GAUDI2_QUEUE_ID_CPU_PQ: + return !!(gaudi2->hw_cap_initialized & HW_CAP_CPU_Q); + + default: + return false; + } + + if (hw_tpc_cap_bit) + return !!(gaudi2->tpc_hw_cap_initialized & BIT_ULL(hw_tpc_cap_bit)); + + if (hw_nic_cap_bit) + return !!(gaudi2->nic_hw_cap_initialized & BIT_ULL(hw_nic_cap_bit)); + + if (hw_test_cap_bit) + hw_cap_mask = BIT_ULL(hw_test_cap_bit); + + return !!(gaudi2->hw_cap_initialized & hw_cap_mask); +} + +static bool gaudi2_is_arc_enabled(struct hl_device *hdev, u64 arc_id) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + + switch (arc_id) { + case CPU_ID_SCHED_ARC0 ... CPU_ID_SCHED_ARC5: + case CPU_ID_MME_QMAN_ARC0...CPU_ID_ROT_QMAN_ARC1: + return !!(gaudi2->active_hw_arc & BIT_ULL(arc_id)); + + case CPU_ID_TPC_QMAN_ARC0...CPU_ID_TPC_QMAN_ARC24: + return !!(gaudi2->active_tpc_arc & BIT_ULL(arc_id - CPU_ID_TPC_QMAN_ARC0)); + + case CPU_ID_NIC_QMAN_ARC0...CPU_ID_NIC_QMAN_ARC23: + return !!(gaudi2->active_nic_arc & BIT_ULL(arc_id - CPU_ID_NIC_QMAN_ARC0)); + + default: + return false; + } +} + +static void gaudi2_clr_arc_id_cap(struct hl_device *hdev, u64 arc_id) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + + switch (arc_id) { + case CPU_ID_SCHED_ARC0 ... CPU_ID_SCHED_ARC5: + case CPU_ID_MME_QMAN_ARC0...CPU_ID_ROT_QMAN_ARC1: + gaudi2->active_hw_arc &= ~(BIT_ULL(arc_id)); + break; + + case CPU_ID_TPC_QMAN_ARC0...CPU_ID_TPC_QMAN_ARC24: + gaudi2->active_tpc_arc &= ~(BIT_ULL(arc_id - CPU_ID_TPC_QMAN_ARC0)); + break; + + case CPU_ID_NIC_QMAN_ARC0...CPU_ID_NIC_QMAN_ARC23: + gaudi2->active_nic_arc &= ~(BIT_ULL(arc_id - CPU_ID_NIC_QMAN_ARC0)); + break; + + default: + return; + } +} + +static void gaudi2_set_arc_id_cap(struct hl_device *hdev, u64 arc_id) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + + switch (arc_id) { + case CPU_ID_SCHED_ARC0 ... CPU_ID_SCHED_ARC5: + case CPU_ID_MME_QMAN_ARC0...CPU_ID_ROT_QMAN_ARC1: + gaudi2->active_hw_arc |= BIT_ULL(arc_id); + break; + + case CPU_ID_TPC_QMAN_ARC0...CPU_ID_TPC_QMAN_ARC24: + gaudi2->active_tpc_arc |= BIT_ULL(arc_id - CPU_ID_TPC_QMAN_ARC0); + break; + + case CPU_ID_NIC_QMAN_ARC0...CPU_ID_NIC_QMAN_ARC23: + gaudi2->active_nic_arc |= BIT_ULL(arc_id - CPU_ID_NIC_QMAN_ARC0); + break; + + default: + return; + } +} + +static void gaudi2_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi) +{ + struct cpu_dyn_regs *dyn_regs = &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs; + u32 pq_offset, reg_base, db_reg_offset, db_value; + + if (hw_queue_id != GAUDI2_QUEUE_ID_CPU_PQ) { + /* + * QMAN has 4 successive PQ_PI registers, 1 for each of the QMAN PQs. + * Masking the H/W queue ID with 0x3 extracts the QMAN internal PQ + * number. + */ + pq_offset = (hw_queue_id & 0x3) * 4; + reg_base = gaudi2_qm_blocks_bases[hw_queue_id]; + db_reg_offset = reg_base + QM_PQ_PI_0_OFFSET + pq_offset; + } else { + db_reg_offset = mmCPU_IF_PF_PQ_PI; + } + + db_value = pi; + + /* ring the doorbell */ + WREG32(db_reg_offset, db_value); + + if (hw_queue_id == GAUDI2_QUEUE_ID_CPU_PQ) { + /* make sure device CPU will read latest data from host */ + mb(); + WREG32(le32_to_cpu(dyn_regs->gic_host_pi_upd_irq), + gaudi2_irq_map_table[GAUDI2_EVENT_CPU_PI_UPDATE].cpu_id); + } +} + +static void gaudi2_pqe_write(struct hl_device *hdev, __le64 *pqe, struct hl_bd *bd) +{ + __le64 *pbd = (__le64 *) bd; + + /* The QMANs are on the host memory so a simple copy suffice */ + pqe[0] = pbd[0]; + pqe[1] = pbd[1]; +} + +static void *gaudi2_dma_alloc_coherent(struct hl_device *hdev, size_t size, + dma_addr_t *dma_handle, gfp_t flags) +{ + return dma_alloc_coherent(&hdev->pdev->dev, size, dma_handle, flags); +} + +static void gaudi2_dma_free_coherent(struct hl_device *hdev, size_t size, + void *cpu_addr, dma_addr_t dma_handle) +{ + dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, dma_handle); +} + +static int gaudi2_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len, + u32 timeout, u64 *result) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + + if (!(gaudi2->hw_cap_initialized & HW_CAP_CPU_Q)) { + if (result) + *result = 0; + return 0; + } + + if (!timeout) + timeout = GAUDI2_MSG_TO_CPU_TIMEOUT_USEC; + + return hl_fw_send_cpu_message(hdev, GAUDI2_QUEUE_ID_CPU_PQ, msg, len, timeout, result); +} + +static void *gaudi2_dma_pool_zalloc(struct hl_device *hdev, size_t size, + gfp_t mem_flags, dma_addr_t *dma_handle) +{ + if (size > GAUDI2_DMA_POOL_BLK_SIZE) + return NULL; + + return dma_pool_zalloc(hdev->dma_pool, mem_flags, dma_handle); +} + +static void gaudi2_dma_pool_free(struct hl_device *hdev, void *vaddr, dma_addr_t dma_addr) +{ + dma_pool_free(hdev->dma_pool, vaddr, dma_addr); +} + +static void *gaudi2_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size, + dma_addr_t *dma_handle) +{ + return hl_fw_cpu_accessible_dma_pool_alloc(hdev, size, dma_handle); +} + +static void gaudi2_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size, void *vaddr) +{ + hl_fw_cpu_accessible_dma_pool_free(hdev, size, vaddr); +} + +static dma_addr_t gaudi2_dma_map_single(struct hl_device *hdev, void *addr, int len, + enum dma_data_direction dir) +{ + dma_addr_t dma_addr; + + dma_addr = dma_map_single(&hdev->pdev->dev, addr, len, dir); + if (unlikely(dma_mapping_error(&hdev->pdev->dev, dma_addr))) + return 0; + + return dma_addr; +} + +static void gaudi2_dma_unmap_single(struct hl_device *hdev, dma_addr_t addr, int len, + enum dma_data_direction dir) +{ + dma_unmap_single(&hdev->pdev->dev, addr, len, dir); +} + +static int gaudi2_validate_cb_address(struct hl_device *hdev, struct hl_cs_parser *parser) +{ + struct asic_fixed_properties *asic_prop = &hdev->asic_prop; + struct gaudi2_device *gaudi2 = hdev->asic_specific; + + if (!gaudi2_is_queue_enabled(hdev, parser->hw_queue_id)) { + dev_err(hdev->dev, "h/w queue %d is disabled\n", parser->hw_queue_id); + return -EINVAL; + } + + /* Just check if CB address is valid */ + + if (hl_mem_area_inside_range((u64) (uintptr_t) parser->user_cb, + parser->user_cb_size, + asic_prop->sram_user_base_address, + asic_prop->sram_end_address)) + return 0; + + if (hl_mem_area_inside_range((u64) (uintptr_t) parser->user_cb, + parser->user_cb_size, + asic_prop->dram_user_base_address, + asic_prop->dram_end_address)) + return 0; + + if ((gaudi2->hw_cap_initialized & HW_CAP_DMMU_MASK) && + hl_mem_area_inside_range((u64) (uintptr_t) parser->user_cb, + parser->user_cb_size, + asic_prop->dmmu.start_addr, + asic_prop->dmmu.end_addr)) + return 0; + + if (gaudi2->hw_cap_initialized & HW_CAP_PMMU) { + if (hl_mem_area_inside_range((u64) (uintptr_t) parser->user_cb, + parser->user_cb_size, + asic_prop->pmmu.start_addr, + asic_prop->pmmu.end_addr) || + hl_mem_area_inside_range( + (u64) (uintptr_t) parser->user_cb, + parser->user_cb_size, + asic_prop->pmmu_huge.start_addr, + asic_prop->pmmu_huge.end_addr)) + return 0; + + } else if (gaudi2_host_phys_addr_valid((u64) (uintptr_t) parser->user_cb)) { + if (!hdev->pdev) + return 0; + + if (!device_iommu_mapped(&hdev->pdev->dev)) + return 0; + } + + dev_err(hdev->dev, "CB address %p + 0x%x for internal QMAN is not valid\n", + parser->user_cb, parser->user_cb_size); + + return -EFAULT; +} + +static int gaudi2_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + + if (!parser->is_kernel_allocated_cb) + return gaudi2_validate_cb_address(hdev, parser); + + if (!(gaudi2->hw_cap_initialized & HW_CAP_PMMU)) { + dev_err(hdev->dev, "PMMU not initialized - Unsupported mode in Gaudi2\n"); + return -EINVAL; + } + + return 0; +} + +static int gaudi2_send_heartbeat(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + + if (!(gaudi2->hw_cap_initialized & HW_CAP_CPU_Q)) + return 0; + + return hl_fw_send_heartbeat(hdev); +} + +/* This is an internal helper function, used to update the KDMA mmu props. + * Should be called with a proper kdma lock. + */ +static void gaudi2_kdma_set_mmbp_asid(struct hl_device *hdev, + bool mmu_bypass, u32 asid) +{ + u32 rw_asid, rw_mmu_bp; + + rw_asid = (asid << ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_SHIFT) | + (asid << ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_SHIFT); + + rw_mmu_bp = (!!mmu_bypass << ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_RD_SHIFT) | + (!!mmu_bypass << ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_WR_SHIFT); + + WREG32(mmARC_FARM_KDMA_CTX_AXUSER_HB_ASID, rw_asid); + WREG32(mmARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP, rw_mmu_bp); +} + +static void gaudi2_arm_cq_monitor(struct hl_device *hdev, u32 sob_id, u32 mon_id, u32 cq_id, + u32 mon_payload, u32 sync_value) +{ + u32 sob_offset, mon_offset, sync_group_id, mode, mon_arm; + u8 mask; + + sob_offset = sob_id * 4; + mon_offset = mon_id * 4; + + /* Reset the SOB value */ + WREG32(mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + sob_offset, 0); + + /* Configure this address with CQ_ID 0 because CQ_EN is set */ + WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 + mon_offset, cq_id); + + /* Configure this address with CS index because CQ_EN is set */ + WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_0 + mon_offset, mon_payload); + + sync_group_id = sob_id / 8; + mask = ~(1 << (sob_id & 0x7)); + mode = 1; /* comparison mode is "equal to" */ + + mon_arm = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_ARM_SOD_MASK, sync_value); + mon_arm |= FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_ARM_SOP_MASK, mode); + mon_arm |= FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_ARM_MASK_MASK, mask); + mon_arm |= FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_ARM_SID_MASK, sync_group_id); + WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_0 + mon_offset, mon_arm); +} + +/* This is an internal helper function used by gaudi2_send_job_to_kdma only */ +static int gaudi2_send_job_to_kdma(struct hl_device *hdev, + u64 src_addr, u64 dst_addr, + u32 size, bool is_memset) +{ + u32 comp_val, commit_mask, *polling_addr, timeout, status = 0; + struct hl_cq_entry *cq_base; + struct hl_cq *cq; + u64 comp_addr; + int rc; + + gaudi2_arm_cq_monitor(hdev, GAUDI2_RESERVED_SOB_KDMA_COMPLETION, + GAUDI2_RESERVED_MON_KDMA_COMPLETION, + GAUDI2_RESERVED_CQ_KDMA_COMPLETION, 1, 1); + + comp_addr = CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + + (GAUDI2_RESERVED_SOB_KDMA_COMPLETION * sizeof(u32)); + + comp_val = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_MASK, 1) | + FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_MASK, 1); + + WREG32(mmARC_FARM_KDMA_CTX_SRC_BASE_LO, lower_32_bits(src_addr)); + WREG32(mmARC_FARM_KDMA_CTX_SRC_BASE_HI, upper_32_bits(src_addr)); + WREG32(mmARC_FARM_KDMA_CTX_DST_BASE_LO, lower_32_bits(dst_addr)); + WREG32(mmARC_FARM_KDMA_CTX_DST_BASE_HI, upper_32_bits(dst_addr)); + WREG32(mmARC_FARM_KDMA_CTX_WR_COMP_ADDR_LO, lower_32_bits(comp_addr)); + WREG32(mmARC_FARM_KDMA_CTX_WR_COMP_ADDR_HI, upper_32_bits(comp_addr)); + WREG32(mmARC_FARM_KDMA_CTX_WR_COMP_WDATA, comp_val); + WREG32(mmARC_FARM_KDMA_CTX_DST_TSIZE_0, size); + + commit_mask = FIELD_PREP(ARC_FARM_KDMA_CTX_COMMIT_LIN_MASK, 1) | + FIELD_PREP(ARC_FARM_KDMA_CTX_COMMIT_WR_COMP_EN_MASK, 1); + + if (is_memset) + commit_mask |= FIELD_PREP(ARC_FARM_KDMA_CTX_COMMIT_MEM_SET_MASK, 1); + + WREG32(mmARC_FARM_KDMA_CTX_COMMIT, commit_mask); + + /* Wait for completion */ + cq = &hdev->completion_queue[GAUDI2_RESERVED_CQ_KDMA_COMPLETION]; + cq_base = cq->kernel_address; + polling_addr = (u32 *)&cq_base[cq->ci]; + + if (hdev->pldm) + /* for each 1MB 20 second of timeout */ + timeout = ((size / SZ_1M) + 1) * USEC_PER_SEC * 20; + else + timeout = KDMA_TIMEOUT_USEC; + + /* Polling */ + rc = hl_poll_timeout_memory( + hdev, + polling_addr, + status, + (status == 1), + 1000, + timeout, + true); + + *polling_addr = 0; + + if (rc) { + dev_err(hdev->dev, "Timeout while waiting for KDMA to be idle\n"); + WREG32(mmARC_FARM_KDMA_CFG_1, 1 << ARC_FARM_KDMA_CFG_1_HALT_SHIFT); + return rc; + } + + cq->ci = hl_cq_inc_ptr(cq->ci); + + return 0; +} + +static void gaudi2_memset_device_lbw(struct hl_device *hdev, u32 addr, u32 size, u32 val) +{ + u32 i; + + for (i = 0 ; i < size ; i += sizeof(u32)) + WREG32(addr + i, val); +} + +static void gaudi2_qman_set_test_mode(struct hl_device *hdev, u32 hw_queue_id, bool enable) +{ + u32 reg_base = gaudi2_qm_blocks_bases[hw_queue_id]; + + if (enable) { + WREG32(reg_base + QM_GLBL_PROT_OFFSET, QMAN_MAKE_TRUSTED_TEST_MODE); + WREG32(reg_base + QM_PQC_CFG_OFFSET, 0); + } else { + WREG32(reg_base + QM_GLBL_PROT_OFFSET, QMAN_MAKE_TRUSTED); + WREG32(reg_base + QM_PQC_CFG_OFFSET, 1 << PDMA0_QM_PQC_CFG_EN_SHIFT); + } +} + +static int gaudi2_test_queue(struct hl_device *hdev, u32 hw_queue_id) +{ + u32 sob_offset = hdev->asic_prop.first_available_user_sob[0] * 4; + u32 sob_addr = mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + sob_offset; + u32 timeout_usec, tmp, sob_base = 1, sob_val = 0x5a5a; + struct packet_msg_short *msg_short_pkt; + dma_addr_t pkt_dma_addr; + size_t pkt_size; + int rc; + + if (hdev->pldm) + timeout_usec = GAUDI2_PLDM_TEST_QUEUE_WAIT_USEC; + else + timeout_usec = GAUDI2_TEST_QUEUE_WAIT_USEC; + + pkt_size = sizeof(*msg_short_pkt); + msg_short_pkt = hl_asic_dma_pool_zalloc(hdev, pkt_size, GFP_KERNEL, &pkt_dma_addr); + if (!msg_short_pkt) { + dev_err(hdev->dev, "Failed to allocate packet for H/W queue %d testing\n", + hw_queue_id); + return -ENOMEM; + } + + tmp = (PACKET_MSG_SHORT << GAUDI2_PKT_CTL_OPCODE_SHIFT) | + (1 << GAUDI2_PKT_CTL_EB_SHIFT) | + (1 << GAUDI2_PKT_CTL_MB_SHIFT) | + (sob_base << GAUDI2_PKT_SHORT_CTL_BASE_SHIFT) | + (sob_offset << GAUDI2_PKT_SHORT_CTL_ADDR_SHIFT); + + msg_short_pkt->value = cpu_to_le32(sob_val); + msg_short_pkt->ctl = cpu_to_le32(tmp); + + /* Reset the SOB value */ + WREG32(sob_addr, 0); + + rc = hl_hw_queue_send_cb_no_cmpl(hdev, hw_queue_id, pkt_size, pkt_dma_addr); + if (rc) { + dev_err(hdev->dev, "Failed to send msg_short packet to H/W queue %d\n", + hw_queue_id); + goto free_pkt; + } + + rc = hl_poll_timeout( + hdev, + sob_addr, + tmp, + (tmp == sob_val), + 1000, + timeout_usec); + + if (rc == -ETIMEDOUT) { + dev_err(hdev->dev, "H/W queue %d test failed (SOB_OBJ_0 == 0x%x)\n", + hw_queue_id, tmp); + rc = -EIO; + } + + /* Reset the SOB value */ + WREG32(sob_addr, 0); + +free_pkt: + hl_asic_dma_pool_free(hdev, (void *) msg_short_pkt, pkt_dma_addr); + return rc; +} + +static int gaudi2_test_cpu_queue(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + + /* + * check capability here as send_cpu_message() won't update the result + * value if no capability + */ + if (!(gaudi2->hw_cap_initialized & HW_CAP_CPU_Q)) + return 0; + + return hl_fw_test_cpu_queue(hdev); +} + +static int gaudi2_test_queues(struct hl_device *hdev) +{ + int i, rc, ret_val = 0; + + for (i = GAUDI2_QUEUE_ID_PDMA_0_0 ; i < GAUDI2_QUEUE_ID_CPU_PQ; i++) { + if (!gaudi2_is_queue_enabled(hdev, i)) + continue; + + gaudi2_qman_set_test_mode(hdev, i, true); + rc = gaudi2_test_queue(hdev, i); + gaudi2_qman_set_test_mode(hdev, i, false); + + if (rc) { + ret_val = -EINVAL; + goto done; + } + } + + rc = gaudi2_test_cpu_queue(hdev); + if (rc) { + ret_val = -EINVAL; + goto done; + } + +done: + return ret_val; +} + +static int gaudi2_non_hard_reset_late_init(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + size_t irq_arr_size; + + /* TODO: missing gaudi2_nic_resume. + * Until implemented nic_hw_cap_initialized will remain zeroed + */ + gaudi2_init_arcs(hdev); + gaudi2_scrub_arcs_dccm(hdev); + gaudi2_init_security(hdev); + + /* Unmask all IRQs since some could have been received during the soft reset */ + irq_arr_size = gaudi2->num_of_valid_hw_events * sizeof(gaudi2->hw_events[0]); + return hl_fw_unmask_irq_arr(hdev, gaudi2->hw_events, irq_arr_size); +} + +static void gaudi2_is_tpc_engine_idle(struct hl_device *hdev, int dcore, int inst, u32 offset, + void *data) +{ + struct gaudi2_tpc_idle_data *idle_data = (struct gaudi2_tpc_idle_data *)data; + u32 tpc_cfg_sts, qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts; + bool is_eng_idle; + int engine_idx; + + if ((dcore == 0) && (inst == (NUM_DCORE0_TPC - 1))) + engine_idx = GAUDI2_DCORE0_ENGINE_ID_TPC_6; + else + engine_idx = GAUDI2_DCORE0_ENGINE_ID_TPC_0 + + dcore * GAUDI2_ENGINE_ID_DCORE_OFFSET + inst; + + tpc_cfg_sts = RREG32(mmDCORE0_TPC0_CFG_STATUS + offset); + qm_glbl_sts0 = RREG32(mmDCORE0_TPC0_QM_GLBL_STS0 + offset); + qm_glbl_sts1 = RREG32(mmDCORE0_TPC0_QM_GLBL_STS1 + offset); + qm_cgm_sts = RREG32(mmDCORE0_TPC0_QM_CGM_STS + offset); + + is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts) && + IS_TPC_IDLE(tpc_cfg_sts); + *(idle_data->is_idle) &= is_eng_idle; + + if (idle_data->mask && !is_eng_idle) + set_bit(engine_idx, idle_data->mask); + + if (idle_data->s) + seq_printf(idle_data->s, idle_data->tpc_fmt, dcore, inst, + is_eng_idle ? "Y" : "N", + qm_glbl_sts0, qm_cgm_sts, tpc_cfg_sts); +} + +static bool gaudi2_is_device_idle(struct hl_device *hdev, u64 *mask_arr, + u8 mask_len, struct seq_file *s) +{ + u32 qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts, dma_core_idle_ind_mask, + mme_arch_sts, dec_swreg15, dec_enabled_bit; + struct asic_fixed_properties *prop = &hdev->asic_prop; + const char *rot_fmt = "%-6d%-5d%-9s%#-14x%#-12x%s\n"; + unsigned long *mask = (unsigned long *) mask_arr; + const char *edma_fmt = "%-6d%-6d%-9s%#-14x%#x\n"; + const char *mme_fmt = "%-5d%-6s%-9s%#-14x%#x\n"; + const char *nic_fmt = "%-5d%-9s%#-14x%#-12x\n"; + const char *pdma_fmt = "%-6d%-9s%#-14x%#x\n"; + const char *pcie_dec_fmt = "%-10d%-9s%#x\n"; + const char *dec_fmt = "%-6d%-5d%-9s%#x\n"; + bool is_idle = true, is_eng_idle; + u64 offset; + + struct gaudi2_tpc_idle_data tpc_idle_data = { + .tpc_fmt = "%-6d%-5d%-9s%#-14x%#-12x%#x\n", + .s = s, + .mask = mask, + .is_idle = &is_idle, + }; + struct iterate_module_ctx tpc_iter = { + .fn = &gaudi2_is_tpc_engine_idle, + .data = &tpc_idle_data, + }; + + int engine_idx, i, j; + + /* EDMA, Two engines per Dcore */ + if (s) + seq_puts(s, + "\nCORE EDMA is_idle QM_GLBL_STS0 DMA_CORE_IDLE_IND_MASK\n" + "---- ---- ------- ------------ ----------------------\n"); + + for (i = 0; i < NUM_OF_DCORES; i++) { + for (j = 0 ; j < NUM_OF_EDMA_PER_DCORE ; j++) { + int seq = i * NUM_OF_EDMA_PER_DCORE + j; + + if (!(prop->edma_enabled_mask & BIT(seq))) + continue; + + engine_idx = GAUDI2_DCORE0_ENGINE_ID_EDMA_0 + + i * GAUDI2_ENGINE_ID_DCORE_OFFSET + j; + offset = i * DCORE_OFFSET + j * DCORE_EDMA_OFFSET; + + dma_core_idle_ind_mask = + RREG32(mmDCORE0_EDMA0_CORE_IDLE_IND_MASK + offset); + + qm_glbl_sts0 = RREG32(mmDCORE0_EDMA0_QM_GLBL_STS0 + offset); + qm_glbl_sts1 = RREG32(mmDCORE0_EDMA0_QM_GLBL_STS1 + offset); + qm_cgm_sts = RREG32(mmDCORE0_EDMA0_QM_CGM_STS + offset); + + is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts) && + IS_DMA_IDLE(dma_core_idle_ind_mask); + is_idle &= is_eng_idle; + + if (mask && !is_eng_idle) + set_bit(engine_idx, mask); + + if (s) + seq_printf(s, edma_fmt, i, j, + is_eng_idle ? "Y" : "N", + qm_glbl_sts0, + dma_core_idle_ind_mask); + } + } + + /* PDMA, Two engines in Full chip */ + if (s) + seq_puts(s, + "\nPDMA is_idle QM_GLBL_STS0 DMA_CORE_IDLE_IND_MASK\n" + "---- ------- ------------ ----------------------\n"); + + for (i = 0 ; i < NUM_OF_PDMA ; i++) { + engine_idx = GAUDI2_ENGINE_ID_PDMA_0 + i; + offset = i * PDMA_OFFSET; + dma_core_idle_ind_mask = RREG32(mmPDMA0_CORE_IDLE_IND_MASK + offset); + + qm_glbl_sts0 = RREG32(mmPDMA0_QM_GLBL_STS0 + offset); + qm_glbl_sts1 = RREG32(mmPDMA0_QM_GLBL_STS1 + offset); + qm_cgm_sts = RREG32(mmPDMA0_QM_CGM_STS + offset); + + is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts) && + IS_DMA_IDLE(dma_core_idle_ind_mask); + is_idle &= is_eng_idle; + + if (mask && !is_eng_idle) + set_bit(engine_idx, mask); + + if (s) + seq_printf(s, pdma_fmt, i, is_eng_idle ? "Y" : "N", qm_glbl_sts0, + dma_core_idle_ind_mask); + } + + /* NIC, twelve macros in Full chip */ + if (s && hdev->nic_ports_mask) + seq_puts(s, + "\nNIC is_idle QM_GLBL_STS0 QM_CGM_STS\n" + "--- ------- ------------ ----------\n"); + + for (i = 0 ; i < NIC_NUMBER_OF_ENGINES ; i++) { + if (!(i & 1)) + offset = i / 2 * NIC_OFFSET; + else + offset += NIC_QM_OFFSET; + + if (!(hdev->nic_ports_mask & BIT(i))) + continue; + + engine_idx = GAUDI2_ENGINE_ID_NIC0_0 + i; + + + qm_glbl_sts0 = RREG32(mmNIC0_QM0_GLBL_STS0 + offset); + qm_glbl_sts1 = RREG32(mmNIC0_QM0_GLBL_STS1 + offset); + qm_cgm_sts = RREG32(mmNIC0_QM0_CGM_STS + offset); + + is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts); + is_idle &= is_eng_idle; + + if (mask && !is_eng_idle) + set_bit(engine_idx, mask); + + if (s) + seq_printf(s, nic_fmt, i, is_eng_idle ? "Y" : "N", qm_glbl_sts0, + qm_cgm_sts); + } + + if (s) + seq_puts(s, + "\nMME Stub is_idle QM_GLBL_STS0 MME_ARCH_STATUS\n" + "--- ---- ------- ------------ ---------------\n"); + /* MME, one per Dcore */ + for (i = 0 ; i < NUM_OF_DCORES ; i++) { + engine_idx = GAUDI2_DCORE0_ENGINE_ID_MME + i * GAUDI2_ENGINE_ID_DCORE_OFFSET; + offset = i * DCORE_OFFSET; + + qm_glbl_sts0 = RREG32(mmDCORE0_MME_QM_GLBL_STS0 + offset); + qm_glbl_sts1 = RREG32(mmDCORE0_MME_QM_GLBL_STS1 + offset); + qm_cgm_sts = RREG32(mmDCORE0_MME_QM_CGM_STS + offset); + + is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts); + is_idle &= is_eng_idle; + + mme_arch_sts = RREG32(mmDCORE0_MME_CTRL_LO_ARCH_STATUS + offset); + is_eng_idle &= IS_MME_IDLE(mme_arch_sts); + is_idle &= is_eng_idle; + + if (s) + seq_printf(s, mme_fmt, i, "N", + is_eng_idle ? "Y" : "N", + qm_glbl_sts0, + mme_arch_sts); + + if (mask && !is_eng_idle) + set_bit(engine_idx, mask); + } + + /* + * TPC + */ + if (s && prop->tpc_enabled_mask) + seq_puts(s, + "\nCORE TPC is_idle QM_GLBL_STS0 QM_CGM_STS DMA_CORE_IDLE_IND_MASK\n" + "---- --- -------- ------------ ---------- ----------------------\n"); + + gaudi2_iterate_tpcs(hdev, &tpc_iter); + + /* Decoders, two each Dcore and two shared PCIe decoders */ + if (s && (prop->decoder_enabled_mask & (~PCIE_DEC_EN_MASK))) + seq_puts(s, + "\nCORE DEC is_idle VSI_CMD_SWREG15\n" + "---- --- ------- ---------------\n"); + + for (i = 0 ; i < NUM_OF_DCORES ; i++) { + for (j = 0 ; j < NUM_OF_DEC_PER_DCORE ; j++) { + dec_enabled_bit = 1 << (i * NUM_OF_DEC_PER_DCORE + j); + if (!(prop->decoder_enabled_mask & dec_enabled_bit)) + continue; + + engine_idx = GAUDI2_DCORE0_ENGINE_ID_DEC_0 + + i * GAUDI2_ENGINE_ID_DCORE_OFFSET + j; + offset = i * DCORE_OFFSET + j * DCORE_DEC_OFFSET; + + dec_swreg15 = RREG32(mmDCORE0_DEC0_CMD_SWREG15 + offset); + is_eng_idle = IS_DEC_IDLE(dec_swreg15); + is_idle &= is_eng_idle; + + if (mask && !is_eng_idle) + set_bit(engine_idx, mask); + + if (s) + seq_printf(s, dec_fmt, i, j, is_eng_idle ? "Y" : "N", dec_swreg15); + } + } + + if (s && (prop->decoder_enabled_mask & PCIE_DEC_EN_MASK)) + seq_puts(s, + "\nPCIe DEC is_idle VSI_CMD_SWREG15\n" + "-------- ------- ---------------\n"); + + /* Check shared(PCIe) decoders */ + for (i = 0 ; i < NUM_OF_DEC_PER_DCORE ; i++) { + dec_enabled_bit = PCIE_DEC_SHIFT + i; + if (!(prop->decoder_enabled_mask & BIT(dec_enabled_bit))) + continue; + + engine_idx = GAUDI2_PCIE_ENGINE_ID_DEC_0 + i; + offset = i * DCORE_DEC_OFFSET; + dec_swreg15 = RREG32(mmPCIE_DEC0_CMD_SWREG15 + offset); + is_eng_idle = IS_DEC_IDLE(dec_swreg15); + is_idle &= is_eng_idle; + + if (mask && !is_eng_idle) + set_bit(engine_idx, mask); + + if (s) + seq_printf(s, pcie_dec_fmt, i, is_eng_idle ? "Y" : "N", dec_swreg15); + } + + if (s) + seq_puts(s, + "\nCORE ROT is_idle QM_GLBL_STS0 QM_CGM_STS DMA_CORE_STS0\n" + "---- ---- ------- ------------ ---------- -------------\n"); + + for (i = 0 ; i < NUM_OF_ROT ; i++) { + engine_idx = GAUDI2_ENGINE_ID_ROT_0 + i; + + offset = i * ROT_OFFSET; + + qm_glbl_sts0 = RREG32(mmROT0_QM_GLBL_STS0 + offset); + qm_glbl_sts1 = RREG32(mmROT0_QM_GLBL_STS1 + offset); + qm_cgm_sts = RREG32(mmROT0_QM_CGM_STS + offset); + + is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts); + is_idle &= is_eng_idle; + + if (mask && !is_eng_idle) + set_bit(engine_idx, mask); + + if (s) + seq_printf(s, rot_fmt, i, 0, is_eng_idle ? "Y" : "N", + qm_glbl_sts0, qm_cgm_sts, "-"); + } + + return is_idle; +} + +static void gaudi2_hw_queues_lock(struct hl_device *hdev) + __acquires(&gaudi2->hw_queues_lock) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + + spin_lock(&gaudi2->hw_queues_lock); +} + +static void gaudi2_hw_queues_unlock(struct hl_device *hdev) + __releases(&gaudi2->hw_queues_lock) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + + spin_unlock(&gaudi2->hw_queues_lock); +} + +static void gaudi2_kdma_lock(struct hl_device *hdev, int dcore_id) + __acquires(&gaudi2->kdma_lock) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + + spin_lock(&gaudi2->kdma_lock); +} + +static void gaudi2_kdma_unlock(struct hl_device *hdev, int dcore_id) + __releases(&gaudi2->kdma_lock) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + + spin_unlock(&gaudi2->kdma_lock); +} + +static u32 gaudi2_get_pci_id(struct hl_device *hdev) +{ + return hdev->pdev->device; +} + +static int gaudi2_get_eeprom_data(struct hl_device *hdev, void *data, size_t max_size) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + + if (!(gaudi2->hw_cap_initialized & HW_CAP_CPU_Q)) + return 0; + + return hl_fw_get_eeprom_data(hdev, data, max_size); +} + +static void gaudi2_update_eq_ci(struct hl_device *hdev, u32 val) +{ + WREG32(mmCPU_IF_EQ_RD_OFFS, val); +} + +static void *gaudi2_get_events_stat(struct hl_device *hdev, bool aggregate, u32 *size) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + + if (aggregate) { + *size = (u32) sizeof(gaudi2->events_stat_aggregate); + return gaudi2->events_stat_aggregate; + } + + *size = (u32) sizeof(gaudi2->events_stat); + return gaudi2->events_stat; +} + +static void gaudi2_mmu_vdec_dcore_prepare(struct hl_device *hdev, int dcore_id, + int dcore_vdec_id, u32 rw_asid, u32 rw_mmu_bp) +{ + u32 offset = (mmDCORE0_VDEC1_BRDG_CTRL_BASE - mmDCORE0_VDEC0_BRDG_CTRL_BASE) * + dcore_vdec_id + DCORE_OFFSET * dcore_id; + + WREG32(mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_MMU_BP + offset, rw_mmu_bp); + WREG32(mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_ASID + offset, rw_asid); + + WREG32(mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_MMU_BP + offset, rw_mmu_bp); + WREG32(mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_ASID + offset, rw_asid); + + WREG32(mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_MMU_BP + offset, rw_mmu_bp); + WREG32(mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_ASID + offset, rw_asid); + + WREG32(mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_MMU_BP + offset, rw_mmu_bp); + WREG32(mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_ASID + offset, rw_asid); + + WREG32(mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_MMU_BP + offset, rw_mmu_bp); + WREG32(mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_ASID + offset, rw_asid); +} + +static void gaudi2_mmu_dcore_prepare(struct hl_device *hdev, int dcore_id, u32 asid) +{ + u32 rw_asid = (asid << ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_SHIFT) | + (asid << ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_SHIFT); + struct asic_fixed_properties *prop = &hdev->asic_prop; + u32 dcore_offset = dcore_id * DCORE_OFFSET; + u32 vdec_id, i, ports_offset, reg_val; + u8 edma_seq_base; + + /* EDMA */ + edma_seq_base = dcore_id * NUM_OF_EDMA_PER_DCORE; + if (prop->edma_enabled_mask & BIT(edma_seq_base)) { + WREG32(mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_MMU_BP + dcore_offset, 0); + WREG32(mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_ASID + dcore_offset, rw_asid); + WREG32(mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_MMU_BP + dcore_offset, 0); + WREG32(mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_ASID + dcore_offset, rw_asid); + } + + if (prop->edma_enabled_mask & BIT(edma_seq_base + 1)) { + WREG32(mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_MMU_BP + dcore_offset, 0); + WREG32(mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_ASID + dcore_offset, rw_asid); + WREG32(mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_ASID + dcore_offset, rw_asid); + WREG32(mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_MMU_BP + dcore_offset, 0); + } + + /* Sync Mngr */ + WREG32(mmDCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV + dcore_offset, asid); + /* + * Sync Mngrs on dcores 1 - 3 are exposed to user, so must use user ASID + * for any access type + */ + if (dcore_id > 0) { + reg_val = (asid << DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_RD_SHIFT) | + (asid << DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_WR_SHIFT); + WREG32(mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID + dcore_offset, reg_val); + WREG32(mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP + dcore_offset, 0); + } + + WREG32(mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_MMU_BP + dcore_offset, 0); + WREG32(mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_ASID + dcore_offset, rw_asid); + + for (i = 0 ; i < NUM_OF_MME_SBTE_PORTS ; i++) { + ports_offset = i * DCORE_MME_SBTE_OFFSET; + WREG32(mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_MMU_BP + + dcore_offset + ports_offset, 0); + WREG32(mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_ASID + + dcore_offset + ports_offset, rw_asid); + } + + for (i = 0 ; i < NUM_OF_MME_WB_PORTS ; i++) { + ports_offset = i * DCORE_MME_WB_OFFSET; + WREG32(mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_MMU_BP + + dcore_offset + ports_offset, 0); + WREG32(mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_ASID + + dcore_offset + ports_offset, rw_asid); + } + + WREG32(mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_MMU_BP + dcore_offset, 0); + WREG32(mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_ASID + dcore_offset, rw_asid); + + /* + * Decoders + */ + for (vdec_id = 0 ; vdec_id < NUM_OF_DEC_PER_DCORE ; vdec_id++) { + if (prop->decoder_enabled_mask & BIT(dcore_id * NUM_OF_DEC_PER_DCORE + vdec_id)) + gaudi2_mmu_vdec_dcore_prepare(hdev, dcore_id, vdec_id, rw_asid, 0); + } +} + +static void gudi2_mmu_vdec_shared_prepare(struct hl_device *hdev, + int shared_vdec_id, u32 rw_asid, u32 rw_mmu_bp) +{ + u32 offset = (mmPCIE_VDEC1_BRDG_CTRL_BASE - mmPCIE_VDEC0_BRDG_CTRL_BASE) * shared_vdec_id; + + WREG32(mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_MMU_BP + offset, rw_mmu_bp); + WREG32(mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_ASID + offset, rw_asid); + + WREG32(mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_MMU_BP + offset, rw_mmu_bp); + WREG32(mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_ASID + offset, rw_asid); + + WREG32(mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_MMU_BP + offset, rw_mmu_bp); + WREG32(mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_ASID + offset, rw_asid); + + WREG32(mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_MMU_BP + offset, rw_mmu_bp); + WREG32(mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_ASID + offset, rw_asid); + + WREG32(mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_MMU_BP + offset, rw_mmu_bp); + WREG32(mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_ASID + offset, rw_asid); +} + +static void gudi2_mmu_arc_farm_arc_dup_eng_prepare(struct hl_device *hdev, int arc_farm_id, + u32 rw_asid, u32 rw_mmu_bp) +{ + u32 offset = (mmARC_FARM_ARC1_DUP_ENG_BASE - mmARC_FARM_ARC0_DUP_ENG_BASE) * arc_farm_id; + + WREG32(mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_MMU_BP + offset, rw_mmu_bp); + WREG32(mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_ASID + offset, rw_asid); +} + +static void gaudi2_arc_mmu_prepare(struct hl_device *hdev, u32 cpu_id, u32 asid) +{ + u32 reg_base, reg_offset, reg_val = 0; + + reg_base = gaudi2_arc_blocks_bases[cpu_id]; + + /* Enable MMU and configure asid for all relevant ARC regions */ + reg_val = FIELD_PREP(ARC_FARM_ARC0_AUX_ARC_REGION_CFG_MMU_BP_MASK, 0); + reg_val |= FIELD_PREP(ARC_FARM_ARC0_AUX_ARC_REGION_CFG_0_ASID_MASK, asid); + + reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION3_GENERAL); + WREG32(reg_base + reg_offset, reg_val); + + reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION4_HBM0_FW); + WREG32(reg_base + reg_offset, reg_val); + + reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION5_HBM1_GC_DATA); + WREG32(reg_base + reg_offset, reg_val); + + reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION6_HBM2_GC_DATA); + WREG32(reg_base + reg_offset, reg_val); + + reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION7_HBM3_GC_DATA); + WREG32(reg_base + reg_offset, reg_val); + + reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION9_PCIE); + WREG32(reg_base + reg_offset, reg_val); + + reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION10_GENERAL); + WREG32(reg_base + reg_offset, reg_val); + + reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION11_GENERAL); + WREG32(reg_base + reg_offset, reg_val); + + reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION12_GENERAL); + WREG32(reg_base + reg_offset, reg_val); + + reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION13_GENERAL); + WREG32(reg_base + reg_offset, reg_val); + + reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION14_GENERAL); + WREG32(reg_base + reg_offset, reg_val); +} + +static int gaudi2_arc_mmu_prepare_all(struct hl_device *hdev, u32 asid) +{ + int i; + + if (hdev->fw_components & FW_TYPE_BOOT_CPU) + return hl_fw_cpucp_engine_core_asid_set(hdev, asid); + + for (i = CPU_ID_SCHED_ARC0 ; i < NUM_OF_ARC_FARMS_ARC ; i++) + gaudi2_arc_mmu_prepare(hdev, i, asid); + + for (i = GAUDI2_QUEUE_ID_PDMA_0_0 ; i < GAUDI2_QUEUE_ID_CPU_PQ ; i += 4) { + if (!gaudi2_is_queue_enabled(hdev, i)) + continue; + + gaudi2_arc_mmu_prepare(hdev, gaudi2_queue_id_to_arc_id[i], asid); + } + + return 0; +} + +static int gaudi2_mmu_shared_prepare(struct hl_device *hdev, u32 asid) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + u32 rw_asid, offset; + int rc, i; + + rw_asid = FIELD_PREP(ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_MASK, asid) | + FIELD_PREP(ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_MASK, asid); + + WREG32(mmPDMA0_QM_AXUSER_NONSECURED_HB_ASID, rw_asid); + WREG32(mmPDMA0_QM_AXUSER_NONSECURED_HB_MMU_BP, 0); + WREG32(mmPDMA0_CORE_CTX_AXUSER_HB_ASID, rw_asid); + WREG32(mmPDMA0_CORE_CTX_AXUSER_HB_MMU_BP, 0); + + WREG32(mmPDMA1_QM_AXUSER_NONSECURED_HB_ASID, rw_asid); + WREG32(mmPDMA1_QM_AXUSER_NONSECURED_HB_MMU_BP, 0); + WREG32(mmPDMA1_CORE_CTX_AXUSER_HB_ASID, rw_asid); + WREG32(mmPDMA1_CORE_CTX_AXUSER_HB_MMU_BP, 0); + + /* ROT */ + for (i = 0 ; i < NUM_OF_ROT ; i++) { + offset = i * ROT_OFFSET; + WREG32(mmROT0_QM_AXUSER_NONSECURED_HB_ASID + offset, rw_asid); + WREG32(mmROT0_QM_AXUSER_NONSECURED_HB_MMU_BP + offset, 0); + RMWREG32(mmROT0_CPL_QUEUE_AWUSER + offset, asid, MMUBP_ASID_MASK); + RMWREG32(mmROT0_DESC_HBW_ARUSER_LO + offset, asid, MMUBP_ASID_MASK); + RMWREG32(mmROT0_DESC_HBW_AWUSER_LO + offset, asid, MMUBP_ASID_MASK); + } + + /* Shared Decoders are the last bits in the decoders mask */ + if (prop->decoder_enabled_mask & BIT(NUM_OF_DCORES * NUM_OF_DEC_PER_DCORE + 0)) + gudi2_mmu_vdec_shared_prepare(hdev, 0, rw_asid, 0); + + if (prop->decoder_enabled_mask & BIT(NUM_OF_DCORES * NUM_OF_DEC_PER_DCORE + 1)) + gudi2_mmu_vdec_shared_prepare(hdev, 1, rw_asid, 0); + + /* arc farm arc dup eng */ + for (i = 0 ; i < NUM_OF_ARC_FARMS_ARC ; i++) + gudi2_mmu_arc_farm_arc_dup_eng_prepare(hdev, i, rw_asid, 0); + + rc = gaudi2_arc_mmu_prepare_all(hdev, asid); + if (rc) + return rc; + + return 0; +} + +static void gaudi2_tpc_mmu_prepare(struct hl_device *hdev, int dcore, int inst, u32 offset, + void *data) +{ + struct gaudi2_tpc_mmu_data *mmu_data = (struct gaudi2_tpc_mmu_data *)data; + + WREG32(mmDCORE0_TPC0_CFG_AXUSER_HB_MMU_BP + offset, 0); + WREG32(mmDCORE0_TPC0_CFG_AXUSER_HB_ASID + offset, mmu_data->rw_asid); + WREG32(mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_MMU_BP + offset, 0); + WREG32(mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_ASID + offset, mmu_data->rw_asid); +} + +/* zero the MMUBP and set the ASID */ +static int gaudi2_mmu_prepare(struct hl_device *hdev, u32 asid) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + struct gaudi2_tpc_mmu_data tpc_mmu_data; + struct iterate_module_ctx tpc_iter = { + .fn = &gaudi2_tpc_mmu_prepare, + .data = &tpc_mmu_data, + }; + int rc, i; + + if (asid & ~DCORE0_HMMU0_STLB_ASID_ASID_MASK) { + dev_crit(hdev->dev, "asid %u is too big\n", asid); + return -EINVAL; + } + + if (!(gaudi2->hw_cap_initialized & HW_CAP_MMU_MASK)) + return 0; + + rc = gaudi2_mmu_shared_prepare(hdev, asid); + if (rc) + return rc; + + /* configure DCORE MMUs */ + tpc_mmu_data.rw_asid = (asid << ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_SHIFT) | + (asid << ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_SHIFT); + gaudi2_iterate_tpcs(hdev, &tpc_iter); + for (i = 0 ; i < NUM_OF_DCORES ; i++) + gaudi2_mmu_dcore_prepare(hdev, i, asid); + + return 0; +} + +static inline bool is_info_event(u32 event) +{ + switch (event) { + case GAUDI2_EVENT_CPU_CPLD_SHUTDOWN_CAUSE: + return true; + default: + return false; + } +} + +static void gaudi2_print_irq_info(struct hl_device *hdev, u16 event_type) +{ + char desc[64] = ""; + bool event_valid = false; + + /* return in case of NIC status event - these events are received periodically and not as + * an indication to an error, thus not printed. + */ + if (event_type >= GAUDI2_EVENT_CPU0_STATUS_NIC0_ENG0 && + event_type <= GAUDI2_EVENT_CPU11_STATUS_NIC11_ENG1) + return; + + if (gaudi2_irq_map_table[event_type].valid) { + snprintf(desc, sizeof(desc), gaudi2_irq_map_table[event_type].name); + event_valid = true; + } + + if (!event_valid) + snprintf(desc, sizeof(desc), "N/A"); + + if (is_info_event(event_type)) + dev_info_ratelimited(hdev->dev, "Received H/W interrupt %d [\"%s\"]\n", + event_type, desc); + else + dev_err_ratelimited(hdev->dev, "Received H/W interrupt %d [\"%s\"]\n", + event_type, desc); +} + +static bool gaudi2_handle_ecc_event(struct hl_device *hdev, u16 event_type, + struct hl_eq_ecc_data *ecc_data) +{ + u64 ecc_address = 0, ecc_syndrom = 0; + u8 memory_wrapper_idx = 0; + + ecc_address = le64_to_cpu(ecc_data->ecc_address); + ecc_syndrom = le64_to_cpu(ecc_data->ecc_syndrom); + memory_wrapper_idx = ecc_data->memory_wrapper_idx; + + dev_err(hdev->dev, + "ECC error detected. address: %#llx. Syndrom: %#llx. block id %u. critical %u.\n", + ecc_address, ecc_syndrom, memory_wrapper_idx, ecc_data->is_critical); + + return !!ecc_data->is_critical; +} + +/* + * gaudi2_queue_idx_dec - decrement queue index (pi/ci) and handle wrap + * + * @idx: the current pi/ci value + * @q_len: the queue length (power of 2) + * + * @return the cyclically decremented index + */ +static inline u32 gaudi2_queue_idx_dec(u32 idx, u32 q_len) +{ + u32 mask = q_len - 1; + + /* + * modular decrement is equivalent to adding (queue_size -1) + * later we take LSBs to make sure the value is in the + * range [0, queue_len - 1] + */ + return (idx + q_len - 1) & mask; +} + +/** + * gaudi2_print_sw_config_stream_data - print SW config stream data + * + * @hdev: pointer to the habanalabs device structure + * @stream: the QMAN's stream + * @qman_base: base address of QMAN registers block + */ +static void gaudi2_print_sw_config_stream_data(struct hl_device *hdev, + u32 stream, u64 qman_base) +{ + u64 cq_ptr_lo, cq_ptr_hi, cq_tsize, cq_ptr; + u32 cq_ptr_lo_off, size; + + cq_ptr_lo_off = mmDCORE0_TPC0_QM_CQ_PTR_LO_1 - mmDCORE0_TPC0_QM_CQ_PTR_LO_0; + + cq_ptr_lo = qman_base + (mmDCORE0_TPC0_QM_CQ_PTR_LO_0 - mmDCORE0_TPC0_QM_BASE) + + stream * cq_ptr_lo_off; + + cq_ptr_hi = cq_ptr_lo + (mmDCORE0_TPC0_QM_CQ_PTR_HI_0 - mmDCORE0_TPC0_QM_CQ_PTR_LO_0); + + cq_tsize = cq_ptr_lo + (mmDCORE0_TPC0_QM_CQ_TSIZE_0 - mmDCORE0_TPC0_QM_CQ_PTR_LO_0); + + cq_ptr = (((u64) RREG32(cq_ptr_hi)) << 32) | RREG32(cq_ptr_lo); + size = RREG32(cq_tsize); + dev_info(hdev->dev, "stop on err: stream: %u, addr: %#llx, size: %x\n", + stream, cq_ptr, size); +} + +/** + * gaudi2_print_last_pqes_on_err - print last PQEs on error + * + * @hdev: pointer to the habanalabs device structure + * @qid_base: first QID of the QMAN (out of 4 streams) + * @stream: the QMAN's stream + * @qman_base: base address of QMAN registers block + * @pr_sw_conf: if true print the SW config stream data (CQ PTR and SIZE) + */ +static void gaudi2_print_last_pqes_on_err(struct hl_device *hdev, u32 qid_base, u32 stream, + u64 qman_base, bool pr_sw_conf) +{ + u32 ci, qm_ci_stream_off; + struct hl_hw_queue *q; + u64 pq_ci; + int i; + + q = &hdev->kernel_queues[qid_base + stream]; + + qm_ci_stream_off = mmDCORE0_TPC0_QM_PQ_CI_1 - mmDCORE0_TPC0_QM_PQ_CI_0; + pq_ci = qman_base + (mmDCORE0_TPC0_QM_PQ_CI_0 - mmDCORE0_TPC0_QM_BASE) + + stream * qm_ci_stream_off; + + hdev->asic_funcs->hw_queues_lock(hdev); + + if (pr_sw_conf) + gaudi2_print_sw_config_stream_data(hdev, stream, qman_base); + + ci = RREG32(pq_ci); + + /* we should start printing form ci -1 */ + ci = gaudi2_queue_idx_dec(ci, HL_QUEUE_LENGTH); + + for (i = 0; i < PQ_FETCHER_CACHE_SIZE; i++) { + struct hl_bd *bd; + u64 addr; + u32 len; + + bd = q->kernel_address; + bd += ci; + + len = le32_to_cpu(bd->len); + /* len 0 means uninitialized entry- break */ + if (!len) + break; + + addr = le64_to_cpu(bd->ptr); + + dev_info(hdev->dev, "stop on err PQE(stream %u): ci: %u, addr: %#llx, size: %x\n", + stream, ci, addr, len); + + /* get previous ci, wrap if needed */ + ci = gaudi2_queue_idx_dec(ci, HL_QUEUE_LENGTH); + } + + hdev->asic_funcs->hw_queues_unlock(hdev); +} + +/** + * print_qman_data_on_err - extract QMAN data on error + * + * @hdev: pointer to the habanalabs device structure + * @qid_base: first QID of the QMAN (out of 4 streams) + * @stream: the QMAN's stream + * @qman_base: base address of QMAN registers block + * + * This function attempt to extract as much data as possible on QMAN error. + * On upper CP print the SW config stream data and last 8 PQEs. + * On lower CP print SW config data and last PQEs of ALL 4 upper CPs + */ +static void print_qman_data_on_err(struct hl_device *hdev, u32 qid_base, u32 stream, u64 qman_base) +{ + u32 i; + + if (stream != QMAN_STREAMS) { + gaudi2_print_last_pqes_on_err(hdev, qid_base, stream, qman_base, true); + return; + } + + gaudi2_print_sw_config_stream_data(hdev, stream, qman_base); + + for (i = 0 ; i < QMAN_STREAMS ; i++) + gaudi2_print_last_pqes_on_err(hdev, qid_base, i, qman_base, false); +} + +static void gaudi2_handle_qman_err_generic(struct hl_device *hdev, const char *qm_name, + u64 qman_base, u32 qid_base) +{ + u32 i, j, glbl_sts_val, arb_err_val, num_error_causes; + u64 glbl_sts_addr, arb_err_addr; + char reg_desc[32]; + + glbl_sts_addr = qman_base + (mmDCORE0_TPC0_QM_GLBL_ERR_STS_0 - mmDCORE0_TPC0_QM_BASE); + arb_err_addr = qman_base + (mmDCORE0_TPC0_QM_ARB_ERR_CAUSE - mmDCORE0_TPC0_QM_BASE); + + /* Iterate through all stream GLBL_ERR_STS registers + Lower CP */ + for (i = 0 ; i < QMAN_STREAMS + 1 ; i++) { + glbl_sts_val = RREG32(glbl_sts_addr + 4 * i); + + if (!glbl_sts_val) + continue; + + if (i == QMAN_STREAMS) { + snprintf(reg_desc, ARRAY_SIZE(reg_desc), "LowerCP"); + num_error_causes = GAUDI2_NUM_OF_QM_LCP_ERR_CAUSE; + } else { + snprintf(reg_desc, ARRAY_SIZE(reg_desc), "stream%u", i); + num_error_causes = GAUDI2_NUM_OF_QM_ERR_CAUSE; + } + + for (j = 0 ; j < num_error_causes ; j++) + if (glbl_sts_val & BIT(j)) + dev_err_ratelimited(hdev->dev, "%s %s. err cause: %s\n", + qm_name, reg_desc, + i == QMAN_STREAMS ? + gaudi2_qman_lower_cp_error_cause[j] : + gaudi2_qman_error_cause[j]); + + print_qman_data_on_err(hdev, qid_base, i, qman_base); + } + + arb_err_val = RREG32(arb_err_addr); + + if (!arb_err_val) + return; + + for (j = 0 ; j < GAUDI2_NUM_OF_QM_ARB_ERR_CAUSE ; j++) { + if (arb_err_val & BIT(j)) + dev_err_ratelimited(hdev->dev, "%s ARB_ERR. err cause: %s\n", + qm_name, gaudi2_qman_arb_error_cause[j]); + } +} + +static void gaudi2_razwi_rr_hbw_shared_printf_info(struct hl_device *hdev, + u64 rtr_mstr_if_base_addr, bool is_write, char *name, + bool read_razwi_regs, struct hl_eq_razwi_info *razwi_info) +{ + u32 razwi_hi, razwi_lo, razwi_xy; + + if (is_write) { + if (read_razwi_regs) { + razwi_hi = RREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AW_RAZWI_HI); + razwi_lo = RREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AW_RAZWI_LO); + razwi_xy = RREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AW_RAZWI_XY); + } else { + razwi_hi = le32_to_cpu(razwi_info->hbw.rr_aw_razwi_hi_reg); + razwi_lo = le32_to_cpu(razwi_info->hbw.rr_aw_razwi_lo_reg); + razwi_xy = le32_to_cpu(razwi_info->hbw.rr_aw_razwi_id_reg); + } + + dev_err_ratelimited(hdev->dev, + "%s-RAZWI SHARED RR HBW WR error, captured address HI 0x%x LO 0x%x, Initiator coordinates 0x%x\n", + name, razwi_hi, razwi_lo, razwi_xy); + } else { + if (read_razwi_regs) { + razwi_hi = RREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AR_RAZWI_HI); + razwi_lo = RREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AR_RAZWI_LO); + razwi_xy = RREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AR_RAZWI_XY); + } else { + razwi_hi = le32_to_cpu(razwi_info->hbw.rr_ar_razwi_hi_reg); + razwi_lo = le32_to_cpu(razwi_info->hbw.rr_ar_razwi_lo_reg); + razwi_xy = le32_to_cpu(razwi_info->hbw.rr_ar_razwi_id_reg); + } + + dev_err_ratelimited(hdev->dev, + "%s-RAZWI SHARED RR HBW AR error, captured address HI 0x%x LO 0x%x, Initiator coordinates 0x%x\n", + name, razwi_hi, razwi_lo, razwi_xy); + } +} + +static void gaudi2_razwi_rr_lbw_shared_printf_info(struct hl_device *hdev, + u64 rtr_mstr_if_base_addr, bool is_write, char *name, + bool read_razwi_regs, struct hl_eq_razwi_info *razwi_info) +{ + u32 razwi_addr, razwi_xy; + + if (is_write) { + if (read_razwi_regs) { + razwi_addr = RREG32(rtr_mstr_if_base_addr + RR_SHRD_LBW_AW_RAZWI); + razwi_xy = RREG32(rtr_mstr_if_base_addr + RR_SHRD_LBW_AW_RAZWI_XY); + } else { + razwi_addr = le32_to_cpu(razwi_info->lbw.rr_aw_razwi_reg); + razwi_xy = le32_to_cpu(razwi_info->lbw.rr_aw_razwi_id_reg); + } + + dev_err_ratelimited(hdev->dev, + "%s-RAZWI SHARED RR LBW WR error, mstr_if 0x%llx, captured address 0x%x, Initiator coordinates 0x%x\n", + name, rtr_mstr_if_base_addr, razwi_addr, razwi_xy); + } else { + if (read_razwi_regs) { + razwi_addr = RREG32(rtr_mstr_if_base_addr + RR_SHRD_LBW_AR_RAZWI); + razwi_xy = RREG32(rtr_mstr_if_base_addr + RR_SHRD_LBW_AR_RAZWI_XY); + } else { + razwi_addr = le32_to_cpu(razwi_info->lbw.rr_ar_razwi_reg); + razwi_xy = le32_to_cpu(razwi_info->lbw.rr_ar_razwi_id_reg); + } + + dev_err_ratelimited(hdev->dev, + "%s-RAZWI SHARED RR LBW AR error, mstr_if 0x%llx, captured address 0x%x Initiator coordinates 0x%x\n", + name, rtr_mstr_if_base_addr, razwi_addr, razwi_xy); + } +} + +/* + * This function handles RR(Range register) hit events. + * raised be initiators not PSOC RAZWI. + */ +static void gaudi2_ack_module_razwi_event_handler(struct hl_device *hdev, + enum razwi_event_sources module, u8 module_idx, + u8 module_sub_idx, struct hl_eq_razwi_info *razwi_info) +{ + bool via_sft = false, read_razwi_regs = false; + u32 rtr_id, dcore_id, dcore_rtr_id, sft_id; + u64 rtr_mstr_if_base_addr; + u32 hbw_shrd_aw = 0, hbw_shrd_ar = 0; + u32 lbw_shrd_aw = 0, lbw_shrd_ar = 0; + char initiator_name[64]; + + if (hdev->pldm || !(hdev->fw_components & FW_TYPE_LINUX) || !razwi_info) + read_razwi_regs = true; + + switch (module) { + case RAZWI_TPC: + rtr_id = gaudi2_tpc_initiator_rtr_id[module_idx]; + sprintf(initiator_name, "TPC_%u", module_idx); + break; + case RAZWI_MME: + sprintf(initiator_name, "MME_%u", module_idx); + switch (module_sub_idx) { + case MME_WAP0: + rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].wap0; + break; + case MME_WAP1: + rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].wap1; + break; + case MME_WRITE: + rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].write; + break; + case MME_READ: + rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].read; + break; + case MME_SBTE0: + rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].sbte0; + break; + case MME_SBTE1: + rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].sbte1; + break; + case MME_SBTE2: + rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].sbte2; + break; + case MME_SBTE3: + rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].sbte3; + break; + case MME_SBTE4: + rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].sbte4; + break; + default: + return; + } + break; + case RAZWI_EDMA: + sft_id = gaudi2_edma_initiator_sft_id[module_idx].interface_id; + dcore_id = gaudi2_edma_initiator_sft_id[module_idx].dcore_id; + via_sft = true; + sprintf(initiator_name, "EDMA_%u", module_idx); + break; + case RAZWI_PDMA: + rtr_id = gaudi2_pdma_initiator_rtr_id[module_idx]; + sprintf(initiator_name, "PDMA_%u", module_idx); + break; + case RAZWI_NIC: + rtr_id = gaudi2_nic_initiator_rtr_id[module_idx]; + sprintf(initiator_name, "NIC_%u", module_idx); + break; + case RAZWI_DEC: + rtr_id = gaudi2_dec_initiator_rtr_id[module_idx]; + sprintf(initiator_name, "DEC_%u", module_idx); + break; + case RAZWI_ROT: + rtr_id = gaudi2_rot_initiator_rtr_id[module_idx]; + sprintf(initiator_name, "ROT_%u", module_idx); + break; + default: + return; + } + + if (!read_razwi_regs) { + if (le32_to_cpu(razwi_info->razwi_happened_mask) & RAZWI_HAPPENED_HBW) { + hbw_shrd_aw = le32_to_cpu(razwi_info->razwi_happened_mask) & + RAZWI_HAPPENED_AW; + hbw_shrd_ar = le32_to_cpu(razwi_info->razwi_happened_mask) & + RAZWI_HAPPENED_AR; + } else if (le32_to_cpu(razwi_info->razwi_happened_mask) & RAZWI_HAPPENED_LBW) { + lbw_shrd_aw = le32_to_cpu(razwi_info->razwi_happened_mask) & + RAZWI_HAPPENED_AW; + lbw_shrd_ar = le32_to_cpu(razwi_info->razwi_happened_mask) & + RAZWI_HAPPENED_AR; + } + rtr_mstr_if_base_addr = 0; + + goto dump_info; + } + + /* Find router mstr_if register base */ + if (via_sft) { + rtr_mstr_if_base_addr = mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE + + dcore_id * SFT_DCORE_OFFSET + + sft_id * SFT_IF_OFFSET + + RTR_MSTR_IF_OFFSET; + } else { + dcore_id = rtr_id / NUM_OF_RTR_PER_DCORE; + dcore_rtr_id = rtr_id % NUM_OF_RTR_PER_DCORE; + rtr_mstr_if_base_addr = mmDCORE0_RTR0_CTRL_BASE + + dcore_id * DCORE_OFFSET + + dcore_rtr_id * DCORE_RTR_OFFSET + + RTR_MSTR_IF_OFFSET; + } + + /* Find out event cause by reading "RAZWI_HAPPENED" registers */ + hbw_shrd_aw = RREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AW_RAZWI_HAPPENED); + + hbw_shrd_ar = RREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AR_RAZWI_HAPPENED); + + if (via_sft) { + /* SFT has separate MSTR_IF for LBW, only there we can + * read the LBW razwi related registers + */ + u64 base; + + base = mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE + dcore_id * SFT_DCORE_OFFSET + + RTR_LBW_MSTR_IF_OFFSET; + + lbw_shrd_aw = RREG32(base + RR_SHRD_LBW_AW_RAZWI_HAPPENED); + + lbw_shrd_ar = RREG32(base + RR_SHRD_LBW_AR_RAZWI_HAPPENED); + } else { + lbw_shrd_aw = RREG32(rtr_mstr_if_base_addr + RR_SHRD_LBW_AW_RAZWI_HAPPENED); + + lbw_shrd_ar = RREG32(rtr_mstr_if_base_addr + RR_SHRD_LBW_AR_RAZWI_HAPPENED); + } + +dump_info: + /* check if there is no RR razwi indication at all */ + if (!hbw_shrd_aw && !hbw_shrd_ar && !lbw_shrd_aw && !lbw_shrd_ar) + return; + + if (hbw_shrd_aw) { + gaudi2_razwi_rr_hbw_shared_printf_info(hdev, rtr_mstr_if_base_addr, true, + initiator_name, read_razwi_regs, razwi_info); + + /* Clear event indication */ + if (read_razwi_regs) + WREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AW_RAZWI_HAPPENED, hbw_shrd_aw); + } + + if (hbw_shrd_ar) { + gaudi2_razwi_rr_hbw_shared_printf_info(hdev, rtr_mstr_if_base_addr, false, + initiator_name, read_razwi_regs, razwi_info); + + /* Clear event indication */ + if (read_razwi_regs) + WREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AR_RAZWI_HAPPENED, hbw_shrd_ar); + } + + if (lbw_shrd_aw) { + gaudi2_razwi_rr_lbw_shared_printf_info(hdev, rtr_mstr_if_base_addr, true, + initiator_name, read_razwi_regs, razwi_info); + + /* Clear event indication */ + if (read_razwi_regs) + WREG32(rtr_mstr_if_base_addr + RR_SHRD_LBW_AW_RAZWI_HAPPENED, lbw_shrd_aw); + } + + if (lbw_shrd_ar) { + gaudi2_razwi_rr_lbw_shared_printf_info(hdev, rtr_mstr_if_base_addr, false, + initiator_name, read_razwi_regs, razwi_info); + + /* Clear event indication */ + if (read_razwi_regs) + WREG32(rtr_mstr_if_base_addr + RR_SHRD_LBW_AR_RAZWI_HAPPENED, lbw_shrd_ar); + } +} + +static void gaudi2_check_if_razwi_happened(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + u8 mod_idx, sub_mod; + + /* check all TPCs */ + for (mod_idx = 0 ; mod_idx < (NUM_OF_TPC_PER_DCORE * NUM_OF_DCORES + 1) ; mod_idx++) { + if (prop->tpc_enabled_mask & BIT(mod_idx)) + gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_TPC, mod_idx, 0, NULL); + } + + /* check all MMEs */ + for (mod_idx = 0 ; mod_idx < (NUM_OF_MME_PER_DCORE * NUM_OF_DCORES) ; mod_idx++) + for (sub_mod = MME_WAP0 ; sub_mod < MME_INITIATORS_MAX ; sub_mod++) + gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_MME, mod_idx, + sub_mod, NULL); + + /* check all EDMAs */ + for (mod_idx = 0 ; mod_idx < (NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES) ; mod_idx++) + if (prop->edma_enabled_mask & BIT(mod_idx)) + gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_EDMA, mod_idx, 0, NULL); + + /* check all PDMAs */ + for (mod_idx = 0 ; mod_idx < NUM_OF_PDMA ; mod_idx++) + gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_PDMA, mod_idx, 0, NULL); + + /* check all NICs */ + for (mod_idx = 0 ; mod_idx < NIC_NUMBER_OF_PORTS ; mod_idx++) + if (hdev->nic_ports_mask & BIT(mod_idx)) + gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_NIC, mod_idx >> 1, 0, + NULL); + + /* check all DECs */ + for (mod_idx = 0 ; mod_idx < NUMBER_OF_DEC ; mod_idx++) + if (prop->decoder_enabled_mask & BIT(mod_idx)) + gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_DEC, mod_idx, 0, NULL); + + /* check all ROTs */ + for (mod_idx = 0 ; mod_idx < NUM_OF_ROT ; mod_idx++) + gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_ROT, mod_idx, 0, NULL); +} + +static void gaudi2_razwi_unmapped_addr_hbw_printf_info(struct hl_device *hdev, + u64 rtr_ctrl_base_addr, bool is_write) +{ + u32 razwi_hi, razwi_lo; + + if (is_write) { + razwi_hi = RREG32(rtr_ctrl_base_addr + DEC_RAZWI_HBW_AW_ADDR_HI); + razwi_lo = RREG32(rtr_ctrl_base_addr + DEC_RAZWI_HBW_AW_ADDR_LO); + + dev_err_ratelimited(hdev->dev, + "RAZWI PSOC unmapped HBW WR error, ctr_base 0x%llx, captured address HI 0x%x, LO 0x%x\n", + rtr_ctrl_base_addr, razwi_hi, razwi_lo); + + /* Clear set indication */ + WREG32(rtr_ctrl_base_addr + DEC_RAZWI_HBW_AW_SET, 0x1); + } else { + razwi_hi = RREG32(rtr_ctrl_base_addr + DEC_RAZWI_HBW_AR_ADDR_HI); + + razwi_lo = RREG32(rtr_ctrl_base_addr + DEC_RAZWI_HBW_AR_ADDR_LO); + + dev_err_ratelimited(hdev->dev, + "RAZWI PSOC unmapped HBW AR error, ctr_base 0x%llx, captured address HI 0x%x, LO 0x%x\n", + rtr_ctrl_base_addr, razwi_hi, razwi_lo); + + /* Clear set indication */ + WREG32(rtr_ctrl_base_addr + DEC_RAZWI_HBW_AR_SET, 0x1); + } +} + +static void gaudi2_razwi_unmapped_addr_lbw_printf_info(struct hl_device *hdev, + u64 rtr_ctrl_base_addr, bool is_write) +{ + u32 razwi_addr; + + if (is_write) { + razwi_addr = RREG32(rtr_ctrl_base_addr + DEC_RAZWI_LBW_AW_ADDR); + + dev_err_ratelimited(hdev->dev, + "RAZWI PSOC unmapped LBW WR error, ctr_base 0x%llx, captured address 0x%x\n", + rtr_ctrl_base_addr, razwi_addr); + + /* Clear set indication */ + WREG32(rtr_ctrl_base_addr + DEC_RAZWI_LBW_AW_SET, 0x1); + } else { + razwi_addr = RREG32(rtr_ctrl_base_addr + DEC_RAZWI_LBW_AR_ADDR); + + dev_err_ratelimited(hdev->dev, + "RAZWI PSOC unmapped LBW AR error, ctr_base 0x%llx, captured address 0x%x\n", + rtr_ctrl_base_addr, razwi_addr); + + /* Clear set indication */ + WREG32(rtr_ctrl_base_addr + DEC_RAZWI_LBW_AR_SET, 0x1); + } +} + +/* PSOC RAZWI interrupt occurs only when trying to access a bad address */ +static void gaudi2_ack_psoc_razwi_event_handler(struct hl_device *hdev) +{ + u32 hbw_aw_set, hbw_ar_set, lbw_aw_set, lbw_ar_set, rtr_id, dcore_id, dcore_rtr_id, xy, + razwi_mask_info, razwi_intr = 0; + int rtr_map_arr_len = NUM_OF_RTR_PER_DCORE * NUM_OF_DCORES; + u64 rtr_ctrl_base_addr; + + if (hdev->pldm || !(hdev->fw_components & FW_TYPE_LINUX)) { + razwi_intr = RREG32(mmPSOC_GLOBAL_CONF_RAZWI_INTERRUPT); + if (!razwi_intr) + return; + } + + razwi_mask_info = RREG32(mmPSOC_GLOBAL_CONF_RAZWI_MASK_INFO); + + xy = (razwi_mask_info & PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_L_MASK) + >> PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_L_SHIFT; + + dev_err_ratelimited(hdev->dev, + "PSOC RAZWI interrupt: Mask %d, WAS_AR %d, WAS_AW %d, AXUSER_L 0x%x AXUSER_H 0x%x\n", + (razwi_mask_info & PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_MASK_MASK) + >> PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_MASK_SHIFT, + (razwi_mask_info & PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AR_MASK) + >> PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AR_SHIFT, + (razwi_mask_info & PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AW_MASK) + >> PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AW_SHIFT, xy, + (razwi_mask_info & + PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_H_MASK) + >> PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_H_SHIFT); + if (xy == 0) { + dev_err_ratelimited(hdev->dev, + "PSOC RAZWI interrupt: received event from 0 rtr coordinates\n"); + goto clear; + } + + /* Find router id by router coordinates */ + for (rtr_id = 0 ; rtr_id < rtr_map_arr_len ; rtr_id++) + if (rtr_coordinates_to_rtr_id[rtr_id] == xy) + break; + + if (rtr_id == rtr_map_arr_len) { + dev_err_ratelimited(hdev->dev, + "PSOC RAZWI interrupt: invalid rtr coordinates (0x%x)\n", xy); + goto clear; + } + + /* Find router mstr_if register base */ + dcore_id = rtr_id / NUM_OF_RTR_PER_DCORE; + dcore_rtr_id = rtr_id % NUM_OF_RTR_PER_DCORE; + rtr_ctrl_base_addr = mmDCORE0_RTR0_CTRL_BASE + dcore_id * DCORE_OFFSET + + dcore_rtr_id * DCORE_RTR_OFFSET; + + hbw_aw_set = RREG32(rtr_ctrl_base_addr + DEC_RAZWI_HBW_AW_SET); + hbw_ar_set = RREG32(rtr_ctrl_base_addr + DEC_RAZWI_HBW_AR_SET); + lbw_aw_set = RREG32(rtr_ctrl_base_addr + DEC_RAZWI_LBW_AW_SET); + lbw_ar_set = RREG32(rtr_ctrl_base_addr + DEC_RAZWI_LBW_AR_SET); + + if (hbw_aw_set) + gaudi2_razwi_unmapped_addr_hbw_printf_info(hdev, rtr_ctrl_base_addr, true); + + if (hbw_ar_set) + gaudi2_razwi_unmapped_addr_hbw_printf_info(hdev, rtr_ctrl_base_addr, false); + + if (lbw_aw_set) + gaudi2_razwi_unmapped_addr_lbw_printf_info(hdev, rtr_ctrl_base_addr, true); + + if (lbw_ar_set) + gaudi2_razwi_unmapped_addr_lbw_printf_info(hdev, rtr_ctrl_base_addr, false); + +clear: + /* Clear Interrupts only on pldm or if f/w doesn't handle interrupts */ + if (hdev->pldm || !(hdev->fw_components & FW_TYPE_LINUX)) + WREG32(mmPSOC_GLOBAL_CONF_RAZWI_INTERRUPT, razwi_intr); +} + +static void _gaudi2_handle_qm_sei_err(struct hl_device *hdev, u64 qman_base) +{ + u32 i, sts_val, sts_clr_val = 0; + + sts_val = RREG32(qman_base + QM_SEI_STATUS_OFFSET); + + for (i = 0 ; i < GAUDI2_NUM_OF_QM_SEI_ERR_CAUSE ; i++) { + if (sts_val & BIT(i)) { + dev_err_ratelimited(hdev->dev, "QM SEI. err cause: %s\n", + gaudi2_qm_sei_error_cause[i]); + sts_clr_val |= BIT(i); + } + } + + WREG32(qman_base + QM_SEI_STATUS_OFFSET, sts_clr_val); +} + +static void gaudi2_handle_qm_sei_err(struct hl_device *hdev, u16 event_type, + struct hl_eq_razwi_info *razwi_info) +{ + u64 qman_base; + u8 index; + + switch (event_type) { + case GAUDI2_EVENT_TPC0_AXI_ERR_RSP ... GAUDI2_EVENT_TPC23_AXI_ERR_RSP: + index = event_type - GAUDI2_EVENT_TPC0_AXI_ERR_RSP; + qman_base = mmDCORE0_TPC0_QM_BASE + + (index / NUM_OF_TPC_PER_DCORE) * DCORE_OFFSET + + (index % NUM_OF_TPC_PER_DCORE) * DCORE_TPC_OFFSET; + break; + case GAUDI2_EVENT_TPC24_AXI_ERR_RSP: + qman_base = mmDCORE0_TPC6_QM_BASE; + break; + case GAUDI2_EVENT_MME0_CTRL_AXI_ERROR_RESPONSE: + case GAUDI2_EVENT_MME1_CTRL_AXI_ERROR_RESPONSE: + case GAUDI2_EVENT_MME2_CTRL_AXI_ERROR_RESPONSE: + case GAUDI2_EVENT_MME3_CTRL_AXI_ERROR_RESPONSE: + index = (event_type - GAUDI2_EVENT_MME0_CTRL_AXI_ERROR_RESPONSE) / + (GAUDI2_EVENT_MME1_CTRL_AXI_ERROR_RESPONSE - + GAUDI2_EVENT_MME0_CTRL_AXI_ERROR_RESPONSE); + qman_base = mmDCORE0_MME_QM_BASE + index * DCORE_OFFSET; + break; + case GAUDI2_EVENT_PDMA_CH0_AXI_ERR_RSP: + case GAUDI2_EVENT_PDMA_CH1_AXI_ERR_RSP: + index = event_type - GAUDI2_EVENT_PDMA_CH0_AXI_ERR_RSP; + qman_base = mmPDMA0_QM_BASE + index * PDMA_OFFSET; + break; + case GAUDI2_EVENT_ROTATOR0_AXI_ERROR_RESPONSE: + case GAUDI2_EVENT_ROTATOR1_AXI_ERROR_RESPONSE: + index = event_type - GAUDI2_EVENT_ROTATOR0_AXI_ERROR_RESPONSE; + qman_base = mmROT0_QM_BASE + index * ROT_OFFSET; + break; + default: + return; + } + + _gaudi2_handle_qm_sei_err(hdev, qman_base); + + /* There is a single event per NIC macro, so should check its both QMAN blocks */ + if (event_type >= GAUDI2_EVENT_NIC0_AXI_ERROR_RESPONSE && + event_type <= GAUDI2_EVENT_NIC11_AXI_ERROR_RESPONSE) + _gaudi2_handle_qm_sei_err(hdev, qman_base + NIC_QM_OFFSET); + + /* check if RAZWI happened */ + if (razwi_info) + gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_PDMA, 0, 0, razwi_info); +} + +static void gaudi2_handle_qman_err(struct hl_device *hdev, u16 event_type) +{ + u32 qid_base; + u64 qman_base; + char desc[32]; + u8 index; + + switch (event_type) { + case GAUDI2_EVENT_TPC0_QM ... GAUDI2_EVENT_TPC5_QM: + index = event_type - GAUDI2_EVENT_TPC0_QM; + qid_base = GAUDI2_QUEUE_ID_DCORE0_TPC_0_0 + index * QMAN_STREAMS; + qman_base = mmDCORE0_TPC0_QM_BASE + index * DCORE_TPC_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "DCORE0_TPC%d_QM", index); + break; + case GAUDI2_EVENT_TPC6_QM ... GAUDI2_EVENT_TPC11_QM: + index = event_type - GAUDI2_EVENT_TPC6_QM; + qid_base = GAUDI2_QUEUE_ID_DCORE1_TPC_0_0 + index * QMAN_STREAMS; + qman_base = mmDCORE1_TPC0_QM_BASE + index * DCORE_TPC_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "DCORE1_TPC%d_QM", index); + break; + case GAUDI2_EVENT_TPC12_QM ... GAUDI2_EVENT_TPC17_QM: + index = event_type - GAUDI2_EVENT_TPC12_QM; + qid_base = GAUDI2_QUEUE_ID_DCORE2_TPC_0_0 + index * QMAN_STREAMS; + qman_base = mmDCORE2_TPC0_QM_BASE + index * DCORE_TPC_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "DCORE2_TPC%d_QM", index); + break; + case GAUDI2_EVENT_TPC18_QM ... GAUDI2_EVENT_TPC23_QM: + index = event_type - GAUDI2_EVENT_TPC18_QM; + qid_base = GAUDI2_QUEUE_ID_DCORE3_TPC_0_0 + index * QMAN_STREAMS; + qman_base = mmDCORE3_TPC0_QM_BASE + index * DCORE_TPC_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "DCORE3_TPC%d_QM", index); + break; + case GAUDI2_EVENT_TPC24_QM: + qid_base = GAUDI2_QUEUE_ID_DCORE0_TPC_6_0; + qman_base = mmDCORE0_TPC6_QM_BASE; + snprintf(desc, ARRAY_SIZE(desc), "DCORE0_TPC6_QM"); + break; + case GAUDI2_EVENT_MME0_QM: + qid_base = GAUDI2_QUEUE_ID_DCORE0_MME_0_0; + qman_base = mmDCORE0_MME_QM_BASE; + snprintf(desc, ARRAY_SIZE(desc), "DCORE0_MME_QM"); + break; + case GAUDI2_EVENT_MME1_QM: + qid_base = GAUDI2_QUEUE_ID_DCORE1_MME_0_0; + qman_base = mmDCORE1_MME_QM_BASE; + snprintf(desc, ARRAY_SIZE(desc), "DCORE1_MME_QM"); + break; + case GAUDI2_EVENT_MME2_QM: + qid_base = GAUDI2_QUEUE_ID_DCORE2_MME_0_0; + qman_base = mmDCORE2_MME_QM_BASE; + snprintf(desc, ARRAY_SIZE(desc), "DCORE2_MME_QM"); + break; + case GAUDI2_EVENT_MME3_QM: + qid_base = GAUDI2_QUEUE_ID_DCORE3_MME_0_0; + qman_base = mmDCORE3_MME_QM_BASE; + snprintf(desc, ARRAY_SIZE(desc), "DCORE3_MME_QM"); + break; + case GAUDI2_EVENT_HDMA0_QM: + qid_base = GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0; + qman_base = mmDCORE0_EDMA0_QM_BASE; + snprintf(desc, ARRAY_SIZE(desc), "DCORE0_EDMA0_QM"); + break; + case GAUDI2_EVENT_HDMA1_QM: + qid_base = GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0; + qman_base = mmDCORE0_EDMA1_QM_BASE; + snprintf(desc, ARRAY_SIZE(desc), "DCORE0_EDMA1_QM"); + break; + case GAUDI2_EVENT_HDMA2_QM: + qid_base = GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0; + qman_base = mmDCORE1_EDMA0_QM_BASE; + snprintf(desc, ARRAY_SIZE(desc), "DCORE1_EDMA0_QM"); + break; + case GAUDI2_EVENT_HDMA3_QM: + qid_base = GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0; + qman_base = mmDCORE1_EDMA1_QM_BASE; + snprintf(desc, ARRAY_SIZE(desc), "DCORE1_EDMA1_QM"); + break; + case GAUDI2_EVENT_HDMA4_QM: + qid_base = GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0; + qman_base = mmDCORE2_EDMA0_QM_BASE; + snprintf(desc, ARRAY_SIZE(desc), "DCORE2_EDMA0_QM"); + break; + case GAUDI2_EVENT_HDMA5_QM: + qid_base = GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0; + qman_base = mmDCORE2_EDMA1_QM_BASE; + snprintf(desc, ARRAY_SIZE(desc), "DCORE2_EDMA1_QM"); + break; + case GAUDI2_EVENT_HDMA6_QM: + qid_base = GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0; + qman_base = mmDCORE3_EDMA0_QM_BASE; + snprintf(desc, ARRAY_SIZE(desc), "DCORE3_EDMA0_QM"); + break; + case GAUDI2_EVENT_HDMA7_QM: + qid_base = GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0; + qman_base = mmDCORE3_EDMA1_QM_BASE; + snprintf(desc, ARRAY_SIZE(desc), "DCORE3_EDMA1_QM"); + break; + case GAUDI2_EVENT_PDMA0_QM: + qid_base = GAUDI2_QUEUE_ID_PDMA_0_0; + qman_base = mmPDMA0_QM_BASE; + snprintf(desc, ARRAY_SIZE(desc), "PDMA0_QM"); + break; + case GAUDI2_EVENT_PDMA1_QM: + qid_base = GAUDI2_QUEUE_ID_PDMA_1_0; + qman_base = mmPDMA1_QM_BASE; + snprintf(desc, ARRAY_SIZE(desc), "PDMA1_QM"); + break; + case GAUDI2_EVENT_ROTATOR0_ROT0_QM: + qid_base = GAUDI2_QUEUE_ID_ROT_0_0; + qman_base = mmROT0_QM_BASE; + snprintf(desc, ARRAY_SIZE(desc), "ROTATOR0_QM"); + break; + case GAUDI2_EVENT_ROTATOR1_ROT1_QM: + qid_base = GAUDI2_QUEUE_ID_ROT_1_0; + qman_base = mmROT1_QM_BASE; + snprintf(desc, ARRAY_SIZE(desc), "ROTATOR1_QM"); + break; + default: + return; + } + + gaudi2_handle_qman_err_generic(hdev, desc, qman_base, qid_base); + + /* Handle EDMA QM SEI here because there is no AXI error response event for EDMA */ + if (event_type >= GAUDI2_EVENT_HDMA2_QM && event_type <= GAUDI2_EVENT_HDMA5_QM) + _gaudi2_handle_qm_sei_err(hdev, qman_base); +} + +static void gaudi2_handle_arc_farm_sei_err(struct hl_device *hdev) +{ + u32 i, sts_val, sts_clr_val = 0; + + sts_val = RREG32(mmARC_FARM_ARC0_AUX_ARC_SEI_INTR_STS); + + for (i = 0 ; i < GAUDI2_NUM_OF_ARC_SEI_ERR_CAUSE ; i++) { + if (sts_val & BIT(i)) { + dev_err_ratelimited(hdev->dev, "ARC SEI. err cause: %s\n", + gaudi2_arc_sei_error_cause[i]); + sts_clr_val |= BIT(i); + } + } + + WREG32(mmARC_FARM_ARC0_AUX_ARC_SEI_INTR_CLR, sts_clr_val); +} + +static void gaudi2_handle_cpu_sei_err(struct hl_device *hdev) +{ + u32 i, sts_val, sts_clr_val = 0; + + sts_val = RREG32(mmCPU_IF_CPU_SEI_INTR_STS); + + for (i = 0 ; i < GAUDI2_NUM_OF_CPU_SEI_ERR_CAUSE ; i++) { + if (sts_val & BIT(i)) { + dev_err_ratelimited(hdev->dev, "CPU SEI. err cause: %s\n", + gaudi2_cpu_sei_error_cause[i]); + sts_clr_val |= BIT(i); + } + } + + WREG32(mmCPU_IF_CPU_SEI_INTR_CLR, sts_clr_val); +} + +static void gaudi2_handle_rot_err(struct hl_device *hdev, u8 rot_index, + struct hl_eq_razwi_with_intr_cause *razwi_with_intr_cause) +{ + u64 intr_cause_data = le64_to_cpu(razwi_with_intr_cause->intr_cause.intr_cause_data); + int i; + + for (i = 0 ; i < GAUDI2_NUM_OF_ROT_ERR_CAUSE ; i++) + if (intr_cause_data & BIT(i)) + dev_err_ratelimited(hdev->dev, "ROT%u. err cause: %s\n", + rot_index, guadi2_rot_error_cause[i]); + + /* check if RAZWI happened */ + gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_ROT, rot_index, 0, + &razwi_with_intr_cause->razwi_info); +} + +static void gaudi2_tpc_ack_interrupts(struct hl_device *hdev, u8 tpc_index, char *interrupt_name, + struct hl_eq_razwi_with_intr_cause *razwi_with_intr_cause) +{ + u64 intr_cause_data = le64_to_cpu(razwi_with_intr_cause->intr_cause.intr_cause_data); + int i; + + for (i = 0 ; i < GAUDI2_NUM_OF_TPC_INTR_CAUSE ; i++) + if (intr_cause_data & BIT(i)) + dev_err_ratelimited(hdev->dev, "TPC%d_%s interrupt cause: %s\n", + tpc_index, interrupt_name, gaudi2_tpc_interrupts_cause[i]); + + /* check if RAZWI happened */ + gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_TPC, tpc_index, 0, + &razwi_with_intr_cause->razwi_info); +} + +static void gaudi2_handle_dec_err(struct hl_device *hdev, u8 dec_index, const char *interrupt_name, + struct hl_eq_razwi_info *razwi_info) +{ + u32 sts_addr, sts_val, sts_clr_val = 0; + int i; + + if (dec_index < NUM_OF_VDEC_PER_DCORE * NUM_OF_DCORES) + /* DCORE DEC */ + sts_addr = mmDCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR + + DCORE_OFFSET * (dec_index / NUM_OF_DEC_PER_DCORE) + + DCORE_VDEC_OFFSET * (dec_index % NUM_OF_DEC_PER_DCORE); + else + /* PCIE DEC */ + sts_addr = mmPCIE_VDEC0_BRDG_CTRL_CAUSE_INTR + PCIE_VDEC_OFFSET * + (dec_index - NUM_OF_VDEC_PER_DCORE * NUM_OF_DCORES); + + sts_val = RREG32(sts_addr); + + for (i = 0 ; i < GAUDI2_NUM_OF_DEC_ERR_CAUSE ; i++) { + if (sts_val & BIT(i)) { + dev_err_ratelimited(hdev->dev, "DEC%u_%s err cause: %s\n", + dec_index, interrupt_name, gaudi2_dec_error_cause[i]); + sts_clr_val |= BIT(i); + } + } + + /* check if RAZWI happened */ + gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_DEC, dec_index, 0, razwi_info); + + /* Write 1 clear errors */ + WREG32(sts_addr, sts_clr_val); +} + +static void gaudi2_handle_mme_err(struct hl_device *hdev, u8 mme_index, const char *interrupt_name, + struct hl_eq_razwi_info *razwi_info) +{ + u32 sts_addr, sts_val, sts_clr_addr, sts_clr_val = 0; + int i; + + sts_addr = mmDCORE0_MME_CTRL_LO_INTR_CAUSE + DCORE_OFFSET * mme_index; + sts_clr_addr = mmDCORE0_MME_CTRL_LO_INTR_CLEAR + DCORE_OFFSET * mme_index; + + sts_val = RREG32(sts_addr); + + for (i = 0 ; i < GAUDI2_NUM_OF_MME_ERR_CAUSE ; i++) { + if (sts_val & BIT(i)) { + dev_err_ratelimited(hdev->dev, "MME%u_%s err cause: %s\n", + mme_index, interrupt_name, guadi2_mme_error_cause[i]); + sts_clr_val |= BIT(i); + } + } + + /* check if RAZWI happened */ + for (i = MME_WRITE ; i < MME_INITIATORS_MAX ; i++) + gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_MME, mme_index, i, razwi_info); + + WREG32(sts_clr_addr, sts_clr_val); +} + +static void gaudi2_handle_mme_sbte_err(struct hl_device *hdev, u8 mme_index, u8 sbte_index, + u64 intr_cause_data) +{ + int i; + + for (i = 0 ; i < GAUDI2_NUM_OF_MME_SBTE_ERR_CAUSE ; i++) + if (intr_cause_data & BIT(i)) + dev_err_ratelimited(hdev->dev, "MME%uSBTE%u_AXI_ERR_RSP err cause: %s\n", + mme_index, sbte_index, guadi2_mme_sbte_error_cause[i]); +} + +static void gaudi2_handle_mme_wap_err(struct hl_device *hdev, u8 mme_index, + struct hl_eq_razwi_info *razwi_info) +{ + u32 sts_addr, sts_val, sts_clr_addr, sts_clr_val = 0; + int i; + + sts_addr = mmDCORE0_MME_ACC_INTR_CAUSE + DCORE_OFFSET * mme_index; + sts_clr_addr = mmDCORE0_MME_ACC_INTR_CLEAR + DCORE_OFFSET * mme_index; + + sts_val = RREG32(sts_addr); + + for (i = 0 ; i < GAUDI2_NUM_OF_MME_WAP_ERR_CAUSE ; i++) { + if (sts_val & BIT(i)) { + dev_err_ratelimited(hdev->dev, + "MME%u_WAP_SOURCE_RESULT_INVALID err cause: %s\n", + mme_index, guadi2_mme_wap_error_cause[i]); + sts_clr_val |= BIT(i); + } + } + + /* check if RAZWI happened on WAP0/1 */ + gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_MME, mme_index, MME_WAP0, razwi_info); + gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_MME, mme_index, MME_WAP1, razwi_info); + + WREG32(sts_clr_addr, sts_clr_val); +} + +static void gaudi2_handle_kdma_core_event(struct hl_device *hdev, u64 intr_cause_data) +{ + int i; + + /* If an AXI read or write error is received, an error is reported and + * interrupt message is sent. Due to an HW errata, when reading the cause + * register of the KDMA engine, the reported error is always HBW even if + * the actual error caused by a LBW KDMA transaction. + */ + for (i = 0 ; i < GAUDI2_NUM_OF_DMA_CORE_INTR_CAUSE ; i++) + if (intr_cause_data & BIT(i)) + dev_err_ratelimited(hdev->dev, "kdma core err cause: %s\n", + gaudi2_kdma_core_interrupts_cause[i]); +} + +static void gaudi2_handle_dma_core_event(struct hl_device *hdev, u64 intr_cause_data) +{ + int i; + + for (i = 0 ; i < GAUDI2_NUM_OF_DMA_CORE_INTR_CAUSE ; i++) + if (intr_cause_data & BIT(i)) + dev_err_ratelimited(hdev->dev, "dma core err cause: %s\n", + gaudi2_dma_core_interrupts_cause[i]); +} + +static void gaudi2_print_pcie_addr_dec_info(struct hl_device *hdev, u64 intr_cause_data) +{ + int i; + + for (i = 0 ; i < GAUDI2_NUM_OF_PCIE_ADDR_DEC_ERR_CAUSE; i++) + if (intr_cause_data & BIT_ULL(i)) + dev_err_ratelimited(hdev->dev, "PCIE ADDR DEC Error: %s\n", + gaudi2_pcie_addr_dec_error_cause[i]); +} + +static void gaudi2_handle_pif_fatal(struct hl_device *hdev, u64 intr_cause_data) + +{ + int i; + + for (i = 0 ; i < GAUDI2_NUM_OF_PMMU_FATAL_ERR_CAUSE ; i++) { + if (intr_cause_data & BIT_ULL(i)) + dev_err_ratelimited(hdev->dev, "PMMU PIF err cause: %s\n", + gaudi2_pmmu_fatal_interrupts_cause[i]); + } +} + +static void gaudi2_handle_hif_fatal(struct hl_device *hdev, u16 event_type, u64 intr_cause_data) +{ + u32 dcore_id, hif_id; + int i; + + dcore_id = (event_type - GAUDI2_EVENT_HIF0_FATAL) / 4; + hif_id = (event_type - GAUDI2_EVENT_HIF0_FATAL) % 4; + + for (i = 0 ; i < GAUDI2_NUM_OF_HIF_FATAL_ERR_CAUSE ; i++) { + if (intr_cause_data & BIT_ULL(i)) + dev_err_ratelimited(hdev->dev, "DCORE%u_HIF%u: %s\n", dcore_id, hif_id, + gaudi2_hif_fatal_interrupts_cause[i]); + } +} + +static void gaudi2_handle_page_error(struct hl_device *hdev, u64 mmu_base, bool is_pmmu) +{ + u32 valid, val; + u64 addr; + + valid = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID)); + + if (!(valid & DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_PAGE_ERR_VALID_ENTRY_MASK)) + return; + + val = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE)); + addr = val & DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_63_32_MASK; + addr <<= 32; + addr |= RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA)); + + dev_err_ratelimited(hdev->dev, "%s page fault on va 0x%llx\n", + is_pmmu ? "PMMU" : "HMMU", addr); + + WREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE), 0); +} + +static void gaudi2_handle_access_error(struct hl_device *hdev, u64 mmu_base, bool is_pmmu) +{ + u32 valid, val; + u64 addr; + + valid = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID)); + + if (!(valid & DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_ACCESS_ERR_VALID_ENTRY_MASK)) + return; + + val = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE)); + addr = val & DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_63_32_MASK; + addr <<= 32; + addr |= RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA)); + + dev_err_ratelimited(hdev->dev, "%s access error on va 0x%llx\n", + is_pmmu ? "PMMU" : "HMMU", addr); + WREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE), 0); +} + +static void gaudi2_handle_mmu_spi_sei_generic(struct hl_device *hdev, const char *mmu_name, + u64 mmu_base, bool is_pmmu) +{ + u32 spi_sei_cause, interrupt_clr = 0x0; + int i; + + spi_sei_cause = RREG32(mmu_base + MMU_SPI_SEI_CAUSE_OFFSET); + + for (i = 0 ; i < GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE ; i++) { + if (spi_sei_cause & BIT(i)) { + dev_err_ratelimited(hdev->dev, "%s SPI_SEI ERR. err cause: %s\n", + mmu_name, gaudi2_mmu_spi_sei[i].cause); + + if (i == 0) + gaudi2_handle_page_error(hdev, mmu_base, is_pmmu); + else if (i == 1) + gaudi2_handle_access_error(hdev, mmu_base, is_pmmu); + + if (gaudi2_mmu_spi_sei[i].clear_bit >= 0) + interrupt_clr |= BIT(gaudi2_mmu_spi_sei[i].clear_bit); + } + } + + /* Clear cause */ + WREG32_AND(mmu_base + MMU_SPI_SEI_CAUSE_OFFSET, ~spi_sei_cause); + + /* Clear interrupt */ + WREG32(mmu_base + MMU_INTERRUPT_CLR_OFFSET, interrupt_clr); +} + +static bool gaudi2_handle_sm_err(struct hl_device *hdev, u8 sm_index) +{ + u32 sei_cause_addr, sei_cause_val, sei_cause_cause, sei_cause_log; + u32 cq_intr_addr, cq_intr_val, cq_intr_queue_index; + bool reset = true; + int i; + + sei_cause_addr = mmDCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE + DCORE_OFFSET * sm_index; + cq_intr_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_INTR + DCORE_OFFSET * sm_index; + + sei_cause_val = RREG32(sei_cause_addr); + sei_cause_cause = FIELD_GET(DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE_CAUSE_MASK, sei_cause_val); + cq_intr_val = RREG32(cq_intr_addr); + + /* SEI interrupt */ + if (sei_cause_cause) { + /* There are corresponding SEI_CAUSE_log bits for every SEI_CAUSE_cause bit */ + sei_cause_log = FIELD_GET(DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE_LOG_MASK, + sei_cause_val); + + for (i = 0 ; i < GAUDI2_NUM_OF_SM_SEI_ERR_CAUSE ; i++) { + if (!(sei_cause_cause & BIT(i))) + continue; + + dev_err_ratelimited(hdev->dev, "SM%u SEI ERR. err cause: %s. %s: 0x%X\n", + sm_index, + gaudi2_sm_sei_cause[i].cause_name, + gaudi2_sm_sei_cause[i].log_name, + sei_cause_log & gaudi2_sm_sei_cause[i].log_mask); + + /* Due to a potential H/W issue, do not reset upon BRESP errors */ + if (i == 2) + reset = false; + break; + } + + /* Clear SM_SEI_CAUSE */ + WREG32(sei_cause_addr, 0); + } + + /* CQ interrupt */ + if (cq_intr_val & DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_SEC_INTR_MASK) { + cq_intr_queue_index = + FIELD_GET(DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_INTR_QUEUE_INDEX_MASK, + cq_intr_val); + + dev_err_ratelimited(hdev->dev, "SM%u err. err cause: CQ_INTR. queue index: %u\n", + sm_index, cq_intr_queue_index); + + /* Clear CQ_INTR */ + WREG32(cq_intr_addr, 0); + } + + return reset; +} + +static void gaudi2_handle_mmu_spi_sei_err(struct hl_device *hdev, u16 event_type) +{ + bool is_pmmu = false; + char desc[32]; + u64 mmu_base; + u8 index; + + switch (event_type) { + case GAUDI2_EVENT_HMMU0_PAGE_FAULT_OR_WR_PERM ... GAUDI2_EVENT_HMMU3_SECURITY_ERROR: + index = (event_type - GAUDI2_EVENT_HMMU0_PAGE_FAULT_OR_WR_PERM) / 3; + mmu_base = mmDCORE0_HMMU0_MMU_BASE + index * DCORE_HMMU_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "DCORE0_HMMU%d", index); + break; + case GAUDI2_EVENT_HMMU_0_AXI_ERR_RSP ... GAUDI2_EVENT_HMMU_3_AXI_ERR_RSP: + index = (event_type - GAUDI2_EVENT_HMMU_0_AXI_ERR_RSP); + mmu_base = mmDCORE0_HMMU0_MMU_BASE + index * DCORE_HMMU_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "DCORE0_HMMU%d", index); + break; + case GAUDI2_EVENT_HMMU8_PAGE_FAULT_WR_PERM ... GAUDI2_EVENT_HMMU11_SECURITY_ERROR: + index = (event_type - GAUDI2_EVENT_HMMU8_PAGE_FAULT_WR_PERM) / 3; + mmu_base = mmDCORE1_HMMU0_MMU_BASE + index * DCORE_HMMU_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "DCORE1_HMMU%d", index); + break; + case GAUDI2_EVENT_HMMU_8_AXI_ERR_RSP ... GAUDI2_EVENT_HMMU_11_AXI_ERR_RSP: + index = (event_type - GAUDI2_EVENT_HMMU_8_AXI_ERR_RSP); + mmu_base = mmDCORE1_HMMU0_MMU_BASE + index * DCORE_HMMU_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "DCORE1_HMMU%d", index); + break; + case GAUDI2_EVENT_HMMU7_PAGE_FAULT_WR_PERM ... GAUDI2_EVENT_HMMU4_SECURITY_ERROR: + index = (event_type - GAUDI2_EVENT_HMMU7_PAGE_FAULT_WR_PERM) / 3; + mmu_base = mmDCORE2_HMMU0_MMU_BASE + index * DCORE_HMMU_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "DCORE2_HMMU%d", index); + break; + case GAUDI2_EVENT_HMMU_7_AXI_ERR_RSP ... GAUDI2_EVENT_HMMU_4_AXI_ERR_RSP: + index = (event_type - GAUDI2_EVENT_HMMU_7_AXI_ERR_RSP); + mmu_base = mmDCORE2_HMMU0_MMU_BASE + index * DCORE_HMMU_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "DCORE2_HMMU%d", index); + break; + case GAUDI2_EVENT_HMMU15_PAGE_FAULT_WR_PERM ... GAUDI2_EVENT_HMMU12_SECURITY_ERROR: + index = (event_type - GAUDI2_EVENT_HMMU15_PAGE_FAULT_WR_PERM) / 3; + mmu_base = mmDCORE3_HMMU0_MMU_BASE + index * DCORE_HMMU_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "DCORE3_HMMU%d", index); + break; + case GAUDI2_EVENT_HMMU_15_AXI_ERR_RSP ... GAUDI2_EVENT_HMMU_12_AXI_ERR_RSP: + index = (event_type - GAUDI2_EVENT_HMMU_15_AXI_ERR_RSP); + mmu_base = mmDCORE3_HMMU0_MMU_BASE + index * DCORE_HMMU_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "DCORE3_HMMU%d", index); + break; + case GAUDI2_EVENT_PMMU0_PAGE_FAULT_WR_PERM ... GAUDI2_EVENT_PMMU0_SECURITY_ERROR: + case GAUDI2_EVENT_PMMU_AXI_ERR_RSP_0: + is_pmmu = true; + mmu_base = mmPMMU_HBW_MMU_BASE; + snprintf(desc, ARRAY_SIZE(desc), "PMMU"); + break; + default: + return; + } + + gaudi2_handle_mmu_spi_sei_generic(hdev, desc, mmu_base, is_pmmu); +} + + +/* returns true if hard reset is required (ECC DERR or Read parity), false otherwise (ECC SERR) */ +static bool gaudi2_hbm_sei_handle_read_err(struct hl_device *hdev, + struct hl_eq_hbm_sei_read_err_intr_info *rd_err_data, u32 err_cnt) +{ + u32 addr, beat, beat_shift; + bool rc = false; + + dev_err_ratelimited(hdev->dev, + "READ ERROR count: ECC SERR: %d, ECC DERR: %d, RD_PARITY: %d\n", + FIELD_GET(HBM_ECC_SERR_CNTR_MASK, err_cnt), + FIELD_GET(HBM_ECC_DERR_CNTR_MASK, err_cnt), + FIELD_GET(HBM_RD_PARITY_CNTR_MASK, err_cnt)); + + addr = le32_to_cpu(rd_err_data->dbg_rd_err_addr.rd_addr_val); + dev_err_ratelimited(hdev->dev, + "READ ERROR address: sid(%u), bg(%u), ba(%u), col(%u), row(%u)\n", + FIELD_GET(HBM_RD_ADDR_SID_MASK, addr), + FIELD_GET(HBM_RD_ADDR_BG_MASK, addr), + FIELD_GET(HBM_RD_ADDR_BA_MASK, addr), + FIELD_GET(HBM_RD_ADDR_COL_MASK, addr), + FIELD_GET(HBM_RD_ADDR_ROW_MASK, addr)); + + /* For each beat (RDQS edge), look for possible errors and print relevant info */ + for (beat = 0 ; beat < 4 ; beat++) { + if (le32_to_cpu(rd_err_data->dbg_rd_err_misc) & + (HBM_RD_ERR_SERR_BEAT0_MASK << beat)) + dev_err_ratelimited(hdev->dev, "Beat%d ECC SERR: DM: %#x, Syndrome: %#x\n", + beat, + le32_to_cpu(rd_err_data->dbg_rd_err_dm), + le32_to_cpu(rd_err_data->dbg_rd_err_syndrome)); + + if (le32_to_cpu(rd_err_data->dbg_rd_err_misc) & + (HBM_RD_ERR_DERR_BEAT0_MASK << beat)) { + dev_err_ratelimited(hdev->dev, "Beat%d ECC DERR: DM: %#x, Syndrome: %#x\n", + beat, + le32_to_cpu(rd_err_data->dbg_rd_err_dm), + le32_to_cpu(rd_err_data->dbg_rd_err_syndrome)); + rc |= true; + } + + beat_shift = beat * HBM_RD_ERR_BEAT_SHIFT; + if (le32_to_cpu(rd_err_data->dbg_rd_err_misc) & + (HBM_RD_ERR_PAR_ERR_BEAT0_MASK << beat_shift)) { + dev_err_ratelimited(hdev->dev, + "Beat%d read PARITY: DM: %#x, PAR data: %#x\n", + beat, + le32_to_cpu(rd_err_data->dbg_rd_err_dm), + (le32_to_cpu(rd_err_data->dbg_rd_err_misc) & + (HBM_RD_ERR_PAR_DATA_BEAT0_MASK << beat_shift)) >> + (HBM_RD_ERR_PAR_DATA_BEAT0_SHIFT + beat_shift)); + rc |= true; + } + + dev_err_ratelimited(hdev->dev, "Beat%d DQ data:\n", beat); + dev_err_ratelimited(hdev->dev, "\t0x%08x\n", + le32_to_cpu(rd_err_data->dbg_rd_err_data[beat * 2])); + dev_err_ratelimited(hdev->dev, "\t0x%08x\n", + le32_to_cpu(rd_err_data->dbg_rd_err_data[beat * 2 + 1])); + } + + return rc; +} + +static void gaudi2_hbm_sei_print_wr_par_info(struct hl_device *hdev, + struct hl_eq_hbm_sei_wr_par_intr_info *wr_par_err_data, u32 err_cnt) +{ + struct hbm_sei_wr_cmd_address *wr_cmd_addr = wr_par_err_data->dbg_last_wr_cmds; + u32 i, curr_addr, derr = wr_par_err_data->dbg_derr; + + dev_err_ratelimited(hdev->dev, "WRITE PARITY ERROR count: %d\n", err_cnt); + + dev_err_ratelimited(hdev->dev, "CK-0 DERR: 0x%02x, CK-1 DERR: 0x%02x\n", + derr & 0x3, derr & 0xc); + + /* JIRA H6-3286 - the following prints may not be valid */ + dev_err_ratelimited(hdev->dev, "Last latched write commands addresses:\n"); + for (i = 0 ; i < HBM_WR_PAR_CMD_LIFO_LEN ; i++) { + curr_addr = le32_to_cpu(wr_cmd_addr[i].dbg_wr_cmd_addr); + dev_err_ratelimited(hdev->dev, + "\twrite cmd[%u]: Address: SID(%u) BG(%u) BA(%u) COL(%u).\n", + i, + FIELD_GET(WR_PAR_LAST_CMD_SID_MASK, curr_addr), + FIELD_GET(WR_PAR_LAST_CMD_BG_MASK, curr_addr), + FIELD_GET(WR_PAR_LAST_CMD_BA_MASK, curr_addr), + FIELD_GET(WR_PAR_LAST_CMD_COL_MASK, curr_addr)); + } +} + +static void gaudi2_hbm_sei_print_ca_par_info(struct hl_device *hdev, + struct hl_eq_hbm_sei_ca_par_intr_info *ca_par_err_data, u32 err_cnt) +{ + __le32 *col_cmd = ca_par_err_data->dbg_col; + __le16 *row_cmd = ca_par_err_data->dbg_row; + u32 i; + + dev_err_ratelimited(hdev->dev, "CA ERROR count: %d\n", err_cnt); + + dev_err_ratelimited(hdev->dev, "Last latched C&R bus commands:\n"); + for (i = 0 ; i < HBM_CA_ERR_CMD_LIFO_LEN ; i++) + dev_err_ratelimited(hdev->dev, "cmd%u: ROW(0x%04x) COL(0x%05x)\n", i, + le16_to_cpu(row_cmd[i]) & (u16)GENMASK(13, 0), + le32_to_cpu(col_cmd[i]) & (u32)GENMASK(17, 0)); +} + +/* Returns true if hard reset is needed or false otherwise */ +static bool gaudi2_handle_hbm_mc_sei_err(struct hl_device *hdev, u16 event_type, + struct hl_eq_hbm_sei_data *sei_data) +{ + bool require_hard_reset = false; + u32 hbm_id, mc_id, cause_idx; + + hbm_id = (event_type - GAUDI2_EVENT_HBM0_MC0_SEI_SEVERE) / 4; + mc_id = ((event_type - GAUDI2_EVENT_HBM0_MC0_SEI_SEVERE) / 2) % 2; + + cause_idx = sei_data->hdr.sei_cause; + if (cause_idx > GAUDI2_NUM_OF_HBM_SEI_CAUSE - 1) { + dev_err_ratelimited(hdev->dev, "Invalid HBM SEI event cause (%d) provided by FW\n", + cause_idx); + return true; + } + + dev_err_ratelimited(hdev->dev, + "System Error Interrupt - HBM(%u) MC(%u) MC_CH(%u) MC_PC(%u). Critical(%u). Error cause: %s\n", + hbm_id, mc_id, sei_data->hdr.mc_channel, sei_data->hdr.mc_pseudo_channel, + sei_data->hdr.is_critical, hbm_mc_sei_cause[cause_idx]); + + /* Print error-specific info */ + switch (cause_idx) { + case HBM_SEI_CATTRIP: + require_hard_reset = true; + break; + + case HBM_SEI_CMD_PARITY_EVEN: + gaudi2_hbm_sei_print_ca_par_info(hdev, &sei_data->ca_parity_even_info, + le32_to_cpu(sei_data->hdr.cnt)); + require_hard_reset = true; + break; + + case HBM_SEI_CMD_PARITY_ODD: + gaudi2_hbm_sei_print_ca_par_info(hdev, &sei_data->ca_parity_odd_info, + le32_to_cpu(sei_data->hdr.cnt)); + require_hard_reset = true; + break; + + case HBM_SEI_WRITE_DATA_PARITY_ERR: + gaudi2_hbm_sei_print_wr_par_info(hdev, &sei_data->wr_parity_info, + le32_to_cpu(sei_data->hdr.cnt)); + require_hard_reset = true; + break; + + case HBM_SEI_READ_ERR: + /* Unlike other SEI events, read error requires further processing of the + * raw data in order to determine the root cause. + */ + require_hard_reset = gaudi2_hbm_sei_handle_read_err(hdev, + &sei_data->read_err_info, + le32_to_cpu(sei_data->hdr.cnt)); + break; + + default: + break; + } + + require_hard_reset |= !!sei_data->hdr.is_critical; + + return require_hard_reset; +} + +static void gaudi2_handle_hbm_cattrip(struct hl_device *hdev, u64 intr_cause_data) +{ + dev_err(hdev->dev, + "HBM catastrophic temperature error (CATTRIP) cause %#llx\n", + intr_cause_data); +} + +static void gaudi2_handle_hbm_mc_spi(struct hl_device *hdev, u64 intr_cause_data) +{ + u32 i; + + for (i = 0 ; i < GAUDI2_NUM_OF_HBM_MC_SPI_CAUSE ; i++) + if (intr_cause_data & hbm_mc_spi[i].mask) + dev_dbg(hdev->dev, "HBM spi event: notification cause(%s)\n", + hbm_mc_spi[i].cause); +} + +static void gaudi2_print_clk_change_info(struct hl_device *hdev, u16 event_type) +{ + ktime_t zero_time = ktime_set(0, 0); + + mutex_lock(&hdev->clk_throttling.lock); + + switch (event_type) { + case GAUDI2_EVENT_CPU_FIX_POWER_ENV_S: + hdev->clk_throttling.current_reason |= HL_CLK_THROTTLE_POWER; + hdev->clk_throttling.aggregated_reason |= HL_CLK_THROTTLE_POWER; + hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].start = ktime_get(); + hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].end = zero_time; + dev_info_ratelimited(hdev->dev, "Clock throttling due to power consumption\n"); + break; + + case GAUDI2_EVENT_CPU_FIX_POWER_ENV_E: + hdev->clk_throttling.current_reason &= ~HL_CLK_THROTTLE_POWER; + hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].end = ktime_get(); + dev_info_ratelimited(hdev->dev, "Power envelop is safe, back to optimal clock\n"); + break; + + case GAUDI2_EVENT_CPU_FIX_THERMAL_ENV_S: + hdev->clk_throttling.current_reason |= HL_CLK_THROTTLE_THERMAL; + hdev->clk_throttling.aggregated_reason |= HL_CLK_THROTTLE_THERMAL; + hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].start = ktime_get(); + hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].end = zero_time; + dev_info_ratelimited(hdev->dev, "Clock throttling due to overheating\n"); + break; + + case GAUDI2_EVENT_CPU_FIX_THERMAL_ENV_E: + hdev->clk_throttling.current_reason &= ~HL_CLK_THROTTLE_THERMAL; + hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].end = ktime_get(); + dev_info_ratelimited(hdev->dev, "Thermal envelop is safe, back to optimal clock\n"); + break; + + default: + dev_err(hdev->dev, "Received invalid clock change event %d\n", event_type); + break; + } + + mutex_unlock(&hdev->clk_throttling.lock); +} + +static void gaudi2_print_out_of_sync_info(struct hl_device *hdev, + struct cpucp_pkt_sync_err *sync_err) +{ + struct hl_hw_queue *q = &hdev->kernel_queues[GAUDI2_QUEUE_ID_CPU_PQ]; + + dev_err(hdev->dev, "Out of sync with FW, FW: pi=%u, ci=%u, LKD: pi=%u, ci=%u\n", + sync_err->pi, sync_err->ci, q->pi, atomic_read(&q->ci)); +} + +static void gaudi2_handle_pcie_p2p_msix(struct hl_device *hdev) +{ + u32 p2p_intr, msix_gw_intr; + + p2p_intr = RREG32(mmPCIE_WRAP_P2P_INTR); + msix_gw_intr = RREG32(mmPCIE_WRAP_MSIX_GW_INTR); + + if (p2p_intr) { + dev_err_ratelimited(hdev->dev, + "pcie p2p transaction terminated due to security, req_id(0x%x)\n", + RREG32(mmPCIE_WRAP_P2P_REQ_ID)); + + WREG32(mmPCIE_WRAP_P2P_INTR, 0x1); + } + + if (msix_gw_intr) { + dev_err_ratelimited(hdev->dev, + "pcie msi-x gen denied due to vector num check failure, vec(0x%X)\n", + RREG32(mmPCIE_WRAP_MSIX_GW_VEC)); + + WREG32(mmPCIE_WRAP_MSIX_GW_INTR, 0x1); + } +} + +static void gaudi2_handle_pcie_drain(struct hl_device *hdev, + struct hl_eq_pcie_drain_ind_data *drain_data) +{ + u64 lbw_rd, lbw_wr, hbw_rd, hbw_wr, cause; + + cause = le64_to_cpu(drain_data->intr_cause.intr_cause_data); + lbw_rd = le64_to_cpu(drain_data->drain_rd_addr_lbw); + lbw_wr = le64_to_cpu(drain_data->drain_wr_addr_lbw); + hbw_rd = le64_to_cpu(drain_data->drain_rd_addr_hbw); + hbw_wr = le64_to_cpu(drain_data->drain_wr_addr_hbw); + + if (cause & BIT_ULL(0)) + dev_err_ratelimited(hdev->dev, + "PCIE AXI drain LBW completed, read_err %u, write_err %u\n", + !!lbw_rd, !!lbw_wr); + + if (cause & BIT_ULL(1)) + dev_err_ratelimited(hdev->dev, + "PCIE AXI drain HBW completed, raddr %#llx, waddr %#llx\n", + hbw_rd, hbw_wr); +} + +static void gaudi2_handle_psoc_drain(struct hl_device *hdev, u64 intr_cause_data) +{ + int i; + + for (i = 0 ; i < GAUDI2_NUM_OF_AXI_DRAIN_ERR_CAUSE ; i++) { + if (intr_cause_data & BIT_ULL(i)) + dev_err_ratelimited(hdev->dev, "PSOC %s completed\n", + gaudi2_psoc_axi_drain_interrupts_cause[i]); + } +} + +static void gaudi2_print_cpu_pkt_failure_info(struct hl_device *hdev, + struct cpucp_pkt_sync_err *sync_err) +{ + struct hl_hw_queue *q = &hdev->kernel_queues[GAUDI2_QUEUE_ID_CPU_PQ]; + + dev_warn(hdev->dev, + "FW reported sanity check failure, FW: pi=%u, ci=%u, LKD: pi=%u, ci=%u\n", + sync_err->pi, sync_err->ci, q->pi, atomic_read(&q->ci)); +} + +static void hl_arc_event_handle(struct hl_device *hdev, + struct hl_eq_engine_arc_intr_data *data) +{ + struct hl_engine_arc_dccm_queue_full_irq *q; + u32 intr_type, engine_id; + u64 payload; + + intr_type = le32_to_cpu(data->intr_type); + engine_id = le32_to_cpu(data->engine_id); + payload = le64_to_cpu(data->payload); + + switch (intr_type) { + case ENGINE_ARC_DCCM_QUEUE_FULL_IRQ: + q = (struct hl_engine_arc_dccm_queue_full_irq *) &payload; + + dev_err_ratelimited(hdev->dev, + "ARC DCCM Full event: EngId: %u, Intr_type: %u, Qidx: %u\n", + engine_id, intr_type, q->queue_index); + break; + default: + dev_err_ratelimited(hdev->dev, "Unknown ARC event type\n"); + } +} + +static void gaudi2_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry) +{ + u32 ctl, reset_flags = HL_DRV_RESET_HARD | HL_DRV_RESET_DELAY; + struct gaudi2_device *gaudi2 = hdev->asic_specific; + bool reset_required = false, skip_reset = false; + int index, sbte_index; + u16 event_type; + + ctl = le32_to_cpu(eq_entry->hdr.ctl); + event_type = ((ctl & EQ_CTL_EVENT_TYPE_MASK) >> EQ_CTL_EVENT_TYPE_SHIFT); + + if (event_type >= GAUDI2_EVENT_SIZE) { + dev_err(hdev->dev, "Event type %u exceeds maximum of %u", + event_type, GAUDI2_EVENT_SIZE - 1); + return; + } + + gaudi2->events_stat[event_type]++; + gaudi2->events_stat_aggregate[event_type]++; + + gaudi2_print_irq_info(hdev, event_type); + + switch (event_type) { + case GAUDI2_EVENT_PCIE_CORE_SERR ... GAUDI2_EVENT_ARC0_ECC_DERR: + fallthrough; + case GAUDI2_EVENT_ROTATOR0_SERR ... GAUDI2_EVENT_ROTATOR1_DERR: + reset_flags |= HL_DRV_RESET_FW_FATAL_ERR; + reset_required = gaudi2_handle_ecc_event(hdev, event_type, &eq_entry->ecc_data); + break; + + case GAUDI2_EVENT_TPC0_QM ... GAUDI2_EVENT_PDMA1_QM: + fallthrough; + case GAUDI2_EVENT_ROTATOR0_ROT0_QM ... GAUDI2_EVENT_ROTATOR1_ROT1_QM: + fallthrough; + case GAUDI2_EVENT_NIC0_QM0 ... GAUDI2_EVENT_NIC11_QM1: + gaudi2_handle_qman_err(hdev, event_type); + break; + + case GAUDI2_EVENT_ARC_AXI_ERROR_RESPONSE_0: + reset_flags |= HL_DRV_RESET_FW_FATAL_ERR; + gaudi2_handle_arc_farm_sei_err(hdev); + break; + + case GAUDI2_EVENT_CPU_AXI_ERR_RSP: + gaudi2_handle_cpu_sei_err(hdev); + break; + + case GAUDI2_EVENT_PDMA_CH0_AXI_ERR_RSP: + case GAUDI2_EVENT_PDMA_CH1_AXI_ERR_RSP: + reset_flags |= HL_DRV_RESET_FW_FATAL_ERR; + gaudi2_handle_qm_sei_err(hdev, event_type, &eq_entry->razwi_info); + break; + + case GAUDI2_EVENT_ROTATOR0_AXI_ERROR_RESPONSE: + case GAUDI2_EVENT_ROTATOR1_AXI_ERROR_RESPONSE: + index = event_type - GAUDI2_EVENT_ROTATOR0_AXI_ERROR_RESPONSE; + gaudi2_handle_rot_err(hdev, index, &eq_entry->razwi_with_intr_cause); + gaudi2_handle_qm_sei_err(hdev, event_type, NULL); + break; + + case GAUDI2_EVENT_TPC0_AXI_ERR_RSP ... GAUDI2_EVENT_TPC24_AXI_ERR_RSP: + index = event_type - GAUDI2_EVENT_TPC0_AXI_ERR_RSP; + gaudi2_tpc_ack_interrupts(hdev, index, "AXI_ERR_RSP", + &eq_entry->razwi_with_intr_cause); + gaudi2_handle_qm_sei_err(hdev, event_type, NULL); + break; + + case GAUDI2_EVENT_DEC0_AXI_ERR_RSPONSE ... GAUDI2_EVENT_DEC9_AXI_ERR_RSPONSE: + index = event_type - GAUDI2_EVENT_DEC0_AXI_ERR_RSPONSE; + gaudi2_handle_dec_err(hdev, index, "AXI_ERR_RESPONSE", &eq_entry->razwi_info); + break; + + case GAUDI2_EVENT_TPC0_KERNEL_ERR: + case GAUDI2_EVENT_TPC1_KERNEL_ERR: + case GAUDI2_EVENT_TPC2_KERNEL_ERR: + case GAUDI2_EVENT_TPC3_KERNEL_ERR: + case GAUDI2_EVENT_TPC4_KERNEL_ERR: + case GAUDI2_EVENT_TPC5_KERNEL_ERR: + case GAUDI2_EVENT_TPC6_KERNEL_ERR: + case GAUDI2_EVENT_TPC7_KERNEL_ERR: + case GAUDI2_EVENT_TPC8_KERNEL_ERR: + case GAUDI2_EVENT_TPC9_KERNEL_ERR: + case GAUDI2_EVENT_TPC10_KERNEL_ERR: + case GAUDI2_EVENT_TPC11_KERNEL_ERR: + case GAUDI2_EVENT_TPC12_KERNEL_ERR: + case GAUDI2_EVENT_TPC13_KERNEL_ERR: + case GAUDI2_EVENT_TPC14_KERNEL_ERR: + case GAUDI2_EVENT_TPC15_KERNEL_ERR: + case GAUDI2_EVENT_TPC16_KERNEL_ERR: + case GAUDI2_EVENT_TPC17_KERNEL_ERR: + case GAUDI2_EVENT_TPC18_KERNEL_ERR: + case GAUDI2_EVENT_TPC19_KERNEL_ERR: + case GAUDI2_EVENT_TPC20_KERNEL_ERR: + case GAUDI2_EVENT_TPC21_KERNEL_ERR: + case GAUDI2_EVENT_TPC22_KERNEL_ERR: + case GAUDI2_EVENT_TPC23_KERNEL_ERR: + case GAUDI2_EVENT_TPC24_KERNEL_ERR: + index = (event_type - GAUDI2_EVENT_TPC0_KERNEL_ERR) / + (GAUDI2_EVENT_TPC1_KERNEL_ERR - GAUDI2_EVENT_TPC0_KERNEL_ERR); + gaudi2_tpc_ack_interrupts(hdev, index, "KRN_ERR", &eq_entry->razwi_with_intr_cause); + break; + + case GAUDI2_EVENT_DEC0_SPI: + case GAUDI2_EVENT_DEC1_SPI: + case GAUDI2_EVENT_DEC2_SPI: + case GAUDI2_EVENT_DEC3_SPI: + case GAUDI2_EVENT_DEC4_SPI: + case GAUDI2_EVENT_DEC5_SPI: + case GAUDI2_EVENT_DEC6_SPI: + case GAUDI2_EVENT_DEC7_SPI: + case GAUDI2_EVENT_DEC8_SPI: + case GAUDI2_EVENT_DEC9_SPI: + index = (event_type - GAUDI2_EVENT_DEC0_SPI) / + (GAUDI2_EVENT_DEC1_SPI - GAUDI2_EVENT_DEC0_SPI); + gaudi2_handle_dec_err(hdev, index, "SPI", &eq_entry->razwi_info); + break; + + case GAUDI2_EVENT_MME0_CTRL_AXI_ERROR_RESPONSE: + case GAUDI2_EVENT_MME1_CTRL_AXI_ERROR_RESPONSE: + case GAUDI2_EVENT_MME2_CTRL_AXI_ERROR_RESPONSE: + case GAUDI2_EVENT_MME3_CTRL_AXI_ERROR_RESPONSE: + index = (event_type - GAUDI2_EVENT_MME0_CTRL_AXI_ERROR_RESPONSE) / + (GAUDI2_EVENT_MME1_CTRL_AXI_ERROR_RESPONSE - + GAUDI2_EVENT_MME0_CTRL_AXI_ERROR_RESPONSE); + gaudi2_handle_mme_err(hdev, index, + "CTRL_AXI_ERROR_RESPONSE", &eq_entry->razwi_info); + gaudi2_handle_qm_sei_err(hdev, event_type, NULL); + break; + + case GAUDI2_EVENT_MME0_QMAN_SW_ERROR: + case GAUDI2_EVENT_MME1_QMAN_SW_ERROR: + case GAUDI2_EVENT_MME2_QMAN_SW_ERROR: + case GAUDI2_EVENT_MME3_QMAN_SW_ERROR: + index = (event_type - GAUDI2_EVENT_MME0_QMAN_SW_ERROR) / + (GAUDI2_EVENT_MME1_QMAN_SW_ERROR - + GAUDI2_EVENT_MME0_QMAN_SW_ERROR); + gaudi2_handle_mme_err(hdev, index, "QMAN_SW_ERROR", &eq_entry->razwi_info); + break; + + case GAUDI2_EVENT_MME0_WAP_SOURCE_RESULT_INVALID: + case GAUDI2_EVENT_MME1_WAP_SOURCE_RESULT_INVALID: + case GAUDI2_EVENT_MME2_WAP_SOURCE_RESULT_INVALID: + case GAUDI2_EVENT_MME3_WAP_SOURCE_RESULT_INVALID: + index = (event_type - GAUDI2_EVENT_MME0_WAP_SOURCE_RESULT_INVALID) / + (GAUDI2_EVENT_MME1_WAP_SOURCE_RESULT_INVALID - + GAUDI2_EVENT_MME0_WAP_SOURCE_RESULT_INVALID); + gaudi2_handle_mme_wap_err(hdev, index, &eq_entry->razwi_info); + break; + + case GAUDI2_EVENT_KDMA_CH0_AXI_ERR_RSP: + case GAUDI2_EVENT_KDMA0_CORE: + gaudi2_handle_kdma_core_event(hdev, + le64_to_cpu(eq_entry->intr_cause.intr_cause_data)); + break; + + case GAUDI2_EVENT_HDMA2_CORE ... GAUDI2_EVENT_PDMA1_CORE: + gaudi2_handle_dma_core_event(hdev, + le64_to_cpu(eq_entry->intr_cause.intr_cause_data)); + break; + + case GAUDI2_EVENT_PCIE_ADDR_DEC_ERR: + gaudi2_print_pcie_addr_dec_info(hdev, + le64_to_cpu(eq_entry->intr_cause.intr_cause_data)); + break; + + case GAUDI2_EVENT_HMMU0_PAGE_FAULT_OR_WR_PERM ... GAUDI2_EVENT_HMMU12_SECURITY_ERROR: + case GAUDI2_EVENT_HMMU_0_AXI_ERR_RSP ... GAUDI2_EVENT_HMMU_12_AXI_ERR_RSP: + case GAUDI2_EVENT_PMMU0_PAGE_FAULT_WR_PERM ... GAUDI2_EVENT_PMMU0_SECURITY_ERROR: + case GAUDI2_EVENT_PMMU_AXI_ERR_RSP_0: + gaudi2_handle_mmu_spi_sei_err(hdev, event_type); + reset_flags |= HL_DRV_RESET_FW_FATAL_ERR; + break; + + case GAUDI2_EVENT_HIF0_FATAL ... GAUDI2_EVENT_HIF12_FATAL: + gaudi2_handle_hif_fatal(hdev, event_type, + le64_to_cpu(eq_entry->intr_cause.intr_cause_data)); + reset_flags |= HL_DRV_RESET_FW_FATAL_ERR; + break; + + case GAUDI2_EVENT_PMMU_FATAL_0: + gaudi2_handle_pif_fatal(hdev, + le64_to_cpu(eq_entry->intr_cause.intr_cause_data)); + reset_flags |= HL_DRV_RESET_FW_FATAL_ERR; + break; + + case GAUDI2_EVENT_PSOC63_RAZWI_OR_PID_MIN_MAX_INTERRUPT: + gaudi2_ack_psoc_razwi_event_handler(hdev); + break; + + case GAUDI2_EVENT_HBM0_MC0_SEI_SEVERE ... GAUDI2_EVENT_HBM5_MC1_SEI_NON_SEVERE: + if (gaudi2_handle_hbm_mc_sei_err(hdev, event_type, &eq_entry->sei_data)) { + reset_flags |= HL_DRV_RESET_FW_FATAL_ERR; + reset_required = true; + } + break; + + case GAUDI2_EVENT_HBM_CATTRIP_0 ... GAUDI2_EVENT_HBM_CATTRIP_5: + gaudi2_handle_hbm_cattrip(hdev, le64_to_cpu(eq_entry->intr_cause.intr_cause_data)); + break; + + case GAUDI2_EVENT_HBM0_MC0_SPI ... GAUDI2_EVENT_HBM5_MC1_SPI: + gaudi2_handle_hbm_mc_spi(hdev, le64_to_cpu(eq_entry->intr_cause.intr_cause_data)); + break; + + case GAUDI2_EVENT_PCIE_DRAIN_COMPLETE: + gaudi2_handle_pcie_drain(hdev, &eq_entry->pcie_drain_ind_data); + break; + + case GAUDI2_EVENT_PSOC59_RPM_ERROR_OR_DRAIN: + gaudi2_handle_psoc_drain(hdev, le64_to_cpu(eq_entry->intr_cause.intr_cause_data)); + break; + + case GAUDI2_EVENT_CPU_AXI_ECC: + reset_flags |= HL_DRV_RESET_FW_FATAL_ERR; + break; + case GAUDI2_EVENT_CPU_L2_RAM_ECC: + reset_flags |= HL_DRV_RESET_FW_FATAL_ERR; + break; + case GAUDI2_EVENT_MME0_SBTE0_AXI_ERR_RSP ... GAUDI2_EVENT_MME0_SBTE4_AXI_ERR_RSP: + case GAUDI2_EVENT_MME1_SBTE0_AXI_ERR_RSP ... GAUDI2_EVENT_MME1_SBTE4_AXI_ERR_RSP: + case GAUDI2_EVENT_MME2_SBTE0_AXI_ERR_RSP ... GAUDI2_EVENT_MME2_SBTE4_AXI_ERR_RSP: + case GAUDI2_EVENT_MME3_SBTE0_AXI_ERR_RSP ... GAUDI2_EVENT_MME3_SBTE4_AXI_ERR_RSP: + index = (event_type - GAUDI2_EVENT_MME0_SBTE0_AXI_ERR_RSP) / + (GAUDI2_EVENT_MME1_SBTE0_AXI_ERR_RSP - + GAUDI2_EVENT_MME0_SBTE0_AXI_ERR_RSP); + sbte_index = (event_type - GAUDI2_EVENT_MME0_SBTE0_AXI_ERR_RSP) % + (GAUDI2_EVENT_MME1_SBTE0_AXI_ERR_RSP - + GAUDI2_EVENT_MME0_SBTE0_AXI_ERR_RSP); + gaudi2_handle_mme_sbte_err(hdev, index, sbte_index, + le64_to_cpu(eq_entry->intr_cause.intr_cause_data)); + break; + case GAUDI2_EVENT_VM0_ALARM_A ... GAUDI2_EVENT_VM3_ALARM_B: + reset_flags |= HL_DRV_RESET_FW_FATAL_ERR; + break; + case GAUDI2_EVENT_PSOC_AXI_ERR_RSP: + case GAUDI2_EVENT_PSOC_PRSTN_FALL: + break; + case GAUDI2_EVENT_PCIE_APB_TIMEOUT: + reset_flags |= HL_DRV_RESET_FW_FATAL_ERR; + break; + case GAUDI2_EVENT_PCIE_FATAL_ERR: + break; + case GAUDI2_EVENT_TPC0_BMON_SPMU: + case GAUDI2_EVENT_TPC1_BMON_SPMU: + case GAUDI2_EVENT_TPC2_BMON_SPMU: + case GAUDI2_EVENT_TPC3_BMON_SPMU: + case GAUDI2_EVENT_TPC4_BMON_SPMU: + case GAUDI2_EVENT_TPC5_BMON_SPMU: + case GAUDI2_EVENT_TPC6_BMON_SPMU: + case GAUDI2_EVENT_TPC7_BMON_SPMU: + case GAUDI2_EVENT_TPC8_BMON_SPMU: + case GAUDI2_EVENT_TPC9_BMON_SPMU: + case GAUDI2_EVENT_TPC10_BMON_SPMU: + case GAUDI2_EVENT_TPC11_BMON_SPMU: + case GAUDI2_EVENT_TPC12_BMON_SPMU: + case GAUDI2_EVENT_TPC13_BMON_SPMU: + case GAUDI2_EVENT_TPC14_BMON_SPMU: + case GAUDI2_EVENT_TPC15_BMON_SPMU: + case GAUDI2_EVENT_TPC16_BMON_SPMU: + case GAUDI2_EVENT_TPC17_BMON_SPMU: + case GAUDI2_EVENT_TPC18_BMON_SPMU: + case GAUDI2_EVENT_TPC19_BMON_SPMU: + case GAUDI2_EVENT_TPC20_BMON_SPMU: + case GAUDI2_EVENT_TPC21_BMON_SPMU: + case GAUDI2_EVENT_TPC22_BMON_SPMU: + case GAUDI2_EVENT_TPC23_BMON_SPMU: + case GAUDI2_EVENT_TPC24_BMON_SPMU: + case GAUDI2_EVENT_MME0_CTRL_BMON_SPMU: + case GAUDI2_EVENT_MME0_SBTE_BMON_SPMU: + case GAUDI2_EVENT_MME0_WAP_BMON_SPMU: + case GAUDI2_EVENT_MME1_CTRL_BMON_SPMU: + case GAUDI2_EVENT_MME1_SBTE_BMON_SPMU: + case GAUDI2_EVENT_MME1_WAP_BMON_SPMU: + case GAUDI2_EVENT_MME2_CTRL_BMON_SPMU: + case GAUDI2_EVENT_MME2_SBTE_BMON_SPMU: + case GAUDI2_EVENT_MME2_WAP_BMON_SPMU: + case GAUDI2_EVENT_MME3_CTRL_BMON_SPMU: + case GAUDI2_EVENT_MME3_SBTE_BMON_SPMU: + case GAUDI2_EVENT_MME3_WAP_BMON_SPMU: + case GAUDI2_EVENT_HDMA2_BM_SPMU ... GAUDI2_EVENT_PDMA1_BM_SPMU: + fallthrough; + case GAUDI2_EVENT_DEC0_BMON_SPMU: + case GAUDI2_EVENT_DEC1_BMON_SPMU: + case GAUDI2_EVENT_DEC2_BMON_SPMU: + case GAUDI2_EVENT_DEC3_BMON_SPMU: + case GAUDI2_EVENT_DEC4_BMON_SPMU: + case GAUDI2_EVENT_DEC5_BMON_SPMU: + case GAUDI2_EVENT_DEC6_BMON_SPMU: + case GAUDI2_EVENT_DEC7_BMON_SPMU: + case GAUDI2_EVENT_DEC8_BMON_SPMU: + case GAUDI2_EVENT_DEC9_BMON_SPMU: + case GAUDI2_EVENT_ROTATOR0_BMON_SPMU ... GAUDI2_EVENT_SM3_BMON_SPMU: + break; + + case GAUDI2_EVENT_CPU_FIX_POWER_ENV_S: + case GAUDI2_EVENT_CPU_FIX_POWER_ENV_E: + case GAUDI2_EVENT_CPU_FIX_THERMAL_ENV_S: + case GAUDI2_EVENT_CPU_FIX_THERMAL_ENV_E: + gaudi2_print_clk_change_info(hdev, event_type); + break; + + case GAUDI2_EVENT_CPU_PKT_QUEUE_OUT_SYNC: + gaudi2_print_out_of_sync_info(hdev, &eq_entry->pkt_sync_err); + break; + + case GAUDI2_EVENT_PCIE_FLR_REQUESTED: + /* Do nothing- FW will handle it */ + break; + + case GAUDI2_EVENT_PCIE_P2P_MSIX: + gaudi2_handle_pcie_p2p_msix(hdev); + break; + + case GAUDI2_EVENT_SM0_AXI_ERROR_RESPONSE ... GAUDI2_EVENT_SM3_AXI_ERROR_RESPONSE: + index = event_type - GAUDI2_EVENT_SM0_AXI_ERROR_RESPONSE; + skip_reset = !gaudi2_handle_sm_err(hdev, index); + break; + + case GAUDI2_EVENT_PSOC_MME_PLL_LOCK_ERR ... GAUDI2_EVENT_DCORE2_HBM_PLL_LOCK_ERR: + break; + + case GAUDI2_EVENT_CPU_CPLD_SHUTDOWN_CAUSE: + dev_info(hdev->dev, "CPLD shutdown cause, reset reason: 0x%llx\n", + le64_to_cpu(eq_entry->data[0])); + break; + case GAUDI2_EVENT_CPU_CPLD_SHUTDOWN_EVENT: + dev_err(hdev->dev, "CPLD shutdown event, reset reason: 0x%llx\n", + le64_to_cpu(eq_entry->data[0])); + break; + + case GAUDI2_EVENT_CPU_PKT_SANITY_FAILED: + gaudi2_print_cpu_pkt_failure_info(hdev, &eq_entry->pkt_sync_err); + break; + + case GAUDI2_EVENT_ARC_DCCM_FULL: + hl_arc_event_handle(hdev, &eq_entry->arc_data); + break; + + default: + if (gaudi2_irq_map_table[event_type].valid) + dev_err_ratelimited(hdev->dev, "Cannot find handler for event %d\n", + event_type); + } + + if ((gaudi2_irq_map_table[event_type].reset || reset_required) && !skip_reset) + goto reset_device; + + /* Send unmask irq only for interrupts not classified as MSG */ + if (!gaudi2_irq_map_table[event_type].msg) + hl_fw_unmask_irq(hdev, event_type); + + return; + +reset_device: + if (hdev->hard_reset_on_fw_events) { + hl_device_reset(hdev, reset_flags); + } else { + if (!gaudi2_irq_map_table[event_type].msg) + hl_fw_unmask_irq(hdev, event_type); + } +} + +static int gaudi2_memset_device_memory(struct hl_device *hdev, u64 addr, u64 size, u64 val) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + u64 comp_addr, cur_addr = addr, end_addr = addr + size; + u32 chunk_size, busy, dcore, edma_idx, sob_offset, sob_addr, comp_val, edma_commit; + u32 old_mmubp, mmubp; + int rc = 0; + + sob_offset = hdev->asic_prop.first_available_user_sob[0] * 4; + sob_addr = mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + sob_offset; + comp_addr = CFG_BASE + sob_addr; + comp_val = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_MASK, 1) | + FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_MASK, 1); + + edma_commit = FIELD_PREP(ARC_FARM_KDMA_CTX_COMMIT_LIN_MASK, 1) | + FIELD_PREP(ARC_FARM_KDMA_CTX_COMMIT_MEM_SET_MASK, 1) | + FIELD_PREP(ARC_FARM_KDMA_CTX_COMMIT_WR_COMP_EN_MASK, 1); + mmubp = FIELD_PREP(ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_WR_MASK, 1) | + FIELD_PREP(ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_RD_MASK, 1); + + if (prop->edma_enabled_mask == 0) { + dev_info(hdev->dev, "non of the EDMA engines is enabled - skip dram scrubbing\n"); + return -EIO; + } + + /* + * set mmu bypass for the scrubbing - all ddmas are configured the same so save + * only the first one to restore later + */ + old_mmubp = RREG32(mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_MMU_BP); + for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) { + for (edma_idx = 0 ; edma_idx < NUM_OF_EDMA_PER_DCORE ; edma_idx++) { + u32 edma_offset = dcore * DCORE_OFFSET + edma_idx * DCORE_EDMA_OFFSET; + u32 edma_bit = dcore * NUM_OF_EDMA_PER_DCORE + edma_idx; + + if (!(prop->edma_enabled_mask & BIT(edma_bit))) + continue; + + WREG32(mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_MMU_BP + + edma_offset, mmubp); + } + } + + while (cur_addr < end_addr) { + int dma_num = 0; + + WREG32(sob_addr, 0); + for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) { + for (edma_idx = 0 ; edma_idx < NUM_OF_EDMA_PER_DCORE ; edma_idx++) { + u32 edma_offset = dcore * DCORE_OFFSET + + edma_idx * DCORE_EDMA_OFFSET; + u32 edma_bit = dcore * NUM_OF_EDMA_PER_DCORE + edma_idx; + + if (!(prop->edma_enabled_mask & BIT(edma_bit))) + continue; + + chunk_size = min_t(u64, SZ_2G, end_addr - cur_addr); + + WREG32(mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_LO + edma_offset, + lower_32_bits(val)); + WREG32(mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_HI + edma_offset, + upper_32_bits(val)); + + WREG32(mmDCORE0_EDMA0_CORE_CTX_DST_BASE_LO + edma_offset, + lower_32_bits(cur_addr)); + WREG32(mmDCORE0_EDMA0_CORE_CTX_DST_BASE_HI + edma_offset, + upper_32_bits(cur_addr)); + + WREG32(mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_LO + edma_offset, + lower_32_bits(comp_addr)); + WREG32(mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_HI + edma_offset, + upper_32_bits(comp_addr)); + WREG32(mmDCORE0_EDMA0_CORE_CTX_WR_COMP_WDATA + edma_offset, + comp_val); + + WREG32(mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_0 + edma_offset, + chunk_size); + WREG32(mmDCORE0_EDMA0_CORE_CTX_COMMIT + edma_offset, edma_commit); + + dma_num++; + + cur_addr += chunk_size; + + if (cur_addr == end_addr) + goto poll; + } + } +poll: + rc = hl_poll_timeout(hdev, sob_addr, busy, (busy == dma_num), 1000, 1000000); + if (rc) { + dev_err(hdev->dev, "DMA Timeout during HBM scrubbing\n"); + goto end; + } + } +end: + for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) { + for (edma_idx = 0 ; edma_idx < NUM_OF_EDMA_PER_DCORE ; edma_idx++) { + u32 edma_offset = dcore * DCORE_OFFSET + edma_idx * DCORE_EDMA_OFFSET; + u32 edma_bit = dcore * NUM_OF_EDMA_PER_DCORE + edma_idx; + + if (!(prop->edma_enabled_mask & BIT(edma_bit))) + continue; + + WREG32(mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_MMU_BP + edma_offset, old_mmubp); + } + } + + WREG32(sob_addr, 0); + return rc; +} + +static int gaudi2_scrub_device_dram(struct hl_device *hdev, u64 val) +{ + int rc; + struct asic_fixed_properties *prop = &hdev->asic_prop; + u64 size = prop->dram_end_address - prop->dram_user_base_address; + + rc = gaudi2_memset_device_memory(hdev, prop->dram_user_base_address, size, val); + + if (rc) + dev_err(hdev->dev, "Failed to scrub dram, address: 0x%llx size: %llu\n", + prop->dram_user_base_address, size); + return rc; +} + +static int gaudi2_scrub_device_mem(struct hl_device *hdev) +{ + int rc; + struct asic_fixed_properties *prop = &hdev->asic_prop; + u64 val = hdev->memory_scrub_val; + u64 addr, size; + + if (!hdev->memory_scrub) + return 0; + + /* scrub SRAM */ + addr = prop->sram_user_base_address; + size = hdev->pldm ? 0x10000 : (prop->sram_size - SRAM_USER_BASE_OFFSET); + dev_dbg(hdev->dev, "Scrubbing SRAM: 0x%09llx - 0x%09llx, val: 0x%llx\n", + addr, addr + size, val); + rc = gaudi2_memset_device_memory(hdev, addr, size, val); + if (rc) { + dev_err(hdev->dev, "scrubbing SRAM failed (%d)\n", rc); + return rc; + } + + /* scrub DRAM */ + rc = gaudi2_scrub_device_dram(hdev, val); + if (rc) { + dev_err(hdev->dev, "scrubbing DRAM failed (%d)\n", rc); + return rc; + } + return 0; +} + +static void gaudi2_restore_user_sm_registers(struct hl_device *hdev) +{ + u64 addr, mon_sts_addr, mon_cfg_addr, cq_lbw_l_addr, cq_lbw_h_addr, + cq_lbw_data_addr, cq_base_l_addr, cq_base_h_addr, cq_size_addr; + u32 val, size, offset; + int dcore_id; + + offset = hdev->asic_prop.first_available_cq[0] * 4; + cq_lbw_l_addr = mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_0 + offset; + cq_lbw_h_addr = mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0 + offset; + cq_lbw_data_addr = mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_0 + offset; + cq_base_l_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0 + offset; + cq_base_h_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0 + offset; + cq_size_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0 + offset; + size = mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0 - + (mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_0 + offset); + + /* memset dcore0 CQ registers */ + gaudi2_memset_device_lbw(hdev, cq_lbw_l_addr, size, 0); + gaudi2_memset_device_lbw(hdev, cq_lbw_h_addr, size, 0); + gaudi2_memset_device_lbw(hdev, cq_lbw_data_addr, size, 0); + gaudi2_memset_device_lbw(hdev, cq_base_l_addr, size, 0); + gaudi2_memset_device_lbw(hdev, cq_base_h_addr, size, 0); + + cq_lbw_l_addr = mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_0 + DCORE_OFFSET; + cq_lbw_h_addr = mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0 + DCORE_OFFSET; + cq_lbw_data_addr = mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_0 + DCORE_OFFSET; + cq_base_l_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0 + DCORE_OFFSET; + cq_base_h_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0 + DCORE_OFFSET; + cq_size_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0 + DCORE_OFFSET; + size = mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0 - mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_0; + + for (dcore_id = 1 ; dcore_id < NUM_OF_DCORES ; dcore_id++) { + gaudi2_memset_device_lbw(hdev, cq_lbw_l_addr, size, 0); + gaudi2_memset_device_lbw(hdev, cq_lbw_h_addr, size, 0); + gaudi2_memset_device_lbw(hdev, cq_lbw_data_addr, size, 0); + gaudi2_memset_device_lbw(hdev, cq_base_l_addr, size, 0); + gaudi2_memset_device_lbw(hdev, cq_base_h_addr, size, 0); + gaudi2_memset_device_lbw(hdev, cq_size_addr, size, 0); + + cq_lbw_l_addr += DCORE_OFFSET; + cq_lbw_h_addr += DCORE_OFFSET; + cq_lbw_data_addr += DCORE_OFFSET; + cq_base_l_addr += DCORE_OFFSET; + cq_base_h_addr += DCORE_OFFSET; + cq_size_addr += DCORE_OFFSET; + } + + offset = hdev->asic_prop.first_available_user_mon[0] * 4; + addr = mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_0 + offset; + val = 1 << DCORE0_SYNC_MNGR_OBJS_MON_STATUS_PROT_SHIFT; + size = mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_0 - (mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_0 + offset); + + /* memset dcore0 monitors */ + gaudi2_memset_device_lbw(hdev, addr, size, val); + + addr = mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_0 + offset; + gaudi2_memset_device_lbw(hdev, addr, size, 0); + + mon_sts_addr = mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_0 + DCORE_OFFSET; + mon_cfg_addr = mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_0 + DCORE_OFFSET; + size = mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_0 - mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_0; + + for (dcore_id = 1 ; dcore_id < NUM_OF_DCORES ; dcore_id++) { + gaudi2_memset_device_lbw(hdev, mon_sts_addr, size, val); + gaudi2_memset_device_lbw(hdev, mon_cfg_addr, size, 0); + mon_sts_addr += DCORE_OFFSET; + mon_cfg_addr += DCORE_OFFSET; + } + + offset = hdev->asic_prop.first_available_user_sob[0] * 4; + addr = mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + offset; + val = 0; + size = mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 - + (mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + offset); + + /* memset dcore0 sobs */ + gaudi2_memset_device_lbw(hdev, addr, size, val); + + addr = mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + DCORE_OFFSET; + size = mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 - mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0; + + for (dcore_id = 1 ; dcore_id < NUM_OF_DCORES ; dcore_id++) { + gaudi2_memset_device_lbw(hdev, addr, size, val); + addr += DCORE_OFFSET; + } + + /* Flush all WREG to prevent race */ + val = RREG32(mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + offset); +} + +static void gaudi2_restore_user_qm_registers(struct hl_device *hdev) +{ + u32 reg_base, hw_queue_id; + + for (hw_queue_id = GAUDI2_QUEUE_ID_PDMA_0_0 ; hw_queue_id <= GAUDI2_QUEUE_ID_ROT_1_0; + hw_queue_id += NUM_OF_PQ_PER_QMAN) { + if (!gaudi2_is_queue_enabled(hdev, hw_queue_id)) + continue; + + gaudi2_clear_qm_fence_counters_common(hdev, hw_queue_id, false); + + reg_base = gaudi2_qm_blocks_bases[hw_queue_id]; + WREG32(reg_base + QM_ARB_CFG_0_OFFSET, 0); + } + + /* Flush all WREG to prevent race */ + RREG32(mmPDMA0_QM_ARB_CFG_0); +} + +static void gaudi2_restore_nic_qm_registers(struct hl_device *hdev) +{ + u32 reg_base, hw_queue_id; + + for (hw_queue_id = GAUDI2_QUEUE_ID_NIC_0_0 ; hw_queue_id <= GAUDI2_QUEUE_ID_NIC_23_3; + hw_queue_id += NUM_OF_PQ_PER_QMAN) { + if (!gaudi2_is_queue_enabled(hdev, hw_queue_id)) + continue; + + gaudi2_clear_qm_fence_counters_common(hdev, hw_queue_id, false); + + reg_base = gaudi2_qm_blocks_bases[hw_queue_id]; + WREG32(reg_base + QM_ARB_CFG_0_OFFSET, 0); + } + + /* Flush all WREG to prevent race */ + RREG32(mmPDMA0_QM_ARB_CFG_0); +} + +static int gaudi2_context_switch(struct hl_device *hdev, u32 asid) +{ + return 0; +} + +static void gaudi2_restore_phase_topology(struct hl_device *hdev) +{ +} + +static void gaudi2_init_block_instances(struct hl_device *hdev, u32 block_idx, + struct dup_block_ctx *cfg_ctx) +{ + u64 block_base = cfg_ctx->base + block_idx * cfg_ctx->block_off; + u8 seq; + int i; + + for (i = 0 ; i < cfg_ctx->instances ; i++) { + seq = block_idx * cfg_ctx->instances + i; + + /* skip disabled instance */ + if (!(cfg_ctx->enabled_mask & BIT_ULL(seq))) + continue; + + cfg_ctx->instance_cfg_fn(hdev, block_base + i * cfg_ctx->instance_off, + cfg_ctx->data); + } +} + +static void gaudi2_init_blocks_with_mask(struct hl_device *hdev, struct dup_block_ctx *cfg_ctx, + u64 mask) +{ + int i; + + cfg_ctx->enabled_mask = mask; + + for (i = 0 ; i < cfg_ctx->blocks ; i++) + gaudi2_init_block_instances(hdev, i, cfg_ctx); +} + +void gaudi2_init_blocks(struct hl_device *hdev, struct dup_block_ctx *cfg_ctx) +{ + gaudi2_init_blocks_with_mask(hdev, cfg_ctx, U64_MAX); +} + +static int gaudi2_debugfs_read_dma(struct hl_device *hdev, u64 addr, u32 size, void *blob_addr) +{ + void *host_mem_virtual_addr; + dma_addr_t host_mem_dma_addr; + u64 reserved_va_base; + u32 pos, size_left, size_to_dma; + struct hl_ctx *ctx; + int rc = 0; + + /* Fetch the ctx */ + ctx = hl_get_compute_ctx(hdev); + if (!ctx) { + dev_err(hdev->dev, "No ctx available\n"); + return -EINVAL; + } + + /* Allocate buffers for read and for poll */ + host_mem_virtual_addr = hl_asic_dma_alloc_coherent(hdev, SZ_2M, &host_mem_dma_addr, + GFP_KERNEL | __GFP_ZERO); + if (host_mem_virtual_addr == NULL) { + dev_err(hdev->dev, "Failed to allocate memory for KDMA read\n"); + rc = -ENOMEM; + goto put_ctx; + } + + /* Reserve VM region on asic side */ + reserved_va_base = hl_reserve_va_block(hdev, ctx, HL_VA_RANGE_TYPE_HOST, SZ_2M, + HL_MMU_VA_ALIGNMENT_NOT_NEEDED); + if (!reserved_va_base) { + dev_err(hdev->dev, "Failed to reserve vmem on asic\n"); + rc = -ENOMEM; + goto free_data_buffer; + } + + /* Create mapping on asic side */ + mutex_lock(&ctx->mmu_lock); + rc = hl_mmu_map_contiguous(ctx, reserved_va_base, host_mem_dma_addr, SZ_2M); + hl_mmu_invalidate_cache_range(hdev, false, + MMU_OP_USERPTR | MMU_OP_SKIP_LOW_CACHE_INV, + ctx->asid, reserved_va_base, SZ_2M); + mutex_unlock(&ctx->mmu_lock); + if (rc) { + dev_err(hdev->dev, "Failed to create mapping on asic mmu\n"); + goto unreserve_va; + } + + hdev->asic_funcs->kdma_lock(hdev, 0); + + /* Enable MMU on KDMA */ + gaudi2_kdma_set_mmbp_asid(hdev, false, ctx->asid); + + pos = 0; + size_left = size; + size_to_dma = SZ_2M; + + while (size_left > 0) { + if (size_left < SZ_2M) + size_to_dma = size_left; + + rc = gaudi2_send_job_to_kdma(hdev, addr, reserved_va_base, size_to_dma, false); + if (rc) + break; + + memcpy(blob_addr + pos, host_mem_virtual_addr, size_to_dma); + + if (size_left <= SZ_2M) + break; + + pos += SZ_2M; + addr += SZ_2M; + size_left -= SZ_2M; + } + + gaudi2_kdma_set_mmbp_asid(hdev, true, HL_KERNEL_ASID_ID); + + hdev->asic_funcs->kdma_unlock(hdev, 0); + + mutex_lock(&ctx->mmu_lock); + hl_mmu_unmap_contiguous(ctx, reserved_va_base, SZ_2M); + hl_mmu_invalidate_cache_range(hdev, false, MMU_OP_USERPTR, + ctx->asid, reserved_va_base, SZ_2M); + mutex_unlock(&ctx->mmu_lock); +unreserve_va: + hl_unreserve_va_block(hdev, ctx, reserved_va_base, SZ_2M); +free_data_buffer: + hl_asic_dma_free_coherent(hdev, SZ_2M, host_mem_virtual_addr, host_mem_dma_addr); +put_ctx: + hl_ctx_put(ctx); + + return rc; +} + +static int gaudi2_internal_cb_pool_init(struct hl_device *hdev, struct hl_ctx *ctx) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + int min_alloc_order, rc; + + if (!(gaudi2->hw_cap_initialized & HW_CAP_PMMU)) + return 0; + + hdev->internal_cb_pool_virt_addr = hl_asic_dma_alloc_coherent(hdev, + HOST_SPACE_INTERNAL_CB_SZ, + &hdev->internal_cb_pool_dma_addr, + GFP_KERNEL | __GFP_ZERO); + + if (!hdev->internal_cb_pool_virt_addr) + return -ENOMEM; + + min_alloc_order = ilog2(min(gaudi2_get_signal_cb_size(hdev), + gaudi2_get_wait_cb_size(hdev))); + + hdev->internal_cb_pool = gen_pool_create(min_alloc_order, -1); + if (!hdev->internal_cb_pool) { + dev_err(hdev->dev, "Failed to create internal CB pool\n"); + rc = -ENOMEM; + goto free_internal_cb_pool; + } + + rc = gen_pool_add(hdev->internal_cb_pool, (uintptr_t) hdev->internal_cb_pool_virt_addr, + HOST_SPACE_INTERNAL_CB_SZ, -1); + if (rc) { + dev_err(hdev->dev, "Failed to add memory to internal CB pool\n"); + rc = -EFAULT; + goto destroy_internal_cb_pool; + } + + hdev->internal_cb_va_base = hl_reserve_va_block(hdev, ctx, HL_VA_RANGE_TYPE_HOST, + HOST_SPACE_INTERNAL_CB_SZ, HL_MMU_VA_ALIGNMENT_NOT_NEEDED); + + if (!hdev->internal_cb_va_base) { + rc = -ENOMEM; + goto destroy_internal_cb_pool; + } + + mutex_lock(&ctx->mmu_lock); + rc = hl_mmu_map_contiguous(ctx, hdev->internal_cb_va_base, hdev->internal_cb_pool_dma_addr, + HOST_SPACE_INTERNAL_CB_SZ); + hl_mmu_invalidate_cache(hdev, false, MMU_OP_USERPTR); + mutex_unlock(&ctx->mmu_lock); + + if (rc) + goto unreserve_internal_cb_pool; + + return 0; + +unreserve_internal_cb_pool: + hl_unreserve_va_block(hdev, ctx, hdev->internal_cb_va_base, HOST_SPACE_INTERNAL_CB_SZ); +destroy_internal_cb_pool: + gen_pool_destroy(hdev->internal_cb_pool); +free_internal_cb_pool: + hl_asic_dma_free_coherent(hdev, HOST_SPACE_INTERNAL_CB_SZ, hdev->internal_cb_pool_virt_addr, + hdev->internal_cb_pool_dma_addr); + + return rc; +} + +static void gaudi2_internal_cb_pool_fini(struct hl_device *hdev, struct hl_ctx *ctx) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + + if (!(gaudi2->hw_cap_initialized & HW_CAP_PMMU)) + return; + + mutex_lock(&ctx->mmu_lock); + hl_mmu_unmap_contiguous(ctx, hdev->internal_cb_va_base, HOST_SPACE_INTERNAL_CB_SZ); + hl_unreserve_va_block(hdev, ctx, hdev->internal_cb_va_base, HOST_SPACE_INTERNAL_CB_SZ); + hl_mmu_invalidate_cache(hdev, true, MMU_OP_USERPTR); + mutex_unlock(&ctx->mmu_lock); + + gen_pool_destroy(hdev->internal_cb_pool); + + hl_asic_dma_free_coherent(hdev, HOST_SPACE_INTERNAL_CB_SZ, hdev->internal_cb_pool_virt_addr, + hdev->internal_cb_pool_dma_addr); +} + +static void gaudi2_restore_user_registers(struct hl_device *hdev) +{ + gaudi2_restore_user_sm_registers(hdev); + gaudi2_restore_user_qm_registers(hdev); +} + +static int gaudi2_map_virtual_msix_doorbell_memory(struct hl_ctx *ctx) +{ + struct hl_device *hdev = ctx->hdev; + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct gaudi2_device *gaudi2 = hdev->asic_specific; + int rc; + + rc = hl_mmu_map_page(ctx, RESERVED_VA_FOR_VIRTUAL_MSIX_DOORBELL_START, + gaudi2->virt_msix_db_dma_addr, prop->pmmu.page_size, true); + if (rc) + dev_err(hdev->dev, "Failed to map VA %#llx for virtual MSI-X doorbell memory\n", + RESERVED_VA_FOR_VIRTUAL_MSIX_DOORBELL_START); + + return rc; +} + +static void gaudi2_unmap_virtual_msix_doorbell_memory(struct hl_ctx *ctx) +{ + struct hl_device *hdev = ctx->hdev; + struct asic_fixed_properties *prop = &hdev->asic_prop; + int rc; + + rc = hl_mmu_unmap_page(ctx, RESERVED_VA_FOR_VIRTUAL_MSIX_DOORBELL_START, + prop->pmmu.page_size, true); + if (rc) + dev_err(hdev->dev, "Failed to unmap VA %#llx of virtual MSI-X doorbell memory\n", + RESERVED_VA_FOR_VIRTUAL_MSIX_DOORBELL_START); +} + +static int gaudi2_ctx_init(struct hl_ctx *ctx) +{ + int rc; + + rc = gaudi2_mmu_prepare(ctx->hdev, ctx->asid); + if (rc) + return rc; + + /* No need to clear user registers if the device has just + * performed reset, we restore only nic qm registers + */ + if (ctx->hdev->reset_upon_device_release) + gaudi2_restore_nic_qm_registers(ctx->hdev); + else + gaudi2_restore_user_registers(ctx->hdev); + + rc = gaudi2_internal_cb_pool_init(ctx->hdev, ctx); + if (rc) + return rc; + + rc = gaudi2_map_virtual_msix_doorbell_memory(ctx); + if (rc) + gaudi2_internal_cb_pool_fini(ctx->hdev, ctx); + + return rc; +} + +static void gaudi2_ctx_fini(struct hl_ctx *ctx) +{ + if (ctx->asid == HL_KERNEL_ASID_ID) + return; + + gaudi2_internal_cb_pool_fini(ctx->hdev, ctx); + + gaudi2_unmap_virtual_msix_doorbell_memory(ctx); +} + +static int gaudi2_pre_schedule_cs(struct hl_cs *cs) +{ + struct hl_device *hdev = cs->ctx->hdev; + int index = cs->sequence & (hdev->asic_prop.max_pending_cs - 1); + u32 mon_payload, sob_id, mon_id; + + if (!cs_needs_completion(cs)) + return 0; + + /* + * First 64 SOB/MON are reserved for driver for QMAN auto completion + * mechanism. Each SOB/MON pair are used for a pending CS with the same + * cyclic index. The SOB value is increased when each of the CS jobs is + * completed. When the SOB reaches the number of CS jobs, the monitor + * generates MSI-X interrupt. + */ + + sob_id = mon_id = index; + mon_payload = (1 << CQ_ENTRY_SHADOW_INDEX_VALID_SHIFT) | + (1 << CQ_ENTRY_READY_SHIFT) | index; + + gaudi2_arm_cq_monitor(hdev, sob_id, mon_id, GAUDI2_RESERVED_CQ_CS_COMPLETION, mon_payload, + cs->jobs_cnt); + + return 0; +} + +static u32 gaudi2_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx) +{ + return HL_INVALID_QUEUE; +} + +static u32 gaudi2_gen_signal_cb(struct hl_device *hdev, void *data, u16 sob_id, u32 size, bool eb) +{ + struct hl_cb *cb = (struct hl_cb *) data; + struct packet_msg_short *pkt; + u32 value, ctl, pkt_size = sizeof(*pkt); + + pkt = (struct packet_msg_short *) (uintptr_t) (cb->kernel_address + size); + memset(pkt, 0, pkt_size); + + /* Inc by 1, Mode ADD */ + value = FIELD_PREP(GAUDI2_PKT_SHORT_VAL_SOB_SYNC_VAL_MASK, 1); + value |= FIELD_PREP(GAUDI2_PKT_SHORT_VAL_SOB_MOD_MASK, 1); + + ctl = FIELD_PREP(GAUDI2_PKT_SHORT_CTL_ADDR_MASK, sob_id * 4); + ctl |= FIELD_PREP(GAUDI2_PKT_SHORT_CTL_BASE_MASK, 1); /* SOB base */ + ctl |= FIELD_PREP(GAUDI2_PKT_CTL_OPCODE_MASK, PACKET_MSG_SHORT); + ctl |= FIELD_PREP(GAUDI2_PKT_CTL_EB_MASK, eb); + ctl |= FIELD_PREP(GAUDI2_PKT_CTL_MB_MASK, 1); + + pkt->value = cpu_to_le32(value); + pkt->ctl = cpu_to_le32(ctl); + + return size + pkt_size; +} + +static u32 gaudi2_add_mon_msg_short(struct packet_msg_short *pkt, u32 value, u16 addr) +{ + u32 ctl, pkt_size = sizeof(*pkt); + + memset(pkt, 0, pkt_size); + + ctl = FIELD_PREP(GAUDI2_PKT_SHORT_CTL_ADDR_MASK, addr); + ctl |= FIELD_PREP(GAUDI2_PKT_SHORT_CTL_BASE_MASK, 0); /* MON base */ + ctl |= FIELD_PREP(GAUDI2_PKT_CTL_OPCODE_MASK, PACKET_MSG_SHORT); + ctl |= FIELD_PREP(GAUDI2_PKT_CTL_EB_MASK, 0); + ctl |= FIELD_PREP(GAUDI2_PKT_CTL_MB_MASK, 0); + + pkt->value = cpu_to_le32(value); + pkt->ctl = cpu_to_le32(ctl); + + return pkt_size; +} + +static u32 gaudi2_add_arm_monitor_pkt(struct hl_device *hdev, struct packet_msg_short *pkt, + u16 sob_base, u8 sob_mask, u16 sob_val, u16 addr) +{ + u32 ctl, value, pkt_size = sizeof(*pkt); + u8 mask; + + if (hl_gen_sob_mask(sob_base, sob_mask, &mask)) { + dev_err(hdev->dev, "sob_base %u (mask %#x) is not valid\n", sob_base, sob_mask); + return 0; + } + + memset(pkt, 0, pkt_size); + + value = FIELD_PREP(GAUDI2_PKT_SHORT_VAL_MON_SYNC_GID_MASK, sob_base / 8); + value |= FIELD_PREP(GAUDI2_PKT_SHORT_VAL_MON_SYNC_VAL_MASK, sob_val); + value |= FIELD_PREP(GAUDI2_PKT_SHORT_VAL_MON_MODE_MASK, 0); /* GREATER OR EQUAL*/ + value |= FIELD_PREP(GAUDI2_PKT_SHORT_VAL_MON_MASK_MASK, mask); + + ctl = FIELD_PREP(GAUDI2_PKT_SHORT_CTL_ADDR_MASK, addr); + ctl |= FIELD_PREP(GAUDI2_PKT_SHORT_CTL_BASE_MASK, 0); /* MON base */ + ctl |= FIELD_PREP(GAUDI2_PKT_CTL_OPCODE_MASK, PACKET_MSG_SHORT); + ctl |= FIELD_PREP(GAUDI2_PKT_CTL_EB_MASK, 0); + ctl |= FIELD_PREP(GAUDI2_PKT_CTL_MB_MASK, 1); + + pkt->value = cpu_to_le32(value); + pkt->ctl = cpu_to_le32(ctl); + + return pkt_size; +} + +static u32 gaudi2_add_fence_pkt(struct packet_fence *pkt) +{ + u32 ctl, cfg, pkt_size = sizeof(*pkt); + + memset(pkt, 0, pkt_size); + + cfg = FIELD_PREP(GAUDI2_PKT_FENCE_CFG_DEC_VAL_MASK, 1); + cfg |= FIELD_PREP(GAUDI2_PKT_FENCE_CFG_TARGET_VAL_MASK, 1); + cfg |= FIELD_PREP(GAUDI2_PKT_FENCE_CFG_ID_MASK, 2); + + ctl = FIELD_PREP(GAUDI2_PKT_CTL_OPCODE_MASK, PACKET_FENCE); + ctl |= FIELD_PREP(GAUDI2_PKT_CTL_EB_MASK, 0); + ctl |= FIELD_PREP(GAUDI2_PKT_CTL_MB_MASK, 1); + + pkt->cfg = cpu_to_le32(cfg); + pkt->ctl = cpu_to_le32(ctl); + + return pkt_size; +} + +static u32 gaudi2_gen_wait_cb(struct hl_device *hdev, struct hl_gen_wait_properties *prop) +{ + struct hl_cb *cb = (struct hl_cb *) prop->data; + void *buf = (void *) (uintptr_t) (cb->kernel_address); + + u64 monitor_base, fence_addr = 0; + u32 stream_index, size = prop->size; + u16 msg_addr_offset; + + stream_index = prop->q_idx % 4; + fence_addr = CFG_BASE + gaudi2_qm_blocks_bases[prop->q_idx] + + QM_FENCE2_OFFSET + stream_index * 4; + + /* + * monitor_base should be the content of the base0 address registers, + * so it will be added to the msg short offsets + */ + monitor_base = mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0; + + /* First monitor config packet: low address of the sync */ + msg_addr_offset = (mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 + prop->mon_id * 4) - + monitor_base; + + size += gaudi2_add_mon_msg_short(buf + size, (u32) fence_addr, msg_addr_offset); + + /* Second monitor config packet: high address of the sync */ + msg_addr_offset = (mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 + prop->mon_id * 4) - + monitor_base; + + size += gaudi2_add_mon_msg_short(buf + size, (u32) (fence_addr >> 32), msg_addr_offset); + + /* + * Third monitor config packet: the payload, i.e. what to write when the + * sync triggers + */ + msg_addr_offset = (mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_0 + prop->mon_id * 4) - + monitor_base; + + size += gaudi2_add_mon_msg_short(buf + size, 1, msg_addr_offset); + + /* Fourth monitor config packet: bind the monitor to a sync object */ + msg_addr_offset = (mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_0 + prop->mon_id * 4) - monitor_base; + + size += gaudi2_add_arm_monitor_pkt(hdev, buf + size, prop->sob_base, prop->sob_mask, + prop->sob_val, msg_addr_offset); + + /* Fence packet */ + size += gaudi2_add_fence_pkt(buf + size); + + return size; +} + +static void gaudi2_reset_sob(struct hl_device *hdev, void *data) +{ + struct hl_hw_sob *hw_sob = (struct hl_hw_sob *) data; + + dev_dbg(hdev->dev, "reset SOB, q_idx: %d, sob_id: %d\n", hw_sob->q_idx, hw_sob->sob_id); + + WREG32(mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + hw_sob->sob_id * 4, 0); + + kref_init(&hw_sob->kref); +} + +static void gaudi2_reset_sob_group(struct hl_device *hdev, u16 sob_group) +{ +} + +static u64 gaudi2_get_device_time(struct hl_device *hdev) +{ + u64 device_time = ((u64) RREG32(mmPSOC_TIMESTAMP_CNTCVU)) << 32; + + return device_time | RREG32(mmPSOC_TIMESTAMP_CNTCVL); +} + +static int gaudi2_collective_wait_init_cs(struct hl_cs *cs) +{ + return 0; +} + +static int gaudi2_collective_wait_create_jobs(struct hl_device *hdev, struct hl_ctx *ctx, + struct hl_cs *cs, u32 wait_queue_id, + u32 collective_engine_id, u32 encaps_signal_offset) +{ + return -EINVAL; +} + +/* + * hl_mmu_scramble - converts a dram (non power of 2) page-size aligned address + * to DMMU page-size address (64MB) before mapping it in + * the MMU. + * The operation is performed on both the virtual and physical addresses. + * for device with 6 HBMs the scramble is: + * (addr[47:0] / 48M) * 64M + addr % 48M + addr[63:48] + * + * Example: + * ============================================================================= + * Allocated DRAM Reserved VA scrambled VA for MMU mapping Scrambled PA + * Phys address in MMU last + * HOP + * ============================================================================= + * PA1 0x3000000 VA1 0x9C000000 SVA1= (VA1/48M)*64M 0xD0000000 <- PA1/48M 0x1 + * PA2 0x9000000 VA2 0x9F000000 SVA2= (VA2/48M)*64M 0xD4000000 <- PA2/48M 0x3 + * ============================================================================= + */ +static u64 gaudi2_mmu_scramble_addr(struct hl_device *hdev, u64 raw_addr) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + u32 divisor, mod_va; + u64 div_va; + + /* accept any address in the DRAM address space */ + if (hl_mem_area_inside_range(raw_addr, sizeof(raw_addr), DRAM_PHYS_BASE, + VA_HBM_SPACE_END)) { + + divisor = prop->num_functional_hbms * GAUDI2_HBM_MMU_SCRM_MEM_SIZE; + div_va = div_u64_rem(raw_addr & GAUDI2_HBM_MMU_SCRM_ADDRESS_MASK, divisor, &mod_va); + return (raw_addr & ~GAUDI2_HBM_MMU_SCRM_ADDRESS_MASK) | + (div_va << GAUDI2_HBM_MMU_SCRM_DIV_SHIFT) | + (mod_va << GAUDI2_HBM_MMU_SCRM_MOD_SHIFT); + } + + return raw_addr; +} + +static u64 gaudi2_mmu_descramble_addr(struct hl_device *hdev, u64 scrambled_addr) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + u32 divisor, mod_va; + u64 div_va; + + /* accept any address in the DRAM address space */ + if (hl_mem_area_inside_range(scrambled_addr, sizeof(scrambled_addr), DRAM_PHYS_BASE, + VA_HBM_SPACE_END)) { + + divisor = prop->num_functional_hbms * GAUDI2_HBM_MMU_SCRM_MEM_SIZE; + div_va = div_u64_rem(scrambled_addr & GAUDI2_HBM_MMU_SCRM_ADDRESS_MASK, + PAGE_SIZE_64MB, &mod_va); + + return ((scrambled_addr & ~GAUDI2_HBM_MMU_SCRM_ADDRESS_MASK) + + (div_va * divisor + mod_va)); + } + + return scrambled_addr; +} + +static u32 gaudi2_get_dec_base_addr(struct hl_device *hdev, u32 core_id) +{ + u32 base = 0, dcore_id, dec_id; + + if (core_id >= NUMBER_OF_DEC) { + dev_err(hdev->dev, "Unexpected core number %d for DEC\n", core_id); + goto out; + } + + if (core_id < 8) { + dcore_id = core_id / NUM_OF_DEC_PER_DCORE; + dec_id = core_id % NUM_OF_DEC_PER_DCORE; + + base = mmDCORE0_DEC0_CMD_BASE + dcore_id * DCORE_OFFSET + + dec_id * DCORE_VDEC_OFFSET; + } else { + /* PCIe Shared Decoder */ + base = mmPCIE_DEC0_CMD_BASE + ((core_id % 8) * PCIE_VDEC_OFFSET); + } +out: + return base; +} + +static int gaudi2_get_hw_block_id(struct hl_device *hdev, u64 block_addr, + u32 *block_size, u32 *block_id) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + int i; + + for (i = 0 ; i < NUM_USER_MAPPED_BLOCKS ; i++) { + if (block_addr == CFG_BASE + gaudi2->mapped_blocks[i].address) { + *block_id = i; + if (block_size) + *block_size = gaudi2->mapped_blocks[i].size; + return 0; + } + } + + dev_err(hdev->dev, "Invalid block address %#llx", block_addr); + + return -EINVAL; +} + +static int gaudi2_block_mmap(struct hl_device *hdev, struct vm_area_struct *vma, + u32 block_id, u32 block_size) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u64 offset_in_bar; + u64 address; + int rc; + + if (block_id >= NUM_USER_MAPPED_BLOCKS) { + dev_err(hdev->dev, "Invalid block id %u", block_id); + return -EINVAL; + } + + /* we allow mapping only an entire block */ + if (block_size != gaudi2->mapped_blocks[block_id].size) { + dev_err(hdev->dev, "Invalid block size %u", block_size); + return -EINVAL; + } + + offset_in_bar = CFG_BASE + gaudi2->mapped_blocks[block_id].address - STM_FLASH_BASE_ADDR; + + address = pci_resource_start(hdev->pdev, SRAM_CFG_BAR_ID) + offset_in_bar; + + vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP | + VM_DONTCOPY | VM_NORESERVE; + + rc = remap_pfn_range(vma, vma->vm_start, address >> PAGE_SHIFT, + block_size, vma->vm_page_prot); + if (rc) + dev_err(hdev->dev, "remap_pfn_range error %d", rc); + + return rc; +} + +static void gaudi2_enable_events_from_fw(struct hl_device *hdev) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + + struct cpu_dyn_regs *dyn_regs = &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs; + u32 irq_handler_offset = le32_to_cpu(dyn_regs->gic_host_ints_irq); + + if (gaudi2->hw_cap_initialized & HW_CAP_CPU_Q) + WREG32(irq_handler_offset, + gaudi2_irq_map_table[GAUDI2_EVENT_CPU_INTS_REGISTER].cpu_id); +} + +static int gaudi2_get_mmu_base(struct hl_device *hdev, u64 mmu_id, u32 *mmu_base) +{ + switch (mmu_id) { + case HW_CAP_DCORE0_DMMU0: + *mmu_base = mmDCORE0_HMMU0_MMU_BASE; + break; + case HW_CAP_DCORE0_DMMU1: + *mmu_base = mmDCORE0_HMMU1_MMU_BASE; + break; + case HW_CAP_DCORE0_DMMU2: + *mmu_base = mmDCORE0_HMMU2_MMU_BASE; + break; + case HW_CAP_DCORE0_DMMU3: + *mmu_base = mmDCORE0_HMMU3_MMU_BASE; + break; + case HW_CAP_DCORE1_DMMU0: + *mmu_base = mmDCORE1_HMMU0_MMU_BASE; + break; + case HW_CAP_DCORE1_DMMU1: + *mmu_base = mmDCORE1_HMMU1_MMU_BASE; + break; + case HW_CAP_DCORE1_DMMU2: + *mmu_base = mmDCORE1_HMMU2_MMU_BASE; + break; + case HW_CAP_DCORE1_DMMU3: + *mmu_base = mmDCORE1_HMMU3_MMU_BASE; + break; + case HW_CAP_DCORE2_DMMU0: + *mmu_base = mmDCORE2_HMMU0_MMU_BASE; + break; + case HW_CAP_DCORE2_DMMU1: + *mmu_base = mmDCORE2_HMMU1_MMU_BASE; + break; + case HW_CAP_DCORE2_DMMU2: + *mmu_base = mmDCORE2_HMMU2_MMU_BASE; + break; + case HW_CAP_DCORE2_DMMU3: + *mmu_base = mmDCORE2_HMMU3_MMU_BASE; + break; + case HW_CAP_DCORE3_DMMU0: + *mmu_base = mmDCORE3_HMMU0_MMU_BASE; + break; + case HW_CAP_DCORE3_DMMU1: + *mmu_base = mmDCORE3_HMMU1_MMU_BASE; + break; + case HW_CAP_DCORE3_DMMU2: + *mmu_base = mmDCORE3_HMMU2_MMU_BASE; + break; + case HW_CAP_DCORE3_DMMU3: + *mmu_base = mmDCORE3_HMMU3_MMU_BASE; + break; + case HW_CAP_PMMU: + *mmu_base = mmPMMU_HBW_MMU_BASE; + break; + default: + return -EINVAL; + } + + return 0; +} + +static void gaudi2_ack_mmu_error(struct hl_device *hdev, u64 mmu_id) +{ + bool is_pmmu = (mmu_id == HW_CAP_PMMU ? true : false); + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 mmu_base; + + if (!(gaudi2->hw_cap_initialized & mmu_id)) + return; + + if (gaudi2_get_mmu_base(hdev, mmu_id, &mmu_base)) + return; + + gaudi2_handle_page_error(hdev, mmu_base, is_pmmu); + gaudi2_handle_access_error(hdev, mmu_base, is_pmmu); +} + +static int gaudi2_ack_mmu_page_fault_or_access_error(struct hl_device *hdev, u64 mmu_cap_mask) +{ + u32 i, mmu_id, num_of_hmmus = NUM_OF_HMMU_PER_DCORE * NUM_OF_DCORES; + + /* check all HMMUs */ + for (i = 0 ; i < num_of_hmmus ; i++) { + mmu_id = HW_CAP_DCORE0_DMMU0 << i; + + if (mmu_cap_mask & mmu_id) + gaudi2_ack_mmu_error(hdev, mmu_id); + } + + /* check PMMU */ + if (mmu_cap_mask & HW_CAP_PMMU) + gaudi2_ack_mmu_error(hdev, HW_CAP_PMMU); + + return 0; +} + +static void gaudi2_get_msi_info(__le32 *table) +{ + table[CPUCP_EVENT_QUEUE_MSI_TYPE] = cpu_to_le32(GAUDI2_EVENT_QUEUE_MSIX_IDX); +} + +static int gaudi2_map_pll_idx_to_fw_idx(u32 pll_idx) +{ + switch (pll_idx) { + case HL_GAUDI2_CPU_PLL: return CPU_PLL; + case HL_GAUDI2_PCI_PLL: return PCI_PLL; + case HL_GAUDI2_NIC_PLL: return NIC_PLL; + case HL_GAUDI2_DMA_PLL: return DMA_PLL; + case HL_GAUDI2_MESH_PLL: return MESH_PLL; + case HL_GAUDI2_MME_PLL: return MME_PLL; + case HL_GAUDI2_TPC_PLL: return TPC_PLL; + case HL_GAUDI2_IF_PLL: return IF_PLL; + case HL_GAUDI2_SRAM_PLL: return SRAM_PLL; + case HL_GAUDI2_HBM_PLL: return HBM_PLL; + case HL_GAUDI2_VID_PLL: return VID_PLL; + case HL_GAUDI2_MSS_PLL: return MSS_PLL; + default: return -EINVAL; + } +} + +static int gaudi2_gen_sync_to_engine_map(struct hl_device *hdev, struct hl_sync_to_engine_map *map) +{ + /* Not implemented */ + return 0; +} + +static int gaudi2_monitor_valid(struct hl_mon_state_dump *mon) +{ + /* Not implemented */ + return 0; +} + +static int gaudi2_print_single_monitor(char **buf, size_t *size, size_t *offset, + struct hl_device *hdev, struct hl_mon_state_dump *mon) +{ + /* Not implemented */ + return 0; +} + + +static int gaudi2_print_fences_single_engine(struct hl_device *hdev, u64 base_offset, + u64 status_base_offset, enum hl_sync_engine_type engine_type, + u32 engine_id, char **buf, size_t *size, size_t *offset) +{ + /* Not implemented */ + return 0; +} + + +static struct hl_state_dump_specs_funcs gaudi2_state_dump_funcs = { + .monitor_valid = gaudi2_monitor_valid, + .print_single_monitor = gaudi2_print_single_monitor, + .gen_sync_to_engine_map = gaudi2_gen_sync_to_engine_map, + .print_fences_single_engine = gaudi2_print_fences_single_engine, +}; + +static void gaudi2_state_dump_init(struct hl_device *hdev) +{ + /* Not implemented */ + hdev->state_dump_specs.props = gaudi2_state_dump_specs_props; + hdev->state_dump_specs.funcs = gaudi2_state_dump_funcs; +} + +static u32 gaudi2_get_sob_addr(struct hl_device *hdev, u32 sob_id) +{ + return 0; +} + +static u32 *gaudi2_get_stream_master_qid_arr(void) +{ + return NULL; +} + +static void gaudi2_add_device_attr(struct hl_device *hdev, struct attribute_group *dev_clk_attr_grp, + struct attribute_group *dev_vrm_attr_grp) +{ + hl_sysfs_add_dev_clk_attr(hdev, dev_clk_attr_grp); + hl_sysfs_add_dev_vrm_attr(hdev, dev_vrm_attr_grp); +} + +static int gaudi2_mmu_get_real_page_size(struct hl_device *hdev, struct hl_mmu_properties *mmu_prop, + u32 page_size, u32 *real_page_size, bool is_dram_addr) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + + /* for host pages the page size must be */ + if (!is_dram_addr) { + if (page_size % mmu_prop->page_size) + goto page_size_err; + + *real_page_size = mmu_prop->page_size; + return 0; + } + + if ((page_size % prop->dram_page_size) || (prop->dram_page_size > mmu_prop->page_size)) + goto page_size_err; + + /* + * MMU page size is different from DRAM page size (more precisely, DMMU page is greater + * than DRAM page size). + * for this reason work with the DRAM page size and let the MMU scrambling routine handle + * this mismatch when calculating the address to place in the MMU page table. + * (in that case also make sure that the dram_page_size is not greater than the + * mmu page size) + */ + *real_page_size = prop->dram_page_size; + + return 0; + +page_size_err: + dev_err(hdev->dev, "page size of %u is not %uKB aligned, can't map\n", + page_size, mmu_prop->page_size >> 10); + return -EFAULT; +} + +static int gaudi2_get_monitor_dump(struct hl_device *hdev, void *data) +{ + return -EOPNOTSUPP; +} + +static const struct hl_asic_funcs gaudi2_funcs = { + .early_init = gaudi2_early_init, + .early_fini = gaudi2_early_fini, + .late_init = gaudi2_late_init, + .late_fini = gaudi2_late_fini, + .sw_init = gaudi2_sw_init, + .sw_fini = gaudi2_sw_fini, + .hw_init = gaudi2_hw_init, + .hw_fini = gaudi2_hw_fini, + .halt_engines = gaudi2_halt_engines, + .suspend = gaudi2_suspend, + .resume = gaudi2_resume, + .mmap = gaudi2_mmap, + .ring_doorbell = gaudi2_ring_doorbell, + .pqe_write = gaudi2_pqe_write, + .asic_dma_alloc_coherent = gaudi2_dma_alloc_coherent, + .asic_dma_free_coherent = gaudi2_dma_free_coherent, + .scrub_device_mem = gaudi2_scrub_device_mem, + .scrub_device_dram = gaudi2_scrub_device_dram, + .get_int_queue_base = NULL, + .test_queues = gaudi2_test_queues, + .asic_dma_pool_zalloc = gaudi2_dma_pool_zalloc, + .asic_dma_pool_free = gaudi2_dma_pool_free, + .cpu_accessible_dma_pool_alloc = gaudi2_cpu_accessible_dma_pool_alloc, + .cpu_accessible_dma_pool_free = gaudi2_cpu_accessible_dma_pool_free, + .asic_dma_unmap_single = gaudi2_dma_unmap_single, + .asic_dma_map_single = gaudi2_dma_map_single, + .hl_dma_unmap_sgtable = hl_dma_unmap_sgtable, + .cs_parser = gaudi2_cs_parser, + .asic_dma_map_sgtable = hl_dma_map_sgtable, + .add_end_of_cb_packets = NULL, + .update_eq_ci = gaudi2_update_eq_ci, + .context_switch = gaudi2_context_switch, + .restore_phase_topology = gaudi2_restore_phase_topology, + .debugfs_read_dma = gaudi2_debugfs_read_dma, + .add_device_attr = gaudi2_add_device_attr, + .handle_eqe = gaudi2_handle_eqe, + .get_events_stat = gaudi2_get_events_stat, + .read_pte = NULL, + .write_pte = NULL, + .mmu_invalidate_cache = gaudi2_mmu_invalidate_cache, + .mmu_invalidate_cache_range = gaudi2_mmu_invalidate_cache_range, + .mmu_prefetch_cache_range = NULL, + .send_heartbeat = gaudi2_send_heartbeat, + .debug_coresight = gaudi2_debug_coresight, + .is_device_idle = gaudi2_is_device_idle, + .non_hard_reset_late_init = gaudi2_non_hard_reset_late_init, + .hw_queues_lock = gaudi2_hw_queues_lock, + .hw_queues_unlock = gaudi2_hw_queues_unlock, + .kdma_lock = gaudi2_kdma_lock, + .kdma_unlock = gaudi2_kdma_unlock, + .get_pci_id = gaudi2_get_pci_id, + .get_eeprom_data = gaudi2_get_eeprom_data, + .get_monitor_dump = gaudi2_get_monitor_dump, + .send_cpu_message = gaudi2_send_cpu_message, + .pci_bars_map = gaudi2_pci_bars_map, + .init_iatu = gaudi2_init_iatu, + .rreg = hl_rreg, + .wreg = hl_wreg, + .halt_coresight = gaudi2_halt_coresight, + .ctx_init = gaudi2_ctx_init, + .ctx_fini = gaudi2_ctx_fini, + .pre_schedule_cs = gaudi2_pre_schedule_cs, + .get_queue_id_for_cq = gaudi2_get_queue_id_for_cq, + .load_firmware_to_device = NULL, + .load_boot_fit_to_device = NULL, + .get_signal_cb_size = gaudi2_get_signal_cb_size, + .get_wait_cb_size = gaudi2_get_wait_cb_size, + .gen_signal_cb = gaudi2_gen_signal_cb, + .gen_wait_cb = gaudi2_gen_wait_cb, + .reset_sob = gaudi2_reset_sob, + .reset_sob_group = gaudi2_reset_sob_group, + .get_device_time = gaudi2_get_device_time, + .pb_print_security_errors = gaudi2_pb_print_security_errors, + .collective_wait_init_cs = gaudi2_collective_wait_init_cs, + .collective_wait_create_jobs = gaudi2_collective_wait_create_jobs, + .get_dec_base_addr = gaudi2_get_dec_base_addr, + .scramble_addr = gaudi2_mmu_scramble_addr, + .descramble_addr = gaudi2_mmu_descramble_addr, + .ack_protection_bits_errors = gaudi2_ack_protection_bits_errors, + .get_hw_block_id = gaudi2_get_hw_block_id, + .hw_block_mmap = gaudi2_block_mmap, + .enable_events_from_fw = gaudi2_enable_events_from_fw, + .ack_mmu_errors = gaudi2_ack_mmu_page_fault_or_access_error, + .get_msi_info = gaudi2_get_msi_info, + .map_pll_idx_to_fw_idx = gaudi2_map_pll_idx_to_fw_idx, + .init_firmware_preload_params = gaudi2_init_firmware_preload_params, + .init_firmware_loader = gaudi2_init_firmware_loader, + .init_cpu_scrambler_dram = gaudi2_init_scrambler_hbm, + .state_dump_init = gaudi2_state_dump_init, + .get_sob_addr = &gaudi2_get_sob_addr, + .set_pci_memory_regions = gaudi2_set_pci_memory_regions, + .get_stream_master_qid_arr = gaudi2_get_stream_master_qid_arr, + .check_if_razwi_happened = gaudi2_check_if_razwi_happened, + .mmu_get_real_page_size = gaudi2_mmu_get_real_page_size, + .access_dev_mem = hl_access_dev_mem, + .set_dram_bar_base = gaudi2_set_hbm_bar_base, +}; + +void gaudi2_set_asic_funcs(struct hl_device *hdev) +{ + hdev->asic_funcs = &gaudi2_funcs; +} diff --git a/drivers/misc/habanalabs/gaudi2/gaudi2P.h b/drivers/misc/habanalabs/gaudi2/gaudi2P.h new file mode 100644 index 000000000000..e4bc4009f05b --- /dev/null +++ b/drivers/misc/habanalabs/gaudi2/gaudi2P.h @@ -0,0 +1,566 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2020-2022 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI2P_H_ +#define GAUDI2P_H_ + +#include +#include "../common/habanalabs.h" +#include "../include/common/hl_boot_if.h" +#include "../include/gaudi2/gaudi2.h" +#include "../include/gaudi2/gaudi2_packets.h" +#include "../include/gaudi2/gaudi2_fw_if.h" +#include "../include/gaudi2/gaudi2_async_events.h" +#include "../include/gaudi2/gaudi2_async_virt_events.h" + +#define GAUDI2_LINUX_FW_FILE "habanalabs/gaudi2/gaudi2-fit.itb" +#define GAUDI2_BOOT_FIT_FILE "habanalabs/gaudi2/gaudi2-boot-fit.itb" + +#define MMU_PAGE_TABLES_INITIAL_SIZE 0x10000000 /* 256MB */ + +#define GAUDI2_CPU_TIMEOUT_USEC 30000000 /* 30s */ + +#define GAUDI2_FPGA_CPU_TIMEOUT 100000000 /* 100s */ + +#define NUMBER_OF_PDMA_QUEUES 2 +#define NUMBER_OF_EDMA_QUEUES 8 +#define NUMBER_OF_MME_QUEUES 4 +#define NUMBER_OF_TPC_QUEUES 25 +#define NUMBER_OF_NIC_QUEUES 24 +#define NUMBER_OF_ROT_QUEUES 2 +#define NUMBER_OF_CPU_QUEUES 1 + +#define NUMBER_OF_HW_QUEUES ((NUMBER_OF_PDMA_QUEUES + \ + NUMBER_OF_EDMA_QUEUES + \ + NUMBER_OF_MME_QUEUES + \ + NUMBER_OF_TPC_QUEUES + \ + NUMBER_OF_NIC_QUEUES + \ + NUMBER_OF_ROT_QUEUES + \ + NUMBER_OF_CPU_QUEUES) * \ + NUM_OF_PQ_PER_QMAN) + +#define NUMBER_OF_QUEUES (NUMBER_OF_CPU_QUEUES + NUMBER_OF_HW_QUEUES) + +#define DCORE_NUM_OF_SOB \ + (((mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8191 - \ + mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0) + 4) >> 2) + +#define DCORE_NUM_OF_MONITORS \ + (((mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2047 - \ + mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_0) + 4) >> 2) + +#define NUMBER_OF_DEC ((NUM_OF_DEC_PER_DCORE * NUM_OF_DCORES) + NUMBER_OF_PCIE_DEC) + +/* Map all arcs dccm + arc schedulers acp blocks */ +#define NUM_OF_USER_ACP_BLOCKS (NUM_OF_SCHEDULER_ARC + 2) +#define NUM_OF_USER_NIC_UMR_BLOCKS 15 +#define NUM_OF_EXPOSED_SM_BLOCKS ((NUM_OF_DCORES - 1) * 2) +#define NUM_USER_MAPPED_BLOCKS \ + (NUM_ARC_CPUS + NUM_OF_USER_ACP_BLOCKS + NUMBER_OF_DEC + \ + NUM_OF_EXPOSED_SM_BLOCKS + \ + (NIC_NUMBER_OF_ENGINES * NUM_OF_USER_NIC_UMR_BLOCKS)) + +/* Within the user mapped array, decoder entries start post all the ARC related + * entries + */ +#define USR_MAPPED_BLK_DEC_START_IDX \ + (NUM_ARC_CPUS + NUM_OF_USER_ACP_BLOCKS + \ + (NIC_NUMBER_OF_ENGINES * NUM_OF_USER_NIC_UMR_BLOCKS)) + +#define USR_MAPPED_BLK_SM_START_IDX \ + (NUM_ARC_CPUS + NUM_OF_USER_ACP_BLOCKS + NUMBER_OF_DEC + \ + (NIC_NUMBER_OF_ENGINES * NUM_OF_USER_NIC_UMR_BLOCKS)) + +#define SM_OBJS_BLOCK_SIZE (mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_0 - \ + mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0) + +#define GAUDI2_MAX_PENDING_CS 64 + +#if !IS_MAX_PENDING_CS_VALID(GAUDI2_MAX_PENDING_CS) +#error "GAUDI2_MAX_PENDING_CS must be power of 2 and greater than 1" +#endif + +#define CORESIGHT_TIMEOUT_USEC 100000 /* 100 ms */ + +#define GAUDI2_PREBOOT_REQ_TIMEOUT_USEC 25000000 /* 25s */ + +#define GAUDI2_BOOT_FIT_REQ_TIMEOUT_USEC 10000000 /* 10s */ + +#define GAUDI2_NIC_CLK_FREQ 450000000ull /* 450 MHz */ + +#define DC_POWER_DEFAULT 60000 /* 60W */ + +#define GAUDI2_HBM_NUM 6 + +#define DMA_MAX_TRANSFER_SIZE U32_MAX + +#define GAUDI2_DEFAULT_CARD_NAME "HL225" + +#define QMAN_STREAMS 4 +#define PQ_FETCHER_CACHE_SIZE 8 +#define NUM_OF_MME_SBTE_PORTS 5 +#define NUM_OF_MME_WB_PORTS 2 + +#define GAUDI2_ENGINE_ID_DCORE_OFFSET \ + (GAUDI2_DCORE1_ENGINE_ID_EDMA_0 - GAUDI2_DCORE0_ENGINE_ID_EDMA_0) + +/* DRAM Memory Map */ + +#define CPU_FW_IMAGE_SIZE 0x10000000 /* 256MB */ + +/* This define should be used only when working in a debug mode without dram. + * When working with dram, the driver size will be calculated dynamically. + */ +#define NIC_DEFAULT_DRV_SIZE 0x20000000 /* 512MB */ + +#define CPU_FW_IMAGE_ADDR DRAM_PHYS_BASE + +#define NIC_NUMBER_OF_PORTS NIC_NUMBER_OF_ENGINES + +#define NUMBER_OF_PCIE_DEC 2 +#define PCIE_DEC_SHIFT 8 + +#define SRAM_USER_BASE_OFFSET 0 + +/* cluster binning */ +#define MAX_FAULTY_HBMS 1 +#define GAUDI2_XBAR_EDGE_FULL_MASK 0xF +#define GAUDI2_EDMA_FULL_MASK 0xFF +#define GAUDI2_DRAM_FULL_MASK 0x3F + +/* Host virtual address space. */ + +#define VA_HOST_SPACE_PAGE_START 0xFFF0000000000000ull +#define VA_HOST_SPACE_PAGE_END 0xFFF0800000000000ull /* 140TB */ + +#define VA_HOST_SPACE_HPAGE_START 0xFFF0800000000000ull +#define VA_HOST_SPACE_HPAGE_END 0xFFF1000000000000ull /* 140TB */ + +#define VA_HOST_SPACE_USER_MAPPED_CB_START 0xFFF1000000000000ull +#define VA_HOST_SPACE_USER_MAPPED_CB_END 0xFFF1000100000000ull /* 4GB */ + +/* 140TB */ +#define VA_HOST_SPACE_PAGE_SIZE (VA_HOST_SPACE_PAGE_END - VA_HOST_SPACE_PAGE_START) + +/* 140TB */ +#define VA_HOST_SPACE_HPAGE_SIZE (VA_HOST_SPACE_HPAGE_END - VA_HOST_SPACE_HPAGE_START) + +#define VA_HOST_SPACE_SIZE (VA_HOST_SPACE_PAGE_SIZE + VA_HOST_SPACE_HPAGE_SIZE) + +#define HOST_SPACE_INTERNAL_CB_SZ SZ_2M + +/* + * HBM virtual address space + * Gaudi2 has 6 HBM devices, each supporting 16GB total of 96GB at most. + * No core separation is supported so we can have one chunk of virtual address + * space just above the physical ones. + * The virtual address space starts immediately after the end of the physical + * address space which is determined at run-time. + */ +#define VA_HBM_SPACE_END 0x1002000000000000ull + +#define HW_CAP_PLL BIT_ULL(0) +#define HW_CAP_DRAM BIT_ULL(1) +#define HW_CAP_PMMU BIT_ULL(2) +#define HW_CAP_CPU BIT_ULL(3) +#define HW_CAP_MSIX BIT_ULL(4) + +#define HW_CAP_CPU_Q BIT_ULL(5) +#define HW_CAP_CPU_Q_SHIFT 5 + +#define HW_CAP_CLK_GATE BIT_ULL(6) +#define HW_CAP_KDMA BIT_ULL(7) +#define HW_CAP_SRAM_SCRAMBLER BIT_ULL(8) + +#define HW_CAP_DCORE0_DMMU0 BIT_ULL(9) +#define HW_CAP_DCORE0_DMMU1 BIT_ULL(10) +#define HW_CAP_DCORE0_DMMU2 BIT_ULL(11) +#define HW_CAP_DCORE0_DMMU3 BIT_ULL(12) +#define HW_CAP_DCORE1_DMMU0 BIT_ULL(13) +#define HW_CAP_DCORE1_DMMU1 BIT_ULL(14) +#define HW_CAP_DCORE1_DMMU2 BIT_ULL(15) +#define HW_CAP_DCORE1_DMMU3 BIT_ULL(16) +#define HW_CAP_DCORE2_DMMU0 BIT_ULL(17) +#define HW_CAP_DCORE2_DMMU1 BIT_ULL(18) +#define HW_CAP_DCORE2_DMMU2 BIT_ULL(19) +#define HW_CAP_DCORE2_DMMU3 BIT_ULL(20) +#define HW_CAP_DCORE3_DMMU0 BIT_ULL(21) +#define HW_CAP_DCORE3_DMMU1 BIT_ULL(22) +#define HW_CAP_DCORE3_DMMU2 BIT_ULL(23) +#define HW_CAP_DCORE3_DMMU3 BIT_ULL(24) +#define HW_CAP_DMMU_MASK GENMASK_ULL(24, 9) +#define HW_CAP_DMMU_SHIFT 9 +#define HW_CAP_PDMA_MASK BIT_ULL(26) +#define HW_CAP_EDMA_MASK GENMASK_ULL(34, 27) +#define HW_CAP_EDMA_SHIFT 27 +#define HW_CAP_MME_MASK GENMASK_ULL(38, 35) +#define HW_CAP_MME_SHIFT 35 +#define HW_CAP_ROT_MASK GENMASK_ULL(40, 39) +#define HW_CAP_ROT_SHIFT 39 +#define HW_CAP_HBM_SCRAMBLER_HW_RESET BIT_ULL(41) +#define HW_CAP_HBM_SCRAMBLER_SW_RESET BIT_ULL(42) +#define HW_CAP_HBM_SCRAMBLER_MASK (HW_CAP_HBM_SCRAMBLER_HW_RESET | \ + HW_CAP_HBM_SCRAMBLER_SW_RESET) +#define HW_CAP_HBM_SCRAMBLER_SHIFT 41 +#define HW_CAP_RESERVED BIT(43) +#define HW_CAP_MMU_MASK (HW_CAP_PMMU | HW_CAP_DMMU_MASK) + +/* Range Registers */ +#define RR_TYPE_SHORT 0 +#define RR_TYPE_LONG 1 +#define RR_TYPE_SHORT_PRIV 2 +#define RR_TYPE_LONG_PRIV 3 +#define NUM_SHORT_LBW_RR 14 +#define NUM_LONG_LBW_RR 4 +#define NUM_SHORT_HBW_RR 6 +#define NUM_LONG_HBW_RR 4 + +/* RAZWI initiator coordinates- X- 5 bits, Y- 4 bits */ +#define RAZWI_INITIATOR_X_SHIFT 0 +#define RAZWI_INITIATOR_X_MASK 0x1F +#define RAZWI_INITIATOR_Y_SHIFT 5 +#define RAZWI_INITIATOR_Y_MASK 0xF + +#define RTR_ID_X_Y(x, y) \ + ((((y) & RAZWI_INITIATOR_Y_MASK) << RAZWI_INITIATOR_Y_SHIFT) | \ + (((x) & RAZWI_INITIATOR_X_MASK) << RAZWI_INITIATOR_X_SHIFT)) + +/* decoders have separate mask */ +#define HW_CAP_DEC_SHIFT 0 +#define HW_CAP_DEC_MASK GENMASK_ULL(9, 0) + +/* TPCs have separate mask */ +#define HW_CAP_TPC_SHIFT 0 +#define HW_CAP_TPC_MASK GENMASK_ULL(24, 0) + +/* nics have separate mask */ +#define HW_CAP_NIC_SHIFT 0 +#define HW_CAP_NIC_MASK GENMASK_ULL(NIC_NUMBER_OF_ENGINES - 1, 0) + +#define GAUDI2_ARC_PCI_MSB_ADDR(addr) (((addr) & GENMASK_ULL(49, 28)) >> 28) + +#define GAUDI2_SOB_INCREMENT_BY_ONE (FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_MASK, 1) | \ + FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_MASK, 1)) + +enum gaudi2_reserved_sob_id { + GAUDI2_RESERVED_SOB_CS_COMPLETION_FIRST, + GAUDI2_RESERVED_SOB_CS_COMPLETION_LAST = + GAUDI2_RESERVED_SOB_CS_COMPLETION_FIRST + GAUDI2_MAX_PENDING_CS - 1, + GAUDI2_RESERVED_SOB_KDMA_COMPLETION, + GAUDI2_RESERVED_SOB_DEC_NRM_FIRST, + GAUDI2_RESERVED_SOB_DEC_NRM_LAST = + GAUDI2_RESERVED_SOB_DEC_NRM_FIRST + NUMBER_OF_DEC - 1, + GAUDI2_RESERVED_SOB_DEC_ABNRM_FIRST, + GAUDI2_RESERVED_SOB_DEC_ABNRM_LAST = + GAUDI2_RESERVED_SOB_DEC_ABNRM_FIRST + NUMBER_OF_DEC - 1, + GAUDI2_RESERVED_SOB_NUMBER +}; + +enum gaudi2_reserved_mon_id { + GAUDI2_RESERVED_MON_CS_COMPLETION_FIRST, + GAUDI2_RESERVED_MON_CS_COMPLETION_LAST = + GAUDI2_RESERVED_MON_CS_COMPLETION_FIRST + GAUDI2_MAX_PENDING_CS - 1, + GAUDI2_RESERVED_MON_KDMA_COMPLETION, + GAUDI2_RESERVED_MON_DEC_NRM_FIRST, + GAUDI2_RESERVED_MON_DEC_NRM_LAST = + GAUDI2_RESERVED_MON_DEC_NRM_FIRST + 3 * NUMBER_OF_DEC - 1, + GAUDI2_RESERVED_MON_DEC_ABNRM_FIRST, + GAUDI2_RESERVED_MON_DEC_ABNRM_LAST = + GAUDI2_RESERVED_MON_DEC_ABNRM_FIRST + 3 * NUMBER_OF_DEC - 1, + GAUDI2_RESERVED_MON_NUMBER +}; + +enum gaudi2_reserved_cq_id { + GAUDI2_RESERVED_CQ_CS_COMPLETION, + GAUDI2_RESERVED_CQ_KDMA_COMPLETION, + GAUDI2_RESERVED_CQ_NUMBER +}; + +/* + * Gaudi2 subtitute TPCs Numbering + * At most- two faulty TPCs are allowed + * First replacement to a faulty TPC will be TPC24, second- TPC23 + */ +enum substitude_tpc { + FAULTY_TPC_SUBTS_1_TPC_24, + FAULTY_TPC_SUBTS_2_TPC_23, + MAX_FAULTY_TPCS +}; + +enum gaudi2_dma_core_id { + DMA_CORE_ID_PDMA0, /* Dcore 0 */ + DMA_CORE_ID_PDMA1, /* Dcore 0 */ + DMA_CORE_ID_EDMA0, /* Dcore 0 */ + DMA_CORE_ID_EDMA1, /* Dcore 0 */ + DMA_CORE_ID_EDMA2, /* Dcore 1 */ + DMA_CORE_ID_EDMA3, /* Dcore 1 */ + DMA_CORE_ID_EDMA4, /* Dcore 2 */ + DMA_CORE_ID_EDMA5, /* Dcore 2 */ + DMA_CORE_ID_EDMA6, /* Dcore 3 */ + DMA_CORE_ID_EDMA7, /* Dcore 3 */ + DMA_CORE_ID_KDMA, /* Dcore 0 */ + DMA_CORE_ID_SIZE +}; + +enum gaudi2_rotator_id { + ROTATOR_ID_0, + ROTATOR_ID_1, + ROTATOR_ID_SIZE, +}; + +enum gaudi2_mme_id { + MME_ID_DCORE0, + MME_ID_DCORE1, + MME_ID_DCORE2, + MME_ID_DCORE3, + MME_ID_SIZE, +}; + +enum gaudi2_tpc_id { + TPC_ID_DCORE0_TPC0, + TPC_ID_DCORE0_TPC1, + TPC_ID_DCORE0_TPC2, + TPC_ID_DCORE0_TPC3, + TPC_ID_DCORE0_TPC4, + TPC_ID_DCORE0_TPC5, + TPC_ID_DCORE1_TPC0, + TPC_ID_DCORE1_TPC1, + TPC_ID_DCORE1_TPC2, + TPC_ID_DCORE1_TPC3, + TPC_ID_DCORE1_TPC4, + TPC_ID_DCORE1_TPC5, + TPC_ID_DCORE2_TPC0, + TPC_ID_DCORE2_TPC1, + TPC_ID_DCORE2_TPC2, + TPC_ID_DCORE2_TPC3, + TPC_ID_DCORE2_TPC4, + TPC_ID_DCORE2_TPC5, + TPC_ID_DCORE3_TPC0, + TPC_ID_DCORE3_TPC1, + TPC_ID_DCORE3_TPC2, + TPC_ID_DCORE3_TPC3, + TPC_ID_DCORE3_TPC4, + TPC_ID_DCORE3_TPC5, + /* the PCI TPC is placed last (mapped liked HW) */ + TPC_ID_DCORE0_TPC6, + TPC_ID_SIZE, +}; + +enum gaudi2_dec_id { + DEC_ID_DCORE0_DEC0, + DEC_ID_DCORE0_DEC1, + DEC_ID_DCORE1_DEC0, + DEC_ID_DCORE1_DEC1, + DEC_ID_DCORE2_DEC0, + DEC_ID_DCORE2_DEC1, + DEC_ID_DCORE3_DEC0, + DEC_ID_DCORE3_DEC1, + DEC_ID_PCIE_VDEC0, + DEC_ID_PCIE_VDEC1, + DEC_ID_SIZE, +}; + +enum gaudi2_hbm_id { + HBM_ID0, + HBM_ID1, + HBM_ID2, + HBM_ID3, + HBM_ID4, + HBM_ID5, + HBM_ID_SIZE, +}; + +/* specific EDMA enumeration */ +enum gaudi2_edma_id { + EDMA_ID_DCORE0_INSTANCE0, + EDMA_ID_DCORE0_INSTANCE1, + EDMA_ID_DCORE1_INSTANCE0, + EDMA_ID_DCORE1_INSTANCE1, + EDMA_ID_DCORE2_INSTANCE0, + EDMA_ID_DCORE2_INSTANCE1, + EDMA_ID_DCORE3_INSTANCE0, + EDMA_ID_DCORE3_INSTANCE1, + EDMA_ID_SIZE, +}; + +/* User interrupt count is aligned with HW CQ count. + * We have 64 CQ's per dcore, CQ0 in dcore 0 is reserved for legacy mode + */ +#define GAUDI2_NUM_USER_INTERRUPTS 255 + +enum gaudi2_irq_num { + GAUDI2_IRQ_NUM_EVENT_QUEUE = GAUDI2_EVENT_QUEUE_MSIX_IDX, + GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM, + GAUDI2_IRQ_NUM_DCORE0_DEC0_ABNRM, + GAUDI2_IRQ_NUM_DCORE0_DEC1_NRM, + GAUDI2_IRQ_NUM_DCORE0_DEC1_ABNRM, + GAUDI2_IRQ_NUM_DCORE1_DEC0_NRM, + GAUDI2_IRQ_NUM_DCORE1_DEC0_ABNRM, + GAUDI2_IRQ_NUM_DCORE1_DEC1_NRM, + GAUDI2_IRQ_NUM_DCORE1_DEC1_ABNRM, + GAUDI2_IRQ_NUM_DCORE2_DEC0_NRM, + GAUDI2_IRQ_NUM_DCORE2_DEC0_ABNRM, + GAUDI2_IRQ_NUM_DCORE2_DEC1_NRM, + GAUDI2_IRQ_NUM_DCORE2_DEC1_ABNRM, + GAUDI2_IRQ_NUM_DCORE3_DEC0_NRM, + GAUDI2_IRQ_NUM_DCORE3_DEC0_ABNRM, + GAUDI2_IRQ_NUM_DCORE3_DEC1_NRM, + GAUDI2_IRQ_NUM_DCORE3_DEC1_ABNRM, + GAUDI2_IRQ_NUM_SHARED_DEC0_NRM, + GAUDI2_IRQ_NUM_SHARED_DEC0_ABNRM, + GAUDI2_IRQ_NUM_SHARED_DEC1_NRM, + GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM, + GAUDI2_IRQ_NUM_COMPLETION, + GAUDI2_IRQ_NUM_NIC_PORT_FIRST, + GAUDI2_IRQ_NUM_NIC_PORT_LAST = (GAUDI2_IRQ_NUM_NIC_PORT_FIRST + NIC_NUMBER_OF_PORTS - 1), + GAUDI2_IRQ_NUM_RESERVED_FIRST, + GAUDI2_IRQ_NUM_RESERVED_LAST = (GAUDI2_MSIX_ENTRIES - GAUDI2_NUM_USER_INTERRUPTS - 1), + GAUDI2_IRQ_NUM_USER_FIRST, + GAUDI2_IRQ_NUM_USER_LAST = (GAUDI2_IRQ_NUM_USER_FIRST + GAUDI2_NUM_USER_INTERRUPTS - 1), + GAUDI2_IRQ_NUM_LAST = (GAUDI2_MSIX_ENTRIES - 1) +}; + +static_assert(GAUDI2_IRQ_NUM_USER_FIRST > GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM); + +/** + * struct dup_block_ctx - context to initialize unit instances across multiple + * blocks where block can be either a dcore of duplicated + * common module. this code relies on constant offsets + * of blocks and unit instances in a block. + * @instance_cfg_fn: instance specific configuration function. + * @data: private configuration data. + * @base: base address of the first instance in the first block. + * @block_off: subsequent blocks address spacing. + * @instance_off: subsequent block's instances address spacing. + * @enabled_mask: mask of enabled instances (1- enabled, 0- disabled). + * @blocks: number of blocks. + * @instances: unit instances per block. + */ +struct dup_block_ctx { + void (*instance_cfg_fn)(struct hl_device *hdev, u64 base, void *data); + void *data; + u64 base; + u64 block_off; + u64 instance_off; + u64 enabled_mask; + unsigned int blocks; + unsigned int instances; +}; + +/** + * struct gaudi2_device - ASIC specific manage structure. + * @cpucp_info_get: get information on device from CPU-CP + * @mapped_blocks: array that holds the base address and size of all blocks + * the user can map. + * @lfsr_rand_seeds: array of MME ACC random seeds to set. + * @hw_queues_lock: protects the H/W queues from concurrent access. + * @kdma_lock: protects the KDMA engine from concurrent access. + * @scratchpad_kernel_address: general purpose PAGE_SIZE contiguous memory, + * this memory region should be write-only. + * currently used for HBW QMAN writes which is + * redundant. + * @scratchpad_bus_address: scratchpad bus address + * @virt_msix_db_cpu_addr: host memory page for the virtual MSI-X doorbell. + * @virt_msix_db_dma_addr: bus address of the page for the virtual MSI-X doorbell. + * @dram_bar_cur_addr: current address of DRAM PCI bar. + * @hw_cap_initialized: This field contains a bit per H/W engine. When that + * engine is initialized, that bit is set by the driver to + * signal we can use this engine in later code paths. + * Each bit is cleared upon reset of its corresponding H/W + * engine. + * @active_hw_arc: This field contains a bit per ARC of an H/W engine with + * exception of TPC and NIC engines. Once an engine arc is + * initialized, its respective bit is set. Driver can uniquely + * identify each initialized ARC and use this information in + * later code paths. Each respective bit is cleared upon reset + * of its corresponding ARC of the H/W engine. + * @dec_hw_cap_initialized: This field contains a bit per decoder H/W engine. + * When that engine is initialized, that bit is set by + * the driver to signal we can use this engine in later + * code paths. + * Each bit is cleared upon reset of its corresponding H/W + * engine. + * @tpc_hw_cap_initialized: This field contains a bit per TPC H/W engine. + * When that engine is initialized, that bit is set by + * the driver to signal we can use this engine in later + * code paths. + * Each bit is cleared upon reset of its corresponding H/W + * engine. + * @active_tpc_arc: This field contains a bit per ARC of the TPC engines. + * Once an engine arc is initialized, its respective bit is + * set. Each respective bit is cleared upon reset of its + * corresponding ARC of the TPC engine. + * @nic_hw_cap_initialized: This field contains a bit per nic H/W engine. + * @active_nic_arc: This field contains a bit per ARC of the NIC engines. + * Once an engine arc is initialized, its respective bit is + * set. Each respective bit is cleared upon reset of its + * corresponding ARC of the NIC engine. + * @hw_events: array that holds all H/W events that are defined valid. + * @events_stat: array that holds histogram of all received events. + * @events_stat_aggregate: same as events_stat but doesn't get cleared on reset. + * @num_of_valid_hw_events: used to hold the number of valid H/W events. + * @nic_ports: array that holds all NIC ports manage structures. + * @nic_macros: array that holds all NIC macro manage structures. + * @core_info: core info to be used by the Ethernet driver. + * @aux_ops: functions for core <-> aux drivers communication. + * @flush_db_fifo: flag to force flush DB FIFO after a write. + * @hbm_cfg: HBM subsystem settings + * @hw_queues_lock_mutex: used by simulator instead of hw_queues_lock. + * @kdma_lock_mutex: used by simulator instead of kdma_lock. + * @use_deprecated_event_mappings: use old event mappings which are about to be + * deprecated + */ +struct gaudi2_device { + int (*cpucp_info_get)(struct hl_device *hdev); + + struct user_mapped_block mapped_blocks[NUM_USER_MAPPED_BLOCKS]; + int lfsr_rand_seeds[MME_NUM_OF_LFSR_SEEDS]; + + spinlock_t hw_queues_lock; + spinlock_t kdma_lock; + + void *scratchpad_kernel_address; + dma_addr_t scratchpad_bus_address; + + void *virt_msix_db_cpu_addr; + dma_addr_t virt_msix_db_dma_addr; + + u64 dram_bar_cur_addr; + u64 hw_cap_initialized; + u64 active_hw_arc; + u64 dec_hw_cap_initialized; + u64 tpc_hw_cap_initialized; + u64 active_tpc_arc; + u64 nic_hw_cap_initialized; + u64 active_nic_arc; + u32 hw_events[GAUDI2_EVENT_SIZE]; + u32 events_stat[GAUDI2_EVENT_SIZE]; + u32 events_stat_aggregate[GAUDI2_EVENT_SIZE]; + u32 num_of_valid_hw_events; +}; + +extern const u32 gaudi2_dma_core_blocks_bases[DMA_CORE_ID_SIZE]; +extern const u32 gaudi2_qm_blocks_bases[GAUDI2_QUEUE_ID_SIZE]; +extern const u32 gaudi2_mme_acc_blocks_bases[MME_ID_SIZE]; +extern const u32 gaudi2_mme_ctrl_lo_blocks_bases[MME_ID_SIZE]; +extern const u32 edma_stream_base[NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES]; +extern const u32 gaudi2_rot_blocks_bases[ROTATOR_ID_SIZE]; + +void gaudi2_iterate_tpcs(struct hl_device *hdev, struct iterate_module_ctx *ctx); +int gaudi2_coresight_init(struct hl_device *hdev); +int gaudi2_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data); +void gaudi2_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx); +void gaudi2_init_blocks(struct hl_device *hdev, struct dup_block_ctx *cfg_ctx); +bool gaudi2_is_hmmu_enabled(struct hl_device *hdev, int dcore_id, int hmmu_id); +void gaudi2_write_rr_to_all_lbw_rtrs(struct hl_device *hdev, u8 rr_type, u32 rr_index, u64 min_val, + u64 max_val); +void gaudi2_pb_print_security_errors(struct hl_device *hdev, u32 block_addr, u32 cause, + u32 offended_addr); +int gaudi2_init_security(struct hl_device *hdev); +void gaudi2_ack_protection_bits_errors(struct hl_device *hdev); + +#endif /* GAUDI2P_H_ */ diff --git a/drivers/misc/habanalabs/gaudi2/gaudi2_coresight.c b/drivers/misc/habanalabs/gaudi2/gaudi2_coresight.c new file mode 100644 index 000000000000..56c6ab692482 --- /dev/null +++ b/drivers/misc/habanalabs/gaudi2/gaudi2_coresight.c @@ -0,0 +1,2720 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2019-2022 HabanaLabs, Ltd. + * All Rights Reserved. + */ +#include "gaudi2_coresight_regs.h" +#include + +#define GAUDI2_PLDM_CORESIGHT_TIMEOUT_USEC (CORESIGHT_TIMEOUT_USEC * 2000) +#define SPMU_MAX_COUNTERS 6 + +#define COMPONENT_ID_INVALID ((u32)(-1)) +#define MAX_BMONS_PER_UNIT 8 + +enum gaudi2_hif_hmmu_id { + HMMU_ID_DCORE0_HMMU0, + HMMU_ID_DCORE0_HMMU1, + HMMU_ID_DCORE0_HMMU2, + HMMU_ID_DCORE0_HMMU3, + HMMU_ID_DCORE1_HMMU0, + HMMU_ID_DCORE1_HMMU1, + HMMU_ID_DCORE1_HMMU2, + HMMU_ID_DCORE1_HMMU3, + HMMU_ID_DCORE2_HMMU0, + HMMU_ID_DCORE2_HMMU1, + HMMU_ID_DCORE2_HMMU2, + HMMU_ID_DCORE2_HMMU3, + HMMU_ID_DCORE3_HMMU0, + HMMU_ID_DCORE3_HMMU1, + HMMU_ID_DCORE3_HMMU2, + HMMU_ID_DCORE3_HMMU3, + HMMU_ID_SIZE, +}; + +enum gaudi2_xbar_edge_id { + XBAR_EDGE_ID_DCORE0, + XBAR_EDGE_ID_DCORE1, + XBAR_EDGE_ID_DCORE2, + XBAR_EDGE_ID_DCORE3, + XBAR_EDGE_ID_SIZE +}; + +/** + * struct component_config_offsets - per cs_dbg unit - view off all related components indices + * @funnel_id: funnel id - index in debug_funnel_regs + * @etf_id: etf id - index in debug_etf_regs + * @stm_id: stm id - index in debug_stm_regs + * @spmu_id: spmu_id - index in debug_spmu_regs + * @bmon_count: number of bmons per unit + * @bmon_ids: array of bmon id (max size - MAX_BMONS_PER_UNIT) index in debug_bmon_regs + */ +struct component_config_offsets { + u32 funnel_id; + u32 etf_id; + u32 stm_id; + u32 spmu_id; + u32 bmon_count; + u32 bmon_ids[MAX_BMONS_PER_UNIT]; +}; + +static u64 debug_stm_regs[GAUDI2_STM_LAST + 1] = { + [GAUDI2_STM_DCORE0_TPC0_EML] = mmDCORE0_TPC0_EML_STM_BASE, + [GAUDI2_STM_DCORE0_TPC1_EML] = mmDCORE0_TPC1_EML_STM_BASE, + [GAUDI2_STM_DCORE0_TPC2_EML] = mmDCORE0_TPC2_EML_STM_BASE, + [GAUDI2_STM_DCORE0_TPC3_EML] = mmDCORE0_TPC3_EML_STM_BASE, + [GAUDI2_STM_DCORE0_TPC4_EML] = mmDCORE0_TPC4_EML_STM_BASE, + [GAUDI2_STM_DCORE0_TPC5_EML] = mmDCORE0_TPC5_EML_STM_BASE, + [GAUDI2_STM_DCORE0_TPC6_EML] = mmDCORE0_TPC6_EML_STM_BASE, + [GAUDI2_STM_DCORE1_TPC0_EML] = mmDCORE1_TPC0_EML_STM_BASE, + [GAUDI2_STM_DCORE1_TPC1_EML] = mmDCORE1_TPC1_EML_STM_BASE, + [GAUDI2_STM_DCORE1_TPC2_EML] = mmDCORE1_TPC2_EML_STM_BASE, + [GAUDI2_STM_DCORE1_TPC3_EML] = mmDCORE1_TPC3_EML_STM_BASE, + [GAUDI2_STM_DCORE1_TPC4_EML] = mmDCORE1_TPC4_EML_STM_BASE, + [GAUDI2_STM_DCORE1_TPC5_EML] = mmDCORE1_TPC5_EML_STM_BASE, + [GAUDI2_STM_DCORE2_TPC0_EML] = mmDCORE2_TPC0_EML_STM_BASE, + [GAUDI2_STM_DCORE2_TPC1_EML] = mmDCORE2_TPC1_EML_STM_BASE, + [GAUDI2_STM_DCORE2_TPC2_EML] = mmDCORE2_TPC2_EML_STM_BASE, + [GAUDI2_STM_DCORE2_TPC3_EML] = mmDCORE2_TPC3_EML_STM_BASE, + [GAUDI2_STM_DCORE2_TPC4_EML] = mmDCORE2_TPC4_EML_STM_BASE, + [GAUDI2_STM_DCORE2_TPC5_EML] = mmDCORE2_TPC5_EML_STM_BASE, + [GAUDI2_STM_DCORE3_TPC0_EML] = mmDCORE3_TPC0_EML_STM_BASE, + [GAUDI2_STM_DCORE3_TPC1_EML] = mmDCORE3_TPC1_EML_STM_BASE, + [GAUDI2_STM_DCORE3_TPC2_EML] = mmDCORE3_TPC2_EML_STM_BASE, + [GAUDI2_STM_DCORE3_TPC3_EML] = mmDCORE3_TPC3_EML_STM_BASE, + [GAUDI2_STM_DCORE3_TPC4_EML] = mmDCORE3_TPC4_EML_STM_BASE, + [GAUDI2_STM_DCORE3_TPC5_EML] = mmDCORE3_TPC5_EML_STM_BASE, + [GAUDI2_STM_DCORE0_HMMU0_CS] = mmDCORE0_HMMU0_CS_STM_BASE, + [GAUDI2_STM_DCORE0_HMMU1_CS] = mmDCORE0_HMMU1_CS_STM_BASE, + [GAUDI2_STM_DCORE0_HMMU2_CS] = mmDCORE0_HMMU2_CS_STM_BASE, + [GAUDI2_STM_DCORE0_HMMU3_CS] = mmDCORE0_HMMU3_CS_STM_BASE, + [GAUDI2_STM_DCORE0_MME_CTRL] = mmDCORE0_MME_CTRL_STM_BASE, + [GAUDI2_STM_DCORE0_MME_SBTE0] = mmDCORE0_MME_SBTE0_STM_BASE, + [GAUDI2_STM_DCORE0_MME_SBTE1] = mmDCORE0_MME_SBTE1_STM_BASE, + [GAUDI2_STM_DCORE0_MME_SBTE2] = mmDCORE0_MME_SBTE2_STM_BASE, + [GAUDI2_STM_DCORE0_MME_SBTE3] = mmDCORE0_MME_SBTE3_STM_BASE, + [GAUDI2_STM_DCORE0_MME_SBTE4] = mmDCORE0_MME_SBTE4_STM_BASE, + [GAUDI2_STM_DCORE0_MME_ACC] = mmDCORE0_MME_ACC_STM_BASE, + [GAUDI2_STM_DCORE0_SM] = mmDCORE0_SM_STM_BASE, + [GAUDI2_STM_DCORE0_EDMA0_CS] = mmDCORE0_EDMA0_CS_STM_BASE, + [GAUDI2_STM_DCORE0_EDMA1_CS] = mmDCORE0_EDMA1_CS_STM_BASE, + [GAUDI2_STM_DCORE0_VDEC0_CS] = mmDCORE0_VDEC0_CS_STM_BASE, + [GAUDI2_STM_DCORE0_VDEC1_CS] = mmDCORE0_VDEC1_CS_STM_BASE, + [GAUDI2_STM_DCORE1_HMMU0_CS] = mmDCORE1_HMMU0_CS_STM_BASE, + [GAUDI2_STM_DCORE1_HMMU1_CS] = mmDCORE1_HMMU1_CS_STM_BASE, + [GAUDI2_STM_DCORE1_HMMU2_CS] = mmDCORE1_HMMU2_CS_STM_BASE, + [GAUDI2_STM_DCORE1_HMMU3_CS] = mmDCORE1_HMMU3_CS_STM_BASE, + [GAUDI2_STM_DCORE1_MME_CTRL] = mmDCORE1_MME_CTRL_STM_BASE, + [GAUDI2_STM_DCORE1_MME_SBTE0] = mmDCORE1_MME_SBTE0_STM_BASE, + [GAUDI2_STM_DCORE1_MME_SBTE1] = mmDCORE1_MME_SBTE1_STM_BASE, + [GAUDI2_STM_DCORE1_MME_SBTE2] = mmDCORE1_MME_SBTE2_STM_BASE, + [GAUDI2_STM_DCORE1_MME_SBTE3] = mmDCORE1_MME_SBTE3_STM_BASE, + [GAUDI2_STM_DCORE1_MME_SBTE4] = mmDCORE1_MME_SBTE4_STM_BASE, + [GAUDI2_STM_DCORE1_MME_ACC] = mmDCORE1_MME_ACC_STM_BASE, + [GAUDI2_STM_DCORE1_SM] = mmDCORE1_SM_STM_BASE, + [GAUDI2_STM_DCORE1_EDMA0_CS] = mmDCORE1_EDMA0_CS_STM_BASE, + [GAUDI2_STM_DCORE1_EDMA1_CS] = mmDCORE1_EDMA1_CS_STM_BASE, + [GAUDI2_STM_DCORE1_VDEC0_CS] = mmDCORE1_VDEC0_CS_STM_BASE, + [GAUDI2_STM_DCORE1_VDEC1_CS] = mmDCORE1_VDEC1_CS_STM_BASE, + [GAUDI2_STM_DCORE2_HMMU0_CS] = mmDCORE2_HMMU0_CS_STM_BASE, + [GAUDI2_STM_DCORE2_HMMU1_CS] = mmDCORE2_HMMU1_CS_STM_BASE, + [GAUDI2_STM_DCORE2_HMMU2_CS] = mmDCORE2_HMMU2_CS_STM_BASE, + [GAUDI2_STM_DCORE2_HMMU3_CS] = mmDCORE2_HMMU3_CS_STM_BASE, + [GAUDI2_STM_DCORE2_MME_CTRL] = mmDCORE2_MME_CTRL_STM_BASE, + [GAUDI2_STM_DCORE2_MME_SBTE0] = mmDCORE2_MME_SBTE0_STM_BASE, + [GAUDI2_STM_DCORE2_MME_SBTE1] = mmDCORE2_MME_SBTE1_STM_BASE, + [GAUDI2_STM_DCORE2_MME_SBTE2] = mmDCORE2_MME_SBTE2_STM_BASE, + [GAUDI2_STM_DCORE2_MME_SBTE3] = mmDCORE2_MME_SBTE3_STM_BASE, + [GAUDI2_STM_DCORE2_MME_SBTE4] = mmDCORE2_MME_SBTE4_STM_BASE, + [GAUDI2_STM_DCORE2_MME_ACC] = mmDCORE2_MME_ACC_STM_BASE, + [GAUDI2_STM_DCORE2_SM] = mmDCORE2_SM_STM_BASE, + [GAUDI2_STM_DCORE2_EDMA0_CS] = mmDCORE2_EDMA0_CS_STM_BASE, + [GAUDI2_STM_DCORE2_EDMA1_CS] = mmDCORE2_EDMA1_CS_STM_BASE, + [GAUDI2_STM_DCORE2_VDEC0_CS] = mmDCORE2_VDEC0_CS_STM_BASE, + [GAUDI2_STM_DCORE2_VDEC1_CS] = mmDCORE2_VDEC1_CS_STM_BASE, + [GAUDI2_STM_DCORE3_HMMU0_CS] = mmDCORE3_HMMU0_CS_STM_BASE, + [GAUDI2_STM_DCORE3_HMMU1_CS] = mmDCORE3_HMMU1_CS_STM_BASE, + [GAUDI2_STM_DCORE3_HMMU2_CS] = mmDCORE3_HMMU2_CS_STM_BASE, + [GAUDI2_STM_DCORE3_HMMU3_CS] = mmDCORE3_HMMU3_CS_STM_BASE, + [GAUDI2_STM_DCORE3_MME_CTRL] = mmDCORE3_MME_CTRL_STM_BASE, + [GAUDI2_STM_DCORE3_MME_SBTE0] = mmDCORE3_MME_SBTE0_STM_BASE, + [GAUDI2_STM_DCORE3_MME_SBTE1] = mmDCORE3_MME_SBTE1_STM_BASE, + [GAUDI2_STM_DCORE3_MME_SBTE2] = mmDCORE3_MME_SBTE2_STM_BASE, + [GAUDI2_STM_DCORE3_MME_SBTE3] = mmDCORE3_MME_SBTE3_STM_BASE, + [GAUDI2_STM_DCORE3_MME_SBTE4] = mmDCORE3_MME_SBTE4_STM_BASE, + [GAUDI2_STM_DCORE3_MME_ACC] = mmDCORE3_MME_ACC_STM_BASE, + [GAUDI2_STM_DCORE3_SM] = mmDCORE3_SM_STM_BASE, + [GAUDI2_STM_DCORE3_EDMA0_CS] = mmDCORE3_EDMA0_CS_STM_BASE, + [GAUDI2_STM_DCORE3_EDMA1_CS] = mmDCORE3_EDMA1_CS_STM_BASE, + [GAUDI2_STM_DCORE3_VDEC0_CS] = mmDCORE3_VDEC0_CS_STM_BASE, + [GAUDI2_STM_DCORE3_VDEC1_CS] = mmDCORE3_VDEC1_CS_STM_BASE, + [GAUDI2_STM_PCIE] = mmPCIE_STM_BASE, + [GAUDI2_STM_PSOC] = mmPSOC_STM_BASE, + [GAUDI2_STM_PSOC_ARC0_CS] = mmPSOC_ARC0_CS_STM_BASE, + [GAUDI2_STM_PSOC_ARC1_CS] = mmPSOC_ARC1_CS_STM_BASE, + [GAUDI2_STM_PDMA0_CS] = mmPDMA0_CS_STM_BASE, + [GAUDI2_STM_PDMA1_CS] = mmPDMA1_CS_STM_BASE, + [GAUDI2_STM_CPU] = mmCPU_STM_BASE, + [GAUDI2_STM_PMMU_CS] = mmPMMU_CS_STM_BASE, + [GAUDI2_STM_ROT0_CS] = mmROT0_CS_STM_BASE, + [GAUDI2_STM_ROT1_CS] = mmROT1_CS_STM_BASE, + [GAUDI2_STM_ARC_FARM_CS] = mmARC_FARM_CS_STM_BASE, + [GAUDI2_STM_KDMA_CS] = mmKDMA_CS_STM_BASE, + [GAUDI2_STM_PCIE_VDEC0_CS] = mmPCIE_VDEC0_CS_STM_BASE, + [GAUDI2_STM_PCIE_VDEC1_CS] = mmPCIE_VDEC1_CS_STM_BASE, + [GAUDI2_STM_HBM0_MC0_CS] = mmHBM0_MC0_CS_STM_BASE, + [GAUDI2_STM_HBM0_MC1_CS] = mmHBM0_MC1_CS_STM_BASE, + [GAUDI2_STM_HBM1_MC0_CS] = mmHBM1_MC0_CS_STM_BASE, + [GAUDI2_STM_HBM1_MC1_CS] = mmHBM1_MC1_CS_STM_BASE, + [GAUDI2_STM_HBM2_MC0_CS] = mmHBM2_MC0_CS_STM_BASE, + [GAUDI2_STM_HBM2_MC1_CS] = mmHBM2_MC1_CS_STM_BASE, + [GAUDI2_STM_HBM3_MC0_CS] = mmHBM3_MC0_CS_STM_BASE, + [GAUDI2_STM_HBM3_MC1_CS] = mmHBM3_MC1_CS_STM_BASE, + [GAUDI2_STM_HBM4_MC0_CS] = mmHBM4_MC0_CS_STM_BASE, + [GAUDI2_STM_HBM4_MC1_CS] = mmHBM4_MC1_CS_STM_BASE, + [GAUDI2_STM_HBM5_MC0_CS] = mmHBM5_MC0_CS_STM_BASE, + [GAUDI2_STM_HBM5_MC1_CS] = mmHBM5_MC1_CS_STM_BASE, + [GAUDI2_STM_NIC0_DBG_0] = mmNIC0_DBG_STM_0_BASE, + [GAUDI2_STM_NIC0_DBG_1] = mmNIC0_DBG_STM_1_BASE, + [GAUDI2_STM_NIC1_DBG_0] = mmNIC1_DBG_STM_0_BASE, + [GAUDI2_STM_NIC1_DBG_1] = mmNIC1_DBG_STM_1_BASE, + [GAUDI2_STM_NIC2_DBG_0] = mmNIC2_DBG_STM_0_BASE, + [GAUDI2_STM_NIC2_DBG_1] = mmNIC2_DBG_STM_1_BASE, + [GAUDI2_STM_NIC3_DBG_0] = mmNIC3_DBG_STM_0_BASE, + [GAUDI2_STM_NIC3_DBG_1] = mmNIC3_DBG_STM_1_BASE, + [GAUDI2_STM_NIC4_DBG_0] = mmNIC4_DBG_STM_0_BASE, + [GAUDI2_STM_NIC4_DBG_1] = mmNIC4_DBG_STM_1_BASE, + [GAUDI2_STM_NIC5_DBG_0] = mmNIC5_DBG_STM_0_BASE, + [GAUDI2_STM_NIC5_DBG_1] = mmNIC5_DBG_STM_1_BASE, + [GAUDI2_STM_NIC6_DBG_0] = mmNIC6_DBG_STM_0_BASE, + [GAUDI2_STM_NIC6_DBG_1] = mmNIC6_DBG_STM_1_BASE, + [GAUDI2_STM_NIC7_DBG_0] = mmNIC7_DBG_STM_0_BASE, + [GAUDI2_STM_NIC7_DBG_1] = mmNIC7_DBG_STM_1_BASE, + [GAUDI2_STM_NIC8_DBG_0] = mmNIC8_DBG_STM_0_BASE, + [GAUDI2_STM_NIC8_DBG_1] = mmNIC8_DBG_STM_1_BASE, + [GAUDI2_STM_NIC9_DBG_0] = mmNIC9_DBG_STM_0_BASE, + [GAUDI2_STM_NIC9_DBG_1] = mmNIC9_DBG_STM_1_BASE, + [GAUDI2_STM_NIC10_DBG_0] = mmNIC10_DBG_STM_0_BASE, + [GAUDI2_STM_NIC10_DBG_1] = mmNIC10_DBG_STM_1_BASE, + [GAUDI2_STM_NIC11_DBG_0] = mmNIC11_DBG_STM_0_BASE, + [GAUDI2_STM_NIC11_DBG_1] = mmNIC11_DBG_STM_1_BASE +}; + +static u64 debug_etf_regs[GAUDI2_ETF_LAST + 1] = { + [GAUDI2_ETF_DCORE0_TPC0_EML] = mmDCORE0_TPC0_EML_ETF_BASE, + [GAUDI2_ETF_DCORE0_TPC1_EML] = mmDCORE0_TPC1_EML_ETF_BASE, + [GAUDI2_ETF_DCORE0_TPC2_EML] = mmDCORE0_TPC2_EML_ETF_BASE, + [GAUDI2_ETF_DCORE0_TPC3_EML] = mmDCORE0_TPC3_EML_ETF_BASE, + [GAUDI2_ETF_DCORE0_TPC4_EML] = mmDCORE0_TPC4_EML_ETF_BASE, + [GAUDI2_ETF_DCORE0_TPC5_EML] = mmDCORE0_TPC5_EML_ETF_BASE, + [GAUDI2_ETF_DCORE0_TPC6_EML] = mmDCORE0_TPC6_EML_ETF_BASE, + [GAUDI2_ETF_DCORE1_TPC0_EML] = mmDCORE1_TPC0_EML_ETF_BASE, + [GAUDI2_ETF_DCORE1_TPC1_EML] = mmDCORE1_TPC1_EML_ETF_BASE, + [GAUDI2_ETF_DCORE1_TPC2_EML] = mmDCORE1_TPC2_EML_ETF_BASE, + [GAUDI2_ETF_DCORE1_TPC3_EML] = mmDCORE1_TPC3_EML_ETF_BASE, + [GAUDI2_ETF_DCORE1_TPC4_EML] = mmDCORE1_TPC4_EML_ETF_BASE, + [GAUDI2_ETF_DCORE1_TPC5_EML] = mmDCORE1_TPC5_EML_ETF_BASE, + [GAUDI2_ETF_DCORE2_TPC0_EML] = mmDCORE2_TPC0_EML_ETF_BASE, + [GAUDI2_ETF_DCORE2_TPC1_EML] = mmDCORE2_TPC1_EML_ETF_BASE, + [GAUDI2_ETF_DCORE2_TPC2_EML] = mmDCORE2_TPC2_EML_ETF_BASE, + [GAUDI2_ETF_DCORE2_TPC3_EML] = mmDCORE2_TPC3_EML_ETF_BASE, + [GAUDI2_ETF_DCORE2_TPC4_EML] = mmDCORE2_TPC4_EML_ETF_BASE, + [GAUDI2_ETF_DCORE2_TPC5_EML] = mmDCORE2_TPC5_EML_ETF_BASE, + [GAUDI2_ETF_DCORE3_TPC0_EML] = mmDCORE3_TPC0_EML_ETF_BASE, + [GAUDI2_ETF_DCORE3_TPC1_EML] = mmDCORE3_TPC1_EML_ETF_BASE, + [GAUDI2_ETF_DCORE3_TPC2_EML] = mmDCORE3_TPC2_EML_ETF_BASE, + [GAUDI2_ETF_DCORE3_TPC3_EML] = mmDCORE3_TPC3_EML_ETF_BASE, + [GAUDI2_ETF_DCORE3_TPC4_EML] = mmDCORE3_TPC4_EML_ETF_BASE, + [GAUDI2_ETF_DCORE3_TPC5_EML] = mmDCORE3_TPC5_EML_ETF_BASE, + [GAUDI2_ETF_DCORE0_HMMU0_CS] = mmDCORE0_HMMU0_CS_ETF_BASE, + [GAUDI2_ETF_DCORE0_HMMU1_CS] = mmDCORE0_HMMU1_CS_ETF_BASE, + [GAUDI2_ETF_DCORE0_HMMU2_CS] = mmDCORE0_HMMU2_CS_ETF_BASE, + [GAUDI2_ETF_DCORE0_HMMU3_CS] = mmDCORE0_HMMU3_CS_ETF_BASE, + [GAUDI2_ETF_DCORE0_MME_CTRL] = mmDCORE0_MME_CTRL_ETF_BASE, + [GAUDI2_ETF_DCORE0_MME_SBTE0] = mmDCORE0_MME_SBTE0_ETF_BASE, + [GAUDI2_ETF_DCORE0_MME_SBTE1] = mmDCORE0_MME_SBTE1_ETF_BASE, + [GAUDI2_ETF_DCORE0_MME_SBTE2] = mmDCORE0_MME_SBTE2_ETF_BASE, + [GAUDI2_ETF_DCORE0_MME_SBTE3] = mmDCORE0_MME_SBTE3_ETF_BASE, + [GAUDI2_ETF_DCORE0_MME_SBTE4] = mmDCORE0_MME_SBTE4_ETF_BASE, + [GAUDI2_ETF_DCORE0_MME_ACC] = mmDCORE0_MME_ACC_ETF_BASE, + [GAUDI2_ETF_DCORE0_SM] = mmDCORE0_SM_ETF_BASE, + [GAUDI2_ETF_DCORE0_EDMA0_CS] = mmDCORE0_EDMA0_CS_ETF_BASE, + [GAUDI2_ETF_DCORE0_EDMA1_CS] = mmDCORE0_EDMA1_CS_ETF_BASE, + [GAUDI2_ETF_DCORE0_VDEC0_CS] = mmDCORE0_VDEC0_CS_ETF_BASE, + [GAUDI2_ETF_DCORE0_VDEC1_CS] = mmDCORE0_VDEC1_CS_ETF_BASE, + [GAUDI2_ETF_DCORE1_HMMU0_CS] = mmDCORE1_HMMU0_CS_ETF_BASE, + [GAUDI2_ETF_DCORE1_HMMU1_CS] = mmDCORE1_HMMU1_CS_ETF_BASE, + [GAUDI2_ETF_DCORE1_HMMU2_CS] = mmDCORE1_HMMU2_CS_ETF_BASE, + [GAUDI2_ETF_DCORE1_HMMU3_CS] = mmDCORE1_HMMU3_CS_ETF_BASE, + [GAUDI2_ETF_DCORE1_MME_CTRL] = mmDCORE1_MME_CTRL_ETF_BASE, + [GAUDI2_ETF_DCORE1_MME_SBTE0] = mmDCORE1_MME_SBTE0_ETF_BASE, + [GAUDI2_ETF_DCORE1_MME_SBTE1] = mmDCORE1_MME_SBTE1_ETF_BASE, + [GAUDI2_ETF_DCORE1_MME_SBTE2] = mmDCORE1_MME_SBTE2_ETF_BASE, + [GAUDI2_ETF_DCORE1_MME_SBTE3] = mmDCORE1_MME_SBTE3_ETF_BASE, + [GAUDI2_ETF_DCORE1_MME_SBTE4] = mmDCORE1_MME_SBTE4_ETF_BASE, + [GAUDI2_ETF_DCORE1_MME_ACC] = mmDCORE1_MME_ACC_ETF_BASE, + [GAUDI2_ETF_DCORE1_SM] = mmDCORE1_SM_ETF_BASE, + [GAUDI2_ETF_DCORE1_EDMA0_CS] = mmDCORE1_EDMA0_CS_ETF_BASE, + [GAUDI2_ETF_DCORE1_EDMA1_CS] = mmDCORE1_EDMA1_CS_ETF_BASE, + [GAUDI2_ETF_DCORE1_VDEC0_CS] = mmDCORE1_VDEC0_CS_ETF_BASE, + [GAUDI2_ETF_DCORE1_VDEC1_CS] = mmDCORE1_VDEC1_CS_ETF_BASE, + [GAUDI2_ETF_DCORE2_HMMU0_CS] = mmDCORE2_HMMU0_CS_ETF_BASE, + [GAUDI2_ETF_DCORE2_HMMU1_CS] = mmDCORE2_HMMU1_CS_ETF_BASE, + [GAUDI2_ETF_DCORE2_HMMU2_CS] = mmDCORE2_HMMU2_CS_ETF_BASE, + [GAUDI2_ETF_DCORE2_HMMU3_CS] = mmDCORE2_HMMU3_CS_ETF_BASE, + [GAUDI2_ETF_DCORE2_MME_CTRL] = mmDCORE2_MME_CTRL_ETF_BASE, + [GAUDI2_ETF_DCORE2_MME_SBTE0] = mmDCORE2_MME_SBTE0_ETF_BASE, + [GAUDI2_ETF_DCORE2_MME_SBTE1] = mmDCORE2_MME_SBTE1_ETF_BASE, + [GAUDI2_ETF_DCORE2_MME_SBTE2] = mmDCORE2_MME_SBTE2_ETF_BASE, + [GAUDI2_ETF_DCORE2_MME_SBTE3] = mmDCORE2_MME_SBTE3_ETF_BASE, + [GAUDI2_ETF_DCORE2_MME_SBTE4] = mmDCORE2_MME_SBTE4_ETF_BASE, + [GAUDI2_ETF_DCORE2_MME_ACC] = mmDCORE2_MME_ACC_ETF_BASE, + [GAUDI2_ETF_DCORE2_SM] = mmDCORE2_SM_ETF_BASE, + [GAUDI2_ETF_DCORE2_EDMA0_CS] = mmDCORE2_EDMA0_CS_ETF_BASE, + [GAUDI2_ETF_DCORE2_EDMA1_CS] = mmDCORE2_EDMA1_CS_ETF_BASE, + [GAUDI2_ETF_DCORE2_VDEC0_CS] = mmDCORE2_VDEC0_CS_ETF_BASE, + [GAUDI2_ETF_DCORE2_VDEC1_CS] = mmDCORE2_VDEC1_CS_ETF_BASE, + [GAUDI2_ETF_DCORE3_HMMU0_CS] = mmDCORE3_HMMU0_CS_ETF_BASE, + [GAUDI2_ETF_DCORE3_HMMU1_CS] = mmDCORE3_HMMU1_CS_ETF_BASE, + [GAUDI2_ETF_DCORE3_HMMU2_CS] = mmDCORE3_HMMU2_CS_ETF_BASE, + [GAUDI2_ETF_DCORE3_HMMU3_CS] = mmDCORE3_HMMU3_CS_ETF_BASE, + [GAUDI2_ETF_DCORE3_MME_CTRL] = mmDCORE3_MME_CTRL_ETF_BASE, + [GAUDI2_ETF_DCORE3_MME_SBTE0] = mmDCORE3_MME_SBTE0_ETF_BASE, + [GAUDI2_ETF_DCORE3_MME_SBTE1] = mmDCORE3_MME_SBTE1_ETF_BASE, + [GAUDI2_ETF_DCORE3_MME_SBTE2] = mmDCORE3_MME_SBTE2_ETF_BASE, + [GAUDI2_ETF_DCORE3_MME_SBTE3] = mmDCORE3_MME_SBTE3_ETF_BASE, + [GAUDI2_ETF_DCORE3_MME_SBTE4] = mmDCORE3_MME_SBTE4_ETF_BASE, + [GAUDI2_ETF_DCORE3_MME_ACC] = mmDCORE3_MME_ACC_ETF_BASE, + [GAUDI2_ETF_DCORE3_SM] = mmDCORE3_SM_ETF_BASE, + [GAUDI2_ETF_DCORE3_EDMA0_CS] = mmDCORE3_EDMA0_CS_ETF_BASE, + [GAUDI2_ETF_DCORE3_EDMA1_CS] = mmDCORE3_EDMA1_CS_ETF_BASE, + [GAUDI2_ETF_DCORE3_VDEC0_CS] = mmDCORE3_VDEC0_CS_ETF_BASE, + [GAUDI2_ETF_DCORE3_VDEC1_CS] = mmDCORE3_VDEC1_CS_ETF_BASE, + [GAUDI2_ETF_PCIE] = mmPCIE_ETF_BASE, + [GAUDI2_ETF_PSOC] = mmPSOC_ETF_BASE, + [GAUDI2_ETF_PSOC_ARC0_CS] = mmPSOC_ARC0_CS_ETF_BASE, + [GAUDI2_ETF_PSOC_ARC1_CS] = mmPSOC_ARC1_CS_ETF_BASE, + [GAUDI2_ETF_PDMA0_CS] = mmPDMA0_CS_ETF_BASE, + [GAUDI2_ETF_PDMA1_CS] = mmPDMA1_CS_ETF_BASE, + [GAUDI2_ETF_CPU_0] = mmCPU_ETF_0_BASE, + [GAUDI2_ETF_CPU_1] = mmCPU_ETF_1_BASE, + [GAUDI2_ETF_CPU_TRACE] = mmCPU_ETF_TRACE_BASE, + [GAUDI2_ETF_PMMU_CS] = mmPMMU_CS_ETF_BASE, + [GAUDI2_ETF_ROT0_CS] = mmROT0_CS_ETF_BASE, + [GAUDI2_ETF_ROT1_CS] = mmROT1_CS_ETF_BASE, + [GAUDI2_ETF_ARC_FARM_CS] = mmARC_FARM_CS_ETF_BASE, + [GAUDI2_ETF_KDMA_CS] = mmKDMA_CS_ETF_BASE, + [GAUDI2_ETF_PCIE_VDEC0_CS] = mmPCIE_VDEC0_CS_ETF_BASE, + [GAUDI2_ETF_PCIE_VDEC1_CS] = mmPCIE_VDEC1_CS_ETF_BASE, + [GAUDI2_ETF_HBM0_MC0_CS] = mmHBM0_MC0_CS_ETF_BASE, + [GAUDI2_ETF_HBM0_MC1_CS] = mmHBM0_MC1_CS_ETF_BASE, + [GAUDI2_ETF_HBM1_MC0_CS] = mmHBM1_MC0_CS_ETF_BASE, + [GAUDI2_ETF_HBM1_MC1_CS] = mmHBM1_MC1_CS_ETF_BASE, + [GAUDI2_ETF_HBM2_MC0_CS] = mmHBM2_MC0_CS_ETF_BASE, + [GAUDI2_ETF_HBM2_MC1_CS] = mmHBM2_MC1_CS_ETF_BASE, + [GAUDI2_ETF_HBM3_MC0_CS] = mmHBM3_MC0_CS_ETF_BASE, + [GAUDI2_ETF_HBM3_MC1_CS] = mmHBM3_MC1_CS_ETF_BASE, + [GAUDI2_ETF_HBM4_MC0_CS] = mmHBM4_MC0_CS_ETF_BASE, + [GAUDI2_ETF_HBM4_MC1_CS] = mmHBM4_MC1_CS_ETF_BASE, + [GAUDI2_ETF_HBM5_MC0_CS] = mmHBM5_MC0_CS_ETF_BASE, + [GAUDI2_ETF_HBM5_MC1_CS] = mmHBM5_MC1_CS_ETF_BASE, + [GAUDI2_ETF_NIC0_DBG_0] = mmNIC0_DBG_ETF_0_BASE, + [GAUDI2_ETF_NIC0_DBG_1] = mmNIC0_DBG_ETF_1_BASE, + [GAUDI2_ETF_NIC1_DBG_0] = mmNIC1_DBG_ETF_0_BASE, + [GAUDI2_ETF_NIC1_DBG_1] = mmNIC1_DBG_ETF_1_BASE, + [GAUDI2_ETF_NIC2_DBG_0] = mmNIC2_DBG_ETF_0_BASE, + [GAUDI2_ETF_NIC2_DBG_1] = mmNIC2_DBG_ETF_1_BASE, + [GAUDI2_ETF_NIC3_DBG_0] = mmNIC3_DBG_ETF_0_BASE, + [GAUDI2_ETF_NIC3_DBG_1] = mmNIC3_DBG_ETF_1_BASE, + [GAUDI2_ETF_NIC4_DBG_0] = mmNIC4_DBG_ETF_0_BASE, + [GAUDI2_ETF_NIC4_DBG_1] = mmNIC4_DBG_ETF_1_BASE, + [GAUDI2_ETF_NIC5_DBG_0] = mmNIC5_DBG_ETF_0_BASE, + [GAUDI2_ETF_NIC5_DBG_1] = mmNIC5_DBG_ETF_1_BASE, + [GAUDI2_ETF_NIC6_DBG_0] = mmNIC6_DBG_ETF_0_BASE, + [GAUDI2_ETF_NIC6_DBG_1] = mmNIC6_DBG_ETF_1_BASE, + [GAUDI2_ETF_NIC7_DBG_0] = mmNIC7_DBG_ETF_0_BASE, + [GAUDI2_ETF_NIC7_DBG_1] = mmNIC7_DBG_ETF_1_BASE, + [GAUDI2_ETF_NIC8_DBG_0] = mmNIC8_DBG_ETF_0_BASE, + [GAUDI2_ETF_NIC8_DBG_1] = mmNIC8_DBG_ETF_1_BASE, + [GAUDI2_ETF_NIC9_DBG_0] = mmNIC9_DBG_ETF_0_BASE, + [GAUDI2_ETF_NIC9_DBG_1] = mmNIC9_DBG_ETF_1_BASE, + [GAUDI2_ETF_NIC10_DBG_0] = mmNIC10_DBG_ETF_0_BASE, + [GAUDI2_ETF_NIC10_DBG_1] = mmNIC10_DBG_ETF_1_BASE, + [GAUDI2_ETF_NIC11_DBG_0] = mmNIC11_DBG_ETF_0_BASE, + [GAUDI2_ETF_NIC11_DBG_1] = mmNIC11_DBG_ETF_1_BASE +}; + +static u64 debug_funnel_regs[GAUDI2_FUNNEL_LAST + 1] = { + [GAUDI2_FUNNEL_DCORE0_TPC0_EML] = mmDCORE0_TPC0_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE0_TPC1_EML] = mmDCORE0_TPC1_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE0_TPC2_EML] = mmDCORE0_TPC2_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE0_TPC3_EML] = mmDCORE0_TPC3_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE0_TPC4_EML] = mmDCORE0_TPC4_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE0_TPC5_EML] = mmDCORE0_TPC5_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE0_TPC6_EML] = mmDCORE0_TPC6_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE1_TPC0_EML] = mmDCORE1_TPC0_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE1_TPC1_EML] = mmDCORE1_TPC1_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE1_TPC2_EML] = mmDCORE1_TPC2_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE1_TPC3_EML] = mmDCORE1_TPC3_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE1_TPC4_EML] = mmDCORE1_TPC4_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE1_TPC5_EML] = mmDCORE1_TPC5_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE2_TPC0_EML] = mmDCORE2_TPC0_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE2_TPC1_EML] = mmDCORE2_TPC1_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE2_TPC2_EML] = mmDCORE2_TPC2_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE2_TPC3_EML] = mmDCORE2_TPC3_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE2_TPC4_EML] = mmDCORE2_TPC4_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE2_TPC5_EML] = mmDCORE2_TPC5_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE3_TPC0_EML] = mmDCORE3_TPC0_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE3_TPC1_EML] = mmDCORE3_TPC1_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE3_TPC2_EML] = mmDCORE3_TPC2_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE3_TPC3_EML] = mmDCORE3_TPC3_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE3_TPC4_EML] = mmDCORE3_TPC4_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE3_TPC5_EML] = mmDCORE3_TPC5_EML_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE0_XFT] = mmDCORE0_XFT_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE0_TFT0] = mmDCORE0_TFT0_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE0_TFT1] = mmDCORE0_TFT1_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE0_TFT2] = mmDCORE0_TFT2_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE0_RTR0] = mmDCORE0_RTR0_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE0_RTR1] = mmDCORE0_RTR1_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE0_RTR2] = mmDCORE0_RTR2_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE0_RTR3] = mmDCORE0_RTR3_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE0_RTR4] = mmDCORE0_RTR4_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE0_MIF0] = mmDCORE0_MIF0_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE0_RTR5] = mmDCORE0_RTR5_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE0_MIF1] = mmDCORE0_MIF1_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE0_RTR6] = mmDCORE0_RTR6_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE0_MIF2] = mmDCORE0_MIF2_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE0_RTR7] = mmDCORE0_RTR7_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE0_MIF3] = mmDCORE0_MIF3_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE1_XFT] = mmDCORE1_XFT_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE1_TFT0] = mmDCORE1_TFT0_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE1_TFT1] = mmDCORE1_TFT1_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE1_TFT2] = mmDCORE1_TFT2_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE1_RTR0] = mmDCORE1_RTR0_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE1_MIF0] = mmDCORE1_MIF0_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE1_RTR1] = mmDCORE1_RTR1_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE1_MIF1] = mmDCORE1_MIF1_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE1_RTR2] = mmDCORE1_RTR2_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE1_MIF2] = mmDCORE1_MIF2_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE1_RTR3] = mmDCORE1_RTR3_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE1_MIF3] = mmDCORE1_MIF3_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE1_RTR4] = mmDCORE1_RTR4_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE1_RTR5] = mmDCORE1_RTR5_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE1_RTR6] = mmDCORE1_RTR6_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE1_RTR7] = mmDCORE1_RTR7_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE2_XFT] = mmDCORE2_XFT_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE2_TFT0] = mmDCORE2_TFT0_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE2_TFT1] = mmDCORE2_TFT1_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE2_TFT2] = mmDCORE2_TFT2_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE2_RTR0] = mmDCORE2_RTR0_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE2_RTR1] = mmDCORE2_RTR1_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE2_RTR2] = mmDCORE2_RTR2_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE2_RTR3] = mmDCORE2_RTR3_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE2_RTR4] = mmDCORE2_RTR4_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE2_MIF0] = mmDCORE2_MIF0_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE2_RTR5] = mmDCORE2_RTR5_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE2_MIF1] = mmDCORE2_MIF1_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE2_RTR6] = mmDCORE2_RTR6_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE2_MIF2] = mmDCORE2_MIF2_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE2_RTR7] = mmDCORE2_RTR7_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE2_MIF3] = mmDCORE2_MIF3_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE3_XFT] = mmDCORE3_XFT_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE3_TFT0] = mmDCORE3_TFT0_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE3_TFT1] = mmDCORE3_TFT1_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE3_TFT2] = mmDCORE3_TFT2_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE3_RTR0] = mmDCORE3_RTR0_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE3_MIF0] = mmDCORE3_MIF0_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE3_RTR1] = mmDCORE3_RTR1_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE3_MIF1] = mmDCORE3_MIF1_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE3_RTR2] = mmDCORE3_RTR2_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE3_MIF2] = mmDCORE3_MIF2_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE3_RTR3] = mmDCORE3_RTR3_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE3_MIF3] = mmDCORE3_MIF3_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE3_RTR4] = mmDCORE3_RTR4_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE3_RTR5] = mmDCORE3_RTR5_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE3_RTR6] = mmDCORE3_RTR6_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE3_RTR7] = mmDCORE3_RTR7_FUNNEL_BASE, + [GAUDI2_FUNNEL_PSOC] = mmPSOC_FUNNEL_BASE, + [GAUDI2_FUNNEL_PSOC_ARC0] = mmPSOC_ARC0_FUNNEL_BASE, + [GAUDI2_FUNNEL_PSOC_ARC1] = mmPSOC_ARC1_FUNNEL_BASE, + [GAUDI2_FUNNEL_XDMA] = mmXDMA_FUNNEL_BASE, + [GAUDI2_FUNNEL_CPU] = mmCPU_FUNNEL_BASE, + [GAUDI2_FUNNEL_PMMU] = mmPMMU_FUNNEL_BASE, + [GAUDI2_FUNNEL_PMMU_DEC] = mmPMMU_FUNNEL_DEC_BASE, + [GAUDI2_FUNNEL_DCORE0_XBAR_MID] = mmDCORE0_XBAR_MID_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE0_XBAR_EDGE] = mmDCORE0_XBAR_EDGE_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE1_XBAR_MID] = mmDCORE1_XBAR_MID_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE1_XBAR_EDGE] = mmDCORE1_XBAR_EDGE_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE2_XBAR_MID] = mmDCORE2_XBAR_MID_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE2_XBAR_EDGE] = mmDCORE2_XBAR_EDGE_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE3_XBAR_MID] = mmDCORE3_XBAR_MID_FUNNEL_BASE, + [GAUDI2_FUNNEL_DCORE3_XBAR_EDGE] = mmDCORE3_XBAR_EDGE_FUNNEL_BASE, + [GAUDI2_FUNNEL_ARC_FARM] = mmARC_FARM_FUNNEL_BASE, + [GAUDI2_FUNNEL_HBM0_MC0] = mmHBM0_MC0_FUNNEL_BASE, + [GAUDI2_FUNNEL_HBM0_MC1] = mmHBM0_MC1_FUNNEL_BASE, + [GAUDI2_FUNNEL_HBM1_MC0] = mmHBM1_MC0_FUNNEL_BASE, + [GAUDI2_FUNNEL_HBM1_MC1] = mmHBM1_MC1_FUNNEL_BASE, + [GAUDI2_FUNNEL_HBM2_MC0] = mmHBM2_MC0_FUNNEL_BASE, + [GAUDI2_FUNNEL_HBM2_MC1] = mmHBM2_MC1_FUNNEL_BASE, + [GAUDI2_FUNNEL_HBM3_MC0] = mmHBM3_MC0_FUNNEL_BASE, + [GAUDI2_FUNNEL_HBM3_MC1] = mmHBM3_MC1_FUNNEL_BASE, + [GAUDI2_FUNNEL_HBM4_MC0] = mmHBM4_MC0_FUNNEL_BASE, + [GAUDI2_FUNNEL_HBM4_MC1] = mmHBM4_MC1_FUNNEL_BASE, + [GAUDI2_FUNNEL_HBM5_MC0] = mmHBM5_MC0_FUNNEL_BASE, + [GAUDI2_FUNNEL_HBM5_MC1] = mmHBM5_MC1_FUNNEL_BASE, + [GAUDI2_FUNNEL_NIC0_DBG_TX] = mmNIC0_DBG_FUNNEL_TX_BASE, + [GAUDI2_FUNNEL_NIC0_DBG_NCH] = mmNIC0_DBG_FUNNEL_NCH_BASE, + [GAUDI2_FUNNEL_NIC1_DBG_TX] = mmNIC1_DBG_FUNNEL_TX_BASE, + [GAUDI2_FUNNEL_NIC1_DBG_NCH] = mmNIC1_DBG_FUNNEL_NCH_BASE, + [GAUDI2_FUNNEL_NIC2_DBG_TX] = mmNIC2_DBG_FUNNEL_TX_BASE, + [GAUDI2_FUNNEL_NIC2_DBG_NCH] = mmNIC2_DBG_FUNNEL_NCH_BASE, + [GAUDI2_FUNNEL_NIC3_DBG_TX] = mmNIC3_DBG_FUNNEL_TX_BASE, + [GAUDI2_FUNNEL_NIC3_DBG_NCH] = mmNIC3_DBG_FUNNEL_NCH_BASE, + [GAUDI2_FUNNEL_NIC4_DBG_TX] = mmNIC4_DBG_FUNNEL_TX_BASE, + [GAUDI2_FUNNEL_NIC4_DBG_NCH] = mmNIC4_DBG_FUNNEL_NCH_BASE, + [GAUDI2_FUNNEL_NIC5_DBG_TX] = mmNIC5_DBG_FUNNEL_TX_BASE, + [GAUDI2_FUNNEL_NIC5_DBG_NCH] = mmNIC5_DBG_FUNNEL_NCH_BASE, + [GAUDI2_FUNNEL_NIC6_DBG_TX] = mmNIC6_DBG_FUNNEL_TX_BASE, + [GAUDI2_FUNNEL_NIC6_DBG_NCH] = mmNIC6_DBG_FUNNEL_NCH_BASE, + [GAUDI2_FUNNEL_NIC7_DBG_TX] = mmNIC7_DBG_FUNNEL_TX_BASE, + [GAUDI2_FUNNEL_NIC7_DBG_NCH] = mmNIC7_DBG_FUNNEL_NCH_BASE, + [GAUDI2_FUNNEL_NIC8_DBG_TX] = mmNIC8_DBG_FUNNEL_TX_BASE, + [GAUDI2_FUNNEL_NIC8_DBG_NCH] = mmNIC8_DBG_FUNNEL_NCH_BASE, + [GAUDI2_FUNNEL_NIC9_DBG_TX] = mmNIC9_DBG_FUNNEL_TX_BASE, + [GAUDI2_FUNNEL_NIC9_DBG_NCH] = mmNIC9_DBG_FUNNEL_NCH_BASE, + [GAUDI2_FUNNEL_NIC10_DBG_TX] = mmNIC10_DBG_FUNNEL_TX_BASE, + [GAUDI2_FUNNEL_NIC10_DBG_NCH] = mmNIC10_DBG_FUNNEL_NCH_BASE, + [GAUDI2_FUNNEL_NIC11_DBG_TX] = mmNIC11_DBG_FUNNEL_TX_BASE, + [GAUDI2_FUNNEL_NIC11_DBG_NCH] = mmNIC11_DBG_FUNNEL_NCH_BASE +}; + +static u64 debug_bmon_regs[GAUDI2_BMON_LAST + 1] = { + [GAUDI2_BMON_DCORE0_TPC0_EML_0] = mmDCORE0_TPC0_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE0_TPC0_EML_1] = mmDCORE0_TPC0_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE0_TPC0_EML_2] = mmDCORE0_TPC0_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE0_TPC0_EML_3] = mmDCORE0_TPC0_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE0_TPC1_EML_0] = mmDCORE0_TPC1_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE0_TPC1_EML_1] = mmDCORE0_TPC1_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE0_TPC1_EML_2] = mmDCORE0_TPC1_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE0_TPC1_EML_3] = mmDCORE0_TPC1_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE0_TPC2_EML_0] = mmDCORE0_TPC2_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE0_TPC2_EML_1] = mmDCORE0_TPC2_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE0_TPC2_EML_2] = mmDCORE0_TPC2_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE0_TPC2_EML_3] = mmDCORE0_TPC2_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE0_TPC3_EML_0] = mmDCORE0_TPC3_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE0_TPC3_EML_1] = mmDCORE0_TPC3_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE0_TPC3_EML_2] = mmDCORE0_TPC3_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE0_TPC3_EML_3] = mmDCORE0_TPC3_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE0_TPC4_EML_0] = mmDCORE0_TPC4_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE0_TPC4_EML_1] = mmDCORE0_TPC4_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE0_TPC4_EML_2] = mmDCORE0_TPC4_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE0_TPC4_EML_3] = mmDCORE0_TPC4_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE0_TPC5_EML_0] = mmDCORE0_TPC5_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE0_TPC5_EML_1] = mmDCORE0_TPC5_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE0_TPC5_EML_2] = mmDCORE0_TPC5_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE0_TPC5_EML_3] = mmDCORE0_TPC5_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE0_TPC6_EML_0] = mmDCORE0_TPC6_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE0_TPC6_EML_1] = mmDCORE0_TPC6_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE0_TPC6_EML_2] = mmDCORE0_TPC6_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE0_TPC6_EML_3] = mmDCORE0_TPC6_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE1_TPC0_EML_0] = mmDCORE1_TPC0_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE1_TPC0_EML_1] = mmDCORE1_TPC0_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE1_TPC0_EML_2] = mmDCORE1_TPC0_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE1_TPC0_EML_3] = mmDCORE1_TPC0_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE1_TPC1_EML_0] = mmDCORE1_TPC1_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE1_TPC1_EML_1] = mmDCORE1_TPC1_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE1_TPC1_EML_2] = mmDCORE1_TPC1_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE1_TPC1_EML_3] = mmDCORE1_TPC1_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE1_TPC2_EML_0] = mmDCORE1_TPC2_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE1_TPC2_EML_1] = mmDCORE1_TPC2_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE1_TPC2_EML_2] = mmDCORE1_TPC2_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE1_TPC2_EML_3] = mmDCORE1_TPC2_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE1_TPC3_EML_0] = mmDCORE1_TPC3_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE1_TPC3_EML_1] = mmDCORE1_TPC3_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE1_TPC3_EML_2] = mmDCORE1_TPC3_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE1_TPC3_EML_3] = mmDCORE1_TPC3_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE1_TPC4_EML_0] = mmDCORE1_TPC4_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE1_TPC4_EML_1] = mmDCORE1_TPC4_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE1_TPC4_EML_2] = mmDCORE1_TPC4_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE1_TPC4_EML_3] = mmDCORE1_TPC4_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE1_TPC5_EML_0] = mmDCORE1_TPC5_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE1_TPC5_EML_1] = mmDCORE1_TPC5_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE1_TPC5_EML_2] = mmDCORE1_TPC5_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE1_TPC5_EML_3] = mmDCORE1_TPC5_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE2_TPC0_EML_0] = mmDCORE2_TPC0_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE2_TPC0_EML_1] = mmDCORE2_TPC0_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE2_TPC0_EML_2] = mmDCORE2_TPC0_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE2_TPC0_EML_3] = mmDCORE2_TPC0_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE2_TPC1_EML_0] = mmDCORE2_TPC1_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE2_TPC1_EML_1] = mmDCORE2_TPC1_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE2_TPC1_EML_2] = mmDCORE2_TPC1_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE2_TPC1_EML_3] = mmDCORE2_TPC1_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE2_TPC2_EML_0] = mmDCORE2_TPC2_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE2_TPC2_EML_1] = mmDCORE2_TPC2_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE2_TPC2_EML_2] = mmDCORE2_TPC2_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE2_TPC2_EML_3] = mmDCORE2_TPC2_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE2_TPC3_EML_0] = mmDCORE2_TPC3_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE2_TPC3_EML_1] = mmDCORE2_TPC3_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE2_TPC3_EML_2] = mmDCORE2_TPC3_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE2_TPC3_EML_3] = mmDCORE2_TPC3_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE2_TPC4_EML_0] = mmDCORE2_TPC4_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE2_TPC4_EML_1] = mmDCORE2_TPC4_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE2_TPC4_EML_2] = mmDCORE2_TPC4_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE2_TPC4_EML_3] = mmDCORE2_TPC4_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE2_TPC5_EML_0] = mmDCORE2_TPC5_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE2_TPC5_EML_1] = mmDCORE2_TPC5_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE2_TPC5_EML_2] = mmDCORE2_TPC5_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE2_TPC5_EML_3] = mmDCORE2_TPC5_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE3_TPC0_EML_0] = mmDCORE3_TPC0_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE3_TPC0_EML_1] = mmDCORE3_TPC0_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE3_TPC0_EML_2] = mmDCORE3_TPC0_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE3_TPC0_EML_3] = mmDCORE3_TPC0_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE3_TPC1_EML_0] = mmDCORE3_TPC1_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE3_TPC1_EML_1] = mmDCORE3_TPC1_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE3_TPC1_EML_2] = mmDCORE3_TPC1_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE3_TPC1_EML_3] = mmDCORE3_TPC1_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE3_TPC2_EML_0] = mmDCORE3_TPC2_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE3_TPC2_EML_1] = mmDCORE3_TPC2_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE3_TPC2_EML_2] = mmDCORE3_TPC2_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE3_TPC2_EML_3] = mmDCORE3_TPC2_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE3_TPC3_EML_0] = mmDCORE3_TPC3_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE3_TPC3_EML_1] = mmDCORE3_TPC3_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE3_TPC3_EML_2] = mmDCORE3_TPC3_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE3_TPC3_EML_3] = mmDCORE3_TPC3_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE3_TPC4_EML_0] = mmDCORE3_TPC4_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE3_TPC4_EML_1] = mmDCORE3_TPC4_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE3_TPC4_EML_2] = mmDCORE3_TPC4_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE3_TPC4_EML_3] = mmDCORE3_TPC4_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE3_TPC5_EML_0] = mmDCORE3_TPC5_EML_BUSMON_0_BASE, + [GAUDI2_BMON_DCORE3_TPC5_EML_1] = mmDCORE3_TPC5_EML_BUSMON_1_BASE, + [GAUDI2_BMON_DCORE3_TPC5_EML_2] = mmDCORE3_TPC5_EML_BUSMON_2_BASE, + [GAUDI2_BMON_DCORE3_TPC5_EML_3] = mmDCORE3_TPC5_EML_BUSMON_3_BASE, + [GAUDI2_BMON_DCORE0_HMMU0_0] = mmDCORE0_HMMU0_BMON_0_BASE, + [GAUDI2_BMON_DCORE0_HMMU0_1] = mmDCORE0_HMMU0_BMON_1_BASE, + [GAUDI2_BMON_DCORE0_HMMU0_3] = mmDCORE0_HMMU0_BMON_3_BASE, + [GAUDI2_BMON_DCORE0_HMMU0_2] = mmDCORE0_HMMU0_BMON_2_BASE, + [GAUDI2_BMON_DCORE0_HMMU0_4] = mmDCORE0_HMMU0_BMON_4_BASE, + [GAUDI2_BMON_DCORE0_HMMU1_0] = mmDCORE0_HMMU1_BMON_0_BASE, + [GAUDI2_BMON_DCORE0_HMMU1_1] = mmDCORE0_HMMU1_BMON_1_BASE, + [GAUDI2_BMON_DCORE0_HMMU1_3] = mmDCORE0_HMMU1_BMON_3_BASE, + [GAUDI2_BMON_DCORE0_HMMU1_2] = mmDCORE0_HMMU1_BMON_2_BASE, + [GAUDI2_BMON_DCORE0_HMMU1_4] = mmDCORE0_HMMU1_BMON_4_BASE, + [GAUDI2_BMON_DCORE0_HMMU2_0] = mmDCORE0_HMMU2_BMON_0_BASE, + [GAUDI2_BMON_DCORE0_HMMU2_1] = mmDCORE0_HMMU2_BMON_1_BASE, + [GAUDI2_BMON_DCORE0_HMMU2_3] = mmDCORE0_HMMU2_BMON_3_BASE, + [GAUDI2_BMON_DCORE0_HMMU2_2] = mmDCORE0_HMMU2_BMON_2_BASE, + [GAUDI2_BMON_DCORE0_HMMU2_4] = mmDCORE0_HMMU2_BMON_4_BASE, + [GAUDI2_BMON_DCORE0_HMMU3_0] = mmDCORE0_HMMU3_BMON_0_BASE, + [GAUDI2_BMON_DCORE0_HMMU3_1] = mmDCORE0_HMMU3_BMON_1_BASE, + [GAUDI2_BMON_DCORE0_HMMU3_3] = mmDCORE0_HMMU3_BMON_3_BASE, + [GAUDI2_BMON_DCORE0_HMMU3_2] = mmDCORE0_HMMU3_BMON_2_BASE, + [GAUDI2_BMON_DCORE0_HMMU3_4] = mmDCORE0_HMMU3_BMON_4_BASE, + [GAUDI2_BMON_DCORE0_MME_CTRL_0] = mmDCORE0_MME_CTRL_BMON0_BASE, + [GAUDI2_BMON_DCORE0_MME_CTRL_1] = mmDCORE0_MME_CTRL_BMON1_BASE, + [GAUDI2_BMON_DCORE0_MME_CTRL_2] = mmDCORE0_MME_CTRL_BMON2_BASE, + [GAUDI2_BMON_DCORE0_MME_CTRL_3] = mmDCORE0_MME_CTRL_BMON3_BASE, + [GAUDI2_BMON_DCORE0_MME_SBTE0_0] = mmDCORE0_MME_SBTE0_BMON0_BASE, + [GAUDI2_BMON_DCORE0_MME_SBTE1_0] = mmDCORE0_MME_SBTE1_BMON0_BASE, + [GAUDI2_BMON_DCORE0_MME_SBTE2_0] = mmDCORE0_MME_SBTE2_BMON0_BASE, + [GAUDI2_BMON_DCORE0_MME_SBTE3_0] = mmDCORE0_MME_SBTE3_BMON0_BASE, + [GAUDI2_BMON_DCORE0_MME_SBTE4_0] = mmDCORE0_MME_SBTE4_BMON0_BASE, + [GAUDI2_BMON_DCORE0_MME_ACC_0] = mmDCORE0_MME_ACC_BMON0_BASE, + [GAUDI2_BMON_DCORE0_MME_ACC_1] = mmDCORE0_MME_ACC_BMON1_BASE, + [GAUDI2_BMON_DCORE0_SM] = mmDCORE0_SM_BMON_BASE, + [GAUDI2_BMON_DCORE0_SM_1] = mmDCORE0_SM_BMON1_BASE, + [GAUDI2_BMON_DCORE0_EDMA0_0] = mmDCORE0_EDMA0_BMON_0_BASE, + [GAUDI2_BMON_DCORE0_EDMA0_1] = mmDCORE0_EDMA0_BMON_1_BASE, + [GAUDI2_BMON_DCORE0_EDMA1_0] = mmDCORE0_EDMA1_BMON_0_BASE, + [GAUDI2_BMON_DCORE0_EDMA1_1] = mmDCORE0_EDMA1_BMON_1_BASE, + [GAUDI2_BMON_DCORE0_VDEC0_0] = mmDCORE0_VDEC0_BMON_0_BASE, + [GAUDI2_BMON_DCORE0_VDEC0_1] = mmDCORE0_VDEC0_BMON_1_BASE, + [GAUDI2_BMON_DCORE0_VDEC0_2] = mmDCORE0_VDEC0_BMON_2_BASE, + [GAUDI2_BMON_DCORE0_VDEC1_0] = mmDCORE0_VDEC1_BMON_0_BASE, + [GAUDI2_BMON_DCORE0_VDEC1_1] = mmDCORE0_VDEC1_BMON_1_BASE, + [GAUDI2_BMON_DCORE0_VDEC1_2] = mmDCORE0_VDEC1_BMON_2_BASE, + [GAUDI2_BMON_DCORE1_HMMU0_0] = mmDCORE1_HMMU0_BMON_0_BASE, + [GAUDI2_BMON_DCORE1_HMMU0_1] = mmDCORE1_HMMU0_BMON_1_BASE, + [GAUDI2_BMON_DCORE1_HMMU0_3] = mmDCORE1_HMMU0_BMON_3_BASE, + [GAUDI2_BMON_DCORE1_HMMU0_2] = mmDCORE1_HMMU0_BMON_2_BASE, + [GAUDI2_BMON_DCORE1_HMMU0_4] = mmDCORE1_HMMU0_BMON_4_BASE, + [GAUDI2_BMON_DCORE1_HMMU1_0] = mmDCORE1_HMMU1_BMON_0_BASE, + [GAUDI2_BMON_DCORE1_HMMU1_1] = mmDCORE1_HMMU1_BMON_1_BASE, + [GAUDI2_BMON_DCORE1_HMMU1_3] = mmDCORE1_HMMU1_BMON_3_BASE, + [GAUDI2_BMON_DCORE1_HMMU1_2] = mmDCORE1_HMMU1_BMON_2_BASE, + [GAUDI2_BMON_DCORE1_HMMU1_4] = mmDCORE1_HMMU1_BMON_4_BASE, + [GAUDI2_BMON_DCORE1_HMMU2_0] = mmDCORE1_HMMU2_BMON_0_BASE, + [GAUDI2_BMON_DCORE1_HMMU2_1] = mmDCORE1_HMMU2_BMON_1_BASE, + [GAUDI2_BMON_DCORE1_HMMU2_3] = mmDCORE1_HMMU2_BMON_3_BASE, + [GAUDI2_BMON_DCORE1_HMMU2_2] = mmDCORE1_HMMU2_BMON_2_BASE, + [GAUDI2_BMON_DCORE1_HMMU2_4] = mmDCORE1_HMMU2_BMON_4_BASE, + [GAUDI2_BMON_DCORE1_HMMU3_0] = mmDCORE1_HMMU3_BMON_0_BASE, + [GAUDI2_BMON_DCORE1_HMMU3_1] = mmDCORE1_HMMU3_BMON_1_BASE, + [GAUDI2_BMON_DCORE1_HMMU3_3] = mmDCORE1_HMMU3_BMON_3_BASE, + [GAUDI2_BMON_DCORE1_HMMU3_2] = mmDCORE1_HMMU3_BMON_2_BASE, + [GAUDI2_BMON_DCORE1_HMMU3_4] = mmDCORE1_HMMU3_BMON_4_BASE, + [GAUDI2_BMON_DCORE1_MME_CTRL_0] = mmDCORE1_MME_CTRL_BMON0_BASE, + [GAUDI2_BMON_DCORE1_MME_CTRL_1] = mmDCORE1_MME_CTRL_BMON1_BASE, + [GAUDI2_BMON_DCORE1_MME_CTRL_2] = mmDCORE1_MME_CTRL_BMON2_BASE, + [GAUDI2_BMON_DCORE1_MME_CTRL_3] = mmDCORE1_MME_CTRL_BMON3_BASE, + [GAUDI2_BMON_DCORE1_MME_SBTE0_0] = mmDCORE1_MME_SBTE0_BMON0_BASE, + [GAUDI2_BMON_DCORE1_MME_SBTE1_0] = mmDCORE1_MME_SBTE1_BMON0_BASE, + [GAUDI2_BMON_DCORE1_MME_SBTE2_0] = mmDCORE1_MME_SBTE2_BMON0_BASE, + [GAUDI2_BMON_DCORE1_MME_SBTE3_0] = mmDCORE1_MME_SBTE3_BMON0_BASE, + [GAUDI2_BMON_DCORE1_MME_SBTE4_0] = mmDCORE1_MME_SBTE4_BMON0_BASE, + [GAUDI2_BMON_DCORE1_MME_ACC_0] = mmDCORE1_MME_ACC_BMON0_BASE, + [GAUDI2_BMON_DCORE1_MME_ACC_1] = mmDCORE1_MME_ACC_BMON1_BASE, + [GAUDI2_BMON_DCORE1_SM] = mmDCORE1_SM_BMON_BASE, + [GAUDI2_BMON_DCORE1_SM_1] = mmDCORE1_SM_BMON1_BASE, + [GAUDI2_BMON_DCORE1_EDMA0_0] = mmDCORE1_EDMA0_BMON_0_BASE, + [GAUDI2_BMON_DCORE1_EDMA0_1] = mmDCORE1_EDMA0_BMON_1_BASE, + [GAUDI2_BMON_DCORE1_EDMA1_0] = mmDCORE1_EDMA1_BMON_0_BASE, + [GAUDI2_BMON_DCORE1_EDMA1_1] = mmDCORE1_EDMA1_BMON_1_BASE, + [GAUDI2_BMON_DCORE1_VDEC0_0] = mmDCORE1_VDEC0_BMON_0_BASE, + [GAUDI2_BMON_DCORE1_VDEC0_1] = mmDCORE1_VDEC0_BMON_1_BASE, + [GAUDI2_BMON_DCORE1_VDEC0_2] = mmDCORE1_VDEC0_BMON_2_BASE, + [GAUDI2_BMON_DCORE1_VDEC1_0] = mmDCORE1_VDEC1_BMON_0_BASE, + [GAUDI2_BMON_DCORE1_VDEC1_1] = mmDCORE1_VDEC1_BMON_1_BASE, + [GAUDI2_BMON_DCORE1_VDEC1_2] = mmDCORE1_VDEC1_BMON_2_BASE, + [GAUDI2_BMON_DCORE2_HMMU0_0] = mmDCORE2_HMMU0_BMON_0_BASE, + [GAUDI2_BMON_DCORE2_HMMU0_1] = mmDCORE2_HMMU0_BMON_1_BASE, + [GAUDI2_BMON_DCORE2_HMMU0_3] = mmDCORE2_HMMU0_BMON_3_BASE, + [GAUDI2_BMON_DCORE2_HMMU0_2] = mmDCORE2_HMMU0_BMON_2_BASE, + [GAUDI2_BMON_DCORE2_HMMU0_4] = mmDCORE2_HMMU0_BMON_4_BASE, + [GAUDI2_BMON_DCORE2_HMMU1_0] = mmDCORE2_HMMU1_BMON_0_BASE, + [GAUDI2_BMON_DCORE2_HMMU1_1] = mmDCORE2_HMMU1_BMON_1_BASE, + [GAUDI2_BMON_DCORE2_HMMU1_3] = mmDCORE2_HMMU1_BMON_3_BASE, + [GAUDI2_BMON_DCORE2_HMMU1_2] = mmDCORE2_HMMU1_BMON_2_BASE, + [GAUDI2_BMON_DCORE2_HMMU1_4] = mmDCORE2_HMMU1_BMON_4_BASE, + [GAUDI2_BMON_DCORE2_HMMU2_0] = mmDCORE2_HMMU2_BMON_0_BASE, + [GAUDI2_BMON_DCORE2_HMMU2_1] = mmDCORE2_HMMU2_BMON_1_BASE, + [GAUDI2_BMON_DCORE2_HMMU2_3] = mmDCORE2_HMMU2_BMON_3_BASE, + [GAUDI2_BMON_DCORE2_HMMU2_2] = mmDCORE2_HMMU2_BMON_2_BASE, + [GAUDI2_BMON_DCORE2_HMMU2_4] = mmDCORE2_HMMU2_BMON_4_BASE, + [GAUDI2_BMON_DCORE2_HMMU3_0] = mmDCORE2_HMMU3_BMON_0_BASE, + [GAUDI2_BMON_DCORE2_HMMU3_1] = mmDCORE2_HMMU3_BMON_1_BASE, + [GAUDI2_BMON_DCORE2_HMMU3_3] = mmDCORE2_HMMU3_BMON_3_BASE, + [GAUDI2_BMON_DCORE2_HMMU3_2] = mmDCORE2_HMMU3_BMON_2_BASE, + [GAUDI2_BMON_DCORE2_HMMU3_4] = mmDCORE2_HMMU3_BMON_4_BASE, + [GAUDI2_BMON_DCORE2_MME_CTRL_0] = mmDCORE2_MME_CTRL_BMON0_BASE, + [GAUDI2_BMON_DCORE2_MME_CTRL_1] = mmDCORE2_MME_CTRL_BMON1_BASE, + [GAUDI2_BMON_DCORE2_MME_CTRL_2] = mmDCORE2_MME_CTRL_BMON2_BASE, + [GAUDI2_BMON_DCORE2_MME_CTRL_3] = mmDCORE2_MME_CTRL_BMON3_BASE, + [GAUDI2_BMON_DCORE2_MME_SBTE0_0] = mmDCORE2_MME_SBTE0_BMON0_BASE, + [GAUDI2_BMON_DCORE2_MME_SBTE1_0] = mmDCORE2_MME_SBTE1_BMON0_BASE, + [GAUDI2_BMON_DCORE2_MME_SBTE2_0] = mmDCORE2_MME_SBTE2_BMON0_BASE, + [GAUDI2_BMON_DCORE2_MME_SBTE3_0] = mmDCORE2_MME_SBTE3_BMON0_BASE, + [GAUDI2_BMON_DCORE2_MME_SBTE4_0] = mmDCORE2_MME_SBTE4_BMON0_BASE, + [GAUDI2_BMON_DCORE2_MME_ACC_0] = mmDCORE2_MME_ACC_BMON0_BASE, + [GAUDI2_BMON_DCORE2_MME_ACC_1] = mmDCORE2_MME_ACC_BMON1_BASE, + [GAUDI2_BMON_DCORE2_SM] = mmDCORE2_SM_BMON_BASE, + [GAUDI2_BMON_DCORE2_SM_1] = mmDCORE2_SM_BMON1_BASE, + [GAUDI2_BMON_DCORE2_EDMA0_0] = mmDCORE2_EDMA0_BMON_0_BASE, + [GAUDI2_BMON_DCORE2_EDMA0_1] = mmDCORE2_EDMA0_BMON_1_BASE, + [GAUDI2_BMON_DCORE2_EDMA1_0] = mmDCORE2_EDMA1_BMON_0_BASE, + [GAUDI2_BMON_DCORE2_EDMA1_1] = mmDCORE2_EDMA1_BMON_1_BASE, + [GAUDI2_BMON_DCORE2_VDEC0_0] = mmDCORE2_VDEC0_BMON_0_BASE, + [GAUDI2_BMON_DCORE2_VDEC0_1] = mmDCORE2_VDEC0_BMON_1_BASE, + [GAUDI2_BMON_DCORE2_VDEC0_2] = mmDCORE2_VDEC0_BMON_2_BASE, + [GAUDI2_BMON_DCORE2_VDEC1_0] = mmDCORE2_VDEC1_BMON_0_BASE, + [GAUDI2_BMON_DCORE2_VDEC1_1] = mmDCORE2_VDEC1_BMON_1_BASE, + [GAUDI2_BMON_DCORE2_VDEC1_2] = mmDCORE2_VDEC1_BMON_2_BASE, + [GAUDI2_BMON_DCORE3_HMMU0_0] = mmDCORE3_HMMU0_BMON_0_BASE, + [GAUDI2_BMON_DCORE3_HMMU0_1] = mmDCORE3_HMMU0_BMON_1_BASE, + [GAUDI2_BMON_DCORE3_HMMU0_3] = mmDCORE3_HMMU0_BMON_3_BASE, + [GAUDI2_BMON_DCORE3_HMMU0_2] = mmDCORE3_HMMU0_BMON_2_BASE, + [GAUDI2_BMON_DCORE3_HMMU0_4] = mmDCORE3_HMMU0_BMON_4_BASE, + [GAUDI2_BMON_DCORE3_HMMU1_0] = mmDCORE3_HMMU1_BMON_0_BASE, + [GAUDI2_BMON_DCORE3_HMMU1_1] = mmDCORE3_HMMU1_BMON_1_BASE, + [GAUDI2_BMON_DCORE3_HMMU1_3] = mmDCORE3_HMMU1_BMON_3_BASE, + [GAUDI2_BMON_DCORE3_HMMU1_2] = mmDCORE3_HMMU1_BMON_2_BASE, + [GAUDI2_BMON_DCORE3_HMMU1_4] = mmDCORE3_HMMU1_BMON_4_BASE, + [GAUDI2_BMON_DCORE3_HMMU2_0] = mmDCORE3_HMMU2_BMON_0_BASE, + [GAUDI2_BMON_DCORE3_HMMU2_1] = mmDCORE3_HMMU2_BMON_1_BASE, + [GAUDI2_BMON_DCORE3_HMMU2_3] = mmDCORE3_HMMU2_BMON_3_BASE, + [GAUDI2_BMON_DCORE3_HMMU2_2] = mmDCORE3_HMMU2_BMON_2_BASE, + [GAUDI2_BMON_DCORE3_HMMU2_4] = mmDCORE3_HMMU2_BMON_4_BASE, + [GAUDI2_BMON_DCORE3_HMMU3_0] = mmDCORE3_HMMU3_BMON_0_BASE, + [GAUDI2_BMON_DCORE3_HMMU3_1] = mmDCORE3_HMMU3_BMON_1_BASE, + [GAUDI2_BMON_DCORE3_HMMU3_3] = mmDCORE3_HMMU3_BMON_3_BASE, + [GAUDI2_BMON_DCORE3_HMMU3_2] = mmDCORE3_HMMU3_BMON_2_BASE, + [GAUDI2_BMON_DCORE3_HMMU3_4] = mmDCORE3_HMMU3_BMON_4_BASE, + [GAUDI2_BMON_DCORE3_MME_CTRL_0] = mmDCORE3_MME_CTRL_BMON0_BASE, + [GAUDI2_BMON_DCORE3_MME_CTRL_1] = mmDCORE3_MME_CTRL_BMON1_BASE, + [GAUDI2_BMON_DCORE3_MME_CTRL_2] = mmDCORE3_MME_CTRL_BMON2_BASE, + [GAUDI2_BMON_DCORE3_MME_CTRL_3] = mmDCORE3_MME_CTRL_BMON3_BASE, + [GAUDI2_BMON_DCORE3_MME_SBTE0_0] = mmDCORE3_MME_SBTE0_BMON0_BASE, + [GAUDI2_BMON_DCORE3_MME_SBTE1_0] = mmDCORE3_MME_SBTE1_BMON0_BASE, + [GAUDI2_BMON_DCORE3_MME_SBTE2_0] = mmDCORE3_MME_SBTE2_BMON0_BASE, + [GAUDI2_BMON_DCORE3_MME_SBTE3_0] = mmDCORE3_MME_SBTE3_BMON0_BASE, + [GAUDI2_BMON_DCORE3_MME_SBTE4_0] = mmDCORE3_MME_SBTE4_BMON0_BASE, + [GAUDI2_BMON_DCORE3_MME_ACC_0] = mmDCORE3_MME_ACC_BMON0_BASE, + [GAUDI2_BMON_DCORE3_MME_ACC_1] = mmDCORE3_MME_ACC_BMON1_BASE, + [GAUDI2_BMON_DCORE3_SM] = mmDCORE3_SM_BMON_BASE, + [GAUDI2_BMON_DCORE3_SM_1] = mmDCORE3_SM_BMON1_BASE, + [GAUDI2_BMON_DCORE3_EDMA0_0] = mmDCORE3_EDMA0_BMON_0_BASE, + [GAUDI2_BMON_DCORE3_EDMA0_1] = mmDCORE3_EDMA0_BMON_1_BASE, + [GAUDI2_BMON_DCORE3_EDMA1_0] = mmDCORE3_EDMA1_BMON_0_BASE, + [GAUDI2_BMON_DCORE3_EDMA1_1] = mmDCORE3_EDMA1_BMON_1_BASE, + [GAUDI2_BMON_DCORE3_VDEC0_0] = mmDCORE3_VDEC0_BMON_0_BASE, + [GAUDI2_BMON_DCORE3_VDEC0_1] = mmDCORE3_VDEC0_BMON_1_BASE, + [GAUDI2_BMON_DCORE3_VDEC0_2] = mmDCORE3_VDEC0_BMON_2_BASE, + [GAUDI2_BMON_DCORE3_VDEC1_0] = mmDCORE3_VDEC1_BMON_0_BASE, + [GAUDI2_BMON_DCORE3_VDEC1_1] = mmDCORE3_VDEC1_BMON_1_BASE, + [GAUDI2_BMON_DCORE3_VDEC1_2] = mmDCORE3_VDEC1_BMON_2_BASE, + [GAUDI2_BMON_PCIE_MSTR_WR] = mmPCIE_BMON_MSTR_WR_BASE, + [GAUDI2_BMON_PCIE_MSTR_RD] = mmPCIE_BMON_MSTR_RD_BASE, + [GAUDI2_BMON_PCIE_SLV_WR] = mmPCIE_BMON_SLV_WR_BASE, + [GAUDI2_BMON_PCIE_SLV_RD] = mmPCIE_BMON_SLV_RD_BASE, + [GAUDI2_BMON_PSOC_ARC0_0] = mmPSOC_ARC0_BMON_0_BASE, + [GAUDI2_BMON_PSOC_ARC0_1] = mmPSOC_ARC0_BMON_1_BASE, + [GAUDI2_BMON_PSOC_ARC1_0] = mmPSOC_ARC1_BMON_0_BASE, + [GAUDI2_BMON_PSOC_ARC1_1] = mmPSOC_ARC1_BMON_1_BASE, + [GAUDI2_BMON_PDMA0_0] = mmPDMA0_BMON_0_BASE, + [GAUDI2_BMON_PDMA0_1] = mmPDMA0_BMON_1_BASE, + [GAUDI2_BMON_PDMA1_0] = mmPDMA1_BMON_0_BASE, + [GAUDI2_BMON_PDMA1_1] = mmPDMA1_BMON_1_BASE, + [GAUDI2_BMON_CPU_WR] = mmCPU_WR_BMON_BASE, + [GAUDI2_BMON_CPU_RD] = mmCPU_RD_BMON_BASE, + [GAUDI2_BMON_PMMU_0] = mmPMMU_BMON_0_BASE, + [GAUDI2_BMON_PMMU_1] = mmPMMU_BMON_1_BASE, + [GAUDI2_BMON_PMMU_2] = mmPMMU_BMON_2_BASE, + [GAUDI2_BMON_PMMU_3] = mmPMMU_BMON_3_BASE, + [GAUDI2_BMON_PMMU_4] = mmPMMU_BMON_4_BASE, + [GAUDI2_BMON_ROT0_0] = mmROT0_BMON_0_BASE, + [GAUDI2_BMON_ROT0_1] = mmROT0_BMON_1_BASE, + [GAUDI2_BMON_ROT0_2] = mmROT0_BMON_2_BASE, + [GAUDI2_BMON_ROT0_3] = mmROT0_BMON_3_BASE, + [GAUDI2_BMON_ROT1_0] = mmROT1_BMON_0_BASE, + [GAUDI2_BMON_ROT1_1] = mmROT1_BMON_1_BASE, + [GAUDI2_BMON_ROT1_2] = mmROT1_BMON_2_BASE, + [GAUDI2_BMON_ROT1_3] = mmROT1_BMON_3_BASE, + [GAUDI2_BMON_ARC_FARM_0] = mmARC_FARM_BMON_0_BASE, + [GAUDI2_BMON_ARC_FARM_1] = mmARC_FARM_BMON_1_BASE, + [GAUDI2_BMON_ARC_FARM_2] = mmARC_FARM_BMON_2_BASE, + [GAUDI2_BMON_ARC_FARM_3] = mmARC_FARM_BMON_3_BASE, + [GAUDI2_BMON_KDMA_0] = mmKDMA_BMON_0_BASE, + [GAUDI2_BMON_KDMA_1] = mmKDMA_BMON_1_BASE, + [GAUDI2_BMON_KDMA_2] = mmKDMA_BMON_2_BASE, + [GAUDI2_BMON_KDMA_3] = mmKDMA_BMON_3_BASE, + [GAUDI2_BMON_PCIE_VDEC0_0] = mmPCIE_VDEC0_BMON_0_BASE, + [GAUDI2_BMON_PCIE_VDEC0_1] = mmPCIE_VDEC0_BMON_1_BASE, + [GAUDI2_BMON_PCIE_VDEC0_2] = mmPCIE_VDEC0_BMON_2_BASE, + [GAUDI2_BMON_PCIE_VDEC1_0] = mmPCIE_VDEC1_BMON_0_BASE, + [GAUDI2_BMON_PCIE_VDEC1_1] = mmPCIE_VDEC1_BMON_1_BASE, + [GAUDI2_BMON_PCIE_VDEC1_2] = mmPCIE_VDEC1_BMON_2_BASE, + [GAUDI2_BMON_NIC0_DBG_0_0] = mmNIC0_DBG_BMON0_0_BASE, + [GAUDI2_BMON_NIC0_DBG_1_0] = mmNIC0_DBG_BMON1_0_BASE, + [GAUDI2_BMON_NIC0_DBG_2_0] = mmNIC0_DBG_BMON2_0_BASE, + [GAUDI2_BMON_NIC0_DBG_0_1] = mmNIC0_DBG_BMON0_1_BASE, + [GAUDI2_BMON_NIC0_DBG_1_1] = mmNIC0_DBG_BMON1_1_BASE, + [GAUDI2_BMON_NIC0_DBG_2_1] = mmNIC0_DBG_BMON2_1_BASE, + [GAUDI2_BMON_NIC1_DBG_0_0] = mmNIC1_DBG_BMON0_0_BASE, + [GAUDI2_BMON_NIC1_DBG_1_0] = mmNIC1_DBG_BMON1_0_BASE, + [GAUDI2_BMON_NIC1_DBG_2_0] = mmNIC1_DBG_BMON2_0_BASE, + [GAUDI2_BMON_NIC1_DBG_0_1] = mmNIC1_DBG_BMON0_1_BASE, + [GAUDI2_BMON_NIC1_DBG_1_1] = mmNIC1_DBG_BMON1_1_BASE, + [GAUDI2_BMON_NIC1_DBG_2_1] = mmNIC1_DBG_BMON2_1_BASE, + [GAUDI2_BMON_NIC2_DBG_0_0] = mmNIC2_DBG_BMON0_0_BASE, + [GAUDI2_BMON_NIC2_DBG_1_0] = mmNIC2_DBG_BMON1_0_BASE, + [GAUDI2_BMON_NIC2_DBG_2_0] = mmNIC2_DBG_BMON2_0_BASE, + [GAUDI2_BMON_NIC2_DBG_0_1] = mmNIC2_DBG_BMON0_1_BASE, + [GAUDI2_BMON_NIC2_DBG_1_1] = mmNIC2_DBG_BMON1_1_BASE, + [GAUDI2_BMON_NIC2_DBG_2_1] = mmNIC2_DBG_BMON2_1_BASE, + [GAUDI2_BMON_NIC3_DBG_0_0] = mmNIC3_DBG_BMON0_0_BASE, + [GAUDI2_BMON_NIC3_DBG_1_0] = mmNIC3_DBG_BMON1_0_BASE, + [GAUDI2_BMON_NIC3_DBG_2_0] = mmNIC3_DBG_BMON2_0_BASE, + [GAUDI2_BMON_NIC3_DBG_0_1] = mmNIC3_DBG_BMON0_1_BASE, + [GAUDI2_BMON_NIC3_DBG_1_1] = mmNIC3_DBG_BMON1_1_BASE, + [GAUDI2_BMON_NIC3_DBG_2_1] = mmNIC3_DBG_BMON2_1_BASE, + [GAUDI2_BMON_NIC4_DBG_0_0] = mmNIC4_DBG_BMON0_0_BASE, + [GAUDI2_BMON_NIC4_DBG_1_0] = mmNIC4_DBG_BMON1_0_BASE, + [GAUDI2_BMON_NIC4_DBG_2_0] = mmNIC4_DBG_BMON2_0_BASE, + [GAUDI2_BMON_NIC4_DBG_0_1] = mmNIC4_DBG_BMON0_1_BASE, + [GAUDI2_BMON_NIC4_DBG_1_1] = mmNIC4_DBG_BMON1_1_BASE, + [GAUDI2_BMON_NIC4_DBG_2_1] = mmNIC4_DBG_BMON2_1_BASE, + [GAUDI2_BMON_NIC5_DBG_0_0] = mmNIC5_DBG_BMON0_0_BASE, + [GAUDI2_BMON_NIC5_DBG_1_0] = mmNIC5_DBG_BMON1_0_BASE, + [GAUDI2_BMON_NIC5_DBG_2_0] = mmNIC5_DBG_BMON2_0_BASE, + [GAUDI2_BMON_NIC5_DBG_0_1] = mmNIC5_DBG_BMON0_1_BASE, + [GAUDI2_BMON_NIC5_DBG_1_1] = mmNIC5_DBG_BMON1_1_BASE, + [GAUDI2_BMON_NIC5_DBG_2_1] = mmNIC5_DBG_BMON2_1_BASE, + [GAUDI2_BMON_NIC6_DBG_0_0] = mmNIC6_DBG_BMON0_0_BASE, + [GAUDI2_BMON_NIC6_DBG_1_0] = mmNIC6_DBG_BMON1_0_BASE, + [GAUDI2_BMON_NIC6_DBG_2_0] = mmNIC6_DBG_BMON2_0_BASE, + [GAUDI2_BMON_NIC6_DBG_0_1] = mmNIC6_DBG_BMON0_1_BASE, + [GAUDI2_BMON_NIC6_DBG_1_1] = mmNIC6_DBG_BMON1_1_BASE, + [GAUDI2_BMON_NIC6_DBG_2_1] = mmNIC6_DBG_BMON2_1_BASE, + [GAUDI2_BMON_NIC7_DBG_0_0] = mmNIC7_DBG_BMON0_0_BASE, + [GAUDI2_BMON_NIC7_DBG_1_0] = mmNIC7_DBG_BMON1_0_BASE, + [GAUDI2_BMON_NIC7_DBG_2_0] = mmNIC7_DBG_BMON2_0_BASE, + [GAUDI2_BMON_NIC7_DBG_0_1] = mmNIC7_DBG_BMON0_1_BASE, + [GAUDI2_BMON_NIC7_DBG_1_1] = mmNIC7_DBG_BMON1_1_BASE, + [GAUDI2_BMON_NIC7_DBG_2_1] = mmNIC7_DBG_BMON2_1_BASE, + [GAUDI2_BMON_NIC8_DBG_0_0] = mmNIC8_DBG_BMON0_0_BASE, + [GAUDI2_BMON_NIC8_DBG_1_0] = mmNIC8_DBG_BMON1_0_BASE, + [GAUDI2_BMON_NIC8_DBG_2_0] = mmNIC8_DBG_BMON2_0_BASE, + [GAUDI2_BMON_NIC8_DBG_0_1] = mmNIC8_DBG_BMON0_1_BASE, + [GAUDI2_BMON_NIC8_DBG_1_1] = mmNIC8_DBG_BMON1_1_BASE, + [GAUDI2_BMON_NIC8_DBG_2_1] = mmNIC8_DBG_BMON2_1_BASE, + [GAUDI2_BMON_NIC9_DBG_0_0] = mmNIC9_DBG_BMON0_0_BASE, + [GAUDI2_BMON_NIC9_DBG_1_0] = mmNIC9_DBG_BMON1_0_BASE, + [GAUDI2_BMON_NIC9_DBG_2_0] = mmNIC9_DBG_BMON2_0_BASE, + [GAUDI2_BMON_NIC9_DBG_0_1] = mmNIC9_DBG_BMON0_1_BASE, + [GAUDI2_BMON_NIC9_DBG_1_1] = mmNIC9_DBG_BMON1_1_BASE, + [GAUDI2_BMON_NIC9_DBG_2_1] = mmNIC9_DBG_BMON2_1_BASE, + [GAUDI2_BMON_NIC10_DBG_0_0] = mmNIC10_DBG_BMON0_0_BASE, + [GAUDI2_BMON_NIC10_DBG_1_0] = mmNIC10_DBG_BMON1_0_BASE, + [GAUDI2_BMON_NIC10_DBG_2_0] = mmNIC10_DBG_BMON2_0_BASE, + [GAUDI2_BMON_NIC10_DBG_0_1] = mmNIC10_DBG_BMON0_1_BASE, + [GAUDI2_BMON_NIC10_DBG_1_1] = mmNIC10_DBG_BMON1_1_BASE, + [GAUDI2_BMON_NIC10_DBG_2_1] = mmNIC10_DBG_BMON2_1_BASE, + [GAUDI2_BMON_NIC11_DBG_0_0] = mmNIC11_DBG_BMON0_0_BASE, + [GAUDI2_BMON_NIC11_DBG_1_0] = mmNIC11_DBG_BMON1_0_BASE, + [GAUDI2_BMON_NIC11_DBG_2_0] = mmNIC11_DBG_BMON2_0_BASE, + [GAUDI2_BMON_NIC11_DBG_0_1] = mmNIC11_DBG_BMON0_1_BASE, + [GAUDI2_BMON_NIC11_DBG_1_1] = mmNIC11_DBG_BMON1_1_BASE, + [GAUDI2_BMON_NIC11_DBG_2_1] = mmNIC11_DBG_BMON2_1_BASE +}; + +static u64 debug_spmu_regs[GAUDI2_SPMU_LAST + 1] = { + [GAUDI2_SPMU_DCORE0_TPC0_EML] = mmDCORE0_TPC0_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE0_TPC1_EML] = mmDCORE0_TPC1_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE0_TPC2_EML] = mmDCORE0_TPC2_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE0_TPC3_EML] = mmDCORE0_TPC3_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE0_TPC4_EML] = mmDCORE0_TPC4_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE0_TPC5_EML] = mmDCORE0_TPC5_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE0_TPC6_EML] = mmDCORE0_TPC6_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE1_TPC0_EML] = mmDCORE1_TPC0_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE1_TPC1_EML] = mmDCORE1_TPC1_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE1_TPC2_EML] = mmDCORE1_TPC2_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE1_TPC3_EML] = mmDCORE1_TPC3_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE1_TPC4_EML] = mmDCORE1_TPC4_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE1_TPC5_EML] = mmDCORE1_TPC5_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE2_TPC0_EML] = mmDCORE2_TPC0_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE2_TPC1_EML] = mmDCORE2_TPC1_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE2_TPC2_EML] = mmDCORE2_TPC2_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE2_TPC3_EML] = mmDCORE2_TPC3_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE2_TPC4_EML] = mmDCORE2_TPC4_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE2_TPC5_EML] = mmDCORE2_TPC5_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE3_TPC0_EML] = mmDCORE3_TPC0_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE3_TPC1_EML] = mmDCORE3_TPC1_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE3_TPC2_EML] = mmDCORE3_TPC2_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE3_TPC3_EML] = mmDCORE3_TPC3_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE3_TPC4_EML] = mmDCORE3_TPC4_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE3_TPC5_EML] = mmDCORE3_TPC5_EML_SPMU_BASE, + [GAUDI2_SPMU_DCORE0_HMMU0_CS] = mmDCORE0_HMMU0_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE0_HMMU1_CS] = mmDCORE0_HMMU1_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE0_HMMU2_CS] = mmDCORE0_HMMU2_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE0_HMMU3_CS] = mmDCORE0_HMMU3_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE0_MME_CTRL] = mmDCORE0_MME_CTRL_SPMU_BASE, + [GAUDI2_SPMU_DCORE0_MME_SBTE0] = mmDCORE0_MME_SBTE0_SPMU_BASE, + [GAUDI2_SPMU_DCORE0_MME_SBTE1] = mmDCORE0_MME_SBTE1_SPMU_BASE, + [GAUDI2_SPMU_DCORE0_MME_SBTE2] = mmDCORE0_MME_SBTE2_SPMU_BASE, + [GAUDI2_SPMU_DCORE0_MME_SBTE3] = mmDCORE0_MME_SBTE3_SPMU_BASE, + [GAUDI2_SPMU_DCORE0_MME_SBTE4] = mmDCORE0_MME_SBTE4_SPMU_BASE, + [GAUDI2_SPMU_DCORE0_MME_ACC] = mmDCORE0_MME_ACC_SPMU_BASE, + [GAUDI2_SPMU_DCORE0_SM] = mmDCORE0_SM_SPMU_BASE, + [GAUDI2_SPMU_DCORE0_EDMA0_CS] = mmDCORE0_EDMA0_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE0_EDMA1_CS] = mmDCORE0_EDMA1_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE0_VDEC0_CS] = mmDCORE0_VDEC0_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE0_VDEC1_CS] = mmDCORE0_VDEC1_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE1_HMMU0_CS] = mmDCORE1_HMMU0_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE1_HMMU1_CS] = mmDCORE1_HMMU1_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE1_HMMU2_CS] = mmDCORE1_HMMU2_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE1_HMMU3_CS] = mmDCORE1_HMMU3_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE1_MME_CTRL] = mmDCORE1_MME_CTRL_SPMU_BASE, + [GAUDI2_SPMU_DCORE1_MME_SBTE0] = mmDCORE1_MME_SBTE0_SPMU_BASE, + [GAUDI2_SPMU_DCORE1_MME_SBTE1] = mmDCORE1_MME_SBTE1_SPMU_BASE, + [GAUDI2_SPMU_DCORE1_MME_SBTE2] = mmDCORE1_MME_SBTE2_SPMU_BASE, + [GAUDI2_SPMU_DCORE1_MME_SBTE3] = mmDCORE1_MME_SBTE3_SPMU_BASE, + [GAUDI2_SPMU_DCORE1_MME_SBTE4] = mmDCORE1_MME_SBTE4_SPMU_BASE, + [GAUDI2_SPMU_DCORE1_MME_ACC] = mmDCORE1_MME_ACC_SPMU_BASE, + [GAUDI2_SPMU_DCORE1_SM] = mmDCORE1_SM_SPMU_BASE, + [GAUDI2_SPMU_DCORE1_EDMA0_CS] = mmDCORE1_EDMA0_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE1_EDMA1_CS] = mmDCORE1_EDMA1_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE1_VDEC0_CS] = mmDCORE1_VDEC0_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE1_VDEC1_CS] = mmDCORE1_VDEC1_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE2_HMMU0_CS] = mmDCORE2_HMMU0_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE2_HMMU1_CS] = mmDCORE2_HMMU1_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE2_HMMU2_CS] = mmDCORE2_HMMU2_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE2_HMMU3_CS] = mmDCORE2_HMMU3_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE2_MME_CTRL] = mmDCORE2_MME_CTRL_SPMU_BASE, + [GAUDI2_SPMU_DCORE2_MME_SBTE0] = mmDCORE2_MME_SBTE0_SPMU_BASE, + [GAUDI2_SPMU_DCORE2_MME_SBTE1] = mmDCORE2_MME_SBTE1_SPMU_BASE, + [GAUDI2_SPMU_DCORE2_MME_SBTE2] = mmDCORE2_MME_SBTE2_SPMU_BASE, + [GAUDI2_SPMU_DCORE2_MME_SBTE3] = mmDCORE2_MME_SBTE3_SPMU_BASE, + [GAUDI2_SPMU_DCORE2_MME_SBTE4] = mmDCORE2_MME_SBTE4_SPMU_BASE, + [GAUDI2_SPMU_DCORE2_MME_ACC] = mmDCORE2_MME_ACC_SPMU_BASE, + [GAUDI2_SPMU_DCORE2_SM] = mmDCORE2_SM_SPMU_BASE, + [GAUDI2_SPMU_DCORE2_EDMA0_CS] = mmDCORE2_EDMA0_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE2_EDMA1_CS] = mmDCORE2_EDMA1_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE2_VDEC0_CS] = mmDCORE2_VDEC0_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE2_VDEC1_CS] = mmDCORE2_VDEC1_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE3_HMMU0_CS] = mmDCORE3_HMMU0_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE3_HMMU1_CS] = mmDCORE3_HMMU1_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE3_HMMU2_CS] = mmDCORE3_HMMU2_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE3_HMMU3_CS] = mmDCORE3_HMMU3_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE3_MME_CTRL] = mmDCORE3_MME_CTRL_SPMU_BASE, + [GAUDI2_SPMU_DCORE3_MME_SBTE0] = mmDCORE3_MME_SBTE0_SPMU_BASE, + [GAUDI2_SPMU_DCORE3_MME_SBTE1] = mmDCORE3_MME_SBTE1_SPMU_BASE, + [GAUDI2_SPMU_DCORE3_MME_SBTE2] = mmDCORE3_MME_SBTE2_SPMU_BASE, + [GAUDI2_SPMU_DCORE3_MME_SBTE3] = mmDCORE3_MME_SBTE3_SPMU_BASE, + [GAUDI2_SPMU_DCORE3_MME_SBTE4] = mmDCORE3_MME_SBTE4_SPMU_BASE, + [GAUDI2_SPMU_DCORE3_MME_ACC] = mmDCORE3_MME_ACC_SPMU_BASE, + [GAUDI2_SPMU_DCORE3_SM] = mmDCORE3_SM_SPMU_BASE, + [GAUDI2_SPMU_DCORE3_EDMA0_CS] = mmDCORE3_EDMA0_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE3_EDMA1_CS] = mmDCORE3_EDMA1_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE3_VDEC0_CS] = mmDCORE3_VDEC0_CS_SPMU_BASE, + [GAUDI2_SPMU_DCORE3_VDEC1_CS] = mmDCORE3_VDEC1_CS_SPMU_BASE, + [GAUDI2_SPMU_PCIE] = mmPCIE_SPMU_BASE, + [GAUDI2_SPMU_PSOC_ARC0_CS] = mmPSOC_ARC0_CS_SPMU_BASE, + [GAUDI2_SPMU_PSOC_ARC1_CS] = mmPSOC_ARC1_CS_SPMU_BASE, + [GAUDI2_SPMU_PDMA0_CS] = mmPDMA0_CS_SPMU_BASE, + [GAUDI2_SPMU_PDMA1_CS] = mmPDMA1_CS_SPMU_BASE, + [GAUDI2_SPMU_PMMU_CS] = mmPMMU_CS_SPMU_BASE, + [GAUDI2_SPMU_ROT0_CS] = mmROT0_CS_SPMU_BASE, + [GAUDI2_SPMU_ROT1_CS] = mmROT1_CS_SPMU_BASE, + [GAUDI2_SPMU_ARC_FARM_CS] = mmARC_FARM_CS_SPMU_BASE, + [GAUDI2_SPMU_KDMA_CS] = mmKDMA_CS_SPMU_BASE, + [GAUDI2_SPMU_PCIE_VDEC0_CS] = mmPCIE_VDEC0_CS_SPMU_BASE, + [GAUDI2_SPMU_PCIE_VDEC1_CS] = mmPCIE_VDEC1_CS_SPMU_BASE, + [GAUDI2_SPMU_HBM0_MC0_CS] = mmHBM0_MC0_CS_SPMU_BASE, + [GAUDI2_SPMU_HBM0_MC1_CS] = mmHBM0_MC1_CS_SPMU_BASE, + [GAUDI2_SPMU_HBM1_MC0_CS] = mmHBM1_MC0_CS_SPMU_BASE, + [GAUDI2_SPMU_HBM1_MC1_CS] = mmHBM1_MC1_CS_SPMU_BASE, + [GAUDI2_SPMU_HBM2_MC0_CS] = mmHBM2_MC0_CS_SPMU_BASE, + [GAUDI2_SPMU_HBM2_MC1_CS] = mmHBM2_MC1_CS_SPMU_BASE, + [GAUDI2_SPMU_HBM3_MC0_CS] = mmHBM3_MC0_CS_SPMU_BASE, + [GAUDI2_SPMU_HBM3_MC1_CS] = mmHBM3_MC1_CS_SPMU_BASE, + [GAUDI2_SPMU_HBM4_MC0_CS] = mmHBM4_MC0_CS_SPMU_BASE, + [GAUDI2_SPMU_HBM4_MC1_CS] = mmHBM4_MC1_CS_SPMU_BASE, + [GAUDI2_SPMU_HBM5_MC0_CS] = mmHBM5_MC0_CS_SPMU_BASE, + [GAUDI2_SPMU_HBM5_MC1_CS] = mmHBM5_MC1_CS_SPMU_BASE, + [GAUDI2_SPMU_NIC0_DBG_0] = mmNIC0_DBG_SPMU_0_BASE, + [GAUDI2_SPMU_NIC0_DBG_1] = mmNIC0_DBG_SPMU_1_BASE, + [GAUDI2_SPMU_NIC1_DBG_0] = mmNIC1_DBG_SPMU_0_BASE, + [GAUDI2_SPMU_NIC1_DBG_1] = mmNIC1_DBG_SPMU_1_BASE, + [GAUDI2_SPMU_NIC2_DBG_0] = mmNIC2_DBG_SPMU_0_BASE, + [GAUDI2_SPMU_NIC2_DBG_1] = mmNIC2_DBG_SPMU_1_BASE, + [GAUDI2_SPMU_NIC3_DBG_0] = mmNIC3_DBG_SPMU_0_BASE, + [GAUDI2_SPMU_NIC3_DBG_1] = mmNIC3_DBG_SPMU_1_BASE, + [GAUDI2_SPMU_NIC4_DBG_0] = mmNIC4_DBG_SPMU_0_BASE, + [GAUDI2_SPMU_NIC4_DBG_1] = mmNIC4_DBG_SPMU_1_BASE, + [GAUDI2_SPMU_NIC5_DBG_0] = mmNIC5_DBG_SPMU_0_BASE, + [GAUDI2_SPMU_NIC5_DBG_1] = mmNIC5_DBG_SPMU_1_BASE, + [GAUDI2_SPMU_NIC6_DBG_0] = mmNIC6_DBG_SPMU_0_BASE, + [GAUDI2_SPMU_NIC6_DBG_1] = mmNIC6_DBG_SPMU_1_BASE, + [GAUDI2_SPMU_NIC7_DBG_0] = mmNIC7_DBG_SPMU_0_BASE, + [GAUDI2_SPMU_NIC7_DBG_1] = mmNIC7_DBG_SPMU_1_BASE, + [GAUDI2_SPMU_NIC8_DBG_0] = mmNIC8_DBG_SPMU_0_BASE, + [GAUDI2_SPMU_NIC8_DBG_1] = mmNIC8_DBG_SPMU_1_BASE, + [GAUDI2_SPMU_NIC9_DBG_0] = mmNIC9_DBG_SPMU_0_BASE, + [GAUDI2_SPMU_NIC9_DBG_1] = mmNIC9_DBG_SPMU_1_BASE, + [GAUDI2_SPMU_NIC10_DBG_0] = mmNIC10_DBG_SPMU_0_BASE, + [GAUDI2_SPMU_NIC10_DBG_1] = mmNIC10_DBG_SPMU_1_BASE, + [GAUDI2_SPMU_NIC11_DBG_0] = mmNIC11_DBG_SPMU_0_BASE, + [GAUDI2_SPMU_NIC11_DBG_1] = mmNIC11_DBG_SPMU_1_BASE +}; + +static struct component_config_offsets xbar_edge_binning_cfg_table[XBAR_EDGE_ID_SIZE] = { + [XBAR_EDGE_ID_DCORE0] = { + .funnel_id = GAUDI2_FUNNEL_DCORE0_XBAR_EDGE, + .etf_id = COMPONENT_ID_INVALID, + .stm_id = COMPONENT_ID_INVALID, + .spmu_id = COMPONENT_ID_INVALID, + .bmon_count = 0, + .bmon_ids = {COMPONENT_ID_INVALID} + }, + [XBAR_EDGE_ID_DCORE1] = { + .funnel_id = GAUDI2_FUNNEL_DCORE1_XBAR_EDGE, + .etf_id = COMPONENT_ID_INVALID, + .stm_id = COMPONENT_ID_INVALID, + .spmu_id = COMPONENT_ID_INVALID, + .bmon_count = 0, + .bmon_ids = {COMPONENT_ID_INVALID} + }, + [XBAR_EDGE_ID_DCORE2] = { + .funnel_id = GAUDI2_FUNNEL_DCORE2_XBAR_EDGE, + .etf_id = COMPONENT_ID_INVALID, + .stm_id = COMPONENT_ID_INVALID, + .spmu_id = COMPONENT_ID_INVALID, + .bmon_count = 0, + .bmon_ids = {COMPONENT_ID_INVALID} + }, + [XBAR_EDGE_ID_DCORE3] = { + .funnel_id = GAUDI2_FUNNEL_DCORE3_XBAR_EDGE, + .etf_id = COMPONENT_ID_INVALID, + .stm_id = COMPONENT_ID_INVALID, + .spmu_id = COMPONENT_ID_INVALID, + .bmon_count = 0, + .bmon_ids = {COMPONENT_ID_INVALID} + }, +}; + + +static struct component_config_offsets hmmu_binning_cfg_table[HMMU_ID_SIZE] = { + [HMMU_ID_DCORE0_HMMU0] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE0_HMMU0_CS, + .stm_id = GAUDI2_STM_DCORE0_HMMU0_CS, + .spmu_id = GAUDI2_SPMU_DCORE0_HMMU0_CS, + .bmon_count = 5, + .bmon_ids = { + GAUDI2_BMON_DCORE0_HMMU0_0, + GAUDI2_BMON_DCORE0_HMMU0_1, + GAUDI2_BMON_DCORE0_HMMU0_2, + GAUDI2_BMON_DCORE0_HMMU0_3, + GAUDI2_BMON_DCORE0_HMMU0_4, + } + }, + [HMMU_ID_DCORE0_HMMU1] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE0_HMMU1_CS, + .stm_id = GAUDI2_STM_DCORE0_HMMU1_CS, + .spmu_id = GAUDI2_SPMU_DCORE0_HMMU1_CS, + .bmon_count = 5, + .bmon_ids = { + GAUDI2_BMON_DCORE0_HMMU1_0, + GAUDI2_BMON_DCORE0_HMMU1_1, + GAUDI2_BMON_DCORE0_HMMU1_2, + GAUDI2_BMON_DCORE0_HMMU1_3, + GAUDI2_BMON_DCORE0_HMMU1_4, + } + }, + [HMMU_ID_DCORE0_HMMU2] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE0_HMMU2_CS, + .stm_id = GAUDI2_STM_DCORE0_HMMU2_CS, + .spmu_id = GAUDI2_SPMU_DCORE0_HMMU2_CS, + .bmon_count = 5, + .bmon_ids = { + GAUDI2_BMON_DCORE0_HMMU2_0, + GAUDI2_BMON_DCORE0_HMMU2_1, + GAUDI2_BMON_DCORE0_HMMU2_2, + GAUDI2_BMON_DCORE0_HMMU2_3, + GAUDI2_BMON_DCORE0_HMMU2_4, + } + }, + [HMMU_ID_DCORE0_HMMU3] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE0_HMMU3_CS, + .stm_id = GAUDI2_STM_DCORE0_HMMU3_CS, + .spmu_id = GAUDI2_SPMU_DCORE0_HMMU3_CS, + .bmon_count = 5, + .bmon_ids = { + GAUDI2_BMON_DCORE0_HMMU3_0, + GAUDI2_BMON_DCORE0_HMMU3_1, + GAUDI2_BMON_DCORE0_HMMU3_2, + GAUDI2_BMON_DCORE0_HMMU3_3, + GAUDI2_BMON_DCORE0_HMMU3_4, + } + }, + [HMMU_ID_DCORE1_HMMU0] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE1_HMMU0_CS, + .stm_id = GAUDI2_STM_DCORE1_HMMU0_CS, + .spmu_id = GAUDI2_SPMU_DCORE1_HMMU0_CS, + .bmon_count = 5, + .bmon_ids = { + GAUDI2_BMON_DCORE1_HMMU0_0, + GAUDI2_BMON_DCORE1_HMMU0_1, + GAUDI2_BMON_DCORE1_HMMU0_2, + GAUDI2_BMON_DCORE1_HMMU0_3, + GAUDI2_BMON_DCORE1_HMMU0_4, + } + }, + [HMMU_ID_DCORE1_HMMU1] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE1_HMMU1_CS, + .stm_id = GAUDI2_STM_DCORE1_HMMU1_CS, + .spmu_id = GAUDI2_SPMU_DCORE1_HMMU1_CS, + .bmon_count = 5, + .bmon_ids = { + GAUDI2_BMON_DCORE1_HMMU1_0, + GAUDI2_BMON_DCORE1_HMMU1_1, + GAUDI2_BMON_DCORE1_HMMU1_2, + GAUDI2_BMON_DCORE1_HMMU1_3, + GAUDI2_BMON_DCORE1_HMMU1_4, + } + }, + [HMMU_ID_DCORE1_HMMU2] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE1_HMMU2_CS, + .stm_id = GAUDI2_STM_DCORE1_HMMU2_CS, + .spmu_id = GAUDI2_SPMU_DCORE1_HMMU2_CS, + .bmon_count = 5, + .bmon_ids = { + GAUDI2_BMON_DCORE1_HMMU2_0, + GAUDI2_BMON_DCORE1_HMMU2_1, + GAUDI2_BMON_DCORE1_HMMU2_2, + GAUDI2_BMON_DCORE1_HMMU2_3, + GAUDI2_BMON_DCORE1_HMMU2_4, + } + }, + [HMMU_ID_DCORE1_HMMU3] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE1_HMMU3_CS, + .stm_id = GAUDI2_STM_DCORE1_HMMU3_CS, + .spmu_id = GAUDI2_SPMU_DCORE1_HMMU3_CS, + .bmon_count = 5, + .bmon_ids = { + GAUDI2_BMON_DCORE1_HMMU3_0, + GAUDI2_BMON_DCORE1_HMMU3_1, + GAUDI2_BMON_DCORE1_HMMU3_2, + GAUDI2_BMON_DCORE1_HMMU3_3, + GAUDI2_BMON_DCORE1_HMMU3_4, + } + }, + [HMMU_ID_DCORE2_HMMU0] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE2_HMMU0_CS, + .stm_id = GAUDI2_STM_DCORE2_HMMU0_CS, + .spmu_id = GAUDI2_SPMU_DCORE2_HMMU0_CS, + .bmon_count = 5, + .bmon_ids = { + GAUDI2_BMON_DCORE2_HMMU0_0, + GAUDI2_BMON_DCORE2_HMMU0_1, + GAUDI2_BMON_DCORE2_HMMU0_2, + GAUDI2_BMON_DCORE2_HMMU0_3, + GAUDI2_BMON_DCORE2_HMMU0_4, + } + }, + [HMMU_ID_DCORE2_HMMU1] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE2_HMMU1_CS, + .stm_id = GAUDI2_STM_DCORE2_HMMU1_CS, + .spmu_id = GAUDI2_SPMU_DCORE2_HMMU1_CS, + .bmon_count = 5, + .bmon_ids = { + GAUDI2_BMON_DCORE2_HMMU1_0, + GAUDI2_BMON_DCORE2_HMMU1_1, + GAUDI2_BMON_DCORE2_HMMU1_2, + GAUDI2_BMON_DCORE2_HMMU1_3, + GAUDI2_BMON_DCORE2_HMMU1_4, + } + }, + [HMMU_ID_DCORE2_HMMU2] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE2_HMMU2_CS, + .stm_id = GAUDI2_STM_DCORE2_HMMU2_CS, + .spmu_id = GAUDI2_SPMU_DCORE2_HMMU2_CS, + .bmon_count = 5, + .bmon_ids = { + GAUDI2_BMON_DCORE2_HMMU2_0, + GAUDI2_BMON_DCORE2_HMMU2_1, + GAUDI2_BMON_DCORE2_HMMU2_2, + GAUDI2_BMON_DCORE2_HMMU2_3, + GAUDI2_BMON_DCORE2_HMMU2_4, + } + }, + [HMMU_ID_DCORE2_HMMU3] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE2_HMMU3_CS, + .stm_id = GAUDI2_STM_DCORE2_HMMU3_CS, + .spmu_id = GAUDI2_SPMU_DCORE2_HMMU3_CS, + .bmon_count = 5, + .bmon_ids = { + GAUDI2_BMON_DCORE2_HMMU3_0, + GAUDI2_BMON_DCORE2_HMMU3_1, + GAUDI2_BMON_DCORE2_HMMU3_2, + GAUDI2_BMON_DCORE2_HMMU3_3, + GAUDI2_BMON_DCORE2_HMMU3_4, + } + }, + [HMMU_ID_DCORE3_HMMU0] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE3_HMMU0_CS, + .stm_id = GAUDI2_STM_DCORE3_HMMU0_CS, + .spmu_id = GAUDI2_SPMU_DCORE3_HMMU0_CS, + .bmon_count = 5, + .bmon_ids = { + GAUDI2_BMON_DCORE3_HMMU0_0, + GAUDI2_BMON_DCORE3_HMMU0_1, + GAUDI2_BMON_DCORE3_HMMU0_2, + GAUDI2_BMON_DCORE3_HMMU0_3, + GAUDI2_BMON_DCORE3_HMMU0_4, + } + }, + [HMMU_ID_DCORE3_HMMU1] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE3_HMMU1_CS, + .stm_id = GAUDI2_STM_DCORE3_HMMU1_CS, + .spmu_id = GAUDI2_SPMU_DCORE3_HMMU1_CS, + .bmon_count = 5, + .bmon_ids = { + GAUDI2_BMON_DCORE3_HMMU1_0, + GAUDI2_BMON_DCORE3_HMMU1_1, + GAUDI2_BMON_DCORE3_HMMU1_2, + GAUDI2_BMON_DCORE3_HMMU1_3, + GAUDI2_BMON_DCORE3_HMMU1_4, + } + }, + [HMMU_ID_DCORE3_HMMU2] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE3_HMMU2_CS, + .stm_id = GAUDI2_STM_DCORE3_HMMU2_CS, + .spmu_id = GAUDI2_SPMU_DCORE3_HMMU2_CS, + .bmon_count = 5, + .bmon_ids = { + GAUDI2_BMON_DCORE3_HMMU2_0, + GAUDI2_BMON_DCORE3_HMMU2_1, + GAUDI2_BMON_DCORE3_HMMU2_2, + GAUDI2_BMON_DCORE3_HMMU2_3, + GAUDI2_BMON_DCORE3_HMMU2_4, + } + }, + [HMMU_ID_DCORE3_HMMU3] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE3_HMMU3_CS, + .stm_id = GAUDI2_STM_DCORE3_HMMU3_CS, + .spmu_id = GAUDI2_SPMU_DCORE3_HMMU3_CS, + .bmon_count = 5, + .bmon_ids = { + GAUDI2_BMON_DCORE3_HMMU3_0, + GAUDI2_BMON_DCORE3_HMMU3_1, + GAUDI2_BMON_DCORE3_HMMU3_2, + GAUDI2_BMON_DCORE3_HMMU3_3, + GAUDI2_BMON_DCORE3_HMMU3_4, + } + }, +}; + +static struct component_config_offsets hbm_mc0_binning_cfg_table[HBM_ID_SIZE] = { + [HBM_ID0] = { + .funnel_id = GAUDI2_FUNNEL_HBM0_MC0, + .etf_id = GAUDI2_ETF_HBM0_MC0_CS, + .stm_id = GAUDI2_STM_HBM0_MC0_CS, + .spmu_id = GAUDI2_SPMU_HBM0_MC0_CS, + .bmon_count = 0, + .bmon_ids = {COMPONENT_ID_INVALID} + }, + [HBM_ID1] = { + .funnel_id = GAUDI2_FUNNEL_HBM1_MC0, + .etf_id = GAUDI2_ETF_HBM1_MC0_CS, + .stm_id = GAUDI2_STM_HBM1_MC0_CS, + .spmu_id = GAUDI2_SPMU_HBM1_MC0_CS, + .bmon_count = 0, + .bmon_ids = {COMPONENT_ID_INVALID} + }, + [HBM_ID2] = { + .funnel_id = GAUDI2_FUNNEL_HBM2_MC0, + .etf_id = GAUDI2_ETF_HBM2_MC0_CS, + .stm_id = GAUDI2_STM_HBM2_MC0_CS, + .spmu_id = GAUDI2_SPMU_HBM2_MC0_CS, + .bmon_count = 0, + .bmon_ids = {COMPONENT_ID_INVALID} + }, + [HBM_ID3] = { + .funnel_id = GAUDI2_FUNNEL_HBM3_MC0, + .etf_id = GAUDI2_ETF_HBM3_MC0_CS, + .stm_id = GAUDI2_STM_HBM3_MC0_CS, + .spmu_id = GAUDI2_SPMU_HBM3_MC0_CS, + .bmon_count = 0, + .bmon_ids = {COMPONENT_ID_INVALID} + }, + [HBM_ID4] = { + .funnel_id = GAUDI2_FUNNEL_HBM4_MC0, + .etf_id = GAUDI2_ETF_HBM4_MC0_CS, + .stm_id = GAUDI2_STM_HBM4_MC0_CS, + .spmu_id = GAUDI2_SPMU_HBM4_MC0_CS, + .bmon_count = 0, + .bmon_ids = {COMPONENT_ID_INVALID} + }, + [HBM_ID5] = { + .funnel_id = GAUDI2_FUNNEL_HBM5_MC0, + .etf_id = GAUDI2_ETF_HBM5_MC0_CS, + .stm_id = GAUDI2_STM_HBM5_MC0_CS, + .spmu_id = GAUDI2_SPMU_HBM5_MC0_CS, + .bmon_count = 0, + .bmon_ids = {COMPONENT_ID_INVALID} + }, +}; + +static struct component_config_offsets hbm_mc1_binning_cfg_table[HBM_ID_SIZE] = { + [HBM_ID0] = { + .funnel_id = GAUDI2_FUNNEL_HBM0_MC1, + .etf_id = GAUDI2_ETF_HBM0_MC1_CS, + .stm_id = GAUDI2_STM_HBM0_MC1_CS, + .spmu_id = GAUDI2_SPMU_HBM0_MC1_CS, + .bmon_count = 0, + .bmon_ids = {COMPONENT_ID_INVALID} + }, + [HBM_ID1] = { + .funnel_id = GAUDI2_FUNNEL_HBM1_MC1, + .etf_id = GAUDI2_ETF_HBM1_MC1_CS, + .stm_id = GAUDI2_STM_HBM1_MC1_CS, + .spmu_id = GAUDI2_SPMU_HBM1_MC1_CS, + .bmon_count = 0, + .bmon_ids = {COMPONENT_ID_INVALID} + }, + [HBM_ID2] = { + .funnel_id = GAUDI2_FUNNEL_HBM2_MC1, + .etf_id = GAUDI2_ETF_HBM2_MC1_CS, + .stm_id = GAUDI2_STM_HBM2_MC1_CS, + .spmu_id = GAUDI2_SPMU_HBM2_MC1_CS, + .bmon_count = 0, + .bmon_ids = {COMPONENT_ID_INVALID} + }, + [HBM_ID3] = { + .funnel_id = GAUDI2_FUNNEL_HBM3_MC1, + .etf_id = GAUDI2_ETF_HBM3_MC1_CS, + .stm_id = GAUDI2_STM_HBM3_MC1_CS, + .spmu_id = GAUDI2_SPMU_HBM3_MC1_CS, + .bmon_count = 0, + .bmon_ids = {COMPONENT_ID_INVALID} + }, + [HBM_ID4] = { + .funnel_id = GAUDI2_FUNNEL_HBM4_MC1, + .etf_id = GAUDI2_ETF_HBM4_MC1_CS, + .stm_id = GAUDI2_STM_HBM4_MC1_CS, + .spmu_id = GAUDI2_SPMU_HBM4_MC1_CS, + .bmon_count = 0, + .bmon_ids = {COMPONENT_ID_INVALID} + }, + [HBM_ID5] = { + .funnel_id = GAUDI2_FUNNEL_HBM5_MC1, + .etf_id = GAUDI2_ETF_HBM5_MC1_CS, + .stm_id = GAUDI2_STM_HBM5_MC1_CS, + .spmu_id = GAUDI2_SPMU_HBM5_MC1_CS, + .bmon_count = 0, + .bmon_ids = {COMPONENT_ID_INVALID} + }, +}; + +static struct component_config_offsets decoder_binning_cfg_table[DEC_ID_SIZE] = { + [DEC_ID_DCORE0_DEC0] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE0_VDEC0_CS, + .stm_id = GAUDI2_STM_DCORE0_VDEC0_CS, + .spmu_id = GAUDI2_SPMU_DCORE0_VDEC0_CS, + .bmon_count = 3, + .bmon_ids = { + GAUDI2_BMON_DCORE0_VDEC0_0, + GAUDI2_BMON_DCORE0_VDEC0_1, + GAUDI2_BMON_DCORE0_VDEC0_2, + } + }, + [DEC_ID_DCORE0_DEC1] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE0_VDEC1_CS, + .stm_id = GAUDI2_STM_DCORE0_VDEC1_CS, + .spmu_id = GAUDI2_SPMU_DCORE0_VDEC1_CS, + .bmon_count = 3, + .bmon_ids = { + GAUDI2_BMON_DCORE0_VDEC1_0, + GAUDI2_BMON_DCORE0_VDEC1_1, + GAUDI2_BMON_DCORE0_VDEC1_2, + } + }, + [DEC_ID_DCORE1_DEC0] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE1_VDEC0_CS, + .stm_id = GAUDI2_STM_DCORE1_VDEC0_CS, + .spmu_id = GAUDI2_SPMU_DCORE1_VDEC0_CS, + .bmon_count = 3, + .bmon_ids = { + GAUDI2_BMON_DCORE1_VDEC0_0, + GAUDI2_BMON_DCORE1_VDEC0_1, + GAUDI2_BMON_DCORE1_VDEC0_2, + } + }, + [DEC_ID_DCORE1_DEC1] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE1_VDEC1_CS, + .stm_id = GAUDI2_STM_DCORE1_VDEC1_CS, + .spmu_id = GAUDI2_SPMU_DCORE1_VDEC1_CS, + .bmon_count = 3, + .bmon_ids = { + GAUDI2_BMON_DCORE1_VDEC1_0, + GAUDI2_BMON_DCORE1_VDEC1_1, + GAUDI2_BMON_DCORE1_VDEC1_2, + } + }, + [DEC_ID_DCORE2_DEC0] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE2_VDEC0_CS, + .stm_id = GAUDI2_STM_DCORE2_VDEC0_CS, + .spmu_id = GAUDI2_SPMU_DCORE2_VDEC0_CS, + .bmon_count = 3, + .bmon_ids = { + GAUDI2_BMON_DCORE2_VDEC0_0, + GAUDI2_BMON_DCORE2_VDEC0_1, + GAUDI2_BMON_DCORE2_VDEC0_2, + } + }, + [DEC_ID_DCORE2_DEC1] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE2_VDEC1_CS, + .stm_id = GAUDI2_STM_DCORE2_VDEC1_CS, + .spmu_id = GAUDI2_SPMU_DCORE2_VDEC1_CS, + .bmon_count = 3, + .bmon_ids = { + GAUDI2_BMON_DCORE2_VDEC1_0, + GAUDI2_BMON_DCORE2_VDEC1_1, + GAUDI2_BMON_DCORE2_VDEC1_2, + } + }, + [DEC_ID_DCORE3_DEC0] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE3_VDEC0_CS, + .stm_id = GAUDI2_STM_DCORE3_VDEC0_CS, + .spmu_id = GAUDI2_SPMU_DCORE3_VDEC0_CS, + .bmon_count = 3, + .bmon_ids = { + GAUDI2_BMON_DCORE3_VDEC0_0, + GAUDI2_BMON_DCORE3_VDEC0_1, + GAUDI2_BMON_DCORE3_VDEC0_2, + } + }, + [DEC_ID_DCORE3_DEC1] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE3_VDEC1_CS, + .stm_id = GAUDI2_STM_DCORE3_VDEC1_CS, + .spmu_id = GAUDI2_SPMU_DCORE3_VDEC1_CS, + .bmon_count = 3, + .bmon_ids = { + GAUDI2_BMON_DCORE3_VDEC1_0, + GAUDI2_BMON_DCORE3_VDEC1_1, + GAUDI2_BMON_DCORE3_VDEC1_2, + } + }, + [DEC_ID_PCIE_VDEC0] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_PCIE_VDEC0_CS, + .stm_id = GAUDI2_STM_PCIE_VDEC0_CS, + .spmu_id = GAUDI2_SPMU_PCIE_VDEC0_CS, + .bmon_count = 3, + .bmon_ids = { + GAUDI2_BMON_PCIE_VDEC0_0, + GAUDI2_BMON_PCIE_VDEC0_1, + GAUDI2_BMON_PCIE_VDEC0_2, + } + }, + [DEC_ID_PCIE_VDEC1] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_PCIE_VDEC1_CS, + .stm_id = GAUDI2_STM_PCIE_VDEC1_CS, + .spmu_id = GAUDI2_SPMU_PCIE_VDEC1_CS, + .bmon_count = 3, + .bmon_ids = { + GAUDI2_BMON_PCIE_VDEC1_0, + GAUDI2_BMON_PCIE_VDEC1_1, + GAUDI2_BMON_PCIE_VDEC1_2, + } + }, +}; + +static struct component_config_offsets edma_binning_cfg_table[EDMA_ID_SIZE] = { + [EDMA_ID_DCORE0_INSTANCE0] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE0_EDMA0_CS, + .stm_id = GAUDI2_STM_DCORE0_EDMA0_CS, + .spmu_id = GAUDI2_SPMU_DCORE0_EDMA0_CS, + .bmon_count = 2, + .bmon_ids = { + GAUDI2_BMON_DCORE0_EDMA0_0, + GAUDI2_BMON_DCORE0_EDMA0_1, + } + }, + [EDMA_ID_DCORE0_INSTANCE1] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE0_EDMA1_CS, + .stm_id = GAUDI2_STM_DCORE0_EDMA1_CS, + .spmu_id = GAUDI2_SPMU_DCORE0_EDMA1_CS, + .bmon_count = 2, + .bmon_ids = { + GAUDI2_BMON_DCORE0_EDMA1_0, + GAUDI2_BMON_DCORE0_EDMA1_1, + } + }, + [EDMA_ID_DCORE1_INSTANCE0] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE1_EDMA0_CS, + .stm_id = GAUDI2_STM_DCORE1_EDMA0_CS, + .spmu_id = GAUDI2_SPMU_DCORE1_EDMA0_CS, + .bmon_count = 2, + .bmon_ids = { + GAUDI2_BMON_DCORE1_EDMA0_0, + GAUDI2_BMON_DCORE1_EDMA0_1, + } + }, + [EDMA_ID_DCORE1_INSTANCE1] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE1_EDMA1_CS, + .stm_id = GAUDI2_STM_DCORE1_EDMA1_CS, + .spmu_id = GAUDI2_SPMU_DCORE1_EDMA1_CS, + .bmon_count = 2, + .bmon_ids = { + GAUDI2_BMON_DCORE1_EDMA1_0, + GAUDI2_BMON_DCORE1_EDMA1_1, + } + }, + [EDMA_ID_DCORE2_INSTANCE0] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE2_EDMA0_CS, + .stm_id = GAUDI2_STM_DCORE2_EDMA0_CS, + .spmu_id = GAUDI2_SPMU_DCORE2_EDMA0_CS, + .bmon_count = 2, + .bmon_ids = { + GAUDI2_BMON_DCORE2_EDMA0_0, + GAUDI2_BMON_DCORE2_EDMA0_1, + } + }, + [EDMA_ID_DCORE2_INSTANCE1] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE2_EDMA1_CS, + .stm_id = GAUDI2_STM_DCORE2_EDMA1_CS, + .spmu_id = GAUDI2_SPMU_DCORE2_EDMA1_CS, + .bmon_count = 2, + .bmon_ids = { + GAUDI2_BMON_DCORE2_EDMA1_0, + GAUDI2_BMON_DCORE2_EDMA1_1, + } + }, + [EDMA_ID_DCORE3_INSTANCE0] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE3_EDMA0_CS, + .stm_id = GAUDI2_STM_DCORE3_EDMA0_CS, + .spmu_id = GAUDI2_SPMU_DCORE3_EDMA0_CS, + .bmon_count = 2, + .bmon_ids = { + GAUDI2_BMON_DCORE3_EDMA0_0, + GAUDI2_BMON_DCORE3_EDMA0_1, + } + }, + [EDMA_ID_DCORE3_INSTANCE1] = { + .funnel_id = COMPONENT_ID_INVALID, + .etf_id = GAUDI2_ETF_DCORE3_EDMA1_CS, + .stm_id = GAUDI2_STM_DCORE3_EDMA1_CS, + .spmu_id = GAUDI2_SPMU_DCORE3_EDMA1_CS, + .bmon_count = 2, + .bmon_ids = { + GAUDI2_BMON_DCORE3_EDMA1_0, + GAUDI2_BMON_DCORE3_EDMA1_1, + } + }, +}; + +static struct component_config_offsets tpc_binning_cfg_table[TPC_ID_SIZE] = { + [TPC_ID_DCORE0_TPC0] = { + .funnel_id = GAUDI2_FUNNEL_DCORE0_TPC0_EML, + .etf_id = GAUDI2_ETF_DCORE0_TPC0_EML, + .stm_id = GAUDI2_STM_DCORE0_TPC0_EML, + .spmu_id = GAUDI2_SPMU_DCORE0_TPC0_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE0_TPC0_EML_0, + GAUDI2_BMON_DCORE0_TPC0_EML_1, + GAUDI2_BMON_DCORE0_TPC0_EML_2, + GAUDI2_BMON_DCORE0_TPC0_EML_3, + } + }, + [TPC_ID_DCORE0_TPC1] = { + .funnel_id = GAUDI2_FUNNEL_DCORE0_TPC1_EML, + .etf_id = GAUDI2_ETF_DCORE0_TPC1_EML, + .stm_id = GAUDI2_STM_DCORE0_TPC1_EML, + .spmu_id = GAUDI2_SPMU_DCORE0_TPC1_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE0_TPC1_EML_0, + GAUDI2_BMON_DCORE0_TPC1_EML_1, + GAUDI2_BMON_DCORE0_TPC1_EML_2, + GAUDI2_BMON_DCORE0_TPC1_EML_3, + } + }, + [TPC_ID_DCORE0_TPC2] = { + .funnel_id = GAUDI2_FUNNEL_DCORE0_TPC2_EML, + .etf_id = GAUDI2_ETF_DCORE0_TPC2_EML, + .stm_id = GAUDI2_STM_DCORE0_TPC2_EML, + .spmu_id = GAUDI2_SPMU_DCORE0_TPC2_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE0_TPC2_EML_0, + GAUDI2_BMON_DCORE0_TPC2_EML_1, + GAUDI2_BMON_DCORE0_TPC2_EML_2, + GAUDI2_BMON_DCORE0_TPC2_EML_3, + } + }, + [TPC_ID_DCORE0_TPC3] = { + .funnel_id = GAUDI2_FUNNEL_DCORE0_TPC3_EML, + .etf_id = GAUDI2_ETF_DCORE0_TPC3_EML, + .stm_id = GAUDI2_STM_DCORE0_TPC3_EML, + .spmu_id = GAUDI2_SPMU_DCORE0_TPC3_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE0_TPC3_EML_0, + GAUDI2_BMON_DCORE0_TPC3_EML_1, + GAUDI2_BMON_DCORE0_TPC3_EML_2, + GAUDI2_BMON_DCORE0_TPC3_EML_3, + } + }, + [TPC_ID_DCORE0_TPC4] = { + .funnel_id = GAUDI2_FUNNEL_DCORE0_TPC4_EML, + .etf_id = GAUDI2_ETF_DCORE0_TPC4_EML, + .stm_id = GAUDI2_STM_DCORE0_TPC4_EML, + .spmu_id = GAUDI2_SPMU_DCORE0_TPC4_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE0_TPC4_EML_0, + GAUDI2_BMON_DCORE0_TPC4_EML_1, + GAUDI2_BMON_DCORE0_TPC4_EML_2, + GAUDI2_BMON_DCORE0_TPC4_EML_3, + } + }, + [TPC_ID_DCORE0_TPC5] = { + .funnel_id = GAUDI2_FUNNEL_DCORE0_TPC5_EML, + .etf_id = GAUDI2_ETF_DCORE0_TPC5_EML, + .stm_id = GAUDI2_STM_DCORE0_TPC5_EML, + .spmu_id = GAUDI2_SPMU_DCORE0_TPC5_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE0_TPC5_EML_0, + GAUDI2_BMON_DCORE0_TPC5_EML_1, + GAUDI2_BMON_DCORE0_TPC5_EML_2, + GAUDI2_BMON_DCORE0_TPC5_EML_3, + } + }, + [TPC_ID_DCORE1_TPC0] = { + .funnel_id = GAUDI2_FUNNEL_DCORE1_TPC0_EML, + .etf_id = GAUDI2_ETF_DCORE1_TPC0_EML, + .stm_id = GAUDI2_STM_DCORE1_TPC0_EML, + .spmu_id = GAUDI2_SPMU_DCORE1_TPC0_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE1_TPC0_EML_0, + GAUDI2_BMON_DCORE1_TPC0_EML_1, + GAUDI2_BMON_DCORE1_TPC0_EML_2, + GAUDI2_BMON_DCORE1_TPC0_EML_3, + } + }, + [TPC_ID_DCORE1_TPC1] = { + .funnel_id = GAUDI2_FUNNEL_DCORE1_TPC1_EML, + .etf_id = GAUDI2_ETF_DCORE1_TPC1_EML, + .stm_id = GAUDI2_STM_DCORE1_TPC1_EML, + .spmu_id = GAUDI2_SPMU_DCORE1_TPC1_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE1_TPC1_EML_0, + GAUDI2_BMON_DCORE1_TPC1_EML_1, + GAUDI2_BMON_DCORE1_TPC1_EML_2, + GAUDI2_BMON_DCORE1_TPC1_EML_3, + } + }, + [TPC_ID_DCORE1_TPC2] = { + .funnel_id = GAUDI2_FUNNEL_DCORE1_TPC2_EML, + .etf_id = GAUDI2_ETF_DCORE1_TPC2_EML, + .stm_id = GAUDI2_STM_DCORE1_TPC2_EML, + .spmu_id = GAUDI2_SPMU_DCORE1_TPC2_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE1_TPC2_EML_0, + GAUDI2_BMON_DCORE1_TPC2_EML_1, + GAUDI2_BMON_DCORE1_TPC2_EML_2, + GAUDI2_BMON_DCORE1_TPC2_EML_3, + } + }, + [TPC_ID_DCORE1_TPC3] = { + .funnel_id = GAUDI2_FUNNEL_DCORE1_TPC3_EML, + .etf_id = GAUDI2_ETF_DCORE1_TPC3_EML, + .stm_id = GAUDI2_STM_DCORE1_TPC3_EML, + .spmu_id = GAUDI2_SPMU_DCORE1_TPC3_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE1_TPC3_EML_0, + GAUDI2_BMON_DCORE1_TPC3_EML_1, + GAUDI2_BMON_DCORE1_TPC3_EML_2, + GAUDI2_BMON_DCORE1_TPC3_EML_3, + } + }, + [TPC_ID_DCORE1_TPC4] = { + .funnel_id = GAUDI2_FUNNEL_DCORE1_TPC4_EML, + .etf_id = GAUDI2_ETF_DCORE1_TPC4_EML, + .stm_id = GAUDI2_STM_DCORE1_TPC4_EML, + .spmu_id = GAUDI2_SPMU_DCORE1_TPC4_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE1_TPC4_EML_0, + GAUDI2_BMON_DCORE1_TPC4_EML_1, + GAUDI2_BMON_DCORE1_TPC4_EML_2, + GAUDI2_BMON_DCORE1_TPC4_EML_3, + } + }, + [TPC_ID_DCORE1_TPC5] = { + .funnel_id = GAUDI2_FUNNEL_DCORE1_TPC5_EML, + .etf_id = GAUDI2_ETF_DCORE1_TPC5_EML, + .stm_id = GAUDI2_STM_DCORE1_TPC5_EML, + .spmu_id = GAUDI2_SPMU_DCORE1_TPC5_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE1_TPC5_EML_0, + GAUDI2_BMON_DCORE1_TPC5_EML_1, + GAUDI2_BMON_DCORE1_TPC5_EML_2, + GAUDI2_BMON_DCORE1_TPC5_EML_3, + } + }, + [TPC_ID_DCORE2_TPC0] = { + .funnel_id = GAUDI2_FUNNEL_DCORE2_TPC0_EML, + .etf_id = GAUDI2_ETF_DCORE2_TPC0_EML, + .stm_id = GAUDI2_STM_DCORE2_TPC0_EML, + .spmu_id = GAUDI2_SPMU_DCORE2_TPC0_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE2_TPC0_EML_0, + GAUDI2_BMON_DCORE2_TPC0_EML_1, + GAUDI2_BMON_DCORE2_TPC0_EML_2, + GAUDI2_BMON_DCORE2_TPC0_EML_3, + } + }, + [TPC_ID_DCORE2_TPC1] = { + .funnel_id = GAUDI2_FUNNEL_DCORE2_TPC1_EML, + .etf_id = GAUDI2_ETF_DCORE2_TPC1_EML, + .stm_id = GAUDI2_STM_DCORE2_TPC1_EML, + .spmu_id = GAUDI2_SPMU_DCORE2_TPC1_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE2_TPC1_EML_0, + GAUDI2_BMON_DCORE2_TPC1_EML_1, + GAUDI2_BMON_DCORE2_TPC1_EML_2, + GAUDI2_BMON_DCORE2_TPC1_EML_3, + } + }, + [TPC_ID_DCORE2_TPC2] = { + .funnel_id = GAUDI2_FUNNEL_DCORE2_TPC2_EML, + .etf_id = GAUDI2_ETF_DCORE2_TPC2_EML, + .stm_id = GAUDI2_STM_DCORE2_TPC2_EML, + .spmu_id = GAUDI2_SPMU_DCORE2_TPC2_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE2_TPC2_EML_0, + GAUDI2_BMON_DCORE2_TPC2_EML_1, + GAUDI2_BMON_DCORE2_TPC2_EML_2, + GAUDI2_BMON_DCORE2_TPC2_EML_3, + } + }, + [TPC_ID_DCORE2_TPC3] = { + .funnel_id = GAUDI2_FUNNEL_DCORE2_TPC3_EML, + .etf_id = GAUDI2_ETF_DCORE2_TPC3_EML, + .stm_id = GAUDI2_STM_DCORE2_TPC3_EML, + .spmu_id = GAUDI2_SPMU_DCORE2_TPC3_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE2_TPC3_EML_0, + GAUDI2_BMON_DCORE2_TPC3_EML_1, + GAUDI2_BMON_DCORE2_TPC3_EML_2, + GAUDI2_BMON_DCORE2_TPC3_EML_3, + } + }, + [TPC_ID_DCORE2_TPC4] = { + .funnel_id = GAUDI2_FUNNEL_DCORE2_TPC4_EML, + .etf_id = GAUDI2_ETF_DCORE2_TPC4_EML, + .stm_id = GAUDI2_STM_DCORE2_TPC4_EML, + .spmu_id = GAUDI2_SPMU_DCORE2_TPC4_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE2_TPC4_EML_0, + GAUDI2_BMON_DCORE2_TPC4_EML_1, + GAUDI2_BMON_DCORE2_TPC4_EML_2, + GAUDI2_BMON_DCORE2_TPC4_EML_3, + } + }, + [TPC_ID_DCORE2_TPC5] = { + .funnel_id = GAUDI2_FUNNEL_DCORE2_TPC5_EML, + .etf_id = GAUDI2_ETF_DCORE2_TPC5_EML, + .stm_id = GAUDI2_STM_DCORE2_TPC5_EML, + .spmu_id = GAUDI2_SPMU_DCORE2_TPC5_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE2_TPC5_EML_0, + GAUDI2_BMON_DCORE2_TPC5_EML_1, + GAUDI2_BMON_DCORE2_TPC5_EML_2, + GAUDI2_BMON_DCORE2_TPC5_EML_3, + } + }, + [TPC_ID_DCORE3_TPC0] = { + .funnel_id = GAUDI2_FUNNEL_DCORE3_TPC0_EML, + .etf_id = GAUDI2_ETF_DCORE3_TPC0_EML, + .stm_id = GAUDI2_STM_DCORE3_TPC0_EML, + .spmu_id = GAUDI2_SPMU_DCORE3_TPC0_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE3_TPC0_EML_0, + GAUDI2_BMON_DCORE3_TPC0_EML_1, + GAUDI2_BMON_DCORE3_TPC0_EML_2, + GAUDI2_BMON_DCORE3_TPC0_EML_3, + } + }, + [TPC_ID_DCORE3_TPC1] = { + .funnel_id = GAUDI2_FUNNEL_DCORE3_TPC1_EML, + .etf_id = GAUDI2_ETF_DCORE3_TPC1_EML, + .stm_id = GAUDI2_STM_DCORE3_TPC1_EML, + .spmu_id = GAUDI2_SPMU_DCORE3_TPC1_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE3_TPC1_EML_0, + GAUDI2_BMON_DCORE3_TPC1_EML_1, + GAUDI2_BMON_DCORE3_TPC1_EML_2, + GAUDI2_BMON_DCORE3_TPC1_EML_3, + } + }, + [TPC_ID_DCORE3_TPC2] = { + .funnel_id = GAUDI2_FUNNEL_DCORE3_TPC2_EML, + .etf_id = GAUDI2_ETF_DCORE3_TPC2_EML, + .stm_id = GAUDI2_STM_DCORE3_TPC2_EML, + .spmu_id = GAUDI2_SPMU_DCORE3_TPC2_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE3_TPC2_EML_0, + GAUDI2_BMON_DCORE3_TPC2_EML_1, + GAUDI2_BMON_DCORE3_TPC2_EML_2, + GAUDI2_BMON_DCORE3_TPC2_EML_3, + } + }, + [TPC_ID_DCORE3_TPC3] = { + .funnel_id = GAUDI2_FUNNEL_DCORE3_TPC3_EML, + .etf_id = GAUDI2_ETF_DCORE3_TPC3_EML, + .stm_id = GAUDI2_STM_DCORE3_TPC3_EML, + .spmu_id = GAUDI2_SPMU_DCORE3_TPC3_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE3_TPC3_EML_0, + GAUDI2_BMON_DCORE3_TPC3_EML_1, + GAUDI2_BMON_DCORE3_TPC3_EML_2, + GAUDI2_BMON_DCORE3_TPC3_EML_3, + } + }, + [TPC_ID_DCORE3_TPC4] = { + .funnel_id = GAUDI2_FUNNEL_DCORE3_TPC4_EML, + .etf_id = GAUDI2_ETF_DCORE3_TPC4_EML, + .stm_id = GAUDI2_STM_DCORE3_TPC4_EML, + .spmu_id = GAUDI2_SPMU_DCORE3_TPC4_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE3_TPC4_EML_0, + GAUDI2_BMON_DCORE3_TPC4_EML_1, + GAUDI2_BMON_DCORE3_TPC4_EML_2, + GAUDI2_BMON_DCORE3_TPC4_EML_3, + } + }, + [TPC_ID_DCORE3_TPC5] = { + .funnel_id = GAUDI2_FUNNEL_DCORE3_TPC5_EML, + .etf_id = GAUDI2_ETF_DCORE3_TPC5_EML, + .stm_id = GAUDI2_STM_DCORE3_TPC5_EML, + .spmu_id = GAUDI2_SPMU_DCORE3_TPC5_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE3_TPC5_EML_0, + GAUDI2_BMON_DCORE3_TPC5_EML_1, + GAUDI2_BMON_DCORE3_TPC5_EML_2, + GAUDI2_BMON_DCORE3_TPC5_EML_3, + } + }, + [TPC_ID_DCORE0_TPC6] = { + .funnel_id = GAUDI2_FUNNEL_DCORE0_TPC6_EML, + .etf_id = GAUDI2_ETF_DCORE0_TPC6_EML, + .stm_id = GAUDI2_STM_DCORE0_TPC6_EML, + .spmu_id = GAUDI2_SPMU_DCORE0_TPC6_EML, + .bmon_count = 4, + .bmon_ids = { + GAUDI2_BMON_DCORE0_TPC6_EML_0, + GAUDI2_BMON_DCORE0_TPC6_EML_1, + GAUDI2_BMON_DCORE0_TPC6_EML_2, + GAUDI2_BMON_DCORE0_TPC6_EML_3, + } + } +}; + +static int gaudi2_coresight_timeout(struct hl_device *hdev, u64 addr, + int position, bool up) +{ + int rc; + u32 val, timeout_usec; + + if (hdev->pldm) + timeout_usec = GAUDI2_PLDM_CORESIGHT_TIMEOUT_USEC; + else + timeout_usec = CORESIGHT_TIMEOUT_USEC; + + rc = hl_poll_timeout( + hdev, + addr, + val, + up ? val & BIT(position) : !(val & BIT(position)), + 1000, + timeout_usec); + + if (rc) + dev_err(hdev->dev, + "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n", + addr, position, up); + + return rc; +} + +static int gaudi2_unlock_coresight_unit(struct hl_device *hdev, + const u64 base_reg) +{ + int rc = 0; + + WREG32(base_reg + mmCORESIGHT_UNLOCK_REGISTER_OFFSET, CORESIGHT_UNLOCK); + + rc = gaudi2_coresight_timeout(hdev, base_reg + mmCORESIGHT_UNLOCK_STATUS_REGISTER_OFFSET, + 1, 0); + + if (rc) + dev_err(hdev->dev, + "Failed to unlock register base addr: 0x%llx , position: 1, up: 0\n", + base_reg); + + return rc; +} + +static int gaudi2_config_stm(struct hl_device *hdev, struct hl_debug_params *params) +{ + struct hl_debug_params_stm *input; + u64 base_reg; + u32 frequency; + u32 read_reg; + int rc; + + if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) { + dev_err(hdev->dev, "Invalid register index in STM\n"); + return -EINVAL; + } + + base_reg = debug_stm_regs[params->reg_idx]; + + /* + * in case base reg is 0x0 we ignore this configuration + */ + if (!base_reg) + return 0; + + /* check if stub component on pldm + * we check offset 0xCFC STMDMAIDR in case + * return value is 0x0 - hence stub component + */ + read_reg = RREG32(base_reg + mmSTM_STMDMAIDR_OFFSET); + if (hdev->pldm && read_reg == 0x0) + return 0; + + rc = gaudi2_unlock_coresight_unit(hdev, base_reg); + if (rc) + return -EIO; + + if (params->enable) { + input = params->input; + + if (!input) + return -EINVAL; + + WREG32(base_reg + mmSTM_STMTCSR_OFFSET, 0x80004); + /* dummy read for pldm to flush outstanding writes */ + if (hdev->pldm) + RREG32(base_reg + mmSTM_STMTCSR_OFFSET); + + WREG32(base_reg + mmSTM_STMHEMCR_OFFSET, 7); + WREG32(base_reg + mmSTM_STMHEBSR_OFFSET, 0); + WREG32(base_reg + mmSTM_STMHEER_OFFSET, lower_32_bits(input->he_mask)); + WREG32(base_reg + mmSTM_STMHEBSR_OFFSET, 1); + WREG32(base_reg + mmSTM_STMHEER_OFFSET, upper_32_bits(input->he_mask)); + WREG32(base_reg + mmSTM_STMSPTRIGCSR_OFFSET, 0x10); + WREG32(base_reg + mmSTM_STMSPSCR_OFFSET, 0); + WREG32(base_reg + mmSTM_STMSPER_OFFSET, lower_32_bits(input->sp_mask)); + WREG32(base_reg + mmSTM_STMITATBID_OFFSET, input->id); + WREG32(base_reg + mmSTM_STMHEMASTR_OFFSET, 0x80); + frequency = hdev->asic_prop.psoc_timestamp_frequency; + if (frequency == 0) + frequency = input->frequency; + WREG32(base_reg + mmSTM_STMTSFREQR_OFFSET, frequency); + WREG32(base_reg + mmSTM_STMSYNCR_OFFSET, 0x7FF); + WREG32(base_reg + mmSTM_STMTCSR_OFFSET, 0x27 | (input->id << 16)); + } else { + WREG32(base_reg + mmSTM_STMTCSR_OFFSET, 4); + WREG32(base_reg + mmSTM_STMHEMCR_OFFSET, 0); + WREG32(base_reg + mmSTM_STMHEBSR_OFFSET, 1); + WREG32(base_reg + mmSTM_STMHEER_OFFSET, 0); + WREG32(base_reg + mmSTM_STMHETER_OFFSET, 0); + WREG32(base_reg + mmSTM_STMHEBSR_OFFSET, 0); + WREG32(base_reg + mmSTM_STMSPTER_OFFSET, 0); + WREG32(base_reg + mmSTM_STMSPER_OFFSET, 0); + WREG32(base_reg + mmSTM_STMHEMASTR_OFFSET, 0x80); + WREG32(base_reg + mmSTM_STMSPTRIGCSR_OFFSET, 0); + WREG32(base_reg + mmSTM_STMSPSCR_OFFSET, 0); + WREG32(base_reg + mmSTM_STMSPMSCR_OFFSET, 0); + WREG32(base_reg + mmSTM_STMTSFREQR_OFFSET, 0); + + rc = gaudi2_coresight_timeout(hdev, base_reg + mmSTM_STMTCSR_OFFSET, 23, false); + if (rc) { + dev_err(hdev->dev, "Failed to disable STM on timeout, error %d\n", rc); + return rc; + } + + WREG32(base_reg + mmSTM_STMTCSR_OFFSET, 4); + } + + return 0; +} + +static int gaudi2_config_etf(struct hl_device *hdev, struct hl_debug_params *params) +{ + struct hl_debug_params_etf *input; + u64 base_reg; + u32 read_reg; + u32 val; + int rc; + + if (params->reg_idx >= ARRAY_SIZE(debug_etf_regs)) { + dev_err(hdev->dev, "Invalid register index in ETF\n"); + return -EINVAL; + } + + base_reg = debug_etf_regs[params->reg_idx]; + + /* + * in case base reg is 0x0 we ignore this configuration + */ + if (!base_reg) + return 0; + + + /* in pldm we need to check if unit is not stub + * for doing do need to read ETF STS register and check + * it is not return 0x0 - in case it does + * it means that this is stub, we ignore this and return 0 + * means success + */ + read_reg = RREG32(base_reg + mmETF_STS_OFFSET); + if (hdev->pldm && read_reg == 0x0) + return 0; + + rc = gaudi2_unlock_coresight_unit(hdev, base_reg); + if (rc) + return -EIO; + + val = RREG32(base_reg + mmETF_FFCR_OFFSET); + val |= 0x1000; + WREG32(base_reg + mmETF_FFCR_OFFSET, val); + val |= 0x40; + WREG32(base_reg + mmETF_FFCR_OFFSET, val); + + rc = gaudi2_coresight_timeout(hdev, base_reg + mmETF_FFCR_OFFSET, 6, false); + if (rc) { + dev_err(hdev->dev, "Failed to %s ETF on timeout, error %d\n", + params->enable ? "enable" : "disable", rc); + return rc; + } + + rc = gaudi2_coresight_timeout(hdev, base_reg + mmETF_STS_OFFSET, 2, true); + if (rc) { + dev_err(hdev->dev, "Failed to %s ETF on timeout, error %d\n", + params->enable ? "enable" : "disable", rc); + return rc; + } + + WREG32(base_reg + mmETF_CTL_OFFSET, 0); + + if (params->enable) { + input = params->input; + + if (!input) + return -EINVAL; + + WREG32(base_reg + mmETF_BUFWM_OFFSET, 0x3FFC); + WREG32(base_reg + mmETF_MODE_OFFSET, input->sink_mode); + WREG32(base_reg + mmETF_FFCR_OFFSET, 0x4001); + WREG32(base_reg + mmETF_PSCR_OFFSET, 0x10); + WREG32(base_reg + mmETF_CTL_OFFSET, 1); + } else { + WREG32(base_reg + mmETF_BUFWM_OFFSET, 0); + WREG32(base_reg + mmETF_MODE_OFFSET, 0); + WREG32(base_reg + mmETF_FFCR_OFFSET, 0); + } + + return 0; +} + +static int gaudi2_etr_validate_address(struct hl_device *hdev, u64 addr, u64 size) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct gaudi2_device *gaudi2 = hdev->asic_specific; + + if (addr > (addr + size)) { + dev_err(hdev->dev, "ETR buffer size %llu overflow\n", size); + return false; + } + + if (gaudi2->hw_cap_initialized & HW_CAP_PMMU) { + if (hl_mem_area_inside_range(addr, size, + prop->pmmu.start_addr, + prop->pmmu.end_addr)) + return true; + + if (hl_mem_area_inside_range(addr, size, + prop->pmmu_huge.start_addr, + prop->pmmu_huge.end_addr)) + return true; + + if (hl_mem_area_inside_range(addr, size, + prop->dmmu.start_addr, + prop->dmmu.end_addr)) + return true; + } else { + if (hl_mem_area_inside_range(addr, size, + prop->dram_user_base_address, + prop->dram_end_address)) + return true; + } + + if (hl_mem_area_inside_range(addr, size, + prop->sram_user_base_address, + prop->sram_end_address)) + return true; + + if (!(gaudi2->hw_cap_initialized & HW_CAP_PMMU)) + dev_err(hdev->dev, "ETR buffer should be in SRAM/DRAM\n"); + + return false; +} + +static int gaudi2_config_etr(struct hl_device *hdev, struct hl_ctx *ctx, + struct hl_debug_params *params) +{ + struct hl_debug_params_etr *input; + u64 msb; + u32 val; + int rc; + + rc = gaudi2_unlock_coresight_unit(hdev, mmPSOC_ETR_BASE); + if (rc) + return -EIO; + + val = RREG32(mmPSOC_ETR_FFCR); + val |= 0x1000; + WREG32(mmPSOC_ETR_FFCR, val); + val |= 0x40; + WREG32(mmPSOC_ETR_FFCR, val); + + rc = gaudi2_coresight_timeout(hdev, mmPSOC_ETR_FFCR, 6, false); + if (rc) { + dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", + params->enable ? "enable" : "disable", rc); + return rc; + } + + rc = gaudi2_coresight_timeout(hdev, mmPSOC_ETR_STS, 2, true); + if (rc) { + dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", + params->enable ? "enable" : "disable", rc); + return rc; + } + + WREG32(mmPSOC_ETR_CTL, 0); + + if (params->enable) { + input = params->input; + + if (!input) + return -EINVAL; + + if (input->buffer_size == 0) { + dev_err(hdev->dev, "ETR buffer size should be bigger than 0\n"); + return -EINVAL; + } + + if (!gaudi2_etr_validate_address(hdev, input->buffer_address, input->buffer_size)) { + dev_err(hdev->dev, "ETR buffer address is invalid\n"); + return -EINVAL; + } + + RMWREG32(mmPSOC_GLOBAL_CONF_TRACE_AWUSER, ctx->asid, MMUBP_ASID_MASK); + RMWREG32(mmPSOC_GLOBAL_CONF_TRACE_ARUSER, ctx->asid, MMUBP_ASID_MASK); + + msb = upper_32_bits(input->buffer_address) >> 8; + WREG32(mmPSOC_GLOBAL_CONF_TRACE_ADDR, msb); + + WREG32(mmPSOC_ETR_BUFWM, 0x3FFC); + WREG32(mmPSOC_ETR_RSZ, input->buffer_size); + WREG32(mmPSOC_ETR_MODE, input->sink_mode); + /* write the protection bits only if security is disable */ + if (!(hdev->fw_components & FW_TYPE_BOOT_CPU)) { + /* make ETR not privileged */ + val = FIELD_PREP(PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK, 0); + /* make ETR non-secured (inverted logic) */ + val |= FIELD_PREP(PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK, 1); + /* burst size 16 */ + val |= FIELD_PREP(PSOC_ETR_AXICTL_WRBURSTLEN_MASK, 0xF); + WREG32(mmPSOC_ETR_AXICTL, val); + } + WREG32(mmPSOC_ETR_DBALO, lower_32_bits(input->buffer_address)); + WREG32(mmPSOC_ETR_DBAHI, upper_32_bits(input->buffer_address)); + WREG32(mmPSOC_ETR_FFCR, 3); + WREG32(mmPSOC_ETR_PSCR, 0x10); + WREG32(mmPSOC_ETR_CTL, 1); + } else { + WREG32(mmPSOC_ETR_BUFWM, 0); + WREG32(mmPSOC_ETR_RSZ, 0x400); + WREG32(mmPSOC_ETR_DBALO, 0); + WREG32(mmPSOC_ETR_DBAHI, 0); + WREG32(mmPSOC_ETR_PSCR, 0); + WREG32(mmPSOC_ETR_MODE, 0); + WREG32(mmPSOC_ETR_FFCR, 0); + + if (params->output_size >= sizeof(u64)) { + u32 rwp, rwphi; + + /* + * The trace buffer address is 64 bits wide. The end of + * the buffer is set in the RWP register (lower 32 + * bits), and in the RWPHI register (upper 8 bits). + * The 24 msb of the 64-bit address are stored in a + * global configuration register. + */ + rwp = RREG32(mmPSOC_ETR_RWP); + rwphi = RREG32(mmPSOC_ETR_RWPHI) & 0xff; + msb = RREG32(mmPSOC_GLOBAL_CONF_TRACE_ADDR); + *(u64 *) params->output = ((u64) msb << 40) | ((u64) rwphi << 32) | rwp; + } + } + + return 0; +} + +static int gaudi2_config_funnel(struct hl_device *hdev, struct hl_debug_params *params) +{ + u64 base_reg; + u32 val = params->enable ? 0xFFF : 0; + u32 read_reg; + int rc = 0; + + if (params->reg_idx >= ARRAY_SIZE(debug_funnel_regs)) { + dev_err(hdev->dev, "Invalid register index in FUNNEL\n"); + return -EINVAL; + } + + base_reg = debug_funnel_regs[params->reg_idx]; + + /* + * in case base reg is 0x0 we ignore this configuration + */ + if (!base_reg) + return 0; + + + /* in pldm we need to check if unit is not stub + * for doing so, need to read DEVID value. + * in case return 0x0 - it means that this is stub, + * we ignore this and return 0 - means success + */ + read_reg = RREG32(base_reg + mmFUNNEL_DEVID_OFFSET); + if (hdev->pldm && read_reg == 0x0) + return 0; + + rc = gaudi2_unlock_coresight_unit(hdev, base_reg); + if (rc) + return -EIO; + + WREG32(base_reg, val); + + return 0; +} + +static int gaudi2_config_bmon(struct hl_device *hdev, struct hl_debug_params *params) +{ + struct hl_debug_params_bmon *input; + u64 base_reg; + u32 read_reg; + + if (params->reg_idx >= ARRAY_SIZE(debug_bmon_regs)) { + dev_err(hdev->dev, "Invalid register index in BMON\n"); + return -EINVAL; + } + + base_reg = debug_bmon_regs[params->reg_idx]; + + /* + * in case base reg is 0x0 we ignore this configuration + */ + if (!base_reg) + return 0; + + + /* in pldm we need to check if unit is not stub + * for doing do need to read Control Register (offset 0x0) and check + * it is not return 0x0 - in case it does + * it means that this is stub, we ignore this and return 0 + * means success + */ + read_reg = RREG32(base_reg + mmBMON_CR_OFFSET); + if (hdev->pldm && read_reg == 0x0) + return 0; + + WREG32(base_reg + mmBMON_ATTREN_OFFSET, 1); + /* dummy read for pldm to flush outstanding writes */ + if (hdev->pldm) + RREG32(base_reg + mmBMON_ATTREN_OFFSET); + + /* Write Only Reset AXIMON */ + + WREG32(base_reg + mmBMON_RESET_OFFSET, 0x1); + + if (params->enable) { + input = params->input; + + if (!input) + return -EINVAL; + + WREG32(base_reg + mmBMON_ADDRL_S0_OFFSET, lower_32_bits(input->start_addr0)); + WREG32(base_reg + mmBMON_ADDRH_S0_OFFSET, upper_32_bits(input->start_addr0)); + WREG32(base_reg + mmBMON_ADDRL_E0_OFFSET, lower_32_bits(input->addr_mask0)); + WREG32(base_reg + mmBMON_ADDRH_E0_OFFSET, upper_32_bits(input->addr_mask0)); + WREG32(base_reg + mmBMON_ADDRL_S1_OFFSET, lower_32_bits(input->start_addr1)); + WREG32(base_reg + mmBMON_ADDRH_S1_OFFSET, upper_32_bits(input->start_addr1)); + WREG32(base_reg + mmBMON_ADDRL_E1_OFFSET, lower_32_bits(input->addr_mask1)); + WREG32(base_reg + mmBMON_ADDRH_E1_OFFSET, upper_32_bits(input->addr_mask1)); + WREG32(base_reg + mmBMON_ADDRL_S2_OFFSET, lower_32_bits(input->start_addr2)); + WREG32(base_reg + mmBMON_ADDRH_S2_OFFSET, upper_32_bits(input->start_addr2)); + WREG32(base_reg + mmBMON_ADDRL_E2_OFFSET, lower_32_bits(input->end_addr2)); + WREG32(base_reg + mmBMON_ADDRH_E2_OFFSET, upper_32_bits(input->end_addr2)); + WREG32(base_reg + mmBMON_ADDRL_S3_OFFSET, lower_32_bits(input->start_addr2)); + WREG32(base_reg + mmBMON_ADDRH_S3_OFFSET, upper_32_bits(input->start_addr2)); + WREG32(base_reg + mmBMON_ADDRL_E3_OFFSET, lower_32_bits(input->end_addr2)); + WREG32(base_reg + mmBMON_ADDRH_E3_OFFSET, upper_32_bits(input->end_addr2)); + + WREG32(base_reg + mmBMON_IDL_OFFSET, 0x0); + WREG32(base_reg + mmBMON_IDH_OFFSET, 0x0); + + WREG32(base_reg + mmBMON_ATTREN_OFFSET, 0); + WREG32(base_reg + mmBMON_BW_WIN_OFFSET, input->bw_win); + WREG32(base_reg + mmBMON_WIN_CAPTURE_OFFSET, input->win_capture); + WREG32(base_reg + mmBMON_REDUCTION_OFFSET, 0x1 | (13 << 8)); + WREG32(base_reg + mmBMON_STM_TRC_OFFSET, 0x7 | (input->id << 8)); + WREG32(base_reg + mmBMON_CR_OFFSET, input->control); + } else { + WREG32(base_reg + mmBMON_ADDRL_S0_OFFSET, 0); + WREG32(base_reg + mmBMON_ADDRH_S0_OFFSET, 0); + WREG32(base_reg + mmBMON_ADDRL_E0_OFFSET, 0); + WREG32(base_reg + mmBMON_ADDRH_E0_OFFSET, 0); + WREG32(base_reg + mmBMON_ADDRL_S1_OFFSET, 0); + WREG32(base_reg + mmBMON_ADDRH_S1_OFFSET, 0); + WREG32(base_reg + mmBMON_ADDRL_E1_OFFSET, 0); + WREG32(base_reg + mmBMON_ADDRH_E1_OFFSET, 0); + WREG32(base_reg + mmBMON_ADDRL_S2_OFFSET, 0); + WREG32(base_reg + mmBMON_ADDRH_S2_OFFSET, 0); + WREG32(base_reg + mmBMON_ADDRL_E2_OFFSET, 0); + WREG32(base_reg + mmBMON_ADDRH_E2_OFFSET, 0); + WREG32(base_reg + mmBMON_ADDRL_S3_OFFSET, 0); + WREG32(base_reg + mmBMON_ADDRH_S3_OFFSET, 0); + WREG32(base_reg + mmBMON_ADDRL_E3_OFFSET, 0); + WREG32(base_reg + mmBMON_ADDRH_E3_OFFSET, 0); + WREG32(base_reg + mmBMON_REDUCTION_OFFSET, 0); + WREG32(base_reg + mmBMON_STM_TRC_OFFSET, 0x7 | (0xA << 8)); + WREG32(base_reg + mmBMON_CR_OFFSET, 0x77 | 0xf << 24); + } + + return 0; +} + +static int gaudi2_config_spmu(struct hl_device *hdev, struct hl_debug_params *params) +{ + struct hl_debug_params_spmu *input = params->input; + u32 output_arr_len; + u32 cycle_cnt_idx; + u32 overflow_idx; + u32 events_num; + u32 event_mask; + u64 base_reg; + u32 read_reg; + u64 *output; + int i; + + if (params->reg_idx >= ARRAY_SIZE(debug_spmu_regs)) { + dev_err(hdev->dev, "Invalid register index in SPMU\n"); + return -EINVAL; + } + + base_reg = debug_spmu_regs[params->reg_idx]; + + /* + * in case base reg is 0x0 we ignore this configuration + */ + if (!base_reg) + return 0; + + /* in pldm we need to check if unit is not stub + * for doing do need to read PMTRC (at offset 0x200) + * address and check if return value is 0x0 - in case it does + * it means that this is stub, we ignore this and return 0 + * means success + */ + read_reg = RREG32(base_reg + mmSPMU_PMCR_EL0_OFFSET); + if (hdev->pldm && read_reg == 0x0) + return 0; + + if (params->enable) { + input = params->input; + + if (!input) + return -EINVAL; + + if (input->event_types_num > SPMU_MAX_COUNTERS) { + dev_err(hdev->dev, "too many event types values for SPMU enable\n"); + return -EINVAL; + } + + WREG32(base_reg + mmSPMU_PMCR_EL0_OFFSET, 0x41013046); + WREG32(base_reg + mmSPMU_PMCR_EL0_OFFSET, 0x41013040); + + /* dummy read for pldm to flush outstanding writes */ + if (hdev->pldm) + RREG32(base_reg); + + for (i = 0 ; i < input->event_types_num ; i++) + WREG32(base_reg + mmSPMU_PMEVTYPER0_EL0_OFFSET + i * 4, + input->event_types[i]); + + WREG32(base_reg + mmSPMU_PMTRC_OFFSET, input->pmtrc_val); + WREG32(base_reg + mmSPMU_TRC_CTRL_HOST_OFFSET, input->trc_ctrl_host_val); + WREG32(base_reg + mmSPMU_TRC_EN_HOST_OFFSET, input->trc_en_host_val); + + WREG32(base_reg + mmSPMU_PMCR_EL0_OFFSET, 0x41013041); + + /* + * set enabled events mask based on input->event_types_num + */ + event_mask = 0x80000000; + event_mask |= GENMASK(input->event_types_num, 0); + + WREG32(base_reg + mmSPMU_PMCNTENSET_EL0_OFFSET, event_mask); + } else { + output = params->output; + output_arr_len = params->output_size / 8; + events_num = output_arr_len - 2; + overflow_idx = output_arr_len - 2; + cycle_cnt_idx = output_arr_len - 1; + + WREG32(base_reg + mmSPMU_PMCR_EL0_OFFSET, 0x41013040); + + if (output && output_arr_len > 2) { + + if (events_num > SPMU_MAX_COUNTERS) { + dev_err(hdev->dev, "too many events values for SPMU disable\n"); + return -EINVAL; + } + + for (i = 0 ; i < events_num ; i++) { + const u64 performance_counter_offset = + base_reg + mmSPMU_PMEVCNTR0_EL0_OFFSET + (i * 8); + + output[i] = RREG32(performance_counter_offset); + } + + output[overflow_idx] = RREG32(base_reg + mmSPMU_PMOVSSET_EL0_OFFSET); + output[cycle_cnt_idx] = RREG32(base_reg + mmSPMU_PMCCNTR_H_EL0_OFFSET); + output[cycle_cnt_idx] <<= 32; + output[cycle_cnt_idx] |= RREG32(base_reg + mmSPMU_PMCCNTR_L_EL0_OFFSET); + } + + WREG32(base_reg + mmSPMU_PMOVSSET_EL0_OFFSET, 0); + + /* clean pmtrc to reset value */ + WREG32(base_reg + mmSPMU_PMTRC_OFFSET, 0x100400); + } + + return 0; +} + +int gaudi2_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data) +{ + struct hl_debug_params *params = data; + int rc = 0; + + switch (params->op) { + case HL_DEBUG_OP_STM: + rc = gaudi2_config_stm(hdev, params); + break; + case HL_DEBUG_OP_ETF: + rc = gaudi2_config_etf(hdev, params); + break; + case HL_DEBUG_OP_ETR: + rc = gaudi2_config_etr(hdev, ctx, params); + break; + case HL_DEBUG_OP_FUNNEL: + rc = gaudi2_config_funnel(hdev, params); + break; + case HL_DEBUG_OP_BMON: + rc = gaudi2_config_bmon(hdev, params); + break; + case HL_DEBUG_OP_SPMU: + rc = gaudi2_config_spmu(hdev, params); + break; + case HL_DEBUG_OP_TIMESTAMP: + /* Do nothing as this opcode is deprecated */ + break; + default: + dev_err(hdev->dev, "Unknown coresight id %d\n", params->op); + return -EINVAL; + } + + return rc; +} + +void gaudi2_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx) +{ + struct hl_debug_params params = {}; + int i, rc; + + /* in pldm attempting to access stubbed etfs can cause problems */ + if (!hdev->pldm) + for (i = GAUDI2_ETF_FIRST ; i <= GAUDI2_ETF_LAST ; i++) { + params.reg_idx = i; + rc = gaudi2_config_etf(hdev, ¶ms); + if (rc) + dev_err(hdev->dev, "halt ETF failed, %d/%d\n", rc, i); + } + + rc = gaudi2_config_etr(hdev, ctx, ¶ms); + if (rc) + dev_err(hdev->dev, "halt ETR failed, %d\n", rc); +} + + +static int gaudi2_coresight_set_disabled_components(struct hl_device *hdev, u32 unit_count, + u32 enabled_mask, + const struct component_config_offsets *binning_table) +{ + u32 component_idx = 0; + u32 disabled_mask; + u32 full_mask; + + /* in case no unit - no need to do work */ + if (!unit_count) + return 0; + + full_mask = GENMASK(unit_count - 1, 0); + + /* set the disable bits on disabled mask */ + disabled_mask = (~enabled_mask) & full_mask; + + while (disabled_mask) { + u32 component_mask = 1 << component_idx; + + if (component_idx >= unit_count) { + dev_err(hdev->dev, "index is out of range index(%u) >= units_count(%u)\n", + component_idx, unit_count); + return -EINVAL; + } + + /* + * in case mask is set, driver need to set to 0x0 + * all offsets for the following structures in the appropriate indices: + * debug_funnel_regs - offsets for all cs_dbg FUNNELs + * debug_etf_regs - offsets for all cs_dbg ETFs + * debug_stm_regs - offsets for all cs_dbg STMs + * debug_spmu_regs - offsets for all cs_dbg SPMUs + * debug_bmon_regs - offsets for all cs_dbg BMONs + * when value is set to COMPONENT_ID_INVALID - + * it means there is no such register for current component. + */ + + if (disabled_mask & component_mask) { + u32 bmon_idx; + const struct component_config_offsets *binned_component = + &(binning_table[component_idx]); + + if (binned_component->funnel_id != COMPONENT_ID_INVALID) + debug_funnel_regs[binned_component->funnel_id] = 0x0; + + if (binned_component->etf_id != COMPONENT_ID_INVALID) + debug_etf_regs[binned_component->etf_id] = 0x0; + + if (binned_component->stm_id != COMPONENT_ID_INVALID) + debug_stm_regs[binned_component->stm_id] = 0x0; + + if (binned_component->spmu_id != COMPONENT_ID_INVALID) + debug_spmu_regs[binned_component->spmu_id] = 0x0; + + for (bmon_idx = 0; bmon_idx < binned_component->bmon_count; bmon_idx++) + debug_bmon_regs[binned_component->bmon_ids[bmon_idx]] = 0x0; + + /* + * reset enabled bit + */ + disabled_mask &= ~component_mask; + } + + component_idx++; + } + + return 0; +} + +int gaudi2_coresight_init(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + int ret; + + /* + * Mask out all the disabled binned offsets. + * so when user request to configure a binned or masked out component, + * driver will ignore programing it ( happens when offset value is set to 0x0 ) + * this is being set in gaudi2_coresight_set_disabled_components + */ + + /* Set TPC disable components */ + ret = gaudi2_coresight_set_disabled_components(hdev, TPC_ID_SIZE, prop->tpc_enabled_mask, + tpc_binning_cfg_table); + if (ret) { + dev_err(hdev->dev, "Failed to set disabled cs_dbg units for tpc coresight\n"); + return ret; + } + + /* Set decoder disable components */ + ret = gaudi2_coresight_set_disabled_components(hdev, DEC_ID_SIZE, + prop->decoder_enabled_mask, decoder_binning_cfg_table); + if (ret) { + dev_err(hdev->dev, "Failed to set disabled cs_dbg units for decoder coresight\n"); + return ret; + } + + /* Set HBM (MC0 and MC1) disable components */ + ret = gaudi2_coresight_set_disabled_components(hdev, HBM_ID_SIZE, prop->dram_enabled_mask, + hbm_mc0_binning_cfg_table); + if (ret) { + dev_err(hdev->dev, "Failed to set disabled cs_dbg units for hbm mc0 coresight\n"); + return ret; + } + + ret = gaudi2_coresight_set_disabled_components(hdev, HBM_ID_SIZE, prop->dram_enabled_mask, + hbm_mc1_binning_cfg_table); + if (ret) { + dev_err(hdev->dev, "Failed to set disabled cs_dbg units for hbm mc1 coresight\n"); + return ret; + } + + /* Set HIF_HMMU disable components */ + ret = gaudi2_coresight_set_disabled_components(hdev, HMMU_ID_SIZE, + prop->hmmu_hif_enabled_mask, hmmu_binning_cfg_table); + if (ret) { + dev_err(hdev->dev, "Failed to set disabled cs_dbg units for hmmu coresight\n"); + return ret; + } + + /* Set XBAR_EDGE disable components */ + ret = gaudi2_coresight_set_disabled_components(hdev, XBAR_EDGE_ID_SIZE, + prop->xbar_edge_enabled_mask, xbar_edge_binning_cfg_table); + if (ret) { + dev_err(hdev->dev, "Failed to set disabled cs_dbg units for xbar_edge coresight\n"); + return ret; + } + + /* Set EDMA disable components */ + ret = gaudi2_coresight_set_disabled_components(hdev, EDMA_ID_SIZE, prop->edma_enabled_mask, + edma_binning_cfg_table); + if (ret) { + dev_err(hdev->dev, "Failed to set disabled cs_dbg units for edma coresight\n"); + return ret; + } + + return 0; +} diff --git a/drivers/misc/habanalabs/gaudi2/gaudi2_coresight_regs.h b/drivers/misc/habanalabs/gaudi2/gaudi2_coresight_regs.h new file mode 100644 index 000000000000..df8729286e06 --- /dev/null +++ b/drivers/misc/habanalabs/gaudi2/gaudi2_coresight_regs.h @@ -0,0 +1,1063 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ +#ifndef GAUDI2_CORESIGHT_REGS_DRV_H_ +#define GAUDI2_CORESIGHT_REGS_DRV_H_ + +#include "gaudi2_masks.h" +#include "../include/gaudi2/gaudi2_coresight.h" +#include "gaudi2P.h" + +/* FUNNEL Offsets - same offsets for all funnels*/ +#define mmFUNNEL_CTRL_REG_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_CTRL_REG - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_PRIORITY_CTRL_REG_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_PRIORITY_CTRL_REG - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_ITATBDATA0_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_ITATBDATA0 - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_ITATBCTR2_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR2 - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_ITATBCTR1_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR1 - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_ITATBCTR0_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR0 - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_ITCTRL_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_ITCTRL - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_CLAIMSET_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_CLAIMSET - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_CLAIMCLR_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_CLAIMCLR - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_LOCKACCESS_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_LOCKACCESS - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_LOCKSTATUS_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_LOCKSTATUS - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_AUTHSTATUS_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_AUTHSTATUS - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_DEVID_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_DEVID - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_DEVTYPE_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_DEVTYPE - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_PIDR4_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_PIDR4 - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_PERIPHID5_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_PERIPHID5 - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_PERIPHID6_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_PERIPHID6 - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_PERIPHID7_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_PERIPHID7 - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_PIDR0_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_PIDR0 - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_PIDR1_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_PIDR1 - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_PIDR2_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_PIDR2 - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_PIDR3_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_PIDR3 - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_CID0_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_CID0 - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_CID1_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_CID1 - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_CID2_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_CID2 - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +#define mmFUNNEL_CID3_OFFSET \ + (mmDCORE0_TPC0_EML_FUNNEL_CID3 - \ + mmDCORE0_TPC0_EML_FUNNEL_BASE) + +/* ETF Offsets - same offsets for all etfs */ +#define mmETF_RSZ_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_RSZ - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_STS_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_STS - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_RRD_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_RRD - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_RRP_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_RRP - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_RWP_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_RWP - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_TRG_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_TRG - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_CTL_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_CTL - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_RWD_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_RWD - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_MODE_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_MODE - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_LBUFLEVEL_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_LBUFLEVEL - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_CBUFLEVEL_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_CBUFLEVEL - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_BUFWM_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_BUFWM - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_FFSR_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_FFSR - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_FFCR_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_FFCR - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_PSCR_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_PSCR - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_ITATBMDATA0_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_ITATBMDATA0 - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_ITATBMCTR2_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_ITATBMCTR2 - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_ITATBMCTR1_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_ITATBMCTR1 - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_ITATBMCTR0_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_ITATBMCTR0 - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_ITMISCOP0_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_ITMISCOP0 - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_ITTRFLIN_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_ITTRFLIN - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_ITATBDATA0_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_ITATBDATA0 - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_ITATBCTR2_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_ITATBCTR2 - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_ITATBCTR1_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_ITATBCTR1 - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_ITATBCTR0_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_ITATBCTR0 - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_ITCTRL_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_ITCTRL - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_CLAIMSET_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_CLAIMSET - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_CLAIMCLR_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_CLAIMCLR - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_LAR_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_LAR - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_LSR_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_LSR - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_AUTHSTATUS_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_AUTHSTATUS - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_DEVID_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_DEVID - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_DEVTYPE_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_DEVTYPE - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_PERIPHID4_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_PERIPHID4 - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_PERIPHID5_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_PERIPHID5 - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_PERIPHID6_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_PERIPHID6 - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_PERIPHID7_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_PERIPHID7 - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_PERIPHID0_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_PERIPHID0 - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_PERIPHID1_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_PERIPHID1 - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_PERIPHID2_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_PERIPHID2 - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_PERIPHID3_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_PERIPHID3 - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_COMPID0_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_COMPID0 - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_COMPID1_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_COMPID1 - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_COMPID2_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_COMPID2 - \ + mmDCORE0_TPC0_EML_ETF_BASE) + +#define mmETF_COMPID3_OFFSET \ + (mmDCORE0_TPC0_EML_ETF_COMPID3 - \ + mmDCORE0_TPC0_EML_ETF_BASE) + + +/* STM OFFSETS - same offsets for all stms */ +#define mmSTM_STMDMASTARTR_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMDMASTARTR - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMDMASTOPR_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMDMASTOPR - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMDMASTATR_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMDMASTATR - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMDMACTLR_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMDMACTLR - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMDMAIDR_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMDMAIDR - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMHEER_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMHEER - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMHETER_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMHETER - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMHEBSR_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMHEBSR - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMHEMCR_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMHEMCR - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMHEEXTMUXR_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMHEEXTMUXR - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMHEMASTR_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMHEMASTR - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMHEFEAT1R_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMHEFEAT1R - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMHEIDR_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMHEIDR - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMSPER_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMSPER - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMSPTER_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMSPTER - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMSPSCR_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMSPSCR - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMSPMSCR_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMSPMSCR - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMSPOVERRIDER_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMSPOVERRIDER - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMSPMOVERRIDER_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMSPMOVERRIDER - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMSPTRIGCSR_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMSPTRIGCSR - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMTCSR_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMTCSR - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMTSSTIMR_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMTSSTIMR - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMTSFREQR_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMTSFREQR - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMSYNCR_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMSYNCR - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMAUXCR_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMAUXCR - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMFEAT1R_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMFEAT1R - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMFEAT2R_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMFEAT2R - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMFEAT3R_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMFEAT3R - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMITTRIGGER_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMITTRIGGER - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMITATBDATA0_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMITATBDATA0 - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMITATBCTR2_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMITATBCTR2 - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMITATBID_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMITATBID - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMITATBCTR0_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMITATBCTR0 - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMITCTRL_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMITCTRL - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMCLAIMSET_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMCLAIMSET - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMCLAIMCLR_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMCLAIMCLR - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMLAR_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMLAR - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMLSR_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMLSR - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMAUTHSTATUS_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMAUTHSTATUS - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMDEVARCH_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMDEVARCH - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMDEVID_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMDEVID - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMDEVTYPE_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMDEVTYPE - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMPIDR4_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMPIDR4 - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMPIDR5_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMPIDR5 - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMPIDR6_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMPIDR6 - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMPIDR7_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMPIDR7 - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMPIDR0_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMPIDR0 - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMPIDR1_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMPIDR1 - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMPIDR2_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMPIDR2 - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMPIDR3_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMPIDR3 - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMCIDR0_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMCIDR0 - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMCIDR1_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMCIDR1 - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMCIDR2_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMCIDR2 - \ + mmDCORE0_TPC0_EML_STM_BASE) + +#define mmSTM_STMCIDR3_OFFSET \ + (mmDCORE0_TPC0_EML_STM_STMCIDR3 - \ + mmDCORE0_TPC0_EML_STM_BASE) + + +/* SPMU OFFSETS - same offsets for all SPMUs */ +#define mmSPMU_PMEVCNTR0_EL0_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMEVCNTR0_EL0 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMEVCNTR1_EL0_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMEVCNTR1_EL0 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMEVCNTR2_EL0_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMEVCNTR2_EL0 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMEVCNTR3_EL0_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMEVCNTR3_EL0 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMEVCNTR4_EL0_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMEVCNTR4_EL0 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMEVCNTR5_EL0_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMEVCNTR5_EL0 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMCCNTR_L_EL0_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMCCNTR_L_EL0 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMCCNTR_H_EL0_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMCCNTR_H_EL0 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMTRC_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMTRC - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_TRC_CTRL_HOST_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_TRC_CTRL_HOST - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_TRC_STAT_HOST_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_TRC_STAT_HOST - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_TRC_EN_HOST_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_TRC_EN_HOST - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMEVTYPER0_EL0_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMEVTYPER0_EL0 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMEVTYPER1_EL0_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMEVTYPER1_EL0 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMEVTYPER2_EL0_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMEVTYPER2_EL0 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMEVTYPER3_EL0_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMEVTYPER3_EL0 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMEVTYPER4_EL0_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMEVTYPER4_EL0 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMEVTYPER5_EL0_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMEVTYPER5_EL0 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMSSR_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMSSR - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMOVSSR_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMOVSSR - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMCCNTSR_L_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_L - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMCCNTSR_H_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_H - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMEVCNTSR0_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR0 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMEVCNTSR1_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR1 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMEVCNTSR2_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR2 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMEVCNTSR3_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR3 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMEVCNTSR4_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR4 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMEVCNTSR5_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR5 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMSCR_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMSCR - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMSRR_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMSRR - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMCNTENSET_EL0_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMCNTENSET_EL0 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMCNTENCLR_EL0_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMCNTENCLR_EL0 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMINTENSET_EL1_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMINTENSET_EL1 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMINTENCLR_EL1_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMINTENCLR_EL1 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMOVSCLR_EL0_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMOVSCLR_EL0 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMSWINC_EL0_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMSWINC_EL0 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMOVSSET_EL0_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMOVSSET_EL0 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMCFGR_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMCFGR - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMCR_EL0_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMCR_EL0 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMITCTRL_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMITCTRL - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMCLAIMSET_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMCLAIMSET - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMCLAIMCLR_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMCLAIMCLR - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMDEVAFF0_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMDEVAFF0 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMDEVAFF1_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMDEVAFF1 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMLAR_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMLAR - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMLSR_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMLSR - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMAUTHSTATUS_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMAUTHSTATUS - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMDEVARCH_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMDEVARCH - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMDEVID2_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMDEVID2 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMDEVID1_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMDEVID1 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMDEVID_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMDEVID - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMDEVTYPE_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMDEVTYPE - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMPIDR4_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMPIDR4 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMPIDR5_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMPIDR5 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMPIDR6_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMPIDR6 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMPIDR7_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMPIDR7 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMPIDR0_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMPIDR0 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMPIDR1_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMPIDR1 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMPIDR2_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMPIDR2 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMPIDR3_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMPIDR3 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMCIDR0_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMCIDR0 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMCIDR1_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMCIDR1 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMCIDR2_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMCIDR2 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + +#define mmSPMU_PMCIDR3_OFFSET \ + (mmDCORE0_TPC0_EML_SPMU_PMCIDR3 - \ + mmDCORE0_TPC0_EML_SPMU_BASE) + + +/* BMON OFFSETS - same offsets for all BMONs*/ +#define mmBMON_CR_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_CR - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_RESET_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_REG_RESET - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_INT_CLR_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_INT_CLR - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_TRIG_TH_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_TRIG_TH - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_ADDRL_S0_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S0 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_ADDRH_S0_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S0 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_ADDRL_E0_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E0 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_ADDRH_E0_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E0 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_ADDRL_S1_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S1 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_ADDRH_S1_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S1 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_ADDRL_E1_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E1 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_ADDRH_E1_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E1 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_ADDRL_S2_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S2 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_ADDRH_S2_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S2 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_ADDRL_E2_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E2 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_ADDRH_E2_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E2 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_ADDRL_S3_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S3 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_ADDRH_S3_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S3 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_ADDRL_E3_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E3 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_ADDRH_E3_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E3 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_REDUCTION_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_REDUCTION - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_IDL_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_IDL - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_IDH_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_IDH - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_IDENL_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_IDENL - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_IDENH_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_IDENH - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_LATENCY_SMP_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_LATENCY_SMP - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_ATTR_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_ATTR - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_ATTREN_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_ATTREN - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_USRENL_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_USRENL - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_USRL_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_USRL - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_USRENH_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_USRENH - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_USRH_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_USRH - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_CAPTURE_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_CAPTURE - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_RELEASE_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_RELEASE - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_WIN_CAPTURE_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_WIN_CAPTURE - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_BW_WIN_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_BW_WIN - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_MATCH_CNT_SOD_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_MATCH_CNT_SOD - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_MATCH_CNT_WIN_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_MATCH_CNT_WIN - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_CYCCNT_L_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_CYCCNT_L - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_CYCCNT_H_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_CYCCNT_H - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_MAXLAT_SOD_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_MAXLAT_SOD - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_MINLAT_SOD_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_MINLAT_SOD - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_MAXBW_SOD_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_MAXBW_SOD - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_MINBW_SOD_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_MINBW_SOD - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_MAXOS_SOD_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_MAXOS_SOD - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_MINOS_SOD_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_MINOS_SOD - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_ADDRL_SNAPSHOT_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_SNAPSHOT - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_ADDRH_SNAPSHOT_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_SNAPSHOT - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_IDL_SNAPSHOT_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_IDL_SNAPSHOT - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_IDH_SNAPSHOT_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_IDH_SNAPSHOT - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_ATTR_SNAPSHOT_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_ATTR_SNAPSHOT - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_STM_TRC_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_STM_TRC - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_STM_TRC_DROP_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_STM_TRC_DROP - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_DEVARCH_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_DEVARCH - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_PMDEVID2_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID2 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_PMDEVID1_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID1 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_PMDEVID_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_DEVTYPE_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_DEVTYPE - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_PIDR4_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_PIDR4 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_PIDR5_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_PIDR5 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_PIDR6_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_PIDR6 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_PIDR7_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_PIDR7 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_PIDR0_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_PIDR0 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_PIDR1_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_PIDR1 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_PIDR2_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_PIDR2 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_PIDR3_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_PIDR3 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_CIDR0_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_CIDR0 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_CIDR1_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_CIDR1 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_CIDR2_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_CIDR2 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + +#define mmBMON_CIDR3_OFFSET \ + (mmDCORE0_TPC0_EML_BUSMON_0_CIDR3 - \ + mmDCORE0_TPC0_EML_BUSMON_0_BASE) + + +/* Coresight unlock offset */ +#define mmCORESIGHT_UNLOCK_REGISTER_OFFSET mmSTM_STMLAR_OFFSET +#define mmCORESIGHT_UNLOCK_STATUS_REGISTER_OFFSET mmSTM_STMLSR_OFFSET + +#endif /* GAUDI2_CORESIGHT_REGS_DRV_H_ */ diff --git a/drivers/misc/habanalabs/gaudi2/gaudi2_masks.h b/drivers/misc/habanalabs/gaudi2/gaudi2_masks.h new file mode 100644 index 000000000000..eed16d642a5a --- /dev/null +++ b/drivers/misc/habanalabs/gaudi2/gaudi2_masks.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2020-2022 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI2_MASKS_H_ +#define GAUDI2_MASKS_H_ + +#include "../include/gaudi2/asic_reg/gaudi2_regs.h" + +/* Useful masks for bits in various registers */ +#define QMAN_GLBL_ERR_CFG_MSG_EN_MASK \ + ((0xF << PDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ + (0x1F << PDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ + (0x1F << PDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT)) + +#define QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK \ + ((0xF << PDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ + (0x1F << PDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ + (0x1F << PDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \ + (0x1 << PDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT)) + +#define QMAN_GLBL_ERR_CFG1_MSG_EN_MASK \ + (0x1 << PDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_SHIFT) + +#define QMAN_GLBL_ERR_CFG1_STOP_ON_ERR_EN_MASK \ + ((0x1 << PDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_SHIFT) | \ + (0x1 << PDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_SHIFT)) + +#define QM_PQC_LBW_WDATA \ + ((1 << DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_SHIFT) | \ + (1 << DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_SHIFT)) + +#define QMAN_MAKE_TRUSTED \ + ((0xF << PDMA0_QM_GLBL_PROT_PQF_SHIFT) | \ + (0x1 << PDMA0_QM_GLBL_PROT_ERR_SHIFT) | \ + (0x1 << PDMA0_QM_GLBL_PROT_PQC_SHIFT)) + +#define QMAN_MAKE_TRUSTED_TEST_MODE \ + ((0xF << PDMA0_QM_GLBL_PROT_PQF_SHIFT) | \ + (0xF << PDMA0_QM_GLBL_PROT_CQF_SHIFT) | \ + (0xF << PDMA0_QM_GLBL_PROT_CP_SHIFT) | \ + (0x1 << PDMA0_QM_GLBL_PROT_ERR_SHIFT) | \ + (0x1 << PDMA0_QM_GLBL_PROT_PQC_SHIFT)) + +#define QMAN_ENABLE \ + ((0xF << PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ + (0x1F << PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ + (0x1F << PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT) | \ + (0x1 << PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT)) + +#define PDMA1_QMAN_ENABLE \ + ((0x3 << PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ + (0x1F << PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ + (0x1F << PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT) | \ + (0x1 << PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT)) + +/* QM_IDLE_MASK is valid for all engines QM idle check */ +#define QM_IDLE_MASK (DCORE0_EDMA0_QM_GLBL_STS0_PQF_IDLE_MASK | \ + DCORE0_EDMA0_QM_GLBL_STS0_CQF_IDLE_MASK | \ + DCORE0_EDMA0_QM_GLBL_STS0_CP_IDLE_MASK) + +#define QM_ARC_IDLE_MASK DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_MASK + +#define MME_ARCH_IDLE_MASK \ + (DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_MASK | \ + DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_MASK | \ + DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_MASK | \ + DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_MASK | \ + DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_IDLE_MASK | \ + DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_RDY_MASK) + +#define TPC_IDLE_MASK (DCORE0_TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK | \ + DCORE0_TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK | \ + DCORE0_TPC0_CFG_STATUS_IQ_EMPTY_MASK | \ + DCORE0_TPC0_CFG_STATUS_SB_EMPTY_MASK | \ + DCORE0_TPC0_CFG_STATUS_QM_IDLE_MASK | \ + DCORE0_TPC0_CFG_STATUS_QM_RDY_MASK) + +#define DCORE0_TPC0_QM_CGM_STS_AGENT_IDLE_MASK 0x100 + +/* CGM_IDLE_MASK is valid for all engines CGM idle check */ +#define CGM_IDLE_MASK DCORE0_TPC0_QM_CGM_STS_AGENT_IDLE_MASK + +#define QM_GLBL_CFG1_PQF_STOP PDMA0_QM_GLBL_CFG1_PQF_STOP_MASK +#define QM_GLBL_CFG1_CQF_STOP PDMA0_QM_GLBL_CFG1_CQF_STOP_MASK +#define QM_GLBL_CFG1_CP_STOP PDMA0_QM_GLBL_CFG1_CP_STOP_MASK +#define QM_GLBL_CFG1_PQF_FLUSH PDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK +#define QM_GLBL_CFG1_CQF_FLUSH PDMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK +#define QM_GLBL_CFG1_CP_FLUSH PDMA0_QM_GLBL_CFG1_CP_FLUSH_MASK + +#define QM_GLBL_CFG2_ARC_CQF_STOP PDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_MASK +#define QM_GLBL_CFG2_ARC_CQF_FLUSH PDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_MASK + +#define QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1 +#define QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2 +#define QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 + +#define QM_ARB_ERR_MSG_EN_MASK (\ + QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK |\ + QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK |\ + QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK) + +#define PCIE_AUX_FLR_CTRL_HW_CTRL_MASK 0x1 +#define PCIE_AUX_FLR_CTRL_INT_MASK_MASK 0x2 + +#define MME_ACC_INTR_MASK_WBC_ERR_RESP_MASK GENMASK(1, 0) +#define MME_ACC_INTR_MASK_AP_SRC_POS_INF_MASK BIT(2) +#define MME_ACC_INTR_MASK_AP_SRC_NEG_INF_MASK BIT(3) +#define MME_ACC_INTR_MASK_AP_SRC_NAN_MASK BIT(4) +#define MME_ACC_INTR_MASK_AP_RESULT_POS_INF_MASK BIT(5) +#define MME_ACC_INTR_MASK_AP_RESULT_NEG_INF_MASK BIT(6) + +#define SM_CQ_L2H_MASK_VAL 0xFFFFFFFFFC000000ull +#define SM_CQ_L2H_CMPR_VAL 0x1000007FFC000000ull +#define SM_CQ_L2H_LOW_MASK GENMASK(31, 20) +#define SM_CQ_L2H_LOW_SHIFT 20 + +#define MMU_STATIC_MULTI_PAGE_SIZE_HOP4_PAGE_SIZE_MASK \ + REG_FIELD_MASK(DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE, HOP4_PAGE_SIZE) +#define STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_MASK \ + REG_FIELD_MASK(DCORE0_HMMU0_STLB_HOP_CONFIGURATION, ONLY_LARGE_PAGE) + +#define AXUSER_HB_SEC_ASID_MASK 0x3FF +#define AXUSER_HB_SEC_MMBP_MASK 0x400 + +#define MMUBP_ASID_MASK (AXUSER_HB_SEC_ASID_MASK | AXUSER_HB_SEC_MMBP_MASK) + +#define ROT_MSS_HALT_WBC_MASK BIT(0) +#define ROT_MSS_HALT_RSB_MASK BIT(1) +#define ROT_MSS_HALT_MRSB_MASK BIT(2) + +#define PCIE_DBI_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_SHIFT 0 +#define PCIE_DBI_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_MASK 0x1 + +#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_SIGN_SHIFT 15 +#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_SIGN_MASK 0x8000 + +#endif /* GAUDI2_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/gaudi2/gaudi2_security.c b/drivers/misc/habanalabs/gaudi2/gaudi2_security.c new file mode 100644 index 000000000000..89a06ff5ba34 --- /dev/null +++ b/drivers/misc/habanalabs/gaudi2/gaudi2_security.c @@ -0,0 +1,3849 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2020-2022 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "gaudi2P.h" +#include "../include/gaudi2/asic_reg/gaudi2_regs.h" + +#define UNSET_GLBL_SEC_BIT(array, b) ((array)[((b) / 32)] |= (1 << ((b) % 32))) + +#define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_MASK +#define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD_MASK +#define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR_MASK +#define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR_MASK +#define SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR_MASK +#define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD \ + PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD_MASK +#define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR \ + PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR_MASK +#define SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR \ + PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR_MASK + +/* LBW RR */ +#define SFT_NUM_OF_LBW_RTR 1 +#define SFT_LBW_RTR_OFFSET 0 +#define RR_LBW_LONG_MASK 0x7FFFFFFull +#define RR_LBW_SHORT_MASK 0x7FFF000ull + +/* HBW RR */ +#define SFT_NUM_OF_HBW_RTR 2 +#define RR_HBW_SHORT_LO_MASK 0xFFFFFFFF000ull +#define RR_HBW_SHORT_HI_MASK 0xF00000000000ull +#define RR_HBW_LONG_LO_MASK 0xFFFFFFFF000ull +#define RR_HBW_LONG_HI_MASK 0xFFFFF00000000000ull + +struct rr_config { + u64 min; + u64 max; + u32 index; + u8 type; +}; + +struct gaudi2_atypical_bp_blocks { + u32 mm_block_base_addr; + u32 block_size; + u32 glbl_sec_offset; + u32 glbl_sec_length; +}; + +static const struct gaudi2_atypical_bp_blocks gaudi2_pb_dcr0_sm_objs = { + mmDCORE0_SYNC_MNGR_OBJS_BASE, + 128 * 1024, + SM_OBJS_PROT_BITS_OFFS, + 640 +}; + +static const u32 gaudi2_pb_sft0[] = { + mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE, + mmSFT0_HBW_RTR_IF0_RTR_H3_BASE, + mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE, + mmSFT0_HBW_RTR_IF0_ADDR_DEC_HBW_BASE, + mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE, + mmSFT0_HBW_RTR_IF1_RTR_H3_BASE, + mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE, + mmSFT0_HBW_RTR_IF1_ADDR_DEC_HBW_BASE, + mmSFT0_LBW_RTR_IF_RTR_CTRL_BASE, + mmSFT0_LBW_RTR_IF_RTR_H3_BASE, + mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE, + mmSFT0_LBW_RTR_IF_ADDR_DEC_HBW_BASE, + mmSFT0_BASE, +}; + +static const u32 gaudi2_pb_dcr0_hif[] = { + mmDCORE0_HIF0_BASE, +}; + +static const u32 gaudi2_pb_dcr0_rtr0[] = { + mmDCORE0_RTR0_CTRL_BASE, + mmDCORE0_RTR0_H3_BASE, + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE, + mmDCORE0_RTR0_ADD_DEC_HBW_BASE, + mmDCORE0_RTR0_BASE, + mmDCORE0_RTR0_DBG_ADDR_BASE, +}; + +static const u32 gaudi2_pb_dcr0_hmmu0[] = { + mmDCORE0_HMMU0_MMU_BASE, + mmDCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE, + mmDCORE0_HMMU0_SCRAMB_OUT_BASE, + mmDCORE0_HMMU0_STLB_BASE, +}; + +static const u32 gaudi2_pb_cpu_if[] = { + mmCPU_IF_BASE, +}; + +static const u32 gaudi2_pb_cpu[] = { + mmCPU_CA53_CFG_BASE, + mmCPU_MSTR_IF_RR_SHRD_HBW_BASE, +}; + +static const u32 gaudi2_pb_kdma[] = { + mmARC_FARM_KDMA_BASE, + mmARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_BASE, +}; + +static const u32 gaudi2_pb_pdma0[] = { + mmPDMA0_CORE_BASE, + mmPDMA0_MSTR_IF_RR_SHRD_HBW_BASE, + mmPDMA0_QM_BASE, +}; + +static const u32 gaudi2_pb_pdma0_arc[] = { + mmPDMA0_QM_ARC_AUX_BASE, +}; + +static const struct range gaudi2_pb_pdma0_arc_unsecured_regs[] = { + {mmPDMA0_QM_ARC_AUX_RUN_HALT_REQ, mmPDMA0_QM_ARC_AUX_RUN_HALT_ACK}, + {mmPDMA0_QM_ARC_AUX_CLUSTER_NUM, mmPDMA0_QM_ARC_AUX_WAKE_UP_EVENT}, + {mmPDMA0_QM_ARC_AUX_ARC_RST_REQ, mmPDMA0_QM_ARC_AUX_CID_OFFSET_7}, + {mmPDMA0_QM_ARC_AUX_SCRATCHPAD_0, mmPDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT}, + {mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN}, + {mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN}, + {mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG}, + {mmPDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, mmPDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI}, + {mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmPDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN}, +}; + +static const u32 gaudi2_pb_pdma0_unsecured_regs[] = { + mmPDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION, + mmPDMA0_CORE_CTX_WR_COMP_ADDR_HI, + mmPDMA0_CORE_CTX_WR_COMP_ADDR_LO, + mmPDMA0_CORE_CTX_WR_COMP_WDATA, + mmPDMA0_CORE_CTX_SRC_BASE_LO, + mmPDMA0_CORE_CTX_SRC_BASE_HI, + mmPDMA0_CORE_CTX_DST_BASE_LO, + mmPDMA0_CORE_CTX_DST_BASE_HI, + mmPDMA0_CORE_CTX_SRC_TSIZE_0, + mmPDMA0_CORE_CTX_SRC_TSIZE_1, + mmPDMA0_CORE_CTX_SRC_TSIZE_2, + mmPDMA0_CORE_CTX_SRC_TSIZE_3, + mmPDMA0_CORE_CTX_SRC_TSIZE_4, + mmPDMA0_CORE_CTX_SRC_STRIDE_1, + mmPDMA0_CORE_CTX_SRC_STRIDE_2, + mmPDMA0_CORE_CTX_SRC_STRIDE_3, + mmPDMA0_CORE_CTX_SRC_STRIDE_4, + mmPDMA0_CORE_CTX_SRC_OFFSET_LO, + mmPDMA0_CORE_CTX_SRC_OFFSET_HI, + mmPDMA0_CORE_CTX_DST_TSIZE_0, + mmPDMA0_CORE_CTX_DST_TSIZE_1, + mmPDMA0_CORE_CTX_DST_TSIZE_2, + mmPDMA0_CORE_CTX_DST_TSIZE_3, + mmPDMA0_CORE_CTX_DST_TSIZE_4, + mmPDMA0_CORE_CTX_DST_STRIDE_1, + mmPDMA0_CORE_CTX_DST_STRIDE_2, + mmPDMA0_CORE_CTX_DST_STRIDE_3, + mmPDMA0_CORE_CTX_DST_STRIDE_4, + mmPDMA0_CORE_CTX_DST_OFFSET_LO, + mmPDMA0_CORE_CTX_DST_OFFSET_HI, + mmPDMA0_CORE_CTX_COMMIT, + mmPDMA0_CORE_CTX_CTRL, + mmPDMA0_CORE_CTX_TE_NUMROWS, + mmPDMA0_CORE_CTX_IDX, + mmPDMA0_CORE_CTX_IDX_INC, + mmPDMA0_QM_CQ_CFG0_0, + mmPDMA0_QM_CQ_CFG0_1, + mmPDMA0_QM_CQ_CFG0_2, + mmPDMA0_QM_CQ_CFG0_3, + mmPDMA0_QM_CQ_CFG0_4, + mmPDMA0_QM_CP_FENCE0_RDATA_0, + mmPDMA0_QM_CP_FENCE0_RDATA_1, + mmPDMA0_QM_CP_FENCE0_RDATA_2, + mmPDMA0_QM_CP_FENCE0_RDATA_3, + mmPDMA0_QM_CP_FENCE0_RDATA_4, + mmPDMA0_QM_CP_FENCE1_RDATA_0, + mmPDMA0_QM_CP_FENCE1_RDATA_1, + mmPDMA0_QM_CP_FENCE1_RDATA_2, + mmPDMA0_QM_CP_FENCE1_RDATA_3, + mmPDMA0_QM_CP_FENCE1_RDATA_4, + mmPDMA0_QM_CP_FENCE2_RDATA_0, + mmPDMA0_QM_CP_FENCE2_RDATA_1, + mmPDMA0_QM_CP_FENCE2_RDATA_2, + mmPDMA0_QM_CP_FENCE2_RDATA_3, + mmPDMA0_QM_CP_FENCE2_RDATA_4, + mmPDMA0_QM_CP_FENCE3_RDATA_0, + mmPDMA0_QM_CP_FENCE3_RDATA_1, + mmPDMA0_QM_CP_FENCE3_RDATA_2, + mmPDMA0_QM_CP_FENCE3_RDATA_3, + mmPDMA0_QM_CP_FENCE3_RDATA_4, + mmPDMA0_QM_CP_FENCE0_CNT_0, + mmPDMA0_QM_CP_FENCE0_CNT_1, + mmPDMA0_QM_CP_FENCE0_CNT_2, + mmPDMA0_QM_CP_FENCE0_CNT_3, + mmPDMA0_QM_CP_FENCE0_CNT_4, + mmPDMA0_QM_CP_FENCE1_CNT_0, + mmPDMA0_QM_CP_FENCE1_CNT_1, + mmPDMA0_QM_CP_FENCE1_CNT_2, + mmPDMA0_QM_CP_FENCE1_CNT_3, + mmPDMA0_QM_CP_FENCE1_CNT_4, + mmPDMA0_QM_CP_FENCE2_CNT_0, + mmPDMA0_QM_CP_FENCE2_CNT_1, + mmPDMA0_QM_CP_FENCE2_CNT_2, + mmPDMA0_QM_CP_FENCE2_CNT_3, + mmPDMA0_QM_CP_FENCE2_CNT_4, + mmPDMA0_QM_CP_FENCE3_CNT_0, + mmPDMA0_QM_CP_FENCE3_CNT_1, + mmPDMA0_QM_CP_FENCE3_CNT_2, + mmPDMA0_QM_CP_FENCE3_CNT_3, + mmPDMA0_QM_CP_FENCE3_CNT_4, + mmPDMA0_QM_CQ_PTR_LO_0, + mmPDMA0_QM_CQ_PTR_HI_0, + mmPDMA0_QM_CQ_TSIZE_0, + mmPDMA0_QM_CQ_CTL_0, + mmPDMA0_QM_CQ_PTR_LO_1, + mmPDMA0_QM_CQ_PTR_HI_1, + mmPDMA0_QM_CQ_TSIZE_1, + mmPDMA0_QM_CQ_CTL_1, + mmPDMA0_QM_CQ_PTR_LO_2, + mmPDMA0_QM_CQ_PTR_HI_2, + mmPDMA0_QM_CQ_TSIZE_2, + mmPDMA0_QM_CQ_CTL_2, + mmPDMA0_QM_CQ_PTR_LO_3, + mmPDMA0_QM_CQ_PTR_HI_3, + mmPDMA0_QM_CQ_TSIZE_3, + mmPDMA0_QM_CQ_CTL_3, + mmPDMA0_QM_CQ_PTR_LO_4, + mmPDMA0_QM_CQ_PTR_HI_4, + mmPDMA0_QM_CQ_TSIZE_4, + mmPDMA0_QM_CQ_CTL_4, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE, + mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4, + mmPDMA0_QM_ARC_CQ_PTR_LO, + mmPDMA0_QM_ARC_CQ_PTR_LO_STS, + mmPDMA0_QM_ARC_CQ_PTR_HI, + mmPDMA0_QM_ARC_CQ_PTR_HI_STS, + mmPDMA0_QM_ARB_CFG_0, + mmPDMA0_QM_ARB_MST_QUIET_PER, + mmPDMA0_QM_ARB_CHOICE_Q_PUSH, + mmPDMA0_QM_ARB_WRR_WEIGHT_0, + mmPDMA0_QM_ARB_WRR_WEIGHT_1, + mmPDMA0_QM_ARB_WRR_WEIGHT_2, + mmPDMA0_QM_ARB_WRR_WEIGHT_3, + mmPDMA0_QM_ARB_BASE_LO, + mmPDMA0_QM_ARB_BASE_HI, + mmPDMA0_QM_ARB_MST_SLAVE_EN, + mmPDMA0_QM_ARB_MST_SLAVE_EN_1, + mmPDMA0_QM_ARB_MST_CRED_INC, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62, + mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63, + mmPDMA0_QM_ARB_SLV_ID, + mmPDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST, + mmPDMA0_QM_ARC_CQ_CFG0, + mmPDMA0_QM_CQ_IFIFO_CI_0, + mmPDMA0_QM_CQ_IFIFO_CI_1, + mmPDMA0_QM_CQ_IFIFO_CI_2, + mmPDMA0_QM_CQ_IFIFO_CI_3, + mmPDMA0_QM_CQ_IFIFO_CI_4, + mmPDMA0_QM_ARC_CQ_IFIFO_CI, + mmPDMA0_QM_CQ_CTL_CI_0, + mmPDMA0_QM_CQ_CTL_CI_1, + mmPDMA0_QM_CQ_CTL_CI_2, + mmPDMA0_QM_CQ_CTL_CI_3, + mmPDMA0_QM_CQ_CTL_CI_4, + mmPDMA0_QM_ARC_CQ_CTL_CI, + mmPDMA0_QM_ARC_CQ_TSIZE, + mmPDMA0_QM_ARC_CQ_CTL, + mmPDMA0_QM_CP_SWITCH_WD_SET, + mmPDMA0_QM_CP_EXT_SWITCH, + mmPDMA0_QM_CP_PRED_0, + mmPDMA0_QM_CP_PRED_1, + mmPDMA0_QM_CP_PRED_2, + mmPDMA0_QM_CP_PRED_3, + mmPDMA0_QM_CP_PRED_4, + mmPDMA0_QM_CP_PRED_UPEN_0, + mmPDMA0_QM_CP_PRED_UPEN_1, + mmPDMA0_QM_CP_PRED_UPEN_2, + mmPDMA0_QM_CP_PRED_UPEN_3, + mmPDMA0_QM_CP_PRED_UPEN_4, + mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_0, + mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_1, + mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_2, + mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_3, + mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_4, + mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_0, + mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_1, + mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_2, + mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_3, + mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_4, + mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_0, + mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_1, + mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_2, + mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_3, + mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_4, + mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_0, + mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_1, + mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_2, + mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_3, + mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_4, + mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_0, + mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_1, + mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_2, + mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_3, + mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_4, + mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_0, + mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_1, + mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_2, + mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_3, + mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_4, + mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_0, + mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_1, + mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_2, + mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_3, + mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_4, + mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_0, + mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_1, + mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_2, + mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_3, + mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_4, + mmPDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO, + mmPDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO, + mmPDMA0_QM_CQ_IFIFO_MSG_BASE_LO, + mmPDMA0_QM_CQ_CTL_MSG_BASE_LO +}; + +static const u32 gaudi2_pb_dcr0_edma0[] = { + mmDCORE0_EDMA0_CORE_BASE, + mmDCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE, + mmDCORE0_EDMA0_QM_BASE, +}; + +static const u32 gaudi2_pb_dcr0_edma0_arc[] = { + mmDCORE0_EDMA0_QM_ARC_AUX_BASE, +}; + +static const struct range gaudi2_pb_dcr0_edma0_arc_unsecured_regs[] = { + {mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_ACK}, + {mmDCORE0_EDMA0_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_EDMA0_QM_ARC_AUX_WAKE_UP_EVENT}, + {mmDCORE0_EDMA0_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_7}, + {mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_EDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT}, + {mmDCORE0_EDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, + mmDCORE0_EDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN}, + {mmDCORE0_EDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, + mmDCORE0_EDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN}, + {mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, + mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG}, + {mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, + mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI}, + {mmDCORE0_EDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, + mmDCORE0_EDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN}, +}; + +static const u32 gaudi2_pb_dcr0_edma0_unsecured_regs[] = { + mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION, + mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_HI, + mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_LO, + mmDCORE0_EDMA0_CORE_CTX_WR_COMP_WDATA, + mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_LO, + mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_HI, + mmDCORE0_EDMA0_CORE_CTX_DST_BASE_LO, + mmDCORE0_EDMA0_CORE_CTX_DST_BASE_HI, + mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_0, + mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_1, + mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_2, + mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_3, + mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_4, + mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_1, + mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_2, + mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_3, + mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_4, + mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_LO, + mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_HI, + mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_0, + mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_1, + mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_2, + mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_3, + mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_4, + mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_1, + mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_2, + mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_3, + mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_4, + mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_LO, + mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_HI, + mmDCORE0_EDMA0_CORE_CTX_COMMIT, + mmDCORE0_EDMA0_CORE_CTX_CTRL, + mmDCORE0_EDMA0_CORE_CTX_TE_NUMROWS, + mmDCORE0_EDMA0_CORE_CTX_IDX, + mmDCORE0_EDMA0_CORE_CTX_IDX_INC, + mmDCORE0_EDMA0_QM_CQ_CFG0_0, + mmDCORE0_EDMA0_QM_CQ_CFG0_1, + mmDCORE0_EDMA0_QM_CQ_CFG0_2, + mmDCORE0_EDMA0_QM_CQ_CFG0_3, + mmDCORE0_EDMA0_QM_CQ_CFG0_4, + mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_0, + mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_1, + mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_2, + mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_3, + mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_4, + mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_0, + mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_1, + mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_2, + mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_3, + mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_4, + mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_0, + mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_1, + mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_2, + mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_3, + mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_4, + mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_0, + mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_1, + mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_2, + mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_3, + mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_4, + mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_0, + mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_1, + mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_2, + mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_3, + mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_4, + mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_0, + mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_1, + mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_2, + mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_3, + mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_4, + mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_0, + mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_1, + mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_2, + mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_3, + mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_4, + mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_0, + mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_1, + mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_2, + mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_3, + mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_4, + mmDCORE0_EDMA0_QM_CQ_PTR_LO_0, + mmDCORE0_EDMA0_QM_CQ_PTR_HI_0, + mmDCORE0_EDMA0_QM_CQ_TSIZE_0, + mmDCORE0_EDMA0_QM_CQ_CTL_0, + mmDCORE0_EDMA0_QM_CQ_PTR_LO_1, + mmDCORE0_EDMA0_QM_CQ_PTR_HI_1, + mmDCORE0_EDMA0_QM_CQ_TSIZE_1, + mmDCORE0_EDMA0_QM_CQ_CTL_1, + mmDCORE0_EDMA0_QM_CQ_PTR_LO_2, + mmDCORE0_EDMA0_QM_CQ_PTR_HI_2, + mmDCORE0_EDMA0_QM_CQ_TSIZE_2, + mmDCORE0_EDMA0_QM_CQ_CTL_2, + mmDCORE0_EDMA0_QM_CQ_PTR_LO_3, + mmDCORE0_EDMA0_QM_CQ_PTR_HI_3, + mmDCORE0_EDMA0_QM_CQ_TSIZE_3, + mmDCORE0_EDMA0_QM_CQ_CTL_3, + mmDCORE0_EDMA0_QM_CQ_PTR_LO_4, + mmDCORE0_EDMA0_QM_CQ_PTR_HI_4, + mmDCORE0_EDMA0_QM_CQ_TSIZE_4, + mmDCORE0_EDMA0_QM_CQ_CTL_4, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE, + mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4, + mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO, + mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS, + mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI, + mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS, + mmDCORE0_EDMA0_QM_ARB_CFG_0, + mmDCORE0_EDMA0_QM_ARB_MST_QUIET_PER, + mmDCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH, + mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_0, + mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_1, + mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_2, + mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_3, + mmDCORE0_EDMA0_QM_ARB_BASE_LO, + mmDCORE0_EDMA0_QM_ARB_BASE_HI, + mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN, + mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1, + mmDCORE0_EDMA0_QM_ARB_MST_CRED_INC, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62, + mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63, + mmDCORE0_EDMA0_QM_ARB_SLV_ID, + mmDCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST, + mmDCORE0_EDMA0_QM_ARC_CQ_CFG0, + mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_0, + mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_1, + mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_2, + mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_3, + mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_4, + mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI, + mmDCORE0_EDMA0_QM_CQ_CTL_CI_0, + mmDCORE0_EDMA0_QM_CQ_CTL_CI_1, + mmDCORE0_EDMA0_QM_CQ_CTL_CI_2, + mmDCORE0_EDMA0_QM_CQ_CTL_CI_3, + mmDCORE0_EDMA0_QM_CQ_CTL_CI_4, + mmDCORE0_EDMA0_QM_ARC_CQ_CTL_CI, + mmDCORE0_EDMA0_QM_ARC_CQ_TSIZE, + mmDCORE0_EDMA0_QM_ARC_CQ_CTL, + mmDCORE0_EDMA0_QM_CP_SWITCH_WD_SET, + mmDCORE0_EDMA0_QM_CP_EXT_SWITCH, + mmDCORE0_EDMA0_QM_CP_PRED_0, + mmDCORE0_EDMA0_QM_CP_PRED_1, + mmDCORE0_EDMA0_QM_CP_PRED_2, + mmDCORE0_EDMA0_QM_CP_PRED_3, + mmDCORE0_EDMA0_QM_CP_PRED_4, + mmDCORE0_EDMA0_QM_CP_PRED_UPEN_0, + mmDCORE0_EDMA0_QM_CP_PRED_UPEN_1, + mmDCORE0_EDMA0_QM_CP_PRED_UPEN_2, + mmDCORE0_EDMA0_QM_CP_PRED_UPEN_3, + mmDCORE0_EDMA0_QM_CP_PRED_UPEN_4, + mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_0, + mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_1, + mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_2, + mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_3, + mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_4, + mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_0, + mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_1, + mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_2, + mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_3, + mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_4, + mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_0, + mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_1, + mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_2, + mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_3, + mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_4, + mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_0, + mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_1, + mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_2, + mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_3, + mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_4, + mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_0, + mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_1, + mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_2, + mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_3, + mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_4, + mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_0, + mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_1, + mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_2, + mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_3, + mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_4, + mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_0, + mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_1, + mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_2, + mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_3, + mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_4, + mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_0, + mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_1, + mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_2, + mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_3, + mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_4, + mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO, + mmDCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO, + mmDCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO, + mmDCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO +}; + +static const u32 gaudi2_pb_dcr0_mme_sbte[] = { + mmDCORE0_MME_SBTE0_BASE, + mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE, +}; + +static const u32 gaudi2_pb_dcr0_mme_qm[] = { + mmDCORE0_MME_QM_BASE, +}; + +static const u32 gaudi2_pb_dcr0_mme_eng[] = { + mmDCORE0_MME_ACC_BASE, + mmDCORE0_MME_CTRL_HI_BASE, + mmDCORE0_MME_CTRL_LO_BASE, + mmDCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE, + mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE, + mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE, +}; + +static const u32 gaudi2_pb_dcr0_mme_arc[] = { + mmDCORE0_MME_QM_ARC_AUX_BASE, + mmDCORE0_MME_QM_ARC_DUP_ENG_BASE, +}; + +static const struct range gaudi2_pb_dcr0_mme_arc_unsecured_regs[] = { + {mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_ACK}, + {mmDCORE0_MME_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_MME_QM_ARC_AUX_WAKE_UP_EVENT}, + {mmDCORE0_MME_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_7}, + {mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT}, + {mmDCORE0_MME_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmDCORE0_MME_QM_ARC_AUX_CBU_EARLY_BRESP_EN}, + {mmDCORE0_MME_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmDCORE0_MME_QM_ARC_AUX_LBU_EARLY_BRESP_EN}, + {mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, + mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG}, + {mmDCORE0_MME_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, + mmDCORE0_MME_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI}, + {mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, + mmDCORE0_MME_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN}, + {mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_0, + mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_63}, + {mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_STRONG_ORDER, + mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_LB_OVRD}, +}; + +static const u32 gaudi2_pb_dcr0_mme_qm_unsecured_regs[] = { + mmDCORE0_MME_QM_CQ_CFG0_0, + mmDCORE0_MME_QM_CQ_CFG0_1, + mmDCORE0_MME_QM_CQ_CFG0_2, + mmDCORE0_MME_QM_CQ_CFG0_3, + mmDCORE0_MME_QM_CQ_CFG0_4, + mmDCORE0_MME_QM_CP_FENCE0_RDATA_0, + mmDCORE0_MME_QM_CP_FENCE0_RDATA_1, + mmDCORE0_MME_QM_CP_FENCE0_RDATA_2, + mmDCORE0_MME_QM_CP_FENCE0_RDATA_3, + mmDCORE0_MME_QM_CP_FENCE0_RDATA_4, + mmDCORE0_MME_QM_CP_FENCE1_RDATA_0, + mmDCORE0_MME_QM_CP_FENCE1_RDATA_1, + mmDCORE0_MME_QM_CP_FENCE1_RDATA_2, + mmDCORE0_MME_QM_CP_FENCE1_RDATA_3, + mmDCORE0_MME_QM_CP_FENCE1_RDATA_4, + mmDCORE0_MME_QM_CP_FENCE2_RDATA_0, + mmDCORE0_MME_QM_CP_FENCE2_RDATA_1, + mmDCORE0_MME_QM_CP_FENCE2_RDATA_2, + mmDCORE0_MME_QM_CP_FENCE2_RDATA_3, + mmDCORE0_MME_QM_CP_FENCE2_RDATA_4, + mmDCORE0_MME_QM_CP_FENCE3_RDATA_0, + mmDCORE0_MME_QM_CP_FENCE3_RDATA_1, + mmDCORE0_MME_QM_CP_FENCE3_RDATA_2, + mmDCORE0_MME_QM_CP_FENCE3_RDATA_3, + mmDCORE0_MME_QM_CP_FENCE3_RDATA_4, + mmDCORE0_MME_QM_CP_FENCE0_CNT_0, + mmDCORE0_MME_QM_CP_FENCE0_CNT_1, + mmDCORE0_MME_QM_CP_FENCE0_CNT_2, + mmDCORE0_MME_QM_CP_FENCE0_CNT_3, + mmDCORE0_MME_QM_CP_FENCE0_CNT_4, + mmDCORE0_MME_QM_CP_FENCE1_CNT_0, + mmDCORE0_MME_QM_CP_FENCE1_CNT_1, + mmDCORE0_MME_QM_CP_FENCE1_CNT_2, + mmDCORE0_MME_QM_CP_FENCE1_CNT_3, + mmDCORE0_MME_QM_CP_FENCE1_CNT_4, + mmDCORE0_MME_QM_CP_FENCE2_CNT_0, + mmDCORE0_MME_QM_CP_FENCE2_CNT_1, + mmDCORE0_MME_QM_CP_FENCE2_CNT_2, + mmDCORE0_MME_QM_CP_FENCE2_CNT_3, + mmDCORE0_MME_QM_CP_FENCE2_CNT_4, + mmDCORE0_MME_QM_CP_FENCE3_CNT_0, + mmDCORE0_MME_QM_CP_FENCE3_CNT_1, + mmDCORE0_MME_QM_CP_FENCE3_CNT_2, + mmDCORE0_MME_QM_CP_FENCE3_CNT_3, + mmDCORE0_MME_QM_CP_FENCE3_CNT_4, + mmDCORE0_MME_QM_CQ_PTR_LO_0, + mmDCORE0_MME_QM_CQ_PTR_HI_0, + mmDCORE0_MME_QM_CQ_TSIZE_0, + mmDCORE0_MME_QM_CQ_CTL_0, + mmDCORE0_MME_QM_CQ_PTR_LO_1, + mmDCORE0_MME_QM_CQ_PTR_HI_1, + mmDCORE0_MME_QM_CQ_TSIZE_1, + mmDCORE0_MME_QM_CQ_CTL_1, + mmDCORE0_MME_QM_CQ_PTR_LO_2, + mmDCORE0_MME_QM_CQ_PTR_HI_2, + mmDCORE0_MME_QM_CQ_TSIZE_2, + mmDCORE0_MME_QM_CQ_CTL_2, + mmDCORE0_MME_QM_CQ_PTR_LO_3, + mmDCORE0_MME_QM_CQ_PTR_HI_3, + mmDCORE0_MME_QM_CQ_TSIZE_3, + mmDCORE0_MME_QM_CQ_CTL_3, + mmDCORE0_MME_QM_CQ_PTR_LO_4, + mmDCORE0_MME_QM_CQ_PTR_HI_4, + mmDCORE0_MME_QM_CQ_TSIZE_4, + mmDCORE0_MME_QM_CQ_CTL_4, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE + 4, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE + 4, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE + 4, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE + 4, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE + 4, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE + 4, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE + 4, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE + 4, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE + 4, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE + 4, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE + 4, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE + 4, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE + 4, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE + 4, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE + 4, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE, + mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE + 4, + mmDCORE0_MME_QM_ARC_CQ_PTR_LO, + mmDCORE0_MME_QM_ARC_CQ_PTR_LO_STS, + mmDCORE0_MME_QM_ARC_CQ_PTR_HI, + mmDCORE0_MME_QM_ARC_CQ_PTR_HI_STS, + mmDCORE0_MME_QM_ARB_CFG_0, + mmDCORE0_MME_QM_ARB_MST_QUIET_PER, + mmDCORE0_MME_QM_ARB_CHOICE_Q_PUSH, + mmDCORE0_MME_QM_ARB_WRR_WEIGHT_0, + mmDCORE0_MME_QM_ARB_WRR_WEIGHT_1, + mmDCORE0_MME_QM_ARB_WRR_WEIGHT_2, + mmDCORE0_MME_QM_ARB_WRR_WEIGHT_3, + mmDCORE0_MME_QM_ARB_BASE_LO, + mmDCORE0_MME_QM_ARB_BASE_HI, + mmDCORE0_MME_QM_ARB_MST_SLAVE_EN, + mmDCORE0_MME_QM_ARB_MST_SLAVE_EN_1, + mmDCORE0_MME_QM_ARB_MST_CRED_INC, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_0, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_1, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_2, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_3, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_4, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_5, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_6, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_7, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_8, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_9, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_10, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_11, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_12, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_13, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_14, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_15, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_16, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_17, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_18, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_19, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_20, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_21, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_22, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_23, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_24, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_25, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_26, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_27, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_28, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_29, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_30, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_31, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_32, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_33, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_34, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_35, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_36, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_37, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_38, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_39, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_40, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_41, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_42, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_43, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_44, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_45, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_46, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_47, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_48, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_49, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_50, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_51, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_52, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_53, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_54, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_55, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_56, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_57, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_58, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_59, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_60, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_61, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_62, + mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_63, + mmDCORE0_MME_QM_ARB_SLV_ID, + mmDCORE0_MME_QM_ARB_SLV_MASTER_INC_CRED_OFST, + mmDCORE0_MME_QM_ARC_CQ_CFG0, + mmDCORE0_MME_QM_CQ_IFIFO_CI_0, + mmDCORE0_MME_QM_CQ_IFIFO_CI_1, + mmDCORE0_MME_QM_CQ_IFIFO_CI_2, + mmDCORE0_MME_QM_CQ_IFIFO_CI_3, + mmDCORE0_MME_QM_CQ_IFIFO_CI_4, + mmDCORE0_MME_QM_ARC_CQ_IFIFO_CI, + mmDCORE0_MME_QM_CQ_CTL_CI_0, + mmDCORE0_MME_QM_CQ_CTL_CI_1, + mmDCORE0_MME_QM_CQ_CTL_CI_2, + mmDCORE0_MME_QM_CQ_CTL_CI_3, + mmDCORE0_MME_QM_CQ_CTL_CI_4, + mmDCORE0_MME_QM_ARC_CQ_CTL_CI, + mmDCORE0_MME_QM_ARC_CQ_TSIZE, + mmDCORE0_MME_QM_ARC_CQ_CTL, + mmDCORE0_MME_QM_CP_SWITCH_WD_SET, + mmDCORE0_MME_QM_CP_EXT_SWITCH, + mmDCORE0_MME_QM_CP_PRED_0, + mmDCORE0_MME_QM_CP_PRED_1, + mmDCORE0_MME_QM_CP_PRED_2, + mmDCORE0_MME_QM_CP_PRED_3, + mmDCORE0_MME_QM_CP_PRED_4, + mmDCORE0_MME_QM_CP_PRED_UPEN_0, + mmDCORE0_MME_QM_CP_PRED_UPEN_1, + mmDCORE0_MME_QM_CP_PRED_UPEN_2, + mmDCORE0_MME_QM_CP_PRED_UPEN_3, + mmDCORE0_MME_QM_CP_PRED_UPEN_4, + mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_0, + mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_1, + mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_2, + mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_3, + mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_4, + mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_0, + mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_1, + mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_2, + mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_3, + mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_4, + mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_0, + mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_1, + mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_2, + mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_3, + mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_4, + mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_0, + mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_1, + mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_2, + mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_3, + mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_4, + mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_0, + mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_1, + mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_2, + mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_3, + mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_4, + mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_0, + mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_1, + mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_2, + mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_3, + mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_4, + mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_0, + mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_1, + mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_2, + mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_3, + mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_4, + mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_0, + mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_1, + mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_2, + mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_3, + mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_4, + mmDCORE0_MME_QM_ARC_CQ_IFIFO_MSG_BASE_LO, + mmDCORE0_MME_QM_ARC_CQ_CTL_MSG_BASE_LO, + mmDCORE0_MME_QM_CQ_IFIFO_MSG_BASE_LO, + mmDCORE0_MME_QM_CQ_CTL_MSG_BASE_LO +}; + +static const u32 gaudi2_pb_dcr0_mme_eng_unsecured_regs[] = { + mmDCORE0_MME_CTRL_LO_CMD, + mmDCORE0_MME_CTRL_LO_AGU, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_0, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_1, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_2, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_3, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_4, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_0, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_1, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_2, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_3, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_4, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_LOW, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_HIGH, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_LOW, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_HIGH, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_MASTER, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_SLAVE, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_KERNEL_SIZE_MINUS_1, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_LOW, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_HIGH, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_OUTER_LOOP, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_NUM_ITERATIONS_MINUS_1, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SB_REPEAT, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_FP8_BIAS, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_RATE_LIMITER, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_USER_DATA, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_IN, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_OUT, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PCU, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ0_ADDR, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ1_ADDR, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_POWER_LOOP, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_MASTER, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_MASTER, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_MASTER, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_MASTER, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_SLAVE, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_SLAVE, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_SLAVE, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_SLAVE, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_WKL_ID, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_0, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_1, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_2, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_3, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_4, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_0, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_1, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_2, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_3, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_4, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_0, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_1, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_2, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_3, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_4, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_0, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_1, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_2, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_3, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_4, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_0, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_1, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_2, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_3, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_4, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_0, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_1, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_2, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_3, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_4, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_0, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_1, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_2, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_3, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_4, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_0, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_1, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_2, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_3, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_4, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_0, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_1, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_2, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_3, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_0, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_1, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_2, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_3, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_0, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_1, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_2, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_3, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_0, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_1, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_2, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_3, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_4, + mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_LOW, + mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_HIGH, + mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_LOW, + mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_HIGH, + mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_LOW, + mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_HIGH, + mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_LOW, + mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_HIGH, + mmDCORE0_MME_CTRL_LO_ARCH_STATUS, + mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0, + mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0, + mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0, + mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1, + mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1, + mmDCORE0_MME_CTRL_LO_ARCH_A_SS, + mmDCORE0_MME_CTRL_LO_ARCH_B_SS, + mmDCORE0_MME_CTRL_LO_ARCH_COUT_SS, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_0, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_1, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_2, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_3, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_4, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_0, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_1, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_2, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_3, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_4, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_0, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_1, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_2, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_3, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_4, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_0, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_1, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_2, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_3, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_4, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_0, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_1, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_2, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_3, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_0, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_1, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_2, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_3, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_0, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_1, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_2, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_3, + mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_BASE, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_BASE, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_BASE, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE, + mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_0, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_1, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_2, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_3, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_4, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_0, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_1, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_2, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_3, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_4, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_0, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_1, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_2, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_3, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_4, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_0, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_1, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_2, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_3, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_4, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_0, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_1, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_2, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_3, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_0, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_1, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_2, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_3, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_0, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_1, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_2, + mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_3, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_0, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_1, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_2, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_3, + mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_4, + mmDCORE0_MME_ACC_AP_LFSR_POLY, + mmDCORE0_MME_ACC_AP_LFSR_SEED_WDATA, + mmDCORE0_MME_ACC_AP_LFSR_SEED_SEL, + mmDCORE0_MME_ACC_AP_LFSR_SEED_RDATA, + mmDCORE0_MME_ACC_AP_LFSR_CLOSE_CGATE_DLY, + mmDCORE0_MME_ACC_WBC_SRC_BP, +}; + +static const u32 gaudi2_pb_dcr0_tpc0[] = { + mmDCORE0_TPC0_QM_BASE, + mmDCORE0_TPC0_CFG_BASE, + mmDCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_BASE, +}; + +static const u32 gaudi2_pb_dcr0_tpc0_arc[] = { + mmDCORE0_TPC0_QM_ARC_AUX_BASE, +}; + +static const struct range gaudi2_pb_dcr0_tpc0_arc_unsecured_regs[] = { + {mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_ACK}, + {mmDCORE0_TPC0_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_TPC0_QM_ARC_AUX_WAKE_UP_EVENT}, + {mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_7}, + {mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT}, + {mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN}, + {mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN}, + {mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, + mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG}, + {mmDCORE0_TPC0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, + mmDCORE0_TPC0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI}, + {mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, + mmDCORE0_TPC0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN}, +}; + +static const u32 gaudi2_pb_dcr0_tpc0_unsecured_regs[] = { + mmDCORE0_TPC0_QM_CQ_CFG0_0, + mmDCORE0_TPC0_QM_CQ_CFG0_1, + mmDCORE0_TPC0_QM_CQ_CFG0_2, + mmDCORE0_TPC0_QM_CQ_CFG0_3, + mmDCORE0_TPC0_QM_CQ_CFG0_4, + mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_0, + mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_1, + mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_2, + mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_3, + mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_4, + mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_0, + mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_1, + mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_2, + mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_3, + mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_4, + mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_0, + mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_1, + mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_2, + mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_3, + mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_4, + mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_0, + mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_1, + mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_2, + mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_3, + mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_4, + mmDCORE0_TPC0_QM_CP_FENCE0_CNT_0, + mmDCORE0_TPC0_QM_CP_FENCE0_CNT_1, + mmDCORE0_TPC0_QM_CP_FENCE0_CNT_2, + mmDCORE0_TPC0_QM_CP_FENCE0_CNT_3, + mmDCORE0_TPC0_QM_CP_FENCE0_CNT_4, + mmDCORE0_TPC0_QM_CP_FENCE1_CNT_0, + mmDCORE0_TPC0_QM_CP_FENCE1_CNT_1, + mmDCORE0_TPC0_QM_CP_FENCE1_CNT_2, + mmDCORE0_TPC0_QM_CP_FENCE1_CNT_3, + mmDCORE0_TPC0_QM_CP_FENCE1_CNT_4, + mmDCORE0_TPC0_QM_CP_FENCE2_CNT_0, + mmDCORE0_TPC0_QM_CP_FENCE2_CNT_1, + mmDCORE0_TPC0_QM_CP_FENCE2_CNT_2, + mmDCORE0_TPC0_QM_CP_FENCE2_CNT_3, + mmDCORE0_TPC0_QM_CP_FENCE2_CNT_4, + mmDCORE0_TPC0_QM_CP_FENCE3_CNT_0, + mmDCORE0_TPC0_QM_CP_FENCE3_CNT_1, + mmDCORE0_TPC0_QM_CP_FENCE3_CNT_2, + mmDCORE0_TPC0_QM_CP_FENCE3_CNT_3, + mmDCORE0_TPC0_QM_CP_FENCE3_CNT_4, + mmDCORE0_TPC0_QM_CQ_PTR_LO_0, + mmDCORE0_TPC0_QM_CQ_PTR_HI_0, + mmDCORE0_TPC0_QM_CQ_TSIZE_0, + mmDCORE0_TPC0_QM_CQ_CTL_0, + mmDCORE0_TPC0_QM_CQ_PTR_LO_1, + mmDCORE0_TPC0_QM_CQ_PTR_HI_1, + mmDCORE0_TPC0_QM_CQ_TSIZE_1, + mmDCORE0_TPC0_QM_CQ_CTL_1, + mmDCORE0_TPC0_QM_CQ_PTR_LO_2, + mmDCORE0_TPC0_QM_CQ_PTR_HI_2, + mmDCORE0_TPC0_QM_CQ_TSIZE_2, + mmDCORE0_TPC0_QM_CQ_CTL_2, + mmDCORE0_TPC0_QM_CQ_PTR_LO_3, + mmDCORE0_TPC0_QM_CQ_PTR_HI_3, + mmDCORE0_TPC0_QM_CQ_TSIZE_3, + mmDCORE0_TPC0_QM_CQ_CTL_3, + mmDCORE0_TPC0_QM_CQ_PTR_LO_4, + mmDCORE0_TPC0_QM_CQ_PTR_HI_4, + mmDCORE0_TPC0_QM_CQ_TSIZE_4, + mmDCORE0_TPC0_QM_CQ_CTL_4, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE, + mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4, + mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO, + mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO_STS, + mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI, + mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI_STS, + mmDCORE0_TPC0_QM_ARB_CFG_0, + mmDCORE0_TPC0_QM_ARB_MST_QUIET_PER, + mmDCORE0_TPC0_QM_ARB_CHOICE_Q_PUSH, + mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_0, + mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_1, + mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_2, + mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_3, + mmDCORE0_TPC0_QM_ARB_BASE_LO, + mmDCORE0_TPC0_QM_ARB_BASE_HI, + mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN, + mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN_1, + mmDCORE0_TPC0_QM_ARB_MST_CRED_INC, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_0, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_1, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_2, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_3, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_4, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_5, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_6, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_7, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_8, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_9, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_10, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_11, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_12, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_13, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_14, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_15, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_16, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_17, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_18, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_19, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_20, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_21, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_22, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_23, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_24, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_25, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_26, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_27, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_28, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_29, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_30, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_31, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_32, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_33, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_34, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_35, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_36, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_37, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_38, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_39, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_40, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_41, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_42, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_43, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_44, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_45, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_46, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_47, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_48, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_49, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_50, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_51, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_52, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_53, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_54, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_55, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_56, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_57, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_58, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_59, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_60, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_61, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_62, + mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_63, + mmDCORE0_TPC0_QM_ARB_SLV_ID, + mmDCORE0_TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST, + mmDCORE0_TPC0_QM_ARC_CQ_CFG0, + mmDCORE0_TPC0_QM_CQ_IFIFO_CI_0, + mmDCORE0_TPC0_QM_CQ_IFIFO_CI_1, + mmDCORE0_TPC0_QM_CQ_IFIFO_CI_2, + mmDCORE0_TPC0_QM_CQ_IFIFO_CI_3, + mmDCORE0_TPC0_QM_CQ_IFIFO_CI_4, + mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_CI, + mmDCORE0_TPC0_QM_CQ_CTL_CI_0, + mmDCORE0_TPC0_QM_CQ_CTL_CI_1, + mmDCORE0_TPC0_QM_CQ_CTL_CI_2, + mmDCORE0_TPC0_QM_CQ_CTL_CI_3, + mmDCORE0_TPC0_QM_CQ_CTL_CI_4, + mmDCORE0_TPC0_QM_ARC_CQ_CTL_CI, + mmDCORE0_TPC0_QM_ARC_CQ_TSIZE, + mmDCORE0_TPC0_QM_ARC_CQ_CTL, + mmDCORE0_TPC0_QM_CP_SWITCH_WD_SET, + mmDCORE0_TPC0_QM_CP_EXT_SWITCH, + mmDCORE0_TPC0_QM_CP_PRED_0, + mmDCORE0_TPC0_QM_CP_PRED_1, + mmDCORE0_TPC0_QM_CP_PRED_2, + mmDCORE0_TPC0_QM_CP_PRED_3, + mmDCORE0_TPC0_QM_CP_PRED_4, + mmDCORE0_TPC0_QM_CP_PRED_UPEN_0, + mmDCORE0_TPC0_QM_CP_PRED_UPEN_1, + mmDCORE0_TPC0_QM_CP_PRED_UPEN_2, + mmDCORE0_TPC0_QM_CP_PRED_UPEN_3, + mmDCORE0_TPC0_QM_CP_PRED_UPEN_4, + mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_0, + mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_1, + mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_2, + mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_3, + mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_4, + mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_0, + mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_1, + mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_2, + mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_3, + mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_4, + mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_0, + mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_1, + mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_2, + mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_3, + mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_4, + mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_0, + mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_1, + mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_2, + mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_3, + mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_4, + mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_0, + mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_1, + mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_2, + mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_3, + mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_4, + mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_0, + mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_1, + mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_2, + mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_3, + mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_4, + mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_0, + mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_1, + mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_2, + mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_3, + mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_4, + mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_0, + mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_1, + mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_2, + mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_3, + mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_4, + mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_MSG_BASE_LO, + mmDCORE0_TPC0_QM_ARC_CQ_CTL_MSG_BASE_LO, + mmDCORE0_TPC0_QM_CQ_IFIFO_MSG_BASE_LO, + mmDCORE0_TPC0_QM_CQ_CTL_MSG_BASE_LO, + mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_MESSAGE, + mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_ADDR, + mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW, + mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH, + mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_0, + mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_0, + mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_1, + mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_1, + mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_2, + mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_2, + mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_3, + mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_3, + mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_4, + mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_4, + mmDCORE0_TPC0_CFG_QM_KERNEL_CONFIG, + mmDCORE0_TPC0_CFG_QM_KERNEL_ID, + mmDCORE0_TPC0_CFG_QM_POWER_LOOP, + mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO, + mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI, + mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO, + mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI, + mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO, + mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI, + mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO, + mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI, + mmDCORE0_TPC0_CFG_ROUND_CSR, + mmDCORE0_TPC0_CFG_CONV_ROUND_CSR, + mmDCORE0_TPC0_CFG_SEMAPHORE, + mmDCORE0_TPC0_CFG_LFSR_POLYNOM, + mmDCORE0_TPC0_CFG_STATUS, + mmDCORE0_TPC0_CFG_TPC_CMD, + mmDCORE0_TPC0_CFG_TPC_EXECUTE, + mmDCORE0_TPC0_CFG_TPC_DCACHE_L0CD, + mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW, + mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH, + mmDCORE0_TPC0_CFG_RD_RATE_LIMIT, + mmDCORE0_TPC0_CFG_WR_RATE_LIMIT, + mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO, + mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI, + mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO, + mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI, + mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO, + mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI, + mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO, + mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI, + mmDCORE0_TPC0_CFG_KERNEL_SRF_0, + mmDCORE0_TPC0_CFG_KERNEL_SRF_1, + mmDCORE0_TPC0_CFG_KERNEL_SRF_2, + mmDCORE0_TPC0_CFG_KERNEL_SRF_3, + mmDCORE0_TPC0_CFG_KERNEL_SRF_4, + mmDCORE0_TPC0_CFG_KERNEL_SRF_5, + mmDCORE0_TPC0_CFG_KERNEL_SRF_6, + mmDCORE0_TPC0_CFG_KERNEL_SRF_7, + mmDCORE0_TPC0_CFG_KERNEL_SRF_8, + mmDCORE0_TPC0_CFG_KERNEL_SRF_9, + mmDCORE0_TPC0_CFG_KERNEL_SRF_10, + mmDCORE0_TPC0_CFG_KERNEL_SRF_11, + mmDCORE0_TPC0_CFG_KERNEL_SRF_12, + mmDCORE0_TPC0_CFG_KERNEL_SRF_13, + mmDCORE0_TPC0_CFG_KERNEL_SRF_14, + mmDCORE0_TPC0_CFG_KERNEL_SRF_15, + mmDCORE0_TPC0_CFG_KERNEL_SRF_16, + mmDCORE0_TPC0_CFG_KERNEL_SRF_17, + mmDCORE0_TPC0_CFG_KERNEL_SRF_18, + mmDCORE0_TPC0_CFG_KERNEL_SRF_19, + mmDCORE0_TPC0_CFG_KERNEL_SRF_20, + mmDCORE0_TPC0_CFG_KERNEL_SRF_21, + mmDCORE0_TPC0_CFG_KERNEL_SRF_22, + mmDCORE0_TPC0_CFG_KERNEL_SRF_23, + mmDCORE0_TPC0_CFG_KERNEL_SRF_24, + mmDCORE0_TPC0_CFG_KERNEL_SRF_25, + mmDCORE0_TPC0_CFG_KERNEL_SRF_26, + mmDCORE0_TPC0_CFG_KERNEL_SRF_27, + mmDCORE0_TPC0_CFG_KERNEL_SRF_28, + mmDCORE0_TPC0_CFG_KERNEL_SRF_29, + mmDCORE0_TPC0_CFG_KERNEL_SRF_30, + mmDCORE0_TPC0_CFG_KERNEL_SRF_31, + mmDCORE0_TPC0_CFG_TPC_SB_L0CD, + mmDCORE0_TPC0_CFG_QM_KERNEL_ID_INC, + mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_0, + mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_1, + mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_2, + mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_3, + mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_4, + mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_0, + mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_1, + mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_2, + mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_3 +}; + +static const u32 gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs[] = { + mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW, + mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH, + mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE, + mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG, + mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE, + mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE, + mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE, + mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE, + mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE, + mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE, + mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE, + mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE, + mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE, + mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE, + mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PREF_STRIDE, + mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH, + mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH, + mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH, + mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH, + mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH, +}; + +static const u32 gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs[] = { + mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW, + mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH, + mmDCORE0_TPC0_CFG_QM_TENSOR_0_PADDING_VALUE, + mmDCORE0_TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG, + mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE, + mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE, + mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE, + mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE, + mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE, + mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE, + mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE, + mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE, + mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE, + mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE, + mmDCORE0_TPC0_CFG_QM_TENSOR_0_PREF_STRIDE, + mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH, + mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH, + mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH, + mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH, + mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH, +}; + +static const u32 gaudi2_pb_dcr0_sram0[] = { + mmDCORE0_SRAM0_BANK_BASE, + mmDCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE, + mmDCORE0_SRAM0_RTR_BASE, +}; + +static const u32 gaudi2_pb_dcr0_sm_mstr_if[] = { + mmDCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE, +}; + +static const u32 gaudi2_pb_dcr0_sm_glbl[] = { + mmDCORE0_SYNC_MNGR_GLBL_BASE, +}; + +static const struct range gaudi2_pb_dcr0_sm_glbl_unsecured_regs[] = { + {mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63}, + {mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63}, + {mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63}, + {mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_63}, + {mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_63}, + {mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_63}, + {mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_63}, + {mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_63}, +}; + +static const struct range gaudi2_pb_dcr_x_sm_glbl_unsecured_regs[] = { + {mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63}, + {mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63}, + {mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63}, + {mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_63}, + {mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_0, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_63}, + {mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_63}, + {mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_0, mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_63}, + {mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_63}, +}; + +static const u32 gaudi2_pb_arc_sched[] = { + mmARC_FARM_ARC0_AUX_BASE, + mmARC_FARM_ARC0_DUP_ENG_BASE, + mmARC_FARM_ARC0_ACP_ENG_BASE, +}; + +static const struct range gaudi2_pb_arc_sched_unsecured_regs[] = { + {mmARC_FARM_ARC0_AUX_RUN_HALT_REQ, mmARC_FARM_ARC0_AUX_RUN_HALT_ACK}, + {mmARC_FARM_ARC0_AUX_CLUSTER_NUM, mmARC_FARM_ARC0_AUX_WAKE_UP_EVENT}, + {mmARC_FARM_ARC0_AUX_ARC_RST_REQ, mmARC_FARM_ARC0_AUX_CID_OFFSET_7}, + {mmARC_FARM_ARC0_AUX_SCRATCHPAD_0, mmARC_FARM_ARC0_AUX_INFLIGHT_LBU_RD_CNT}, + {mmARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN, mmARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN}, + {mmARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN, mmARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN}, + {mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_0, mmARC_FARM_ARC0_AUX_DCCM_QUEUE_ALERT_MSG}, + {mmARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_CNT, mmARC_FARM_ARC0_AUX_QMAN_ARC_CQ_SHADOW_CI}, + {mmARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN}, + {mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_0, mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_63}, + {mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_STRONG_ORDER, mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_OVRD}, + {mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_0, mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_REG}, +}; + +static const u32 gaudi2_pb_xbar_mid[] = { + mmXBAR_MID_0_BASE, +}; + +static const u32 gaudi2_pb_xbar_mid_unsecured_regs[] = { + mmXBAR_MID_0_UPSCALE, + mmXBAR_MID_0_DOWN_CONV, + mmXBAR_MID_0_DOWN_CONV_LFSR_EN, + mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VLD, + mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VALUE, + mmXBAR_MID_0_DOWN_CONV_LFSR_CFG_POLY, +}; + +static const u32 gaudi2_pb_xbar_edge[] = { + mmXBAR_EDGE_0_BASE, +}; + +static const u32 gaudi2_pb_xbar_edge_unsecured_regs[] = { + mmXBAR_EDGE_0_UPSCALE, + mmXBAR_EDGE_0_DOWN_CONV, + mmXBAR_EDGE_0_DOWN_CONV_LFSR_EN, + mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VLD, + mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VALUE, + mmXBAR_EDGE_0_DOWN_CONV_LFSR_CFG_POLY, +}; + +static const u32 gaudi2_pb_nic0[] = { + mmNIC0_TMR_BASE, + mmNIC0_RXB_CORE_BASE, + mmNIC0_RXE0_BASE, + mmNIC0_RXE1_BASE, + mmNIC0_RXE0_AXUSER_AXUSER_CQ0_BASE, + mmNIC0_RXE1_AXUSER_AXUSER_CQ0_BASE, + mmNIC0_TXS0_BASE, + mmNIC0_TXS1_BASE, + mmNIC0_TXE0_BASE, + mmNIC0_TXE1_BASE, + mmNIC0_TXB_BASE, + mmNIC0_MSTR_IF_RR_SHRD_HBW_BASE, +}; + +static const u32 gaudi2_pb_nic0_qm_qpc[] = { + mmNIC0_QM0_BASE, + mmNIC0_QPC0_BASE, +}; + +static const u32 gaudi2_pb_nic0_qm_arc_aux0[] = { + mmNIC0_QM_ARC_AUX0_BASE, +}; + +static const struct range gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs[] = { + {mmNIC0_QM_ARC_AUX0_RUN_HALT_REQ, mmNIC0_QM_ARC_AUX0_RUN_HALT_ACK}, + {mmNIC0_QM_ARC_AUX0_CLUSTER_NUM, mmNIC0_QM_ARC_AUX0_WAKE_UP_EVENT}, + {mmNIC0_QM_ARC_AUX0_ARC_RST_REQ, mmNIC0_QM_ARC_AUX0_CID_OFFSET_7}, + {mmNIC0_QM_ARC_AUX0_SCRATCHPAD_0, mmNIC0_QM_ARC_AUX0_INFLIGHT_LBU_RD_CNT}, + {mmNIC0_QM_ARC_AUX0_LBU_EARLY_BRESP_EN, mmNIC0_QM_ARC_AUX0_LBU_EARLY_BRESP_EN}, + {mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_0, mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_ALERT_MSG}, + {mmNIC0_QM_ARC_AUX0_DCCM_Q_PUSH_FIFO_CNT, mmNIC0_QM_ARC_AUX0_QMAN_ARC_CQ_SHADOW_CI}, + {mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_WR_IF_CNT, mmNIC0_QM_ARC_AUX0_MME_ARC_UPPER_DCCM_EN}, +}; + +static const u32 gaudi2_pb_nic0_umr[] = { + mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE, + mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 1, /* UMR0_1 */ + mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 2, /* UMR0_2 */ + mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 3, /* UMR0_3 */ + mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 4, /* UMR0_4 */ + mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 5, /* UMR0_5 */ + mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 6, /* UMR0_6 */ + mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 7, /* UMR0_7 */ + mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 8, /* UMR0_8 */ + mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 9, /* UMR0_9 */ + mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 10, /* UMR0_10 */ + mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 11, /* UMR0_11 */ + mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 12, /* UMR0_12 */ + mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 13, /* UMR0_13 */ + mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 14, /* UMR0_14 */ +}; + +static const struct range gaudi2_pb_nic0_umr_unsecured_regs[] = { + {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32, + mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX}, + {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 1, /* UMR0_1 */ + mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 1}, + {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 2, /* UMR0_2 */ + mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 2}, + {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 3, /* UMR0_3 */ + mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 3}, + {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 4, /* UMR0_4 */ + mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 4}, + {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 5, /* UMR0_5 */ + mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 5}, + {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 6, /* UMR0_6 */ + mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 6}, + {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 7, /* UMR0_7 */ + mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 7}, + {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 8, /* UMR0_8 */ + mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 8}, + {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 9, /* UMR0_9 */ + mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 9}, + {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 10, /* UMR0_10 */ + mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 10}, + {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 11, /* UMR0_11 */ + mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 11}, + {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 12, /* UMR0_12 */ + mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 12}, + {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 13, /* UMR0_13 */ + mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 13}, + {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 14, /* UMR0_14 */ + mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 14}, +}; + +/* + * mmNIC0_QPC0_LINEAR_WQE_QPN and mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN are 32-bit + * registers and since the user writes in bulks of 64 bits we need to un-secure + * also the following 32 bits (that's why we added also the next 4 bytes to the + * table). In the RTL, as part of ECO (2874), writing to the next 4 bytes + * triggers a write to the SPECIAL_GLBL_SPARE register, hence it's must be + * unsecured as well. + */ +#define mmNIC0_QPC0_LINEAR_WQE_RSV (mmNIC0_QPC0_LINEAR_WQE_QPN + 4) +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_RSV (mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN + 4) +#define mmNIC0_QPC0_SPECIAL_GLBL_SPARE 0x541FF60 + +static const u32 gaudi2_pb_nic0_qm_qpc_unsecured_regs[] = { + mmNIC0_QPC0_LINEAR_WQE_STATIC_0, + mmNIC0_QPC0_LINEAR_WQE_STATIC_1, + mmNIC0_QPC0_LINEAR_WQE_STATIC_2, + mmNIC0_QPC0_LINEAR_WQE_STATIC_3, + mmNIC0_QPC0_LINEAR_WQE_STATIC_4, + mmNIC0_QPC0_LINEAR_WQE_STATIC_5, + mmNIC0_QPC0_LINEAR_WQE_STATIC_6, + mmNIC0_QPC0_LINEAR_WQE_STATIC_7, + mmNIC0_QPC0_LINEAR_WQE_STATIC_8, + mmNIC0_QPC0_LINEAR_WQE_STATIC_9, + mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_0, + mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_1, + mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_2, + mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_3, + mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_4, + mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_5, + mmNIC0_QPC0_LINEAR_WQE_QPN, + mmNIC0_QPC0_LINEAR_WQE_RSV, + mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_0, + mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_1, + mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_2, + mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_3, + mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_4, + mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_5, + mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_6, + mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_7, + mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_8, + mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_9, + mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_10, + mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_11, + mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_12, + mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_13, + mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_14, + mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_15, + mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_16, + mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_17, + mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_0, + mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_1, + mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_2, + mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_3, + mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_4, + mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_5, + mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN, + mmNIC0_QPC0_MULTI_STRIDE_WQE_RSV, + mmNIC0_QPC0_QMAN_DOORBELL, + mmNIC0_QPC0_QMAN_DOORBELL_QPN, + mmNIC0_QPC0_SPECIAL_GLBL_SPARE, + mmNIC0_QM0_CQ_CFG0_0, + mmNIC0_QM0_CQ_CFG0_1, + mmNIC0_QM0_CQ_CFG0_2, + mmNIC0_QM0_CQ_CFG0_3, + mmNIC0_QM0_CQ_CFG0_4, + mmNIC0_QM0_CP_FENCE0_RDATA_0, + mmNIC0_QM0_CP_FENCE0_RDATA_1, + mmNIC0_QM0_CP_FENCE0_RDATA_2, + mmNIC0_QM0_CP_FENCE0_RDATA_3, + mmNIC0_QM0_CP_FENCE0_RDATA_4, + mmNIC0_QM0_CP_FENCE1_RDATA_0, + mmNIC0_QM0_CP_FENCE1_RDATA_1, + mmNIC0_QM0_CP_FENCE1_RDATA_2, + mmNIC0_QM0_CP_FENCE1_RDATA_3, + mmNIC0_QM0_CP_FENCE1_RDATA_4, + mmNIC0_QM0_CP_FENCE2_RDATA_0, + mmNIC0_QM0_CP_FENCE2_RDATA_1, + mmNIC0_QM0_CP_FENCE2_RDATA_2, + mmNIC0_QM0_CP_FENCE2_RDATA_3, + mmNIC0_QM0_CP_FENCE2_RDATA_4, + mmNIC0_QM0_CP_FENCE3_RDATA_0, + mmNIC0_QM0_CP_FENCE3_RDATA_1, + mmNIC0_QM0_CP_FENCE3_RDATA_2, + mmNIC0_QM0_CP_FENCE3_RDATA_3, + mmNIC0_QM0_CP_FENCE3_RDATA_4, + mmNIC0_QM0_CP_FENCE0_CNT_0, + mmNIC0_QM0_CP_FENCE0_CNT_1, + mmNIC0_QM0_CP_FENCE0_CNT_2, + mmNIC0_QM0_CP_FENCE0_CNT_3, + mmNIC0_QM0_CP_FENCE0_CNT_4, + mmNIC0_QM0_CP_FENCE1_CNT_0, + mmNIC0_QM0_CP_FENCE1_CNT_1, + mmNIC0_QM0_CP_FENCE1_CNT_2, + mmNIC0_QM0_CP_FENCE1_CNT_3, + mmNIC0_QM0_CP_FENCE1_CNT_4, + mmNIC0_QM0_CP_FENCE2_CNT_0, + mmNIC0_QM0_CP_FENCE2_CNT_1, + mmNIC0_QM0_CP_FENCE2_CNT_2, + mmNIC0_QM0_CP_FENCE2_CNT_3, + mmNIC0_QM0_CP_FENCE2_CNT_4, + mmNIC0_QM0_CP_FENCE3_CNT_0, + mmNIC0_QM0_CP_FENCE3_CNT_1, + mmNIC0_QM0_CP_FENCE3_CNT_2, + mmNIC0_QM0_CP_FENCE3_CNT_3, + mmNIC0_QM0_CP_FENCE3_CNT_4, + mmNIC0_QM0_CQ_PTR_LO_0, + mmNIC0_QM0_CQ_PTR_HI_0, + mmNIC0_QM0_CQ_TSIZE_0, + mmNIC0_QM0_CQ_CTL_0, + mmNIC0_QM0_CQ_PTR_LO_1, + mmNIC0_QM0_CQ_PTR_HI_1, + mmNIC0_QM0_CQ_TSIZE_1, + mmNIC0_QM0_CQ_CTL_1, + mmNIC0_QM0_CQ_PTR_LO_2, + mmNIC0_QM0_CQ_PTR_HI_2, + mmNIC0_QM0_CQ_TSIZE_2, + mmNIC0_QM0_CQ_CTL_2, + mmNIC0_QM0_CQ_PTR_LO_3, + mmNIC0_QM0_CQ_PTR_HI_3, + mmNIC0_QM0_CQ_TSIZE_3, + mmNIC0_QM0_CQ_CTL_3, + mmNIC0_QM0_CQ_PTR_LO_4, + mmNIC0_QM0_CQ_PTR_HI_4, + mmNIC0_QM0_CQ_TSIZE_4, + mmNIC0_QM0_CQ_CTL_4, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR0_BASE, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR0_BASE + 4, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR1_BASE, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR1_BASE + 4, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR2_BASE, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR2_BASE + 4, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR3_BASE, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR3_BASE + 4, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR4_BASE, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR4_BASE + 4, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR5_BASE, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR5_BASE + 4, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR6_BASE, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR6_BASE + 4, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR7_BASE, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR7_BASE + 4, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR8_BASE, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR8_BASE + 4, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR9_BASE, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR9_BASE + 4, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR10_BASE, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR10_BASE + 4, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR11_BASE, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR11_BASE + 4, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR12_BASE, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR12_BASE + 4, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR13_BASE, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR13_BASE + 4, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR14_BASE, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR14_BASE + 4, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR15_BASE, + mmNIC0_QM0_QMAN_WR64_BASE_ADDR15_BASE + 4, + mmNIC0_QM0_ARC_CQ_PTR_LO, + mmNIC0_QM0_ARC_CQ_PTR_LO_STS, + mmNIC0_QM0_ARC_CQ_PTR_HI, + mmNIC0_QM0_ARC_CQ_PTR_HI_STS, + mmNIC0_QM0_ARB_CFG_0, + mmNIC0_QM0_ARB_MST_QUIET_PER, + mmNIC0_QM0_ARB_CHOICE_Q_PUSH, + mmNIC0_QM0_ARB_WRR_WEIGHT_0, + mmNIC0_QM0_ARB_WRR_WEIGHT_1, + mmNIC0_QM0_ARB_WRR_WEIGHT_2, + mmNIC0_QM0_ARB_WRR_WEIGHT_3, + mmNIC0_QM0_ARB_BASE_LO, + mmNIC0_QM0_ARB_BASE_HI, + mmNIC0_QM0_ARB_MST_SLAVE_EN, + mmNIC0_QM0_ARB_MST_SLAVE_EN_1, + mmNIC0_QM0_ARB_MST_CRED_INC, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_0, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_1, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_2, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_3, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_4, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_5, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_6, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_7, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_8, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_9, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_10, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_11, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_12, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_13, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_14, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_15, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_16, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_17, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_18, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_19, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_20, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_21, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_22, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_23, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_24, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_25, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_26, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_27, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_28, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_29, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_30, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_31, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_32, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_33, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_34, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_35, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_36, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_37, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_38, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_39, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_40, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_41, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_42, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_43, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_44, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_45, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_46, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_47, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_48, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_49, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_50, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_51, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_52, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_53, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_54, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_55, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_56, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_57, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_58, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_59, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_60, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_61, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_62, + mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_63, + mmNIC0_QM0_ARB_SLV_ID, + mmNIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST, + mmNIC0_QM0_ARC_CQ_CFG0, + mmNIC0_QM0_CQ_IFIFO_CI_0, + mmNIC0_QM0_CQ_IFIFO_CI_1, + mmNIC0_QM0_CQ_IFIFO_CI_2, + mmNIC0_QM0_CQ_IFIFO_CI_3, + mmNIC0_QM0_CQ_IFIFO_CI_4, + mmNIC0_QM0_ARC_CQ_IFIFO_CI, + mmNIC0_QM0_CQ_CTL_CI_0, + mmNIC0_QM0_CQ_CTL_CI_1, + mmNIC0_QM0_CQ_CTL_CI_2, + mmNIC0_QM0_CQ_CTL_CI_3, + mmNIC0_QM0_CQ_CTL_CI_4, + mmNIC0_QM0_ARC_CQ_CTL_CI, + mmNIC0_QM0_ARC_CQ_TSIZE, + mmNIC0_QM0_ARC_CQ_CTL, + mmNIC0_QM0_CP_SWITCH_WD_SET, + mmNIC0_QM0_CP_EXT_SWITCH, + mmNIC0_QM0_CP_PRED_0, + mmNIC0_QM0_CP_PRED_1, + mmNIC0_QM0_CP_PRED_2, + mmNIC0_QM0_CP_PRED_3, + mmNIC0_QM0_CP_PRED_4, + mmNIC0_QM0_CP_PRED_UPEN_0, + mmNIC0_QM0_CP_PRED_UPEN_1, + mmNIC0_QM0_CP_PRED_UPEN_2, + mmNIC0_QM0_CP_PRED_UPEN_3, + mmNIC0_QM0_CP_PRED_UPEN_4, + mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0, + mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_1, + mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_2, + mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_3, + mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_4, + mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0, + mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_1, + mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_2, + mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_3, + mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_4, + mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0, + mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_1, + mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_2, + mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_3, + mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_4, + mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0, + mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_1, + mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_2, + mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_3, + mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_4, + mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0, + mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_1, + mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2, + mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_3, + mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_4, + mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0, + mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_1, + mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_2, + mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_3, + mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_4, + mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0, + mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_1, + mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_2, + mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_3, + mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_4, + mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0, + mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_1, + mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_2, + mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_3, + mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_4, + mmNIC0_QM0_ARC_CQ_IFIFO_MSG_BASE_LO, + mmNIC0_QM0_ARC_CQ_CTL_MSG_BASE_LO, + mmNIC0_QM0_CQ_IFIFO_MSG_BASE_LO, + mmNIC0_QM0_CQ_CTL_MSG_BASE_LO +}; + +static const u32 gaudi2_pb_rot0[] = { + mmROT0_BASE, + mmROT0_MSTR_IF_RR_SHRD_HBW_BASE, + mmROT0_QM_BASE, +}; + +static const u32 gaudi2_pb_rot0_arc[] = { + mmROT0_QM_ARC_AUX_BASE +}; + +static const struct range gaudi2_pb_rot0_arc_unsecured_regs[] = { + {mmROT0_QM_ARC_AUX_RUN_HALT_REQ, mmROT0_QM_ARC_AUX_RUN_HALT_ACK}, + {mmROT0_QM_ARC_AUX_CLUSTER_NUM, mmROT0_QM_ARC_AUX_WAKE_UP_EVENT}, + {mmROT0_QM_ARC_AUX_ARC_RST_REQ, mmROT0_QM_ARC_AUX_CID_OFFSET_7}, + {mmROT0_QM_ARC_AUX_SCRATCHPAD_0, mmROT0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT}, + {mmROT0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmROT0_QM_ARC_AUX_CBU_EARLY_BRESP_EN}, + {mmROT0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmROT0_QM_ARC_AUX_LBU_EARLY_BRESP_EN}, + {mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, mmROT0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG}, + {mmROT0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, mmROT0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI}, + {mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmROT0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN}, +}; + +static const u32 gaudi2_pb_rot0_unsecured_regs[] = { + mmROT0_QM_CQ_CFG0_0, + mmROT0_QM_CQ_CFG0_1, + mmROT0_QM_CQ_CFG0_2, + mmROT0_QM_CQ_CFG0_3, + mmROT0_QM_CQ_CFG0_4, + mmROT0_QM_CP_FENCE0_RDATA_0, + mmROT0_QM_CP_FENCE0_RDATA_1, + mmROT0_QM_CP_FENCE0_RDATA_2, + mmROT0_QM_CP_FENCE0_RDATA_3, + mmROT0_QM_CP_FENCE0_RDATA_4, + mmROT0_QM_CP_FENCE1_RDATA_0, + mmROT0_QM_CP_FENCE1_RDATA_1, + mmROT0_QM_CP_FENCE1_RDATA_2, + mmROT0_QM_CP_FENCE1_RDATA_3, + mmROT0_QM_CP_FENCE1_RDATA_4, + mmROT0_QM_CP_FENCE2_RDATA_0, + mmROT0_QM_CP_FENCE2_RDATA_1, + mmROT0_QM_CP_FENCE2_RDATA_2, + mmROT0_QM_CP_FENCE2_RDATA_3, + mmROT0_QM_CP_FENCE2_RDATA_4, + mmROT0_QM_CP_FENCE3_RDATA_0, + mmROT0_QM_CP_FENCE3_RDATA_1, + mmROT0_QM_CP_FENCE3_RDATA_2, + mmROT0_QM_CP_FENCE3_RDATA_3, + mmROT0_QM_CP_FENCE3_RDATA_4, + mmROT0_QM_CP_FENCE0_CNT_0, + mmROT0_QM_CP_FENCE0_CNT_1, + mmROT0_QM_CP_FENCE0_CNT_2, + mmROT0_QM_CP_FENCE0_CNT_3, + mmROT0_QM_CP_FENCE0_CNT_4, + mmROT0_QM_CP_FENCE1_CNT_0, + mmROT0_QM_CP_FENCE1_CNT_1, + mmROT0_QM_CP_FENCE1_CNT_2, + mmROT0_QM_CP_FENCE1_CNT_3, + mmROT0_QM_CP_FENCE1_CNT_4, + mmROT0_QM_CP_FENCE2_CNT_0, + mmROT0_QM_CP_FENCE2_CNT_1, + mmROT0_QM_CP_FENCE2_CNT_2, + mmROT0_QM_CP_FENCE2_CNT_3, + mmROT0_QM_CP_FENCE2_CNT_4, + mmROT0_QM_CP_FENCE3_CNT_0, + mmROT0_QM_CP_FENCE3_CNT_1, + mmROT0_QM_CP_FENCE3_CNT_2, + mmROT0_QM_CP_FENCE3_CNT_3, + mmROT0_QM_CP_FENCE3_CNT_4, + mmROT0_QM_CQ_PTR_LO_0, + mmROT0_QM_CQ_PTR_HI_0, + mmROT0_QM_CQ_TSIZE_0, + mmROT0_QM_CQ_CTL_0, + mmROT0_QM_CQ_PTR_LO_1, + mmROT0_QM_CQ_PTR_HI_1, + mmROT0_QM_CQ_TSIZE_1, + mmROT0_QM_CQ_CTL_1, + mmROT0_QM_CQ_PTR_LO_2, + mmROT0_QM_CQ_PTR_HI_2, + mmROT0_QM_CQ_TSIZE_2, + mmROT0_QM_CQ_CTL_2, + mmROT0_QM_CQ_PTR_LO_3, + mmROT0_QM_CQ_PTR_HI_3, + mmROT0_QM_CQ_TSIZE_3, + mmROT0_QM_CQ_CTL_3, + mmROT0_QM_CQ_PTR_LO_4, + mmROT0_QM_CQ_PTR_HI_4, + mmROT0_QM_CQ_TSIZE_4, + mmROT0_QM_CQ_CTL_4, + mmROT0_QM_QMAN_WR64_BASE_ADDR0_BASE, + mmROT0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4, + mmROT0_QM_QMAN_WR64_BASE_ADDR1_BASE, + mmROT0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4, + mmROT0_QM_QMAN_WR64_BASE_ADDR2_BASE, + mmROT0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4, + mmROT0_QM_QMAN_WR64_BASE_ADDR3_BASE, + mmROT0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4, + mmROT0_QM_QMAN_WR64_BASE_ADDR4_BASE, + mmROT0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4, + mmROT0_QM_QMAN_WR64_BASE_ADDR5_BASE, + mmROT0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4, + mmROT0_QM_QMAN_WR64_BASE_ADDR6_BASE, + mmROT0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4, + mmROT0_QM_QMAN_WR64_BASE_ADDR7_BASE, + mmROT0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4, + mmROT0_QM_QMAN_WR64_BASE_ADDR8_BASE, + mmROT0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4, + mmROT0_QM_QMAN_WR64_BASE_ADDR9_BASE, + mmROT0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4, + mmROT0_QM_QMAN_WR64_BASE_ADDR10_BASE, + mmROT0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4, + mmROT0_QM_QMAN_WR64_BASE_ADDR11_BASE, + mmROT0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4, + mmROT0_QM_QMAN_WR64_BASE_ADDR12_BASE, + mmROT0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4, + mmROT0_QM_QMAN_WR64_BASE_ADDR13_BASE, + mmROT0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4, + mmROT0_QM_QMAN_WR64_BASE_ADDR14_BASE, + mmROT0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4, + mmROT0_QM_QMAN_WR64_BASE_ADDR15_BASE, + mmROT0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4, + mmROT0_QM_ARC_CQ_PTR_LO, + mmROT0_QM_ARC_CQ_PTR_LO_STS, + mmROT0_QM_ARC_CQ_PTR_HI, + mmROT0_QM_ARC_CQ_PTR_HI_STS, + mmROT0_QM_ARB_CFG_0, + mmROT0_QM_ARB_MST_QUIET_PER, + mmROT0_QM_ARB_CHOICE_Q_PUSH, + mmROT0_QM_ARB_WRR_WEIGHT_0, + mmROT0_QM_ARB_WRR_WEIGHT_1, + mmROT0_QM_ARB_WRR_WEIGHT_2, + mmROT0_QM_ARB_WRR_WEIGHT_3, + mmROT0_QM_ARB_BASE_LO, + mmROT0_QM_ARB_BASE_HI, + mmROT0_QM_ARB_MST_SLAVE_EN, + mmROT0_QM_ARB_MST_SLAVE_EN_1, + mmROT0_QM_ARB_MST_CRED_INC, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_0, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_1, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_2, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_3, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_4, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_5, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_6, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_7, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_8, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_9, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_10, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_11, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_12, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_13, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_14, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_15, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_16, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_17, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_18, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_19, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_20, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_21, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_22, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_23, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_24, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_25, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_26, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_27, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_28, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_29, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_30, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_31, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_32, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_33, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_34, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_35, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_36, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_37, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_38, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_39, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_40, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_41, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_42, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_43, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_44, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_45, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_46, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_47, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_48, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_49, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_50, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_51, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_52, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_53, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_54, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_55, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_56, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_57, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_58, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_59, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_60, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_61, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_62, + mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_63, + mmROT0_QM_ARB_SLV_ID, + mmROT0_QM_ARB_SLV_MASTER_INC_CRED_OFST, + mmROT0_QM_ARC_CQ_CFG0, + mmROT0_QM_CQ_IFIFO_CI_0, + mmROT0_QM_CQ_IFIFO_CI_1, + mmROT0_QM_CQ_IFIFO_CI_2, + mmROT0_QM_CQ_IFIFO_CI_3, + mmROT0_QM_CQ_IFIFO_CI_4, + mmROT0_QM_ARC_CQ_IFIFO_CI, + mmROT0_QM_CQ_CTL_CI_0, + mmROT0_QM_CQ_CTL_CI_1, + mmROT0_QM_CQ_CTL_CI_2, + mmROT0_QM_CQ_CTL_CI_3, + mmROT0_QM_CQ_CTL_CI_4, + mmROT0_QM_ARC_CQ_CTL_CI, + mmROT0_QM_ARC_CQ_TSIZE, + mmROT0_QM_ARC_CQ_CTL, + mmROT0_QM_CP_SWITCH_WD_SET, + mmROT0_QM_CP_EXT_SWITCH, + mmROT0_QM_CP_PRED_0, + mmROT0_QM_CP_PRED_1, + mmROT0_QM_CP_PRED_2, + mmROT0_QM_CP_PRED_3, + mmROT0_QM_CP_PRED_4, + mmROT0_QM_CP_PRED_UPEN_0, + mmROT0_QM_CP_PRED_UPEN_1, + mmROT0_QM_CP_PRED_UPEN_2, + mmROT0_QM_CP_PRED_UPEN_3, + mmROT0_QM_CP_PRED_UPEN_4, + mmROT0_QM_CP_MSG_BASE0_ADDR_LO_0, + mmROT0_QM_CP_MSG_BASE0_ADDR_LO_1, + mmROT0_QM_CP_MSG_BASE0_ADDR_LO_2, + mmROT0_QM_CP_MSG_BASE0_ADDR_LO_3, + mmROT0_QM_CP_MSG_BASE0_ADDR_LO_4, + mmROT0_QM_CP_MSG_BASE0_ADDR_HI_0, + mmROT0_QM_CP_MSG_BASE0_ADDR_HI_1, + mmROT0_QM_CP_MSG_BASE0_ADDR_HI_2, + mmROT0_QM_CP_MSG_BASE0_ADDR_HI_3, + mmROT0_QM_CP_MSG_BASE0_ADDR_HI_4, + mmROT0_QM_CP_MSG_BASE1_ADDR_LO_0, + mmROT0_QM_CP_MSG_BASE1_ADDR_LO_1, + mmROT0_QM_CP_MSG_BASE1_ADDR_LO_2, + mmROT0_QM_CP_MSG_BASE1_ADDR_LO_3, + mmROT0_QM_CP_MSG_BASE1_ADDR_LO_4, + mmROT0_QM_CP_MSG_BASE1_ADDR_HI_0, + mmROT0_QM_CP_MSG_BASE1_ADDR_HI_1, + mmROT0_QM_CP_MSG_BASE1_ADDR_HI_2, + mmROT0_QM_CP_MSG_BASE1_ADDR_HI_3, + mmROT0_QM_CP_MSG_BASE1_ADDR_HI_4, + mmROT0_QM_CP_MSG_BASE2_ADDR_LO_0, + mmROT0_QM_CP_MSG_BASE2_ADDR_LO_1, + mmROT0_QM_CP_MSG_BASE2_ADDR_LO_2, + mmROT0_QM_CP_MSG_BASE2_ADDR_LO_3, + mmROT0_QM_CP_MSG_BASE2_ADDR_LO_4, + mmROT0_QM_CP_MSG_BASE2_ADDR_HI_0, + mmROT0_QM_CP_MSG_BASE2_ADDR_HI_1, + mmROT0_QM_CP_MSG_BASE2_ADDR_HI_2, + mmROT0_QM_CP_MSG_BASE2_ADDR_HI_3, + mmROT0_QM_CP_MSG_BASE2_ADDR_HI_4, + mmROT0_QM_CP_MSG_BASE3_ADDR_LO_0, + mmROT0_QM_CP_MSG_BASE3_ADDR_LO_1, + mmROT0_QM_CP_MSG_BASE3_ADDR_LO_2, + mmROT0_QM_CP_MSG_BASE3_ADDR_LO_3, + mmROT0_QM_CP_MSG_BASE3_ADDR_LO_4, + mmROT0_QM_CP_MSG_BASE3_ADDR_HI_0, + mmROT0_QM_CP_MSG_BASE3_ADDR_HI_1, + mmROT0_QM_CP_MSG_BASE3_ADDR_HI_2, + mmROT0_QM_CP_MSG_BASE3_ADDR_HI_3, + mmROT0_QM_CP_MSG_BASE3_ADDR_HI_4, + mmROT0_QM_ARC_CQ_IFIFO_MSG_BASE_LO, + mmROT0_QM_ARC_CQ_CTL_MSG_BASE_LO, + mmROT0_QM_CQ_IFIFO_MSG_BASE_LO, + mmROT0_QM_CQ_CTL_MSG_BASE_LO, + mmROT0_DESC_CONTEXT_ID, + mmROT0_DESC_IN_IMG_START_ADDR_L, + mmROT0_DESC_IN_IMG_START_ADDR_H, + mmROT0_DESC_OUT_IMG_START_ADDR_L, + mmROT0_DESC_OUT_IMG_START_ADDR_H, + mmROT0_DESC_CFG, + mmROT0_DESC_IM_READ_SLOPE, + mmROT0_DESC_SIN_D, + mmROT0_DESC_COS_D, + mmROT0_DESC_IN_IMG, + mmROT0_DESC_IN_STRIDE, + mmROT0_DESC_IN_STRIPE, + mmROT0_DESC_IN_CENTER, + mmROT0_DESC_OUT_IMG, + mmROT0_DESC_OUT_STRIDE, + mmROT0_DESC_OUT_STRIPE, + mmROT0_DESC_OUT_CENTER, + mmROT0_DESC_BACKGROUND, + mmROT0_DESC_CPL_MSG_EN, + mmROT0_DESC_IDLE_STATE, + mmROT0_DESC_CPL_MSG_ADDR, + mmROT0_DESC_CPL_MSG_DATA, + mmROT0_DESC_X_I_START_OFFSET, + mmROT0_DESC_X_I_START_OFFSET_FLIP, + mmROT0_DESC_X_I_FIRST, + mmROT0_DESC_Y_I_FIRST, + mmROT0_DESC_Y_I, + mmROT0_DESC_OUT_STRIPE_SIZE, + mmROT0_DESC_RSB_CFG_0, + mmROT0_DESC_RSB_PAD_VAL, + mmROT0_DESC_OWM_CFG, + mmROT0_DESC_CTRL_CFG, + mmROT0_DESC_PIXEL_PAD, + mmROT0_DESC_PREC_SHIFT, + mmROT0_DESC_MAX_VAL, + mmROT0_DESC_A0_M11, + mmROT0_DESC_A1_M12, + mmROT0_DESC_A2, + mmROT0_DESC_B0_M21, + mmROT0_DESC_B1_M22, + mmROT0_DESC_B2, + mmROT0_DESC_C0, + mmROT0_DESC_C1, + mmROT0_DESC_C2, + mmROT0_DESC_D0, + mmROT0_DESC_D1, + mmROT0_DESC_D2, + mmROT0_DESC_INV_PROC_SIZE_M_1, + mmROT0_DESC_MESH_IMG_START_ADDR_L, + mmROT0_DESC_MESH_IMG_START_ADDR_H, + mmROT0_DESC_MESH_IMG, + mmROT0_DESC_MESH_STRIDE, + mmROT0_DESC_MESH_STRIPE, + mmROT0_DESC_MESH_CTRL, + mmROT0_DESC_MESH_GH, + mmROT0_DESC_MESH_GV, + mmROT0_DESC_MRSB_CFG_0, + mmROT0_DESC_MRSB_PAD_VAL, + mmROT0_DESC_BUF_CFG, + mmROT0_DESC_CID_OFFSET, + mmROT0_DESC_PUSH_DESC +}; + +static const u32 gaudi2_pb_psoc_global_conf[] = { + mmPSOC_GLOBAL_CONF_BASE +}; + +static const u32 gaudi2_pb_psoc[] = { + mmPSOC_EFUSE_BASE, + mmPSOC_BTL_BASE, + mmPSOC_CS_TRACE_BASE, + mmPSOC_DFT_EFUSE_BASE, + mmPSOC_PID_BASE, + mmPSOC_ARC0_CFG_BASE, + mmPSOC_ARC0_MSTR_IF_RR_SHRD_HBW_BASE, + mmPSOC_ARC0_AUX_BASE, + mmPSOC_ARC1_CFG_BASE, + mmPSOC_ARC1_MSTR_IF_RR_SHRD_HBW_BASE, + mmPSOC_ARC1_AUX_BASE, + mmJT_MSTR_IF_RR_SHRD_HBW_BASE, + mmSMI_MSTR_IF_RR_SHRD_HBW_BASE, + mmI2C_S_MSTR_IF_RR_SHRD_HBW_BASE, + mmPSOC_SVID0_BASE, + mmPSOC_SVID1_BASE, + mmPSOC_SVID2_BASE, + mmPSOC_AVS0_BASE, + mmPSOC_AVS1_BASE, + mmPSOC_AVS2_BASE, + mmPSOC_PWM0_BASE, + mmPSOC_PWM1_BASE, + mmPSOC_MSTR_IF_RR_SHRD_HBW_BASE, +}; + +static const u32 gaudi2_pb_pmmu[] = { + mmPMMU_HBW_MMU_BASE, + mmPMMU_HBW_STLB_BASE, + mmPMMU_HBW_MSTR_IF_RR_SHRD_HBW_BASE, + mmPMMU_PIF_BASE, +}; + +static const u32 gaudi2_pb_psoc_pll[] = { + mmPSOC_MME_PLL_CTRL_BASE, + mmPSOC_CPU_PLL_CTRL_BASE, + mmPSOC_VID_PLL_CTRL_BASE +}; + +static const u32 gaudi2_pb_pmmu_pll[] = { + mmPMMU_MME_PLL_CTRL_BASE, + mmPMMU_VID_PLL_CTRL_BASE +}; + +static const u32 gaudi2_pb_xbar_pll[] = { + mmDCORE0_XBAR_DMA_PLL_CTRL_BASE, + mmDCORE0_XBAR_MMU_PLL_CTRL_BASE, + mmDCORE0_XBAR_IF_PLL_CTRL_BASE, + mmDCORE0_XBAR_MESH_PLL_CTRL_BASE, + mmDCORE1_XBAR_DMA_PLL_CTRL_BASE, + mmDCORE1_XBAR_MMU_PLL_CTRL_BASE, + mmDCORE1_XBAR_IF_PLL_CTRL_BASE, + mmDCORE1_XBAR_MESH_PLL_CTRL_BASE, + mmDCORE1_XBAR_HBM_PLL_CTRL_BASE, + mmDCORE2_XBAR_DMA_PLL_CTRL_BASE, + mmDCORE2_XBAR_MMU_PLL_CTRL_BASE, + mmDCORE2_XBAR_IF_PLL_CTRL_BASE, + mmDCORE2_XBAR_BANK_PLL_CTRL_BASE, + mmDCORE2_XBAR_HBM_PLL_CTRL_BASE, + mmDCORE3_XBAR_DMA_PLL_CTRL_BASE, + mmDCORE3_XBAR_MMU_PLL_CTRL_BASE, + mmDCORE3_XBAR_IF_PLL_CTRL_BASE, + mmDCORE3_XBAR_BANK_PLL_CTRL_BASE +}; + +static const u32 gaudi2_pb_xft_pll[] = { + mmDCORE0_HBM_PLL_CTRL_BASE, + mmDCORE0_TPC_PLL_CTRL_BASE, + mmDCORE0_PCI_PLL_CTRL_BASE, + mmDCORE1_HBM_PLL_CTRL_BASE, + mmDCORE1_TPC_PLL_CTRL_BASE, + mmDCORE1_NIC_PLL_CTRL_BASE, + mmDCORE2_HBM_PLL_CTRL_BASE, + mmDCORE2_TPC_PLL_CTRL_BASE, + mmDCORE3_HBM_PLL_CTRL_BASE, + mmDCORE3_TPC_PLL_CTRL_BASE, + mmDCORE3_NIC_PLL_CTRL_BASE, +}; + +static const u32 gaudi2_pb_pcie[] = { + mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_BASE, + mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_BASE, + mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE, + mmPCIE_WRAP_BASE, +}; + +static const u32 gaudi2_pb_thermal_sensor0[] = { + mmDCORE0_XFT_BASE, + mmDCORE0_TSTDVS_BASE, +}; + +static const u32 gaudi2_pb_hbm[] = { + mmHBM0_MC0_BASE, + mmHBM0_MC1_BASE, +}; + +static const u32 gaudi2_pb_mme_qm_arc_acp_eng[] = { + mmDCORE0_MME_QM_ARC_ACP_ENG_BASE, +}; + +static const struct range gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs[] = { + {mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_0, mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_REG}, +}; + +struct gaudi2_tpc_pb_data { + struct hl_block_glbl_sec *glbl_sec; + u32 block_array_size; +}; + +static void gaudi2_config_tpcs_glbl_sec(struct hl_device *hdev, int dcore, int inst, u32 offset, + void *data) +{ + struct gaudi2_tpc_pb_data *pb_data = (struct gaudi2_tpc_pb_data *)data; + + hl_config_glbl_sec(hdev, gaudi2_pb_dcr0_tpc0, pb_data->glbl_sec, + offset, pb_data->block_array_size); +} + +static int gaudi2_init_pb_tpc(struct hl_device *hdev) +{ + u32 stride, kernel_tensor_stride, qm_tensor_stride, block_array_size; + struct gaudi2_tpc_pb_data tpc_pb_data; + struct hl_block_glbl_sec *glbl_sec; + struct iterate_module_ctx tpc_iter; + int i; + + block_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0); + + glbl_sec = kcalloc(block_array_size, sizeof(struct hl_block_glbl_sec), GFP_KERNEL); + if (!glbl_sec) + return -ENOMEM; + + kernel_tensor_stride = mmDCORE0_TPC0_CFG_KERNEL_TENSOR_1_BASE - + mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE; + qm_tensor_stride = mmDCORE0_TPC0_CFG_QM_TENSOR_1_BASE - mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE; + + hl_secure_block(hdev, glbl_sec, block_array_size); + hl_unsecure_registers(hdev, gaudi2_pb_dcr0_tpc0_unsecured_regs, + ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_unsecured_regs), + 0, gaudi2_pb_dcr0_tpc0, glbl_sec, + block_array_size); + + /* Unsecure all TPC kernel tensors */ + for (i = 0 ; i < TPC_NUM_OF_KERNEL_TENSORS ; i++) + hl_unsecure_registers(hdev, + gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs, + ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs), + i * kernel_tensor_stride, gaudi2_pb_dcr0_tpc0, + glbl_sec, block_array_size); + + /* Unsecure all TPC QM tensors */ + for (i = 0 ; i < TPC_NUM_OF_QM_TENSORS ; i++) + hl_unsecure_registers(hdev, + gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs, + ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs), + i * qm_tensor_stride, + gaudi2_pb_dcr0_tpc0, glbl_sec, block_array_size); + + /* unsecure all 32 TPC QM SRF regs */ + stride = mmDCORE0_TPC0_CFG_QM_SRF_1 - mmDCORE0_TPC0_CFG_QM_SRF_0; + for (i = 0 ; i < 32 ; i++) + hl_unsecure_register(hdev, mmDCORE0_TPC0_CFG_QM_SRF_0, + i * stride, gaudi2_pb_dcr0_tpc0, glbl_sec, + block_array_size); + + /* unsecure the 4 TPC LOCK VALUE regs */ + stride = mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_1 - mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0; + for (i = 0 ; i < 4 ; i++) + hl_unsecure_register(hdev, mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0, + i * stride, gaudi2_pb_dcr0_tpc0, glbl_sec, + block_array_size); + + /* prepare data for TPC iterator */ + tpc_pb_data.glbl_sec = glbl_sec; + tpc_pb_data.block_array_size = block_array_size; + tpc_iter.fn = &gaudi2_config_tpcs_glbl_sec; + tpc_iter.data = &tpc_pb_data; + gaudi2_iterate_tpcs(hdev, &tpc_iter); + + kfree(glbl_sec); + + return 0; +} + +struct gaudi2_tpc_arc_pb_data { + u32 unsecured_regs_arr_size; + u32 arc_regs_arr_size; + int rc; +}; + +static void gaudi2_config_tpcs_pb_ranges(struct hl_device *hdev, int dcore, int inst, u32 offset, + void *data) +{ + struct gaudi2_tpc_arc_pb_data *pb_data = (struct gaudi2_tpc_arc_pb_data *)data; + + pb_data->rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, 1, + offset, gaudi2_pb_dcr0_tpc0_arc, + pb_data->arc_regs_arr_size, + gaudi2_pb_dcr0_tpc0_arc_unsecured_regs, + pb_data->unsecured_regs_arr_size); +} + +static int gaudi2_init_pb_tpc_arc(struct hl_device *hdev) +{ + struct gaudi2_tpc_arc_pb_data tpc_arc_pb_data; + struct iterate_module_ctx tpc_iter; + + tpc_arc_pb_data.arc_regs_arr_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc); + tpc_arc_pb_data.unsecured_regs_arr_size = + ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc_unsecured_regs); + tpc_arc_pb_data.rc = 0; + tpc_iter.fn = &gaudi2_config_tpcs_pb_ranges; + tpc_iter.data = &tpc_arc_pb_data; + gaudi2_iterate_tpcs(hdev, &tpc_iter); + + return tpc_arc_pb_data.rc; +} + +static int gaudi2_init_pb_sm_objs(struct hl_device *hdev) +{ + int i, j, glbl_sec_array_len = gaudi2_pb_dcr0_sm_objs.glbl_sec_length; + u32 sec_entry, *sec_array, array_base, first_sob, first_mon; + + array_base = gaudi2_pb_dcr0_sm_objs.mm_block_base_addr + + gaudi2_pb_dcr0_sm_objs.glbl_sec_offset; + + sec_array = kcalloc(glbl_sec_array_len, sizeof(u32), GFP_KERNEL); + if (!sec_array) + return -ENOMEM; + + first_sob = GAUDI2_RESERVED_SOB_NUMBER; + first_mon = GAUDI2_RESERVED_MON_NUMBER; + + /* 8192 SOB_OBJs skipping first GAUDI2_MAX_PENDING_CS of them */ + for (j = i = first_sob ; i < DCORE_NUM_OF_SOB ; i++, j++) + UNSET_GLBL_SEC_BIT(sec_array, j); + + /* 2048 MON_PAY ADDR_L skipping first GAUDI2_MAX_PENDING_CS of them */ + for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++) + UNSET_GLBL_SEC_BIT(sec_array, j); + + /* 2048 MON_PAY ADDR_H skipping first GAUDI2_MAX_PENDING_CS of them */ + for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++) + UNSET_GLBL_SEC_BIT(sec_array, j); + + /* 2048 MON_PAY DATA skipping first GAUDI2_MAX_PENDING_CS of them */ + for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++) + UNSET_GLBL_SEC_BIT(sec_array, j); + + /* 2048 MON_ARM skipping first GAUDI2_MAX_PENDING_CS of them */ + for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++) + UNSET_GLBL_SEC_BIT(sec_array, j); + + /* 2048 MON_CONFIG skipping first GAUDI2_MAX_PENDING_CS of them */ + for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++) + UNSET_GLBL_SEC_BIT(sec_array, j); + + /* 2048 MON_STATUS skipping first GAUDI2_MAX_PENDING_CS of them */ + for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++) + UNSET_GLBL_SEC_BIT(sec_array, j); + + /* Unsecure selected Dcore0 registers */ + for (i = 0 ; i < glbl_sec_array_len ; i++) { + sec_entry = array_base + i * sizeof(u32); + WREG32(sec_entry, sec_array[i]); + } + + /* Unsecure Dcore1 - Dcore3 registers */ + memset(sec_array, -1, glbl_sec_array_len * sizeof(u32)); + + for (i = 1 ; i < NUM_OF_DCORES ; i++) { + for (j = 0 ; j < glbl_sec_array_len ; j++) { + sec_entry = DCORE_OFFSET * i + array_base + j * sizeof(u32); + WREG32(sec_entry, sec_array[j]); + } + } + + kfree(sec_array); + + return 0; +} + +static void gaudi2_write_lbw_range_register(struct hl_device *hdev, u64 base, void *data) +{ + u32 reg_min_offset, reg_max_offset, write_min, write_max; + struct rr_config *rr_cfg = (struct rr_config *) data; + + switch (rr_cfg->type) { + case RR_TYPE_SHORT: + reg_min_offset = RR_LBW_SEC_RANGE_MIN_SHORT_0_OFFSET; + reg_max_offset = RR_LBW_SEC_RANGE_MAX_SHORT_0_OFFSET; + break; + + case RR_TYPE_LONG: + reg_min_offset = RR_LBW_SEC_RANGE_MIN_0_OFFSET; + reg_max_offset = RR_LBW_SEC_RANGE_MAX_0_OFFSET; + break; + + case RR_TYPE_SHORT_PRIV: + reg_min_offset = RR_LBW_PRIV_RANGE_MIN_SHORT_0_OFFSET; + reg_max_offset = RR_LBW_PRIV_RANGE_MAX_SHORT_0_OFFSET; + break; + + case RR_TYPE_LONG_PRIV: + reg_min_offset = RR_LBW_PRIV_RANGE_MIN_0_OFFSET; + reg_max_offset = RR_LBW_PRIV_RANGE_MAX_0_OFFSET; + break; + + default: + dev_err(hdev->dev, "Invalid LBW RR type %u\n", rr_cfg->type); + return; + } + + reg_min_offset += rr_cfg->index * sizeof(u32); + reg_max_offset += rr_cfg->index * sizeof(u32); + + if (rr_cfg->type == RR_TYPE_SHORT || rr_cfg->type == RR_TYPE_SHORT_PRIV) { + write_min = FIELD_GET(RR_LBW_SHORT_MASK, lower_32_bits(rr_cfg->min)); + write_max = FIELD_GET(RR_LBW_SHORT_MASK, lower_32_bits(rr_cfg->max)); + + } else { + write_min = FIELD_GET(RR_LBW_LONG_MASK, lower_32_bits(rr_cfg->min)); + write_max = FIELD_GET(RR_LBW_LONG_MASK, lower_32_bits(rr_cfg->max)); + } + + /* Configure LBW RR: + * Both RR types start blocking from base address 0x1000007FF8000000 + * SHORT RRs address bits [26:12] + * LONG RRs address bits [26:0] + */ + WREG32(base + reg_min_offset, write_min); + WREG32(base + reg_max_offset, write_max); +} + +void gaudi2_write_rr_to_all_lbw_rtrs(struct hl_device *hdev, u8 rr_type, u32 rr_index, u64 min_val, + u64 max_val) +{ + struct dup_block_ctx block_ctx; + struct rr_config rr_cfg; + + if ((rr_type == RR_TYPE_SHORT || rr_type == RR_TYPE_SHORT_PRIV) && + rr_index >= NUM_SHORT_LBW_RR) { + + dev_err(hdev->dev, "invalid short LBW %s range register index: %u", + rr_type == RR_TYPE_SHORT ? "secure" : "privileged", rr_index); + return; + } + + if ((rr_type == RR_TYPE_LONG || rr_type == RR_TYPE_LONG_PRIV) && + rr_index >= NUM_LONG_LBW_RR) { + + dev_err(hdev->dev, "invalid long LBW %s range register index: %u", + rr_type == RR_TYPE_LONG ? "secure" : "privileged", rr_index); + return; + } + + rr_cfg.type = rr_type; + rr_cfg.index = rr_index; + rr_cfg.min = min_val; + rr_cfg.max = max_val; + + block_ctx.instance_cfg_fn = &gaudi2_write_lbw_range_register; + block_ctx.data = &rr_cfg; + + /* SFT */ + block_ctx.base = mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE; + block_ctx.blocks = NUM_OF_SFT; + block_ctx.block_off = SFT_OFFSET; + block_ctx.instances = SFT_NUM_OF_LBW_RTR; + block_ctx.instance_off = SFT_LBW_RTR_OFFSET; + gaudi2_init_blocks(hdev, &block_ctx); + + /* SIF */ + block_ctx.base = mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE; + block_ctx.blocks = NUM_OF_DCORES; + block_ctx.block_off = DCORE_OFFSET; + block_ctx.instances = NUM_OF_RTR_PER_DCORE; + block_ctx.instance_off = DCORE_RTR_OFFSET; + gaudi2_init_blocks(hdev, &block_ctx); + + block_ctx.blocks = 1; + block_ctx.block_off = 0; + block_ctx.instances = 1; + block_ctx.instance_off = 0; + + /* PCIE ELBI */ + block_ctx.base = mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_BASE; + gaudi2_init_blocks(hdev, &block_ctx); + + /* PCIE MSTR */ + block_ctx.base = mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_BASE; + gaudi2_init_blocks(hdev, &block_ctx); + + /* PCIE LBW */ + block_ctx.base = mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_BASE; + gaudi2_init_blocks(hdev, &block_ctx); +} + +static void gaudi2_init_lbw_range_registers_secure(struct hl_device *hdev) +{ + int i; + + /* Up to 14 14bit-address regs. + * + * - range 0: NIC0_CFG + * - range 1: NIC1_CFG + * - range 2: NIC2_CFG + * - range 3: NIC3_CFG + * - range 4: NIC4_CFG + * - range 5: NIC5_CFG + * - range 6: NIC6_CFG + * - range 7: NIC7_CFG + * - range 8: NIC8_CFG + * - range 9: NIC9_CFG + * - range 10: NIC10_CFG + * - range 11: NIC11_CFG + *_DBG (not including TPC_DBG) + * + * If F/W security is not enabled: + * - ranges 12,13: PSOC_CFG (excluding PSOC_TIMESTAMP) + */ + u64 lbw_range_min_short[] = { + mmNIC0_TX_AXUSER_BASE, + mmNIC1_TX_AXUSER_BASE, + mmNIC2_TX_AXUSER_BASE, + mmNIC3_TX_AXUSER_BASE, + mmNIC4_TX_AXUSER_BASE, + mmNIC5_TX_AXUSER_BASE, + mmNIC6_TX_AXUSER_BASE, + mmNIC7_TX_AXUSER_BASE, + mmNIC8_TX_AXUSER_BASE, + mmNIC9_TX_AXUSER_BASE, + mmNIC10_TX_AXUSER_BASE, + mmNIC11_TX_AXUSER_BASE, + mmPSOC_I2C_M0_BASE, + mmPSOC_EFUSE_BASE + }; + u64 lbw_range_max_short[] = { + mmNIC0_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE, + mmNIC1_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE, + mmNIC2_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE, + mmNIC3_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE, + mmNIC4_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE, + mmNIC5_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE, + mmNIC6_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE, + mmNIC7_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE, + mmNIC8_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE, + mmNIC9_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE, + mmNIC10_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE, + mmNIC11_DBG_FUNNEL_NCH_BASE + HL_BLOCK_SIZE, + mmPSOC_WDOG_BASE + HL_BLOCK_SIZE, + mmSVID2_AC_BASE + HL_BLOCK_SIZE + }; + + /* Up to 4 26bit-address regs. + * + * - range 0: TPC_DBG + * - range 1: PCIE_DBI.MSIX_DOORBELL_OFF + * - range 2/3: used in soft reset to block access to several blocks and are cleared here + */ + u64 lbw_range_min_long[] = { + mmDCORE0_TPC0_ROM_TABLE_BASE, + mmPCIE_DBI_MSIX_DOORBELL_OFF, + 0x0, + 0x0 + }; + u64 lbw_range_max_long[] = { + mmDCORE3_TPC5_EML_CS_BASE + HL_BLOCK_SIZE, + mmPCIE_DBI_MSIX_DOORBELL_OFF + 0x4, + 0x0, + 0x0 + }; + + /* write short range registers to all lbw rtrs */ + for (i = 0 ; i < ARRAY_SIZE(lbw_range_min_short) ; i++) { + if ((lbw_range_min_short[i] == mmPSOC_I2C_M0_BASE || + lbw_range_min_short[i] == mmPSOC_EFUSE_BASE) && + hdev->asic_prop.fw_security_enabled) + continue; + + gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_SHORT, i, + lbw_range_min_short[i], lbw_range_max_short[i]); + } + + /* write long range registers to all lbw rtrs */ + for (i = 0 ; i < ARRAY_SIZE(lbw_range_min_long) ; i++) { + gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_LONG, i, + lbw_range_min_long[i], lbw_range_max_long[i]); + } +} + +static void gaudi2_init_lbw_range_registers(struct hl_device *hdev) +{ + gaudi2_init_lbw_range_registers_secure(hdev); +} + +static void gaudi2_write_hbw_range_register(struct hl_device *hdev, u64 base, void *data) +{ + u32 min_lo_reg_offset, min_hi_reg_offset, max_lo_reg_offset, max_hi_reg_offset; + struct rr_config *rr_cfg = (struct rr_config *) data; + u64 val_min, val_max; + + switch (rr_cfg->type) { + case RR_TYPE_SHORT: + min_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0_OFFSET; + min_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0_OFFSET; + max_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0_OFFSET; + max_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0_OFFSET; + break; + + case RR_TYPE_LONG: + min_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_LO_0_OFFSET; + min_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_HI_0_OFFSET; + max_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_LO_0_OFFSET; + max_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_HI_0_OFFSET; + break; + + case RR_TYPE_SHORT_PRIV: + min_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0_OFFSET; + min_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0_OFFSET; + max_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0_OFFSET; + max_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0_OFFSET; + break; + + case RR_TYPE_LONG_PRIV: + min_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0_OFFSET; + min_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0_OFFSET; + max_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0_OFFSET; + max_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0_OFFSET; + break; + + default: + dev_err(hdev->dev, "Invalid HBW RR type %u\n", rr_cfg->type); + return; + } + + min_lo_reg_offset += rr_cfg->index * sizeof(u32); + min_hi_reg_offset += rr_cfg->index * sizeof(u32); + max_lo_reg_offset += rr_cfg->index * sizeof(u32); + max_hi_reg_offset += rr_cfg->index * sizeof(u32); + + if (rr_cfg->type == RR_TYPE_SHORT || rr_cfg->type == RR_TYPE_SHORT_PRIV) { + val_min = FIELD_GET(RR_HBW_SHORT_HI_MASK, rr_cfg->min) | + FIELD_GET(RR_HBW_SHORT_LO_MASK, rr_cfg->min); + val_max = FIELD_GET(RR_HBW_SHORT_HI_MASK, rr_cfg->max) | + FIELD_GET(RR_HBW_SHORT_LO_MASK, rr_cfg->max); + } else { + val_min = FIELD_GET(RR_HBW_LONG_HI_MASK, rr_cfg->min) | + FIELD_GET(RR_HBW_LONG_LO_MASK, rr_cfg->min); + val_max = FIELD_GET(RR_HBW_LONG_HI_MASK, rr_cfg->max) | + FIELD_GET(RR_HBW_LONG_LO_MASK, rr_cfg->max); + } + + /* Configure HBW RR: + * SHORT RRs (0x1000_<36bits>000) - HI: address bits [47:44], LO: address bits [43:12] + * LONG RRs (0x<52bits>000) - HI: address bits [63:44], LO: address bits [43:12] + */ + WREG32(base + min_lo_reg_offset, lower_32_bits(val_min)); + WREG32(base + min_hi_reg_offset, upper_32_bits(val_min)); + WREG32(base + max_lo_reg_offset, lower_32_bits(val_max)); + WREG32(base + max_hi_reg_offset, upper_32_bits(val_max)); +} + +static void gaudi2_write_hbw_rr_to_all_mstr_if(struct hl_device *hdev, u8 rr_type, u32 rr_index, + u64 min_val, u64 max_val) +{ + struct dup_block_ctx block_ctx; + struct rr_config rr_cfg; + + if ((rr_type == RR_TYPE_SHORT || rr_type == RR_TYPE_SHORT_PRIV) && + rr_index >= NUM_SHORT_HBW_RR) { + + dev_err(hdev->dev, "invalid short HBW %s range register index: %u", + rr_type == RR_TYPE_SHORT ? "secure" : "privileged", rr_index); + return; + } + + if ((rr_type == RR_TYPE_LONG || rr_type == RR_TYPE_LONG_PRIV) && + rr_index >= NUM_LONG_HBW_RR) { + + dev_err(hdev->dev, "invalid long HBW %s range register index: %u", + rr_type == RR_TYPE_LONG ? "secure" : "privileged", rr_index); + return; + } + + rr_cfg.type = rr_type; + rr_cfg.index = rr_index; + rr_cfg.min = min_val; + rr_cfg.max = max_val; + + block_ctx.instance_cfg_fn = &gaudi2_write_hbw_range_register; + block_ctx.data = &rr_cfg; + + /* SFT */ + block_ctx.base = mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE; + block_ctx.blocks = NUM_OF_SFT; + block_ctx.block_off = SFT_OFFSET; + block_ctx.instances = SFT_NUM_OF_HBW_RTR; + block_ctx.instance_off = SFT_IF_RTR_OFFSET; + gaudi2_init_blocks(hdev, &block_ctx); + + /* SIF */ + block_ctx.base = mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE; + block_ctx.blocks = NUM_OF_DCORES; + block_ctx.block_off = DCORE_OFFSET; + block_ctx.instances = NUM_OF_RTR_PER_DCORE; + block_ctx.instance_off = DCORE_RTR_OFFSET; + gaudi2_init_blocks(hdev, &block_ctx); + + /* PCIE MSTR */ + block_ctx.base = mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE; + block_ctx.blocks = 1; + block_ctx.block_off = 0; + block_ctx.instances = 1; + block_ctx.instance_off = 0; + gaudi2_init_blocks(hdev, &block_ctx); +} + +static void gaudi2_init_hbw_range_registers(struct hl_device *hdev) +{ + int i; + + /* Up to 6 short RR (0x1000_<36bits>000) and 4 long RR (0x<52bits>000). + * + * - short range 0: + * SPI Flash, ARC0/1 ICCM/DCCM, Secure Boot ROM, PSOC_FW/Scratchpad/PCIE_FW SRAM + */ + u64 hbw_range_min_short[] = { + SPI_FLASH_BASE_ADDR + }; + u64 hbw_range_max_short[] = { + PCIE_FW_SRAM_ADDR + PCIE_FW_SRAM_SIZE + }; + + for (i = 0 ; i < ARRAY_SIZE(hbw_range_min_short) ; i++) { + gaudi2_write_hbw_rr_to_all_mstr_if(hdev, RR_TYPE_SHORT, i, hbw_range_min_short[i], + hbw_range_max_short[i]); + } +} + +static void gaudi2_write_mmu_range_register(struct hl_device *hdev, u64 base, + struct rr_config *rr_cfg) +{ + u32 min_lo_reg_offset, min_hi_reg_offset, max_lo_reg_offset, max_hi_reg_offset; + + switch (rr_cfg->type) { + case RR_TYPE_LONG: + min_lo_reg_offset = MMU_RR_SEC_MIN_31_0_0_OFFSET; + min_hi_reg_offset = MMU_RR_SEC_MIN_63_32_0_OFFSET; + max_lo_reg_offset = MMU_RR_SEC_MAX_31_0_0_OFFSET; + max_hi_reg_offset = MMU_RR_SEC_MAX_63_32_0_OFFSET; + break; + + case RR_TYPE_LONG_PRIV: + min_lo_reg_offset = MMU_RR_PRIV_MIN_31_0_0_OFFSET; + min_hi_reg_offset = MMU_RR_PRIV_MIN_63_32_0_OFFSET; + max_lo_reg_offset = MMU_RR_PRIV_MAX_31_0_0_OFFSET; + max_hi_reg_offset = MMU_RR_PRIV_MAX_63_32_0_OFFSET; + break; + + default: + dev_err(hdev->dev, "Invalid MMU RR type %u\n", rr_cfg->type); + return; + } + + min_lo_reg_offset += rr_cfg->index * sizeof(u32); + min_hi_reg_offset += rr_cfg->index * sizeof(u32); + max_lo_reg_offset += rr_cfg->index * sizeof(u32); + max_hi_reg_offset += rr_cfg->index * sizeof(u32); + + /* Configure MMU RR (address bits [63:0]) */ + WREG32(base + min_lo_reg_offset, lower_32_bits(rr_cfg->min)); + WREG32(base + min_hi_reg_offset, upper_32_bits(rr_cfg->min)); + WREG32(base + max_lo_reg_offset, lower_32_bits(rr_cfg->max)); + WREG32(base + max_hi_reg_offset, upper_32_bits(rr_cfg->max)); +} + +static void gaudi2_init_mmu_range_registers(struct hl_device *hdev) +{ + u32 dcore_id, hmmu_id, hmmu_base; + struct rr_config rr_cfg; + + /* Up to 8 ranges [63:0]. + * + * - range 0: Reserved HBM area for F/W and driver + */ + + /* The RRs are located after the HMMU so need to use the scrambled addresses */ + rr_cfg.min = hdev->asic_funcs->scramble_addr(hdev, DRAM_PHYS_BASE); + rr_cfg.max = hdev->asic_funcs->scramble_addr(hdev, hdev->asic_prop.dram_user_base_address); + rr_cfg.index = 0; + rr_cfg.type = RR_TYPE_LONG; + + for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++) { + for (hmmu_id = 0 ; hmmu_id < NUM_OF_HMMU_PER_DCORE; hmmu_id++) { + if (!gaudi2_is_hmmu_enabled(hdev, dcore_id, hmmu_id)) + continue; + + hmmu_base = mmDCORE0_HMMU0_MMU_BASE + dcore_id * DCORE_OFFSET + + hmmu_id * DCORE_HMMU_OFFSET; + + gaudi2_write_mmu_range_register(hdev, hmmu_base, &rr_cfg); + } + } +} + +/** + * gaudi2_init_range_registers - + * Initialize range registers of all initiators + * + * @hdev: pointer to hl_device structure + */ +static void gaudi2_init_range_registers(struct hl_device *hdev) +{ + gaudi2_init_lbw_range_registers(hdev); + gaudi2_init_hbw_range_registers(hdev); + gaudi2_init_mmu_range_registers(hdev); +} + +/** + * gaudi2_init_protection_bits - + * Initialize protection bits of specific registers + * + * @hdev: pointer to hl_device structure + * + * All protection bits are 1 by default, means not protected. Need to set to 0 + * each bit that belongs to a protected register. + * + */ +static int gaudi2_init_protection_bits(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + u32 instance_offset; + int rc = 0; + u8 i; + + /* SFT */ + instance_offset = mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE; + rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset, + gaudi2_pb_sft0, ARRAY_SIZE(gaudi2_pb_sft0), + NULL, HL_PB_NA); + + /* HIF */ + instance_offset = mmDCORE0_HIF1_BASE - mmDCORE0_HIF0_BASE; + rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, + NUM_OF_HIF_PER_DCORE, instance_offset, + gaudi2_pb_dcr0_hif, ARRAY_SIZE(gaudi2_pb_dcr0_hif), + NULL, HL_PB_NA, prop->hmmu_hif_enabled_mask); + + /* RTR */ + instance_offset = mmDCORE0_RTR1_CTRL_BASE - mmDCORE0_RTR0_CTRL_BASE; + rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset, + gaudi2_pb_dcr0_rtr0, ARRAY_SIZE(gaudi2_pb_dcr0_rtr0), + NULL, HL_PB_NA); + + /* HMMU */ + rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, + NUM_OF_HMMU_PER_DCORE, DCORE_HMMU_OFFSET, + gaudi2_pb_dcr0_hmmu0, ARRAY_SIZE(gaudi2_pb_dcr0_hmmu0), + NULL, HL_PB_NA, prop->hmmu_hif_enabled_mask); + + /* CPU. + * Except for CPU_IF, skip when security is enabled in F/W, because the blocks are protected + * by privileged RR. + */ + rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, + HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_cpu_if, ARRAY_SIZE(gaudi2_pb_cpu_if), + NULL, HL_PB_NA); + + if (!hdev->asic_prop.fw_security_enabled) + rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, + HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_cpu, ARRAY_SIZE(gaudi2_pb_cpu), + NULL, HL_PB_NA); + + /* KDMA */ + rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, + HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_kdma, ARRAY_SIZE(gaudi2_pb_kdma), + NULL, HL_PB_NA); + + /* PDMA */ + instance_offset = mmPDMA1_CORE_BASE - mmPDMA0_CORE_BASE; + rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset, + gaudi2_pb_pdma0, ARRAY_SIZE(gaudi2_pb_pdma0), + gaudi2_pb_pdma0_unsecured_regs, + ARRAY_SIZE(gaudi2_pb_pdma0_unsecured_regs)); + + /* ARC PDMA */ + rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, 2, + instance_offset, gaudi2_pb_pdma0_arc, + ARRAY_SIZE(gaudi2_pb_pdma0_arc), + gaudi2_pb_pdma0_arc_unsecured_regs, + ARRAY_SIZE(gaudi2_pb_pdma0_arc_unsecured_regs)); + + /* EDMA */ + instance_offset = mmDCORE0_EDMA1_CORE_BASE - mmDCORE0_EDMA0_CORE_BASE; + rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2, + instance_offset, gaudi2_pb_dcr0_edma0, + ARRAY_SIZE(gaudi2_pb_dcr0_edma0), + gaudi2_pb_dcr0_edma0_unsecured_regs, + ARRAY_SIZE(gaudi2_pb_dcr0_edma0_unsecured_regs), + prop->edma_enabled_mask); + + /* ARC EDMA */ + rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2, + instance_offset, gaudi2_pb_dcr0_edma0_arc, + ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc), + gaudi2_pb_dcr0_edma0_arc_unsecured_regs, + ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc_unsecured_regs), + prop->edma_enabled_mask); + + /* MME */ + instance_offset = mmDCORE0_MME_SBTE1_BASE - mmDCORE0_MME_SBTE0_BASE; + + for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) { + /* MME SBTE */ + rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i), 5, + instance_offset, gaudi2_pb_dcr0_mme_sbte, + ARRAY_SIZE(gaudi2_pb_dcr0_mme_sbte), NULL, + HL_PB_NA); + + /* MME */ + rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i), + HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_dcr0_mme_eng, + ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng), + gaudi2_pb_dcr0_mme_eng_unsecured_regs, + ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng_unsecured_regs)); + } + + /* + * we have special iteration for case in which we would like to + * configure stubbed MME's ARC/QMAN + */ + for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) { + /* MME QM */ + rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i), + HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_dcr0_mme_qm, + ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm), + gaudi2_pb_dcr0_mme_qm_unsecured_regs, + ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm_unsecured_regs)); + + /* ARC MME */ + rc |= hl_init_pb_ranges_single_dcore(hdev, (DCORE_OFFSET * i), + HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_dcr0_mme_arc, + ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc), + gaudi2_pb_dcr0_mme_arc_unsecured_regs, + ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc_unsecured_regs)); + } + + /* MME QM ARC ACP ENG */ + rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, + HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_mme_qm_arc_acp_eng, + ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng), + gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs, + ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs), + (BIT(NUM_OF_DCORES * NUM_OF_MME_PER_DCORE) - 1)); + + /* TPC */ + rc |= gaudi2_init_pb_tpc(hdev); + rc |= gaudi2_init_pb_tpc_arc(hdev); + + /* SRAM */ + instance_offset = mmDCORE0_SRAM1_BANK_BASE - mmDCORE0_SRAM0_BANK_BASE; + rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset, + gaudi2_pb_dcr0_sram0, ARRAY_SIZE(gaudi2_pb_dcr0_sram0), + NULL, HL_PB_NA); + + /* Sync Manager MSTR IF */ + rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, + HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_dcr0_sm_mstr_if, + ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if), + NULL, HL_PB_NA); + + /* Sync Manager GLBL */ + + /* Unsecure all CQ registers */ + rc |= hl_init_pb_ranges(hdev, NUM_OF_DCORES, DCORE_OFFSET, + HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_dcr0_sm_glbl, + ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl), + gaudi2_pb_dcr_x_sm_glbl_unsecured_regs, + ARRAY_SIZE(gaudi2_pb_dcr_x_sm_glbl_unsecured_regs)); + + /* Secure Dcore0 CQ0 registers */ + rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, + HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_dcr0_sm_glbl, + ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl), + gaudi2_pb_dcr0_sm_glbl_unsecured_regs, + ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl_unsecured_regs)); + + /* PSOC. + * Except for PSOC_GLOBAL_CONF, skip when security is enabled in F/W, because the blocks are + * protected by privileged RR. + */ + rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, + HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_psoc_global_conf, ARRAY_SIZE(gaudi2_pb_psoc_global_conf), + NULL, HL_PB_NA); + + if (!hdev->asic_prop.fw_security_enabled) + rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, + HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_psoc, ARRAY_SIZE(gaudi2_pb_psoc), + NULL, HL_PB_NA); + + /* PMMU */ + rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, + HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_pmmu, ARRAY_SIZE(gaudi2_pb_pmmu), + NULL, HL_PB_NA); + + /* PLL. + * Skip PSOC/XFT PLL when security is enabled in F/W, because these blocks are protected by + * privileged RR. + */ + rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, + HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_pmmu_pll, ARRAY_SIZE(gaudi2_pb_pmmu_pll), + NULL, HL_PB_NA); + rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, + HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_xbar_pll, ARRAY_SIZE(gaudi2_pb_xbar_pll), + NULL, HL_PB_NA); + + if (!hdev->asic_prop.fw_security_enabled) { + rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, + HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_psoc_pll, ARRAY_SIZE(gaudi2_pb_psoc_pll), + NULL, HL_PB_NA); + rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, + HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_xft_pll, ARRAY_SIZE(gaudi2_pb_xft_pll), + NULL, HL_PB_NA); + } + + /* PCIE */ + rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, + HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_pcie, ARRAY_SIZE(gaudi2_pb_pcie), + NULL, HL_PB_NA); + + /* Thermal Sensor. + * Skip when security is enabled in F/W, because the blocks are protected by privileged RR. + */ + if (!hdev->asic_prop.fw_security_enabled) { + instance_offset = mmDCORE1_XFT_BASE - mmDCORE0_XFT_BASE; + rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset, + gaudi2_pb_thermal_sensor0, + ARRAY_SIZE(gaudi2_pb_thermal_sensor0), NULL, HL_PB_NA); + } + + /* HBM */ + /* Temporarily skip until SW-63348 is solved + * instance_offset = mmHBM1_MC0_BASE - mmHBM0_MC0_BASE; + * rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, GAUDI2_HBM_NUM, + * instance_offset, gaudi2_pb_hbm, + * ARRAY_SIZE(gaudi2_pb_hbm), NULL, HL_PB_NA, + * prop->dram_enabled_mask); + */ + + /* Scheduler ARCs */ + instance_offset = mmARC_FARM_ARC1_AUX_BASE - mmARC_FARM_ARC0_AUX_BASE; + rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, + NUM_OF_ARC_FARMS_ARC, + instance_offset, gaudi2_pb_arc_sched, + ARRAY_SIZE(gaudi2_pb_arc_sched), + gaudi2_pb_arc_sched_unsecured_regs, + ARRAY_SIZE(gaudi2_pb_arc_sched_unsecured_regs)); + + /* XBAR MIDs */ + instance_offset = mmXBAR_MID_1_BASE - mmXBAR_MID_0_BASE; + rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR, + instance_offset, gaudi2_pb_xbar_mid, + ARRAY_SIZE(gaudi2_pb_xbar_mid), + gaudi2_pb_xbar_mid_unsecured_regs, + ARRAY_SIZE(gaudi2_pb_xbar_mid_unsecured_regs)); + + /* XBAR EDGEs */ + instance_offset = mmXBAR_EDGE_1_BASE - mmXBAR_EDGE_0_BASE; + rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR, + instance_offset, gaudi2_pb_xbar_edge, + ARRAY_SIZE(gaudi2_pb_xbar_edge), + gaudi2_pb_xbar_edge_unsecured_regs, + ARRAY_SIZE(gaudi2_pb_xbar_edge_unsecured_regs), + prop->xbar_edge_enabled_mask); + + /* NIC */ + rc |= hl_init_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, + HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_nic0, ARRAY_SIZE(gaudi2_pb_nic0), + NULL, HL_PB_NA, hdev->nic_ports_mask); + + /* NIC QM and QPC */ + rc |= hl_init_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, + NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET, + gaudi2_pb_nic0_qm_qpc, ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc), + gaudi2_pb_nic0_qm_qpc_unsecured_regs, + ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc_unsecured_regs), + hdev->nic_ports_mask); + + /* NIC QM ARC */ + rc |= hl_init_pb_ranges_with_mask(hdev, NIC_NUMBER_OF_MACROS, + NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET, + gaudi2_pb_nic0_qm_arc_aux0, + ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0), + gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs, + ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs), + hdev->nic_ports_mask); + + /* NIC UMR */ + rc |= hl_init_pb_ranges_with_mask(hdev, NIC_NUMBER_OF_MACROS, + NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET, + gaudi2_pb_nic0_umr, + ARRAY_SIZE(gaudi2_pb_nic0_umr), + gaudi2_pb_nic0_umr_unsecured_regs, + ARRAY_SIZE(gaudi2_pb_nic0_umr_unsecured_regs), + hdev->nic_ports_mask); + + /* Rotators */ + instance_offset = mmROT1_BASE - mmROT0_BASE; + rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, + instance_offset, gaudi2_pb_rot0, + ARRAY_SIZE(gaudi2_pb_rot0), + gaudi2_pb_rot0_unsecured_regs, + ARRAY_SIZE(gaudi2_pb_rot0_unsecured_regs), + (BIT(NUM_OF_ROT) - 1)); + + /* Rotators ARCS */ + rc |= hl_init_pb_ranges_with_mask(hdev, HL_PB_SHARED, + HL_PB_NA, NUM_OF_ROT, instance_offset, + gaudi2_pb_rot0_arc, ARRAY_SIZE(gaudi2_pb_rot0_arc), + gaudi2_pb_rot0_arc_unsecured_regs, + ARRAY_SIZE(gaudi2_pb_rot0_arc_unsecured_regs), + (BIT(NUM_OF_ROT) - 1)); + + rc |= gaudi2_init_pb_sm_objs(hdev); + + return rc; +} + +/** + * gaudi2_init_security - Initialize security model + * + * @hdev: pointer to hl_device structure + * + * Initialize the security model of the device + * That includes range registers and protection bit per register. + */ +int gaudi2_init_security(struct hl_device *hdev) +{ + int rc; + + rc = gaudi2_init_protection_bits(hdev); + if (rc) + return rc; + + gaudi2_init_range_registers(hdev); + + return 0; +} + +struct gaudi2_ack_pb_tpc_data { + u32 tpc_regs_array_size; + u32 arc_tpc_regs_array_size; +}; + +static void gaudi2_ack_pb_tpc_config(struct hl_device *hdev, int dcore, int inst, u32 offset, + void *data) +{ + struct gaudi2_ack_pb_tpc_data *pb_data = (struct gaudi2_ack_pb_tpc_data *)data; + + hl_ack_pb_single_dcore(hdev, offset, HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_dcr0_tpc0, pb_data->tpc_regs_array_size); + + hl_ack_pb_single_dcore(hdev, offset, HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_dcr0_tpc0_arc, pb_data->arc_tpc_regs_array_size); +} + +static void gaudi2_ack_pb_tpc(struct hl_device *hdev) +{ + struct iterate_module_ctx tpc_iter = { + .fn = &gaudi2_ack_pb_tpc_config, + }; + struct gaudi2_ack_pb_tpc_data data; + + data.tpc_regs_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0); + data.arc_tpc_regs_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc); + tpc_iter.data = &data; + + gaudi2_iterate_tpcs(hdev, &tpc_iter); +} + +/** + * gaudi2_ack_protection_bits_errors - scan all blocks having protection bits + * and for every protection error found, display the appropriate error message + * and clear the error. + * + * @hdev: pointer to hl_device structure + * + * All protection bits are 1 by default, means not protected. Need to set to 0 + * each bit that belongs to a protected register. + * + */ +void gaudi2_ack_protection_bits_errors(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + u32 instance_offset; + u8 i; + + /* SFT */ + instance_offset = mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE; + hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset, + gaudi2_pb_sft0, ARRAY_SIZE(gaudi2_pb_sft0)); + + /* HIF */ + instance_offset = mmDCORE0_HIF1_BASE - mmDCORE0_HIF0_BASE; + hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, + NUM_OF_HIF_PER_DCORE, instance_offset, + gaudi2_pb_dcr0_hif, ARRAY_SIZE(gaudi2_pb_dcr0_hif), + prop->hmmu_hif_enabled_mask); + + /* RTR */ + instance_offset = mmDCORE0_RTR1_CTRL_BASE - mmDCORE0_RTR0_CTRL_BASE; + hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset, + gaudi2_pb_dcr0_rtr0, ARRAY_SIZE(gaudi2_pb_dcr0_rtr0)); + + /* HMMU */ + hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, + NUM_OF_HMMU_PER_DCORE, DCORE_HMMU_OFFSET, + gaudi2_pb_dcr0_hmmu0, ARRAY_SIZE(gaudi2_pb_dcr0_hmmu0), + prop->hmmu_hif_enabled_mask); + + /* CPU. + * Except for CPU_IF, skip when security is enabled in F/W, because the blocks are protected + * by privileged RR. + */ + hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_cpu_if, ARRAY_SIZE(gaudi2_pb_cpu_if)); + if (!hdev->asic_prop.fw_security_enabled) + hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_cpu, ARRAY_SIZE(gaudi2_pb_cpu)); + + /* KDMA */ + hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_kdma, ARRAY_SIZE(gaudi2_pb_kdma)); + + /* PDMA */ + instance_offset = mmPDMA1_CORE_BASE - mmPDMA0_CORE_BASE; + hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset, + gaudi2_pb_pdma0, ARRAY_SIZE(gaudi2_pb_pdma0)); + + /* ARC PDMA */ + hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset, + gaudi2_pb_pdma0_arc, ARRAY_SIZE(gaudi2_pb_pdma0_arc)); + + /* EDMA */ + instance_offset = mmDCORE0_EDMA1_CORE_BASE - mmDCORE0_EDMA0_CORE_BASE; + hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2, + instance_offset, gaudi2_pb_dcr0_edma0, + ARRAY_SIZE(gaudi2_pb_dcr0_edma0), + prop->edma_enabled_mask); + + /* ARC EDMA */ + hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2, + instance_offset, gaudi2_pb_dcr0_edma0_arc, + ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc), + prop->edma_enabled_mask); + + /* MME */ + instance_offset = mmDCORE0_MME_SBTE1_BASE - mmDCORE0_MME_SBTE0_BASE; + + for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) { + /* MME SBTE */ + hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i), 5, + instance_offset, gaudi2_pb_dcr0_mme_sbte, + ARRAY_SIZE(gaudi2_pb_dcr0_mme_sbte)); + + /* MME */ + hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i), + HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_dcr0_mme_eng, + ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng)); + } + + /* + * we have special iteration for case in which we would like to + * configure stubbed MME's ARC/QMAN + */ + for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) { + /* MME QM */ + hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i), + HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_dcr0_mme_qm, + ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm)); + + /* ARC MME */ + hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i), + HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_dcr0_mme_arc, + ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc)); + } + + /* MME QM ARC ACP ENG */ + hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, + HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_mme_qm_arc_acp_eng, + ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng), + (BIT(NUM_OF_DCORES * NUM_OF_MME_PER_DCORE) - 1)); + + /* TPC */ + gaudi2_ack_pb_tpc(hdev); + + /* SRAM */ + instance_offset = mmDCORE0_SRAM1_BANK_BASE - mmDCORE0_SRAM0_BANK_BASE; + hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset, + gaudi2_pb_dcr0_sram0, ARRAY_SIZE(gaudi2_pb_dcr0_sram0)); + + /* Sync Manager MSTR IF */ + hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_dcr0_sm_mstr_if, ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if)); + + /* Sync Manager */ + hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_dcr0_sm_glbl, ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl)); + + hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_dcr0_sm_mstr_if, ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if)); + + /* PSOC. + * Except for PSOC_GLOBAL_CONF, skip when security is enabled in F/W, because the blocks are + * protected by privileged RR. + */ + hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_psoc_global_conf, ARRAY_SIZE(gaudi2_pb_psoc_global_conf)); + if (!hdev->asic_prop.fw_security_enabled) + hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_psoc, ARRAY_SIZE(gaudi2_pb_psoc)); + + /* PMMU */ + hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_pmmu, ARRAY_SIZE(gaudi2_pb_pmmu)); + + /* PLL. + * Skip PSOC/XFT PLL when security is enabled in F/W, because these blocks are protected by + * privileged RR. + */ + hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_pmmu_pll, ARRAY_SIZE(gaudi2_pb_pmmu_pll)); + hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_xbar_pll, ARRAY_SIZE(gaudi2_pb_xbar_pll)); + if (!hdev->asic_prop.fw_security_enabled) { + hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_psoc_pll, ARRAY_SIZE(gaudi2_pb_psoc_pll)); + hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_xft_pll, ARRAY_SIZE(gaudi2_pb_xft_pll)); + } + + /* PCIE */ + hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_pcie, ARRAY_SIZE(gaudi2_pb_pcie)); + + /* Thermal Sensor. + * Skip when security is enabled in F/W, because the blocks are protected by privileged RR. + */ + if (!hdev->asic_prop.fw_security_enabled) { + instance_offset = mmDCORE1_XFT_BASE - mmDCORE0_XFT_BASE; + hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset, + gaudi2_pb_thermal_sensor0, ARRAY_SIZE(gaudi2_pb_thermal_sensor0)); + } + + /* HBM */ + instance_offset = mmHBM1_MC0_BASE - mmHBM0_MC0_BASE; + hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, GAUDI2_HBM_NUM, + instance_offset, gaudi2_pb_hbm, + ARRAY_SIZE(gaudi2_pb_hbm), prop->dram_enabled_mask); + + /* Scheduler ARCs */ + instance_offset = mmARC_FARM_ARC1_AUX_BASE - mmARC_FARM_ARC0_AUX_BASE; + hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ARC_FARMS_ARC, + instance_offset, gaudi2_pb_arc_sched, + ARRAY_SIZE(gaudi2_pb_arc_sched)); + + /* XBAR MIDs */ + instance_offset = mmXBAR_MID_1_BASE - mmXBAR_MID_0_BASE; + hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR, + instance_offset, gaudi2_pb_xbar_mid, + ARRAY_SIZE(gaudi2_pb_xbar_mid)); + + /* XBAR EDGEs */ + instance_offset = mmXBAR_EDGE_1_BASE - mmXBAR_EDGE_0_BASE; + hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR, + instance_offset, gaudi2_pb_xbar_edge, + ARRAY_SIZE(gaudi2_pb_xbar_edge), prop->xbar_edge_enabled_mask); + + /* NIC */ + hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA, + gaudi2_pb_nic0, ARRAY_SIZE(gaudi2_pb_nic0), hdev->nic_ports_mask); + + /* NIC QM and QPC */ + hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO, + NIC_QM_OFFSET, gaudi2_pb_nic0_qm_qpc, ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc), + hdev->nic_ports_mask); + + /* NIC QM ARC */ + hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO, + NIC_QM_OFFSET, gaudi2_pb_nic0_qm_arc_aux0, + ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0), hdev->nic_ports_mask); + + /* NIC UMR */ + hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO, + NIC_QM_OFFSET, gaudi2_pb_nic0_umr, ARRAY_SIZE(gaudi2_pb_nic0_umr), + hdev->nic_ports_mask); + + /* Rotators */ + instance_offset = mmROT1_BASE - mmROT0_BASE; + hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset, + gaudi2_pb_rot0, ARRAY_SIZE(gaudi2_pb_rot0), (BIT(NUM_OF_ROT) - 1)); + + /* Rotators ARCS */ + hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset, + gaudi2_pb_rot0_arc, ARRAY_SIZE(gaudi2_pb_rot0_arc), (BIT(NUM_OF_ROT) - 1)); +} + +/* + * Print PB security errors + */ + +void gaudi2_pb_print_security_errors(struct hl_device *hdev, u32 block_addr, u32 cause, + u32 offended_addr) +{ + int i = 0; + const char *error_format = + "Security error at block 0x%x, offending address 0x%x\n" + "Cause 0x%x: %s %s %s %s %s %s %s %s\n"; + char *mcause[8] = {"Unknown", "", "", "", "", "", "", "" }; + + if (!cause) + return; + + if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD) + mcause[i++] = "APB_PRIV_RD"; + + if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD) + mcause[i++] = "APB_SEC_RD"; + + if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD) + mcause[i++] = "APB_UNMAPPED_RD"; + + if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR) + mcause[i++] = "APB_PRIV_WR"; + + if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR) + mcause[i++] = "APB_SEC_WR"; + + if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR) + mcause[i++] = "APB_UNMAPPED_WR"; + + if (cause & SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR) + mcause[i++] = "EXT_SEC_WR"; + + if (cause & SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR) + mcause[i++] = "APB_EXT_UNMAPPED_WR"; + + dev_err_ratelimited(hdev->dev, error_format, block_addr, offended_addr, + cause, mcause[0], mcause[1], mcause[2], mcause[3], + mcause[4], mcause[5], mcause[6], mcause[7]); +} diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/goya/goya.c index 4cde505a7416..db4487c33582 100644 --- a/drivers/misc/habanalabs/goya/goya.c +++ b/drivers/misc/habanalabs/goya/goya.c @@ -389,11 +389,12 @@ int goya_set_fixed_properties(struct hl_device *hdev) prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_USER; } + prop->cfg_base_address = CFG_BASE; prop->device_dma_offset_for_host_access = HOST_PHYS_BASE; prop->host_base_address = HOST_PHYS_BASE; prop->host_end_address = prop->host_base_address + HOST_PHYS_SIZE; prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES; - + prop->completion_mode = HL_COMPLETION_MODE_JOB; prop->dram_base_address = DRAM_PHYS_BASE; prop->dram_size = DRAM_PHYS_DEFAULT_SIZE; prop->dram_end_address = prop->dram_base_address + prop->dram_size; @@ -470,7 +471,7 @@ int goya_set_fixed_properties(struct hl_device *hdev) prop->max_pending_cs = GOYA_MAX_PENDING_CS; - prop->first_available_user_msix_interrupt = USHRT_MAX; + prop->first_available_user_interrupt = USHRT_MAX; for (i = 0 ; i < HL_MAX_DCORES ; i++) prop->first_available_cq[i] = USHRT_MAX; @@ -608,6 +609,7 @@ static int goya_early_init(struct hl_device *hdev) { struct asic_fixed_properties *prop = &hdev->asic_prop; struct pci_dev *pdev = hdev->pdev; + resource_size_t pci_bar_size; u32 fw_boot_status, val; int rc; @@ -618,24 +620,20 @@ static int goya_early_init(struct hl_device *hdev) } /* Check BAR sizes */ - if (pci_resource_len(pdev, SRAM_CFG_BAR_ID) != CFG_BAR_SIZE) { - dev_err(hdev->dev, - "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n", - SRAM_CFG_BAR_ID, - (unsigned long long) pci_resource_len(pdev, - SRAM_CFG_BAR_ID), - CFG_BAR_SIZE); + pci_bar_size = pci_resource_len(pdev, SRAM_CFG_BAR_ID); + + if (pci_bar_size != CFG_BAR_SIZE) { + dev_err(hdev->dev, "Not " HL_NAME "? BAR %d size %pa, expecting %llu\n", + SRAM_CFG_BAR_ID, &pci_bar_size, CFG_BAR_SIZE); rc = -ENODEV; goto free_queue_props; } - if (pci_resource_len(pdev, MSIX_BAR_ID) != MSIX_BAR_SIZE) { - dev_err(hdev->dev, - "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n", - MSIX_BAR_ID, - (unsigned long long) pci_resource_len(pdev, - MSIX_BAR_ID), - MSIX_BAR_SIZE); + pci_bar_size = pci_resource_len(pdev, MSIX_BAR_ID); + + if (pci_bar_size != MSIX_BAR_SIZE) { + dev_err(hdev->dev, "Not " HL_NAME "? BAR %d size %pa, expecting %llu\n", + MSIX_BAR_ID, &pci_bar_size, MSIX_BAR_SIZE); rc = -ENODEV; goto free_queue_props; } @@ -667,11 +665,7 @@ pci_init: /* Before continuing in the initialization, we need to read the preboot * version to determine whether we run with a security-enabled firmware */ - rc = hl_fw_read_preboot_status(hdev, mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS, - mmCPU_BOOT_DEV_STS0, - mmCPU_BOOT_DEV_STS1, mmCPU_BOOT_ERR0, - mmCPU_BOOT_ERR1, - GOYA_BOOT_FIT_REQ_TIMEOUT_USEC); + rc = hl_fw_read_preboot_status(hdev); if (rc) { if (hdev->reset_on_preboot_fail) hdev->asic_funcs->hw_fini(hdev, true, false); @@ -679,8 +673,7 @@ pci_init: } if (goya_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) { - dev_info(hdev->dev, - "H/W state is dirty, must reset before initializing\n"); + dev_dbg(hdev->dev, "H/W state is dirty, must reset before initializing\n"); hdev->asic_funcs->hw_fini(hdev, true, false); } @@ -894,7 +887,7 @@ int goya_late_init(struct hl_device *hdev) */ WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size)); - rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_ENABLE_PCI_ACCESS); + rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_ENABLE_PCI_ACCESS, 0x0); if (rc) { dev_err(hdev->dev, "Failed to enable PCI access from CPU %d\n", rc); @@ -1012,11 +1005,9 @@ static int goya_sw_init(struct hl_device *hdev) goto free_goya_device; } - hdev->cpu_accessible_dma_mem = - hdev->asic_funcs->asic_dma_alloc_coherent(hdev, - HL_CPU_ACCESSIBLE_MEM_SIZE, - &hdev->cpu_accessible_dma_address, - GFP_KERNEL | __GFP_ZERO); + hdev->cpu_accessible_dma_mem = hl_asic_dma_alloc_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, + &hdev->cpu_accessible_dma_address, + GFP_KERNEL | __GFP_ZERO); if (!hdev->cpu_accessible_dma_mem) { rc = -ENOMEM; @@ -1046,7 +1037,7 @@ static int goya_sw_init(struct hl_device *hdev) spin_lock_init(&goya->hw_queues_lock); hdev->supports_coresight = true; - hdev->asic_prop.supports_soft_reset = true; + hdev->asic_prop.supports_compute_reset = true; hdev->asic_prop.allow_inference_soft_reset = true; hdev->supports_wait_for_multi_cs = false; @@ -1066,10 +1057,8 @@ static int goya_sw_init(struct hl_device *hdev) free_cpu_accessible_dma_pool: gen_pool_destroy(hdev->cpu_accessible_dma_pool); free_cpu_dma_mem: - hdev->asic_funcs->asic_dma_free_coherent(hdev, - HL_CPU_ACCESSIBLE_MEM_SIZE, - hdev->cpu_accessible_dma_mem, - hdev->cpu_accessible_dma_address); + hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->cpu_accessible_dma_mem, + hdev->cpu_accessible_dma_address); free_dma_pool: dma_pool_destroy(hdev->dma_pool); free_goya_device: @@ -1090,10 +1079,8 @@ static int goya_sw_fini(struct hl_device *hdev) gen_pool_destroy(hdev->cpu_accessible_dma_pool); - hdev->asic_funcs->asic_dma_free_coherent(hdev, - HL_CPU_ACCESSIBLE_MEM_SIZE, - hdev->cpu_accessible_dma_mem, - hdev->cpu_accessible_dma_address); + hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->cpu_accessible_dma_mem, + hdev->cpu_accessible_dma_address); dma_pool_destroy(hdev->dma_pool); @@ -2588,6 +2575,18 @@ static void goya_init_static_firmware_loader(struct hl_device *hdev) static_loader->sram_offset_mask = ~(lower_32_bits(SRAM_BASE_ADDR)); } +static void goya_init_firmware_preload_params(struct hl_device *hdev) +{ + struct pre_fw_load_props *pre_fw_load = &hdev->fw_loader.pre_fw_load; + + pre_fw_load->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS; + pre_fw_load->sts_boot_dev_sts0_reg = mmCPU_BOOT_DEV_STS0; + pre_fw_load->sts_boot_dev_sts1_reg = mmCPU_BOOT_DEV_STS1; + pre_fw_load->boot_err0_reg = mmCPU_BOOT_ERR0; + pre_fw_load->boot_err1_reg = mmCPU_BOOT_ERR1; + pre_fw_load->wait_for_preboot_timeout = GOYA_BOOT_FIT_REQ_TIMEOUT_USEC; +} + static void goya_init_firmware_loader(struct hl_device *hdev) { struct asic_fixed_properties *prop = &hdev->asic_prop; @@ -2878,7 +2877,7 @@ int goya_suspend(struct hl_device *hdev) { int rc; - rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS); + rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS, 0x0); if (rc) dev_err(hdev->dev, "Failed to disable PCI access from CPU\n"); @@ -3019,7 +3018,7 @@ static void goya_dma_free_coherent(struct hl_device *hdev, size_t size, dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, fixed_dma_handle); } -int goya_scrub_device_mem(struct hl_device *hdev, u64 addr, u64 size) +int goya_scrub_device_mem(struct hl_device *hdev) { return 0; } @@ -3102,8 +3101,7 @@ static int goya_send_job_on_qman0(struct hl_device *hdev, struct hl_cs_job *job) return -EBUSY; } - fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL, - &fence_dma_addr); + fence_ptr = hl_asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL, &fence_dma_addr); if (!fence_ptr) { dev_err(hdev->dev, "Failed to allocate fence memory for QMAN0\n"); @@ -3143,8 +3141,7 @@ static int goya_send_job_on_qman0(struct hl_device *hdev, struct hl_cs_job *job) } free_fence_ptr: - hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr, - fence_dma_addr); + hl_asic_dma_pool_free(hdev, (void *) fence_ptr, fence_dma_addr); goya_qman0_set_security(hdev, false); @@ -3180,8 +3177,7 @@ int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id) fence_val = GOYA_QMAN0_FENCE_VAL; - fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL, - &fence_dma_addr); + fence_ptr = hl_asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL, &fence_dma_addr); if (!fence_ptr) { dev_err(hdev->dev, "Failed to allocate memory for H/W queue %d testing\n", @@ -3191,9 +3187,8 @@ int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id) *fence_ptr = 0; - fence_pkt = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, - sizeof(struct packet_msg_prot), - GFP_KERNEL, &pkt_dma_addr); + fence_pkt = hl_asic_dma_pool_zalloc(hdev, sizeof(struct packet_msg_prot), GFP_KERNEL, + &pkt_dma_addr); if (!fence_pkt) { dev_err(hdev->dev, "Failed to allocate packet for H/W queue %d testing\n", @@ -3232,11 +3227,9 @@ int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id) } free_pkt: - hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_pkt, - pkt_dma_addr); + hl_asic_dma_pool_free(hdev, (void *) fence_pkt, pkt_dma_addr); free_fence_ptr: - hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr, - fence_dma_addr); + hl_asic_dma_pool_free(hdev, (void *) fence_ptr, fence_dma_addr); return rc; } @@ -3403,7 +3396,7 @@ static int goya_validate_dma_pkt_host(struct hl_device *hdev, { u64 device_memory_addr, addr; enum dma_data_direction dir; - enum goya_dma_direction user_dir; + enum hl_goya_dma_direction user_dir; bool sram_addr = true; bool skip_host_mem_pin = false; bool user_memset; @@ -3419,7 +3412,7 @@ static int goya_validate_dma_pkt_host(struct hl_device *hdev, GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT; switch (user_dir) { - case DMA_HOST_TO_DRAM: + case HL_DMA_HOST_TO_DRAM: dev_dbg(hdev->dev, "DMA direction is HOST --> DRAM\n"); dir = DMA_TO_DEVICE; sram_addr = false; @@ -3429,7 +3422,7 @@ static int goya_validate_dma_pkt_host(struct hl_device *hdev, skip_host_mem_pin = true; break; - case DMA_DRAM_TO_HOST: + case HL_DMA_DRAM_TO_HOST: dev_dbg(hdev->dev, "DMA direction is DRAM --> HOST\n"); dir = DMA_FROM_DEVICE; sram_addr = false; @@ -3437,7 +3430,7 @@ static int goya_validate_dma_pkt_host(struct hl_device *hdev, device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); break; - case DMA_HOST_TO_SRAM: + case HL_DMA_HOST_TO_SRAM: dev_dbg(hdev->dev, "DMA direction is HOST --> SRAM\n"); dir = DMA_TO_DEVICE; addr = le64_to_cpu(user_dma_pkt->src_addr); @@ -3446,14 +3439,14 @@ static int goya_validate_dma_pkt_host(struct hl_device *hdev, skip_host_mem_pin = true; break; - case DMA_SRAM_TO_HOST: + case HL_DMA_SRAM_TO_HOST: dev_dbg(hdev->dev, "DMA direction is SRAM --> HOST\n"); dir = DMA_FROM_DEVICE; addr = le64_to_cpu(user_dma_pkt->dst_addr); device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); break; default: - dev_err(hdev->dev, "DMA direction is undefined\n"); + dev_err(hdev->dev, "DMA direction %d is unsupported/undefined\n", user_dir); return -EFAULT; } @@ -3505,14 +3498,14 @@ static int goya_validate_dma_pkt_no_host(struct hl_device *hdev, struct packet_lin_dma *user_dma_pkt) { u64 sram_memory_addr, dram_memory_addr; - enum goya_dma_direction user_dir; + enum hl_goya_dma_direction user_dir; u32 ctl; ctl = le32_to_cpu(user_dma_pkt->ctl); user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >> GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT; - if (user_dir == DMA_DRAM_TO_SRAM) { + if (user_dir == HL_DMA_DRAM_TO_SRAM) { dev_dbg(hdev->dev, "DMA direction is DRAM --> SRAM\n"); dram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); sram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); @@ -3549,7 +3542,7 @@ static int goya_validate_dma_pkt_no_mmu(struct hl_device *hdev, struct hl_cs_parser *parser, struct packet_lin_dma *user_dma_pkt) { - enum goya_dma_direction user_dir; + enum hl_goya_dma_direction user_dir; u32 ctl; int rc; @@ -3574,7 +3567,7 @@ static int goya_validate_dma_pkt_no_mmu(struct hl_device *hdev, return -EINVAL; } - if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM)) + if ((user_dir == HL_DMA_DRAM_TO_SRAM) || (user_dir == HL_DMA_SRAM_TO_DRAM)) rc = goya_validate_dma_pkt_no_host(hdev, parser, user_dma_pkt); else rc = goya_validate_dma_pkt_host(hdev, parser, user_dma_pkt); @@ -3781,7 +3774,7 @@ static int goya_patch_dma_packet(struct hl_device *hdev, u32 count, dma_desc_cnt; u64 len, len_next; dma_addr_t dma_addr, dma_addr_next; - enum goya_dma_direction user_dir; + enum hl_goya_dma_direction user_dir; u64 device_memory_addr, addr; enum dma_data_direction dir; struct sg_table *sgt; @@ -3797,14 +3790,14 @@ static int goya_patch_dma_packet(struct hl_device *hdev, user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >> GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT; - if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM) || + if ((user_dir == HL_DMA_DRAM_TO_SRAM) || (user_dir == HL_DMA_SRAM_TO_DRAM) || (user_dma_pkt->tsize == 0)) { memcpy(new_dma_pkt, user_dma_pkt, sizeof(*new_dma_pkt)); *new_dma_pkt_size = sizeof(*new_dma_pkt); return 0; } - if ((user_dir == DMA_HOST_TO_DRAM) || (user_dir == DMA_HOST_TO_SRAM)) { + if ((user_dir == HL_DMA_HOST_TO_DRAM) || (user_dir == HL_DMA_HOST_TO_SRAM)) { addr = le64_to_cpu(user_dma_pkt->src_addr); device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); dir = DMA_TO_DEVICE; @@ -4166,8 +4159,8 @@ int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser) } void goya_add_end_of_cb_packets(struct hl_device *hdev, void *kernel_address, - u32 len, u64 cq_addr, u32 cq_val, u32 msix_vec, - bool eb) + u32 len, u32 original_len, u64 cq_addr, u32 cq_val, + u32 msix_vec, bool eb) { struct packet_msg_prot *cq_pkt; u32 tmp; @@ -4804,7 +4797,7 @@ static int goya_memset_device_memory(struct hl_device *hdev, u64 addr, u64 size, (1 << GOYA_PKT_LIN_DMA_CTL_WO_SHIFT) | (1 << GOYA_PKT_CTL_RB_SHIFT) | (1 << GOYA_PKT_CTL_MB_SHIFT)); - ctl |= (is_dram ? DMA_HOST_TO_DRAM : DMA_HOST_TO_SRAM) << + ctl |= (is_dram ? HL_DMA_HOST_TO_DRAM : HL_DMA_HOST_TO_SRAM) << GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT; lin_dma_pkt->ctl = cpu_to_le32(ctl); @@ -5268,6 +5261,11 @@ static int goya_ctx_init(struct hl_ctx *ctx) return 0; } +static int goya_pre_schedule_cs(struct hl_cs *cs) +{ + return 0; +} + u32 goya_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx) { return cq_idx; @@ -5347,6 +5345,11 @@ static void goya_enable_events_from_fw(struct hl_device *hdev) GOYA_ASYNC_EVENT_ID_INTS_REGISTER); } +static int goya_ack_mmu_page_fault_or_access_error(struct hl_device *hdev, u64 mmu_cap_mask) +{ + return -EINVAL; +} + static int goya_map_pll_idx_to_fw_idx(u32 pll_idx) { switch (pll_idx) { @@ -5417,17 +5420,15 @@ static u32 *goya_get_stream_master_qid_arr(void) return NULL; } -static void goya_get_valid_dram_page_orders(struct hl_info_dev_memalloc_page_sizes *info) -{ - /* set 0 since multiple pages are not supported */ - info->page_order_bitmask = 0; -} - static int goya_get_monitor_dump(struct hl_device *hdev, void *data) { return -EOPNOTSUPP; } +static void goya_check_if_razwi_happened(struct hl_device *hdev) +{ +} + static int goya_scrub_device_dram(struct hl_device *hdev, u64 val) { return -EOPNOTSUPP; @@ -5461,7 +5462,6 @@ static const struct hl_asic_funcs goya_funcs = { .hl_dma_unmap_sgtable = hl_dma_unmap_sgtable, .cs_parser = goya_cs_parser, .asic_dma_map_sgtable = hl_dma_map_sgtable, - .get_dma_desc_list_size = goya_get_dma_desc_list_size, .add_end_of_cb_packets = goya_add_end_of_cb_packets, .update_eq_ci = goya_update_eq_ci, .context_switch = goya_context_switch, @@ -5481,6 +5481,8 @@ static const struct hl_asic_funcs goya_funcs = { .non_hard_reset_late_init = goya_non_hard_reset_late_init, .hw_queues_lock = goya_hw_queues_lock, .hw_queues_unlock = goya_hw_queues_unlock, + .kdma_lock = NULL, + .kdma_unlock = NULL, .get_pci_id = goya_get_pci_id, .get_eeprom_data = goya_get_eeprom_data, .get_monitor_dump = goya_get_monitor_dump, @@ -5492,6 +5494,7 @@ static const struct hl_asic_funcs goya_funcs = { .halt_coresight = goya_halt_coresight, .ctx_init = goya_ctx_init, .ctx_fini = goya_ctx_fini, + .pre_schedule_cs = goya_pre_schedule_cs, .get_queue_id_for_cq = goya_get_queue_id_for_cq, .load_firmware_to_device = goya_load_firmware_to_device, .load_boot_fit_to_device = goya_load_boot_fit_to_device, @@ -5502,24 +5505,27 @@ static const struct hl_asic_funcs goya_funcs = { .reset_sob = goya_reset_sob, .reset_sob_group = goya_reset_sob_group, .get_device_time = goya_get_device_time, + .pb_print_security_errors = NULL, .collective_wait_init_cs = goya_collective_wait_init_cs, .collective_wait_create_jobs = goya_collective_wait_create_jobs, + .get_dec_base_addr = NULL, .scramble_addr = hl_mmu_scramble_addr, .descramble_addr = hl_mmu_descramble_addr, .ack_protection_bits_errors = goya_ack_protection_bits_errors, .get_hw_block_id = goya_get_hw_block_id, .hw_block_mmap = goya_block_mmap, .enable_events_from_fw = goya_enable_events_from_fw, + .ack_mmu_errors = goya_ack_mmu_page_fault_or_access_error, .map_pll_idx_to_fw_idx = goya_map_pll_idx_to_fw_idx, + .init_firmware_preload_params = goya_init_firmware_preload_params, .init_firmware_loader = goya_init_firmware_loader, .init_cpu_scrambler_dram = goya_cpu_init_scrambler_dram, .state_dump_init = goya_state_dump_init, .get_sob_addr = &goya_get_sob_addr, .set_pci_memory_regions = goya_set_pci_memory_regions, .get_stream_master_qid_arr = goya_get_stream_master_qid_arr, - .is_valid_dram_page_size = NULL, + .check_if_razwi_happened = goya_check_if_razwi_happened, .mmu_get_real_page_size = hl_mmu_get_real_page_size, - .get_valid_dram_page_orders = goya_get_valid_dram_page_orders, .access_dev_mem = hl_access_dev_mem, .set_dram_bar_base = goya_set_ddr_bar_base, }; diff --git a/drivers/misc/habanalabs/goya/goyaP.h b/drivers/misc/habanalabs/goya/goyaP.h index 647f57402616..d6ec43d6f6b0 100644 --- a/drivers/misc/habanalabs/goya/goyaP.h +++ b/drivers/misc/habanalabs/goya/goyaP.h @@ -230,10 +230,10 @@ void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry); void *goya_get_events_stat(struct hl_device *hdev, bool aggregate, u32 *size); void goya_add_end_of_cb_packets(struct hl_device *hdev, void *kernel_address, - u32 len, u64 cq_addr, u32 cq_val, u32 msix_vec, - bool eb); + u32 len, u32 original_len, u64 cq_addr, u32 cq_val, + u32 msix_vec, bool eb); int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser); -int goya_scrub_device_mem(struct hl_device *hdev, u64 addr, u64 size); +int goya_scrub_device_mem(struct hl_device *hdev); void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id, dma_addr_t *dma_handle, u16 *queue_len); u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt); diff --git a/drivers/misc/habanalabs/goya/goya_hwmgr.c b/drivers/misc/habanalabs/goya/goya_hwmgr.c index 6580fc6a486a..b595721751c1 100644 --- a/drivers/misc/habanalabs/goya/goya_hwmgr.c +++ b/drivers/misc/habanalabs/goya/goya_hwmgr.c @@ -359,6 +359,7 @@ static struct attribute *goya_clk_dev_attrs[] = { &dev_attr_pm_mng_profile.attr, &dev_attr_tpc_clk.attr, &dev_attr_tpc_clk_curr.attr, + NULL, }; static ssize_t infineon_ver_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -375,6 +376,7 @@ static DEVICE_ATTR_RO(infineon_ver); static struct attribute *goya_vrm_dev_attrs[] = { &dev_attr_infineon_ver.attr, + NULL, }; void goya_add_device_attr(struct hl_device *hdev, struct attribute_group *dev_clk_attr_grp, diff --git a/drivers/misc/habanalabs/include/common/cpucp_if.h b/drivers/misc/habanalabs/include/common/cpucp_if.h index 38e44b6cf581..abf40e1c4965 100644 --- a/drivers/misc/habanalabs/include/common/cpucp_if.h +++ b/drivers/misc/habanalabs/include/common/cpucp_if.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright 2020-2021 HabanaLabs, Ltd. + * Copyright 2020-2022 HabanaLabs, Ltd. * All Rights Reserved. * */ @@ -68,7 +68,8 @@ struct hl_eq_ecc_data { __le64 ecc_address; __le64 ecc_syndrom; __u8 memory_wrapper_idx; - __u8 pad[7]; + __u8 is_critical; + __u8 pad[6]; }; enum hl_sm_sei_cause { @@ -98,27 +99,265 @@ struct hl_eq_fw_alive { __u8 pad[7]; }; -enum hl_pcie_addr_dec_cause { - PCIE_ADDR_DEC_HBW_ERR_RESP, - PCIE_ADDR_DEC_LBW_ERR_RESP, - PCIE_ADDR_DEC_TLP_BLOCKED_BY_RR +struct hl_eq_intr_cause { + __le64 intr_cause_data; }; -struct hl_eq_pcie_addr_dec_data { - /* enum hl_pcie_addr_dec_cause */ - __u8 addr_dec_cause; - __u8 pad[7]; +struct hl_eq_pcie_drain_ind_data { + struct hl_eq_intr_cause intr_cause; + __le64 drain_wr_addr_lbw; + __le64 drain_rd_addr_lbw; + __le64 drain_wr_addr_hbw; + __le64 drain_rd_addr_hbw; +}; + +struct hl_eq_razwi_lbw_info_regs { + __le32 rr_aw_razwi_reg; + __le32 rr_aw_razwi_id_reg; + __le32 rr_ar_razwi_reg; + __le32 rr_ar_razwi_id_reg; +}; + +struct hl_eq_razwi_hbw_info_regs { + __le32 rr_aw_razwi_hi_reg; + __le32 rr_aw_razwi_lo_reg; + __le32 rr_aw_razwi_id_reg; + __le32 rr_ar_razwi_hi_reg; + __le32 rr_ar_razwi_lo_reg; + __le32 rr_ar_razwi_id_reg; +}; + +/* razwi_happened masks */ +#define RAZWI_HAPPENED_HBW 0x1 +#define RAZWI_HAPPENED_LBW 0x2 +#define RAZWI_HAPPENED_AW 0x4 +#define RAZWI_HAPPENED_AR 0x8 + +struct hl_eq_razwi_info { + __le32 razwi_happened_mask; + union { + struct hl_eq_razwi_lbw_info_regs lbw; + struct hl_eq_razwi_hbw_info_regs hbw; + }; + __le32 pad; +}; + +struct hl_eq_razwi_with_intr_cause { + struct hl_eq_razwi_info razwi_info; + struct hl_eq_intr_cause intr_cause; +}; + +#define HBM_CA_ERR_CMD_LIFO_LEN 8 +#define HBM_RD_ERR_DATA_LIFO_LEN 8 +#define HBM_WR_PAR_CMD_LIFO_LEN 11 + +enum hl_hbm_sei_cause { + /* Command/address parity error event is split into 2 events due to + * size limitation: ODD suffix for odd HBM CK_t cycles and EVEN suffix + * for even HBM CK_t cycles + */ + HBM_SEI_CMD_PARITY_EVEN, + HBM_SEI_CMD_PARITY_ODD, + /* Read errors can be reflected as a combination of SERR/DERR/parity + * errors. Therefore, we define one event for all read error types. + * LKD will perform further proccessing. + */ + HBM_SEI_READ_ERR, + HBM_SEI_WRITE_DATA_PARITY_ERR, + HBM_SEI_CATTRIP, + HBM_SEI_MEM_BIST_FAIL, + HBM_SEI_DFI, + HBM_SEI_INV_TEMP_READ_OUT, + HBM_SEI_BIST_FAIL, +}; + +/* Masks for parsing hl_hbm_sei_headr fields */ +#define HBM_ECC_SERR_CNTR_MASK 0xFF +#define HBM_ECC_DERR_CNTR_MASK 0xFF00 +#define HBM_RD_PARITY_CNTR_MASK 0xFF0000 + +/* HBM index and MC index are known by the event_id */ +struct hl_hbm_sei_header { + union { + /* relevant only in case of HBM read error */ + struct { + __u8 ecc_serr_cnt; + __u8 ecc_derr_cnt; + __u8 read_par_cnt; + __u8 reserved; + }; + /* All other cases */ + __le32 cnt; + }; + __u8 sei_cause; /* enum hl_hbm_sei_cause */ + __u8 mc_channel; /* range: 0-3 */ + __u8 mc_pseudo_channel; /* range: 0-7 */ + __u8 is_critical; +}; + +#define HBM_RD_ADDR_SID_SHIFT 0 +#define HBM_RD_ADDR_SID_MASK 0x1 +#define HBM_RD_ADDR_BG_SHIFT 1 +#define HBM_RD_ADDR_BG_MASK 0x6 +#define HBM_RD_ADDR_BA_SHIFT 3 +#define HBM_RD_ADDR_BA_MASK 0x18 +#define HBM_RD_ADDR_COL_SHIFT 5 +#define HBM_RD_ADDR_COL_MASK 0x7E0 +#define HBM_RD_ADDR_ROW_SHIFT 11 +#define HBM_RD_ADDR_ROW_MASK 0x3FFF800 + +struct hbm_rd_addr { + union { + /* bit fields are only for FW use */ + struct { + u32 dbg_rd_err_addr_sid:1; + u32 dbg_rd_err_addr_bg:2; + u32 dbg_rd_err_addr_ba:2; + u32 dbg_rd_err_addr_col:6; + u32 dbg_rd_err_addr_row:15; + u32 reserved:6; + }; + __le32 rd_addr_val; + }; +}; + +#define HBM_RD_ERR_BEAT_SHIFT 2 +/* dbg_rd_err_misc fields: */ +/* Read parity is calculated per DW on every beat */ +#define HBM_RD_ERR_PAR_ERR_BEAT0_SHIFT 0 +#define HBM_RD_ERR_PAR_ERR_BEAT0_MASK 0x3 +#define HBM_RD_ERR_PAR_DATA_BEAT0_SHIFT 8 +#define HBM_RD_ERR_PAR_DATA_BEAT0_MASK 0x300 +/* ECC is calculated per PC on every beat */ +#define HBM_RD_ERR_SERR_BEAT0_SHIFT 16 +#define HBM_RD_ERR_SERR_BEAT0_MASK 0x10000 +#define HBM_RD_ERR_DERR_BEAT0_SHIFT 24 +#define HBM_RD_ERR_DERR_BEAT0_MASK 0x100000 + +struct hl_eq_hbm_sei_read_err_intr_info { + /* DFI_RD_ERR_REP_ADDR */ + struct hbm_rd_addr dbg_rd_err_addr; + /* DFI_RD_ERR_REP_ERR */ + union { + struct { + /* bit fields are only for FW use */ + u32 dbg_rd_err_par:8; + u32 dbg_rd_err_par_data:8; + u32 dbg_rd_err_serr:4; + u32 dbg_rd_err_derr:4; + u32 reserved:8; + }; + __le32 dbg_rd_err_misc; + }; + /* DFI_RD_ERR_REP_DM */ + __le32 dbg_rd_err_dm; + /* DFI_RD_ERR_REP_SYNDROME */ + __le32 dbg_rd_err_syndrome; + /* DFI_RD_ERR_REP_DATA */ + __le32 dbg_rd_err_data[HBM_RD_ERR_DATA_LIFO_LEN]; +}; + +struct hl_eq_hbm_sei_ca_par_intr_info { + /* 14 LSBs */ + __le16 dbg_row[HBM_CA_ERR_CMD_LIFO_LEN]; + /* 18 LSBs */ + __le32 dbg_col[HBM_CA_ERR_CMD_LIFO_LEN]; +}; + +#define WR_PAR_LAST_CMD_COL_SHIFT 0 +#define WR_PAR_LAST_CMD_COL_MASK 0x3F +#define WR_PAR_LAST_CMD_BG_SHIFT 6 +#define WR_PAR_LAST_CMD_BG_MASK 0xC0 +#define WR_PAR_LAST_CMD_BA_SHIFT 8 +#define WR_PAR_LAST_CMD_BA_MASK 0x300 +#define WR_PAR_LAST_CMD_SID_SHIFT 10 +#define WR_PAR_LAST_CMD_SID_MASK 0x400 + +/* Row address isn't latched */ +struct hbm_sei_wr_cmd_address { + /* DFI_DERR_LAST_CMD */ + union { + struct { + /* bit fields are only for FW use */ + u32 col:6; + u32 bg:2; + u32 ba:2; + u32 sid:1; + u32 reserved:21; + }; + __le32 dbg_wr_cmd_addr; + }; +}; + +struct hl_eq_hbm_sei_wr_par_intr_info { + /* entry 0: WR command address from the 1st cycle prior to the error + * entry 1: WR command address from the 2nd cycle prior to the error + * and so on... + */ + struct hbm_sei_wr_cmd_address dbg_last_wr_cmds[HBM_WR_PAR_CMD_LIFO_LEN]; + /* derr[0:1] - 1st HBM cycle DERR output + * derr[2:3] - 2nd HBM cycle DERR output + */ + __u8 dbg_derr; + /* extend to reach 8B */ + __u8 pad[3]; +}; + +/* + * this struct represents the following sei causes: + * command parity, ECC double error, ECC single error, dfi error, cattrip, + * temperature read-out, read parity error and write parity error. + * some only use the header while some have extra data. + */ +struct hl_eq_hbm_sei_data { + struct hl_hbm_sei_header hdr; + union { + struct hl_eq_hbm_sei_ca_par_intr_info ca_parity_even_info; + struct hl_eq_hbm_sei_ca_par_intr_info ca_parity_odd_info; + struct hl_eq_hbm_sei_read_err_intr_info read_err_info; + struct hl_eq_hbm_sei_wr_par_intr_info wr_parity_info; + }; +}; + +/* Engine/farm arc interrupt type */ +enum hl_engine_arc_interrupt_type { + /* Qman/farm ARC DCCM QUEUE FULL interrupt type */ + ENGINE_ARC_DCCM_QUEUE_FULL_IRQ = 1 +}; + +/* Data structure specifies details of payload of DCCM QUEUE FULL interrupt */ +struct hl_engine_arc_dccm_queue_full_irq { + /* Queue index value which caused DCCM QUEUE FULL */ + __le32 queue_index; + __le32 pad; +}; + +/* Data structure specifies details of QM/FARM ARC interrupt */ +struct hl_eq_engine_arc_intr_data { + /* ARC engine id e.g. DCORE0_TPC0_QM_ARC, DCORE0_TCP1_QM_ARC */ + __le32 engine_id; + __le32 intr_type; /* enum hl_engine_arc_interrupt_type */ + /* More info related to the interrupt e.g. queue index + * incase of DCCM_QUEUE_FULL interrupt. + */ + __le64 payload; + __le64 pad[5]; }; struct hl_eq_entry { struct hl_eq_header hdr; union { struct hl_eq_ecc_data ecc_data; - struct hl_eq_hbm_ecc_data hbm_ecc_data; + struct hl_eq_hbm_ecc_data hbm_ecc_data; /* Gaudi1 HBM */ struct hl_eq_sm_sei_data sm_sei_data; struct cpucp_pkt_sync_err pkt_sync_err; struct hl_eq_fw_alive fw_alive; - struct hl_eq_pcie_addr_dec_data pcie_addr_dec_data; + struct hl_eq_intr_cause intr_cause; + struct hl_eq_pcie_drain_ind_data pcie_drain_ind_data; + struct hl_eq_razwi_info razwi_info; + struct hl_eq_razwi_with_intr_cause razwi_with_intr_cause; + struct hl_eq_hbm_sei_data sei_data; /* Gaudi2 HBM */ + struct hl_eq_engine_arc_intr_data arc_data; __le64 data[7]; }; }; @@ -792,10 +1031,23 @@ struct cpucp_security_info { * @infineon_second_stage_version: Infineon 2nd stage DC-DC version. * @dram_size: available DRAM size. * @card_name: card name that will be displayed in HWMON subsystem on the host + * @tpc_binning_mask: TPC binning mask, 1 bit per TPC instance + * (0 = functional, 1 = binned) + * @decoder_binning_mask: Decoder binning mask, 1 bit per decoder instance + * (0 = functional, 1 = binned), maximum 1 per dcore + * @sram_binning: Categorize SRAM functionality + * (0 = fully functional, 1 = lower-half is not functional, + * 2 = upper-half is not functional) * @sec_info: security information * @pll_map: Bit map of supported PLLs for current ASIC version. * @mme_binning_mask: MME binning mask, - * (0 = functional, 1 = binned) + * bits [0:6] <==> dcore0 mme fma + * bits [7:13] <==> dcore1 mme fma + * bits [14:20] <==> dcore0 mme ima + * bits [21:27] <==> dcore1 mme ima + * For each group, if the 6th bit is set then first 5 bits + * represent the col's idx [0-31], otherwise these bits are + * ignored, and col idx 32 is binned. 7th bit is don't care. * @dram_binning_mask: DRAM binning mask, 1 bit per dram instance * (0 = functional 1 = binned) * @memory_repair_flag: eFuse flag indicating memory repair @@ -803,6 +1055,8 @@ struct cpucp_security_info { * (0 = functional 1 = binned) * @xbar_binning_mask: Xbar binning mask, 1 bit per Xbar instance * (0 = functional 1 = binned) + * @interposer_version: Interposer version programmed in eFuse + * @substrate_version: Substrate version programmed in eFuse * @fw_os_version: Firmware OS Version */ struct cpucp_info { @@ -819,16 +1073,18 @@ struct cpucp_info { __le32 infineon_second_stage_version; __le64 dram_size; char card_name[CARD_NAME_MAX_LEN]; - __le64 reserved3; - __le64 reserved4; - __u8 reserved5; + __le64 tpc_binning_mask; + __le64 decoder_binning_mask; + __u8 sram_binning; __u8 dram_binning_mask; __u8 memory_repair_flag; __u8 edma_binning_mask; __u8 xbar_binning_mask; - __u8 pad[3]; + __u8 interposer_version; + __u8 substrate_version; + __u8 reserved2; struct cpucp_security_info sec_info; - __le32 reserved6; + __le32 reserved3; __u8 pll_map[PLL_MAP_LEN]; __le64 mme_binning_mask; __u8 fw_os_version[VERSION_MAX_LEN]; @@ -932,6 +1188,11 @@ struct cpucp_hbm_row_replaced_rows_info { struct cpucp_hbm_row_info replaced_rows[CPUCP_HBM_ROW_REPLACE_MAX]; }; +enum cpu_reset_status { + CPU_RST_STATUS_NA = 0, + CPU_RST_STATUS_SOFT_RST_DONE = 1, +}; + /* * struct dcore_monitor_regs_data - DCORE monitor regs data. * the structure follows sync manager block layout. relevant only to Gaudi. diff --git a/drivers/misc/habanalabs/include/common/hl_boot_if.h b/drivers/misc/habanalabs/include/common/hl_boot_if.h index 15f91ae9de6e..a3594119bc51 100644 --- a/drivers/misc/habanalabs/include/common/hl_boot_if.h +++ b/drivers/misc/habanalabs/include/common/hl_boot_if.h @@ -525,6 +525,13 @@ struct lkd_fw_comms_msg { struct { __u8 fw_cfg_skip; /* 1 - skip, 0 - don't skip */ }; + struct { + __le64 tpc_binning_conf; + __le32 dec_binning_conf; + __le32 hbm_binning_conf; + __le32 edma_binning_conf; + __le32 mme_redundancy_conf; /* use MME_REDUNDANT_COLUMN */ + }; }; }; diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_masks.h b/drivers/misc/habanalabs/include/gaudi/gaudi_masks.h index acc85d3ed98b..880c57b26c63 100644 --- a/drivers/misc/habanalabs/include/gaudi/gaudi_masks.h +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_masks.h @@ -444,6 +444,7 @@ enum axi_id { #define QM_ARB_ERR_MSG_EN_MASK (\ QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK |\ + QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK |\ QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK) #define PCIE_AUX_FLR_CTRL_HW_CTRL_MASK 0x1 diff --git a/drivers/misc/habanalabs/include/gaudi2/arc/gaudi2_arc_common_packets.h b/drivers/misc/habanalabs/include/gaudi2/arc/gaudi2_arc_common_packets.h new file mode 100644 index 000000000000..2cf30c206ac6 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/arc/gaudi2_arc_common_packets.h @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 HabanaLabs Ltd. + * All Rights Reserved. + */ + +#ifndef __GAUDI2_ARC_COMMON_PACKETS_H__ +#define __GAUDI2_ARC_COMMON_PACKETS_H__ + +/* + * CPU IDs for each ARC CPUs + */ + +#define CPU_ID_SCHED_ARC0 0 /* FARM_ARC0 */ +#define CPU_ID_SCHED_ARC1 1 /* FARM_ARC1 */ +#define CPU_ID_SCHED_ARC2 2 /* FARM_ARC2 */ +#define CPU_ID_SCHED_ARC3 3 /* FARM_ARC3 */ +/* Dcore1 MME Engine ARC instance used as scheduler */ +#define CPU_ID_SCHED_ARC4 4 /* DCORE1_MME0 */ +/* Dcore3 MME Engine ARC instance used as scheduler */ +#define CPU_ID_SCHED_ARC5 5 /* DCORE3_MME0 */ + +#define CPU_ID_TPC_QMAN_ARC0 6 /* DCORE0_TPC0 */ +#define CPU_ID_TPC_QMAN_ARC1 7 /* DCORE0_TPC1 */ +#define CPU_ID_TPC_QMAN_ARC2 8 /* DCORE0_TPC2 */ +#define CPU_ID_TPC_QMAN_ARC3 9 /* DCORE0_TPC3 */ +#define CPU_ID_TPC_QMAN_ARC4 10 /* DCORE0_TPC4 */ +#define CPU_ID_TPC_QMAN_ARC5 11 /* DCORE0_TPC5 */ +#define CPU_ID_TPC_QMAN_ARC6 12 /* DCORE1_TPC0 */ +#define CPU_ID_TPC_QMAN_ARC7 13 /* DCORE1_TPC1 */ +#define CPU_ID_TPC_QMAN_ARC8 14 /* DCORE1_TPC2 */ +#define CPU_ID_TPC_QMAN_ARC9 15 /* DCORE1_TPC3 */ +#define CPU_ID_TPC_QMAN_ARC10 16 /* DCORE1_TPC4 */ +#define CPU_ID_TPC_QMAN_ARC11 17 /* DCORE1_TPC5 */ +#define CPU_ID_TPC_QMAN_ARC12 18 /* DCORE2_TPC0 */ +#define CPU_ID_TPC_QMAN_ARC13 19 /* DCORE2_TPC1 */ +#define CPU_ID_TPC_QMAN_ARC14 20 /* DCORE2_TPC2 */ +#define CPU_ID_TPC_QMAN_ARC15 21 /* DCORE2_TPC3 */ +#define CPU_ID_TPC_QMAN_ARC16 22 /* DCORE2_TPC4 */ +#define CPU_ID_TPC_QMAN_ARC17 23 /* DCORE2_TPC5 */ +#define CPU_ID_TPC_QMAN_ARC18 24 /* DCORE3_TPC0 */ +#define CPU_ID_TPC_QMAN_ARC19 25 /* DCORE3_TPC1 */ +#define CPU_ID_TPC_QMAN_ARC20 26 /* DCORE3_TPC2 */ +#define CPU_ID_TPC_QMAN_ARC21 27 /* DCORE3_TPC3 */ +#define CPU_ID_TPC_QMAN_ARC22 28 /* DCORE3_TPC4 */ +#define CPU_ID_TPC_QMAN_ARC23 29 /* DCORE3_TPC5 */ +#define CPU_ID_TPC_QMAN_ARC24 30 /* DCORE0_TPC6 - Never present */ + +#define CPU_ID_MME_QMAN_ARC0 31 /* DCORE0_MME0 */ +#define CPU_ID_MME_QMAN_ARC1 32 /* DCORE2_MME0 */ + +#define CPU_ID_EDMA_QMAN_ARC0 33 /* DCORE0_EDMA0 */ +#define CPU_ID_EDMA_QMAN_ARC1 34 /* DCORE0_EDMA1 */ +#define CPU_ID_EDMA_QMAN_ARC2 35 /* DCORE1_EDMA0 */ +#define CPU_ID_EDMA_QMAN_ARC3 36 /* DCORE1_EDMA1 */ +#define CPU_ID_EDMA_QMAN_ARC4 37 /* DCORE2_EDMA0 */ +#define CPU_ID_EDMA_QMAN_ARC5 38 /* DCORE2_EDMA1 */ +#define CPU_ID_EDMA_QMAN_ARC6 39 /* DCORE3_EDMA0 */ +#define CPU_ID_EDMA_QMAN_ARC7 40 /* DCORE3_EDMA1 */ + +#define CPU_ID_PDMA_QMAN_ARC0 41 /* DCORE0_PDMA0 */ +#define CPU_ID_PDMA_QMAN_ARC1 42 /* DCORE0_PDMA1 */ + +#define CPU_ID_ROT_QMAN_ARC0 43 /* ROT0 */ +#define CPU_ID_ROT_QMAN_ARC1 44 /* ROT1 */ + +#define CPU_ID_NIC_QMAN_ARC0 45 /* NIC0_0 */ +#define CPU_ID_NIC_QMAN_ARC1 46 /* NIC0_1 */ +#define CPU_ID_NIC_QMAN_ARC2 47 /* NIC1_0 */ +#define CPU_ID_NIC_QMAN_ARC3 48 /* NIC1_1 */ +#define CPU_ID_NIC_QMAN_ARC4 49 /* NIC2_0 */ +#define CPU_ID_NIC_QMAN_ARC5 50 /* NIC2_1 */ +#define CPU_ID_NIC_QMAN_ARC6 51 /* NIC3_0 */ +#define CPU_ID_NIC_QMAN_ARC7 52 /* NIC3_1 */ +#define CPU_ID_NIC_QMAN_ARC8 53 /* NIC4_0 */ +#define CPU_ID_NIC_QMAN_ARC9 54 /* NIC4_1 */ +#define CPU_ID_NIC_QMAN_ARC10 55 /* NIC5_0 */ +#define CPU_ID_NIC_QMAN_ARC11 56 /* NIC5_1 */ +#define CPU_ID_NIC_QMAN_ARC12 57 /* NIC6_0 */ +#define CPU_ID_NIC_QMAN_ARC13 58 /* NIC6_1 */ +#define CPU_ID_NIC_QMAN_ARC14 59 /* NIC7_0 */ +#define CPU_ID_NIC_QMAN_ARC15 60 /* NIC7_1 */ +#define CPU_ID_NIC_QMAN_ARC16 61 /* NIC8_0 */ +#define CPU_ID_NIC_QMAN_ARC17 62 /* NIC8_1 */ +#define CPU_ID_NIC_QMAN_ARC18 63 /* NIC9_0 */ +#define CPU_ID_NIC_QMAN_ARC19 64 /* NIC9_1 */ +#define CPU_ID_NIC_QMAN_ARC20 65 /* NIC10_0 */ +#define CPU_ID_NIC_QMAN_ARC21 66 /* NIC10_1 */ +#define CPU_ID_NIC_QMAN_ARC22 67 /* NIC11_0 */ +#define CPU_ID_NIC_QMAN_ARC23 68 /* NIC11_1 */ + +#define CPU_ID_MAX 69 +#define CPU_ID_SCHED_MAX 6 + +#define CPU_ID_ALL 0xFE +#define CPU_ID_INVALID 0xFF + +enum arc_regions_t { + ARC_REGION0_UNSED = 0, + /* + * Extension registers + * None + */ + ARC_REGION1_SRAM = 1, + /* + * Extension registers + * AUX_SRAM_LSB_ADDR + * AUX_SRAM_MSB_ADDR + * ARC Address: 0x1000_0000 + */ + ARC_REGION2_CFG = 2, + /* + * Extension registers + * AUX_CFG_LSB_ADDR + * AUX_CFG_MSB_ADDR + * ARC Address: 0x2000_0000 + */ + ARC_REGION3_GENERAL = 3, + /* + * Extension registers + * AUX_GENERAL_PURPOSE_LSB_ADDR_0 + * AUX_GENERAL_PURPOSE_MSB_ADDR_0 + * ARC Address: 0x3000_0000 + */ + ARC_REGION4_HBM0_FW = 4, + /* + * Extension registers + * AUX_HBM0_LSB_ADDR + * AUX_HBM0_MSB_ADDR + * AUX_HBM0_OFFSET + * ARC Address: 0x4000_0000 + */ + ARC_REGION5_HBM1_GC_DATA = 5, + /* + * Extension registers + * AUX_HBM1_LSB_ADDR + * AUX_HBM1_MSB_ADDR + * AUX_HBM1_OFFSET + * ARC Address: 0x5000_0000 + */ + ARC_REGION6_HBM2_GC_DATA = 6, + /* + * Extension registers + * AUX_HBM2_LSB_ADDR + * AUX_HBM2_MSB_ADDR + * AUX_HBM2_OFFSET + * ARC Address: 0x6000_0000 + */ + ARC_REGION7_HBM3_GC_DATA = 7, + /* + * Extension registers + * AUX_HBM3_LSB_ADDR + * AUX_HBM3_MSB_ADDR + * AUX_HBM3_OFFSET + * ARC Address: 0x7000_0000 + */ + ARC_REGION8_DCCM = 8, + /* + * Extension registers + * None + * ARC Address: 0x8000_0000 + */ + ARC_REGION9_PCIE = 9, + /* + * Extension registers + * AUX_PCIE_LSB_ADDR + * AUX_PCIE_MSB_ADDR + * ARC Address: 0x9000_0000 + */ + ARC_REGION10_GENERAL = 10, + /* + * Extension registers + * AUX_GENERAL_PURPOSE_LSB_ADDR_1 + * AUX_GENERAL_PURPOSE_MSB_ADDR_1 + * ARC Address: 0xA000_0000 + */ + ARC_REGION11_GENERAL = 11, + /* + * Extension registers + * AUX_GENERAL_PURPOSE_LSB_ADDR_2 + * AUX_GENERAL_PURPOSE_MSB_ADDR_2 + * ARC Address: 0xB000_0000 + */ + ARC_REGION12_GENERAL = 12, + /* + * Extension registers + * AUX_GENERAL_PURPOSE_LSB_ADDR_3 + * AUX_GENERAL_PURPOSE_MSB_ADDR_3 + * ARC Address: 0xC000_0000 + */ + ARC_REGION13_GENERAL = 13, + /* + * Extension registers + * AUX_GENERAL_PURPOSE_LSB_ADDR_4 + * AUX_GENERAL_PURPOSE_MSB_ADDR_4 + * ARC Address: 0xD000_0000 + */ + ARC_REGION14_GENERAL = 14, + /* + * Extension registers + * AUX_GENERAL_PURPOSE_LSB_ADDR_5 + * AUX_GENERAL_PURPOSE_MSB_ADDR_5 + * ARC Address: 0xE000_0000 + */ + ARC_REGION15_LBU = 15 + /* + * Extension registers + * None + * ARC Address: 0xF000_0000 + */ +}; + +#endif /* __GAUDI2_ARC_COMMON_PACKETS_H__ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_acp_eng_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_acp_eng_regs.h new file mode 100644 index 000000000000..1974df13b5f9 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_acp_eng_regs.h @@ -0,0 +1,567 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ARC_FARM_ARC0_ACP_ENG_REGS_H_ +#define ASIC_REG_ARC_FARM_ARC0_ACP_ENG_REGS_H_ + +/* + ***************************************** + * ARC_FARM_ARC0_ACP_ENG + * (Prototype: ARC_ACP_ENG) + ***************************************** + */ + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_0 0x4E8F000 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_1 0x4E8F004 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_2 0x4E8F008 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_3 0x4E8F00C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_4 0x4E8F010 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_5 0x4E8F014 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_6 0x4E8F018 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_7 0x4E8F01C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_8 0x4E8F020 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_9 0x4E8F024 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_10 0x4E8F028 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_11 0x4E8F02C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_12 0x4E8F030 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_13 0x4E8F034 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_14 0x4E8F038 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_15 0x4E8F03C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_16 0x4E8F040 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_17 0x4E8F044 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_18 0x4E8F048 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_19 0x4E8F04C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_20 0x4E8F050 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_21 0x4E8F054 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_22 0x4E8F058 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_23 0x4E8F05C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_24 0x4E8F060 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_25 0x4E8F064 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_26 0x4E8F068 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_27 0x4E8F06C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_28 0x4E8F070 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_29 0x4E8F074 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_30 0x4E8F078 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_31 0x4E8F07C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_32 0x4E8F080 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_33 0x4E8F084 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_34 0x4E8F088 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_35 0x4E8F08C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_36 0x4E8F090 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_37 0x4E8F094 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_38 0x4E8F098 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_39 0x4E8F09C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_40 0x4E8F0A0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_41 0x4E8F0A4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_42 0x4E8F0A8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_43 0x4E8F0AC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_44 0x4E8F0B0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_45 0x4E8F0B4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_46 0x4E8F0B8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_47 0x4E8F0BC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_48 0x4E8F0C0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_49 0x4E8F0C4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_50 0x4E8F0C8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_51 0x4E8F0CC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_52 0x4E8F0D0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_53 0x4E8F0D4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_54 0x4E8F0D8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_55 0x4E8F0DC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_56 0x4E8F0E0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_57 0x4E8F0E4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_58 0x4E8F0E8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_59 0x4E8F0EC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_60 0x4E8F0F0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_61 0x4E8F0F4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_62 0x4E8F0F8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_63 0x4E8F0FC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_0 0x4E8F100 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_1 0x4E8F104 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_2 0x4E8F108 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_3 0x4E8F10C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_4 0x4E8F110 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_5 0x4E8F114 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_6 0x4E8F118 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_7 0x4E8F11C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_8 0x4E8F120 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_9 0x4E8F124 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_10 0x4E8F128 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_11 0x4E8F12C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_12 0x4E8F130 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_13 0x4E8F134 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_14 0x4E8F138 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_15 0x4E8F13C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_16 0x4E8F140 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_17 0x4E8F144 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_18 0x4E8F148 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_19 0x4E8F14C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_20 0x4E8F150 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_21 0x4E8F154 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_22 0x4E8F158 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_23 0x4E8F15C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_24 0x4E8F160 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_25 0x4E8F164 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_26 0x4E8F168 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_27 0x4E8F16C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_28 0x4E8F170 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_29 0x4E8F174 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_30 0x4E8F178 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_31 0x4E8F17C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_32 0x4E8F180 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_33 0x4E8F184 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_34 0x4E8F188 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_35 0x4E8F18C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_36 0x4E8F190 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_37 0x4E8F194 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_38 0x4E8F198 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_39 0x4E8F19C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_40 0x4E8F1A0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_41 0x4E8F1A4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_42 0x4E8F1A8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_43 0x4E8F1AC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_44 0x4E8F1B0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_45 0x4E8F1B4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_46 0x4E8F1B8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_47 0x4E8F1BC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_48 0x4E8F1C0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_49 0x4E8F1C4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_50 0x4E8F1C8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_51 0x4E8F1CC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_52 0x4E8F1D0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_53 0x4E8F1D4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_54 0x4E8F1D8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_55 0x4E8F1DC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_56 0x4E8F1E0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_57 0x4E8F1E4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_58 0x4E8F1E8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_59 0x4E8F1EC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_60 0x4E8F1F0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_61 0x4E8F1F4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_62 0x4E8F1F8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_63 0x4E8F1FC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_0 0x4E8F200 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_1 0x4E8F204 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_2 0x4E8F208 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_3 0x4E8F20C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_4 0x4E8F210 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_5 0x4E8F214 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_6 0x4E8F218 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_7 0x4E8F21C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_8 0x4E8F220 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_9 0x4E8F224 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_10 0x4E8F228 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_11 0x4E8F22C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_12 0x4E8F230 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_13 0x4E8F234 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_14 0x4E8F238 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_15 0x4E8F23C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_16 0x4E8F240 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_17 0x4E8F244 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_18 0x4E8F248 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_19 0x4E8F24C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_20 0x4E8F250 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_21 0x4E8F254 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_22 0x4E8F258 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_23 0x4E8F25C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_24 0x4E8F260 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_25 0x4E8F264 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_26 0x4E8F268 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_27 0x4E8F26C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_28 0x4E8F270 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_29 0x4E8F274 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_30 0x4E8F278 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_31 0x4E8F27C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_32 0x4E8F280 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_33 0x4E8F284 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_34 0x4E8F288 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_35 0x4E8F28C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_36 0x4E8F290 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_37 0x4E8F294 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_38 0x4E8F298 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_39 0x4E8F29C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_40 0x4E8F2A0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_41 0x4E8F2A4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_42 0x4E8F2A8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_43 0x4E8F2AC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_44 0x4E8F2B0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_45 0x4E8F2B4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_46 0x4E8F2B8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_47 0x4E8F2BC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_48 0x4E8F2C0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_49 0x4E8F2C4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_50 0x4E8F2C8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_51 0x4E8F2CC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_52 0x4E8F2D0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_53 0x4E8F2D4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_54 0x4E8F2D8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_55 0x4E8F2DC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_56 0x4E8F2E0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_57 0x4E8F2E4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_58 0x4E8F2E8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_59 0x4E8F2EC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_60 0x4E8F2F0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_61 0x4E8F2F4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_62 0x4E8F2F8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_63 0x4E8F2FC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_0 0x4E8F300 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_1 0x4E8F304 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_2 0x4E8F308 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_3 0x4E8F30C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_4 0x4E8F310 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_5 0x4E8F314 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_6 0x4E8F318 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_7 0x4E8F31C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_8 0x4E8F320 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_9 0x4E8F324 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_10 0x4E8F328 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_11 0x4E8F32C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_12 0x4E8F330 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_13 0x4E8F334 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_14 0x4E8F338 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_15 0x4E8F33C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_16 0x4E8F340 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_17 0x4E8F344 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_18 0x4E8F348 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_19 0x4E8F34C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_20 0x4E8F350 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_21 0x4E8F354 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_22 0x4E8F358 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_23 0x4E8F35C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_24 0x4E8F360 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_25 0x4E8F364 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_26 0x4E8F368 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_27 0x4E8F36C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_28 0x4E8F370 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_29 0x4E8F374 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_30 0x4E8F378 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_31 0x4E8F37C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_32 0x4E8F380 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_33 0x4E8F384 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_34 0x4E8F388 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_35 0x4E8F38C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_36 0x4E8F390 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_37 0x4E8F394 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_38 0x4E8F398 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_39 0x4E8F39C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_40 0x4E8F3A0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_41 0x4E8F3A4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_42 0x4E8F3A8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_43 0x4E8F3AC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_44 0x4E8F3B0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_45 0x4E8F3B4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_46 0x4E8F3B8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_47 0x4E8F3BC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_48 0x4E8F3C0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_49 0x4E8F3C4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_50 0x4E8F3C8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_51 0x4E8F3CC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_52 0x4E8F3D0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_53 0x4E8F3D4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_54 0x4E8F3D8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_55 0x4E8F3DC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_56 0x4E8F3E0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_57 0x4E8F3E4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_58 0x4E8F3E8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_59 0x4E8F3EC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_60 0x4E8F3F0 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_61 0x4E8F3F4 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_62 0x4E8F3F8 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_63 0x4E8F3FC + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_SELECTED_QUEUE_ID 0x4E8F400 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_0 0x4E8F404 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_1 0x4E8F408 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_2 0x4E8F40C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_0 0x4E8F410 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_1 0x4E8F414 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_2 0x4E8F418 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_0 0x4E8F41C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_1 0x4E8F420 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_2 0x4E8F424 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_3 0x4E8F428 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_RD_CNT_0 0x4E8F42C + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_RD_CNT_1 0x4E8F430 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_RD_CNT_2 0x4E8F434 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_RD_CNT_3 0x4E8F438 + +#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_REG 0x4E8F43C + +#endif /* ASIC_REG_ARC_FARM_ARC0_ACP_ENG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_aux_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_aux_masks.h new file mode 100644 index 000000000000..fc2c52af6509 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_aux_masks.h @@ -0,0 +1,819 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ARC_FARM_ARC0_AUX_MASKS_H_ +#define ASIC_REG_ARC_FARM_ARC0_AUX_MASKS_H_ + +/* + ***************************************** + * ARC_FARM_ARC0_AUX + * (Prototype: QMAN_ARC_AUX) + ***************************************** + */ + +/* ARC_FARM_ARC0_AUX_RUN_HALT_REQ */ +#define ARC_FARM_ARC0_AUX_RUN_HALT_REQ_RUN_REQ_SHIFT 0 +#define ARC_FARM_ARC0_AUX_RUN_HALT_REQ_RUN_REQ_MASK 0x1 +#define ARC_FARM_ARC0_AUX_RUN_HALT_REQ_HALT_REQ_SHIFT 1 +#define ARC_FARM_ARC0_AUX_RUN_HALT_REQ_HALT_REQ_MASK 0x2 + +/* ARC_FARM_ARC0_AUX_RUN_HALT_ACK */ +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_RUN_ACK_SHIFT 0 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_RUN_ACK_MASK 0x1 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_HALT_ACK_SHIFT 4 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_HALT_ACK_MASK 0x10 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_HALT_R_SHIFT 8 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_HALT_R_MASK 0x100 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_TF_HALT_R_SHIFT 12 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_TF_HALT_R_MASK 0x1000 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_SLEEP_R_SHIFT 16 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_SLEEP_R_MASK 0x10000 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_SLEEP_MODE_R_SHIFT 17 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_SLEEP_MODE_R_MASK 0xE0000 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_WATCHDOG_RESET_SHIFT 20 +#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_WATCHDOG_RESET_MASK 0x100000 + +/* ARC_FARM_ARC0_AUX_RST_VEC_ADDR */ +#define ARC_FARM_ARC0_AUX_RST_VEC_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_RST_VEC_ADDR_VAL_MASK 0x3FFFFF + +/* ARC_FARM_ARC0_AUX_DBG_MODE */ +#define ARC_FARM_ARC0_AUX_DBG_MODE_DBG_PROT_SEL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DBG_MODE_DBG_PROT_SEL_MASK 0x1 +#define ARC_FARM_ARC0_AUX_DBG_MODE_DBGEN_SHIFT 4 +#define ARC_FARM_ARC0_AUX_DBG_MODE_DBGEN_MASK 0x10 +#define ARC_FARM_ARC0_AUX_DBG_MODE_NIDEN_SHIFT 8 +#define ARC_FARM_ARC0_AUX_DBG_MODE_NIDEN_MASK 0x100 +#define ARC_FARM_ARC0_AUX_DBG_MODE_CASHE_RST_DISABLE_SHIFT 12 +#define ARC_FARM_ARC0_AUX_DBG_MODE_CASHE_RST_DISABLE_MASK 0x1000 +#define ARC_FARM_ARC0_AUX_DBG_MODE_DDCM_DMI_PRIORITY_SHIFT 16 +#define ARC_FARM_ARC0_AUX_DBG_MODE_DDCM_DMI_PRIORITY_MASK 0x10000 + +/* ARC_FARM_ARC0_AUX_CLUSTER_NUM */ +#define ARC_FARM_ARC0_AUX_CLUSTER_NUM_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CLUSTER_NUM_VAL_MASK 0xFF + +/* ARC_FARM_ARC0_AUX_ARC_NUM */ +#define ARC_FARM_ARC0_AUX_ARC_NUM_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_NUM_VAL_MASK 0xFF + +/* ARC_FARM_ARC0_AUX_WAKE_UP_EVENT */ +#define ARC_FARM_ARC0_AUX_WAKE_UP_EVENT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_WAKE_UP_EVENT_VAL_MASK 0x1 + +/* ARC_FARM_ARC0_AUX_DCCM_SYS_ADDR_BASE */ +#define ARC_FARM_ARC0_AUX_DCCM_SYS_ADDR_BASE_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_SYS_ADDR_BASE_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CTI_AP_STS */ +#define ARC_FARM_ARC0_AUX_CTI_AP_STS_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CTI_AP_STS_VAL_MASK 0xFF + +/* ARC_FARM_ARC0_AUX_CTI_CFG_MUX_SEL */ +#define ARC_FARM_ARC0_AUX_CTI_CFG_MUX_SEL_RUN_HALT_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CTI_CFG_MUX_SEL_RUN_HALT_MASK 0x1 + +/* ARC_FARM_ARC0_AUX_ARC_RST */ +#define ARC_FARM_ARC0_AUX_ARC_RST_CORE_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_RST_CORE_MASK 0x1 +#define ARC_FARM_ARC0_AUX_ARC_RST_PRESETDBGN_SHIFT 4 +#define ARC_FARM_ARC0_AUX_ARC_RST_PRESETDBGN_MASK 0x10 + +/* ARC_FARM_ARC0_AUX_ARC_RST_REQ */ +#define ARC_FARM_ARC0_AUX_ARC_RST_REQ_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_RST_REQ_VAL_MASK 0x1 + +/* ARC_FARM_ARC0_AUX_SRAM_LSB_ADDR */ +#define ARC_FARM_ARC0_AUX_SRAM_LSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_SRAM_LSB_ADDR_VAL_MASK 0x3F + +/* ARC_FARM_ARC0_AUX_SRAM_MSB_ADDR */ +#define ARC_FARM_ARC0_AUX_SRAM_MSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_SRAM_MSB_ADDR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_PCIE_LSB_ADDR */ +#define ARC_FARM_ARC0_AUX_PCIE_LSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_PCIE_LSB_ADDR_VAL_MASK 0xF + +/* ARC_FARM_ARC0_AUX_PCIE_MSB_ADDR */ +#define ARC_FARM_ARC0_AUX_PCIE_MSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_PCIE_MSB_ADDR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CFG_LSB_ADDR */ +#define ARC_FARM_ARC0_AUX_CFG_LSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CFG_LSB_ADDR_VAL_MASK 0xF + +/* ARC_FARM_ARC0_AUX_CFG_MSB_ADDR */ +#define ARC_FARM_ARC0_AUX_CFG_MSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CFG_MSB_ADDR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_HBM0_LSB_ADDR */ +#define ARC_FARM_ARC0_AUX_HBM0_LSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_HBM0_LSB_ADDR_VAL_MASK 0xF + +/* ARC_FARM_ARC0_AUX_HBM0_MSB_ADDR */ +#define ARC_FARM_ARC0_AUX_HBM0_MSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_HBM0_MSB_ADDR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_HBM1_LSB_ADDR */ +#define ARC_FARM_ARC0_AUX_HBM1_LSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_HBM1_LSB_ADDR_VAL_MASK 0xF + +/* ARC_FARM_ARC0_AUX_HBM1_MSB_ADDR */ +#define ARC_FARM_ARC0_AUX_HBM1_MSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_HBM1_MSB_ADDR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_HBM2_LSB_ADDR */ +#define ARC_FARM_ARC0_AUX_HBM2_LSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_HBM2_LSB_ADDR_VAL_MASK 0xF + +/* ARC_FARM_ARC0_AUX_HBM2_MSB_ADDR */ +#define ARC_FARM_ARC0_AUX_HBM2_MSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_HBM2_MSB_ADDR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_HBM3_LSB_ADDR */ +#define ARC_FARM_ARC0_AUX_HBM3_LSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_HBM3_LSB_ADDR_VAL_MASK 0xF + +/* ARC_FARM_ARC0_AUX_HBM3_MSB_ADDR */ +#define ARC_FARM_ARC0_AUX_HBM3_MSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_HBM3_MSB_ADDR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_HBM0_OFFSET */ +#define ARC_FARM_ARC0_AUX_HBM0_OFFSET_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_HBM0_OFFSET_VAL_MASK 0xFFFFFFF + +/* ARC_FARM_ARC0_AUX_HBM1_OFFSET */ +#define ARC_FARM_ARC0_AUX_HBM1_OFFSET_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_HBM1_OFFSET_VAL_MASK 0xFFFFFFF + +/* ARC_FARM_ARC0_AUX_HBM2_OFFSET */ +#define ARC_FARM_ARC0_AUX_HBM2_OFFSET_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_HBM2_OFFSET_VAL_MASK 0xFFFFFFF + +/* ARC_FARM_ARC0_AUX_HBM3_OFFSET */ +#define ARC_FARM_ARC0_AUX_HBM3_OFFSET_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_HBM3_OFFSET_VAL_MASK 0xFFFFFFF + +/* ARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR */ +#define ARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_VAL_MASK 0xF + +/* ARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR */ +#define ARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_ARC_CBU_AWCACHE_OVR */ +#define ARC_FARM_ARC0_AUX_ARC_CBU_AWCACHE_OVR_AXI_WRITE_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_CBU_AWCACHE_OVR_AXI_WRITE_MASK 0xF +#define ARC_FARM_ARC0_AUX_ARC_CBU_AWCACHE_OVR_AXI_WRITE_EN_SHIFT 4 +#define ARC_FARM_ARC0_AUX_ARC_CBU_AWCACHE_OVR_AXI_WRITE_EN_MASK 0xF0 + +/* ARC_FARM_ARC0_AUX_ARC_LBU_AWCACHE_OVR */ +#define ARC_FARM_ARC0_AUX_ARC_LBU_AWCACHE_OVR_AXI_WRITE_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_LBU_AWCACHE_OVR_AXI_WRITE_MASK 0xF +#define ARC_FARM_ARC0_AUX_ARC_LBU_AWCACHE_OVR_AXI_WRITE_EN_SHIFT 4 +#define ARC_FARM_ARC0_AUX_ARC_LBU_AWCACHE_OVR_AXI_WRITE_EN_MASK 0xF0 + +/* ARC_FARM_ARC0_AUX_CONTEXT_ID */ +#define ARC_FARM_ARC0_AUX_CONTEXT_ID_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CONTEXT_ID_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CID_OFFSET */ +#define ARC_FARM_ARC0_AUX_CID_OFFSET_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CID_OFFSET_VAL_MASK 0xFF + +/* ARC_FARM_ARC0_AUX_SW_INTR */ +#define ARC_FARM_ARC0_AUX_SW_INTR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_SW_INTR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_IRQ_INTR_MASK */ +#define ARC_FARM_ARC0_AUX_IRQ_INTR_MASK_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_IRQ_INTR_MASK_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_ARC_SEI_INTR_STS */ +#define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_STS_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_STS_VAL_MASK 0x3FFF + +/* ARC_FARM_ARC0_AUX_ARC_SEI_INTR_CLR */ +#define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_CLR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_CLR_VAL_MASK 0x3FFF + +/* ARC_FARM_ARC0_AUX_ARC_SEI_INTR_MASK */ +#define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_MASK_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_MASK_VAL_MASK 0x3FFF + +/* ARC_FARM_ARC0_AUX_ARC_EXCPTN_CAUSE */ +#define ARC_FARM_ARC0_AUX_ARC_EXCPTN_CAUSE_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_EXCPTN_CAUSE_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_SEI_INTR_HALT_EN */ +#define ARC_FARM_ARC0_AUX_SEI_INTR_HALT_EN_INTR_EN_SHIFT 0 +#define ARC_FARM_ARC0_AUX_SEI_INTR_HALT_EN_INTR_EN_MASK 0x1 +#define ARC_FARM_ARC0_AUX_SEI_INTR_HALT_EN_HALT_EN_SHIFT 1 +#define ARC_FARM_ARC0_AUX_SEI_INTR_HALT_EN_HALT_EN_MASK 0x2 + +/* ARC_FARM_ARC0_AUX_ARC_SEI_INTR_HALT_MASK */ +#define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_HALT_MASK_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_HALT_MASK_VAL_MASK 0x3FFF + +/* ARC_FARM_ARC0_AUX_QMAN_SEI_INTR_HALT_MASK */ +#define ARC_FARM_ARC0_AUX_QMAN_SEI_INTR_HALT_MASK_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_QMAN_SEI_INTR_HALT_MASK_VAL_MASK 0x3FFF + +/* ARC_FARM_ARC0_AUX_ARC_REI_INTR_STS */ +#define ARC_FARM_ARC0_AUX_ARC_REI_INTR_STS_SERR_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REI_INTR_STS_SERR_MASK 0x1 +#define ARC_FARM_ARC0_AUX_ARC_REI_INTR_STS_DERR_SHIFT 1 +#define ARC_FARM_ARC0_AUX_ARC_REI_INTR_STS_DERR_MASK 0x2 + +/* ARC_FARM_ARC0_AUX_ARC_REI_INTR_CLR */ +#define ARC_FARM_ARC0_AUX_ARC_REI_INTR_CLR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REI_INTR_CLR_VAL_MASK 0x3 + +/* ARC_FARM_ARC0_AUX_ARC_REI_INTR_MASK */ +#define ARC_FARM_ARC0_AUX_ARC_REI_INTR_MASK_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REI_INTR_MASK_VAL_MASK 0x3 + +/* ARC_FARM_ARC0_AUX_DCCM_ECC_ERR_ADDR */ +#define ARC_FARM_ARC0_AUX_DCCM_ECC_ERR_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_ECC_ERR_ADDR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_DCCM_ECC_SYNDROME */ +#define ARC_FARM_ARC0_AUX_DCCM_ECC_SYNDROME_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_ECC_SYNDROME_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_I_CACHE_ECC_ERR_ADDR */ +#define ARC_FARM_ARC0_AUX_I_CACHE_ECC_ERR_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_I_CACHE_ECC_ERR_ADDR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_I_CACHE_ECC_SYNDROME */ +#define ARC_FARM_ARC0_AUX_I_CACHE_ECC_SYNDROME_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_I_CACHE_ECC_SYNDROME_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_D_CACHE_ECC_ERR_ADDR */ +#define ARC_FARM_ARC0_AUX_D_CACHE_ECC_ERR_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_D_CACHE_ECC_ERR_ADDR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_D_CACHE_ECC_SYNDROME */ +#define ARC_FARM_ARC0_AUX_D_CACHE_ECC_SYNDROME_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_D_CACHE_ECC_SYNDROME_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_LBW_TRMINATE_AWADDR_ERR */ +#define ARC_FARM_ARC0_AUX_LBW_TRMINATE_AWADDR_ERR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBW_TRMINATE_AWADDR_ERR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_LBW_TRMINATE_ARADDR_ERR */ +#define ARC_FARM_ARC0_AUX_LBW_TRMINATE_ARADDR_ERR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBW_TRMINATE_ARADDR_ERR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_BRESP */ +#define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_BRESP_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_BRESP_VAL_MASK 0x3 + +/* ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_RRESP */ +#define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_RRESP_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_RRESP_VAL_MASK 0x3 + +/* ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXLEN */ +#define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXLEN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXLEN_VAL_MASK 0xFF + +/* ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXSIZE */ +#define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXSIZE_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXSIZE_VAL_MASK 0x7 + +/* ARC_FARM_ARC0_AUX_SCRATCHPAD */ +#define ARC_FARM_ARC0_AUX_SCRATCHPAD_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_SCRATCHPAD_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_TOTAL_CBU_WR_CNT */ +#define ARC_FARM_ARC0_AUX_TOTAL_CBU_WR_CNT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_TOTAL_CBU_WR_CNT_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_INFLIGHT_CBU_WR_CNT */ +#define ARC_FARM_ARC0_AUX_INFLIGHT_CBU_WR_CNT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_INFLIGHT_CBU_WR_CNT_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_TOTAL_CBU_RD_CNT */ +#define ARC_FARM_ARC0_AUX_TOTAL_CBU_RD_CNT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_TOTAL_CBU_RD_CNT_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_INFLIGHT_CBU_RD_CNT */ +#define ARC_FARM_ARC0_AUX_INFLIGHT_CBU_RD_CNT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_INFLIGHT_CBU_RD_CNT_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_TOTAL_LBU_WR_CNT */ +#define ARC_FARM_ARC0_AUX_TOTAL_LBU_WR_CNT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_TOTAL_LBU_WR_CNT_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_INFLIGHT_LBU_WR_CNT */ +#define ARC_FARM_ARC0_AUX_INFLIGHT_LBU_WR_CNT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_INFLIGHT_LBU_WR_CNT_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_TOTAL_LBU_RD_CNT */ +#define ARC_FARM_ARC0_AUX_TOTAL_LBU_RD_CNT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_TOTAL_LBU_RD_CNT_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_INFLIGHT_LBU_RD_CNT */ +#define ARC_FARM_ARC0_AUX_INFLIGHT_LBU_RD_CNT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_INFLIGHT_LBU_RD_CNT_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_ARUSER_OVR */ +#define ARC_FARM_ARC0_AUX_CBU_ARUSER_OVR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_ARUSER_OVR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_ARUSER_OVR_EN */ +#define ARC_FARM_ARC0_AUX_CBU_ARUSER_OVR_EN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_ARUSER_OVR_EN_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_AWUSER_OVR */ +#define ARC_FARM_ARC0_AUX_CBU_AWUSER_OVR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_AWUSER_OVR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_AWUSER_OVR_EN */ +#define ARC_FARM_ARC0_AUX_CBU_AWUSER_OVR_EN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_AWUSER_OVR_EN_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR */ +#define ARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR_VAL_MASK 0x3FF + +/* ARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR_EN */ +#define ARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR_EN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR_EN_VAL_MASK 0x3FF + +/* ARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR */ +#define ARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR_VAL_MASK 0x3FF + +/* ARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR_EN */ +#define ARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR_EN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR_EN_VAL_MASK 0x3FF + +/* ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR */ +#define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_READ_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_READ_MASK 0xF +#define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_WRITE_SHIFT 4 +#define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_WRITE_MASK 0xF0 +#define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_RD_EN_SHIFT 8 +#define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_RD_EN_MASK 0xF00 +#define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_WR_EN_SHIFT 12 +#define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_WR_EN_MASK 0xF000 + +/* ARC_FARM_ARC0_AUX_CBU_LOCK_OVR */ +#define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_READ_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_READ_MASK 0x3 +#define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_WRITE_SHIFT 4 +#define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_WRITE_MASK 0x30 +#define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_RD_EN_SHIFT 8 +#define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_RD_EN_MASK 0x300 +#define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_WR_EN_SHIFT 12 +#define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_WR_EN_MASK 0x3000 + +/* ARC_FARM_ARC0_AUX_CBU_PROT_OVR */ +#define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_READ_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_READ_MASK 0x7 +#define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_WRITE_SHIFT 4 +#define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_WRITE_MASK 0x70 +#define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_RD_EN_SHIFT 8 +#define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_RD_EN_MASK 0x700 +#define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_WR_EN_SHIFT 12 +#define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_WR_EN_MASK 0x7000 + +/* ARC_FARM_ARC0_AUX_CBU_MAX_OUTSTANDING */ +#define ARC_FARM_ARC0_AUX_CBU_MAX_OUTSTANDING_CBU_READ_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_MAX_OUTSTANDING_CBU_READ_MASK 0xFF +#define ARC_FARM_ARC0_AUX_CBU_MAX_OUTSTANDING_CBU_WRITE_SHIFT 8 +#define ARC_FARM_ARC0_AUX_CBU_MAX_OUTSTANDING_CBU_WRITE_MASK 0xFF00 + +/* ARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN */ +#define ARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN_CBU_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN_CBU_VAL_MASK 0x1 + +/* ARC_FARM_ARC0_AUX_CBU_FORCE_RSP_OK */ +#define ARC_FARM_ARC0_AUX_CBU_FORCE_RSP_OK_CBU_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORCE_RSP_OK_CBU_VAL_MASK 0x1 + +/* ARC_FARM_ARC0_AUX_CBU_NO_WR_INFLIGHT */ +#define ARC_FARM_ARC0_AUX_CBU_NO_WR_INFLIGHT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_NO_WR_INFLIGHT_VAL_MASK 0x1 + +/* ARC_FARM_ARC0_AUX_CBU_SEI_INTR_ID */ +#define ARC_FARM_ARC0_AUX_CBU_SEI_INTR_ID_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_SEI_INTR_ID_VAL_MASK 0x7F + +/* ARC_FARM_ARC0_AUX_LBU_ARUSER_OVR */ +#define ARC_FARM_ARC0_AUX_LBU_ARUSER_OVR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBU_ARUSER_OVR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_LBU_ARUSER_OVR_EN */ +#define ARC_FARM_ARC0_AUX_LBU_ARUSER_OVR_EN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBU_ARUSER_OVR_EN_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_LBU_AWUSER_OVR */ +#define ARC_FARM_ARC0_AUX_LBU_AWUSER_OVR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBU_AWUSER_OVR_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_LBU_AWUSER_OVR_EN */ +#define ARC_FARM_ARC0_AUX_LBU_AWUSER_OVR_EN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBU_AWUSER_OVR_EN_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR */ +#define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_READ_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_READ_MASK 0xF +#define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_WRITE_SHIFT 4 +#define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_WRITE_MASK 0xF0 +#define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_RD_EN_SHIFT 8 +#define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_RD_EN_MASK 0xF00 +#define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_WR_EN_SHIFT 12 +#define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_WR_EN_MASK 0xF000 + +/* ARC_FARM_ARC0_AUX_LBU_LOCK_OVR */ +#define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_READ_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_READ_MASK 0x3 +#define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_WRITE_SHIFT 4 +#define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_WRITE_MASK 0x30 +#define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_RD_EN_SHIFT 8 +#define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_RD_EN_MASK 0x300 +#define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_WR_EN_SHIFT 12 +#define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_WR_EN_MASK 0x3000 + +/* ARC_FARM_ARC0_AUX_LBU_PROT_OVR */ +#define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_READ_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_READ_MASK 0x7 +#define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_WRITE_SHIFT 4 +#define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_WRITE_MASK 0x70 +#define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_RD_EN_SHIFT 8 +#define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_RD_EN_MASK 0x700 +#define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_WR_EN_SHIFT 12 +#define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_WR_EN_MASK 0x7000 + +/* ARC_FARM_ARC0_AUX_LBU_MAX_OUTSTANDING */ +#define ARC_FARM_ARC0_AUX_LBU_MAX_OUTSTANDING_LBU_READ_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBU_MAX_OUTSTANDING_LBU_READ_MASK 0xFF +#define ARC_FARM_ARC0_AUX_LBU_MAX_OUTSTANDING_LBU_WRITE_SHIFT 8 +#define ARC_FARM_ARC0_AUX_LBU_MAX_OUTSTANDING_LBU_WRITE_MASK 0xFF00 + +/* ARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN */ +#define ARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN_VAL_MASK 0x1 + +/* ARC_FARM_ARC0_AUX_LBU_FORCE_RSP_OK */ +#define ARC_FARM_ARC0_AUX_LBU_FORCE_RSP_OK_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBU_FORCE_RSP_OK_VAL_MASK 0x1 + +/* ARC_FARM_ARC0_AUX_LBU_NO_WR_INFLIGHT */ +#define ARC_FARM_ARC0_AUX_LBU_NO_WR_INFLIGHT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBU_NO_WR_INFLIGHT_VAL_MASK 0x1 + +/* ARC_FARM_ARC0_AUX_LBU_SEI_INTR_ID */ +#define ARC_FARM_ARC0_AUX_LBU_SEI_INTR_ID_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBU_SEI_INTR_ID_VAL_MASK 0x3FF + +/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR */ +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_VAL_MASK 0xFFFFFF + +/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE */ +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_VAL_MASK 0xFFFFFF + +/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_PI */ +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_VAL_MASK 0xFFFFFF + +/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_CI */ +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_VAL_MASK 0xFFFFFF + +/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG */ +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY */ +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_VAL_MASK 0xFFFFFF + +/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES */ +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_VAL_MASK 0xFFFFFF + +/* ARC_FARM_ARC0_AUX_GENERAL_Q_VLD_ENTRY_MASK */ +#define ARC_FARM_ARC0_AUX_GENERAL_Q_VLD_ENTRY_MASK_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_GENERAL_Q_VLD_ENTRY_MASK_VAL_MASK 0xFF + +/* ARC_FARM_ARC0_AUX_NIC_Q_VLD_ENTRY_MASK */ +#define ARC_FARM_ARC0_AUX_NIC_Q_VLD_ENTRY_MASK_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_NIC_Q_VLD_ENTRY_MASK_VAL_MASK 0xFF + +/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_DROP_EN */ +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_DROP_EN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_DROP_EN_VAL_MASK 0x1 + +/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_WARN_MSG */ +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_WARN_MSG_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_WARN_MSG_VAL_MASK 0xFFFF + +/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_ALERT_MSG */ +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_ALERT_MSG_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_ALERT_MSG_VAL_MASK 0xFFFF + +/* ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWPROT */ +#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWPROT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWPROT_VAL_MASK 0x7 + +/* ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWUSER */ +#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWUSER_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWUSER_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWBURST */ +#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWBURST_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWBURST_VAL_MASK 0x3 + +/* ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWLOCK */ +#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWLOCK_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWLOCK_VAL_MASK 0x1 + +/* ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWCACHE */ +#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWCACHE_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWCACHE_VAL_MASK 0xF + +/* ARC_FARM_ARC0_AUX_DCCM_WRR_ARB_WEIGHT */ +#define ARC_FARM_ARC0_AUX_DCCM_WRR_ARB_WEIGHT_LBW_SLV_AXI_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_WRR_ARB_WEIGHT_LBW_SLV_AXI_MASK 0xF +#define ARC_FARM_ARC0_AUX_DCCM_WRR_ARB_WEIGHT_GEN_AXI_SHIFT 4 +#define ARC_FARM_ARC0_AUX_DCCM_WRR_ARB_WEIGHT_GEN_AXI_MASK 0xF0 + +/* ARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG */ +#define ARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG_VAL_MASK 0x1F + +/* ARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_CNT */ +#define ARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_CNT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_CNT_VAL_MASK 0x1F + +/* ARC_FARM_ARC0_AUX_QMAN_CQ_IFIFO_SHADOW_CI */ +#define ARC_FARM_ARC0_AUX_QMAN_CQ_IFIFO_SHADOW_CI_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_QMAN_CQ_IFIFO_SHADOW_CI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI */ +#define ARC_FARM_ARC0_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_QMAN_CQ_SHADOW_CI */ +#define ARC_FARM_ARC0_AUX_QMAN_CQ_SHADOW_CI_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_QMAN_CQ_SHADOW_CI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_QMAN_ARC_CQ_SHADOW_CI */ +#define ARC_FARM_ARC0_AUX_QMAN_ARC_CQ_SHADOW_CI_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_QMAN_ARC_CQ_SHADOW_CI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_AUX2APB_PROT */ +#define ARC_FARM_ARC0_AUX_AUX2APB_PROT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_AUX2APB_PROT_VAL_MASK 0x7 + +/* ARC_FARM_ARC0_AUX_LBW_FORK_WIN_EN */ +#define ARC_FARM_ARC0_AUX_LBW_FORK_WIN_EN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBW_FORK_WIN_EN_VAL_MASK 0x3 + +/* ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR0 */ +#define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR0_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR0_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK0 */ +#define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK0_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK0_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR1 */ +#define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR1_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR1_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK1 */ +#define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK1_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK1_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR0 */ +#define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR0_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR0_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK0 */ +#define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK0_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK0_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR1 */ +#define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR1_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR1_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK1 */ +#define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK1_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK1_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR0 */ +#define ARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR0_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR0_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR1 */ +#define ARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR1_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR1_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_LBW_FORK_MASK */ +#define ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_LBW_FORK_MASK_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_LBW_FORK_MASK_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_ARC_DUP_ENG_LBW_FORK_ADDR */ +#define ARC_FARM_ARC0_AUX_ARC_DUP_ENG_LBW_FORK_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_DUP_ENG_LBW_FORK_ADDR_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_ARC_ACP_ENG_LBW_FORK_ADDR */ +#define ARC_FARM_ARC0_AUX_ARC_ACP_ENG_LBW_FORK_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_ACP_ENG_LBW_FORK_ADDR_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR */ +#define ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_WIN_EN */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_WIN_EN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_WIN_EN_VAL_MASK 0xF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_LSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_LSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_LSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_MSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_MSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_MSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_LSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_LSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_LSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_MSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_MSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_MSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_LSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_LSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_LSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_MSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_MSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_MSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_LSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_LSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_LSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_MSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_MSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_MSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_LSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_LSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_LSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_MSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_MSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_MSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_LSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_LSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_LSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_MSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_MSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_MSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_LSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_LSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_LSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_MSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_MSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_MSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_LSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_LSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_LSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_MSB */ +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_MSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_MSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_LSB */ +#define ARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_LSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_LSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_MSB */ +#define ARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_MSB_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_MSB_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_BRESP */ +#define ARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_BRESP_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_BRESP_VAL_MASK 0x3 + +/* ARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_RRESP */ +#define ARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_RRESP_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_RRESP_VAL_MASK 0x3 + +/* ARC_FARM_ARC0_AUX_ARC_REGION_CFG */ +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_0_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_0_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_1_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_1_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_2_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_2_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_3_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_3_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_4_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_4_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_5_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_5_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_6_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_6_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_7_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_7_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_8_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_8_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_9_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_9_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_10_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_10_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_11_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_11_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_12_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_12_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_13_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_13_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_14_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_14_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_15_ASID_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_15_ASID_MASK 0x3FF +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_MMU_BP_SHIFT 12 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_MMU_BP_MASK 0x1000 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_PROT_VAL_SHIFT 16 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_PROT_VAL_MASK 0x70000 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_PROT_VAL_EN_SHIFT 20 +#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_PROT_VAL_EN_MASK 0x700000 + +/* ARC_FARM_ARC0_AUX_DCCM_TRMINATE_AWADDR_ERR */ +#define ARC_FARM_ARC0_AUX_DCCM_TRMINATE_AWADDR_ERR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_TRMINATE_AWADDR_ERR_VAL_MASK 0xFFFFFF + +/* ARC_FARM_ARC0_AUX_DCCM_TRMINATE_ARADDR_ERR */ +#define ARC_FARM_ARC0_AUX_DCCM_TRMINATE_ARADDR_ERR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_DCCM_TRMINATE_ARADDR_ERR_VAL_MASK 0xFFFFFF + +/* ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_BRESP */ +#define ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_BRESP_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_BRESP_VAL_MASK 0x3 + +/* ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_RRESP */ +#define ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_RRESP_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_RRESP_VAL_MASK 0x3 + +/* ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_EN */ +#define ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_EN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_EN_VAL_MASK 0x1 + +/* ARC_FARM_ARC0_AUX_CFG_DCCM_SECURE_REGION */ +#define ARC_FARM_ARC0_AUX_CFG_DCCM_SECURE_REGION_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_CFG_DCCM_SECURE_REGION_VAL_MASK 0xFFFFFF + +/* ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_WR_IF_CNT */ +#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_WR_IF_CNT_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_WR_IF_CNT_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_CTL */ +#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_CTL_ENABLE_BP_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_CTL_ENABLE_BP_MASK 0x1 +#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_CTL_RD_DELAY_CC_SHIFT 1 +#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_CTL_RD_DELAY_CC_MASK 0x3E + +/* ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR_MSK */ +#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR_MSK_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR_MSK_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR */ +#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR_VAL_MASK 0x7FFFFFF + +/* ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_BUSER */ +#define ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_BUSER_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_BUSER_VAL_MASK 0x3 + +/* ARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN */ +#define ARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN_VAL_SHIFT 0 +#define ARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN_VAL_MASK 0x1 + +#endif /* ASIC_REG_ARC_FARM_ARC0_AUX_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_aux_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_aux_regs.h new file mode 100644 index 000000000000..5345b5faa3a2 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_aux_regs.h @@ -0,0 +1,591 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ARC_FARM_ARC0_AUX_REGS_H_ +#define ASIC_REG_ARC_FARM_ARC0_AUX_REGS_H_ + +/* + ***************************************** + * ARC_FARM_ARC0_AUX + * (Prototype: QMAN_ARC_AUX) + ***************************************** + */ + +#define mmARC_FARM_ARC0_AUX_RUN_HALT_REQ 0x4E88100 + +#define mmARC_FARM_ARC0_AUX_RUN_HALT_ACK 0x4E88104 + +#define mmARC_FARM_ARC0_AUX_RST_VEC_ADDR 0x4E88108 + +#define mmARC_FARM_ARC0_AUX_DBG_MODE 0x4E8810C + +#define mmARC_FARM_ARC0_AUX_CLUSTER_NUM 0x4E88110 + +#define mmARC_FARM_ARC0_AUX_ARC_NUM 0x4E88114 + +#define mmARC_FARM_ARC0_AUX_WAKE_UP_EVENT 0x4E88118 + +#define mmARC_FARM_ARC0_AUX_DCCM_SYS_ADDR_BASE 0x4E8811C + +#define mmARC_FARM_ARC0_AUX_CTI_AP_STS 0x4E88120 + +#define mmARC_FARM_ARC0_AUX_CTI_CFG_MUX_SEL 0x4E88124 + +#define mmARC_FARM_ARC0_AUX_ARC_RST 0x4E88128 + +#define mmARC_FARM_ARC0_AUX_ARC_RST_REQ 0x4E8812C + +#define mmARC_FARM_ARC0_AUX_SRAM_LSB_ADDR 0x4E88130 + +#define mmARC_FARM_ARC0_AUX_SRAM_MSB_ADDR 0x4E88134 + +#define mmARC_FARM_ARC0_AUX_PCIE_LSB_ADDR 0x4E88138 + +#define mmARC_FARM_ARC0_AUX_PCIE_MSB_ADDR 0x4E8813C + +#define mmARC_FARM_ARC0_AUX_CFG_LSB_ADDR 0x4E88140 + +#define mmARC_FARM_ARC0_AUX_CFG_MSB_ADDR 0x4E88144 + +#define mmARC_FARM_ARC0_AUX_HBM0_LSB_ADDR 0x4E88150 + +#define mmARC_FARM_ARC0_AUX_HBM0_MSB_ADDR 0x4E88154 + +#define mmARC_FARM_ARC0_AUX_HBM1_LSB_ADDR 0x4E88158 + +#define mmARC_FARM_ARC0_AUX_HBM1_MSB_ADDR 0x4E8815C + +#define mmARC_FARM_ARC0_AUX_HBM2_LSB_ADDR 0x4E88160 + +#define mmARC_FARM_ARC0_AUX_HBM2_MSB_ADDR 0x4E88164 + +#define mmARC_FARM_ARC0_AUX_HBM3_LSB_ADDR 0x4E88168 + +#define mmARC_FARM_ARC0_AUX_HBM3_MSB_ADDR 0x4E8816C + +#define mmARC_FARM_ARC0_AUX_HBM0_OFFSET 0x4E88170 + +#define mmARC_FARM_ARC0_AUX_HBM1_OFFSET 0x4E88174 + +#define mmARC_FARM_ARC0_AUX_HBM2_OFFSET 0x4E88178 + +#define mmARC_FARM_ARC0_AUX_HBM3_OFFSET 0x4E8817C + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x4E88180 + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x4E88184 + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x4E88188 + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x4E8818C + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x4E88190 + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x4E88194 + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x4E88198 + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x4E8819C + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x4E881A0 + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x4E881A4 + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x4E881A8 + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x4E881AC + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x4E881B0 + +#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x4E881B4 + +#define mmARC_FARM_ARC0_AUX_ARC_CBU_AWCACHE_OVR 0x4E881B8 + +#define mmARC_FARM_ARC0_AUX_ARC_LBU_AWCACHE_OVR 0x4E881BC + +#define mmARC_FARM_ARC0_AUX_CONTEXT_ID_0 0x4E881C0 + +#define mmARC_FARM_ARC0_AUX_CONTEXT_ID_1 0x4E881C4 + +#define mmARC_FARM_ARC0_AUX_CONTEXT_ID_2 0x4E881C8 + +#define mmARC_FARM_ARC0_AUX_CONTEXT_ID_3 0x4E881CC + +#define mmARC_FARM_ARC0_AUX_CONTEXT_ID_4 0x4E881D0 + +#define mmARC_FARM_ARC0_AUX_CONTEXT_ID_5 0x4E881D4 + +#define mmARC_FARM_ARC0_AUX_CONTEXT_ID_6 0x4E881D8 + +#define mmARC_FARM_ARC0_AUX_CONTEXT_ID_7 0x4E881DC + +#define mmARC_FARM_ARC0_AUX_CID_OFFSET_0 0x4E881E0 + +#define mmARC_FARM_ARC0_AUX_CID_OFFSET_1 0x4E881E4 + +#define mmARC_FARM_ARC0_AUX_CID_OFFSET_2 0x4E881E8 + +#define mmARC_FARM_ARC0_AUX_CID_OFFSET_3 0x4E881EC + +#define mmARC_FARM_ARC0_AUX_CID_OFFSET_4 0x4E881F0 + +#define mmARC_FARM_ARC0_AUX_CID_OFFSET_5 0x4E881F4 + +#define mmARC_FARM_ARC0_AUX_CID_OFFSET_6 0x4E881F8 + +#define mmARC_FARM_ARC0_AUX_CID_OFFSET_7 0x4E881FC + +#define mmARC_FARM_ARC0_AUX_SW_INTR_0 0x4E88200 + +#define mmARC_FARM_ARC0_AUX_SW_INTR_1 0x4E88204 + +#define mmARC_FARM_ARC0_AUX_SW_INTR_2 0x4E88208 + +#define mmARC_FARM_ARC0_AUX_SW_INTR_3 0x4E8820C + +#define mmARC_FARM_ARC0_AUX_SW_INTR_4 0x4E88210 + +#define mmARC_FARM_ARC0_AUX_SW_INTR_5 0x4E88214 + +#define mmARC_FARM_ARC0_AUX_SW_INTR_6 0x4E88218 + +#define mmARC_FARM_ARC0_AUX_SW_INTR_7 0x4E8821C + +#define mmARC_FARM_ARC0_AUX_SW_INTR_8 0x4E88220 + +#define mmARC_FARM_ARC0_AUX_SW_INTR_9 0x4E88224 + +#define mmARC_FARM_ARC0_AUX_SW_INTR_10 0x4E88228 + +#define mmARC_FARM_ARC0_AUX_SW_INTR_11 0x4E8822C + +#define mmARC_FARM_ARC0_AUX_SW_INTR_12 0x4E88230 + +#define mmARC_FARM_ARC0_AUX_SW_INTR_13 0x4E88234 + +#define mmARC_FARM_ARC0_AUX_SW_INTR_14 0x4E88238 + +#define mmARC_FARM_ARC0_AUX_SW_INTR_15 0x4E8823C + +#define mmARC_FARM_ARC0_AUX_IRQ_INTR_MASK_0 0x4E88280 + +#define mmARC_FARM_ARC0_AUX_IRQ_INTR_MASK_1 0x4E88284 + +#define mmARC_FARM_ARC0_AUX_ARC_SEI_INTR_STS 0x4E88290 + +#define mmARC_FARM_ARC0_AUX_ARC_SEI_INTR_CLR 0x4E88294 + +#define mmARC_FARM_ARC0_AUX_ARC_SEI_INTR_MASK 0x4E88298 + +#define mmARC_FARM_ARC0_AUX_ARC_EXCPTN_CAUSE 0x4E8829C + +#define mmARC_FARM_ARC0_AUX_SEI_INTR_HALT_EN 0x4E882A0 + +#define mmARC_FARM_ARC0_AUX_ARC_SEI_INTR_HALT_MASK 0x4E882A4 + +#define mmARC_FARM_ARC0_AUX_QMAN_SEI_INTR_HALT_MASK 0x4E882A8 + +#define mmARC_FARM_ARC0_AUX_ARC_REI_INTR_STS 0x4E882B0 + +#define mmARC_FARM_ARC0_AUX_ARC_REI_INTR_CLR 0x4E882B4 + +#define mmARC_FARM_ARC0_AUX_ARC_REI_INTR_MASK 0x4E882B8 + +#define mmARC_FARM_ARC0_AUX_DCCM_ECC_ERR_ADDR 0x4E882BC + +#define mmARC_FARM_ARC0_AUX_DCCM_ECC_SYNDROME 0x4E882C0 + +#define mmARC_FARM_ARC0_AUX_I_CACHE_ECC_ERR_ADDR 0x4E882C4 + +#define mmARC_FARM_ARC0_AUX_I_CACHE_ECC_SYNDROME 0x4E882C8 + +#define mmARC_FARM_ARC0_AUX_D_CACHE_ECC_ERR_ADDR 0x4E882CC + +#define mmARC_FARM_ARC0_AUX_D_CACHE_ECC_SYNDROME 0x4E882D0 + +#define mmARC_FARM_ARC0_AUX_LBW_TRMINATE_AWADDR_ERR 0x4E882E0 + +#define mmARC_FARM_ARC0_AUX_LBW_TRMINATE_ARADDR_ERR 0x4E882E4 + +#define mmARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_BRESP 0x4E882E8 + +#define mmARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_RRESP 0x4E882EC + +#define mmARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXLEN 0x4E882F0 + +#define mmARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXSIZE 0x4E882F4 + +#define mmARC_FARM_ARC0_AUX_SCRATCHPAD_0 0x4E88300 + +#define mmARC_FARM_ARC0_AUX_SCRATCHPAD_1 0x4E88304 + +#define mmARC_FARM_ARC0_AUX_SCRATCHPAD_2 0x4E88308 + +#define mmARC_FARM_ARC0_AUX_SCRATCHPAD_3 0x4E8830C + +#define mmARC_FARM_ARC0_AUX_SCRATCHPAD_4 0x4E88310 + +#define mmARC_FARM_ARC0_AUX_SCRATCHPAD_5 0x4E88314 + +#define mmARC_FARM_ARC0_AUX_SCRATCHPAD_6 0x4E88318 + +#define mmARC_FARM_ARC0_AUX_SCRATCHPAD_7 0x4E8831C + +#define mmARC_FARM_ARC0_AUX_TOTAL_CBU_WR_CNT 0x4E88320 + +#define mmARC_FARM_ARC0_AUX_INFLIGHT_CBU_WR_CNT 0x4E88324 + +#define mmARC_FARM_ARC0_AUX_TOTAL_CBU_RD_CNT 0x4E88328 + +#define mmARC_FARM_ARC0_AUX_INFLIGHT_CBU_RD_CNT 0x4E8832C + +#define mmARC_FARM_ARC0_AUX_TOTAL_LBU_WR_CNT 0x4E88330 + +#define mmARC_FARM_ARC0_AUX_INFLIGHT_LBU_WR_CNT 0x4E88334 + +#define mmARC_FARM_ARC0_AUX_TOTAL_LBU_RD_CNT 0x4E88338 + +#define mmARC_FARM_ARC0_AUX_INFLIGHT_LBU_RD_CNT 0x4E8833C + +#define mmARC_FARM_ARC0_AUX_CBU_ARUSER_OVR 0x4E88350 + +#define mmARC_FARM_ARC0_AUX_CBU_ARUSER_OVR_EN 0x4E88354 + +#define mmARC_FARM_ARC0_AUX_CBU_AWUSER_OVR 0x4E88358 + +#define mmARC_FARM_ARC0_AUX_CBU_AWUSER_OVR_EN 0x4E8835C + +#define mmARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR 0x4E88360 + +#define mmARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR_EN 0x4E88364 + +#define mmARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR 0x4E88368 + +#define mmARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR_EN 0x4E8836C + +#define mmARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR 0x4E88370 + +#define mmARC_FARM_ARC0_AUX_CBU_LOCK_OVR 0x4E88374 + +#define mmARC_FARM_ARC0_AUX_CBU_PROT_OVR 0x4E88378 + +#define mmARC_FARM_ARC0_AUX_CBU_MAX_OUTSTANDING 0x4E8837C + +#define mmARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN 0x4E88380 + +#define mmARC_FARM_ARC0_AUX_CBU_FORCE_RSP_OK 0x4E88384 + +#define mmARC_FARM_ARC0_AUX_CBU_NO_WR_INFLIGHT 0x4E8838C + +#define mmARC_FARM_ARC0_AUX_CBU_SEI_INTR_ID 0x4E88390 + +#define mmARC_FARM_ARC0_AUX_LBU_ARUSER_OVR 0x4E88400 + +#define mmARC_FARM_ARC0_AUX_LBU_ARUSER_OVR_EN 0x4E88404 + +#define mmARC_FARM_ARC0_AUX_LBU_AWUSER_OVR 0x4E88408 + +#define mmARC_FARM_ARC0_AUX_LBU_AWUSER_OVR_EN 0x4E8840C + +#define mmARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR 0x4E88420 + +#define mmARC_FARM_ARC0_AUX_LBU_LOCK_OVR 0x4E88424 + +#define mmARC_FARM_ARC0_AUX_LBU_PROT_OVR 0x4E88428 + +#define mmARC_FARM_ARC0_AUX_LBU_MAX_OUTSTANDING 0x4E8842C + +#define mmARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN 0x4E88430 + +#define mmARC_FARM_ARC0_AUX_LBU_FORCE_RSP_OK 0x4E88434 + +#define mmARC_FARM_ARC0_AUX_LBU_NO_WR_INFLIGHT 0x4E8843C + +#define mmARC_FARM_ARC0_AUX_LBU_SEI_INTR_ID 0x4E88440 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_0 0x4E88500 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_1 0x4E88504 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_2 0x4E88508 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_3 0x4E8850C + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_4 0x4E88510 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_5 0x4E88514 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_6 0x4E88518 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_7 0x4E8851C + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_0 0x4E88520 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_1 0x4E88524 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_2 0x4E88528 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_3 0x4E8852C + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_4 0x4E88530 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_5 0x4E88534 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_6 0x4E88538 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_7 0x4E8853C + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_0 0x4E88540 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_1 0x4E88544 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_2 0x4E88548 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_3 0x4E8854C + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_4 0x4E88550 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_5 0x4E88554 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_6 0x4E88558 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_7 0x4E8855C + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_0 0x4E88560 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_1 0x4E88564 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_2 0x4E88568 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_3 0x4E8856C + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_4 0x4E88570 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_5 0x4E88574 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_6 0x4E88578 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_7 0x4E8857C + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_0 0x4E88580 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_1 0x4E88584 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_2 0x4E88588 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_3 0x4E8858C + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_4 0x4E88590 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_5 0x4E88594 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_6 0x4E88598 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_7 0x4E8859C + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x4E885A0 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x4E885A4 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x4E885A8 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x4E885AC + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x4E885B0 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x4E885B4 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x4E885B8 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x4E885BC + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x4E885C0 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x4E885C4 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x4E885C8 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x4E885CC + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x4E885D0 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x4E885D4 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x4E885D8 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x4E885DC + +#define mmARC_FARM_ARC0_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x4E885E0 + +#define mmARC_FARM_ARC0_AUX_NIC_Q_VLD_ENTRY_MASK 0x4E885E4 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_DROP_EN 0x4E88620 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_WARN_MSG 0x4E88624 + +#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_ALERT_MSG 0x4E88628 + +#define mmARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWPROT 0x4E88630 + +#define mmARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWUSER 0x4E88634 + +#define mmARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWBURST 0x4E88638 + +#define mmARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWLOCK 0x4E8863C + +#define mmARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWCACHE 0x4E88640 + +#define mmARC_FARM_ARC0_AUX_DCCM_WRR_ARB_WEIGHT 0x4E88644 + +#define mmARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x4E88648 + +#define mmARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_CNT 0x4E8864C + +#define mmARC_FARM_ARC0_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x4E88650 + +#define mmARC_FARM_ARC0_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x4E88654 + +#define mmARC_FARM_ARC0_AUX_QMAN_CQ_SHADOW_CI 0x4E88658 + +#define mmARC_FARM_ARC0_AUX_QMAN_ARC_CQ_SHADOW_CI 0x4E8865C + +#define mmARC_FARM_ARC0_AUX_AUX2APB_PROT 0x4E88700 + +#define mmARC_FARM_ARC0_AUX_LBW_FORK_WIN_EN 0x4E88704 + +#define mmARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x4E88708 + +#define mmARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x4E8870C + +#define mmARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x4E88710 + +#define mmARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x4E88714 + +#define mmARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR0 0x4E88718 + +#define mmARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK0 0x4E8871C + +#define mmARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR1 0x4E88720 + +#define mmARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK1 0x4E88724 + +#define mmARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR0 0x4E88728 + +#define mmARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR1 0x4E8872C + +#define mmARC_FARM_ARC0_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x4E88730 + +#define mmARC_FARM_ARC0_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x4E88734 + +#define mmARC_FARM_ARC0_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x4E88738 + +#define mmARC_FARM_ARC0_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x4E8873C + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_WIN_EN 0x4E88740 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_LSB 0x4E88750 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_MSB 0x4E88754 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_LSB 0x4E88758 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_MSB 0x4E8875C + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_LSB 0x4E88760 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_MSB 0x4E88764 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_LSB 0x4E88768 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_MSB 0x4E8876C + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_LSB 0x4E88770 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_MSB 0x4E88774 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_LSB 0x4E88778 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_MSB 0x4E8877C + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_LSB 0x4E88780 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_MSB 0x4E88784 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_LSB 0x4E88788 + +#define mmARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_MSB 0x4E8878C + +#define mmARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_LSB 0x4E88790 + +#define mmARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_MSB 0x4E88794 + +#define mmARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_BRESP 0x4E88798 + +#define mmARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_RRESP 0x4E8879C + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_0 0x4E88800 + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_1 0x4E88804 + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_2 0x4E88808 + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_3 0x4E8880C + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_4 0x4E88810 + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_5 0x4E88814 + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_6 0x4E88818 + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_7 0x4E8881C + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_8 0x4E88820 + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_9 0x4E88824 + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_10 0x4E88828 + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_11 0x4E8882C + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_12 0x4E88830 + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_13 0x4E88834 + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_14 0x4E88838 + +#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_15 0x4E8883C + +#define mmARC_FARM_ARC0_AUX_DCCM_TRMINATE_AWADDR_ERR 0x4E88840 + +#define mmARC_FARM_ARC0_AUX_DCCM_TRMINATE_ARADDR_ERR 0x4E88844 + +#define mmARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_BRESP 0x4E88848 + +#define mmARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_RRESP 0x4E8884C + +#define mmARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_EN 0x4E88850 + +#define mmARC_FARM_ARC0_AUX_CFG_DCCM_SECURE_REGION 0x4E88854 + +#define mmARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x4E88900 + +#define mmARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_CTL 0x4E88904 + +#define mmARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x4E88908 + +#define mmARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR 0x4E8890C + +#define mmARC_FARM_ARC0_AUX_ARC_ACC_ENGS_BUSER 0x4E88910 + +#define mmARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN 0x4E88920 + +#endif /* ASIC_REG_ARC_FARM_ARC0_AUX_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_dup_eng_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_dup_eng_axuser_regs.h new file mode 100644 index 000000000000..bde077eed285 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_dup_eng_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ARC_FARM_ARC0_DUP_ENG_AXUSER_REGS_H_ +#define ASIC_REG_ARC_FARM_ARC0_DUP_ENG_AXUSER_REGS_H_ + +/* + ***************************************** + * ARC_FARM_ARC0_DUP_ENG_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_ASID 0x4E89900 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_MMU_BP 0x4E89904 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_STRONG_ORDER 0x4E89908 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_NO_SNOOP 0x4E8990C + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_WR_REDUCTION 0x4E89910 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_RD_ATOMIC 0x4E89914 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_QOS 0x4E89918 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_RSVD 0x4E8991C + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_EMEM_CPAGE 0x4E89920 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_CORE 0x4E89924 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_E2E_COORD 0x4E89928 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_WR_OVRD_LO 0x4E89930 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_WR_OVRD_HI 0x4E89934 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_RD_OVRD_LO 0x4E89938 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_RD_OVRD_HI 0x4E8993C + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_COORD 0x4E89940 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_LOCK 0x4E89944 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_RSVD 0x4E89948 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_OVRD 0x4E8994C + +#endif /* ASIC_REG_ARC_FARM_ARC0_DUP_ENG_AXUSER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_dup_eng_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_dup_eng_regs.h new file mode 100644 index 000000000000..491af75c12c3 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_dup_eng_regs.h @@ -0,0 +1,575 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ARC_FARM_ARC0_DUP_ENG_REGS_H_ +#define ASIC_REG_ARC_FARM_ARC0_DUP_ENG_REGS_H_ + +/* + ***************************************** + * ARC_FARM_ARC0_DUP_ENG + * (Prototype: ARC_DUP_ENG) + ***************************************** + */ + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_0 0x4E89000 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_1 0x4E89004 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_2 0x4E89008 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_3 0x4E8900C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_4 0x4E89010 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_5 0x4E89014 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_6 0x4E89018 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_7 0x4E8901C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_8 0x4E89020 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_9 0x4E89024 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_10 0x4E89028 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_11 0x4E8902C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_12 0x4E89030 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_13 0x4E89034 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_14 0x4E89038 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_15 0x4E8903C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_16 0x4E89040 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_17 0x4E89044 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_18 0x4E89048 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_19 0x4E8904C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_20 0x4E89050 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_21 0x4E89054 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_22 0x4E89058 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_23 0x4E8905C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_24 0x4E89060 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_MME_ENG_ADDR_0 0x4E89064 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_MME_ENG_ADDR_1 0x4E89068 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_MME_ENG_ADDR_2 0x4E8906C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_MME_ENG_ADDR_3 0x4E89070 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_0 0x4E89074 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_1 0x4E89078 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_2 0x4E8907C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_3 0x4E89080 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_4 0x4E89084 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_5 0x4E89088 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_6 0x4E8908C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_7 0x4E89090 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_8 0x4E89094 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_9 0x4E89098 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_10 0x4E8909C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_11 0x4E890A0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_12 0x4E890A4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_13 0x4E890A8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_14 0x4E890AC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_15 0x4E890B0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_16 0x4E890B4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_17 0x4E890B8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_18 0x4E890BC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_19 0x4E890C0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_20 0x4E890C4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_21 0x4E890C8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_22 0x4E890CC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_23 0x4E890D0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_ADDR_0 0x4E890D4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_ADDR_1 0x4E890D8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_ADDR_2 0x4E890DC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_ADDR_3 0x4E890E0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_ADDR_4 0x4E890E4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_ADDR_5 0x4E890E8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_ADDR_6 0x4E890EC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_ADDR_7 0x4E890F0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_PDMA_ENG_ADDR_0 0x4E890F4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_PDMA_ENG_ADDR_1 0x4E890F8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_ROT_ENG_ADDR_0 0x4E890FC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_ROT_ENG_ADDR_1 0x4E89100 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_0 0x4E89104 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_1 0x4E89108 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_2 0x4E8910C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_3 0x4E89110 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_4 0x4E89114 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_5 0x4E89118 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_6 0x4E8911C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_7 0x4E89120 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_8 0x4E89124 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_9 0x4E89128 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_10 0x4E8912C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_11 0x4E89130 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_12 0x4E89134 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_13 0x4E89138 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_14 0x4E8913C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_15 0x4E89140 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_MASK 0x4E89200 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_MME_ENG_MASK 0x4E89204 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_MASK 0x4E89208 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_PDMA_ENG_MASK 0x4E8920C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_ROT_ENG_MASK 0x4E89210 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_MASK 0x4E89214 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_MASK_0 0x4E89218 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_MASK_1 0x4E8921C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_MASK_2 0x4E89220 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_MASK_3 0x4E89224 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_MASK_4 0x4E89228 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_MASK_5 0x4E8922C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_MASK_6 0x4E89230 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_MASK_7 0x4E89234 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_0 0x4E89238 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_1 0x4E8923C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_2 0x4E89240 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_3 0x4E89244 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_4 0x4E89248 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_5 0x4E8924C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_6 0x4E89250 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_7 0x4E89254 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_8 0x4E89258 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_9 0x4E8925C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_10 0x4E89260 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_11 0x4E89264 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_12 0x4E89268 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_13 0x4E8926C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_1_0 0x4E89288 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_1_1 0x4E8928C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_1_2 0x4E89290 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_1_3 0x4E89294 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_1_4 0x4E89298 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_1_5 0x4E8929C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_2_0 0x4E892A0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_2_1 0x4E892A4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_2_2 0x4E892A8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_2_3 0x4E892AC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_2_4 0x4E892B0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_2_5 0x4E892B4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_3_0 0x4E892B8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_3_1 0x4E892BC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_3_2 0x4E892C0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_3_3 0x4E892C4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_3_4 0x4E892C8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_3_5 0x4E892CC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GENERAL_CFG 0x4E892D0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_BP_CFG 0x4E892D4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_0 0x4E892D8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_1 0x4E892DC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_2 0x4E892E0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_3 0x4E892E4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_4 0x4E892E8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_5 0x4E892EC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_6 0x4E892F0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_7 0x4E892F4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_8 0x4E892F8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_9 0x4E892FC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_10 0x4E89300 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_11 0x4E89304 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_12 0x4E89308 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_13 0x4E8930C + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_DBG_IN_GRP_TRANS_0 0x4E894A0 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_DBG_IN_GRP_TRANS_1 0x4E894A4 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_DBG_IN_GRP_TRANS_2 0x4E894A8 + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_DBG_STS 0x4E894AC + +#define mmARC_FARM_ARC0_DUP_ENG_DUP_DBG_OUT_RQ_CNT 0x4E894B0 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_0 0x4E894B4 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_1 0x4E894B8 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_2 0x4E894BC + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_3 0x4E894C0 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_4 0x4E894C4 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_5 0x4E894C8 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_6 0x4E894CC + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_7 0x4E894D0 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_8 0x4E894D4 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_9 0x4E894D8 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_10 0x4E894DC + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_11 0x4E894E0 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_12 0x4E894E4 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_13 0x4E894E8 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_14 0x4E894EC + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_15 0x4E894F0 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_16 0x4E894F4 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_17 0x4E894F8 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_18 0x4E894FC + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_19 0x4E89500 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_20 0x4E89504 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_21 0x4E89508 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_22 0x4E8950C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_23 0x4E89510 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_24 0x4E89514 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_25 0x4E89518 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_26 0x4E8951C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_27 0x4E89520 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_28 0x4E89524 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_29 0x4E89528 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_30 0x4E8952C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_31 0x4E89530 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_32 0x4E89534 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_33 0x4E89538 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_34 0x4E8953C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_35 0x4E89540 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_36 0x4E89544 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_37 0x4E89548 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_38 0x4E8954C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_39 0x4E89550 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_40 0x4E89554 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_41 0x4E89558 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_42 0x4E8955C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_43 0x4E89560 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_44 0x4E89564 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_45 0x4E89568 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_46 0x4E8956C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_47 0x4E89570 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_48 0x4E89574 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_49 0x4E89578 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_50 0x4E8957C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_51 0x4E89580 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_52 0x4E89584 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_53 0x4E89588 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_54 0x4E8958C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_55 0x4E89590 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_56 0x4E89594 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_57 0x4E89598 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_58 0x4E8959C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_59 0x4E895A0 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_60 0x4E895A4 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_61 0x4E895A8 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_62 0x4E895AC + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_63 0x4E895B0 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_0 0x4E895B4 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_1 0x4E895B8 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_2 0x4E895BC + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_3 0x4E895C0 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_4 0x4E895C4 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_5 0x4E895C8 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_6 0x4E895CC + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_7 0x4E895D0 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_8 0x4E895D4 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_9 0x4E895D8 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_10 0x4E895DC + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_11 0x4E895E0 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_12 0x4E895E4 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_13 0x4E895E8 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_14 0x4E895EC + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_15 0x4E895F0 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_16 0x4E895F4 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_17 0x4E895F8 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_18 0x4E895FC + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_19 0x4E89600 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_20 0x4E89604 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_21 0x4E89608 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_22 0x4E8960C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_23 0x4E89610 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_24 0x4E89614 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_25 0x4E89618 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_26 0x4E8961C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_27 0x4E89620 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_28 0x4E89624 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_29 0x4E89628 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_30 0x4E8962C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_31 0x4E89630 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_32 0x4E89634 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_33 0x4E89638 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_34 0x4E8963C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_35 0x4E89640 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_36 0x4E89644 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_37 0x4E89648 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_38 0x4E8964C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_39 0x4E89650 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_40 0x4E89654 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_41 0x4E89658 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_42 0x4E8965C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_43 0x4E89660 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_44 0x4E89664 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_45 0x4E89668 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_46 0x4E8966C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_47 0x4E89670 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_48 0x4E89674 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_49 0x4E89678 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_50 0x4E8967C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_51 0x4E89680 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_52 0x4E89684 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_53 0x4E89688 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_54 0x4E8968C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_55 0x4E89690 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_56 0x4E89694 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_57 0x4E89698 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_58 0x4E8969C + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_59 0x4E896A0 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_60 0x4E896A4 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_61 0x4E896A8 + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_62 0x4E896AC + +#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_63 0x4E896B0 + +#endif /* ASIC_REG_ARC_FARM_ARC0_DUP_ENG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_masks.h new file mode 100644 index 000000000000..12d6a124a2e9 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_masks.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ARC_FARM_KDMA_CTX_AXUSER_MASKS_H_ +#define ASIC_REG_ARC_FARM_KDMA_CTX_AXUSER_MASKS_H_ + +/* + ***************************************** + * ARC_FARM_KDMA_CTX_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_ASID */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_MASK 0x3FF +#define ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_SHIFT 16 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_MASK 0x3FF0000 + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_WR_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_WR_MASK 0x1 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_RD_SHIFT 4 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_RD_MASK 0x10 + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER_WR_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER_WR_MASK 0x1 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER_RD_SHIFT 4 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER_RD_MASK 0x10 + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP_WR_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP_WR_MASK 0x1 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP_RD_SHIFT 4 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP_RD_MASK 0x10 + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_IND_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_IND_MASK 0x1 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_DTYPE_SHIFT 4 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_DTYPE_MASK 0xF0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_OP_SHIFT 8 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_OP_MASK 0x300 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_ROUND_SHIFT 12 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_ROUND_MASK 0x3000 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_MAX_SHIFT 16 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_MAX_MASK 0x10000 + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_IND_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_IND_MASK 0x3 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_ADDITION_SIZE_SHIFT 4 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_ADDITION_SIZE_MASK 0xFF0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_MSB_MASK_SHIFT 12 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_MSB_MASK_MASK 0x1F000 + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_QOS */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_QOS_WR_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_QOS_WR_MASK 0xF +#define ARC_FARM_KDMA_CTX_AXUSER_HB_QOS_RD_SHIFT 4 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_QOS_RD_MASK 0x70 + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_27_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_27_MASK 0x1 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_28_SHIFT 1 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_28_MASK 0x2 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_30_SHIFT 2 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_30_MASK 0x4 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_31_SHIFT 3 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_31_MASK 0x8 + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE_WR_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE_WR_MASK 0x1 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE_RD_SHIFT 4 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE_RD_MASK 0x10 + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_CORE */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_CORE_WR_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_CORE_WR_MASK 0x1 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_CORE_RD_SHIFT 4 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_CORE_RD_MASK 0x10 + +/* ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD */ +#define ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD_X_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD_X_MASK 0x1F +#define ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD_Y_SHIFT 8 +#define ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD_Y_MASK 0xF00 + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_LO */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_LO_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_LO_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_HI */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_HI_VAL_MASK 0x3FF + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_LO */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_LO_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_LO_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_HI */ +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_HI_VAL_MASK 0x3FF + +/* ARC_FARM_KDMA_CTX_AXUSER_LB_COORD */ +#define ARC_FARM_KDMA_CTX_AXUSER_LB_COORD_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_LB_COORD_VAL_MASK 0x3FF + +/* ARC_FARM_KDMA_CTX_AXUSER_LB_LOCK */ +#define ARC_FARM_KDMA_CTX_AXUSER_LB_LOCK_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_LB_LOCK_VAL_MASK 0x1 + +/* ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD */ +#define ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD_BIT_21_11_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD_BIT_21_11_MASK 0x7FF +#define ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD_BIT_22_SHIFT 12 +#define ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD_BIT_22_MASK 0x1000 + +/* ARC_FARM_KDMA_CTX_AXUSER_LB_OVRD */ +#define ARC_FARM_KDMA_CTX_AXUSER_LB_OVRD_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_AXUSER_LB_OVRD_VAL_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_ARC_FARM_KDMA_CTX_AXUSER_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_regs.h new file mode 100644 index 000000000000..23f9d2df52a7 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ARC_FARM_KDMA_CTX_AXUSER_REGS_H_ +#define ASIC_REG_ARC_FARM_KDMA_CTX_AXUSER_REGS_H_ + +/* + ***************************************** + * ARC_FARM_KDMA_CTX_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_ASID 0x4E8B800 + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP 0x4E8B804 + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER 0x4E8B808 + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP 0x4E8B80C + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION 0x4E8B810 + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC 0x4E8B814 + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_QOS 0x4E8B818 + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_RSVD 0x4E8B81C + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE 0x4E8B820 + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_CORE 0x4E8B824 + +#define mmARC_FARM_KDMA_CTX_AXUSER_E2E_COORD 0x4E8B828 + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_LO 0x4E8B830 + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_HI 0x4E8B834 + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_LO 0x4E8B838 + +#define mmARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_HI 0x4E8B83C + +#define mmARC_FARM_KDMA_CTX_AXUSER_LB_COORD 0x4E8B840 + +#define mmARC_FARM_KDMA_CTX_AXUSER_LB_LOCK 0x4E8B844 + +#define mmARC_FARM_KDMA_CTX_AXUSER_LB_RSVD 0x4E8B848 + +#define mmARC_FARM_KDMA_CTX_AXUSER_LB_OVRD 0x4E8B84C + +#endif /* ASIC_REG_ARC_FARM_KDMA_CTX_AXUSER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_masks.h new file mode 100644 index 000000000000..bee4de0b28d6 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_masks.h @@ -0,0 +1,221 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ARC_FARM_KDMA_CTX_MASKS_H_ +#define ASIC_REG_ARC_FARM_KDMA_CTX_MASKS_H_ + +/* + ***************************************** + * ARC_FARM_KDMA_CTX + * (Prototype: DMA_CORE_CTX) + ***************************************** + */ + +/* ARC_FARM_KDMA_CTX_RATE_LIM_TKN */ +#define ARC_FARM_KDMA_CTX_RATE_LIM_TKN_RD_SHIFT 0 +#define ARC_FARM_KDMA_CTX_RATE_LIM_TKN_RD_MASK 0xFF +#define ARC_FARM_KDMA_CTX_RATE_LIM_TKN_WR_SHIFT 16 +#define ARC_FARM_KDMA_CTX_RATE_LIM_TKN_WR_MASK 0xFF0000 + +/* ARC_FARM_KDMA_CTX_PWRLP */ +#define ARC_FARM_KDMA_CTX_PWRLP_DATA_SHIFT 0 +#define ARC_FARM_KDMA_CTX_PWRLP_DATA_MASK 0xFF +#define ARC_FARM_KDMA_CTX_PWRLP_EN_SHIFT 8 +#define ARC_FARM_KDMA_CTX_PWRLP_EN_MASK 0x100 + +/* ARC_FARM_KDMA_CTX_TE_NUMROWS */ +#define ARC_FARM_KDMA_CTX_TE_NUMROWS_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_TE_NUMROWS_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_IDX */ +#define ARC_FARM_KDMA_CTX_IDX_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_IDX_VAL_MASK 0xFFFF + +/* ARC_FARM_KDMA_CTX_IDX_INC */ +#define ARC_FARM_KDMA_CTX_IDX_INC_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_IDX_INC_VAL_MASK 0xFF + +/* ARC_FARM_KDMA_CTX_CTRL */ +#define ARC_FARM_KDMA_CTX_CTRL_TRANSPOSE_SHIFT 0 +#define ARC_FARM_KDMA_CTX_CTRL_TRANSPOSE_MASK 0x1 +#define ARC_FARM_KDMA_CTX_CTRL_DTYPE_SHIFT 4 +#define ARC_FARM_KDMA_CTX_CTRL_DTYPE_MASK 0x30 +#define ARC_FARM_KDMA_CTX_CTRL_COMPRESS_SHIFT 8 +#define ARC_FARM_KDMA_CTX_CTRL_COMPRESS_MASK 0x100 +#define ARC_FARM_KDMA_CTX_CTRL_DECOMPRESS_SHIFT 9 +#define ARC_FARM_KDMA_CTX_CTRL_DECOMPRESS_MASK 0x200 +#define ARC_FARM_KDMA_CTX_CTRL_RD_UNCACHEABLE_SHIFT 12 +#define ARC_FARM_KDMA_CTX_CTRL_RD_UNCACHEABLE_MASK 0x1000 + +/* ARC_FARM_KDMA_CTX_SRC_TSIZE_0 */ +#define ARC_FARM_KDMA_CTX_SRC_TSIZE_0_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_TSIZE_0_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_SRC_TSIZE_1 */ +#define ARC_FARM_KDMA_CTX_SRC_TSIZE_1_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_TSIZE_1_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_SRC_STRIDE_1 */ +#define ARC_FARM_KDMA_CTX_SRC_STRIDE_1_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_STRIDE_1_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_SRC_TSIZE_2 */ +#define ARC_FARM_KDMA_CTX_SRC_TSIZE_2_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_TSIZE_2_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_SRC_STRIDE_2 */ +#define ARC_FARM_KDMA_CTX_SRC_STRIDE_2_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_STRIDE_2_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_SRC_TSIZE_3 */ +#define ARC_FARM_KDMA_CTX_SRC_TSIZE_3_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_TSIZE_3_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_SRC_STRIDE_3 */ +#define ARC_FARM_KDMA_CTX_SRC_STRIDE_3_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_STRIDE_3_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_SRC_TSIZE_4 */ +#define ARC_FARM_KDMA_CTX_SRC_TSIZE_4_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_TSIZE_4_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_SRC_STRIDE_4 */ +#define ARC_FARM_KDMA_CTX_SRC_STRIDE_4_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_STRIDE_4_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_TSIZE_1 */ +#define ARC_FARM_KDMA_CTX_DST_TSIZE_1_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_TSIZE_1_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_STRIDE_1 */ +#define ARC_FARM_KDMA_CTX_DST_STRIDE_1_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_STRIDE_1_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_TSIZE_2 */ +#define ARC_FARM_KDMA_CTX_DST_TSIZE_2_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_TSIZE_2_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_STRIDE_2 */ +#define ARC_FARM_KDMA_CTX_DST_STRIDE_2_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_STRIDE_2_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_TSIZE_3 */ +#define ARC_FARM_KDMA_CTX_DST_TSIZE_3_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_TSIZE_3_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_STRIDE_3 */ +#define ARC_FARM_KDMA_CTX_DST_STRIDE_3_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_STRIDE_3_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_TSIZE_4 */ +#define ARC_FARM_KDMA_CTX_DST_TSIZE_4_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_TSIZE_4_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_STRIDE_4 */ +#define ARC_FARM_KDMA_CTX_DST_STRIDE_4_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_STRIDE_4_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_WR_COMP_ADDR_HI */ +#define ARC_FARM_KDMA_CTX_WR_COMP_ADDR_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_WR_COMP_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_WR_COMP_ADDR_LO */ +#define ARC_FARM_KDMA_CTX_WR_COMP_ADDR_LO_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_WR_COMP_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_WR_COMP_WDATA */ +#define ARC_FARM_KDMA_CTX_WR_COMP_WDATA_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_WR_COMP_WDATA_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_SRC_OFFSET_LO */ +#define ARC_FARM_KDMA_CTX_SRC_OFFSET_LO_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_OFFSET_LO_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_SRC_OFFSET_HI */ +#define ARC_FARM_KDMA_CTX_SRC_OFFSET_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_OFFSET_HI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_OFFSET_LO */ +#define ARC_FARM_KDMA_CTX_DST_OFFSET_LO_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_OFFSET_LO_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_OFFSET_HI */ +#define ARC_FARM_KDMA_CTX_DST_OFFSET_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_OFFSET_HI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_SRC_BASE_LO */ +#define ARC_FARM_KDMA_CTX_SRC_BASE_LO_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_SRC_BASE_HI */ +#define ARC_FARM_KDMA_CTX_SRC_BASE_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_SRC_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_BASE_LO */ +#define ARC_FARM_KDMA_CTX_DST_BASE_LO_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_BASE_HI */ +#define ARC_FARM_KDMA_CTX_DST_BASE_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_DST_TSIZE_0 */ +#define ARC_FARM_KDMA_CTX_DST_TSIZE_0_VAL_SHIFT 0 +#define ARC_FARM_KDMA_CTX_DST_TSIZE_0_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_CTX_COMMIT */ +#define ARC_FARM_KDMA_CTX_COMMIT_WR_COMP_EN_SHIFT 0 +#define ARC_FARM_KDMA_CTX_COMMIT_WR_COMP_EN_MASK 0x1 +#define ARC_FARM_KDMA_CTX_COMMIT_ENDIAN_SWAP_SHIFT 1 +#define ARC_FARM_KDMA_CTX_COMMIT_ENDIAN_SWAP_MASK 0x6 +#define ARC_FARM_KDMA_CTX_COMMIT_MEM_SET_SHIFT 4 +#define ARC_FARM_KDMA_CTX_COMMIT_MEM_SET_MASK 0x10 +#define ARC_FARM_KDMA_CTX_COMMIT_BF16_SHIFT 6 +#define ARC_FARM_KDMA_CTX_COMMIT_BF16_MASK 0x40 +#define ARC_FARM_KDMA_CTX_COMMIT_FP16_SHIFT 7 +#define ARC_FARM_KDMA_CTX_COMMIT_FP16_MASK 0x80 +#define ARC_FARM_KDMA_CTX_COMMIT_CTX_ID_INC_SHIFT 8 +#define ARC_FARM_KDMA_CTX_COMMIT_CTX_ID_INC_MASK 0x100 +#define ARC_FARM_KDMA_CTX_COMMIT_ADD_OFFSET_0_SHIFT 9 +#define ARC_FARM_KDMA_CTX_COMMIT_ADD_OFFSET_0_MASK 0x200 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE0_FROM_DST_SIZE0_SHIFT 10 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE0_FROM_DST_SIZE0_MASK 0x400 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_OFST_FROM_DST_OFST_SHIFT 11 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_OFST_FROM_DST_OFST_MASK 0x800 +#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM1_SHIFT 12 +#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM1_MASK 0x1000 +#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM2_SHIFT 13 +#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM2_MASK 0x2000 +#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM3_SHIFT 14 +#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM3_MASK 0x4000 +#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM4_SHIFT 15 +#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM4_MASK 0x8000 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE1_FROM_DST_SIZE1_SHIFT 16 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE1_FROM_DST_SIZE1_MASK 0x10000 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE2_FROM_DST_SIZE2_SHIFT 17 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE2_FROM_DST_SIZE2_MASK 0x20000 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE3_FROM_DST_SIZE3_SHIFT 18 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE3_FROM_DST_SIZE3_MASK 0x40000 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE4_FROM_DST_SIZE4_SHIFT 19 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE4_FROM_DST_SIZE4_MASK 0x80000 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD1_FROM_DST_STRD1_SHIFT 20 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD1_FROM_DST_STRD1_MASK 0x100000 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD2_FROM_DST_STRD2_SHIFT 21 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD2_FROM_DST_STRD2_MASK 0x200000 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD3_FROM_DST_STRD3_SHIFT 22 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD3_FROM_DST_STRD3_MASK 0x400000 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD4_FROM_DST_STRD4_SHIFT 23 +#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD4_FROM_DST_STRD4_MASK 0x800000 +#define ARC_FARM_KDMA_CTX_COMMIT_LIN_SHIFT 31 +#define ARC_FARM_KDMA_CTX_COMMIT_LIN_MASK 0x80000000 + +#endif /* ASIC_REG_ARC_FARM_KDMA_CTX_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_regs.h new file mode 100644 index 000000000000..b9f09e8199e6 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_regs.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ARC_FARM_KDMA_CTX_REGS_H_ +#define ASIC_REG_ARC_FARM_KDMA_CTX_REGS_H_ + +/* + ***************************************** + * ARC_FARM_KDMA_CTX + * (Prototype: DMA_CORE_CTX) + ***************************************** + */ + +#define mmARC_FARM_KDMA_CTX_RATE_LIM_TKN 0x4E8B860 + +#define mmARC_FARM_KDMA_CTX_PWRLP 0x4E8B864 + +#define mmARC_FARM_KDMA_CTX_TE_NUMROWS 0x4E8B868 + +#define mmARC_FARM_KDMA_CTX_IDX 0x4E8B86C + +#define mmARC_FARM_KDMA_CTX_IDX_INC 0x4E8B870 + +#define mmARC_FARM_KDMA_CTX_CTRL 0x4E8B874 + +#define mmARC_FARM_KDMA_CTX_SRC_TSIZE_0 0x4E8B878 + +#define mmARC_FARM_KDMA_CTX_SRC_TSIZE_1 0x4E8B87C + +#define mmARC_FARM_KDMA_CTX_SRC_STRIDE_1 0x4E8B880 + +#define mmARC_FARM_KDMA_CTX_SRC_TSIZE_2 0x4E8B884 + +#define mmARC_FARM_KDMA_CTX_SRC_STRIDE_2 0x4E8B888 + +#define mmARC_FARM_KDMA_CTX_SRC_TSIZE_3 0x4E8B88C + +#define mmARC_FARM_KDMA_CTX_SRC_STRIDE_3 0x4E8B890 + +#define mmARC_FARM_KDMA_CTX_SRC_TSIZE_4 0x4E8B894 + +#define mmARC_FARM_KDMA_CTX_SRC_STRIDE_4 0x4E8B898 + +#define mmARC_FARM_KDMA_CTX_DST_TSIZE_1 0x4E8B89C + +#define mmARC_FARM_KDMA_CTX_DST_STRIDE_1 0x4E8B8A0 + +#define mmARC_FARM_KDMA_CTX_DST_TSIZE_2 0x4E8B8A4 + +#define mmARC_FARM_KDMA_CTX_DST_STRIDE_2 0x4E8B8A8 + +#define mmARC_FARM_KDMA_CTX_DST_TSIZE_3 0x4E8B8AC + +#define mmARC_FARM_KDMA_CTX_DST_STRIDE_3 0x4E8B8B0 + +#define mmARC_FARM_KDMA_CTX_DST_TSIZE_4 0x4E8B8B4 + +#define mmARC_FARM_KDMA_CTX_DST_STRIDE_4 0x4E8B8B8 + +#define mmARC_FARM_KDMA_CTX_WR_COMP_ADDR_HI 0x4E8B8BC + +#define mmARC_FARM_KDMA_CTX_WR_COMP_ADDR_LO 0x4E8B8C0 + +#define mmARC_FARM_KDMA_CTX_WR_COMP_WDATA 0x4E8B8C4 + +#define mmARC_FARM_KDMA_CTX_SRC_OFFSET_LO 0x4E8B8C8 + +#define mmARC_FARM_KDMA_CTX_SRC_OFFSET_HI 0x4E8B8CC + +#define mmARC_FARM_KDMA_CTX_DST_OFFSET_LO 0x4E8B8D0 + +#define mmARC_FARM_KDMA_CTX_DST_OFFSET_HI 0x4E8B8D4 + +#define mmARC_FARM_KDMA_CTX_SRC_BASE_LO 0x4E8B8D8 + +#define mmARC_FARM_KDMA_CTX_SRC_BASE_HI 0x4E8B8DC + +#define mmARC_FARM_KDMA_CTX_DST_BASE_LO 0x4E8B8E0 + +#define mmARC_FARM_KDMA_CTX_DST_BASE_HI 0x4E8B8E4 + +#define mmARC_FARM_KDMA_CTX_DST_TSIZE_0 0x4E8B8E8 + +#define mmARC_FARM_KDMA_CTX_COMMIT 0x4E8B8EC + +#endif /* ASIC_REG_ARC_FARM_KDMA_CTX_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_kdma_cgm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_kdma_cgm_regs.h new file mode 100644 index 000000000000..d6dd2c066fa9 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_kdma_cgm_regs.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ARC_FARM_KDMA_KDMA_CGM_REGS_H_ +#define ASIC_REG_ARC_FARM_KDMA_KDMA_CGM_REGS_H_ + +/* + ***************************************** + * ARC_FARM_KDMA_KDMA_CGM + * (Prototype: QMAN_CGM) + ***************************************** + */ + +#define mmARC_FARM_KDMA_KDMA_CGM_CFG 0x4E8BE00 + +#define mmARC_FARM_KDMA_KDMA_CGM_STS 0x4E8BE04 + +#define mmARC_FARM_KDMA_KDMA_CGM_CFG1 0x4E8BE08 + +#endif /* ASIC_REG_ARC_FARM_KDMA_KDMA_CGM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_masks.h new file mode 100644 index 000000000000..5903dbacec80 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_masks.h @@ -0,0 +1,415 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ARC_FARM_KDMA_MASKS_H_ +#define ASIC_REG_ARC_FARM_KDMA_MASKS_H_ + +/* + ***************************************** + * ARC_FARM_KDMA + * (Prototype: DMA_CORE) + ***************************************** + */ + +/* ARC_FARM_KDMA_CFG_0 */ +#define ARC_FARM_KDMA_CFG_0_EN_SHIFT 0 +#define ARC_FARM_KDMA_CFG_0_EN_MASK 0x1 + +/* ARC_FARM_KDMA_CFG_1 */ +#define ARC_FARM_KDMA_CFG_1_HALT_SHIFT 0 +#define ARC_FARM_KDMA_CFG_1_HALT_MASK 0x1 +#define ARC_FARM_KDMA_CFG_1_FLUSH_SHIFT 1 +#define ARC_FARM_KDMA_CFG_1_FLUSH_MASK 0x2 + +/* ARC_FARM_KDMA_PROT */ +#define ARC_FARM_KDMA_PROT_VAL_SHIFT 0 +#define ARC_FARM_KDMA_PROT_VAL_MASK 0x1 +#define ARC_FARM_KDMA_PROT_ERR_VAL_SHIFT 1 +#define ARC_FARM_KDMA_PROT_ERR_VAL_MASK 0x2 + +/* ARC_FARM_KDMA_CKG */ +#define ARC_FARM_KDMA_CKG_HBW_RBUF_SHIFT 0 +#define ARC_FARM_KDMA_CKG_HBW_RBUF_MASK 0x1 +#define ARC_FARM_KDMA_CKG_LBW_RBUF_KDMA_SHIFT 1 +#define ARC_FARM_KDMA_CKG_LBW_RBUF_KDMA_MASK 0x2 +#define ARC_FARM_KDMA_CKG_TE_SHIFT 2 +#define ARC_FARM_KDMA_CKG_TE_MASK 0x4 + +/* ARC_FARM_KDMA_RD_GLBL */ +#define ARC_FARM_KDMA_RD_GLBL_LBW_VIA_HBW_SHIFT 0 +#define ARC_FARM_KDMA_RD_GLBL_LBW_VIA_HBW_MASK 0x1 +#define ARC_FARM_KDMA_RD_GLBL_HBW_FORCE_MISS_SHIFT 4 +#define ARC_FARM_KDMA_RD_GLBL_HBW_FORCE_MISS_MASK 0x10 +#define ARC_FARM_KDMA_RD_GLBL_LBW_FORCE_MISS_SHIFT 5 +#define ARC_FARM_KDMA_RD_GLBL_LBW_FORCE_MISS_MASK 0x20 + +/* ARC_FARM_KDMA_RD_HBW_MAX_OUTSTAND */ +#define ARC_FARM_KDMA_RD_HBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define ARC_FARM_KDMA_RD_HBW_MAX_OUTSTAND_VAL_MASK 0xFFF + +/* ARC_FARM_KDMA_RD_HBW_MAX_SIZE */ +#define ARC_FARM_KDMA_RD_HBW_MAX_SIZE_DATA_SHIFT 0 +#define ARC_FARM_KDMA_RD_HBW_MAX_SIZE_DATA_MASK 0xFFF +#define ARC_FARM_KDMA_RD_HBW_MAX_SIZE_MD_SHIFT 16 +#define ARC_FARM_KDMA_RD_HBW_MAX_SIZE_MD_MASK 0xFFF0000 + +/* ARC_FARM_KDMA_RD_HBW_ARCACHE */ +#define ARC_FARM_KDMA_RD_HBW_ARCACHE_VAL_SHIFT 0 +#define ARC_FARM_KDMA_RD_HBW_ARCACHE_VAL_MASK 0xF + +/* ARC_FARM_KDMA_RD_HBW_INFLIGHTS */ +#define ARC_FARM_KDMA_RD_HBW_INFLIGHTS_VAL_SHIFT 0 +#define ARC_FARM_KDMA_RD_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG */ +#define ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG_TOUT_SHIFT 0 +#define ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF +#define ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG_SAT_SHIFT 16 +#define ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 +#define ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG_EN_SHIFT 31 +#define ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG_EN_MASK 0x80000000 + +/* ARC_FARM_KDMA_RD_LBW_MAX_OUTSTAND */ +#define ARC_FARM_KDMA_RD_LBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define ARC_FARM_KDMA_RD_LBW_MAX_OUTSTAND_VAL_MASK 0xFFF + +/* ARC_FARM_KDMA_RD_LBW_MAX_SIZE */ +#define ARC_FARM_KDMA_RD_LBW_MAX_SIZE_DATA_SHIFT 0 +#define ARC_FARM_KDMA_RD_LBW_MAX_SIZE_DATA_MASK 0xFFF +#define ARC_FARM_KDMA_RD_LBW_MAX_SIZE_MD_SHIFT 16 +#define ARC_FARM_KDMA_RD_LBW_MAX_SIZE_MD_MASK 0xFFF0000 + +/* ARC_FARM_KDMA_RD_LBW_ARCACHE */ +#define ARC_FARM_KDMA_RD_LBW_ARCACHE_VAL_SHIFT 0 +#define ARC_FARM_KDMA_RD_LBW_ARCACHE_VAL_MASK 0xF + +/* ARC_FARM_KDMA_RD_LBW_INFLIGHTS */ +#define ARC_FARM_KDMA_RD_LBW_INFLIGHTS_VAL_SHIFT 0 +#define ARC_FARM_KDMA_RD_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG */ +#define ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG_TOUT_SHIFT 0 +#define ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF +#define ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG_SAT_SHIFT 16 +#define ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 +#define ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG_EN_SHIFT 31 +#define ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG_EN_MASK 0x80000000 + +/* ARC_FARM_KDMA_WR_HBW_MAX_OUTSTAND */ +#define ARC_FARM_KDMA_WR_HBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define ARC_FARM_KDMA_WR_HBW_MAX_OUTSTAND_VAL_MASK 0xFFFF + +/* ARC_FARM_KDMA_WR_HBW_MAX_AWID */ +#define ARC_FARM_KDMA_WR_HBW_MAX_AWID_VAL_SHIFT 0 +#define ARC_FARM_KDMA_WR_HBW_MAX_AWID_VAL_MASK 0x3FFF + +/* ARC_FARM_KDMA_WR_HBW_AWCACHE */ +#define ARC_FARM_KDMA_WR_HBW_AWCACHE_VAL_SHIFT 0 +#define ARC_FARM_KDMA_WR_HBW_AWCACHE_VAL_MASK 0xF + +/* ARC_FARM_KDMA_WR_HBW_INFLIGHTS */ +#define ARC_FARM_KDMA_WR_HBW_INFLIGHTS_VAL_SHIFT 0 +#define ARC_FARM_KDMA_WR_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG */ +#define ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG_TOUT_SHIFT 0 +#define ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF +#define ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG_SAT_SHIFT 16 +#define ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 +#define ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG_EN_SHIFT 31 +#define ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG_EN_MASK 0x80000000 + +/* ARC_FARM_KDMA_WR_LBW_MAX_OUTSTAND */ +#define ARC_FARM_KDMA_WR_LBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define ARC_FARM_KDMA_WR_LBW_MAX_OUTSTAND_VAL_MASK 0xFFFF + +/* ARC_FARM_KDMA_WR_LBW_MAX_AWID */ +#define ARC_FARM_KDMA_WR_LBW_MAX_AWID_VAL_SHIFT 0 +#define ARC_FARM_KDMA_WR_LBW_MAX_AWID_VAL_MASK 0x7F + +/* ARC_FARM_KDMA_WR_LBW_AWCACHE */ +#define ARC_FARM_KDMA_WR_LBW_AWCACHE_VAL_SHIFT 0 +#define ARC_FARM_KDMA_WR_LBW_AWCACHE_VAL_MASK 0xF + +/* ARC_FARM_KDMA_WR_LBW_INFLIGHTS */ +#define ARC_FARM_KDMA_WR_LBW_INFLIGHTS_VAL_SHIFT 0 +#define ARC_FARM_KDMA_WR_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG */ +#define ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG_TOUT_SHIFT 0 +#define ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF +#define ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG_SAT_SHIFT 16 +#define ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 +#define ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG_EN_SHIFT 31 +#define ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG_EN_MASK 0x80000000 + +/* ARC_FARM_KDMA_WR_COMP_MAX_OUTSTAND */ +#define ARC_FARM_KDMA_WR_COMP_MAX_OUTSTAND_VAL_SHIFT 0 +#define ARC_FARM_KDMA_WR_COMP_MAX_OUTSTAND_VAL_MASK 0x1F + +/* ARC_FARM_KDMA_WR_COMP_AWUSER */ +#define ARC_FARM_KDMA_WR_COMP_AWUSER_VAL_SHIFT 0 +#define ARC_FARM_KDMA_WR_COMP_AWUSER_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_ERR_CFG */ +#define ARC_FARM_KDMA_ERR_CFG_ERR_MSG_EN_SHIFT 0 +#define ARC_FARM_KDMA_ERR_CFG_ERR_MSG_EN_MASK 0x1 +#define ARC_FARM_KDMA_ERR_CFG_STOP_ON_ERR_SHIFT 1 +#define ARC_FARM_KDMA_ERR_CFG_STOP_ON_ERR_MASK 0x2 + +/* ARC_FARM_KDMA_ERR_CAUSE */ +#define ARC_FARM_KDMA_ERR_CAUSE_HBW_RD_ERR_SHIFT 0 +#define ARC_FARM_KDMA_ERR_CAUSE_HBW_RD_ERR_MASK 0x1 +#define ARC_FARM_KDMA_ERR_CAUSE_HBW_WR_ERR_SHIFT 1 +#define ARC_FARM_KDMA_ERR_CAUSE_HBW_WR_ERR_MASK 0x2 +#define ARC_FARM_KDMA_ERR_CAUSE_LBW_MSG_WR_ERR_SHIFT 2 +#define ARC_FARM_KDMA_ERR_CAUSE_LBW_MSG_WR_ERR_MASK 0x4 +#define ARC_FARM_KDMA_ERR_CAUSE_DESC_OVF_SHIFT 3 +#define ARC_FARM_KDMA_ERR_CAUSE_DESC_OVF_MASK 0x8 +#define ARC_FARM_KDMA_ERR_CAUSE_LBW_RD_ERR_SHIFT 4 +#define ARC_FARM_KDMA_ERR_CAUSE_LBW_RD_ERR_MASK 0x10 +#define ARC_FARM_KDMA_ERR_CAUSE_LBW_WR_ERR_SHIFT 5 +#define ARC_FARM_KDMA_ERR_CAUSE_LBW_WR_ERR_MASK 0x20 +#define ARC_FARM_KDMA_ERR_CAUSE_TE_DESC_FIFO_OVFL_SHIFT 6 +#define ARC_FARM_KDMA_ERR_CAUSE_TE_DESC_FIFO_OVFL_MASK 0x40 +#define ARC_FARM_KDMA_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_SHIFT 7 +#define ARC_FARM_KDMA_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_MASK 0x80 + +/* ARC_FARM_KDMA_ERRMSG_ADDR_LO */ +#define ARC_FARM_KDMA_ERRMSG_ADDR_LO_VAL_SHIFT 0 +#define ARC_FARM_KDMA_ERRMSG_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_ERRMSG_ADDR_HI */ +#define ARC_FARM_KDMA_ERRMSG_ADDR_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_ERRMSG_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_ERRMSG_WDATA */ +#define ARC_FARM_KDMA_ERRMSG_WDATA_VAL_SHIFT 0 +#define ARC_FARM_KDMA_ERRMSG_WDATA_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_STS0 */ +#define ARC_FARM_KDMA_STS0_RD_REQ_CNT_SHIFT 0 +#define ARC_FARM_KDMA_STS0_RD_REQ_CNT_MASK 0x7FFF +#define ARC_FARM_KDMA_STS0_WR_REQ_CNT_SHIFT 16 +#define ARC_FARM_KDMA_STS0_WR_REQ_CNT_MASK 0x7FFF0000 +#define ARC_FARM_KDMA_STS0_BUSY_SHIFT 31 +#define ARC_FARM_KDMA_STS0_BUSY_MASK 0x80000000 + +/* ARC_FARM_KDMA_STS1 */ +#define ARC_FARM_KDMA_STS1_IS_HALT_SHIFT 0 +#define ARC_FARM_KDMA_STS1_IS_HALT_MASK 0x1 + +/* ARC_FARM_KDMA_STS_RD_CTX_SEL */ +#define ARC_FARM_KDMA_STS_RD_CTX_SEL_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_RD_CTX_SEL_VAL_MASK 0x7 +#define ARC_FARM_KDMA_STS_RD_CTX_SEL_STRIDE_SHIFT 8 +#define ARC_FARM_KDMA_STS_RD_CTX_SEL_STRIDE_MASK 0x100 + +/* ARC_FARM_KDMA_STS_RD_CTX_SIZE */ +#define ARC_FARM_KDMA_STS_RD_CTX_SIZE_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_RD_CTX_SIZE_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_STS_RD_CTX_BASE_LO */ +#define ARC_FARM_KDMA_STS_RD_CTX_BASE_LO_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_RD_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_STS_RD_CTX_BASE_HI */ +#define ARC_FARM_KDMA_STS_RD_CTX_BASE_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_RD_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_STS_RD_CTX_ID */ +#define ARC_FARM_KDMA_STS_RD_CTX_ID_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_RD_CTX_ID_VAL_MASK 0xFFFF + +/* ARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_LO */ +#define ARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_LO_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_HI */ +#define ARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR */ +#define ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF +#define ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR_RDY_SHIFT 30 +#define ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR_RDY_MASK 0x40000000 +#define ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR_VLD_SHIFT 31 +#define ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR_VLD_MASK 0x80000000 + +/* ARC_FARM_KDMA_STS_WR_CTX_SEL */ +#define ARC_FARM_KDMA_STS_WR_CTX_SEL_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_WR_CTX_SEL_VAL_MASK 0x7 +#define ARC_FARM_KDMA_STS_WR_CTX_SEL_STRIDE_SHIFT 8 +#define ARC_FARM_KDMA_STS_WR_CTX_SEL_STRIDE_MASK 0x100 + +/* ARC_FARM_KDMA_STS_WR_CTX_SIZE */ +#define ARC_FARM_KDMA_STS_WR_CTX_SIZE_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_WR_CTX_SIZE_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_STS_WR_CTX_BASE_LO */ +#define ARC_FARM_KDMA_STS_WR_CTX_BASE_LO_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_WR_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_STS_WR_CTX_BASE_HI */ +#define ARC_FARM_KDMA_STS_WR_CTX_BASE_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_WR_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_STS_WR_CTX_ID */ +#define ARC_FARM_KDMA_STS_WR_CTX_ID_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_WR_CTX_ID_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO */ +#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO_VAL_MASK 0x3FFFF +#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO_RDY_SHIFT 30 +#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO_RDY_MASK 0x40000000 +#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO_VLD_SHIFT 31 +#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO_VLD_MASK 0x80000000 + +/* ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI */ +#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI_VAL_MASK 0x3FFFF +#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI_RDY_SHIFT 30 +#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI_RDY_MASK 0x40000000 +#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI_VLD_SHIFT 31 +#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI_VLD_MASK 0x80000000 + +/* ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR */ +#define ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR_VAL_SHIFT 0 +#define ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF +#define ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR_RDY_SHIFT 30 +#define ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR_RDY_MASK 0x40000000 +#define ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR_VLD_SHIFT 31 +#define ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR_VLD_MASK 0x80000000 + +/* ARC_FARM_KDMA_PWRLP_CFG */ +#define ARC_FARM_KDMA_PWRLP_CFG_GLBL_EN_SHIFT 0 +#define ARC_FARM_KDMA_PWRLP_CFG_GLBL_EN_MASK 0x1 +#define ARC_FARM_KDMA_PWRLP_CFG_CLR_SHIFT 4 +#define ARC_FARM_KDMA_PWRLP_CFG_CLR_MASK 0x10 + +/* ARC_FARM_KDMA_PWRLP_STS */ +#define ARC_FARM_KDMA_PWRLP_STS_RLVL_SHIFT 0 +#define ARC_FARM_KDMA_PWRLP_STS_RLVL_MASK 0x7F +#define ARC_FARM_KDMA_PWRLP_STS_WLVL_SHIFT 8 +#define ARC_FARM_KDMA_PWRLP_STS_WLVL_MASK 0x7F00 +#define ARC_FARM_KDMA_PWRLP_STS_RCNT_SHIFT 16 +#define ARC_FARM_KDMA_PWRLP_STS_RCNT_MASK 0x7F0000 +#define ARC_FARM_KDMA_PWRLP_STS_WCNT_SHIFT 23 +#define ARC_FARM_KDMA_PWRLP_STS_WCNT_MASK 0x3F800000 +#define ARC_FARM_KDMA_PWRLP_STS_RFULL_SHIFT 30 +#define ARC_FARM_KDMA_PWRLP_STS_RFULL_MASK 0x40000000 +#define ARC_FARM_KDMA_PWRLP_STS_WFULL_SHIFT 31 +#define ARC_FARM_KDMA_PWRLP_STS_WFULL_MASK 0x80000000 + +/* ARC_FARM_KDMA_DBG_DESC_CNT */ +#define ARC_FARM_KDMA_DBG_DESC_CNT_VAL_SHIFT 0 +#define ARC_FARM_KDMA_DBG_DESC_CNT_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_DBG_STS */ +#define ARC_FARM_KDMA_DBG_STS_RD_CTX_FULL_SHIFT 0 +#define ARC_FARM_KDMA_DBG_STS_RD_CTX_FULL_MASK 0x1 +#define ARC_FARM_KDMA_DBG_STS_WR_CTX_FULL_SHIFT 1 +#define ARC_FARM_KDMA_DBG_STS_WR_CTX_FULL_MASK 0x2 +#define ARC_FARM_KDMA_DBG_STS_WR_COMP_FULL_SHIFT 2 +#define ARC_FARM_KDMA_DBG_STS_WR_COMP_FULL_MASK 0x4 +#define ARC_FARM_KDMA_DBG_STS_RD_CTX_EMPTY_SHIFT 3 +#define ARC_FARM_KDMA_DBG_STS_RD_CTX_EMPTY_MASK 0x8 +#define ARC_FARM_KDMA_DBG_STS_WR_CTX_EMPTY_SHIFT 4 +#define ARC_FARM_KDMA_DBG_STS_WR_CTX_EMPTY_MASK 0x10 +#define ARC_FARM_KDMA_DBG_STS_WR_COMP_EMPTY_SHIFT 5 +#define ARC_FARM_KDMA_DBG_STS_WR_COMP_EMPTY_MASK 0x20 +#define ARC_FARM_KDMA_DBG_STS_TE_EMPTY_SHIFT 6 +#define ARC_FARM_KDMA_DBG_STS_TE_EMPTY_MASK 0x40 +#define ARC_FARM_KDMA_DBG_STS_TE_BUSY_SHIFT 7 +#define ARC_FARM_KDMA_DBG_STS_TE_BUSY_MASK 0x80 +#define ARC_FARM_KDMA_DBG_STS_GSKT_EMPTY_SHIFT 8 +#define ARC_FARM_KDMA_DBG_STS_GSKT_EMPTY_MASK 0x100 +#define ARC_FARM_KDMA_DBG_STS_GSKT_FULL_SHIFT 9 +#define ARC_FARM_KDMA_DBG_STS_GSKT_FULL_MASK 0x200 +#define ARC_FARM_KDMA_DBG_STS_RD_AGU_CS_SHIFT 10 +#define ARC_FARM_KDMA_DBG_STS_RD_AGU_CS_MASK 0x400 +#define ARC_FARM_KDMA_DBG_STS_WR_AGU_CS_SHIFT 11 +#define ARC_FARM_KDMA_DBG_STS_WR_AGU_CS_MASK 0x800 + +/* ARC_FARM_KDMA_DBG_BUF_STS */ +#define ARC_FARM_KDMA_DBG_BUF_STS_HBW_FULLNESS_SHIFT 0 +#define ARC_FARM_KDMA_DBG_BUF_STS_HBW_FULLNESS_MASK 0xFFF +#define ARC_FARM_KDMA_DBG_BUF_STS_LBW_FULLNESS_SHIFT 16 +#define ARC_FARM_KDMA_DBG_BUF_STS_LBW_FULLNESS_MASK 0xFFF0000 + +/* ARC_FARM_KDMA_DBG_RD_DESC_ID */ +#define ARC_FARM_KDMA_DBG_RD_DESC_ID_VAL_SHIFT 0 +#define ARC_FARM_KDMA_DBG_RD_DESC_ID_VAL_MASK 0xFFFF + +/* ARC_FARM_KDMA_DBG_WR_DESC_ID */ +#define ARC_FARM_KDMA_DBG_WR_DESC_ID_VAL_SHIFT 0 +#define ARC_FARM_KDMA_DBG_WR_DESC_ID_VAL_MASK 0xFFFF + +/* ARC_FARM_KDMA_APB_DMA_LBW_BASE */ +#define ARC_FARM_KDMA_APB_DMA_LBW_BASE_VAL_SHIFT 0 +#define ARC_FARM_KDMA_APB_DMA_LBW_BASE_VAL_MASK 0xFFFF + +/* ARC_FARM_KDMA_APB_MSTR_IF_LBW_BASE */ +#define ARC_FARM_KDMA_APB_MSTR_IF_LBW_BASE_VAL_SHIFT 0 +#define ARC_FARM_KDMA_APB_MSTR_IF_LBW_BASE_VAL_MASK 0xFFFF + +/* ARC_FARM_KDMA_E2E_CRED_ASYNC_CFG */ +#define ARC_FARM_KDMA_E2E_CRED_ASYNC_CFG_Y_X_FORCE_SHIFT 0 +#define ARC_FARM_KDMA_E2E_CRED_ASYNC_CFG_Y_X_FORCE_MASK 0x1FF +#define ARC_FARM_KDMA_E2E_CRED_ASYNC_CFG_FORCE_EN_SHIFT 9 +#define ARC_FARM_KDMA_E2E_CRED_ASYNC_CFG_FORCE_EN_MASK 0x200 + +/* ARC_FARM_KDMA_DBG_APB_ENABLER */ +#define ARC_FARM_KDMA_DBG_APB_ENABLER_DIS_SHIFT 0 +#define ARC_FARM_KDMA_DBG_APB_ENABLER_DIS_MASK 0x1 + +/* ARC_FARM_KDMA_L2H_CMPR_LO */ +#define ARC_FARM_KDMA_L2H_CMPR_LO_VAL_SHIFT 20 +#define ARC_FARM_KDMA_L2H_CMPR_LO_VAL_MASK 0xFFF00000 + +/* ARC_FARM_KDMA_L2H_CMPR_HI */ +#define ARC_FARM_KDMA_L2H_CMPR_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_L2H_CMPR_HI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_L2H_MASK_LO */ +#define ARC_FARM_KDMA_L2H_MASK_LO_VAL_SHIFT 20 +#define ARC_FARM_KDMA_L2H_MASK_LO_VAL_MASK 0xFFF00000 + +/* ARC_FARM_KDMA_L2H_MASK_HI */ +#define ARC_FARM_KDMA_L2H_MASK_HI_VAL_SHIFT 0 +#define ARC_FARM_KDMA_L2H_MASK_HI_VAL_MASK 0xFFFFFFFF + +/* ARC_FARM_KDMA_IDLE_IND_MASK */ +#define ARC_FARM_KDMA_IDLE_IND_MASK_DESC_SHIFT 0 +#define ARC_FARM_KDMA_IDLE_IND_MASK_DESC_MASK 0x1 +#define ARC_FARM_KDMA_IDLE_IND_MASK_COMP_SHIFT 1 +#define ARC_FARM_KDMA_IDLE_IND_MASK_COMP_MASK 0x2 +#define ARC_FARM_KDMA_IDLE_IND_MASK_INSTAGE_SHIFT 2 +#define ARC_FARM_KDMA_IDLE_IND_MASK_INSTAGE_MASK 0x4 +#define ARC_FARM_KDMA_IDLE_IND_MASK_CORE_SHIFT 3 +#define ARC_FARM_KDMA_IDLE_IND_MASK_CORE_MASK 0x8 +#define ARC_FARM_KDMA_IDLE_IND_MASK_DESC_CNT_STS_SHIFT 8 +#define ARC_FARM_KDMA_IDLE_IND_MASK_DESC_CNT_STS_MASK 0x1F00 +#define ARC_FARM_KDMA_IDLE_IND_MASK_COMP_CNT_STS_SHIFT 16 +#define ARC_FARM_KDMA_IDLE_IND_MASK_COMP_CNT_STS_MASK 0x1F0000 +#define ARC_FARM_KDMA_IDLE_IND_MASK_INSTAGE_EMPTY_SHIFT 24 +#define ARC_FARM_KDMA_IDLE_IND_MASK_INSTAGE_EMPTY_MASK 0x1000000 +#define ARC_FARM_KDMA_IDLE_IND_MASK_CORE_IDLE_STS_SHIFT 25 +#define ARC_FARM_KDMA_IDLE_IND_MASK_CORE_IDLE_STS_MASK 0x2000000 + +/* ARC_FARM_KDMA_APB_ENABLER */ +#define ARC_FARM_KDMA_APB_ENABLER_DIS_SHIFT 0 +#define ARC_FARM_KDMA_APB_ENABLER_DIS_MASK 0x1 + +#endif /* ASIC_REG_ARC_FARM_KDMA_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_regs.h new file mode 100644 index 000000000000..e312cf810c0e --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_regs.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ARC_FARM_KDMA_REGS_H_ +#define ASIC_REG_ARC_FARM_KDMA_REGS_H_ + +/* + ***************************************** + * ARC_FARM_KDMA + * (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmARC_FARM_KDMA_CFG_0 0x4E8B000 + +#define mmARC_FARM_KDMA_CFG_1 0x4E8B004 + +#define mmARC_FARM_KDMA_PROT 0x4E8B008 + +#define mmARC_FARM_KDMA_CKG 0x4E8B00C + +#define mmARC_FARM_KDMA_RD_GLBL 0x4E8B07C + +#define mmARC_FARM_KDMA_RD_HBW_MAX_OUTSTAND 0x4E8B080 + +#define mmARC_FARM_KDMA_RD_HBW_MAX_SIZE 0x4E8B084 + +#define mmARC_FARM_KDMA_RD_HBW_ARCACHE 0x4E8B088 + +#define mmARC_FARM_KDMA_RD_HBW_INFLIGHTS 0x4E8B090 + +#define mmARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG 0x4E8B094 + +#define mmARC_FARM_KDMA_RD_LBW_MAX_OUTSTAND 0x4E8B0C0 + +#define mmARC_FARM_KDMA_RD_LBW_MAX_SIZE 0x4E8B0C4 + +#define mmARC_FARM_KDMA_RD_LBW_ARCACHE 0x4E8B0C8 + +#define mmARC_FARM_KDMA_RD_LBW_INFLIGHTS 0x4E8B0D0 + +#define mmARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG 0x4E8B0D4 + +#define mmARC_FARM_KDMA_WR_HBW_MAX_OUTSTAND 0x4E8B100 + +#define mmARC_FARM_KDMA_WR_HBW_MAX_AWID 0x4E8B104 + +#define mmARC_FARM_KDMA_WR_HBW_AWCACHE 0x4E8B108 + +#define mmARC_FARM_KDMA_WR_HBW_INFLIGHTS 0x4E8B10C + +#define mmARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG 0x4E8B110 + +#define mmARC_FARM_KDMA_WR_LBW_MAX_OUTSTAND 0x4E8B140 + +#define mmARC_FARM_KDMA_WR_LBW_MAX_AWID 0x4E8B144 + +#define mmARC_FARM_KDMA_WR_LBW_AWCACHE 0x4E8B148 + +#define mmARC_FARM_KDMA_WR_LBW_INFLIGHTS 0x4E8B14C + +#define mmARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG 0x4E8B150 + +#define mmARC_FARM_KDMA_WR_COMP_MAX_OUTSTAND 0x4E8B180 + +#define mmARC_FARM_KDMA_WR_COMP_AWUSER 0x4E8B184 + +#define mmARC_FARM_KDMA_ERR_CFG 0x4E8B300 + +#define mmARC_FARM_KDMA_ERR_CAUSE 0x4E8B304 + +#define mmARC_FARM_KDMA_ERRMSG_ADDR_LO 0x4E8B308 + +#define mmARC_FARM_KDMA_ERRMSG_ADDR_HI 0x4E8B30C + +#define mmARC_FARM_KDMA_ERRMSG_WDATA 0x4E8B310 + +#define mmARC_FARM_KDMA_STS0 0x4E8B380 + +#define mmARC_FARM_KDMA_STS1 0x4E8B384 + +#define mmARC_FARM_KDMA_STS_RD_CTX_SEL 0x4E8B400 + +#define mmARC_FARM_KDMA_STS_RD_CTX_SIZE 0x4E8B404 + +#define mmARC_FARM_KDMA_STS_RD_CTX_BASE_LO 0x4E8B408 + +#define mmARC_FARM_KDMA_STS_RD_CTX_BASE_HI 0x4E8B40C + +#define mmARC_FARM_KDMA_STS_RD_CTX_ID 0x4E8B410 + +#define mmARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_LO 0x4E8B414 + +#define mmARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_HI 0x4E8B418 + +#define mmARC_FARM_KDMA_STS_RD_LB_AXI_ADDR 0x4E8B41C + +#define mmARC_FARM_KDMA_STS_WR_CTX_SEL 0x4E8B420 + +#define mmARC_FARM_KDMA_STS_WR_CTX_SIZE 0x4E8B424 + +#define mmARC_FARM_KDMA_STS_WR_CTX_BASE_LO 0x4E8B428 + +#define mmARC_FARM_KDMA_STS_WR_CTX_BASE_HI 0x4E8B42C + +#define mmARC_FARM_KDMA_STS_WR_CTX_ID 0x4E8B430 + +#define mmARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO 0x4E8B434 + +#define mmARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI 0x4E8B438 + +#define mmARC_FARM_KDMA_STS_WR_LB_AXI_ADDR 0x4E8B43C + +#define mmARC_FARM_KDMA_PWRLP_CFG 0x4E8B700 + +#define mmARC_FARM_KDMA_PWRLP_STS 0x4E8B704 + +#define mmARC_FARM_KDMA_DBG_DESC_CNT 0x4E8B710 + +#define mmARC_FARM_KDMA_DBG_STS 0x4E8B714 + +#define mmARC_FARM_KDMA_DBG_BUF_STS 0x4E8B718 + +#define mmARC_FARM_KDMA_DBG_RD_DESC_ID 0x4E8B720 + +#define mmARC_FARM_KDMA_DBG_WR_DESC_ID 0x4E8B724 + +#define mmARC_FARM_KDMA_APB_DMA_LBW_BASE 0x4E8B728 + +#define mmARC_FARM_KDMA_APB_MSTR_IF_LBW_BASE 0x4E8B72C + +#define mmARC_FARM_KDMA_E2E_CRED_ASYNC_CFG 0x4E8B730 + +#define mmARC_FARM_KDMA_DBG_APB_ENABLER 0x4E8BE1C + +#define mmARC_FARM_KDMA_L2H_CMPR_LO 0x4E8BE20 + +#define mmARC_FARM_KDMA_L2H_CMPR_HI 0x4E8BE24 + +#define mmARC_FARM_KDMA_L2H_MASK_LO 0x4E8BE28 + +#define mmARC_FARM_KDMA_L2H_MASK_HI 0x4E8BE2C + +#define mmARC_FARM_KDMA_IDLE_IND_MASK 0x4E8BE30 + +#define mmARC_FARM_KDMA_APB_ENABLER 0x4E8BE34 + +#endif /* ASIC_REG_ARC_FARM_KDMA_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/cpu_if_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/cpu_if_regs.h new file mode 100644 index 000000000000..9b3eceec9d5d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/cpu_if_regs.h @@ -0,0 +1,777 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_CPU_IF_REGS_H_ +#define ASIC_REG_CPU_IF_REGS_H_ + +/* + ***************************************** + * CPU_IF + * (Prototype: CPU_IF) + ***************************************** + */ + +#define mmCPU_IF_ARUSER_OVR 0x4CC1104 + +#define mmCPU_IF_ARUSER_OVR_EN 0x4CC1108 + +#define mmCPU_IF_AWUSER_OVR 0x4CC110C + +#define mmCPU_IF_AWUSER_OVR_EN 0x4CC1110 + +#define mmCPU_IF_ARUSER_MSB_OVR 0x4CC1114 + +#define mmCPU_IF_AWUSER_MSB_OVR 0x4CC1120 + +#define mmCPU_IF_AXCACHE_OVR 0x4CC1128 + +#define mmCPU_IF_LOCK_OVR 0x4CC112C + +#define mmCPU_IF_PROT_OVR 0x4CC1130 + +#define mmCPU_IF_MAX_OUTSTANDING 0x4CC1134 + +#define mmCPU_IF_EARLY_BRESP_EN 0x4CC1138 + +#define mmCPU_IF_FORCE_RSP_OK 0x4CC113C + +#define mmCPU_IF_CPU_SEI_INTR_STS 0x4CC1140 + +#define mmCPU_IF_CPU_SEI_INTR_CLR 0x4CC1144 + +#define mmCPU_IF_CPU_SEI_INTR_MASK 0x4CC1148 + +#define mmCPU_IF_AXI_SPLIT_NO_WR_INFLIGHT 0x4CC114C + +#define mmCPU_IF_AXI_SPLIT_SEI_INTR_ID 0x4CC1150 + +#define mmCPU_IF_TOTAL_WR_CNT 0x4CC1154 + +#define mmCPU_IF_INFLIGHT_WR_CNT 0x4CC1158 + +#define mmCPU_IF_TOTAL_RD_CNT 0x4CC115C + +#define mmCPU_IF_INFLIGHT_RD_CNT 0x4CC1160 + +#define mmCPU_IF_SRAM_MSB_ADDR 0x4CC1164 + +#define mmCPU_IF_CFG_MSB_ADDR 0x4CC1168 + +#define mmCPU_IF_HBM_MSB_ADDR 0x4CC116C + +#define mmCPU_IF_PCIE_MSB_ADDR 0x4CC1170 + +#define mmCPU_IF_KMD_HW_DIRTY_STATUS 0x4CC1174 + +#define mmCPU_IF_MSTR_IF_E2E_FORCE_BP 0x4CC1188 + +#define mmCPU_IF_MSTR_IF_E2E_GRCFL_CLR 0x4CC118C + +#define mmCPU_IF_LBW_TERMINATE_AWADDR_ERR 0x4CC11A0 + +#define mmCPU_IF_LBW_TERMINATE_ARADDR_ERR 0x4CC11A4 + +#define mmCPU_IF_CFG_LBW_TERMINATE_BRESP 0x4CC11A8 + +#define mmCPU_IF_CFG_LBW_TERMINATE_RRESP 0x4CC11AC + +#define mmCPU_IF_PF_PQ_PI 0x4CC1200 + +#define mmCPU_IF_PQ_BASE_ADDR_LOW 0x4CC1204 + +#define mmCPU_IF_PQ_BASE_ADDR_HIGH 0x4CC1208 + +#define mmCPU_IF_PQ_LENGTH 0x4CC120C + +#define mmCPU_IF_CQ_BASE_ADDR_LOW 0x4CC1210 + +#define mmCPU_IF_CQ_BASE_ADDR_HIGH 0x4CC1214 + +#define mmCPU_IF_CQ_LENGTH 0x4CC1218 + +#define mmCPU_IF_EQ_BASE_ADDR_LOW 0x4CC1220 + +#define mmCPU_IF_EQ_BASE_ADDR_HIGH 0x4CC1224 + +#define mmCPU_IF_EQ_LENGTH 0x4CC1228 + +#define mmCPU_IF_EQ_RD_OFFS 0x4CC122C + +#define mmCPU_IF_QUEUE_INIT 0x4CC1230 + +#define mmCPU_IF_TPC_SERR_INTR_STS 0x4CC1300 + +#define mmCPU_IF_TPC_SERR_INTR_CLR 0x4CC1304 + +#define mmCPU_IF_TPC_SERR_INTR_MASK 0x4CC1308 + +#define mmCPU_IF_TPC_DERR_INTR_STS 0x4CC1310 + +#define mmCPU_IF_TPC_DERR_INTR_CLR 0x4CC1314 + +#define mmCPU_IF_TPC_DERR_INTR_MASK 0x4CC1318 + +#define mmCPU_IF_MME_SERR_INTR_STS_0 0x4CC1320 + +#define mmCPU_IF_MME_SERR_INTR_STS_1 0x4CC1324 + +#define mmCPU_IF_MME_SERR_INTR_STS_2 0x4CC1328 + +#define mmCPU_IF_MME_SERR_INTR_STS_3 0x4CC132C + +#define mmCPU_IF_MME_SERR_INTR_CLR_0 0x4CC1330 + +#define mmCPU_IF_MME_SERR_INTR_CLR_1 0x4CC1334 + +#define mmCPU_IF_MME_SERR_INTR_CLR_2 0x4CC1338 + +#define mmCPU_IF_MME_SERR_INTR_CLR_3 0x4CC133C + +#define mmCPU_IF_MME_SERR_INTR_MASK_0 0x4CC1340 + +#define mmCPU_IF_MME_SERR_INTR_MASK_1 0x4CC1344 + +#define mmCPU_IF_MME_SERR_INTR_MASK_2 0x4CC1348 + +#define mmCPU_IF_MME_SERR_INTR_MASK_3 0x4CC134C + +#define mmCPU_IF_MME_DERR_INTR_STS_0 0x4CC1350 + +#define mmCPU_IF_MME_DERR_INTR_STS_1 0x4CC1354 + +#define mmCPU_IF_MME_DERR_INTR_STS_2 0x4CC1358 + +#define mmCPU_IF_MME_DERR_INTR_STS_3 0x4CC135C + +#define mmCPU_IF_MME_DERR_INTR_CLR_0 0x4CC1360 + +#define mmCPU_IF_MME_DERR_INTR_CLR_1 0x4CC1364 + +#define mmCPU_IF_MME_DERR_INTR_CLR_2 0x4CC1368 + +#define mmCPU_IF_MME_DERR_INTR_CLR_3 0x4CC136C + +#define mmCPU_IF_MME_DERR_INTR_MASK_0 0x4CC1370 + +#define mmCPU_IF_MME_DERR_INTR_MASK_1 0x4CC1374 + +#define mmCPU_IF_MME_DERR_INTR_MASK_2 0x4CC1378 + +#define mmCPU_IF_MME_DERR_INTR_MASK_3 0x4CC137C + +#define mmCPU_IF_HDMA_SERR_INTR_STS 0x4CC1380 + +#define mmCPU_IF_HDMA_SERR_INTR_CLR 0x4CC1384 + +#define mmCPU_IF_HDMA_SERR_INTR_MASK 0x4CC1388 + +#define mmCPU_IF_HDMA_DERR_INTR_STS 0x4CC1390 + +#define mmCPU_IF_HDMA_DERR_INTR_CLR 0x4CC1394 + +#define mmCPU_IF_HDMA_DERR_INTR_MASK 0x4CC1398 + +#define mmCPU_IF_PDMA_SERR_INTR_STS 0x4CC13A0 + +#define mmCPU_IF_PDMA_SERR_INTR_CLR 0x4CC13A4 + +#define mmCPU_IF_PDMA_SERR_INTR_MASK 0x4CC13A8 + +#define mmCPU_IF_PDMA_DERR_INTR_STS 0x4CC13B0 + +#define mmCPU_IF_PDMA_DERR_INTR_CLR 0x4CC13B4 + +#define mmCPU_IF_PDMA_DERR_INTR_MASK 0x4CC13B8 + +#define mmCPU_IF_SRAM_SERR_INTR_STS 0x4CC13C0 + +#define mmCPU_IF_SRAM_SERR_INTR_CLR 0x4CC13C4 + +#define mmCPU_IF_SRAM_SERR_INTR_MASK 0x4CC13C8 + +#define mmCPU_IF_SRAM_DERR_INTR_STS 0x4CC13D0 + +#define mmCPU_IF_SRAM_DERR_INTR_CLR 0x4CC13D4 + +#define mmCPU_IF_SRAM_DERR_INTR_MASK 0x4CC13D8 + +#define mmCPU_IF_HBM_SERR_INTR_STS 0x4CC13E0 + +#define mmCPU_IF_HBM_SERR_INTR_CLR 0x4CC13E4 + +#define mmCPU_IF_HBM_SERR_INTR_MASK 0x4CC13E8 + +#define mmCPU_IF_HBM_DERR_INTR_STS 0x4CC13F0 + +#define mmCPU_IF_HBM_DERR_INTR_CLR 0x4CC13F4 + +#define mmCPU_IF_HBM_DERR_INTR_MASK 0x4CC13F8 + +#define mmCPU_IF_HMMU_SERR_INTR_STS 0x4CC1400 + +#define mmCPU_IF_HMMU_SERR_INTR_CLR 0x4CC1404 + +#define mmCPU_IF_HMMU_SERR_INTR_MASK 0x4CC1408 + +#define mmCPU_IF_HMMU_DERR_INTR_STS 0x4CC1410 + +#define mmCPU_IF_HMMU_DERR_INTR_CLR 0x4CC1414 + +#define mmCPU_IF_HMMU_DERR_INTR_MASK 0x4CC1418 + +#define mmCPU_IF_DEC_SERR_INTR_STS 0x4CC1420 + +#define mmCPU_IF_DEC_SERR_INTR_CLR 0x4CC1424 + +#define mmCPU_IF_DEC_SERR_INTR_MASK 0x4CC1428 + +#define mmCPU_IF_DEC_DERR_INTR_STS 0x4CC1430 + +#define mmCPU_IF_DEC_DERR_INTR_CLR 0x4CC1434 + +#define mmCPU_IF_DEC_DERR_INTR_MASK 0x4CC1438 + +#define mmCPU_IF_NIC_SERR_INTR_STS 0x4CC1440 + +#define mmCPU_IF_NIC_SERR_INTR_CLR 0x4CC1444 + +#define mmCPU_IF_NIC_SERR_INTR_MASK 0x4CC1448 + +#define mmCPU_IF_NIC_DERR_INTR_STS 0x4CC1450 + +#define mmCPU_IF_NIC_DERR_INTR_CLR 0x4CC1454 + +#define mmCPU_IF_NIC_DERR_INTR_MASK 0x4CC1458 + +#define mmCPU_IF_SYNC_MNGR_SERR_INTR_STS 0x4CC1460 + +#define mmCPU_IF_SYNC_MNGR_SERR_INTR_CLR 0x4CC1464 + +#define mmCPU_IF_SYNC_MNGR_SERR_INTR_MASK 0x4CC1468 + +#define mmCPU_IF_SYNC_MNGR_DERR_INTR_STS 0x4CC1470 + +#define mmCPU_IF_SYNC_MNGR_DERR_INTR_CLR 0x4CC1474 + +#define mmCPU_IF_SYNC_MNGR_DERR_INTR_MASK 0x4CC1478 + +#define mmCPU_IF_HIF_SERR_INTR_STS 0x4CC1480 + +#define mmCPU_IF_HIF_SERR_INTR_CLR 0x4CC1484 + +#define mmCPU_IF_HIF_SERR_INTR_MASK 0x4CC1488 + +#define mmCPU_IF_HIF_DERR_INTR_STS 0x4CC1490 + +#define mmCPU_IF_HIF_DERR_INTR_CLR 0x4CC1494 + +#define mmCPU_IF_HIF_DERR_INTR_MASK 0x4CC1498 + +#define mmCPU_IF_XBAR_SERR_INTR_STS 0x4CC14A0 + +#define mmCPU_IF_XBAR_SERR_INTR_CLR 0x4CC14A4 + +#define mmCPU_IF_XBAR_SERR_INTR_MASK 0x4CC14A8 + +#define mmCPU_IF_XBAR_DERR_INTR_STS 0x4CC14B0 + +#define mmCPU_IF_XBAR_DERR_INTR_CLR 0x4CC14B4 + +#define mmCPU_IF_XBAR_DERR_INTR_MASK 0x4CC14B8 + +#define mmCPU_IF_TPC_SEI_INTR_STS 0x4CC14C0 + +#define mmCPU_IF_TPC_SEI_INTR_CLR 0x4CC14C4 + +#define mmCPU_IF_TPC_SEI_INTR_MASK 0x4CC14C8 + +#define mmCPU_IF_MME_SEI_INTR_STS_0 0x4CC14D0 + +#define mmCPU_IF_MME_SEI_INTR_STS_1 0x4CC14D4 + +#define mmCPU_IF_MME_SEI_INTR_STS_2 0x4CC14D8 + +#define mmCPU_IF_MME_SEI_INTR_STS_3 0x4CC14DC + +#define mmCPU_IF_MME_SEI_INTR_CLR_0 0x4CC14E0 + +#define mmCPU_IF_MME_SEI_INTR_CLR_1 0x4CC14E4 + +#define mmCPU_IF_MME_SEI_INTR_CLR_2 0x4CC14E8 + +#define mmCPU_IF_MME_SEI_INTR_CLR_3 0x4CC14EC + +#define mmCPU_IF_MME_SEI_INTR_MASK_0 0x4CC14F0 + +#define mmCPU_IF_MME_SEI_INTR_MASK_1 0x4CC14F4 + +#define mmCPU_IF_MME_SEI_INTR_MASK_2 0x4CC14F8 + +#define mmCPU_IF_MME_SEI_INTR_MASK_3 0x4CC14FC + +#define mmCPU_IF_PLL_LSB_SEI_INTR_STS 0x4CC1500 + +#define mmCPU_IF_PLL_LSB_SEI_INTR_CLR 0x4CC1504 + +#define mmCPU_IF_PLL_LSB_SEI_INTR_MASK 0x4CC1508 + +#define mmCPU_IF_PLL_MSB_SEI_INTR_STS 0x4CC1510 + +#define mmCPU_IF_PLL_MSB_SEI_INTR_CLR 0x4CC1514 + +#define mmCPU_IF_PLL_MSB_SEI_INTR_MASK 0x4CC1518 + +#define mmCPU_IF_HMMU_SEI_INTR_STS 0x4CC1520 + +#define mmCPU_IF_HMMU_SEI_INTR_CLR 0x4CC1524 + +#define mmCPU_IF_HMMU_SEI_INTR_MASK 0x4CC1528 + +#define mmCPU_IF_HDMA_SEI_INTR_STS 0x4CC1530 + +#define mmCPU_IF_HDMA_SEI_INTR_CLR 0x4CC1534 + +#define mmCPU_IF_HDMA_SEI_INTR_MASK 0x4CC1538 + +#define mmCPU_IF_PDMA_SEI_INTR_STS 0x4CC1540 + +#define mmCPU_IF_PDMA_SEI_INTR_CLR 0x4CC1544 + +#define mmCPU_IF_PDMA_SEI_INTR_MASK 0x4CC1548 + +#define mmCPU_IF_HBM_SEI_INTR_STS 0x4CC1550 + +#define mmCPU_IF_HBM_SEI_INTR_CLR 0x4CC1554 + +#define mmCPU_IF_HBM_SEI_INTR_MASK 0x4CC1558 + +#define mmCPU_IF_DEC_SEI_INTR_STS 0x4CC1560 + +#define mmCPU_IF_DEC_SEI_INTR_CLR 0x4CC1564 + +#define mmCPU_IF_DEC_SEI_INTR_MASK 0x4CC1568 + +#define mmCPU_IF_HIF_SEI_INTR_STS 0x4CC1570 + +#define mmCPU_IF_HIF_SEI_INTR_CLR 0x4CC1574 + +#define mmCPU_IF_HIF_SEI_INTR_MASK 0x4CC1578 + +#define mmCPU_IF_SYNC_MNGR_SEI_INTR_STS 0x4CC1580 + +#define mmCPU_IF_SYNC_MNGR_SEI_INTR_CLR 0x4CC1584 + +#define mmCPU_IF_SYNC_MNGR_SEI_INTR_MASK 0x4CC1588 + +#define mmCPU_IF_NIC_SEI_INTR_STS 0x4CC1590 + +#define mmCPU_IF_NIC_SEI_INTR_CLR 0x4CC1594 + +#define mmCPU_IF_NIC_SEI_INTR_MASK 0x4CC1598 + +#define mmCPU_IF_PCIE_SPI_INTR_STS 0x4CC1600 + +#define mmCPU_IF_PCIE_SPI_INTR_CLR 0x4CC1604 + +#define mmCPU_IF_PCIE_SPI_INTR_MASK 0x4CC1608 + +#define mmCPU_IF_MME_SPI_INTR_STS_0 0x4CC1610 + +#define mmCPU_IF_MME_SPI_INTR_STS_1 0x4CC1614 + +#define mmCPU_IF_MME_SPI_INTR_STS_2 0x4CC1618 + +#define mmCPU_IF_MME_SPI_INTR_STS_3 0x4CC161C + +#define mmCPU_IF_MME_SPI_INTR_CLR_0 0x4CC1620 + +#define mmCPU_IF_MME_SPI_INTR_CLR_1 0x4CC1624 + +#define mmCPU_IF_MME_SPI_INTR_CLR_2 0x4CC1628 + +#define mmCPU_IF_MME_SPI_INTR_CLR_3 0x4CC162C + +#define mmCPU_IF_MME_SPI_INTR_MASK_0 0x4CC1630 + +#define mmCPU_IF_MME_SPI_INTR_MASK_1 0x4CC1634 + +#define mmCPU_IF_MME_SPI_INTR_MASK_2 0x4CC1638 + +#define mmCPU_IF_MME_SPI_INTR_MASK_3 0x4CC163C + +#define mmCPU_IF_HMMU_SPI_INTR_STS_0 0x4CC1640 + +#define mmCPU_IF_HMMU_SPI_INTR_STS_1 0x4CC1644 + +#define mmCPU_IF_HMMU_SPI_INTR_STS_2 0x4CC1648 + +#define mmCPU_IF_HMMU_SPI_INTR_STS_3 0x4CC164C + +#define mmCPU_IF_HMMU_SPI_INTR_STS_4 0x4CC1650 + +#define mmCPU_IF_HMMU_SPI_INTR_STS_5 0x4CC1654 + +#define mmCPU_IF_HMMU_SPI_INTR_STS_6 0x4CC1658 + +#define mmCPU_IF_HMMU_SPI_INTR_STS_7 0x4CC165C + +#define mmCPU_IF_HMMU_SPI_INTR_STS_8 0x4CC1660 + +#define mmCPU_IF_HMMU_SPI_INTR_STS_9 0x4CC1664 + +#define mmCPU_IF_HMMU_SPI_INTR_STS_10 0x4CC1668 + +#define mmCPU_IF_HMMU_SPI_INTR_STS_11 0x4CC166C + +#define mmCPU_IF_HMMU_SPI_INTR_STS_12 0x4CC1670 + +#define mmCPU_IF_HMMU_SPI_INTR_STS_13 0x4CC1674 + +#define mmCPU_IF_HMMU_SPI_INTR_STS_14 0x4CC1678 + +#define mmCPU_IF_HMMU_SPI_INTR_STS_15 0x4CC167C + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_0 0x4CC1680 + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_1 0x4CC1684 + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_2 0x4CC1688 + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_3 0x4CC168C + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_4 0x4CC1690 + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_5 0x4CC1694 + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_6 0x4CC1698 + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_7 0x4CC169C + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_8 0x4CC16A0 + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_9 0x4CC16A4 + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_10 0x4CC16A8 + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_11 0x4CC16AC + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_12 0x4CC16B0 + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_13 0x4CC16B4 + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_14 0x4CC16B8 + +#define mmCPU_IF_HMMU_SPI_INTR_CLR_15 0x4CC16BC + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_0 0x4CC16C0 + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_1 0x4CC16C4 + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_2 0x4CC16C8 + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_3 0x4CC16CC + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_4 0x4CC16D0 + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_5 0x4CC16D4 + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_6 0x4CC16D8 + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_7 0x4CC16DC + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_8 0x4CC16E0 + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_9 0x4CC16E4 + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_10 0x4CC16E8 + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_11 0x4CC16EC + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_12 0x4CC16F0 + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_13 0x4CC16F4 + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_14 0x4CC16F8 + +#define mmCPU_IF_HMMU_SPI_INTR_MASK_15 0x4CC16FC + +#define mmCPU_IF_DEC_SPI_INTR_STS_0 0x4CC1700 + +#define mmCPU_IF_DEC_SPI_INTR_STS_1 0x4CC1704 + +#define mmCPU_IF_DEC_SPI_INTR_STS_2 0x4CC1708 + +#define mmCPU_IF_DEC_SPI_INTR_STS_3 0x4CC170C + +#define mmCPU_IF_DEC_SPI_INTR_STS_4 0x4CC1710 + +#define mmCPU_IF_DEC_SPI_INTR_STS_5 0x4CC1714 + +#define mmCPU_IF_DEC_SPI_INTR_STS_6 0x4CC1718 + +#define mmCPU_IF_DEC_SPI_INTR_STS_7 0x4CC171C + +#define mmCPU_IF_DEC_SPI_INTR_STS_8 0x4CC1720 + +#define mmCPU_IF_DEC_SPI_INTR_STS_9 0x4CC1724 + +#define mmCPU_IF_DEC_SPI_INTR_CLR_0 0x4CC1730 + +#define mmCPU_IF_DEC_SPI_INTR_CLR_1 0x4CC1734 + +#define mmCPU_IF_DEC_SPI_INTR_CLR_2 0x4CC1738 + +#define mmCPU_IF_DEC_SPI_INTR_CLR_3 0x4CC173C + +#define mmCPU_IF_DEC_SPI_INTR_CLR_4 0x4CC1740 + +#define mmCPU_IF_DEC_SPI_INTR_CLR_5 0x4CC1744 + +#define mmCPU_IF_DEC_SPI_INTR_CLR_6 0x4CC1748 + +#define mmCPU_IF_DEC_SPI_INTR_CLR_7 0x4CC174C + +#define mmCPU_IF_DEC_SPI_INTR_CLR_8 0x4CC1750 + +#define mmCPU_IF_DEC_SPI_INTR_CLR_9 0x4CC1754 + +#define mmCPU_IF_DEC_SPI_INTR_MASK_0 0x4CC1760 + +#define mmCPU_IF_DEC_SPI_INTR_MASK_1 0x4CC1764 + +#define mmCPU_IF_DEC_SPI_INTR_MASK_2 0x4CC1768 + +#define mmCPU_IF_DEC_SPI_INTR_MASK_3 0x4CC176C + +#define mmCPU_IF_DEC_SPI_INTR_MASK_4 0x4CC1770 + +#define mmCPU_IF_DEC_SPI_INTR_MASK_5 0x4CC1774 + +#define mmCPU_IF_DEC_SPI_INTR_MASK_6 0x4CC1778 + +#define mmCPU_IF_DEC_SPI_INTR_MASK_7 0x4CC177C + +#define mmCPU_IF_DEC_SPI_INTR_MASK_8 0x4CC1780 + +#define mmCPU_IF_DEC_SPI_INTR_MASK_9 0x4CC1784 + +#define mmCPU_IF_HIF_SPI_INTR_STS 0x4CC17A0 + +#define mmCPU_IF_HIF_SPI_INTR_CLR 0x4CC17A4 + +#define mmCPU_IF_HIF_SPI_INTR_MASK 0x4CC17A8 + +#define mmCPU_IF_NIC_SPI_INTR_STS_0 0x4CC17B0 + +#define mmCPU_IF_NIC_SPI_INTR_STS_1 0x4CC17B4 + +#define mmCPU_IF_NIC_SPI_INTR_STS_2 0x4CC17B8 + +#define mmCPU_IF_NIC_SPI_INTR_STS_3 0x4CC17BC + +#define mmCPU_IF_NIC_SPI_INTR_STS_4 0x4CC17C0 + +#define mmCPU_IF_NIC_SPI_INTR_STS_5 0x4CC17C4 + +#define mmCPU_IF_NIC_SPI_INTR_STS_6 0x4CC17C8 + +#define mmCPU_IF_NIC_SPI_INTR_STS_7 0x4CC17CC + +#define mmCPU_IF_NIC_SPI_INTR_STS_8 0x4CC17D0 + +#define mmCPU_IF_NIC_SPI_INTR_STS_9 0x4CC17D4 + +#define mmCPU_IF_NIC_SPI_INTR_STS_10 0x4CC17D8 + +#define mmCPU_IF_NIC_SPI_INTR_STS_11 0x4CC17DC + +#define mmCPU_IF_NIC_SPI_INTR_CLR_0 0x4CC17E0 + +#define mmCPU_IF_NIC_SPI_INTR_CLR_1 0x4CC17E4 + +#define mmCPU_IF_NIC_SPI_INTR_CLR_2 0x4CC17E8 + +#define mmCPU_IF_NIC_SPI_INTR_CLR_3 0x4CC17EC + +#define mmCPU_IF_NIC_SPI_INTR_CLR_4 0x4CC17F0 + +#define mmCPU_IF_NIC_SPI_INTR_CLR_5 0x4CC17F4 + +#define mmCPU_IF_NIC_SPI_INTR_CLR_6 0x4CC17F8 + +#define mmCPU_IF_NIC_SPI_INTR_CLR_7 0x4CC17FC + +#define mmCPU_IF_NIC_SPI_INTR_CLR_8 0x4CC1800 + +#define mmCPU_IF_NIC_SPI_INTR_CLR_9 0x4CC1804 + +#define mmCPU_IF_NIC_SPI_INTR_CLR_10 0x4CC1808 + +#define mmCPU_IF_NIC_SPI_INTR_CLR_11 0x4CC180C + +#define mmCPU_IF_NIC_SPI_INTR_MASK_0 0x4CC1810 + +#define mmCPU_IF_NIC_SPI_INTR_MASK_1 0x4CC1814 + +#define mmCPU_IF_NIC_SPI_INTR_MASK_2 0x4CC1818 + +#define mmCPU_IF_NIC_SPI_INTR_MASK_3 0x4CC181C + +#define mmCPU_IF_NIC_SPI_INTR_MASK_4 0x4CC1820 + +#define mmCPU_IF_NIC_SPI_INTR_MASK_5 0x4CC1824 + +#define mmCPU_IF_NIC_SPI_INTR_MASK_6 0x4CC1828 + +#define mmCPU_IF_NIC_SPI_INTR_MASK_7 0x4CC182C + +#define mmCPU_IF_NIC_SPI_INTR_MASK_8 0x4CC1830 + +#define mmCPU_IF_NIC_SPI_INTR_MASK_9 0x4CC1834 + +#define mmCPU_IF_NIC_SPI_INTR_MASK_10 0x4CC1838 + +#define mmCPU_IF_NIC_SPI_INTR_MASK_11 0x4CC183C + +#define mmCPU_IF_DEC_ECO_INTR_STS 0x4CC1840 + +#define mmCPU_IF_DEC_ECO_INTR_CLR 0x4CC1844 + +#define mmCPU_IF_DEC_ECO_INTR_MASK 0x4CC1848 + +#define mmCPU_IF_HIF_ECO_INTR_STS 0x4CC1850 + +#define mmCPU_IF_HIF_ECO_INTR_CLR 0x4CC1854 + +#define mmCPU_IF_HIF_ECO_INTR_MASK 0x4CC1858 + +#define mmCPU_IF_HMMU_ECO_INTR_STS 0x4CC1860 + +#define mmCPU_IF_HMMU_ECO_INTR_CLR 0x4CC1864 + +#define mmCPU_IF_HMMU_ECO_INTR_MASK 0x4CC1868 + +#define mmCPU_IF_NIC_ECO_INTR_STS 0x4CC1870 + +#define mmCPU_IF_NIC_ECO_INTR_CLR 0x4CC1874 + +#define mmCPU_IF_NIC_ECO_INTR_MASK 0x4CC1878 + +#define mmCPU_IF_MSI_X_INTR_STS_0 0x4CC1900 + +#define mmCPU_IF_MSI_X_INTR_STS_1 0x4CC1904 + +#define mmCPU_IF_MSI_X_INTR_STS_2 0x4CC1908 + +#define mmCPU_IF_MSI_X_INTR_STS_3 0x4CC190C + +#define mmCPU_IF_MSI_X_INTR_STS_4 0x4CC1910 + +#define mmCPU_IF_MSI_X_INTR_STS_5 0x4CC1914 + +#define mmCPU_IF_MSI_X_INTR_STS_6 0x4CC1918 + +#define mmCPU_IF_MSI_X_INTR_STS_7 0x4CC191C + +#define mmCPU_IF_MSI_X_INTR_STS_8 0x4CC1920 + +#define mmCPU_IF_MSI_X_INTR_STS_9 0x4CC1924 + +#define mmCPU_IF_MSI_X_INTR_STS_10 0x4CC1928 + +#define mmCPU_IF_MSI_X_INTR_STS_11 0x4CC192C + +#define mmCPU_IF_MSI_X_INTR_STS_12 0x4CC1930 + +#define mmCPU_IF_MSI_X_INTR_STS_13 0x4CC1934 + +#define mmCPU_IF_MSI_X_INTR_STS_14 0x4CC1938 + +#define mmCPU_IF_MSI_X_INTR_STS_15 0x4CC193C + +#define mmCPU_IF_MSI_X_INTR_CLR_0 0x4CC1940 + +#define mmCPU_IF_MSI_X_INTR_CLR_1 0x4CC1944 + +#define mmCPU_IF_MSI_X_INTR_CLR_2 0x4CC1948 + +#define mmCPU_IF_MSI_X_INTR_CLR_3 0x4CC194C + +#define mmCPU_IF_MSI_X_INTR_CLR_4 0x4CC1950 + +#define mmCPU_IF_MSI_X_INTR_CLR_5 0x4CC1954 + +#define mmCPU_IF_MSI_X_INTR_CLR_6 0x4CC1958 + +#define mmCPU_IF_MSI_X_INTR_CLR_7 0x4CC195C + +#define mmCPU_IF_MSI_X_INTR_CLR_8 0x4CC1960 + +#define mmCPU_IF_MSI_X_INTR_CLR_9 0x4CC1964 + +#define mmCPU_IF_MSI_X_INTR_CLR_10 0x4CC1968 + +#define mmCPU_IF_MSI_X_INTR_CLR_11 0x4CC196C + +#define mmCPU_IF_MSI_X_INTR_CLR_12 0x4CC1970 + +#define mmCPU_IF_MSI_X_INTR_CLR_13 0x4CC1974 + +#define mmCPU_IF_MSI_X_INTR_CLR_14 0x4CC1978 + +#define mmCPU_IF_MSI_X_INTR_CLR_15 0x4CC197C + +#define mmCPU_IF_MSI_X_INTR_MASK_0 0x4CC1980 + +#define mmCPU_IF_MSI_X_INTR_MASK_1 0x4CC1984 + +#define mmCPU_IF_MSI_X_INTR_MASK_2 0x4CC1988 + +#define mmCPU_IF_MSI_X_INTR_MASK_3 0x4CC198C + +#define mmCPU_IF_MSI_X_INTR_MASK_4 0x4CC1990 + +#define mmCPU_IF_MSI_X_INTR_MASK_5 0x4CC1994 + +#define mmCPU_IF_MSI_X_INTR_MASK_6 0x4CC1998 + +#define mmCPU_IF_MSI_X_INTR_MASK_7 0x4CC199C + +#define mmCPU_IF_MSI_X_INTR_MASK_8 0x4CC19A0 + +#define mmCPU_IF_MSI_X_INTR_MASK_9 0x4CC19A4 + +#define mmCPU_IF_MSI_X_INTR_MASK_10 0x4CC19A8 + +#define mmCPU_IF_MSI_X_INTR_MASK_11 0x4CC19AC + +#define mmCPU_IF_MSI_X_INTR_MASK_12 0x4CC19B0 + +#define mmCPU_IF_MSI_X_INTR_MASK_13 0x4CC19B4 + +#define mmCPU_IF_MSI_X_INTR_MASK_14 0x4CC19B8 + +#define mmCPU_IF_MSI_X_INTR_MASK_15 0x4CC19BC + +#define mmCPU_IF_MSI_X_BUSY_INTR_STS 0x4CC19C0 + +#define mmCPU_IF_MSI_X_BUSY_INTR_CLR 0x4CC19C4 + +#define mmCPU_IF_MSI_X_BUSY_INTR_MASK 0x4CC19C8 + +#define mmCPU_IF_MSI_X_GEN_ADDR 0x4CC19D0 + +#define mmCPU_IF_MSI_X_GEN_DATA 0x4CC19D4 + +#define mmCPU_IF_MSI_X_GEN_AWPROT 0x4CC19D8 + +#endif /* ASIC_REG_CPU_IF_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_dec0_cmd_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_dec0_cmd_masks.h new file mode 100644 index 000000000000..296ab832013f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_dec0_cmd_masks.h @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_DEC0_CMD_MASKS_H_ +#define ASIC_REG_DCORE0_DEC0_CMD_MASKS_H_ + +/* + ***************************************** + * DCORE0_DEC0_CMD + * (Prototype: VSI_CMD) + ***************************************** + */ + +/* DCORE0_DEC0_CMD_SWREG0 */ +#define DCORE0_DEC0_CMD_SWREG0_SW_HW_VERSION_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG0_SW_HW_VERSION_MASK 0xFFFF +#define DCORE0_DEC0_CMD_SWREG0_SW_HW_ID_SHIFT 16 +#define DCORE0_DEC0_CMD_SWREG0_SW_HW_ID_MASK 0xFFFF0000 + +/* DCORE0_DEC0_CMD_SWREG1 */ +#define DCORE0_DEC0_CMD_SWREG1_SW_HW_BUILDDATE_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG1_SW_HW_BUILDDATE_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG2 */ +#define DCORE0_DEC0_CMD_SWREG2_SW_EXT_NORM_INTR_SRC_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG2_SW_EXT_NORM_INTR_SRC_MASK 0xFFFF +#define DCORE0_DEC0_CMD_SWREG2_SW_EXT_ABN_INTR_SRC_SHIFT 16 +#define DCORE0_DEC0_CMD_SWREG2_SW_EXT_ABN_INTR_SRC_MASK 0xFFFF0000 + +/* DCORE0_DEC0_CMD_SWREG3 */ +#define DCORE0_DEC0_CMD_SWREG3_SW_EXE_CMDBUF_COUNT_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG3_SW_EXE_CMDBUF_COUNT_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG4 */ +#define DCORE0_DEC0_CMD_SWREG4_SW_CMD_EXE_LSB_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG4_SW_CMD_EXE_LSB_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG5 */ +#define DCORE0_DEC0_CMD_SWREG5_SW_CMD_EXE_MSB_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG5_SW_CMD_EXE_MSB_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG6 */ +#define DCORE0_DEC0_CMD_SWREG6_SW_AXI_TOTALARLEN_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG6_SW_AXI_TOTALARLEN_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG7 */ +#define DCORE0_DEC0_CMD_SWREG7_SW_AXI_TOTALR_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG7_SW_AXI_TOTALR_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG8 */ +#define DCORE0_DEC0_CMD_SWREG8_SW_AXI_TOTALAR_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG8_SW_AXI_TOTALAR_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG9 */ +#define DCORE0_DEC0_CMD_SWREG9_SW_AXI_TOTALRLAST_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG9_SW_AXI_TOTALRLAST_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG10 */ +#define DCORE0_DEC0_CMD_SWREG10_SW_AXI_TOTALAWLEN_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG10_SW_AXI_TOTALAWLEN_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG11 */ +#define DCORE0_DEC0_CMD_SWREG11_SW_AXI_TOTALW_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG11_SW_AXI_TOTALW_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG12 */ +#define DCORE0_DEC0_CMD_SWREG12_SW_AXI_TOTALAW_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG12_SW_AXI_TOTALAW_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG13 */ +#define DCORE0_DEC0_CMD_SWREG13_SW_AXI_TOTALWLAST_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG13_SW_AXI_TOTALWLAST_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG14 */ +#define DCORE0_DEC0_CMD_SWREG14_SW_AXI_TOTALB_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG14_SW_AXI_TOTALB_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG15 */ +#define DCORE0_DEC0_CMD_SWREG15_SW_WORK_STATE_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG15_SW_WORK_STATE_MASK 0x7 +#define DCORE0_DEC0_CMD_SWREG15_RSV_SHIFT 3 +#define DCORE0_DEC0_CMD_SWREG15_RSV_MASK 0x3FFFF8 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_BREADY_SHIFT 22 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_BREADY_MASK 0x400000 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_BVALID_SHIFT 23 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_BVALID_MASK 0x800000 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_WREADY_SHIFT 24 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_WREADY_MASK 0x1000000 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_WVALID_SHIFT 25 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_WVALID_MASK 0x2000000 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_AWREADY_SHIFT 26 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_AWREADY_MASK 0x4000000 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_AWVALID_SHIFT 27 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_AWVALID_MASK 0x8000000 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_RREADY_SHIFT 28 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_RREADY_MASK 0x10000000 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_RVALID_SHIFT 29 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_RVALID_MASK 0x20000000 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_ARREADY_SHIFT 30 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_ARREADY_MASK 0x40000000 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_ARVALID_SHIFT 31 +#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_ARVALID_MASK 0x80000000 + +/* DCORE0_DEC0_CMD_SWREG16 */ +#define DCORE0_DEC0_CMD_SWREG16_SW_START_TRIGGER_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG16_SW_START_TRIGGER_MASK 0x1 +#define DCORE0_DEC0_CMD_SWREG16_SW_RESET_ALL_SHIFT 1 +#define DCORE0_DEC0_CMD_SWREG16_SW_RESET_ALL_MASK 0x2 +#define DCORE0_DEC0_CMD_SWREG16_SW_RESET_CORE_SHIFT 2 +#define DCORE0_DEC0_CMD_SWREG16_SW_RESET_CORE_MASK 0x4 +#define DCORE0_DEC0_CMD_SWREG16_SW_ABORT_MODE_SHIFT 3 +#define DCORE0_DEC0_CMD_SWREG16_SW_ABORT_MODE_MASK 0x8 +#define DCORE0_DEC0_CMD_SWREG16_SW_CORE_CLK_GATE_DISABLE_SHIFT 4 +#define DCORE0_DEC0_CMD_SWREG16_SW_CORE_CLK_GATE_DISABLE_MASK 0x10 +#define DCORE0_DEC0_CMD_SWREG16_SW_MASTER_OUT_CLK_GATE_DISABLE_SHIFT 5 +#define DCORE0_DEC0_CMD_SWREG16_SW_MASTER_OUT_CLK_GATE_DISABLE_MASK 0x20 +#define DCORE0_DEC0_CMD_SWREG16_SW_AXI_CLK_GATE_DISABLE_SHIFT 6 +#define DCORE0_DEC0_CMD_SWREG16_SW_AXI_CLK_GATE_DISABLE_MASK 0x40 +#define DCORE0_DEC0_CMD_SWREG16_RSV_SHIFT 7 +#define DCORE0_DEC0_CMD_SWREG16_RSV_MASK 0xFFFFFF80 + +/* DCORE0_DEC0_CMD_SWREG17 */ +#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_ENDCMD_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_ENDCMD_MASK 0x1 +#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_BUSERR_SHIFT 1 +#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_BUSERR_MASK 0x2 +#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_TIMEOUT_SHIFT 2 +#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_TIMEOUT_MASK 0x4 +#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_CMDERR_SHIFT 3 +#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_CMDERR_MASK 0x8 +#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_ABORT_SHIFT 4 +#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_ABORT_MASK 0x10 +#define DCORE0_DEC0_CMD_SWREG17_RSV_1_SHIFT 5 +#define DCORE0_DEC0_CMD_SWREG17_RSV_1_MASK 0x20 +#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_JMP_SHIFT 6 +#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_JMP_MASK 0x40 +#define DCORE0_DEC0_CMD_SWREG17_RSV_SHIFT 7 +#define DCORE0_DEC0_CMD_SWREG17_RSV_MASK 0xFFFFFF80 + +/* DCORE0_DEC0_CMD_SWREG18 */ +#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_ENDCMD_EN_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_ENDCMD_EN_MASK 0x1 +#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_BUSERR_EN_SHIFT 1 +#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_BUSERR_EN_MASK 0x2 +#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_TIMEOUT_EN_SHIFT 2 +#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_TIMEOUT_EN_MASK 0x4 +#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_CMDERR_EN_SHIFT 3 +#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_CMDERR_EN_MASK 0x8 +#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_ABORT_EN_SHIFT 4 +#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_ABORT_EN_MASK 0x10 +#define DCORE0_DEC0_CMD_SWREG18_RSV_1_SHIFT 5 +#define DCORE0_DEC0_CMD_SWREG18_RSV_1_MASK 0x20 +#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_JMP_EN_SHIFT 6 +#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_JMP_EN_MASK 0x40 +#define DCORE0_DEC0_CMD_SWREG18_RSV_SHIFT 7 +#define DCORE0_DEC0_CMD_SWREG18_RSV_MASK 0xFFFFFF80 + +/* DCORE0_DEC0_CMD_SWREG19 */ +#define DCORE0_DEC0_CMD_SWREG19_SW_TIMEOUT_CYCLES_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG19_SW_TIMEOUT_CYCLES_MASK 0x7FFFFFFF +#define DCORE0_DEC0_CMD_SWREG19_SW_TIMEOUT_ENABLE_SHIFT 31 +#define DCORE0_DEC0_CMD_SWREG19_SW_TIMEOUT_ENABLE_MASK 0x80000000 + +/* DCORE0_DEC0_CMD_SWREG20 */ +#define DCORE0_DEC0_CMD_SWREG20_SW_CMDBUF_EXE_ADDR_LSB_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG20_SW_CMDBUF_EXE_ADDR_LSB_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG21 */ +#define DCORE0_DEC0_CMD_SWREG21_SW_CMDBUF_EXE_ADDR_MSB_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG21_SW_CMDBUF_EXE_ADDR_MSB_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG22 */ +#define DCORE0_DEC0_CMD_SWREG22_SW_CMDBUF_EXE_LENGTH_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG22_SW_CMDBUF_EXE_LENGTH_MASK 0xFFFF +#define DCORE0_DEC0_CMD_SWREG22_RSV_SHIFT 16 +#define DCORE0_DEC0_CMD_SWREG22_RSV_MASK 0xFFFF0000 + +/* DCORE0_DEC0_CMD_SWREG23 */ +#define DCORE0_DEC0_CMD_SWREG23_SW_AXI_ID_WR_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG23_SW_AXI_ID_WR_MASK 0xFF +#define DCORE0_DEC0_CMD_SWREG23_SW_AXI_ID_RD_SHIFT 8 +#define DCORE0_DEC0_CMD_SWREG23_SW_AXI_ID_RD_MASK 0xFF00 +#define DCORE0_DEC0_CMD_SWREG23_SW_MAX_BURST_LEN_SHIFT 16 +#define DCORE0_DEC0_CMD_SWREG23_SW_MAX_BURST_LEN_MASK 0xFF0000 +#define DCORE0_DEC0_CMD_SWREG23_RSV_SHIFT 24 +#define DCORE0_DEC0_CMD_SWREG23_RSV_MASK 0xF000000 +#define DCORE0_DEC0_CMD_SWREG23_SW_CMD_SWAP_SHIFT 28 +#define DCORE0_DEC0_CMD_SWREG23_SW_CMD_SWAP_MASK 0xF0000000 + +/* DCORE0_DEC0_CMD_SWREG24 */ +#define DCORE0_DEC0_CMD_SWREG24_SW_RDY_CMDBUF_COUNT_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG24_SW_RDY_CMDBUF_COUNT_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG25 */ +#define DCORE0_DEC0_CMD_SWREG25_SW_EXT_NORM_INTR_GATE_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG25_SW_EXT_NORM_INTR_GATE_MASK 0xFFFF +#define DCORE0_DEC0_CMD_SWREG25_SW_EXT_ABN_INTR_GATE_SHIFT 16 +#define DCORE0_DEC0_CMD_SWREG25_SW_EXT_ABN_INTR_GATE_MASK 0xFFFF0000 + +/* DCORE0_DEC0_CMD_SWREG26 */ +#define DCORE0_DEC0_CMD_SWREG26_SW_CMDBUF_EXE_ID_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG26_SW_CMDBUF_EXE_ID_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG64 */ +#define DCORE0_DEC0_CMD_SWREG64_SW_DUMMY0_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG64_SW_DUMMY0_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG65 */ +#define DCORE0_DEC0_CMD_SWREG65_SW_DUMMY1_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG65_SW_DUMMY1_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG66 */ +#define DCORE0_DEC0_CMD_SWREG66_SW_DUMMY2_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG66_SW_DUMMY2_MASK 0xFFFFFFFF + +/* DCORE0_DEC0_CMD_SWREG67 */ +#define DCORE0_DEC0_CMD_SWREG67_SW_DUMMY3_SHIFT 0 +#define DCORE0_DEC0_CMD_SWREG67_SW_DUMMY3_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_DCORE0_DEC0_CMD_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_dec0_cmd_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_dec0_cmd_regs.h new file mode 100644 index 000000000000..e26f0d77c9dc --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_dec0_cmd_regs.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_DEC0_CMD_REGS_H_ +#define ASIC_REG_DCORE0_DEC0_CMD_REGS_H_ + +/* + ***************************************** + * DCORE0_DEC0_CMD + * (Prototype: VSI_CMD) + ***************************************** + */ + +#define mmDCORE0_DEC0_CMD_SWREG0 0x41E0000 + +#define mmDCORE0_DEC0_CMD_SWREG1 0x41E0004 + +#define mmDCORE0_DEC0_CMD_SWREG2 0x41E0008 + +#define mmDCORE0_DEC0_CMD_SWREG3 0x41E000C + +#define mmDCORE0_DEC0_CMD_SWREG4 0x41E0010 + +#define mmDCORE0_DEC0_CMD_SWREG5 0x41E0014 + +#define mmDCORE0_DEC0_CMD_SWREG6 0x41E0018 + +#define mmDCORE0_DEC0_CMD_SWREG7 0x41E001C + +#define mmDCORE0_DEC0_CMD_SWREG8 0x41E0020 + +#define mmDCORE0_DEC0_CMD_SWREG9 0x41E0024 + +#define mmDCORE0_DEC0_CMD_SWREG10 0x41E0028 + +#define mmDCORE0_DEC0_CMD_SWREG11 0x41E002C + +#define mmDCORE0_DEC0_CMD_SWREG12 0x41E0030 + +#define mmDCORE0_DEC0_CMD_SWREG13 0x41E0034 + +#define mmDCORE0_DEC0_CMD_SWREG14 0x41E0038 + +#define mmDCORE0_DEC0_CMD_SWREG15 0x41E003C + +#define mmDCORE0_DEC0_CMD_SWREG16 0x41E0040 + +#define mmDCORE0_DEC0_CMD_SWREG17 0x41E0044 + +#define mmDCORE0_DEC0_CMD_SWREG18 0x41E0048 + +#define mmDCORE0_DEC0_CMD_SWREG19 0x41E004C + +#define mmDCORE0_DEC0_CMD_SWREG20 0x41E0050 + +#define mmDCORE0_DEC0_CMD_SWREG21 0x41E0054 + +#define mmDCORE0_DEC0_CMD_SWREG22 0x41E0058 + +#define mmDCORE0_DEC0_CMD_SWREG23 0x41E005C + +#define mmDCORE0_DEC0_CMD_SWREG24 0x41E0060 + +#define mmDCORE0_DEC0_CMD_SWREG25 0x41E0064 + +#define mmDCORE0_DEC0_CMD_SWREG26 0x41E0068 + +#define mmDCORE0_DEC0_CMD_SWREG64 0x41E0100 + +#define mmDCORE0_DEC0_CMD_SWREG65 0x41E0104 + +#define mmDCORE0_DEC0_CMD_SWREG66 0x41E0108 + +#define mmDCORE0_DEC0_CMD_SWREG67 0x41E010C + +#endif /* ASIC_REG_DCORE0_DEC0_CMD_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_axuser_regs.h new file mode 100644 index 000000000000..8de48939243b --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_EDMA0_CORE_CTX_AXUSER_REGS_H_ +#define ASIC_REG_DCORE0_EDMA0_CORE_CTX_AXUSER_REGS_H_ + +/* + ***************************************** + * DCORE0_EDMA0_CORE_CTX_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_ASID 0x41CB800 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_MMU_BP 0x41CB804 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_STRONG_ORDER 0x41CB808 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_NO_SNOOP 0x41CB80C + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION 0x41CB810 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_RD_ATOMIC 0x41CB814 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_QOS 0x41CB818 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_RSVD 0x41CB81C + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_EMEM_CPAGE 0x41CB820 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_CORE 0x41CB824 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_E2E_COORD 0x41CB828 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_WR_OVRD_LO 0x41CB830 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_WR_OVRD_HI 0x41CB834 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_RD_OVRD_LO 0x41CB838 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_RD_OVRD_HI 0x41CB83C + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_LB_COORD 0x41CB840 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_LB_LOCK 0x41CB844 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_LB_RSVD 0x41CB848 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_LB_OVRD 0x41CB84C + +#endif /* ASIC_REG_DCORE0_EDMA0_CORE_CTX_AXUSER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_regs.h new file mode 100644 index 000000000000..f73e76c8f5bd --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_regs.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_EDMA0_CORE_CTX_REGS_H_ +#define ASIC_REG_DCORE0_EDMA0_CORE_CTX_REGS_H_ + +/* + ***************************************** + * DCORE0_EDMA0_CORE_CTX + * (Prototype: DMA_CORE_CTX) + ***************************************** + */ + +#define mmDCORE0_EDMA0_CORE_CTX_RATE_LIM_TKN 0x41CB860 + +#define mmDCORE0_EDMA0_CORE_CTX_PWRLP 0x41CB864 + +#define mmDCORE0_EDMA0_CORE_CTX_TE_NUMROWS 0x41CB868 + +#define mmDCORE0_EDMA0_CORE_CTX_IDX 0x41CB86C + +#define mmDCORE0_EDMA0_CORE_CTX_IDX_INC 0x41CB870 + +#define mmDCORE0_EDMA0_CORE_CTX_CTRL 0x41CB874 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_0 0x41CB878 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_1 0x41CB87C + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_1 0x41CB880 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_2 0x41CB884 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_2 0x41CB888 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_3 0x41CB88C + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_3 0x41CB890 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_4 0x41CB894 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_4 0x41CB898 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_1 0x41CB89C + +#define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_1 0x41CB8A0 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_2 0x41CB8A4 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_2 0x41CB8A8 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_3 0x41CB8AC + +#define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_3 0x41CB8B0 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_4 0x41CB8B4 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_4 0x41CB8B8 + +#define mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_HI 0x41CB8BC + +#define mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_LO 0x41CB8C0 + +#define mmDCORE0_EDMA0_CORE_CTX_WR_COMP_WDATA 0x41CB8C4 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_LO 0x41CB8C8 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_HI 0x41CB8CC + +#define mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_LO 0x41CB8D0 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_HI 0x41CB8D4 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_LO 0x41CB8D8 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_HI 0x41CB8DC + +#define mmDCORE0_EDMA0_CORE_CTX_DST_BASE_LO 0x41CB8E0 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_BASE_HI 0x41CB8E4 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_0 0x41CB8E8 + +#define mmDCORE0_EDMA0_CORE_CTX_COMMIT 0x41CB8EC + +#endif /* ASIC_REG_DCORE0_EDMA0_CORE_CTX_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_masks.h new file mode 100644 index 000000000000..d600f6bf70d8 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_masks.h @@ -0,0 +1,415 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_EDMA0_CORE_MASKS_H_ +#define ASIC_REG_DCORE0_EDMA0_CORE_MASKS_H_ + +/* + ***************************************** + * DCORE0_EDMA0_CORE + * (Prototype: DMA_CORE) + ***************************************** + */ + +/* DCORE0_EDMA0_CORE_CFG_0 */ +#define DCORE0_EDMA0_CORE_CFG_0_EN_SHIFT 0 +#define DCORE0_EDMA0_CORE_CFG_0_EN_MASK 0x1 + +/* DCORE0_EDMA0_CORE_CFG_1 */ +#define DCORE0_EDMA0_CORE_CFG_1_HALT_SHIFT 0 +#define DCORE0_EDMA0_CORE_CFG_1_HALT_MASK 0x1 +#define DCORE0_EDMA0_CORE_CFG_1_FLUSH_SHIFT 1 +#define DCORE0_EDMA0_CORE_CFG_1_FLUSH_MASK 0x2 + +/* DCORE0_EDMA0_CORE_PROT */ +#define DCORE0_EDMA0_CORE_PROT_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_PROT_VAL_MASK 0x1 +#define DCORE0_EDMA0_CORE_PROT_ERR_VAL_SHIFT 1 +#define DCORE0_EDMA0_CORE_PROT_ERR_VAL_MASK 0x2 + +/* DCORE0_EDMA0_CORE_CKG */ +#define DCORE0_EDMA0_CORE_CKG_HBW_RBUF_SHIFT 0 +#define DCORE0_EDMA0_CORE_CKG_HBW_RBUF_MASK 0x1 +#define DCORE0_EDMA0_CORE_CKG_LBW_RBUF_KDMA_SHIFT 1 +#define DCORE0_EDMA0_CORE_CKG_LBW_RBUF_KDMA_MASK 0x2 +#define DCORE0_EDMA0_CORE_CKG_TE_SHIFT 2 +#define DCORE0_EDMA0_CORE_CKG_TE_MASK 0x4 + +/* DCORE0_EDMA0_CORE_RD_GLBL */ +#define DCORE0_EDMA0_CORE_RD_GLBL_LBW_VIA_HBW_SHIFT 0 +#define DCORE0_EDMA0_CORE_RD_GLBL_LBW_VIA_HBW_MASK 0x1 +#define DCORE0_EDMA0_CORE_RD_GLBL_HBW_FORCE_MISS_SHIFT 4 +#define DCORE0_EDMA0_CORE_RD_GLBL_HBW_FORCE_MISS_MASK 0x10 +#define DCORE0_EDMA0_CORE_RD_GLBL_LBW_FORCE_MISS_SHIFT 5 +#define DCORE0_EDMA0_CORE_RD_GLBL_LBW_FORCE_MISS_MASK 0x20 + +/* DCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND */ +#define DCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND_VAL_MASK 0xFFF + +/* DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE */ +#define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_DATA_SHIFT 0 +#define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_DATA_MASK 0xFFF +#define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_MD_SHIFT 16 +#define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_MD_MASK 0xFFF0000 + +/* DCORE0_EDMA0_CORE_RD_HBW_ARCACHE */ +#define DCORE0_EDMA0_CORE_RD_HBW_ARCACHE_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_RD_HBW_ARCACHE_VAL_MASK 0xF + +/* DCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS */ +#define DCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG */ +#define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_TOUT_SHIFT 0 +#define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF +#define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_SAT_SHIFT 16 +#define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 +#define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_EN_SHIFT 31 +#define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_EN_MASK 0x80000000 + +/* DCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND */ +#define DCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND_VAL_MASK 0xFFF + +/* DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE */ +#define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_DATA_SHIFT 0 +#define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_DATA_MASK 0xFFF +#define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_MD_SHIFT 16 +#define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_MD_MASK 0xFFF0000 + +/* DCORE0_EDMA0_CORE_RD_LBW_ARCACHE */ +#define DCORE0_EDMA0_CORE_RD_LBW_ARCACHE_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_RD_LBW_ARCACHE_VAL_MASK 0xF + +/* DCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS */ +#define DCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG */ +#define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_TOUT_SHIFT 0 +#define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF +#define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_SAT_SHIFT 16 +#define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 +#define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_EN_SHIFT 31 +#define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_EN_MASK 0x80000000 + +/* DCORE0_EDMA0_CORE_WR_HBW_MAX_OUTSTAND */ +#define DCORE0_EDMA0_CORE_WR_HBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_WR_HBW_MAX_OUTSTAND_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_CORE_WR_HBW_MAX_AWID */ +#define DCORE0_EDMA0_CORE_WR_HBW_MAX_AWID_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_WR_HBW_MAX_AWID_VAL_MASK 0x3FFF + +/* DCORE0_EDMA0_CORE_WR_HBW_AWCACHE */ +#define DCORE0_EDMA0_CORE_WR_HBW_AWCACHE_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_WR_HBW_AWCACHE_VAL_MASK 0xF + +/* DCORE0_EDMA0_CORE_WR_HBW_INFLIGHTS */ +#define DCORE0_EDMA0_CORE_WR_HBW_INFLIGHTS_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_WR_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG */ +#define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_TOUT_SHIFT 0 +#define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF +#define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_SAT_SHIFT 16 +#define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 +#define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_EN_SHIFT 31 +#define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_EN_MASK 0x80000000 + +/* DCORE0_EDMA0_CORE_WR_LBW_MAX_OUTSTAND */ +#define DCORE0_EDMA0_CORE_WR_LBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_WR_LBW_MAX_OUTSTAND_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_CORE_WR_LBW_MAX_AWID */ +#define DCORE0_EDMA0_CORE_WR_LBW_MAX_AWID_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_WR_LBW_MAX_AWID_VAL_MASK 0x7F + +/* DCORE0_EDMA0_CORE_WR_LBW_AWCACHE */ +#define DCORE0_EDMA0_CORE_WR_LBW_AWCACHE_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_WR_LBW_AWCACHE_VAL_MASK 0xF + +/* DCORE0_EDMA0_CORE_WR_LBW_INFLIGHTS */ +#define DCORE0_EDMA0_CORE_WR_LBW_INFLIGHTS_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_WR_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG */ +#define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_TOUT_SHIFT 0 +#define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF +#define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_SAT_SHIFT 16 +#define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 +#define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_EN_SHIFT 31 +#define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_EN_MASK 0x80000000 + +/* DCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND */ +#define DCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND_VAL_MASK 0x1F + +/* DCORE0_EDMA0_CORE_WR_COMP_AWUSER */ +#define DCORE0_EDMA0_CORE_WR_COMP_AWUSER_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_WR_COMP_AWUSER_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_ERR_CFG */ +#define DCORE0_EDMA0_CORE_ERR_CFG_ERR_MSG_EN_SHIFT 0 +#define DCORE0_EDMA0_CORE_ERR_CFG_ERR_MSG_EN_MASK 0x1 +#define DCORE0_EDMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT 1 +#define DCORE0_EDMA0_CORE_ERR_CFG_STOP_ON_ERR_MASK 0x2 + +/* DCORE0_EDMA0_CORE_ERR_CAUSE */ +#define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_RD_ERR_SHIFT 0 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK 0x1 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_WR_ERR_SHIFT 1 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_WR_ERR_MASK 0x2 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_MSG_WR_ERR_SHIFT 2 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_MSG_WR_ERR_MASK 0x4 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_DESC_OVF_SHIFT 3 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_DESC_OVF_MASK 0x8 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_RD_ERR_SHIFT 4 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_RD_ERR_MASK 0x10 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_WR_ERR_SHIFT 5 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_WR_ERR_MASK 0x20 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_TE_DESC_FIFO_OVFL_SHIFT 6 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_TE_DESC_FIFO_OVFL_MASK 0x40 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_SHIFT 7 +#define DCORE0_EDMA0_CORE_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_MASK 0x80 + +/* DCORE0_EDMA0_CORE_ERRMSG_ADDR_LO */ +#define DCORE0_EDMA0_CORE_ERRMSG_ADDR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_ERRMSG_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_ERRMSG_ADDR_HI */ +#define DCORE0_EDMA0_CORE_ERRMSG_ADDR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_ERRMSG_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_ERRMSG_WDATA */ +#define DCORE0_EDMA0_CORE_ERRMSG_WDATA_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_ERRMSG_WDATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_STS0 */ +#define DCORE0_EDMA0_CORE_STS0_RD_REQ_CNT_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS0_RD_REQ_CNT_MASK 0x7FFF +#define DCORE0_EDMA0_CORE_STS0_WR_REQ_CNT_SHIFT 16 +#define DCORE0_EDMA0_CORE_STS0_WR_REQ_CNT_MASK 0x7FFF0000 +#define DCORE0_EDMA0_CORE_STS0_BUSY_SHIFT 31 +#define DCORE0_EDMA0_CORE_STS0_BUSY_MASK 0x80000000 + +/* DCORE0_EDMA0_CORE_STS1 */ +#define DCORE0_EDMA0_CORE_STS1_IS_HALT_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS1_IS_HALT_MASK 0x1 + +/* DCORE0_EDMA0_CORE_STS_RD_CTX_SEL */ +#define DCORE0_EDMA0_CORE_STS_RD_CTX_SEL_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_RD_CTX_SEL_VAL_MASK 0x7 +#define DCORE0_EDMA0_CORE_STS_RD_CTX_SEL_STRIDE_SHIFT 8 +#define DCORE0_EDMA0_CORE_STS_RD_CTX_SEL_STRIDE_MASK 0x100 + +/* DCORE0_EDMA0_CORE_STS_RD_CTX_SIZE */ +#define DCORE0_EDMA0_CORE_STS_RD_CTX_SIZE_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_RD_CTX_SIZE_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_LO */ +#define DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_HI */ +#define DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_STS_RD_CTX_ID */ +#define DCORE0_EDMA0_CORE_STS_RD_CTX_ID_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_RD_CTX_ID_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_LO */ +#define DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_HI */ +#define DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR */ +#define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF +#define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_RDY_SHIFT 30 +#define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_RDY_MASK 0x40000000 +#define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_VLD_SHIFT 31 +#define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_VLD_MASK 0x80000000 + +/* DCORE0_EDMA0_CORE_STS_WR_CTX_SEL */ +#define DCORE0_EDMA0_CORE_STS_WR_CTX_SEL_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_WR_CTX_SEL_VAL_MASK 0x7 +#define DCORE0_EDMA0_CORE_STS_WR_CTX_SEL_STRIDE_SHIFT 8 +#define DCORE0_EDMA0_CORE_STS_WR_CTX_SEL_STRIDE_MASK 0x100 + +/* DCORE0_EDMA0_CORE_STS_WR_CTX_SIZE */ +#define DCORE0_EDMA0_CORE_STS_WR_CTX_SIZE_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_WR_CTX_SIZE_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_LO */ +#define DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_HI */ +#define DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_STS_WR_CTX_ID */ +#define DCORE0_EDMA0_CORE_STS_WR_CTX_ID_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_WR_CTX_ID_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO */ +#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VAL_MASK 0x3FFFF +#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_RDY_SHIFT 30 +#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_RDY_MASK 0x40000000 +#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VLD_SHIFT 31 +#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VLD_MASK 0x80000000 + +/* DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI */ +#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VAL_MASK 0x3FFFF +#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_RDY_SHIFT 30 +#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_RDY_MASK 0x40000000 +#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VLD_SHIFT 31 +#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VLD_MASK 0x80000000 + +/* DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR */ +#define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF +#define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_RDY_SHIFT 30 +#define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_RDY_MASK 0x40000000 +#define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_VLD_SHIFT 31 +#define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_VLD_MASK 0x80000000 + +/* DCORE0_EDMA0_CORE_PWRLP_CFG */ +#define DCORE0_EDMA0_CORE_PWRLP_CFG_GLBL_EN_SHIFT 0 +#define DCORE0_EDMA0_CORE_PWRLP_CFG_GLBL_EN_MASK 0x1 +#define DCORE0_EDMA0_CORE_PWRLP_CFG_CLR_SHIFT 4 +#define DCORE0_EDMA0_CORE_PWRLP_CFG_CLR_MASK 0x10 + +/* DCORE0_EDMA0_CORE_PWRLP_STS */ +#define DCORE0_EDMA0_CORE_PWRLP_STS_RLVL_SHIFT 0 +#define DCORE0_EDMA0_CORE_PWRLP_STS_RLVL_MASK 0x7F +#define DCORE0_EDMA0_CORE_PWRLP_STS_WLVL_SHIFT 8 +#define DCORE0_EDMA0_CORE_PWRLP_STS_WLVL_MASK 0x7F00 +#define DCORE0_EDMA0_CORE_PWRLP_STS_RCNT_SHIFT 16 +#define DCORE0_EDMA0_CORE_PWRLP_STS_RCNT_MASK 0x7F0000 +#define DCORE0_EDMA0_CORE_PWRLP_STS_WCNT_SHIFT 23 +#define DCORE0_EDMA0_CORE_PWRLP_STS_WCNT_MASK 0x3F800000 +#define DCORE0_EDMA0_CORE_PWRLP_STS_RFULL_SHIFT 30 +#define DCORE0_EDMA0_CORE_PWRLP_STS_RFULL_MASK 0x40000000 +#define DCORE0_EDMA0_CORE_PWRLP_STS_WFULL_SHIFT 31 +#define DCORE0_EDMA0_CORE_PWRLP_STS_WFULL_MASK 0x80000000 + +/* DCORE0_EDMA0_CORE_DBG_DESC_CNT */ +#define DCORE0_EDMA0_CORE_DBG_DESC_CNT_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_DBG_DESC_CNT_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_DBG_STS */ +#define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_FULL_SHIFT 0 +#define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_FULL_MASK 0x1 +#define DCORE0_EDMA0_CORE_DBG_STS_WR_CTX_FULL_SHIFT 1 +#define DCORE0_EDMA0_CORE_DBG_STS_WR_CTX_FULL_MASK 0x2 +#define DCORE0_EDMA0_CORE_DBG_STS_WR_COMP_FULL_SHIFT 2 +#define DCORE0_EDMA0_CORE_DBG_STS_WR_COMP_FULL_MASK 0x4 +#define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_EMPTY_SHIFT 3 +#define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_EMPTY_MASK 0x8 +#define DCORE0_EDMA0_CORE_DBG_STS_WR_CTX_EMPTY_SHIFT 4 +#define DCORE0_EDMA0_CORE_DBG_STS_WR_CTX_EMPTY_MASK 0x10 +#define DCORE0_EDMA0_CORE_DBG_STS_WR_COMP_EMPTY_SHIFT 5 +#define DCORE0_EDMA0_CORE_DBG_STS_WR_COMP_EMPTY_MASK 0x20 +#define DCORE0_EDMA0_CORE_DBG_STS_TE_EMPTY_SHIFT 6 +#define DCORE0_EDMA0_CORE_DBG_STS_TE_EMPTY_MASK 0x40 +#define DCORE0_EDMA0_CORE_DBG_STS_TE_BUSY_SHIFT 7 +#define DCORE0_EDMA0_CORE_DBG_STS_TE_BUSY_MASK 0x80 +#define DCORE0_EDMA0_CORE_DBG_STS_GSKT_EMPTY_SHIFT 8 +#define DCORE0_EDMA0_CORE_DBG_STS_GSKT_EMPTY_MASK 0x100 +#define DCORE0_EDMA0_CORE_DBG_STS_GSKT_FULL_SHIFT 9 +#define DCORE0_EDMA0_CORE_DBG_STS_GSKT_FULL_MASK 0x200 +#define DCORE0_EDMA0_CORE_DBG_STS_RD_AGU_CS_SHIFT 10 +#define DCORE0_EDMA0_CORE_DBG_STS_RD_AGU_CS_MASK 0x400 +#define DCORE0_EDMA0_CORE_DBG_STS_WR_AGU_CS_SHIFT 11 +#define DCORE0_EDMA0_CORE_DBG_STS_WR_AGU_CS_MASK 0x800 + +/* DCORE0_EDMA0_CORE_DBG_BUF_STS */ +#define DCORE0_EDMA0_CORE_DBG_BUF_STS_HBW_FULLNESS_SHIFT 0 +#define DCORE0_EDMA0_CORE_DBG_BUF_STS_HBW_FULLNESS_MASK 0xFFF +#define DCORE0_EDMA0_CORE_DBG_BUF_STS_LBW_FULLNESS_SHIFT 16 +#define DCORE0_EDMA0_CORE_DBG_BUF_STS_LBW_FULLNESS_MASK 0xFFF0000 + +/* DCORE0_EDMA0_CORE_DBG_RD_DESC_ID */ +#define DCORE0_EDMA0_CORE_DBG_RD_DESC_ID_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_DBG_RD_DESC_ID_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_CORE_DBG_WR_DESC_ID */ +#define DCORE0_EDMA0_CORE_DBG_WR_DESC_ID_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_DBG_WR_DESC_ID_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_CORE_APB_DMA_LBW_BASE */ +#define DCORE0_EDMA0_CORE_APB_DMA_LBW_BASE_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_APB_DMA_LBW_BASE_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_CORE_APB_MSTR_IF_LBW_BASE */ +#define DCORE0_EDMA0_CORE_APB_MSTR_IF_LBW_BASE_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_APB_MSTR_IF_LBW_BASE_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG */ +#define DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG_Y_X_FORCE_SHIFT 0 +#define DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG_Y_X_FORCE_MASK 0x1FF +#define DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG_FORCE_EN_SHIFT 9 +#define DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG_FORCE_EN_MASK 0x200 + +/* DCORE0_EDMA0_CORE_DBG_APB_ENABLER */ +#define DCORE0_EDMA0_CORE_DBG_APB_ENABLER_DIS_SHIFT 0 +#define DCORE0_EDMA0_CORE_DBG_APB_ENABLER_DIS_MASK 0x1 + +/* DCORE0_EDMA0_CORE_L2H_CMPR_LO */ +#define DCORE0_EDMA0_CORE_L2H_CMPR_LO_VAL_SHIFT 20 +#define DCORE0_EDMA0_CORE_L2H_CMPR_LO_VAL_MASK 0xFFF00000 + +/* DCORE0_EDMA0_CORE_L2H_CMPR_HI */ +#define DCORE0_EDMA0_CORE_L2H_CMPR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_L2H_CMPR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_L2H_MASK_LO */ +#define DCORE0_EDMA0_CORE_L2H_MASK_LO_VAL_SHIFT 20 +#define DCORE0_EDMA0_CORE_L2H_MASK_LO_VAL_MASK 0xFFF00000 + +/* DCORE0_EDMA0_CORE_L2H_MASK_HI */ +#define DCORE0_EDMA0_CORE_L2H_MASK_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_CORE_L2H_MASK_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_CORE_IDLE_IND_MASK */ +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_SHIFT 0 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_MASK 0x1 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_SHIFT 1 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_MASK 0x2 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_INSTAGE_SHIFT 2 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_INSTAGE_MASK 0x4 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_CORE_SHIFT 3 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_CORE_MASK 0x8 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_CNT_STS_SHIFT 8 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_CNT_STS_MASK 0x1F00 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_CNT_STS_SHIFT 16 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_CNT_STS_MASK 0x1F0000 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_INSTAGE_EMPTY_SHIFT 24 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_INSTAGE_EMPTY_MASK 0x1000000 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_CORE_IDLE_STS_SHIFT 25 +#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_CORE_IDLE_STS_MASK 0x2000000 + +/* DCORE0_EDMA0_CORE_APB_ENABLER */ +#define DCORE0_EDMA0_CORE_APB_ENABLER_DIS_SHIFT 0 +#define DCORE0_EDMA0_CORE_APB_ENABLER_DIS_MASK 0x1 + +#endif /* ASIC_REG_DCORE0_EDMA0_CORE_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_regs.h new file mode 100644 index 000000000000..84f068e4c602 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_regs.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_EDMA0_CORE_REGS_H_ +#define ASIC_REG_DCORE0_EDMA0_CORE_REGS_H_ + +/* + ***************************************** + * DCORE0_EDMA0_CORE + * (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDCORE0_EDMA0_CORE_CFG_0 0x41CB000 + +#define mmDCORE0_EDMA0_CORE_CFG_1 0x41CB004 + +#define mmDCORE0_EDMA0_CORE_PROT 0x41CB008 + +#define mmDCORE0_EDMA0_CORE_CKG 0x41CB00C + +#define mmDCORE0_EDMA0_CORE_RD_GLBL 0x41CB07C + +#define mmDCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND 0x41CB080 + +#define mmDCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE 0x41CB084 + +#define mmDCORE0_EDMA0_CORE_RD_HBW_ARCACHE 0x41CB088 + +#define mmDCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS 0x41CB090 + +#define mmDCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG 0x41CB094 + +#define mmDCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND 0x41CB0C0 + +#define mmDCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE 0x41CB0C4 + +#define mmDCORE0_EDMA0_CORE_RD_LBW_ARCACHE 0x41CB0C8 + +#define mmDCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS 0x41CB0D0 + +#define mmDCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG 0x41CB0D4 + +#define mmDCORE0_EDMA0_CORE_WR_HBW_MAX_OUTSTAND 0x41CB100 + +#define mmDCORE0_EDMA0_CORE_WR_HBW_MAX_AWID 0x41CB104 + +#define mmDCORE0_EDMA0_CORE_WR_HBW_AWCACHE 0x41CB108 + +#define mmDCORE0_EDMA0_CORE_WR_HBW_INFLIGHTS 0x41CB10C + +#define mmDCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG 0x41CB110 + +#define mmDCORE0_EDMA0_CORE_WR_LBW_MAX_OUTSTAND 0x41CB140 + +#define mmDCORE0_EDMA0_CORE_WR_LBW_MAX_AWID 0x41CB144 + +#define mmDCORE0_EDMA0_CORE_WR_LBW_AWCACHE 0x41CB148 + +#define mmDCORE0_EDMA0_CORE_WR_LBW_INFLIGHTS 0x41CB14C + +#define mmDCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG 0x41CB150 + +#define mmDCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND 0x41CB180 + +#define mmDCORE0_EDMA0_CORE_WR_COMP_AWUSER 0x41CB184 + +#define mmDCORE0_EDMA0_CORE_ERR_CFG 0x41CB300 + +#define mmDCORE0_EDMA0_CORE_ERR_CAUSE 0x41CB304 + +#define mmDCORE0_EDMA0_CORE_ERRMSG_ADDR_LO 0x41CB308 + +#define mmDCORE0_EDMA0_CORE_ERRMSG_ADDR_HI 0x41CB30C + +#define mmDCORE0_EDMA0_CORE_ERRMSG_WDATA 0x41CB310 + +#define mmDCORE0_EDMA0_CORE_STS0 0x41CB380 + +#define mmDCORE0_EDMA0_CORE_STS1 0x41CB384 + +#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_SEL 0x41CB400 + +#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_SIZE 0x41CB404 + +#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_BASE_LO 0x41CB408 + +#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_BASE_HI 0x41CB40C + +#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_ID 0x41CB410 + +#define mmDCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_LO 0x41CB414 + +#define mmDCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_HI 0x41CB418 + +#define mmDCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR 0x41CB41C + +#define mmDCORE0_EDMA0_CORE_STS_WR_CTX_SEL 0x41CB420 + +#define mmDCORE0_EDMA0_CORE_STS_WR_CTX_SIZE 0x41CB424 + +#define mmDCORE0_EDMA0_CORE_STS_WR_CTX_BASE_LO 0x41CB428 + +#define mmDCORE0_EDMA0_CORE_STS_WR_CTX_BASE_HI 0x41CB42C + +#define mmDCORE0_EDMA0_CORE_STS_WR_CTX_ID 0x41CB430 + +#define mmDCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO 0x41CB434 + +#define mmDCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI 0x41CB438 + +#define mmDCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR 0x41CB43C + +#define mmDCORE0_EDMA0_CORE_PWRLP_CFG 0x41CB700 + +#define mmDCORE0_EDMA0_CORE_PWRLP_STS 0x41CB704 + +#define mmDCORE0_EDMA0_CORE_DBG_DESC_CNT 0x41CB710 + +#define mmDCORE0_EDMA0_CORE_DBG_STS 0x41CB714 + +#define mmDCORE0_EDMA0_CORE_DBG_BUF_STS 0x41CB718 + +#define mmDCORE0_EDMA0_CORE_DBG_RD_DESC_ID 0x41CB720 + +#define mmDCORE0_EDMA0_CORE_DBG_WR_DESC_ID 0x41CB724 + +#define mmDCORE0_EDMA0_CORE_APB_DMA_LBW_BASE 0x41CB728 + +#define mmDCORE0_EDMA0_CORE_APB_MSTR_IF_LBW_BASE 0x41CB72C + +#define mmDCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG 0x41CB730 + +#define mmDCORE0_EDMA0_CORE_DBG_APB_ENABLER 0x41CBE1C + +#define mmDCORE0_EDMA0_CORE_L2H_CMPR_LO 0x41CBE20 + +#define mmDCORE0_EDMA0_CORE_L2H_CMPR_HI 0x41CBE24 + +#define mmDCORE0_EDMA0_CORE_L2H_MASK_LO 0x41CBE28 + +#define mmDCORE0_EDMA0_CORE_L2H_MASK_HI 0x41CBE2C + +#define mmDCORE0_EDMA0_CORE_IDLE_IND_MASK 0x41CBE30 + +#define mmDCORE0_EDMA0_CORE_APB_ENABLER 0x41CBE34 + +#endif /* ASIC_REG_DCORE0_EDMA0_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_arc_aux_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_arc_aux_regs.h new file mode 100644 index 000000000000..0fc45300df81 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_arc_aux_regs.h @@ -0,0 +1,591 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_EDMA0_QM_ARC_AUX_REGS_H_ +#define ASIC_REG_DCORE0_EDMA0_QM_ARC_AUX_REGS_H_ + +/* + ***************************************** + * DCORE0_EDMA0_QM_ARC_AUX + * (Prototype: QMAN_ARC_AUX) + ***************************************** + */ + +#define mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_REQ 0x41C8100 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_ACK 0x41C8104 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_RST_VEC_ADDR 0x41C8108 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DBG_MODE 0x41C810C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CLUSTER_NUM 0x41C8110 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_NUM 0x41C8114 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_WAKE_UP_EVENT 0x41C8118 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x41C811C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CTI_AP_STS 0x41C8120 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x41C8124 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_RST 0x41C8128 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_RST_REQ 0x41C812C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SRAM_LSB_ADDR 0x41C8130 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SRAM_MSB_ADDR 0x41C8134 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_PCIE_LSB_ADDR 0x41C8138 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_PCIE_MSB_ADDR 0x41C813C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_LSB_ADDR 0x41C8140 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_MSB_ADDR 0x41C8144 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM0_LSB_ADDR 0x41C8150 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM0_MSB_ADDR 0x41C8154 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM1_LSB_ADDR 0x41C8158 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM1_MSB_ADDR 0x41C815C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM2_LSB_ADDR 0x41C8160 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM2_MSB_ADDR 0x41C8164 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM3_LSB_ADDR 0x41C8168 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM3_MSB_ADDR 0x41C816C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM0_OFFSET 0x41C8170 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM1_OFFSET 0x41C8174 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM2_OFFSET 0x41C8178 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM3_OFFSET 0x41C817C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x41C8180 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x41C8184 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x41C8188 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x41C818C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x41C8190 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x41C8194 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x41C8198 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x41C819C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x41C81A0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x41C81A4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x41C81A8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x41C81AC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x41C81B0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x41C81B4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_CBU_AWCACHE_OVR 0x41C81B8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_LBU_AWCACHE_OVR 0x41C81BC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CONTEXT_ID_0 0x41C81C0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CONTEXT_ID_1 0x41C81C4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CONTEXT_ID_2 0x41C81C8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CONTEXT_ID_3 0x41C81CC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CONTEXT_ID_4 0x41C81D0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CONTEXT_ID_5 0x41C81D4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CONTEXT_ID_6 0x41C81D8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CONTEXT_ID_7 0x41C81DC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_0 0x41C81E0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_1 0x41C81E4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_2 0x41C81E8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_3 0x41C81EC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_4 0x41C81F0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_5 0x41C81F4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_6 0x41C81F8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_7 0x41C81FC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_0 0x41C8200 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_1 0x41C8204 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_2 0x41C8208 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_3 0x41C820C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_4 0x41C8210 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_5 0x41C8214 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_6 0x41C8218 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_7 0x41C821C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_8 0x41C8220 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_9 0x41C8224 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_10 0x41C8228 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_11 0x41C822C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_12 0x41C8230 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_13 0x41C8234 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_14 0x41C8238 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_15 0x41C823C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_IRQ_INTR_MASK_0 0x41C8280 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_IRQ_INTR_MASK_1 0x41C8284 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_SEI_INTR_STS 0x41C8290 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_SEI_INTR_CLR 0x41C8294 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_SEI_INTR_MASK 0x41C8298 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_EXCPTN_CAUSE 0x41C829C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SEI_INTR_HALT_EN 0x41C82A0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_SEI_INTR_HALT_MASK 0x41C82A4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_SEI_INTR_HALT_MASK 0x41C82A8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REI_INTR_STS 0x41C82B0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REI_INTR_CLR 0x41C82B4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REI_INTR_MASK 0x41C82B8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_ECC_ERR_ADDR 0x41C82BC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_ECC_SYNDROME 0x41C82C0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_I_CACHE_ECC_ERR_ADDR 0x41C82C4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_I_CACHE_ECC_SYNDROME 0x41C82C8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_D_CACHE_ECC_ERR_ADDR 0x41C82CC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_D_CACHE_ECC_SYNDROME 0x41C82D0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBW_TRMINATE_AWADDR_ERR 0x41C82E0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBW_TRMINATE_ARADDR_ERR 0x41C82E4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_BRESP 0x41C82E8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_RRESP 0x41C82EC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXLEN 0x41C82F0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXSIZE 0x41C82F4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_0 0x41C8300 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_1 0x41C8304 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_2 0x41C8308 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_3 0x41C830C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_4 0x41C8310 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_5 0x41C8314 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_6 0x41C8318 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_7 0x41C831C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_TOTAL_CBU_WR_CNT 0x41C8320 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_INFLIGHT_CBU_WR_CNT 0x41C8324 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_TOTAL_CBU_RD_CNT 0x41C8328 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_INFLIGHT_CBU_RD_CNT 0x41C832C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_TOTAL_LBU_WR_CNT 0x41C8330 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_INFLIGHT_LBU_WR_CNT 0x41C8334 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_TOTAL_LBU_RD_CNT 0x41C8338 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT 0x41C833C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_ARUSER_OVR 0x41C8350 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_ARUSER_OVR_EN 0x41C8354 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_AWUSER_OVR 0x41C8358 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_AWUSER_OVR_EN 0x41C835C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR 0x41C8360 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR_EN 0x41C8364 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR 0x41C8368 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR_EN 0x41C836C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_AXCACHE_OVR 0x41C8370 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_LOCK_OVR 0x41C8374 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_PROT_OVR 0x41C8378 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_MAX_OUTSTANDING 0x41C837C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN 0x41C8380 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORCE_RSP_OK 0x41C8384 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_NO_WR_INFLIGHT 0x41C838C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_SEI_INTR_ID 0x41C8390 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_ARUSER_OVR 0x41C8400 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_ARUSER_OVR_EN 0x41C8404 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_AWUSER_OVR 0x41C8408 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_AWUSER_OVR_EN 0x41C840C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_AXCACHE_OVR 0x41C8420 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_LOCK_OVR 0x41C8424 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_PROT_OVR 0x41C8428 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_MAX_OUTSTANDING 0x41C842C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN 0x41C8430 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_FORCE_RSP_OK 0x41C8434 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_NO_WR_INFLIGHT 0x41C843C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_SEI_INTR_ID 0x41C8440 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0 0x41C8500 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_1 0x41C8504 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_2 0x41C8508 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_3 0x41C850C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_4 0x41C8510 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_5 0x41C8514 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_6 0x41C8518 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_7 0x41C851C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_0 0x41C8520 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_1 0x41C8524 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_2 0x41C8528 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_3 0x41C852C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_4 0x41C8530 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_5 0x41C8534 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_6 0x41C8538 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_7 0x41C853C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_0 0x41C8540 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_1 0x41C8544 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_2 0x41C8548 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_3 0x41C854C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_4 0x41C8550 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_5 0x41C8554 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_6 0x41C8558 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_7 0x41C855C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_0 0x41C8560 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_1 0x41C8564 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_2 0x41C8568 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_3 0x41C856C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_4 0x41C8570 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_5 0x41C8574 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_6 0x41C8578 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_7 0x41C857C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_0 0x41C8580 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_1 0x41C8584 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_2 0x41C8588 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_3 0x41C858C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_4 0x41C8590 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_5 0x41C8594 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_6 0x41C8598 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_7 0x41C859C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x41C85A0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x41C85A4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x41C85A8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x41C85AC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x41C85B0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x41C85B4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x41C85B8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x41C85BC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x41C85C0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x41C85C4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x41C85C8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x41C85CC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x41C85D0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x41C85D4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x41C85D8 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x41C85DC + +#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x41C85E0 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_NIC_Q_VLD_ENTRY_MASK 0x41C85E4 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_DROP_EN 0x41C8620 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_WARN_MSG 0x41C8624 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG 0x41C8628 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWPROT 0x41C8630 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWUSER 0x41C8634 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWBURST 0x41C8638 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWLOCK 0x41C863C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWCACHE 0x41C8640 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_WRR_ARB_WEIGHT 0x41C8644 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x41C8648 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT 0x41C864C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x41C8650 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x41C8654 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_CQ_SHADOW_CI 0x41C8658 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI 0x41C865C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_AUX2APB_PROT 0x41C8700 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBW_FORK_WIN_EN 0x41C8704 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x41C8708 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x41C870C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x41C8710 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x41C8714 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR0 0x41C8718 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK0 0x41C871C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR1 0x41C8720 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK1 0x41C8724 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR0 0x41C8728 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR1 0x41C872C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x41C8730 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x41C8734 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x41C8738 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x41C873C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_WIN_EN 0x41C8740 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_LSB 0x41C8750 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_MSB 0x41C8754 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_LSB 0x41C8758 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_MSB 0x41C875C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_LSB 0x41C8760 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_MSB 0x41C8764 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_LSB 0x41C8768 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_MSB 0x41C876C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_LSB 0x41C8770 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_MSB 0x41C8774 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_LSB 0x41C8778 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_MSB 0x41C877C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_LSB 0x41C8780 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_MSB 0x41C8784 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_LSB 0x41C8788 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_MSB 0x41C878C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_LSB 0x41C8790 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_MSB 0x41C8794 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_CBU_TERMINATE_BRESP 0x41C8798 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_CBU_TERMINATE_RRESP 0x41C879C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_0 0x41C8800 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_1 0x41C8804 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_2 0x41C8808 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_3 0x41C880C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_4 0x41C8810 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_5 0x41C8814 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_6 0x41C8818 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_7 0x41C881C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_8 0x41C8820 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_9 0x41C8824 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_10 0x41C8828 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_11 0x41C882C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_12 0x41C8830 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_13 0x41C8834 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_14 0x41C8838 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_15 0x41C883C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_TRMINATE_AWADDR_ERR 0x41C8840 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_TRMINATE_ARADDR_ERR 0x41C8844 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_DCCM_TERMINATE_BRESP 0x41C8848 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_DCCM_TERMINATE_RRESP 0x41C884C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_DCCM_TERMINATE_EN 0x41C8850 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_DCCM_SECURE_REGION 0x41C8854 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x41C8900 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_CTL 0x41C8904 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x41C8908 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR 0x41C890C + +#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_ACC_ENGS_BUSER 0x41C8910 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN 0x41C8920 + +#endif /* ASIC_REG_DCORE0_EDMA0_QM_ARC_AUX_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_axuser_nonsecured_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_axuser_nonsecured_regs.h new file mode 100644 index 000000000000..88d2a133f129 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_axuser_nonsecured_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_EDMA0_QM_AXUSER_NONSECURED_REGS_H_ +#define ASIC_REG_DCORE0_EDMA0_QM_AXUSER_NONSECURED_REGS_H_ + +/* + ***************************************** + * DCORE0_EDMA0_QM_AXUSER_NONSECURED + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_ASID 0x41CAB80 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_MMU_BP 0x41CAB84 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x41CAB88 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x41CAB8C + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x41CAB90 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x41CAB94 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_QOS 0x41CAB98 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_RSVD 0x41CAB9C + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x41CABA0 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_CORE 0x41CABA4 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_E2E_COORD 0x41CABA8 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x41CABB0 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x41CABB4 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x41CABB8 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x41CABBC + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_LB_COORD 0x41CABC0 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_LB_LOCK 0x41CABC4 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_LB_RSVD 0x41CABC8 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_LB_OVRD 0x41CABCC + +#endif /* ASIC_REG_DCORE0_EDMA0_QM_AXUSER_NONSECURED_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_cgm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_cgm_regs.h new file mode 100644 index 000000000000..0b0a76a5b2a0 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_cgm_regs.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_EDMA0_QM_CGM_REGS_H_ +#define ASIC_REG_DCORE0_EDMA0_QM_CGM_REGS_H_ + +/* + ***************************************** + * DCORE0_EDMA0_QM_CGM + * (Prototype: QMAN_CGM) + ***************************************** + */ + +#define mmDCORE0_EDMA0_QM_CGM_CFG 0x41CAD80 + +#define mmDCORE0_EDMA0_QM_CGM_STS 0x41CAD84 + +#define mmDCORE0_EDMA0_QM_CGM_CFG1 0x41CAD88 + +#endif /* ASIC_REG_DCORE0_EDMA0_QM_CGM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_masks.h new file mode 100644 index 000000000000..102e2a65811c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_masks.h @@ -0,0 +1,1165 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_EDMA0_QM_MASKS_H_ +#define ASIC_REG_DCORE0_EDMA0_QM_MASKS_H_ + +/* + ***************************************** + * DCORE0_EDMA0_QM + * (Prototype: QMAN) + ***************************************** + */ + +/* DCORE0_EDMA0_QM_GLBL_CFG0 */ +#define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF +#define DCORE0_EDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT 4 +#define DCORE0_EDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0 +#define DCORE0_EDMA0_QM_GLBL_CFG0_CP_EN_SHIFT 9 +#define DCORE0_EDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00 +#define DCORE0_EDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT 14 +#define DCORE0_EDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000 + +/* DCORE0_EDMA0_QM_GLBL_CFG1 */ +#define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF +#define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_STOP_SHIFT 4 +#define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0 +#define DCORE0_EDMA0_QM_GLBL_CFG1_CP_STOP_SHIFT 9 +#define DCORE0_EDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00 +#define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 16 +#define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000 +#define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 20 +#define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000 +#define DCORE0_EDMA0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 25 +#define DCORE0_EDMA0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000 + +/* DCORE0_EDMA0_QM_GLBL_CFG2 */ +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_MASK 0x1 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_SHIFT 1 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_MASK 0x2 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWUSER_OVRD_SHIFT 4 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWUSER_OVRD_MASK 0x10 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARUSER_OVRD_SHIFT 5 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARUSER_OVRD_MASK 0x20 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWUSER_OVRD_SHIFT 6 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWUSER_OVRD_MASK 0x40 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARUSER_OVRD_SHIFT 7 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARUSER_OVRD_MASK 0x80 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWPROT_OVRD_SHIFT 8 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWPROT_OVRD_MASK 0x100 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARPROT_OVRD_SHIFT 9 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARPROT_OVRD_MASK 0x200 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWPROT_OVRD_SHIFT 10 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWPROT_OVRD_MASK 0x400 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARPROT_OVRD_SHIFT 11 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARPROT_OVRD_MASK 0x800 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWCACHE_OVRD_SHIFT 12 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWCACHE_OVRD_MASK 0x1000 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARCACHE_OVRD_SHIFT 13 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARCACHE_OVRD_MASK 0x2000 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWCACHE_OVRD_SHIFT 14 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWCACHE_OVRD_MASK 0x4000 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARCACHE_OVRD_SHIFT 15 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARCACHE_OVRD_MASK 0x8000 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_BUSER_OVRD_SHIFT 16 +#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_BUSER_OVRD_MASK 0x10000 + +/* DCORE0_EDMA0_QM_GLBL_ERR_CFG */ +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000 + +/* DCORE0_EDMA0_QM_GLBL_ERR_CFG1 */ +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_MASK 0x1 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_SHIFT 1 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_MASK 0x2 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_SHIFT 2 +#define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_MASK 0x4 + +/* DCORE0_EDMA0_QM_GLBL_ERR_ARC_HALT_EN */ +#define DCORE0_EDMA0_QM_GLBL_ERR_ARC_HALT_EN_ERR_IND_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_ERR_ARC_HALT_EN_ERR_IND_MASK 0xFFFFFF + +/* DCORE0_EDMA0_QM_GLBL_AXCACHE */ +#define DCORE0_EDMA0_QM_GLBL_AXCACHE_HBW_AR_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_AXCACHE_HBW_AR_MASK 0xF +#define DCORE0_EDMA0_QM_GLBL_AXCACHE_HBW_AW_SHIFT 16 +#define DCORE0_EDMA0_QM_GLBL_AXCACHE_HBW_AW_MASK 0xF0000 +#define DCORE0_EDMA0_QM_GLBL_AXCACHE_LBW_AW_SHIFT 20 +#define DCORE0_EDMA0_QM_GLBL_AXCACHE_LBW_AW_MASK 0xF00000 +#define DCORE0_EDMA0_QM_GLBL_AXCACHE_LBW_AR_SHIFT 24 +#define DCORE0_EDMA0_QM_GLBL_AXCACHE_LBW_AR_MASK 0xF000000 + +/* DCORE0_EDMA0_QM_GLBL_STS0 */ +#define DCORE0_EDMA0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF +#define DCORE0_EDMA0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4 +#define DCORE0_EDMA0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0 +#define DCORE0_EDMA0_QM_GLBL_STS0_CP_IDLE_SHIFT 9 +#define DCORE0_EDMA0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00 +#define DCORE0_EDMA0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16 +#define DCORE0_EDMA0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000 +#define DCORE0_EDMA0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20 +#define DCORE0_EDMA0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000 +#define DCORE0_EDMA0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25 +#define DCORE0_EDMA0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000 +#define DCORE0_EDMA0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31 +#define DCORE0_EDMA0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000 + +/* DCORE0_EDMA0_QM_GLBL_STS1 */ +#define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_MASK 0x1 +#define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IS_STOP_SHIFT 1 +#define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IS_STOP_MASK 0x2 + +/* DCORE0_EDMA0_QM_GLBL_ERR_STS */ +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQF_RD_ERR_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQF_RD_ERR_MASK 0x1 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CQF_RD_ERR_SHIFT 1 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CQF_RD_ERR_MASK 0x2 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_RD_ERR_SHIFT 2 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_RD_ERR_MASK 0x4 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_SHIFT 3 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_MASK 0x8 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_STOP_OP_SHIFT 4 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_STOP_OP_MASK 0x10 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_MSG_WR_ERR_SHIFT 5 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_MSG_WR_ERR_MASK 0x20 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_WREG_ERR_SHIFT 6 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_WREG_ERR_MASK 0x40 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE0_OVF_ERR_SHIFT 8 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE0_OVF_ERR_MASK 0x100 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE1_OVF_ERR_SHIFT 9 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE1_OVF_ERR_MASK 0x200 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE2_OVF_ERR_SHIFT 10 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE2_OVF_ERR_MASK 0x400 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE3_OVF_ERR_SHIFT 11 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE3_OVF_ERR_MASK 0x800 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE0_UDF_ERR_SHIFT 12 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE1_UDF_ERR_SHIFT 13 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE2_UDF_ERR_SHIFT 14 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE3_UDF_ERR_SHIFT 15 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE3_UDF_ERR_MASK 0x8000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CPDMA_UP_OVF_ERR_SHIFT 16 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CPDMA_UP_OVF_ERR_MASK 0x10000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQC_L2H_ERR_SHIFT 17 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQC_L2H_ERR_MASK 0x20000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_RSVD_18_24_SHIFT 18 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_RSVD_18_24_MASK 0x1FC0000 + +/* DCORE0_EDMA0_QM_GLBL_ERR_STS_4 */ +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD0_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD0_MASK 0x1 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQF_RD_ERR_SHIFT 1 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQF_RD_ERR_MASK 0x2 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_RD_ERR_SHIFT 2 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_RD_ERR_MASK 0x4 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_STOP_OP_SHIFT 4 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_STOP_OP_MASK 0x10 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_MSG_WR_ERR_SHIFT 5 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_MSG_WR_ERR_MASK 0x20 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_WREG_ERR_SHIFT 6 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_WREG_ERR_MASK 0x40 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_UDF_ERR_MASK 0x8000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CPDMA_UP_OVF_ERR_SHIFT 16 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CPDMA_UP_OVF_ERR_MASK 0x10000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD17_SHIFT 17 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD17_MASK 0x20000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQ_WR_IFIFO_CI_ERR_SHIFT 18 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQ_WR_IFIFO_CI_ERR_MASK 0x40000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQ_WR_CTL_CI_ERR_SHIFT 19 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQ_WR_CTL_CI_ERR_MASK 0x80000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQF_RD_ERR_SHIFT 20 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQF_RD_ERR_MASK 0x100000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_IFIFO_CI_ERR_SHIFT 21 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_IFIFO_CI_ERR_MASK 0x200000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_CTL_CI_ERR_SHIFT 22 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_CTL_CI_ERR_MASK 0x400000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_AXI_ERR_SHIFT 23 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_AXI_ERR_MASK 0x800000 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_SWITCH_WDT_ERR_SHIFT 24 +#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_SWITCH_WDT_ERR_MASK 0x1000000 + +/* DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN */ +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQF_RD_ERR_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQF_RD_ERR_MASK 0x1 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CQF_RD_ERR_SHIFT 1 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CQF_RD_ERR_MASK 0x2 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_RD_ERR_SHIFT 2 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_RD_ERR_MASK 0x4 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_STOP_OP_SHIFT 4 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_STOP_OP_MASK 0x10 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_MSG_WR_ERR_SHIFT 5 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_MSG_WR_ERR_MASK 0x20 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_WREG_ERR_SHIFT 6 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_WREG_ERR_MASK 0x40 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CPDMA_UP_OVF_ERR_SHIFT 16 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CPDMA_UP_OVF_ERR_MASK 0x10000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQC_L2H_ERR_SHIFT 17 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQC_L2H_ERR_MASK 0x20000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_RSVD_18_24_SHIFT 18 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_RSVD_18_24_MASK 0x1FC0000 + +/* DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4 */ +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD0_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD0_MASK 0x1 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQF_RD_ERR_SHIFT 1 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQF_RD_ERR_MASK 0x2 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_RD_ERR_SHIFT 2 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_RD_ERR_MASK 0x4 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_STOP_OP_SHIFT 4 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_STOP_OP_MASK 0x10 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_WREG_ERR_SHIFT 6 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_WREG_ERR_MASK 0x40 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CPDMA_UP_OVF_ERR_SHIFT 16 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CPDMA_UP_OVF_ERR_MASK 0x10000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD17_SHIFT 17 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD17_MASK 0x20000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_IFIFO_CI_ERR_SHIFT 18 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_IFIFO_CI_ERR_MASK 0x40000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_CTL_CI_ERR_SHIFT 19 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_CTL_CI_ERR_MASK 0x80000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQF_RD_ERR_SHIFT 20 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQF_RD_ERR_MASK 0x100000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_IFIFO_CI_ERR_SHIFT 21 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_IFIFO_CI_ERR_MASK 0x200000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_CTL_CI_ERR_SHIFT 22 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_CTL_CI_ERR_MASK 0x400000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_AXI_ERR_SHIFT 23 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_AXI_ERR_MASK 0x800000 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_SWITCH_WDT_ERR_SHIFT 24 +#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_SWITCH_WDT_ERR_MASK 0x1000000 + +/* DCORE0_EDMA0_QM_GLBL_PROT */ +#define DCORE0_EDMA0_QM_GLBL_PROT_PQF_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_PROT_PQF_MASK 0xF +#define DCORE0_EDMA0_QM_GLBL_PROT_CQF_SHIFT 4 +#define DCORE0_EDMA0_QM_GLBL_PROT_CQF_MASK 0x1F0 +#define DCORE0_EDMA0_QM_GLBL_PROT_CP_SHIFT 9 +#define DCORE0_EDMA0_QM_GLBL_PROT_CP_MASK 0x3E00 +#define DCORE0_EDMA0_QM_GLBL_PROT_ERR_SHIFT 14 +#define DCORE0_EDMA0_QM_GLBL_PROT_ERR_MASK 0x4000 +#define DCORE0_EDMA0_QM_GLBL_PROT_ARB_SHIFT 15 +#define DCORE0_EDMA0_QM_GLBL_PROT_ARB_MASK 0x8000 +#define DCORE0_EDMA0_QM_GLBL_PROT_PQC_SHIFT 16 +#define DCORE0_EDMA0_QM_GLBL_PROT_PQC_MASK 0x10000 +#define DCORE0_EDMA0_QM_GLBL_PROT_CQ_IFIFO_MSG_SHIFT 17 +#define DCORE0_EDMA0_QM_GLBL_PROT_CQ_IFIFO_MSG_MASK 0x20000 +#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQ_IFIFO_MSG_SHIFT 18 +#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQ_IFIFO_MSG_MASK 0x40000 +#define DCORE0_EDMA0_QM_GLBL_PROT_CQ_CTL_MSG_SHIFT 19 +#define DCORE0_EDMA0_QM_GLBL_PROT_CQ_CTL_MSG_MASK 0x80000 +#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQ_CTL_MSG_SHIFT 20 +#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQ_CTL_MSG_MASK 0x100000 +#define DCORE0_EDMA0_QM_GLBL_PROT_CP_WR_ARC_SHIFT 21 +#define DCORE0_EDMA0_QM_GLBL_PROT_CP_WR_ARC_MASK 0x200000 +#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQF_SHIFT 22 +#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQF_MASK 0x400000 +#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CORE_SHIFT 23 +#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CORE_MASK 0x800000 + +/* DCORE0_EDMA0_QM_PQ_BASE_LO */ +#define DCORE0_EDMA0_QM_PQ_BASE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PQ_BASE_HI */ +#define DCORE0_EDMA0_QM_PQ_BASE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PQ_SIZE */ +#define DCORE0_EDMA0_QM_PQ_SIZE_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQ_SIZE_VAL_MASK 0x1F + +/* DCORE0_EDMA0_QM_PQ_PI */ +#define DCORE0_EDMA0_QM_PQ_PI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PQ_CI */ +#define DCORE0_EDMA0_QM_PQ_CI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PQ_CFG0 */ +#define DCORE0_EDMA0_QM_PQ_CFG0_FORCE_STALL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQ_CFG0_FORCE_STALL_MASK 0x1 + +/* DCORE0_EDMA0_QM_PQ_CFG1 */ +#define DCORE0_EDMA0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0 +#define DCORE0_EDMA0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFF +#define DCORE0_EDMA0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define DCORE0_EDMA0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000 + +/* DCORE0_EDMA0_QM_PQ_STS0 */ +#define DCORE0_EDMA0_QM_PQ_STS0_CREDIT_CNT_SHIFT 0 +#define DCORE0_EDMA0_QM_PQ_STS0_CREDIT_CNT_MASK 0xFF +#define DCORE0_EDMA0_QM_PQ_STS0_FREE_CNT_SHIFT 8 +#define DCORE0_EDMA0_QM_PQ_STS0_FREE_CNT_MASK 0xFF00 +#define DCORE0_EDMA0_QM_PQ_STS0_INFLIGHT_CNT_SHIFT 16 +#define DCORE0_EDMA0_QM_PQ_STS0_INFLIGHT_CNT_MASK 0xFF0000 + +/* DCORE0_EDMA0_QM_PQ_STS1 */ +#define DCORE0_EDMA0_QM_PQ_STS1_BUF_EMPTY_SHIFT 0 +#define DCORE0_EDMA0_QM_PQ_STS1_BUF_EMPTY_MASK 0x1 +#define DCORE0_EDMA0_QM_PQ_STS1_BUSY_SHIFT 1 +#define DCORE0_EDMA0_QM_PQ_STS1_BUSY_MASK 0x2 + +/* DCORE0_EDMA0_QM_CQ_CFG0 */ +#define DCORE0_EDMA0_QM_CQ_CFG0_IF_B2B_EN_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_CFG0_IF_B2B_EN_MASK 0x1 +#define DCORE0_EDMA0_QM_CQ_CFG0_IF_MSG_EN_SHIFT 1 +#define DCORE0_EDMA0_QM_CQ_CFG0_IF_MSG_EN_MASK 0x2 +#define DCORE0_EDMA0_QM_CQ_CFG0_CTL_MSG_EN_SHIFT 2 +#define DCORE0_EDMA0_QM_CQ_CFG0_CTL_MSG_EN_MASK 0x4 + +/* DCORE0_EDMA0_QM_CQ_STS0 */ +#define DCORE0_EDMA0_QM_CQ_STS0_CREDIT_CNT_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_STS0_CREDIT_CNT_MASK 0xFF +#define DCORE0_EDMA0_QM_CQ_STS0_FREE_CNT_SHIFT 8 +#define DCORE0_EDMA0_QM_CQ_STS0_FREE_CNT_MASK 0xFF00 +#define DCORE0_EDMA0_QM_CQ_STS0_INFLIGHT_CNT_SHIFT 16 +#define DCORE0_EDMA0_QM_CQ_STS0_INFLIGHT_CNT_MASK 0xFF0000 + +/* DCORE0_EDMA0_QM_CQ_CFG1 */ +#define DCORE0_EDMA0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFF +#define DCORE0_EDMA0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define DCORE0_EDMA0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000 + +/* DCORE0_EDMA0_QM_CQ_STS1 */ +#define DCORE0_EDMA0_QM_CQ_STS1_BUF_EMPTY_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_STS1_BUF_EMPTY_MASK 0x1 +#define DCORE0_EDMA0_QM_CQ_STS1_BUSY_SHIFT 1 +#define DCORE0_EDMA0_QM_CQ_STS1_BUSY_MASK 0x2 + +/* DCORE0_EDMA0_QM_CQ_PTR_LO_0 */ +#define DCORE0_EDMA0_QM_CQ_PTR_LO_0_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_PTR_HI_0 */ +#define DCORE0_EDMA0_QM_CQ_PTR_HI_0_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_TSIZE_0 */ +#define DCORE0_EDMA0_QM_CQ_TSIZE_0_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_CTL_0 */ +#define DCORE0_EDMA0_QM_CQ_CTL_0_UP_SHIFT 28 +#define DCORE0_EDMA0_QM_CQ_CTL_0_UP_MASK 0xF0000000 + +/* DCORE0_EDMA0_QM_CQ_PTR_LO_1 */ +#define DCORE0_EDMA0_QM_CQ_PTR_LO_1_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_PTR_HI_1 */ +#define DCORE0_EDMA0_QM_CQ_PTR_HI_1_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_TSIZE_1 */ +#define DCORE0_EDMA0_QM_CQ_TSIZE_1_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_CTL_1 */ +#define DCORE0_EDMA0_QM_CQ_CTL_1_UP_SHIFT 28 +#define DCORE0_EDMA0_QM_CQ_CTL_1_UP_MASK 0xF0000000 + +/* DCORE0_EDMA0_QM_CQ_PTR_LO_2 */ +#define DCORE0_EDMA0_QM_CQ_PTR_LO_2_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_PTR_HI_2 */ +#define DCORE0_EDMA0_QM_CQ_PTR_HI_2_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_TSIZE_2 */ +#define DCORE0_EDMA0_QM_CQ_TSIZE_2_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_CTL_2 */ +#define DCORE0_EDMA0_QM_CQ_CTL_2_UP_SHIFT 28 +#define DCORE0_EDMA0_QM_CQ_CTL_2_UP_MASK 0xF0000000 + +/* DCORE0_EDMA0_QM_CQ_PTR_LO_3 */ +#define DCORE0_EDMA0_QM_CQ_PTR_LO_3_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_PTR_HI_3 */ +#define DCORE0_EDMA0_QM_CQ_PTR_HI_3_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_TSIZE_3 */ +#define DCORE0_EDMA0_QM_CQ_TSIZE_3_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_CTL_3 */ +#define DCORE0_EDMA0_QM_CQ_CTL_3_UP_SHIFT 28 +#define DCORE0_EDMA0_QM_CQ_CTL_3_UP_MASK 0xF0000000 + +/* DCORE0_EDMA0_QM_CQ_PTR_LO_4 */ +#define DCORE0_EDMA0_QM_CQ_PTR_LO_4_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_PTR_HI_4 */ +#define DCORE0_EDMA0_QM_CQ_PTR_HI_4_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_TSIZE_4 */ +#define DCORE0_EDMA0_QM_CQ_TSIZE_4_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_CTL_4 */ +#define DCORE0_EDMA0_QM_CQ_CTL_4_UP_SHIFT 28 +#define DCORE0_EDMA0_QM_CQ_CTL_4_UP_MASK 0xF0000000 + +/* DCORE0_EDMA0_QM_CQ_TSIZE_STS */ +#define DCORE0_EDMA0_QM_CQ_TSIZE_STS_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_PTR_LO_STS */ +#define DCORE0_EDMA0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_PTR_HI_STS */ +#define DCORE0_EDMA0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_IFIFO_STS */ +#define DCORE0_EDMA0_QM_CQ_IFIFO_STS_CNT_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_IFIFO_STS_CNT_MASK 0x7 +#define DCORE0_EDMA0_QM_CQ_IFIFO_STS_RDY_SHIFT 4 +#define DCORE0_EDMA0_QM_CQ_IFIFO_STS_RDY_MASK 0x10 +#define DCORE0_EDMA0_QM_CQ_IFIFO_STS_CTL_STALL_SHIFT 8 +#define DCORE0_EDMA0_QM_CQ_IFIFO_STS_CTL_STALL_MASK 0x100 + +/* DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO */ +#define DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI */ +#define DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO */ +#define DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI */ +#define DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO */ +#define DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI */ +#define DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO */ +#define DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI */ +#define DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_FENCE0_RDATA */ +#define DCORE0_EDMA0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF + +/* DCORE0_EDMA0_QM_CP_FENCE1_RDATA */ +#define DCORE0_EDMA0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF + +/* DCORE0_EDMA0_QM_CP_FENCE2_RDATA */ +#define DCORE0_EDMA0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF + +/* DCORE0_EDMA0_QM_CP_FENCE3_RDATA */ +#define DCORE0_EDMA0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF + +/* DCORE0_EDMA0_QM_CP_FENCE0_CNT */ +#define DCORE0_EDMA0_QM_CP_FENCE0_CNT_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF + +/* DCORE0_EDMA0_QM_CP_FENCE1_CNT */ +#define DCORE0_EDMA0_QM_CP_FENCE1_CNT_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF + +/* DCORE0_EDMA0_QM_CP_FENCE2_CNT */ +#define DCORE0_EDMA0_QM_CP_FENCE2_CNT_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF + +/* DCORE0_EDMA0_QM_CP_FENCE3_CNT */ +#define DCORE0_EDMA0_QM_CP_FENCE3_CNT_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF + +/* DCORE0_EDMA0_QM_CP_BARRIER_CFG */ +#define DCORE0_EDMA0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF +#define DCORE0_EDMA0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16 +#define DCORE0_EDMA0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000 + +/* DCORE0_EDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */ +#define DCORE0_EDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET */ +#define DCORE0_EDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_QM_CP_LDMA_TSIZE_OFFSET */ +#define DCORE0_EDMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_0 */ +#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_0_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_0_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_1 */ +#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_1_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_1_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_2 */ +#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_2_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_2_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_3 */ +#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_3_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_3_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_4 */ +#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_4_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_4_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_QM_CP_STS */ +#define DCORE0_EDMA0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFF +#define DCORE0_EDMA0_QM_CP_STS_ERDY_SHIFT 8 +#define DCORE0_EDMA0_QM_CP_STS_ERDY_MASK 0x100 +#define DCORE0_EDMA0_QM_CP_STS_SWITCH_EN_SHIFT 9 +#define DCORE0_EDMA0_QM_CP_STS_SWITCH_EN_MASK 0x200 +#define DCORE0_EDMA0_QM_CP_STS_MRDY_SHIFT 10 +#define DCORE0_EDMA0_QM_CP_STS_MRDY_MASK 0x400 +#define DCORE0_EDMA0_QM_CP_STS_SW_STOP_SHIFT 11 +#define DCORE0_EDMA0_QM_CP_STS_SW_STOP_MASK 0x800 +#define DCORE0_EDMA0_QM_CP_STS_FENCE_ID_SHIFT 12 +#define DCORE0_EDMA0_QM_CP_STS_FENCE_ID_MASK 0x3000 +#define DCORE0_EDMA0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 14 +#define DCORE0_EDMA0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x4000 +#define DCORE0_EDMA0_QM_CP_STS_FENCE_TARGET_SHIFT 16 +#define DCORE0_EDMA0_QM_CP_STS_FENCE_TARGET_MASK 0x3FFF0000 +#define DCORE0_EDMA0_QM_CP_STS_CUR_CQ_SHIFT 30 +#define DCORE0_EDMA0_QM_CP_STS_CUR_CQ_MASK 0x40000000 + +/* DCORE0_EDMA0_QM_CP_CURRENT_INST_LO */ +#define DCORE0_EDMA0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_CURRENT_INST_HI */ +#define DCORE0_EDMA0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_PRED */ +#define DCORE0_EDMA0_QM_CP_PRED_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_PRED_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_PRED_UPEN */ +#define DCORE0_EDMA0_QM_CP_PRED_UPEN_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_PRED_UPEN_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_DBG_0 */ +#define DCORE0_EDMA0_QM_CP_DBG_0_CS_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_DBG_0_CS_MASK 0x1F +#define DCORE0_EDMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 5 +#define DCORE0_EDMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x20 +#define DCORE0_EDMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 6 +#define DCORE0_EDMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x40 +#define DCORE0_EDMA0_QM_CP_DBG_0_MREB_STALL_SHIFT 7 +#define DCORE0_EDMA0_QM_CP_DBG_0_MREB_STALL_MASK 0x80 +#define DCORE0_EDMA0_QM_CP_DBG_0_STALL_SHIFT 8 +#define DCORE0_EDMA0_QM_CP_DBG_0_STALL_MASK 0x100 + +/* DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED */ +#define DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_TH_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_TH_MASK 0x3 +#define DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_VAL_SHIFT 8 +#define DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_VAL_MASK 0x300 + +/* DCORE0_EDMA0_QM_CP_IN_DATA_LO */ +#define DCORE0_EDMA0_QM_CP_IN_DATA_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_IN_DATA_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_IN_DATA_HI */ +#define DCORE0_EDMA0_QM_CP_IN_DATA_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_IN_DATA_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PQC_HBW_BASE_LO */ +#define DCORE0_EDMA0_QM_PQC_HBW_BASE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQC_HBW_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PQC_HBW_BASE_HI */ +#define DCORE0_EDMA0_QM_PQC_HBW_BASE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQC_HBW_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PQC_SIZE */ +#define DCORE0_EDMA0_QM_PQC_SIZE_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQC_SIZE_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PQC_PI */ +#define DCORE0_EDMA0_QM_PQC_PI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQC_PI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PQC_LBW_WDATA */ +#define DCORE0_EDMA0_QM_PQC_LBW_WDATA_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQC_LBW_WDATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PQC_LBW_BASE_LO */ +#define DCORE0_EDMA0_QM_PQC_LBW_BASE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQC_LBW_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PQC_LBW_BASE_HI */ +#define DCORE0_EDMA0_QM_PQC_LBW_BASE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PQC_LBW_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PQC_CFG */ +#define DCORE0_EDMA0_QM_PQC_CFG_EN_SHIFT 0 +#define DCORE0_EDMA0_QM_PQC_CFG_EN_MASK 0x1 +#define DCORE0_EDMA0_QM_PQC_CFG_DIRECT_SHIFT 4 +#define DCORE0_EDMA0_QM_PQC_CFG_DIRECT_MASK 0x10 + +/* DCORE0_EDMA0_QM_PQC_SECURE_PUSH_IND */ +#define DCORE0_EDMA0_QM_PQC_SECURE_PUSH_IND_CP_NUM_SHIFT 0 +#define DCORE0_EDMA0_QM_PQC_SECURE_PUSH_IND_CP_NUM_MASK 0x3 + +/* DCORE0_EDMA0_QM_ARB_MASK */ +#define DCORE0_EDMA0_QM_ARB_MASK_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_MASK_VAL_MASK 0xF + +/* DCORE0_EDMA0_QM_ARB_CFG_0 */ +#define DCORE0_EDMA0_QM_ARB_CFG_0_PRIO_TYPE_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_CFG_0_PRIO_TYPE_MASK 0x1 +#define DCORE0_EDMA0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4 +#define DCORE0_EDMA0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10 +#define DCORE0_EDMA0_QM_ARB_CFG_0_EN_SHIFT 8 +#define DCORE0_EDMA0_QM_ARB_CFG_0_EN_MASK 0x100 +#define DCORE0_EDMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 9 +#define DCORE0_EDMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x200 + +/* DCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH */ +#define DCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH_VAL_MASK 0x3 + +/* DCORE0_EDMA0_QM_ARB_WRR_WEIGHT */ +#define DCORE0_EDMA0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFF + +/* DCORE0_EDMA0_QM_ARB_CFG_1 */ +#define DCORE0_EDMA0_QM_ARB_CFG_1_CLR_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_CFG_1_CLR_MASK 0x1 + +/* DCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED */ +#define DCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F + +/* DCORE0_EDMA0_QM_ARB_MST_CRED_INC */ +#define DCORE0_EDMA0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST */ +#define DCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST */ +#define DCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN */ +#define DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1 */ +#define DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARB_SLV_CHOICE_WDT */ +#define DCORE0_EDMA0_QM_ARB_SLV_CHOICE_WDT_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_SLV_CHOICE_WDT_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARB_SLV_ID */ +#define DCORE0_EDMA0_QM_ARB_SLV_ID_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_SLV_ID_VAL_MASK 0x7F + +/* DCORE0_EDMA0_QM_ARB_MST_QUIET_PER */ +#define DCORE0_EDMA0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARB_MSG_MAX_INFLIGHT */ +#define DCORE0_EDMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F + +/* DCORE0_EDMA0_QM_ARB_BASE_LO */ +#define DCORE0_EDMA0_QM_ARB_BASE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARB_BASE_HI */ +#define DCORE0_EDMA0_QM_ARB_BASE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARB_STATE_STS */ +#define DCORE0_EDMA0_QM_ARB_STATE_STS_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARB_CHOICE_FULLNESS_STS */ +#define DCORE0_EDMA0_QM_ARB_CHOICE_FULLNESS_STS_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_CHOICE_FULLNESS_STS_VAL_MASK 0x7F + +/* DCORE0_EDMA0_QM_ARB_MSG_STS */ +#define DCORE0_EDMA0_QM_ARB_MSG_STS_FULL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_MSG_STS_FULL_MASK 0x1 +#define DCORE0_EDMA0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1 +#define DCORE0_EDMA0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2 + +/* DCORE0_EDMA0_QM_ARB_SLV_CHOICE_Q_HEAD */ +#define DCORE0_EDMA0_QM_ARB_SLV_CHOICE_Q_HEAD_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_SLV_CHOICE_Q_HEAD_VAL_MASK 0x3 + +/* DCORE0_EDMA0_QM_ARB_ERR_CAUSE */ +#define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_CHOICE_OVF_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_CHOICE_OVF_MASK 0x1 +#define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_CHOICE_WDT_SHIFT 1 +#define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_CHOICE_WDT_MASK 0x2 +#define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2 +#define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4 + +/* DCORE0_EDMA0_QM_ARB_ERR_MSG_EN */ +#define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_CHOICE_OVF_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_CHOICE_OVF_MASK 0x1 +#define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_CHOICE_WDT_SHIFT 1 +#define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_CHOICE_WDT_MASK 0x2 +#define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2 +#define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 + +/* DCORE0_EDMA0_QM_ARB_ERR_STS_DRP */ +#define DCORE0_EDMA0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3 + +/* DCORE0_EDMA0_QM_ARB_MST_CRED_STS */ +#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F +#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_IDX_SHIFT 24 +#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_IDX_MASK 0x1F000000 + +/* DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1 */ +#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1_VAL_MASK 0x7F +#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1_IDX_SHIFT 24 +#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1_IDX_MASK 0x1F000000 + +/* DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG */ +#define DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG_ARB_TYPE_SHIFT 0 +#define DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG_ARB_TYPE_MASK 0x1 +#define DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG_PER_ENTRY_SHIFT 4 +#define DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG_PER_ENTRY_MASK 0x10 + +/* DCORE0_EDMA0_QM_ARC_CQ_CFG0 */ +#define DCORE0_EDMA0_QM_ARC_CQ_CFG0_IF_B2B_EN_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_CFG0_IF_B2B_EN_MASK 0x1 +#define DCORE0_EDMA0_QM_ARC_CQ_CFG0_IF_MSG_EN_SHIFT 1 +#define DCORE0_EDMA0_QM_ARC_CQ_CFG0_IF_MSG_EN_MASK 0x2 +#define DCORE0_EDMA0_QM_ARC_CQ_CFG0_CTL_MSG_EN_SHIFT 2 +#define DCORE0_EDMA0_QM_ARC_CQ_CFG0_CTL_MSG_EN_MASK 0x4 + +/* DCORE0_EDMA0_QM_ARC_CQ_CFG1 */ +#define DCORE0_EDMA0_QM_ARC_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_CFG1_CREDIT_LIM_MASK 0xFF +#define DCORE0_EDMA0_QM_ARC_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define DCORE0_EDMA0_QM_ARC_CQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000 + +/* DCORE0_EDMA0_QM_ARC_CQ_PTR_LO */ +#define DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_CQ_PTR_HI */ +#define DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_CQ_TSIZE */ +#define DCORE0_EDMA0_QM_ARC_CQ_TSIZE_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_TSIZE_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_CQ_CTL */ +#define DCORE0_EDMA0_QM_ARC_CQ_CTL_UP_SHIFT 28 +#define DCORE0_EDMA0_QM_ARC_CQ_CTL_UP_MASK 0xF0000000 + +/* DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS */ +#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_CNT_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_CNT_MASK 0x7 +#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_RDY_SHIFT 4 +#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_RDY_MASK 0x10 +#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_CTL_STALL_SHIFT 8 +#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_CTL_STALL_MASK 0x100 + +/* DCORE0_EDMA0_QM_ARC_CQ_STS0 */ +#define DCORE0_EDMA0_QM_ARC_CQ_STS0_CREDIT_CNT_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_STS0_CREDIT_CNT_MASK 0xFF +#define DCORE0_EDMA0_QM_ARC_CQ_STS0_FREE_CNT_SHIFT 8 +#define DCORE0_EDMA0_QM_ARC_CQ_STS0_FREE_CNT_MASK 0xFF00 +#define DCORE0_EDMA0_QM_ARC_CQ_STS0_INFLIGHT_CNT_SHIFT 16 +#define DCORE0_EDMA0_QM_ARC_CQ_STS0_INFLIGHT_CNT_MASK 0xFF0000 + +/* DCORE0_EDMA0_QM_ARC_CQ_STS1 */ +#define DCORE0_EDMA0_QM_ARC_CQ_STS1_BUF_EMPTY_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_STS1_BUF_EMPTY_MASK 0x1 +#define DCORE0_EDMA0_QM_ARC_CQ_STS1_BUSY_SHIFT 1 +#define DCORE0_EDMA0_QM_ARC_CQ_STS1_BUSY_MASK 0x2 + +/* DCORE0_EDMA0_QM_ARC_CQ_TSIZE_STS */ +#define DCORE0_EDMA0_QM_ARC_CQ_TSIZE_STS_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS */ +#define DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS */ +#define DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_HI */ +#define DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_LO */ +#define DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI */ +#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO */ +#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI */ +#define DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO */ +#define DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_HI */ +#define DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO */ +#define DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_HI */ +#define DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO */ +#define DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ADDR_OVRD */ +#define DCORE0_EDMA0_QM_ADDR_OVRD_IDX_SHIFT 0 +#define DCORE0_EDMA0_QM_ADDR_OVRD_IDX_MASK 0xFF + +/* DCORE0_EDMA0_QM_CQ_IFIFO_CI */ +#define DCORE0_EDMA0_QM_CQ_IFIFO_CI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_IFIFO_CI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI */ +#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CQ_CTL_CI */ +#define DCORE0_EDMA0_QM_CQ_CTL_CI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CQ_CTL_CI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_CQ_CTL_CI */ +#define DCORE0_EDMA0_QM_ARC_CQ_CTL_CI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_CQ_CTL_CI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_CFG */ +#define DCORE0_EDMA0_QM_CP_CFG_SWITCH_EN_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_CFG_SWITCH_EN_MASK 0x1 +#define DCORE0_EDMA0_QM_CP_CFG_SWITCH_WD_EN_SHIFT 1 +#define DCORE0_EDMA0_QM_CP_CFG_SWITCH_WD_EN_MASK 0x2 + +/* DCORE0_EDMA0_QM_CP_EXT_SWITCH */ +#define DCORE0_EDMA0_QM_CP_EXT_SWITCH_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_EXT_SWITCH_VAL_MASK 0x1 + +/* DCORE0_EDMA0_QM_CP_SWITCH_WD_SET */ +#define DCORE0_EDMA0_QM_CP_SWITCH_WD_SET_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_SWITCH_WD_SET_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_CP_SWITCH_WD */ +#define DCORE0_EDMA0_QM_CP_SWITCH_WD_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_CP_SWITCH_WD_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_LO */ +#define DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_HI */ +#define DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_HI */ +#define DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_LO */ +#define DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ENGINE_ADDR_RANGE_SIZE */ +#define DCORE0_EDMA0_QM_ENGINE_ADDR_RANGE_SIZE_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_ENGINE_ADDR_RANGE_SIZE_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI */ +#define DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO */ +#define DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_QM_BASE_ADDR_HI */ +#define DCORE0_EDMA0_QM_QM_BASE_ADDR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_QM_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_QM_BASE_ADDR_LO */ +#define DCORE0_EDMA0_QM_QM_BASE_ADDR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_QM_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_ARC_PQC_SECURE_PUSH_IND */ +#define DCORE0_EDMA0_QM_ARC_PQC_SECURE_PUSH_IND_CP_NUM_SHIFT 0 +#define DCORE0_EDMA0_QM_ARC_PQC_SECURE_PUSH_IND_CP_NUM_MASK 0x3 + +/* DCORE0_EDMA0_QM_PQC_STS_0 */ +#define DCORE0_EDMA0_QM_PQC_STS_0_COMP_DATA_SHIFT 0 +#define DCORE0_EDMA0_QM_PQC_STS_0_COMP_DATA_MASK 0xFFFF +#define DCORE0_EDMA0_QM_PQC_STS_0_COMP_OFST_SHIFT 16 +#define DCORE0_EDMA0_QM_PQC_STS_0_COMP_OFST_MASK 0xFFFF0000 + +/* DCORE0_EDMA0_QM_PQC_STS_1 */ +#define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_CNTR_SHIFT 0 +#define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_CNTR_MASK 0xF +#define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_EMPTY_SHIFT 4 +#define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_EMPTY_MASK 0x10 +#define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_FULL_SHIFT 5 +#define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_FULL_MASK 0x20 + +/* DCORE0_EDMA0_QM_SEI_STATUS */ +#define DCORE0_EDMA0_QM_SEI_STATUS_QM_INT_SHIFT 0 +#define DCORE0_EDMA0_QM_SEI_STATUS_QM_INT_MASK 0x1 +#define DCORE0_EDMA0_QM_SEI_STATUS_ARC_INT_SHIFT 1 +#define DCORE0_EDMA0_QM_SEI_STATUS_ARC_INT_MASK 0x2 + +/* DCORE0_EDMA0_QM_SEI_MASK */ +#define DCORE0_EDMA0_QM_SEI_MASK_QM_INT_SHIFT 0 +#define DCORE0_EDMA0_QM_SEI_MASK_QM_INT_MASK 0x1 +#define DCORE0_EDMA0_QM_SEI_MASK_ARC_INT_SHIFT 1 +#define DCORE0_EDMA0_QM_SEI_MASK_ARC_INT_MASK 0x2 + +/* DCORE0_EDMA0_QM_GLBL_ERR_ADDR_LO */ +#define DCORE0_EDMA0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_GLBL_ERR_ADDR_HI */ +#define DCORE0_EDMA0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_GLBL_ERR_WDATA */ +#define DCORE0_EDMA0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_L2H_MASK_LO */ +#define DCORE0_EDMA0_QM_L2H_MASK_LO_VAL_SHIFT 20 +#define DCORE0_EDMA0_QM_L2H_MASK_LO_VAL_MASK 0xFFF00000 + +/* DCORE0_EDMA0_QM_L2H_MASK_HI */ +#define DCORE0_EDMA0_QM_L2H_MASK_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_L2H_MASK_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_L2H_CMPR_LO */ +#define DCORE0_EDMA0_QM_L2H_CMPR_LO_VAL_SHIFT 20 +#define DCORE0_EDMA0_QM_L2H_CMPR_LO_VAL_MASK 0xFFF00000 + +/* DCORE0_EDMA0_QM_L2H_CMPR_HI */ +#define DCORE0_EDMA0_QM_L2H_CMPR_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_L2H_CMPR_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_LOCAL_RANGE_BASE */ +#define DCORE0_EDMA0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_QM_LOCAL_RANGE_SIZE */ +#define DCORE0_EDMA0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF + +/* DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1 */ +#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31 +#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0 */ +#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1 */ +#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31 +#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0 */ +#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* DCORE0_EDMA0_QM_IND_GW_APB_CFG */ +#define DCORE0_EDMA0_QM_IND_GW_APB_CFG_ADDR_SHIFT 0 +#define DCORE0_EDMA0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF +#define DCORE0_EDMA0_QM_IND_GW_APB_CFG_CMD_SHIFT 31 +#define DCORE0_EDMA0_QM_IND_GW_APB_CFG_CMD_MASK 0x80000000 + +/* DCORE0_EDMA0_QM_IND_GW_APB_WDATA */ +#define DCORE0_EDMA0_QM_IND_GW_APB_WDATA_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_IND_GW_APB_RDATA */ +#define DCORE0_EDMA0_QM_IND_GW_APB_RDATA_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_IND_GW_APB_STATUS */ +#define DCORE0_EDMA0_QM_IND_GW_APB_STATUS_RDY_SHIFT 0 +#define DCORE0_EDMA0_QM_IND_GW_APB_STATUS_RDY_MASK 0x1 +#define DCORE0_EDMA0_QM_IND_GW_APB_STATUS_ERR_SHIFT 1 +#define DCORE0_EDMA0_QM_IND_GW_APB_STATUS_ERR_MASK 0x2 + +/* DCORE0_EDMA0_QM_PERF_CNT_FREE_LO */ +#define DCORE0_EDMA0_QM_PERF_CNT_FREE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PERF_CNT_FREE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PERF_CNT_FREE_HI */ +#define DCORE0_EDMA0_QM_PERF_CNT_FREE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PERF_CNT_FREE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PERF_CNT_IDLE_LO */ +#define DCORE0_EDMA0_QM_PERF_CNT_IDLE_LO_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PERF_CNT_IDLE_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PERF_CNT_IDLE_HI */ +#define DCORE0_EDMA0_QM_PERF_CNT_IDLE_HI_VAL_SHIFT 0 +#define DCORE0_EDMA0_QM_PERF_CNT_IDLE_HI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_EDMA0_QM_PERF_CNT_CFG */ +#define DCORE0_EDMA0_QM_PERF_CNT_CFG_PQ_MASK_SHIFT 0 +#define DCORE0_EDMA0_QM_PERF_CNT_CFG_PQ_MASK_MASK 0xF +#define DCORE0_EDMA0_QM_PERF_CNT_CFG_CQ_MASK_SHIFT 8 +#define DCORE0_EDMA0_QM_PERF_CNT_CFG_CQ_MASK_MASK 0x1F00 +#define DCORE0_EDMA0_QM_PERF_CNT_CFG_CP_MASK_SHIFT 16 +#define DCORE0_EDMA0_QM_PERF_CNT_CFG_CP_MASK_MASK 0x1F0000 +#define DCORE0_EDMA0_QM_PERF_CNT_CFG_AGENT_MASK_SHIFT 24 +#define DCORE0_EDMA0_QM_PERF_CNT_CFG_AGENT_MASK_MASK 0x1000000 +#define DCORE0_EDMA0_QM_PERF_CNT_CFG_EN_FREE_SHIFT 30 +#define DCORE0_EDMA0_QM_PERF_CNT_CFG_EN_FREE_MASK 0x40000000 +#define DCORE0_EDMA0_QM_PERF_CNT_CFG_EN_IDLE_SHIFT 31 +#define DCORE0_EDMA0_QM_PERF_CNT_CFG_EN_IDLE_MASK 0x80000000 + +#endif /* ASIC_REG_DCORE0_EDMA0_QM_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_regs.h new file mode 100644 index 000000000000..32d475b9ed11 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_regs.h @@ -0,0 +1,1057 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_EDMA0_QM_REGS_H_ +#define ASIC_REG_DCORE0_EDMA0_QM_REGS_H_ + +/* + ***************************************** + * DCORE0_EDMA0_QM + * (Prototype: QMAN) + ***************************************** + */ + +#define mmDCORE0_EDMA0_QM_GLBL_CFG0 0x41CA000 + +#define mmDCORE0_EDMA0_QM_GLBL_CFG1 0x41CA004 + +#define mmDCORE0_EDMA0_QM_GLBL_CFG2 0x41CA008 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_CFG 0x41CA00C + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_CFG1 0x41CA010 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_ARC_HALT_EN 0x41CA014 + +#define mmDCORE0_EDMA0_QM_GLBL_AXCACHE 0x41CA018 + +#define mmDCORE0_EDMA0_QM_GLBL_STS0 0x41CA01C + +#define mmDCORE0_EDMA0_QM_GLBL_STS1 0x41CA020 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_0 0x41CA024 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_1 0x41CA028 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_2 0x41CA02C + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_3 0x41CA030 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_4 0x41CA034 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_0 0x41CA038 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_1 0x41CA03C + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_2 0x41CA040 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_3 0x41CA044 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4 0x41CA048 + +#define mmDCORE0_EDMA0_QM_GLBL_PROT 0x41CA04C + +#define mmDCORE0_EDMA0_QM_PQ_BASE_LO_0 0x41CA050 + +#define mmDCORE0_EDMA0_QM_PQ_BASE_LO_1 0x41CA054 + +#define mmDCORE0_EDMA0_QM_PQ_BASE_LO_2 0x41CA058 + +#define mmDCORE0_EDMA0_QM_PQ_BASE_LO_3 0x41CA05C + +#define mmDCORE0_EDMA0_QM_PQ_BASE_HI_0 0x41CA060 + +#define mmDCORE0_EDMA0_QM_PQ_BASE_HI_1 0x41CA064 + +#define mmDCORE0_EDMA0_QM_PQ_BASE_HI_2 0x41CA068 + +#define mmDCORE0_EDMA0_QM_PQ_BASE_HI_3 0x41CA06C + +#define mmDCORE0_EDMA0_QM_PQ_SIZE_0 0x41CA070 + +#define mmDCORE0_EDMA0_QM_PQ_SIZE_1 0x41CA074 + +#define mmDCORE0_EDMA0_QM_PQ_SIZE_2 0x41CA078 + +#define mmDCORE0_EDMA0_QM_PQ_SIZE_3 0x41CA07C + +#define mmDCORE0_EDMA0_QM_PQ_PI_0 0x41CA080 + +#define mmDCORE0_EDMA0_QM_PQ_PI_1 0x41CA084 + +#define mmDCORE0_EDMA0_QM_PQ_PI_2 0x41CA088 + +#define mmDCORE0_EDMA0_QM_PQ_PI_3 0x41CA08C + +#define mmDCORE0_EDMA0_QM_PQ_CI_0 0x41CA090 + +#define mmDCORE0_EDMA0_QM_PQ_CI_1 0x41CA094 + +#define mmDCORE0_EDMA0_QM_PQ_CI_2 0x41CA098 + +#define mmDCORE0_EDMA0_QM_PQ_CI_3 0x41CA09C + +#define mmDCORE0_EDMA0_QM_PQ_CFG0_0 0x41CA0A0 + +#define mmDCORE0_EDMA0_QM_PQ_CFG0_1 0x41CA0A4 + +#define mmDCORE0_EDMA0_QM_PQ_CFG0_2 0x41CA0A8 + +#define mmDCORE0_EDMA0_QM_PQ_CFG0_3 0x41CA0AC + +#define mmDCORE0_EDMA0_QM_PQ_CFG1_0 0x41CA0B0 + +#define mmDCORE0_EDMA0_QM_PQ_CFG1_1 0x41CA0B4 + +#define mmDCORE0_EDMA0_QM_PQ_CFG1_2 0x41CA0B8 + +#define mmDCORE0_EDMA0_QM_PQ_CFG1_3 0x41CA0BC + +#define mmDCORE0_EDMA0_QM_PQ_STS0_0 0x41CA0C0 + +#define mmDCORE0_EDMA0_QM_PQ_STS0_1 0x41CA0C4 + +#define mmDCORE0_EDMA0_QM_PQ_STS0_2 0x41CA0C8 + +#define mmDCORE0_EDMA0_QM_PQ_STS0_3 0x41CA0CC + +#define mmDCORE0_EDMA0_QM_PQ_STS1_0 0x41CA0D0 + +#define mmDCORE0_EDMA0_QM_PQ_STS1_1 0x41CA0D4 + +#define mmDCORE0_EDMA0_QM_PQ_STS1_2 0x41CA0D8 + +#define mmDCORE0_EDMA0_QM_PQ_STS1_3 0x41CA0DC + +#define mmDCORE0_EDMA0_QM_CQ_CFG0_0 0x41CA0E0 + +#define mmDCORE0_EDMA0_QM_CQ_CFG0_1 0x41CA0E4 + +#define mmDCORE0_EDMA0_QM_CQ_CFG0_2 0x41CA0E8 + +#define mmDCORE0_EDMA0_QM_CQ_CFG0_3 0x41CA0EC + +#define mmDCORE0_EDMA0_QM_CQ_CFG0_4 0x41CA0F0 + +#define mmDCORE0_EDMA0_QM_CQ_STS0_0 0x41CA0F4 + +#define mmDCORE0_EDMA0_QM_CQ_STS0_1 0x41CA0F8 + +#define mmDCORE0_EDMA0_QM_CQ_STS0_2 0x41CA0FC + +#define mmDCORE0_EDMA0_QM_CQ_STS0_3 0x41CA100 + +#define mmDCORE0_EDMA0_QM_CQ_STS0_4 0x41CA104 + +#define mmDCORE0_EDMA0_QM_CQ_CFG1_0 0x41CA108 + +#define mmDCORE0_EDMA0_QM_CQ_CFG1_1 0x41CA10C + +#define mmDCORE0_EDMA0_QM_CQ_CFG1_2 0x41CA110 + +#define mmDCORE0_EDMA0_QM_CQ_CFG1_3 0x41CA114 + +#define mmDCORE0_EDMA0_QM_CQ_CFG1_4 0x41CA118 + +#define mmDCORE0_EDMA0_QM_CQ_STS1_0 0x41CA11C + +#define mmDCORE0_EDMA0_QM_CQ_STS1_1 0x41CA120 + +#define mmDCORE0_EDMA0_QM_CQ_STS1_2 0x41CA124 + +#define mmDCORE0_EDMA0_QM_CQ_STS1_3 0x41CA128 + +#define mmDCORE0_EDMA0_QM_CQ_STS1_4 0x41CA12C + +#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_0 0x41CA150 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_0 0x41CA154 + +#define mmDCORE0_EDMA0_QM_CQ_TSIZE_0 0x41CA158 + +#define mmDCORE0_EDMA0_QM_CQ_CTL_0 0x41CA15C + +#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_1 0x41CA160 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_1 0x41CA164 + +#define mmDCORE0_EDMA0_QM_CQ_TSIZE_1 0x41CA168 + +#define mmDCORE0_EDMA0_QM_CQ_CTL_1 0x41CA16C + +#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_2 0x41CA170 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_2 0x41CA174 + +#define mmDCORE0_EDMA0_QM_CQ_TSIZE_2 0x41CA178 + +#define mmDCORE0_EDMA0_QM_CQ_CTL_2 0x41CA17C + +#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_3 0x41CA180 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_3 0x41CA184 + +#define mmDCORE0_EDMA0_QM_CQ_TSIZE_3 0x41CA188 + +#define mmDCORE0_EDMA0_QM_CQ_CTL_3 0x41CA18C + +#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_4 0x41CA190 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_4 0x41CA194 + +#define mmDCORE0_EDMA0_QM_CQ_TSIZE_4 0x41CA198 + +#define mmDCORE0_EDMA0_QM_CQ_CTL_4 0x41CA19C + +#define mmDCORE0_EDMA0_QM_CQ_TSIZE_STS_0 0x41CA1A0 + +#define mmDCORE0_EDMA0_QM_CQ_TSIZE_STS_1 0x41CA1A4 + +#define mmDCORE0_EDMA0_QM_CQ_TSIZE_STS_2 0x41CA1A8 + +#define mmDCORE0_EDMA0_QM_CQ_TSIZE_STS_3 0x41CA1AC + +#define mmDCORE0_EDMA0_QM_CQ_TSIZE_STS_4 0x41CA1B0 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_STS_0 0x41CA1B4 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_STS_1 0x41CA1B8 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_STS_2 0x41CA1BC + +#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_STS_3 0x41CA1C0 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_STS_4 0x41CA1C4 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_STS_0 0x41CA1C8 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_STS_1 0x41CA1CC + +#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_STS_2 0x41CA1D0 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_STS_3 0x41CA1D4 + +#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_STS_4 0x41CA1D8 + +#define mmDCORE0_EDMA0_QM_CQ_IFIFO_STS_0 0x41CA1DC + +#define mmDCORE0_EDMA0_QM_CQ_IFIFO_STS_1 0x41CA1E0 + +#define mmDCORE0_EDMA0_QM_CQ_IFIFO_STS_2 0x41CA1E4 + +#define mmDCORE0_EDMA0_QM_CQ_IFIFO_STS_3 0x41CA1E8 + +#define mmDCORE0_EDMA0_QM_CQ_IFIFO_STS_4 0x41CA1EC + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 0x41CA1F0 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_1 0x41CA1F4 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_2 0x41CA1F8 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_3 0x41CA1FC + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_4 0x41CA200 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 0x41CA204 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_1 0x41CA208 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_2 0x41CA20C + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_3 0x41CA210 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_4 0x41CA214 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 0x41CA218 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_1 0x41CA21C + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_2 0x41CA220 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_3 0x41CA224 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_4 0x41CA228 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 0x41CA22C + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_1 0x41CA230 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_2 0x41CA234 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_3 0x41CA238 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_4 0x41CA23C + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 0x41CA240 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_1 0x41CA244 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 0x41CA248 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_3 0x41CA24C + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_4 0x41CA250 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 0x41CA254 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_1 0x41CA258 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_2 0x41CA25C + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_3 0x41CA260 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_4 0x41CA264 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 0x41CA268 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_1 0x41CA26C + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_2 0x41CA270 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_3 0x41CA274 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_4 0x41CA278 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 0x41CA27C + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_1 0x41CA280 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_2 0x41CA284 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_3 0x41CA288 + +#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_4 0x41CA28C + +#define mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_0 0x41CA290 + +#define mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_1 0x41CA294 + +#define mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_2 0x41CA298 + +#define mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_3 0x41CA29C + +#define mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_4 0x41CA2A0 + +#define mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_0 0x41CA2A4 + +#define mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_1 0x41CA2A8 + +#define mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_2 0x41CA2AC + +#define mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_3 0x41CA2B0 + +#define mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_4 0x41CA2B4 + +#define mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_0 0x41CA2B8 + +#define mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_1 0x41CA2BC + +#define mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_2 0x41CA2C0 + +#define mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_3 0x41CA2C4 + +#define mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_4 0x41CA2C8 + +#define mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_0 0x41CA2CC + +#define mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_1 0x41CA2D0 + +#define mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_2 0x41CA2D4 + +#define mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_3 0x41CA2D8 + +#define mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_4 0x41CA2DC + +#define mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_0 0x41CA2E0 + +#define mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_1 0x41CA2E4 + +#define mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_2 0x41CA2E8 + +#define mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_3 0x41CA2EC + +#define mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_4 0x41CA2F0 + +#define mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_0 0x41CA2F4 + +#define mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_1 0x41CA2F8 + +#define mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_2 0x41CA2FC + +#define mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_3 0x41CA300 + +#define mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_4 0x41CA304 + +#define mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_0 0x41CA308 + +#define mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_1 0x41CA30C + +#define mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_2 0x41CA310 + +#define mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_3 0x41CA314 + +#define mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_4 0x41CA318 + +#define mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_0 0x41CA31C + +#define mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_1 0x41CA320 + +#define mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_2 0x41CA324 + +#define mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_3 0x41CA328 + +#define mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_4 0x41CA32C + +#define mmDCORE0_EDMA0_QM_CP_BARRIER_CFG 0x41CA330 + +#define mmDCORE0_EDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0x41CA334 + +#define mmDCORE0_EDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET 0x41CA338 + +#define mmDCORE0_EDMA0_QM_CP_LDMA_TSIZE_OFFSET 0x41CA33C + +#define mmDCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_0 0x41CA340 + +#define mmDCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_1 0x41CA344 + +#define mmDCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_2 0x41CA348 + +#define mmDCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_3 0x41CA34C + +#define mmDCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_4 0x41CA350 + +#define mmDCORE0_EDMA0_QM_CP_STS_0 0x41CA368 + +#define mmDCORE0_EDMA0_QM_CP_STS_1 0x41CA36C + +#define mmDCORE0_EDMA0_QM_CP_STS_2 0x41CA370 + +#define mmDCORE0_EDMA0_QM_CP_STS_3 0x41CA374 + +#define mmDCORE0_EDMA0_QM_CP_STS_4 0x41CA378 + +#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_LO_0 0x41CA37C + +#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_LO_1 0x41CA380 + +#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_LO_2 0x41CA384 + +#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_LO_3 0x41CA388 + +#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_LO_4 0x41CA38C + +#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_HI_0 0x41CA390 + +#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_HI_1 0x41CA394 + +#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_HI_2 0x41CA398 + +#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_HI_3 0x41CA39C + +#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_HI_4 0x41CA3A0 + +#define mmDCORE0_EDMA0_QM_CP_PRED_0 0x41CA3A4 + +#define mmDCORE0_EDMA0_QM_CP_PRED_1 0x41CA3A8 + +#define mmDCORE0_EDMA0_QM_CP_PRED_2 0x41CA3AC + +#define mmDCORE0_EDMA0_QM_CP_PRED_3 0x41CA3B0 + +#define mmDCORE0_EDMA0_QM_CP_PRED_4 0x41CA3B4 + +#define mmDCORE0_EDMA0_QM_CP_PRED_UPEN_0 0x41CA3B8 + +#define mmDCORE0_EDMA0_QM_CP_PRED_UPEN_1 0x41CA3BC + +#define mmDCORE0_EDMA0_QM_CP_PRED_UPEN_2 0x41CA3C0 + +#define mmDCORE0_EDMA0_QM_CP_PRED_UPEN_3 0x41CA3C4 + +#define mmDCORE0_EDMA0_QM_CP_PRED_UPEN_4 0x41CA3C8 + +#define mmDCORE0_EDMA0_QM_CP_DBG_0_0 0x41CA3CC + +#define mmDCORE0_EDMA0_QM_CP_DBG_0_1 0x41CA3D0 + +#define mmDCORE0_EDMA0_QM_CP_DBG_0_2 0x41CA3D4 + +#define mmDCORE0_EDMA0_QM_CP_DBG_0_3 0x41CA3D8 + +#define mmDCORE0_EDMA0_QM_CP_DBG_0_4 0x41CA3DC + +#define mmDCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_0 0x41CA3E0 + +#define mmDCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_1 0x41CA3E4 + +#define mmDCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_2 0x41CA3E8 + +#define mmDCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_3 0x41CA3EC + +#define mmDCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_4 0x41CA3F0 + +#define mmDCORE0_EDMA0_QM_CP_IN_DATA_LO_0 0x41CA3F4 + +#define mmDCORE0_EDMA0_QM_CP_IN_DATA_LO_1 0x41CA3F8 + +#define mmDCORE0_EDMA0_QM_CP_IN_DATA_LO_2 0x41CA3FC + +#define mmDCORE0_EDMA0_QM_CP_IN_DATA_LO_3 0x41CA400 + +#define mmDCORE0_EDMA0_QM_CP_IN_DATA_LO_4 0x41CA404 + +#define mmDCORE0_EDMA0_QM_CP_IN_DATA_HI_0 0x41CA408 + +#define mmDCORE0_EDMA0_QM_CP_IN_DATA_HI_1 0x41CA40C + +#define mmDCORE0_EDMA0_QM_CP_IN_DATA_HI_2 0x41CA410 + +#define mmDCORE0_EDMA0_QM_CP_IN_DATA_HI_3 0x41CA414 + +#define mmDCORE0_EDMA0_QM_CP_IN_DATA_HI_4 0x41CA418 + +#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_LO_0 0x41CA41C + +#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_LO_1 0x41CA420 + +#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_LO_2 0x41CA424 + +#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_LO_3 0x41CA428 + +#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_HI_0 0x41CA42C + +#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_HI_1 0x41CA430 + +#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_HI_2 0x41CA434 + +#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_HI_3 0x41CA438 + +#define mmDCORE0_EDMA0_QM_PQC_SIZE_0 0x41CA43C + +#define mmDCORE0_EDMA0_QM_PQC_SIZE_1 0x41CA440 + +#define mmDCORE0_EDMA0_QM_PQC_SIZE_2 0x41CA444 + +#define mmDCORE0_EDMA0_QM_PQC_SIZE_3 0x41CA448 + +#define mmDCORE0_EDMA0_QM_PQC_PI_0 0x41CA44C + +#define mmDCORE0_EDMA0_QM_PQC_PI_1 0x41CA450 + +#define mmDCORE0_EDMA0_QM_PQC_PI_2 0x41CA454 + +#define mmDCORE0_EDMA0_QM_PQC_PI_3 0x41CA458 + +#define mmDCORE0_EDMA0_QM_PQC_LBW_WDATA_0 0x41CA45C + +#define mmDCORE0_EDMA0_QM_PQC_LBW_WDATA_1 0x41CA460 + +#define mmDCORE0_EDMA0_QM_PQC_LBW_WDATA_2 0x41CA464 + +#define mmDCORE0_EDMA0_QM_PQC_LBW_WDATA_3 0x41CA468 + +#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_LO_0 0x41CA46C + +#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_LO_1 0x41CA470 + +#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_LO_2 0x41CA474 + +#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_LO_3 0x41CA478 + +#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_HI_0 0x41CA47C + +#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_HI_1 0x41CA480 + +#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_HI_2 0x41CA484 + +#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_HI_3 0x41CA488 + +#define mmDCORE0_EDMA0_QM_PQC_CFG 0x41CA48C + +#define mmDCORE0_EDMA0_QM_PQC_SECURE_PUSH_IND 0x41CA490 + +#define mmDCORE0_EDMA0_QM_ARB_MASK 0x41CA4A0 + +#define mmDCORE0_EDMA0_QM_ARB_CFG_0 0x41CA4A4 + +#define mmDCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH 0x41CA4A8 + +#define mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_0 0x41CA4AC + +#define mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_1 0x41CA4B0 + +#define mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_2 0x41CA4B4 + +#define mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_3 0x41CA4B8 + +#define mmDCORE0_EDMA0_QM_ARB_CFG_1 0x41CA4BC + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_0 0x41CA4C0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_1 0x41CA4C4 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_2 0x41CA4C8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_3 0x41CA4CC + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_4 0x41CA4D0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_5 0x41CA4D4 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_6 0x41CA4D8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_7 0x41CA4DC + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_8 0x41CA4E0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_9 0x41CA4E4 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_10 0x41CA4E8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_11 0x41CA4EC + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_12 0x41CA4F0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_13 0x41CA4F4 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_14 0x41CA4F8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_15 0x41CA4FC + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_16 0x41CA500 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_17 0x41CA504 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_18 0x41CA508 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_19 0x41CA50C + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_20 0x41CA510 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_21 0x41CA514 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_22 0x41CA518 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_23 0x41CA51C + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_24 0x41CA520 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_25 0x41CA524 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_26 0x41CA528 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_27 0x41CA52C + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_28 0x41CA530 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_29 0x41CA534 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_30 0x41CA538 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_31 0x41CA53C + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_32 0x41CA540 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_33 0x41CA544 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_34 0x41CA548 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_35 0x41CA54C + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_36 0x41CA550 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_37 0x41CA554 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_38 0x41CA558 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_39 0x41CA55C + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_40 0x41CA560 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_41 0x41CA564 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_42 0x41CA568 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_43 0x41CA56C + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_44 0x41CA570 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_45 0x41CA574 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_46 0x41CA578 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_47 0x41CA57C + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_48 0x41CA580 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_49 0x41CA584 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_50 0x41CA588 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_51 0x41CA58C + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_52 0x41CA590 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_53 0x41CA594 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_54 0x41CA598 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_55 0x41CA59C + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_56 0x41CA5A0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_57 0x41CA5A4 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_58 0x41CA5A8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_59 0x41CA5AC + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_60 0x41CA5B0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_61 0x41CA5B4 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_62 0x41CA5B8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_63 0x41CA5BC + +#define mmDCORE0_EDMA0_QM_ARB_MST_CRED_INC 0x41CA5E0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0 0x41CA5E4 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1 0x41CA5E8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2 0x41CA5EC + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3 0x41CA5F0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4 0x41CA5F4 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5 0x41CA5F8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6 0x41CA5FC + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7 0x41CA600 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8 0x41CA604 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9 0x41CA608 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10 0x41CA60C + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11 0x41CA610 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12 0x41CA614 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13 0x41CA618 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14 0x41CA61C + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15 0x41CA620 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16 0x41CA624 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17 0x41CA628 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18 0x41CA62C + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19 0x41CA630 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20 0x41CA634 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21 0x41CA638 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22 0x41CA63C + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23 0x41CA640 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24 0x41CA644 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25 0x41CA648 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26 0x41CA64C + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27 0x41CA650 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28 0x41CA654 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29 0x41CA658 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30 0x41CA65C + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31 0x41CA660 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32 0x41CA664 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33 0x41CA668 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34 0x41CA66C + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35 0x41CA670 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36 0x41CA674 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37 0x41CA678 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38 0x41CA67C + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39 0x41CA680 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40 0x41CA684 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41 0x41CA688 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42 0x41CA68C + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43 0x41CA690 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44 0x41CA694 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45 0x41CA698 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46 0x41CA69C + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47 0x41CA6A0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48 0x41CA6A4 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49 0x41CA6A8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50 0x41CA6AC + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51 0x41CA6B0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52 0x41CA6B4 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53 0x41CA6B8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54 0x41CA6BC + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55 0x41CA6C0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56 0x41CA6C4 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57 0x41CA6C8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58 0x41CA6CC + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59 0x41CA6D0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60 0x41CA6D4 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61 0x41CA6D8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62 0x41CA6DC + +#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63 0x41CA6E0 + +#define mmDCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x41CA704 + +#define mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN 0x41CA708 + +#define mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1 0x41CA70C + +#define mmDCORE0_EDMA0_QM_ARB_SLV_CHOICE_WDT 0x41CA710 + +#define mmDCORE0_EDMA0_QM_ARB_SLV_ID 0x41CA714 + +#define mmDCORE0_EDMA0_QM_ARB_MST_QUIET_PER 0x41CA718 + +#define mmDCORE0_EDMA0_QM_ARB_MSG_MAX_INFLIGHT 0x41CA744 + +#define mmDCORE0_EDMA0_QM_ARB_BASE_LO 0x41CA754 + +#define mmDCORE0_EDMA0_QM_ARB_BASE_HI 0x41CA758 + +#define mmDCORE0_EDMA0_QM_ARB_STATE_STS 0x41CA780 + +#define mmDCORE0_EDMA0_QM_ARB_CHOICE_FULLNESS_STS 0x41CA784 + +#define mmDCORE0_EDMA0_QM_ARB_MSG_STS 0x41CA788 + +#define mmDCORE0_EDMA0_QM_ARB_SLV_CHOICE_Q_HEAD 0x41CA78C + +#define mmDCORE0_EDMA0_QM_ARB_ERR_CAUSE 0x41CA79C + +#define mmDCORE0_EDMA0_QM_ARB_ERR_MSG_EN 0x41CA7A0 + +#define mmDCORE0_EDMA0_QM_ARB_ERR_STS_DRP 0x41CA7A8 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CRED_STS 0x41CA7B0 + +#define mmDCORE0_EDMA0_QM_ARB_MST_CRED_STS_1 0x41CA7B4 + +#define mmDCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG 0x41CA7FC + +#define mmDCORE0_EDMA0_QM_ARC_CQ_CFG0 0x41CA800 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_CFG1 0x41CA804 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO 0x41CA808 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI 0x41CA80C + +#define mmDCORE0_EDMA0_QM_ARC_CQ_TSIZE 0x41CA810 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_CTL 0x41CA814 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS 0x41CA81C + +#define mmDCORE0_EDMA0_QM_ARC_CQ_STS0 0x41CA820 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_STS1 0x41CA824 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_TSIZE_STS 0x41CA828 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS 0x41CA82C + +#define mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS 0x41CA830 + +#define mmDCORE0_EDMA0_QM_CP_WR_ARC_ADDR_HI 0x41CA834 + +#define mmDCORE0_EDMA0_QM_CP_WR_ARC_ADDR_LO 0x41CA838 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI 0x41CA83C + +#define mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO 0x41CA840 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI 0x41CA844 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO 0x41CA848 + +#define mmDCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_HI 0x41CA84C + +#define mmDCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO 0x41CA850 + +#define mmDCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_HI 0x41CA854 + +#define mmDCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO 0x41CA858 + +#define mmDCORE0_EDMA0_QM_ADDR_OVRD 0x41CA85C + +#define mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_0 0x41CA860 + +#define mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_1 0x41CA864 + +#define mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_2 0x41CA868 + +#define mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_3 0x41CA86C + +#define mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_4 0x41CA870 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI 0x41CA874 + +#define mmDCORE0_EDMA0_QM_CQ_CTL_CI_0 0x41CA878 + +#define mmDCORE0_EDMA0_QM_CQ_CTL_CI_1 0x41CA87C + +#define mmDCORE0_EDMA0_QM_CQ_CTL_CI_2 0x41CA880 + +#define mmDCORE0_EDMA0_QM_CQ_CTL_CI_3 0x41CA884 + +#define mmDCORE0_EDMA0_QM_CQ_CTL_CI_4 0x41CA888 + +#define mmDCORE0_EDMA0_QM_ARC_CQ_CTL_CI 0x41CA88C + +#define mmDCORE0_EDMA0_QM_CP_CFG 0x41CA890 + +#define mmDCORE0_EDMA0_QM_CP_EXT_SWITCH 0x41CA894 + +#define mmDCORE0_EDMA0_QM_CP_SWITCH_WD_SET 0x41CA898 + +#define mmDCORE0_EDMA0_QM_CP_SWITCH_WD 0x41CA89C + +#define mmDCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_LO 0x41CA8A4 + +#define mmDCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_HI 0x41CA8A8 + +#define mmDCORE0_EDMA0_QM_ENGINE_BASE_ADDR_HI 0x41CA8AC + +#define mmDCORE0_EDMA0_QM_ENGINE_BASE_ADDR_LO 0x41CA8B0 + +#define mmDCORE0_EDMA0_QM_ENGINE_ADDR_RANGE_SIZE 0x41CA8B4 + +#define mmDCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI 0x41CA8B8 + +#define mmDCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO 0x41CA8BC + +#define mmDCORE0_EDMA0_QM_QM_BASE_ADDR_HI 0x41CA8C0 + +#define mmDCORE0_EDMA0_QM_QM_BASE_ADDR_LO 0x41CA8C4 + +#define mmDCORE0_EDMA0_QM_ARC_PQC_SECURE_PUSH_IND 0x41CA8C8 + +#define mmDCORE0_EDMA0_QM_PQC_STS_0_0 0x41CA8D0 + +#define mmDCORE0_EDMA0_QM_PQC_STS_0_1 0x41CA8D4 + +#define mmDCORE0_EDMA0_QM_PQC_STS_0_2 0x41CA8D8 + +#define mmDCORE0_EDMA0_QM_PQC_STS_0_3 0x41CA8DC + +#define mmDCORE0_EDMA0_QM_PQC_STS_1_0 0x41CA8E0 + +#define mmDCORE0_EDMA0_QM_PQC_STS_1_1 0x41CA8E4 + +#define mmDCORE0_EDMA0_QM_PQC_STS_1_2 0x41CA8E8 + +#define mmDCORE0_EDMA0_QM_PQC_STS_1_3 0x41CA8EC + +#define mmDCORE0_EDMA0_QM_SEI_STATUS 0x41CA8F0 + +#define mmDCORE0_EDMA0_QM_SEI_MASK 0x41CA8F4 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_ADDR_LO 0x41CAD00 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_ADDR_HI 0x41CAD04 + +#define mmDCORE0_EDMA0_QM_GLBL_ERR_WDATA 0x41CAD08 + +#define mmDCORE0_EDMA0_QM_L2H_MASK_LO 0x41CAD14 + +#define mmDCORE0_EDMA0_QM_L2H_MASK_HI 0x41CAD18 + +#define mmDCORE0_EDMA0_QM_L2H_CMPR_LO 0x41CAD1C + +#define mmDCORE0_EDMA0_QM_L2H_CMPR_HI 0x41CAD20 + +#define mmDCORE0_EDMA0_QM_LOCAL_RANGE_BASE 0x41CAD24 + +#define mmDCORE0_EDMA0_QM_LOCAL_RANGE_SIZE 0x41CAD28 + +#define mmDCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1 0x41CAD30 + +#define mmDCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0 0x41CAD34 + +#define mmDCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1 0x41CAD38 + +#define mmDCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0 0x41CAD3C + +#define mmDCORE0_EDMA0_QM_IND_GW_APB_CFG 0x41CAD40 + +#define mmDCORE0_EDMA0_QM_IND_GW_APB_WDATA 0x41CAD44 + +#define mmDCORE0_EDMA0_QM_IND_GW_APB_RDATA 0x41CAD48 + +#define mmDCORE0_EDMA0_QM_IND_GW_APB_STATUS 0x41CAD4C + +#define mmDCORE0_EDMA0_QM_PERF_CNT_FREE_LO 0x41CAD60 + +#define mmDCORE0_EDMA0_QM_PERF_CNT_FREE_HI 0x41CAD64 + +#define mmDCORE0_EDMA0_QM_PERF_CNT_IDLE_LO 0x41CAD68 + +#define mmDCORE0_EDMA0_QM_PERF_CNT_IDLE_HI 0x41CAD6C + +#define mmDCORE0_EDMA0_QM_PERF_CNT_CFG 0x41CAD70 + +#endif /* ASIC_REG_DCORE0_EDMA0_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma1_core_ctx_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma1_core_ctx_axuser_regs.h new file mode 100644 index 000000000000..b608a634562f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma1_core_ctx_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_EDMA1_CORE_CTX_AXUSER_REGS_H_ +#define ASIC_REG_DCORE0_EDMA1_CORE_CTX_AXUSER_REGS_H_ + +/* + ***************************************** + * DCORE0_EDMA1_CORE_CTX_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_ASID 0x41DB800 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_MMU_BP 0x41DB804 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_STRONG_ORDER 0x41DB808 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_NO_SNOOP 0x41DB80C + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_WR_REDUCTION 0x41DB810 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_RD_ATOMIC 0x41DB814 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_QOS 0x41DB818 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_RSVD 0x41DB81C + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_EMEM_CPAGE 0x41DB820 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_CORE 0x41DB824 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_E2E_COORD 0x41DB828 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_WR_OVRD_LO 0x41DB830 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_WR_OVRD_HI 0x41DB834 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_RD_OVRD_LO 0x41DB838 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_RD_OVRD_HI 0x41DB83C + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_LB_COORD 0x41DB840 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_LB_LOCK 0x41DB844 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_LB_RSVD 0x41DB848 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_LB_OVRD 0x41DB84C + +#endif /* ASIC_REG_DCORE0_EDMA1_CORE_CTX_AXUSER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma1_qm_axuser_nonsecured_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma1_qm_axuser_nonsecured_regs.h new file mode 100644 index 000000000000..c3a462f2a9ac --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma1_qm_axuser_nonsecured_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_EDMA1_QM_AXUSER_NONSECURED_REGS_H_ +#define ASIC_REG_DCORE0_EDMA1_QM_AXUSER_NONSECURED_REGS_H_ + +/* + ***************************************** + * DCORE0_EDMA1_QM_AXUSER_NONSECURED + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_ASID 0x41DAB80 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_MMU_BP 0x41DAB84 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x41DAB88 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x41DAB8C + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x41DAB90 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x41DAB94 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_QOS 0x41DAB98 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_RSVD 0x41DAB9C + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x41DABA0 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_CORE 0x41DABA4 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_E2E_COORD 0x41DABA8 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x41DABB0 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x41DABB4 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x41DABB8 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x41DABBC + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_LB_COORD 0x41DABC0 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_LB_LOCK 0x41DABC4 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_LB_RSVD 0x41DABC8 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_LB_OVRD 0x41DABCC + +#endif /* ASIC_REG_DCORE0_EDMA1_QM_AXUSER_NONSECURED_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_masks.h new file mode 100644 index 000000000000..df51eac10dd7 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_masks.h @@ -0,0 +1,294 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_HMMU0_MMU_MASKS_H_ +#define ASIC_REG_DCORE0_HMMU0_MMU_MASKS_H_ + +/* + ***************************************** + * DCORE0_HMMU0_MMU + * (Prototype: MMU) + ***************************************** + */ + +/* DCORE0_HMMU0_MMU_MMU_ENABLE */ +#define DCORE0_HMMU0_MMU_MMU_ENABLE_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_MMU_ENABLE_R_MASK 0x1 + +/* DCORE0_HMMU0_MMU_FORCE_ORDERING */ +#define DCORE0_HMMU0_MMU_FORCE_ORDERING_WEAK_ORDERING_SHIFT 0 +#define DCORE0_HMMU0_MMU_FORCE_ORDERING_WEAK_ORDERING_MASK 0x1 +#define DCORE0_HMMU0_MMU_FORCE_ORDERING_STRONG_ORDERING_SHIFT 1 +#define DCORE0_HMMU0_MMU_FORCE_ORDERING_STRONG_ORDERING_MASK 0x2 + +/* DCORE0_HMMU0_MMU_FEATURE_ENABLE */ +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_VA_ORDERING_EN_SHIFT 0 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_VA_ORDERING_EN_MASK 0x1 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_SHIFT 1 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_MASK 0x2 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_HOP_OFFSET_EN_SHIFT 2 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_HOP_OFFSET_EN_MASK 0x4 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_OBI_ORDERING_EN_SHIFT 3 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_OBI_ORDERING_EN_MASK 0x8 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_SHIFT 4 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_MASK 0x10 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_ENABLE_SHIFT 5 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_ENABLE_MASK 0x20 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_EV_MMU_OR_STLB_SHIFT 6 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_EV_MMU_OR_STLB_MASK 0x40 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_CLKH_EQUAL_CLKL_SHIFT 7 +#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_CLKH_EQUAL_CLKL_MASK 0x80 + +/* DCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7 */ +#define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7_R_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39 */ +#define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39_R_MASK 0x3FFFFFF + +/* DCORE0_HMMU0_MMU_LOG2_DDR_SIZE */ +#define DCORE0_HMMU0_MMU_LOG2_DDR_SIZE_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_LOG2_DDR_SIZE_R_MASK 0xFF + +/* DCORE0_HMMU0_MMU_SCRAMBLER */ +#define DCORE0_HMMU0_MMU_SCRAMBLER_ADDR_BIT_SHIFT 0 +#define DCORE0_HMMU0_MMU_SCRAMBLER_ADDR_BIT_MASK 0x3F +#define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_EN_SHIFT 6 +#define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_EN_MASK 0x40 +#define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_ID_SHIFT 7 +#define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_ID_MASK 0x80 +#define DCORE0_HMMU0_MMU_SCRAMBLER_DDR_CH_LSB_BIT_LOCATION_SHIFT 8 +#define DCORE0_HMMU0_MMU_SCRAMBLER_DDR_CH_LSB_BIT_LOCATION_MASK 0x7F00 + +/* DCORE0_HMMU0_MMU_MEM_INIT_BUSY */ +#define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_DATA_SHIFT 0 +#define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_DATA_MASK 0x3 +#define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI0_SHIFT 2 +#define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI0_MASK 0x4 +#define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI1_SHIFT 3 +#define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI1_MASK 0x8 + +/* DCORE0_HMMU0_MMU_SPI_SEI_MASK */ +#define DCORE0_HMMU0_MMU_SPI_SEI_MASK_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_SPI_SEI_MASK_R_MASK 0x7FFFF + +/* DCORE0_HMMU0_MMU_SPI_SEI_CAUSE */ +#define DCORE0_HMMU0_MMU_SPI_SEI_CAUSE_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_SPI_SEI_CAUSE_R_MASK 0x7FFFF + +/* DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE */ +#define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_63_32_SHIFT 0 +#define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_63_32_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA */ +#define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0 +#define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE */ +#define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_63_32_SHIFT 0 +#define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_63_32_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA */ +#define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0 +#define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID */ +#define DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_PAGE_ERR_VALID_ENTRY_SHIFT 0 +#define DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_PAGE_ERR_VALID_ENTRY_MASK 0x1 +#define DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_ACCESS_ERR_VALID_ENTRY_SHIFT 1 +#define DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_ACCESS_ERR_VALID_ENTRY_MASK 0x2 + +/* DCORE0_HMMU0_MMU_INTERRUPT_CLR */ +#define DCORE0_HMMU0_MMU_INTERRUPT_CLR_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_INTERRUPT_CLR_R_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_INTERRUPT_MASK */ +#define DCORE0_HMMU0_MMU_INTERRUPT_MASK_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_INTERRUPT_MASK_R_MASK 0xFF + +/* DCORE0_HMMU0_MMU_DBG_MEM_WRAP_RM */ +#define DCORE0_HMMU0_MMU_DBG_MEM_WRAP_RM_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_DBG_MEM_WRAP_RM_R_MASK 0x3FFFFFFF + +/* DCORE0_HMMU0_MMU_SPI_CAUSE_CLR */ +#define DCORE0_HMMU0_MMU_SPI_CAUSE_CLR_CLR_SHIFT 0 +#define DCORE0_HMMU0_MMU_SPI_CAUSE_CLR_CLR_MASK 0x1 + +/* DCORE0_HMMU0_MMU_PIPE_CREDIT */ +#define DCORE0_HMMU0_MMU_PIPE_CREDIT_READ_CREDIT_SHIFT 0 +#define DCORE0_HMMU0_MMU_PIPE_CREDIT_READ_CREDIT_MASK 0xF +#define DCORE0_HMMU0_MMU_PIPE_CREDIT_READ_FORCE_FULL_SHIFT 7 +#define DCORE0_HMMU0_MMU_PIPE_CREDIT_READ_FORCE_FULL_MASK 0x80 +#define DCORE0_HMMU0_MMU_PIPE_CREDIT_WRITE_CREDIT_SHIFT 8 +#define DCORE0_HMMU0_MMU_PIPE_CREDIT_WRITE_CREDIT_MASK 0xF00 +#define DCORE0_HMMU0_MMU_PIPE_CREDIT_WRITE_FORCE_FULL_SHIFT 15 +#define DCORE0_HMMU0_MMU_PIPE_CREDIT_WRITE_FORCE_FULL_MASK 0x8000 + +/* DCORE0_HMMU0_MMU_MMU_BYPASS */ +#define DCORE0_HMMU0_MMU_MMU_BYPASS_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_MMU_BYPASS_R_MASK 0x1 + +/* DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE */ +#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP5_PAGE_SIZE_SHIFT 0 +#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP5_PAGE_SIZE_MASK 0xF +#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP4_PAGE_SIZE_SHIFT 4 +#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP4_PAGE_SIZE_MASK 0xF0 +#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP3_PAGE_SIZE_SHIFT 8 +#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP3_PAGE_SIZE_MASK 0xF00 +#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP2_PAGE_SIZE_SHIFT 12 +#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP2_PAGE_SIZE_MASK 0xF000 +#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP1_PAGE_SIZE_SHIFT 16 +#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP1_PAGE_SIZE_MASK 0xF0000 +#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_CFG_8_BITS_HOP_MODE_EN_SHIFT 20 +#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_CFG_8_BITS_HOP_MODE_EN_MASK \ +0x100000 + +/* DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG */ +#define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MASK_SHIFT 0 +#define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MASK_MASK 0x1FF +#define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MIN_SHIFT 10 +#define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MIN_MASK 0x7FC00 +#define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MAX_SHIFT 20 +#define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MAX_MASK 0x1FF00000 + +/* DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT */ +#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_WRITE_CRED_SHIFT 0 +#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_WRITE_CRED_MASK 0x1FF +#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_READ_CRED_SHIFT 9 +#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_READ_CRED_MASK 0x3FE00 +#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_TOTAL_SHIFT 18 +#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_TOTAL_MASK 0x7FC0000 +#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_WRITE_SHIFT 27 +#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_WRITE_MASK 0x8000000 +#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_READ_SHIFT 28 +#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_READ_MASK 0x10000000 +#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_TOTAL_SHIFT 29 +#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_TOTAL_MASK 0x20000000 + +/* DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT */ +#define DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT_TOTAL_SHIFT 18 +#define DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT_TOTAL_MASK 0x7FC0000 +#define DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT_FORCE_FULL_TOTAL_SHIFT 29 +#define DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT_FORCE_FULL_TOTAL_MASK 0x20000000 + +/* DCORE0_HMMU0_MMU_PAGE_FAULT_ID_LSB */ +#define DCORE0_HMMU0_MMU_PAGE_FAULT_ID_LSB_PAGE_FAULT_ID_31_0_SHIFT 0 +#define DCORE0_HMMU0_MMU_PAGE_FAULT_ID_LSB_PAGE_FAULT_ID_31_0_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_PAGE_FAULT_ID_MSB */ +#define DCORE0_HMMU0_MMU_PAGE_FAULT_ID_MSB_PAGE_FAULT_ID_42_32_SHIFT 0 +#define DCORE0_HMMU0_MMU_PAGE_FAULT_ID_MSB_PAGE_FAULT_ID_42_32_MASK 0x7FF + +/* DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_LSB */ +#define DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_LSB_PAGE_ACCESS_ID_31_0_SHIFT 0 +#define DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_LSB_PAGE_ACCESS_ID_31_0_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_MSB */ +#define DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_MSB_PAGE_ACCESS_ID_42_32_SHIFT 0 +#define DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_MSB_PAGE_ACCESS_ID_42_32_MASK 0x7FF + +/* DCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE */ +#define DCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE_ENABLE_SHIFT 0 +#define DCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE_ENABLE_MASK 0x1 + +/* DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32 */ +#define DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_SEC_MIN_63_32_SHIFT 0 +#define DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_SEC_MIN_63_32_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0 */ +#define DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_SEC_MIN_31_0_SHIFT 0 +#define DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_SEC_MIN_31_0_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32 */ +#define DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_SEC_MAX_63_32_SHIFT 0 +#define DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_SEC_MAX_63_32_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0 */ +#define DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_SEC_MAX_31_0_SHIFT 0 +#define DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_SEC_MAX_31_0_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32 */ +#define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_PRIV_MIN_63_32_SHIFT 0 +#define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_PRIV_MIN_63_32_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0 */ +#define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_PRIV_MIN_31_0_SHIFT 0 +#define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_PRIV_MIN_31_0_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32 */ +#define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_PRIV_MAX_63_32_SHIFT 0 +#define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_PRIV_MAX_63_32_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0 */ +#define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_PRIV_MAX_31_0_SHIFT 0 +#define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_PRIV_MAX_31_0_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32 */ +#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32_ILLEGAL_ADDR_63_32_SHIFT 0 +#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32_ILLEGAL_ADDR_63_32_MASK \ +0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0 */ +#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0_ILLEGAL_ADDR_31_0_SHIFT 0 +#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0_ILLEGAL_ADDR_31_0_MASK \ +0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32 */ +#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32_ILLEGAL_ADDR_63_32_SHIFT 0 +#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32_ILLEGAL_ADDR_63_32_MASK \ +0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0 */ +#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0_ILLEGAL_ADDR_31_0_SHIFT 0 +#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0_ILLEGAL_ADDR_31_0_MASK \ +0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_RAZWI_WRITE_VLD */ +#define DCORE0_HMMU0_MMU_RAZWI_WRITE_VLD_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_RAZWI_WRITE_VLD_R_MASK 0x1 + +/* DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_31_0 */ +#define DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_31_0_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_31_0_R_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_42_32 */ +#define DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_42_32_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_42_32_R_MASK 0x7FF + +/* DCORE0_HMMU0_MMU_RAZWI_READ_VLD */ +#define DCORE0_HMMU0_MMU_RAZWI_READ_VLD_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_RAZWI_READ_VLD_R_MASK 0x1 + +/* DCORE0_HMMU0_MMU_RAZWI_READ_ID_31_0 */ +#define DCORE0_HMMU0_MMU_RAZWI_READ_ID_31_0_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_RAZWI_READ_ID_31_0_R_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_RAZWI_READ_ID_42_32 */ +#define DCORE0_HMMU0_MMU_RAZWI_READ_ID_42_32_R_SHIFT 0 +#define DCORE0_HMMU0_MMU_RAZWI_READ_ID_42_32_R_MASK 0x7FF + +/* DCORE0_HMMU0_MMU_MMU_SRC_NUM */ +#define DCORE0_HMMU0_MMU_MMU_SRC_NUM_OVERRIDE_SRC_NUM_EN_SHIFT 0 +#define DCORE0_HMMU0_MMU_MMU_SRC_NUM_OVERRIDE_SRC_NUM_EN_MASK 0x1 +#define DCORE0_HMMU0_MMU_MMU_SRC_NUM_SRC_NUM_SHIFT 1 +#define DCORE0_HMMU0_MMU_MMU_SRC_NUM_SRC_NUM_MASK 0x1E + +/* DCORE0_HMMU0_MMU_RAZWI_ADDR_LSB */ +#define DCORE0_HMMU0_MMU_RAZWI_ADDR_LSB_ADDR_SHIFT 0 +#define DCORE0_HMMU0_MMU_RAZWI_ADDR_LSB_ADDR_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_MMU_RAZWI_ADDR_MSB */ +#define DCORE0_HMMU0_MMU_RAZWI_ADDR_MSB_ADDR_SHIFT 0 +#define DCORE0_HMMU0_MMU_RAZWI_ADDR_MSB_ADDR_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_DCORE0_HMMU0_MMU_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_regs.h new file mode 100644 index 000000000000..08ccd695ec89 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_regs.h @@ -0,0 +1,237 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_HMMU0_MMU_REGS_H_ +#define ASIC_REG_DCORE0_HMMU0_MMU_REGS_H_ + +/* + ***************************************** + * DCORE0_HMMU0_MMU + * (Prototype: MMU) + ***************************************** + */ + +#define mmDCORE0_HMMU0_MMU_MMU_ENABLE 0x408000C + +#define mmDCORE0_HMMU0_MMU_FORCE_ORDERING 0x4080010 + +#define mmDCORE0_HMMU0_MMU_FEATURE_ENABLE 0x4080014 + +#define mmDCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7 0x4080018 + +#define mmDCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39 0x408001C + +#define mmDCORE0_HMMU0_MMU_LOG2_DDR_SIZE 0x4080020 + +#define mmDCORE0_HMMU0_MMU_SCRAMBLER 0x4080024 + +#define mmDCORE0_HMMU0_MMU_MEM_INIT_BUSY 0x4080028 + +#define mmDCORE0_HMMU0_MMU_SPI_SEI_MASK 0x408002C + +#define mmDCORE0_HMMU0_MMU_SPI_SEI_CAUSE 0x4080030 + +#define mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE 0x4080034 + +#define mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA 0x4080038 + +#define mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE 0x408003C + +#define mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA 0x4080040 + +#define mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID 0x4080044 + +#define mmDCORE0_HMMU0_MMU_INTERRUPT_CLR 0x4080048 + +#define mmDCORE0_HMMU0_MMU_INTERRUPT_MASK 0x408004C + +#define mmDCORE0_HMMU0_MMU_DBG_MEM_WRAP_RM 0x4080050 + +#define mmDCORE0_HMMU0_MMU_SPI_CAUSE_CLR 0x4080054 + +#define mmDCORE0_HMMU0_MMU_PIPE_CREDIT 0x4080058 + +#define mmDCORE0_HMMU0_MMU_MMU_BYPASS 0x408006C + +#define mmDCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE 0x4080070 + +#define mmDCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG 0x40800A0 + +#define mmDCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT 0x40800D0 + +#define mmDCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT 0x40800F4 + +#define mmDCORE0_HMMU0_MMU_PAGE_FAULT_ID_LSB 0x40800F8 + +#define mmDCORE0_HMMU0_MMU_PAGE_FAULT_ID_MSB 0x40800FC + +#define mmDCORE0_HMMU0_MMU_PAGE_ACCESS_ID_LSB 0x4080100 + +#define mmDCORE0_HMMU0_MMU_PAGE_ACCESS_ID_MSB 0x4080104 + +#define mmDCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE 0x4080108 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_0 0x4080110 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_1 0x4080114 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_2 0x4080118 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_3 0x408011C + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_4 0x4080120 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_5 0x4080124 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_6 0x4080128 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_7 0x408012C + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_0 0x4080140 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_1 0x4080144 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_2 0x4080148 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_3 0x408014C + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_4 0x4080150 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_5 0x4080154 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_6 0x4080158 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_7 0x408015C + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_0 0x4080170 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_1 0x4080174 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_2 0x4080178 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_3 0x408017C + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_4 0x4080180 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_5 0x4080184 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_6 0x4080188 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_7 0x408018C + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_0 0x40801A0 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_1 0x40801A4 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_2 0x40801A8 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_3 0x40801AC + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_4 0x40801B0 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_5 0x40801B4 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_6 0x40801B8 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_7 0x40801BC + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_0 0x40801D0 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_1 0x40801D4 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_2 0x40801D8 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_3 0x40801DC + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_4 0x40801E0 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_5 0x40801E4 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_6 0x40801E8 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_7 0x40801EC + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_0 0x4080200 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_1 0x4080204 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_2 0x4080208 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_3 0x408020C + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_4 0x4080210 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_5 0x4080214 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_6 0x4080218 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_7 0x408021C + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_0 0x4080230 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_1 0x4080234 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_2 0x4080238 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_3 0x408023C + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_4 0x4080240 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_5 0x4080244 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_6 0x4080248 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_7 0x408024C + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_0 0x4080260 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_1 0x4080264 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_2 0x4080268 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_3 0x408026C + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_4 0x4080270 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_5 0x4080274 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_6 0x4080278 + +#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_7 0x408027C + +#define mmDCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32 0x4080290 + +#define mmDCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0 0x4080294 + +#define mmDCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32 0x4080298 + +#define mmDCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0 0x408029C + +#define mmDCORE0_HMMU0_MMU_RAZWI_WRITE_VLD 0x4080300 + +#define mmDCORE0_HMMU0_MMU_RAZWI_WRITE_ID_31_0 0x4080304 + +#define mmDCORE0_HMMU0_MMU_RAZWI_WRITE_ID_42_32 0x4080308 + +#define mmDCORE0_HMMU0_MMU_RAZWI_READ_VLD 0x408030C + +#define mmDCORE0_HMMU0_MMU_RAZWI_READ_ID_31_0 0x4080310 + +#define mmDCORE0_HMMU0_MMU_RAZWI_READ_ID_42_32 0x4080314 + +#define mmDCORE0_HMMU0_MMU_MMU_SRC_NUM 0x408031C + +#define mmDCORE0_HMMU0_MMU_RAZWI_ADDR_LSB 0x4080320 + +#define mmDCORE0_HMMU0_MMU_RAZWI_ADDR_MSB 0x4080324 + +#endif /* ASIC_REG_DCORE0_HMMU0_MMU_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_masks.h new file mode 100644 index 000000000000..192eba5f07bb --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_masks.h @@ -0,0 +1,348 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_HMMU0_STLB_MASKS_H_ +#define ASIC_REG_DCORE0_HMMU0_STLB_MASKS_H_ + +/* + ***************************************** + * DCORE0_HMMU0_STLB + * (Prototype: STLB) + ***************************************** + */ + +/* DCORE0_HMMU0_STLB_BUSY */ +#define DCORE0_HMMU0_STLB_BUSY_BUSY_SHIFT 0 +#define DCORE0_HMMU0_STLB_BUSY_BUSY_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_STLB_ASID */ +#define DCORE0_HMMU0_STLB_ASID_ASID_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_ASID_MASK 0x3FF + +/* DCORE0_HMMU0_STLB_HOP0_PA43_12 */ +#define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_SHIFT 0 +#define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_STLB_HOP0_PA63_44 */ +#define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_SHIFT 0 +#define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_MASK 0xFFFFF + +/* DCORE0_HMMU0_STLB_CACHE_INV */ +#define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0 +#define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF +#define DCORE0_HMMU0_STLB_CACHE_INV_INDEX_MASK_SHIFT 8 +#define DCORE0_HMMU0_STLB_CACHE_INV_INDEX_MASK_MASK 0xFF00 + +/* DCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8 */ +#define DCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8_PA_SHIFT 0 +#define DCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8_PA_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40 */ +#define DCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40_PA_SHIFT 0 +#define DCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40_PA_MASK 0xFFFFFF + +/* DCORE0_HMMU0_STLB_STLB_FEATURE_EN */ +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_SHIFT 0 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_MASK 0x1 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_SHIFT 1 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_MASK 0x2 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_LOOKUP_EN_SHIFT 2 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_LOOKUP_EN_MASK 0x4 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BYPASS_SHIFT 3 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BYPASS_MASK 0x8 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BANK_STOP_SHIFT 4 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BANK_STOP_MASK 0x10 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_TRACE_EN_SHIFT 5 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_TRACE_EN_MASK 0x20 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWER_EN_SHIFT 6 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK 0x40 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_CACHING_EN_SHIFT 7 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_CACHING_EN_MASK 0x1F80 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWING_NUM_LIMIT_SHIFT 13 +#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWING_NUM_LIMIT_MASK 0xE000 + +/* DCORE0_HMMU0_STLB_STLB_AXI_CACHE */ +#define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_SHIFT 0 +#define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_MASK 0xF +#define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_SHIFT 4 +#define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_MASK 0xF0 +#define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_INV_ARCACHE_SHIFT 8 +#define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_INV_ARCACHE_MASK 0xF00 + +/* DCORE0_HMMU0_STLB_HOP_CONFIGURATION */ +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_HOP_SHIFT 0 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_HOP_MASK 0x7 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_SHIFT 4 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_MASK 0x70 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_SHIFT 8 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_MASK 0x700 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LAST_HOP_SHIFT 12 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LAST_HOP_MASK 0x7000 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_SHIFT 16 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_MASK 0x70000 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_SHIFT 20 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_MASK 0x100000 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_SHIFT 21 +#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_MASK \ +0x7E00000 + +/* DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32 */ +#define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_SHIFT 0 +#define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0 */ +#define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0_R_SHIFT 0 +#define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0_R_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_STLB_INV_ALL_START */ +#define DCORE0_HMMU0_STLB_INV_ALL_START_R_SHIFT 0 +#define DCORE0_HMMU0_STLB_INV_ALL_START_R_MASK 0x1 + +/* DCORE0_HMMU0_STLB_INV_ALL_SET */ +#define DCORE0_HMMU0_STLB_INV_ALL_SET_R_SHIFT 0 +#define DCORE0_HMMU0_STLB_INV_ALL_SET_R_MASK 0xFF + +/* DCORE0_HMMU0_STLB_INV_PS */ +#define DCORE0_HMMU0_STLB_INV_PS_R_SHIFT 0 +#define DCORE0_HMMU0_STLB_INV_PS_R_MASK 0x3 + +/* DCORE0_HMMU0_STLB_INV_CONSUMER_INDEX */ +#define DCORE0_HMMU0_STLB_INV_CONSUMER_INDEX_R_SHIFT 0 +#define DCORE0_HMMU0_STLB_INV_CONSUMER_INDEX_R_MASK 0xFF + +/* DCORE0_HMMU0_STLB_INV_HIT_COUNT */ +#define DCORE0_HMMU0_STLB_INV_HIT_COUNT_R_SHIFT 0 +#define DCORE0_HMMU0_STLB_INV_HIT_COUNT_R_MASK 0x7FF + +/* DCORE0_HMMU0_STLB_INV_SET */ +#define DCORE0_HMMU0_STLB_INV_SET_R_SHIFT 0 +#define DCORE0_HMMU0_STLB_INV_SET_R_MASK 0xFF + +/* DCORE0_HMMU0_STLB_SRAM_INIT */ +#define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_TAG_SHIFT 0 +#define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_TAG_MASK 0x3 +#define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_SLICE_SHIFT 2 +#define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_SLICE_MASK 0xC +#define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_DATA_SHIFT 4 +#define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_DATA_MASK 0x10 + +/* DCORE0_HMMU0_STLB_MEM_CACHE_INVALIDATION */ + +/* DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS */ +#define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_INVALIDATE_DONE_SHIFT 0 +#define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_INVALIDATE_DONE_MASK 0x1 +#define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_CACHE_IDLE_SHIFT 1 +#define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_CACHE_IDLE_MASK 0x2 + +/* DCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7 */ +#define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7_R_SHIFT 0 +#define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7_R_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39 */ +#define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39_R_SHIFT 0 +#define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39_R_MASK 0x1FFFFFF + +/* DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG */ +#define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_EN_SHIFT 0 +#define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_EN_MASK 0x3F +#define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_PREFETCH_EN_SHIFT 6 +#define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_PREFETCH_EN_MASK 0xFC0 +#define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_BYPASS_EN_SHIFT 12 +#define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_BYPASS_EN_MASK 0x1000 +#define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_RELEASE_INVALIDATE_SHIFT 13 +#define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_RELEASE_INVALIDATE_MASK 0x2000 + +/* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5 */ +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MIN_SHIFT 0 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MIN_MASK 0x1FF +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MAX_SHIFT 9 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MAX_MASK 0x3FE00 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MASK_SHIFT 18 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MASK_MASK 0x7FC0000 + +/* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4 */ +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MIN_SHIFT 0 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MIN_MASK 0x1FF +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MAX_SHIFT 9 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MAX_MASK 0x3FE00 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MASK_SHIFT 18 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MASK_MASK 0x7FC0000 + +/* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3 */ +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MIN_SHIFT 0 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MIN_MASK 0x1FF +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MAX_SHIFT 9 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MAX_MASK 0x3FE00 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MASK_SHIFT 18 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MASK_MASK 0x7FC0000 + +/* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2 */ +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MIN_SHIFT 0 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MIN_MASK 0x1FF +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MAX_SHIFT 9 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MAX_MASK 0x3FE00 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MASK_SHIFT 18 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MASK_MASK 0x7FC0000 + +/* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1 */ +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MIN_SHIFT 0 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MIN_MASK 0x1FF +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MAX_SHIFT 9 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MAX_MASK 0x3FE00 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MASK_SHIFT 18 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MASK_MASK 0x7FC0000 + +/* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0 */ +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MIN_SHIFT 0 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MIN_MASK 0x1FF +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MAX_SHIFT 9 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MAX_MASK 0x3FE00 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MASK_SHIFT 18 +#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MASK_MASK 0x7FC0000 + +/* DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_CLR */ + +/* DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK */ +#define DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK_R_SHIFT 0 +#define DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK_R_MASK 0x1 + +/* DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG */ +#define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_PLRU_EVICTION_SHIFT 0 +#define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_PLRU_EVICTION_MASK 0x1 +#define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_CACHE_STOP_SHIFT 1 +#define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_CACHE_STOP_MASK 0x2 +#define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_INV_WRITEBACK_SHIFT 2 +#define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_INV_WRITEBACK_MASK 0x4 + +/* DCORE0_HMMU0_STLB_MEM_READ_ARPROT */ +#define DCORE0_HMMU0_STLB_MEM_READ_ARPROT_R_SHIFT 0 +#define DCORE0_HMMU0_STLB_MEM_READ_ARPROT_R_MASK 0x7 + +/* DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION */ +#define \ +DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_SHIFT \ +0 +#define \ +DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_MASK \ +0x1 +#define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_SHIFT 1 +#define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_MASK 0x2 +#define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_SHIFT 2 +#define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_MASK 0xFFC + +/* DCORE0_HMMU0_STLB_RANGE_INV_START_LSB */ +#define DCORE0_HMMU0_STLB_RANGE_INV_START_LSB_INV_START_LSB_SHIFT 0 +#define DCORE0_HMMU0_STLB_RANGE_INV_START_LSB_INV_START_LSB_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_STLB_RANGE_INV_START_MSB */ +#define DCORE0_HMMU0_STLB_RANGE_INV_START_MSB_INV_START_MSB_SHIFT 0 +#define DCORE0_HMMU0_STLB_RANGE_INV_START_MSB_INV_START_MSB_MASK 0xFFFFF + +/* DCORE0_HMMU0_STLB_RANGE_INV_END_LSB */ +#define DCORE0_HMMU0_STLB_RANGE_INV_END_LSB_INV_END_LSB_SHIFT 0 +#define DCORE0_HMMU0_STLB_RANGE_INV_END_LSB_INV_END_LSB_MASK 0xFFFFFFFF + +/* DCORE0_HMMU0_STLB_RANGE_INV_END_MSB */ +#define DCORE0_HMMU0_STLB_RANGE_INV_END_MSB_INV_END_MSB_SHIFT 0 +#define DCORE0_HMMU0_STLB_RANGE_INV_END_MSB_INV_END_MSB_MASK 0xFFFFF + +/* DCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL */ +#define DCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL_SCRAMBLER_SCRAM_EN_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL_SCRAMBLER_SCRAM_EN_MASK 0x1 + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_MASK \ +0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_MASK \ +0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_MASK \ +0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_MASK \ +0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_MASK \ +0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_MASK \ +0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_MASK \ +0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_MASK \ +0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_MASK \ +0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_MASK \ +0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18 */ +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18_ASID_POLY_MATRIX_H3_SHIFT 0 +#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18_ASID_POLY_MATRIX_H3_MASK 0x1FF + +#endif /* ASIC_REG_DCORE0_HMMU0_STLB_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_regs.h new file mode 100644 index 000000000000..864a259f68e2 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_regs.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_HMMU0_STLB_REGS_H_ +#define ASIC_REG_DCORE0_HMMU0_STLB_REGS_H_ + +/* + ***************************************** + * DCORE0_HMMU0_STLB + * (Prototype: STLB) + ***************************************** + */ + +#define mmDCORE0_HMMU0_STLB_BUSY 0x4081000 + +#define mmDCORE0_HMMU0_STLB_ASID 0x4081004 + +#define mmDCORE0_HMMU0_STLB_HOP0_PA43_12 0x4081008 + +#define mmDCORE0_HMMU0_STLB_HOP0_PA63_44 0x408100C + +#define mmDCORE0_HMMU0_STLB_CACHE_INV 0x4081010 + +#define mmDCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8 0x4081014 + +#define mmDCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40 0x4081018 + +#define mmDCORE0_HMMU0_STLB_STLB_FEATURE_EN 0x408101C + +#define mmDCORE0_HMMU0_STLB_STLB_AXI_CACHE 0x4081020 + +#define mmDCORE0_HMMU0_STLB_HOP_CONFIGURATION 0x4081024 + +#define mmDCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32 0x4081028 + +#define mmDCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0 0x408102C + +#define mmDCORE0_HMMU0_STLB_INV_ALL_START 0x4081034 + +#define mmDCORE0_HMMU0_STLB_INV_ALL_SET 0x4081038 + +#define mmDCORE0_HMMU0_STLB_INV_PS 0x408103C + +#define mmDCORE0_HMMU0_STLB_INV_CONSUMER_INDEX 0x4081040 + +#define mmDCORE0_HMMU0_STLB_INV_HIT_COUNT 0x4081044 + +#define mmDCORE0_HMMU0_STLB_INV_SET 0x4081048 + +#define mmDCORE0_HMMU0_STLB_SRAM_INIT 0x408104C + +#define mmDCORE0_HMMU0_STLB_MEM_CACHE_INVALIDATION 0x4081050 + +#define mmDCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS 0x4081054 + +#define mmDCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7 0x4081058 + +#define mmDCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39 0x408105C + +#define mmDCORE0_HMMU0_STLB_MEM_CACHE_CONFIG 0x4081060 + +#define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5 0x4081064 + +#define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4 0x4081068 + +#define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3 0x408106C + +#define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2 0x4081070 + +#define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1 0x4081074 + +#define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0 0x4081078 + +#define mmDCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_CLR 0x408107C + +#define mmDCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK 0x4081080 + +#define mmDCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG 0x4081084 + +#define mmDCORE0_HMMU0_STLB_MEM_READ_ARPROT 0x4081088 + +#define mmDCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION 0x408108C + +#define mmDCORE0_HMMU0_STLB_RANGE_INV_START_LSB 0x4081090 + +#define mmDCORE0_HMMU0_STLB_RANGE_INV_START_MSB 0x4081094 + +#define mmDCORE0_HMMU0_STLB_RANGE_INV_END_LSB 0x4081098 + +#define mmDCORE0_HMMU0_STLB_RANGE_INV_END_MSB 0x408109C + +#define mmDCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL 0x4081100 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0 0x4081104 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1 0x4081108 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2 0x408110C + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3 0x4081110 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4 0x4081114 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5 0x4081118 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6 0x408111C + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7 0x4081120 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8 0x4081124 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9 0x4081128 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10 0x408112C + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11 0x4081130 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12 0x4081134 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13 0x4081138 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14 0x408113C + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15 0x4081140 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16 0x4081144 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17 0x4081148 + +#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18 0x408114C + +#endif /* ASIC_REG_DCORE0_HMMU0_STLB_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_acc_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_acc_regs.h new file mode 100644 index 000000000000..07bed3ec740e --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_acc_regs.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_ACC_REGS_H_ +#define ASIC_REG_DCORE0_MME_ACC_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_ACC + * (Prototype: ACC) + ***************************************** + */ + +#define mmDCORE0_MME_ACC_WBC0_AXI 0x40F8000 + +#define mmDCORE0_MME_ACC_WBC1_AXI 0x40F8004 + +#define mmDCORE0_MME_ACC_WBC0_RL 0x40F8008 + +#define mmDCORE0_MME_ACC_WBC1_RL 0x40F800C + +#define mmDCORE0_MME_ACC_WBC_STALL 0x40F8010 + +#define mmDCORE0_MME_ACC_AWCACHE 0x40F8014 + +#define mmDCORE0_MME_ACC_AWPROT 0x40F8018 + +#define mmDCORE0_MME_ACC_AP_LFSR_POLY 0x40F801C + +#define mmDCORE0_MME_ACC_AP_LFSR_SEED_WDATA 0x40F8020 + +#define mmDCORE0_MME_ACC_AP_LFSR_SEED_SEL 0x40F8024 + +#define mmDCORE0_MME_ACC_AP_LFSR_SEED_RDATA 0x40F8028 + +#define mmDCORE0_MME_ACC_AP_LFSR_CLOSE_CGATE_DLY 0x40F802C + +#define mmDCORE0_MME_ACC_WBC_SRC_BP 0x40F8030 + +#define mmDCORE0_MME_ACC_CLK_GATE_EN 0x40F8034 + +#define mmDCORE0_MME_ACC_WBC_INFLIGHTS 0x40F8038 + +#define mmDCORE0_MME_ACC_HBW_CLK_ENABLER_DIS 0x40F803C + +#define mmDCORE0_MME_ACC_E2E_CRDT_TOP0 0x40F8040 + +#define mmDCORE0_MME_ACC_E2E_CRDT_TOP1 0x40F8044 + +#define mmDCORE0_MME_ACC_INTR_CAUSE 0x40F8048 + +#define mmDCORE0_MME_ACC_INTR_MASK 0x40F804C + +#define mmDCORE0_MME_ACC_INTR_CLEAR 0x40F8050 + +#define mmDCORE0_MME_ACC_WR_AXI_AGG_COUT0 0x40F8054 + +#define mmDCORE0_MME_ACC_WR_AXI_AGG_COUT1 0x40F8058 + +#define mmDCORE0_MME_ACC_BIST 0x40F805C + +#define mmDCORE0_MME_ACC_WR_AXI_AGG_2P_BVALID 0x40F8060 + +#endif /* ASIC_REG_DCORE0_MME_ACC_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout0_master_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout0_master_regs.h new file mode 100644 index 000000000000..c9043979fd69 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout0_master_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_0 0x40CB22C + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_1 0x40CB230 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_2 0x40CB234 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_3 0x40CB238 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_4 0x40CB23C + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout0_slave_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout0_slave_regs.h new file mode 100644 index 000000000000..7d74aea4576f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout0_slave_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_0 0x40CB240 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_1 0x40CB244 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_2 0x40CB248 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_3 0x40CB24C + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_4 0x40CB250 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout1_master_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout1_master_regs.h new file mode 100644 index 000000000000..f6f519eb5f6f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout1_master_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_0 0x40CB254 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_1 0x40CB258 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_2 0x40CB25C + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_3 0x40CB260 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_4 0x40CB264 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout1_slave_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout1_slave_regs.h new file mode 100644 index 000000000000..0e0c056ade9b --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout1_slave_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_0 0x40CB268 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_1 0x40CB26C + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_2 0x40CB270 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_3 0x40CB274 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_4 0x40CB278 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in0_master_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in0_master_regs.h new file mode 100644 index 000000000000..34c6134a2f93 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in0_master_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_0 0x40CB15C + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_1 0x40CB160 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_2 0x40CB164 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_3 0x40CB168 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_4 0x40CB16C + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in0_slave_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in0_slave_regs.h new file mode 100644 index 000000000000..55065032f87c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in0_slave_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_0 0x40CB170 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_1 0x40CB174 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_2 0x40CB178 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_3 0x40CB17C + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_4 0x40CB180 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in1_master_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in1_master_regs.h new file mode 100644 index 000000000000..6022b387eacf --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in1_master_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_0 0x40CB184 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_1 0x40CB188 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_2 0x40CB18C + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_3 0x40CB190 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_4 0x40CB194 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in1_slave_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in1_slave_regs.h new file mode 100644 index 000000000000..f9c9b01f0d1a --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in1_slave_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_0 0x40CB198 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_1 0x40CB19C + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_2 0x40CB1A0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_3 0x40CB1A4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_4 0x40CB1A8 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in2_master_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in2_master_regs.h new file mode 100644 index 000000000000..d96119b8c435 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in2_master_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_0 0x40CB1AC + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_1 0x40CB1B0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_2 0x40CB1B4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_3 0x40CB1B8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_4 0x40CB1BC + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in2_slave_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in2_slave_regs.h new file mode 100644 index 000000000000..c80d6817efe1 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in2_slave_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_0 0x40CB1C0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_1 0x40CB1C4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_2 0x40CB1C8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_3 0x40CB1CC + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_4 0x40CB1D0 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in3_master_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in3_master_regs.h new file mode 100644 index 000000000000..753b31dc1760 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in3_master_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_0 0x40CB1D4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_1 0x40CB1D8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_2 0x40CB1DC + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_3 0x40CB1E0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_4 0x40CB1E4 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in3_slave_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in3_slave_regs.h new file mode 100644 index 000000000000..f68d043edcd9 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in3_slave_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_0 0x40CB1E8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_1 0x40CB1EC + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_2 0x40CB1F0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_3 0x40CB1F4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_4 0x40CB1F8 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_master_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_master_regs.h new file mode 100644 index 000000000000..a6dce326bd74 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_master_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_0 0x40CB1FC + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_1 0x40CB200 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_2 0x40CB204 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_3 0x40CB208 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_4 0x40CB20C + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h new file mode 100644 index 000000000000..5ace0f43cc78 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_0 0x40CB210 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_1 0x40CB214 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_2 0x40CB218 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_3 0x40CB21C + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_4 0x40CB220 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_base_addr_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_base_addr_regs.h new file mode 100644 index 000000000000..b375393dfdc0 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_base_addr_regs.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR + * (Prototype: MME_ADDRESS_DESCRIPTOR) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_LOW 0x40CB008 + +#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_HIGH 0x40CB00C + +#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_LOW 0x40CB010 + +#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_HIGH 0x40CB014 + +#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_LOW 0x40CB018 + +#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_HIGH 0x40CB01C + +#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_LOW 0x40CB020 + +#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_HIGH 0x40CB024 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h new file mode 100644 index 000000000000..7c22b9383f3c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END + * (Prototype: MME_NON_TENSOR_DESCRIPTOR) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_KERNEL_SIZE_MINUS_1 \ +0x40CB280 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_LOW 0x40CB284 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_HIGH 0x40CB288 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_OUTER_LOOP 0x40CB28C + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_NUM_ITERATIONS_MINUS_1 \ +0x40CB290 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SB_REPEAT 0x40CB294 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_FP8_BIAS 0x40CB298 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_RATE_LIMITER 0x40CB29C + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_USER_DATA 0x40CB2A0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_IN 0x40CB2A4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_OUT 0x40CB2A8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PCU 0x40CB2AC + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ0_ADDR 0x40CB2B0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ1_ADDR 0x40CB2B4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_POWER_LOOP 0x40CB2B8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_MASTER 0x40CB2BC + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_MASTER 0x40CB2C0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_MASTER 0x40CB2C4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_MASTER 0x40CB2C8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_SLAVE 0x40CB2CC + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_SLAVE 0x40CB2D0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_SLAVE 0x40CB2D4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_SLAVE 0x40CB2D8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_WKL_ID 0x40CB2DC + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_start_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_start_regs.h new file mode 100644 index 000000000000..d17c165faf8b --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_start_regs.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START + * (Prototype: MME_NON_TENSOR_DESCRIPTOR_START) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_LOW 0x40CB028 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_HIGH 0x40CB02C + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_LOW 0x40CB030 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_HIGH 0x40CB034 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_MASTER 0x40CB038 + +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_SLAVE 0x40CB03C + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_a_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_a_regs.h new file mode 100644 index 000000000000..7b77884e0024 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_a_regs.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_TENSOR_A + * (Prototype: MME_TENSOR) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_0 0x40CB040 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_1 0x40CB044 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_2 0x40CB048 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_3 0x40CB04C + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_4 0x40CB050 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_0 0x40CB054 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_1 0x40CB058 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_2 0x40CB05C + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_3 0x40CB060 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_4 0x40CB064 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_0 0x40CB068 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_1 0x40CB06C + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_2 0x40CB070 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_3 0x40CB074 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_0 0x40CB078 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_1 0x40CB07C + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_2 0x40CB080 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_3 0x40CB084 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_0 0x40CB088 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_1 0x40CB08C + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_2 0x40CB090 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_3 0x40CB094 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_b_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_b_regs.h new file mode 100644 index 000000000000..a2a2ba454d6d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_b_regs.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_TENSOR_B + * (Prototype: MME_TENSOR) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_0 0x40CB098 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_1 0x40CB09C + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_2 0x40CB0A0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_3 0x40CB0A4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_4 0x40CB0A8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_0 0x40CB0AC + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_1 0x40CB0B0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_2 0x40CB0B4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_3 0x40CB0B8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_4 0x40CB0BC + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_0 0x40CB0C0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_1 0x40CB0C4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_2 0x40CB0C8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_3 0x40CB0CC + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_0 0x40CB0D0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_1 0x40CB0D4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_2 0x40CB0D8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_3 0x40CB0DC + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_0 0x40CB0E0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_1 0x40CB0E4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_2 0x40CB0E8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_3 0x40CB0EC + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_cout_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_cout_regs.h new file mode 100644 index 000000000000..7ad7b197cf87 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_cout_regs.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT + * (Prototype: MME_TENSOR) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_0 0x40CB0F0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_1 0x40CB0F4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_2 0x40CB0F8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_3 0x40CB0FC + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_4 0x40CB100 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_0 0x40CB104 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_1 0x40CB108 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_2 0x40CB10C + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_3 0x40CB110 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_4 0x40CB114 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_0 0x40CB118 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_1 0x40CB11C + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_2 0x40CB120 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_3 0x40CB124 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_0 0x40CB128 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_1 0x40CB12C + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_2 0x40CB130 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_3 0x40CB134 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_0 0x40CB138 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_1 0x40CB13C + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_2 0x40CB140 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_3 0x40CB144 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_masks.h new file mode 100644 index 000000000000..f699661d76aa --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_masks.h @@ -0,0 +1,468 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_MASKS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_MASKS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO + * (Prototype: MME_CTRL_LO) + ***************************************** + */ + +/* DCORE0_MME_CTRL_LO_ARCH_STATUS */ +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_SHIFT 0 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_MASK 0x1F +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_EU_SHIFT 5 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_EU_MASK 0x20 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_AP_SHIFT 6 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_AP_MASK 0x40 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SHIFT 7 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_MASK 0x180 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_SHIFT 9 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_MASK 0x3E00 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_SHIFT 14 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_MASK 0xC000 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_SHIFT 16 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_MASK 0x30000 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_SHIFT 18 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_MASK 0x7C0000 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_ACCUM_FREE_SHIFT 23 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_ACCUM_FREE_MASK 0x3800000 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_IDLE_SHIFT 30 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_IDLE_MASK 0x40000000 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_RDY_SHIFT 31 +#define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_RDY_MASK 0x80000000 + +/* DCORE0_MME_CTRL_LO_CMD */ +#define DCORE0_MME_CTRL_LO_CMD_AGU_IN_SHIFT 0 +#define DCORE0_MME_CTRL_LO_CMD_AGU_IN_MASK 0x1F +#define DCORE0_MME_CTRL_LO_CMD_EU_SHIFT 5 +#define DCORE0_MME_CTRL_LO_CMD_EU_MASK 0x20 +#define DCORE0_MME_CTRL_LO_CMD_AP_SHIFT 6 +#define DCORE0_MME_CTRL_LO_CMD_AP_MASK 0x40 +#define DCORE0_MME_CTRL_LO_CMD_AGU_COUT_SHIFT 7 +#define DCORE0_MME_CTRL_LO_CMD_AGU_COUT_MASK 0x180 +#define DCORE0_MME_CTRL_LO_CMD_COPY_AND_INC_SHIFT 9 +#define DCORE0_MME_CTRL_LO_CMD_COPY_AND_INC_MASK 0x200 +#define DCORE0_MME_CTRL_LO_CMD_DESC_SEL_SHIFT 10 +#define DCORE0_MME_CTRL_LO_CMD_DESC_SEL_MASK 0xC00 +#define DCORE0_MME_CTRL_LO_CMD_MASK_IDLE_IND_SHIFT 12 +#define DCORE0_MME_CTRL_LO_CMD_MASK_IDLE_IND_MASK 0x1000 +#define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW0_SHIFT 13 +#define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW0_MASK 0x2000 +#define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW1_4_SHIFT 14 +#define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW1_4_MASK 0x4000 +#define DCORE0_MME_CTRL_LO_CMD_NULL_DESC_SHIFT 15 +#define DCORE0_MME_CTRL_LO_CMD_NULL_DESC_MASK 0x8000 + +/* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0 */ +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK0_SHIFT 0 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK0_MASK 0x3F +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN0_SHIFT 6 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN0_MASK 0x40 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK1_SHIFT 8 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK1_MASK 0x3F00 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN1_SHIFT 14 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN1_MASK 0x4000 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_MASTER_WAIT_SLAVE_FENCE_SHIFT 15 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_MASTER_WAIT_SLAVE_FENCE_MASK 0x8000 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SEND_FENCE2MASTER_SHIFT 16 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SEND_FENCE2MASTER_MASK \ +0x10000 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SIGNAL_EN_SHIFT 17 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SIGNAL_EN_MASK 0x20000 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_SLV_ADR_SHIFT 18 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_SLV_ADR_MASK 0x40000 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_SLV_ADR_SHIFT 19 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_SLV_ADR_MASK 0x80000 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_MSTR_ADR_PLUS4_SHIFT 20 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_MSTR_ADR_PLUS4_MASK \ +0x100000 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_MSTR_ADR_PLUS4_SHIFT 21 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_MSTR_ADR_PLUS4_MASK \ +0x200000 + +/* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0 */ +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0_V_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0 */ +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_VALUE_SHIFT 0 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_VALUE_MASK 0x7FFF +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_RESERVED_SHIFT 15 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_RESERVED_MASK 0x3FFF8000 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_PERF_EN_SHIFT 30 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_PERF_EN_MASK 0x40000000 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_OP_SHIFT 31 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_OP_MASK 0x80000000 + +/* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1 */ +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1_V_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1 */ +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_VALUE_SHIFT 0 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_VALUE_MASK 0x7FFF +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_RESERVED_SHIFT 15 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_RESERVED_MASK 0x3FFF8000 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_PERF_EN_SHIFT 30 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_PERF_EN_MASK 0x40000000 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_OP_SHIFT 31 +#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_OP_MASK 0x80000000 + +/* DCORE0_MME_CTRL_LO_ARCH_A_SS */ +#define DCORE0_MME_CTRL_LO_ARCH_A_SS_MINUS_1_SHIFT 0 +#define DCORE0_MME_CTRL_LO_ARCH_A_SS_MINUS_1_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_ARCH_B_SS */ +#define DCORE0_MME_CTRL_LO_ARCH_B_SS_MINUS_1_SHIFT 0 +#define DCORE0_MME_CTRL_LO_ARCH_B_SS_MINUS_1_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_ARCH_COUT_SS */ +#define DCORE0_MME_CTRL_LO_ARCH_COUT_SS_MINUS_1_SHIFT 0 +#define DCORE0_MME_CTRL_LO_ARCH_COUT_SS_MINUS_1_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_QM_STALL */ +#define DCORE0_MME_CTRL_LO_QM_STALL_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_QM_STALL_V_MASK 0x1 + +/* DCORE0_MME_CTRL_LO_LOG_SHADOW_LO */ +#define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_0_SHIFT 0 +#define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_0_MASK 0x1FF +#define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_1_SHIFT 9 +#define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_1_MASK 0x3FE00 + +/* DCORE0_MME_CTRL_LO_LOG_SHADOW_HI */ +#define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_2_SHIFT 0 +#define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_2_MASK 0x1FF +#define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_3_SHIFT 9 +#define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_3_MASK 0x3FE00 + +/* DCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH */ +#define DCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH_V_MASK 0x1F + +/* DCORE0_MME_CTRL_LO_REDUN */ +#define DCORE0_MME_CTRL_LO_REDUN_FMA_SHIFT 0 +#define DCORE0_MME_CTRL_LO_REDUN_FMA_MASK 0x3F + +/* DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH */ +#define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO0_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO0_MASK 0x1F +#define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO1_SHIFT 5 +#define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO1_MASK 0x3E0 +#define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO2_SHIFT 10 +#define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO2_MASK 0x7C00 + +/* DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0 */ +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_MASK 0xFF +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE0_SHIFT 8 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE0_MASK 0x1F00 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE1_SHIFT 13 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE1_MASK 0x3E000 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE2_SHIFT 18 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE2_MASK 0x7C0000 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE3_SHIFT 23 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE3_MASK 0xF800000 + +/* DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1 */ +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE4_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE4_MASK 0x1F +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE_HI_SHIFT 5 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE_HI_MASK 0x3E0 + +/* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16 */ +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_DLY_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_DLY_MASK 0xFFF +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_EN_SHIFT 31 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_EN_MASK 0x80000000 + +/* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8 */ +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_DLY_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_DLY_MASK 0xFFF +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_EN_SHIFT 31 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_EN_MASK 0x80000000 + +/* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32 */ +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_DLY_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_DLY_MASK 0xFFF +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_EN_SHIFT 31 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_EN_MASK 0x80000000 + +/* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I */ +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_DLY_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_DLY_MASK 0xFFF +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_EN_SHIFT 31 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_EN_MASK 0x80000000 + +/* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32 */ +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_DLY_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_DLY_MASK 0xFFF +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_EN_SHIFT 31 +#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_EN_MASK 0x80000000 + +/* DCORE0_MME_CTRL_LO_PCU_RL_DESC0 */ +#define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_RST_TOKEN_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_RST_TOKEN_MASK 0xFFFF +#define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_TIMEOUT_SHIFT 16 +#define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_TIMEOUT_MASK 0xFF0000 +#define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_DUMMY2REAL_PERIOD_SHIFT 24 +#define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_DUMMY2REAL_PERIOD_MASK 0xFF000000 + +/* DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE */ +#define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_INC_VAL_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_INC_VAL_MASK 0xFFFF +#define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_DEC_VAL_SHIFT 16 +#define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_DEC_VAL_MASK 0xFFFF0000 + +/* DCORE0_MME_CTRL_LO_PCU_RL_TH */ +#define DCORE0_MME_CTRL_LO_PCU_RL_TH_POOL_TH_DEC_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_RL_TH_POOL_TH_DEC_MASK 0xFFFF +#define DCORE0_MME_CTRL_LO_PCU_RL_TH_DUMMY_REAL_DIFF_TH_SHIFT 16 +#define DCORE0_MME_CTRL_LO_PCU_RL_TH_DUMMY_REAL_DIFF_TH_MASK 0xFFFF0000 + +/* DCORE0_MME_CTRL_LO_PCU_RL_MIN */ +#define DCORE0_MME_CTRL_LO_PCU_RL_MIN_AVG_MIN_TO_FORCE_DUMMY_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_RL_MIN_AVG_MIN_TO_FORCE_DUMMY_MASK 0xFFFF +#define DCORE0_MME_CTRL_LO_PCU_RL_MIN_TOKEN_MIN_VAL_SHIFT 16 +#define DCORE0_MME_CTRL_LO_PCU_RL_MIN_TOKEN_MIN_VAL_MASK 0xFFFF0000 + +/* DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN */ +#define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_PCU_DISABLE_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_PCU_DISABLE_MASK 0x1 +#define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_MIN_VAL_PROT_EN_SHIFT 1 +#define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_MIN_VAL_PROT_EN_MASK 0x2 + +/* DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE */ +#define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_ALL_MACS_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_ALL_MACS_MASK 0x7 +#define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_REAL_MACS_SHIFT 3 +#define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_REAL_MACS_MASK 0x18 + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16 */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_ODD_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_ODD_MASK 0xFFFF +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_EVEN_SHIFT 16 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_EVEN_MASK 0xFFFF0000 + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16 */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_ODD_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_ODD_MASK 0xFFFF +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_EVEN_SHIFT 16 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_EVEN_MASK 0xFFFF0000 + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16 */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_ODD_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_ODD_MASK 0xFFFF +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_EVEN_SHIFT 16 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_EVEN_MASK 0xFFFF0000 + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16 */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_ODD_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_ODD_MASK 0xFFFF +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_EVEN_SHIFT 16 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_EVEN_MASK 0xFFFF0000 + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_F8 */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_ODD_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_ODD_MASK 0xFF +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_EVEN_SHIFT 8 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_EVEN_MASK 0xFF00 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_ODD_SHIFT 16 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_ODD_MASK 0xFF0000 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_EVEN_SHIFT 24 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_EVEN_MASK 0xFF000000 + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD_V_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN_V_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD_V_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN_V_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD_V_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN_V_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD_V_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN */ +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN_V_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_PROT */ +#define DCORE0_MME_CTRL_LO_PROT_VALUE_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PROT_VALUE_MASK 0x7 + +/* DCORE0_MME_CTRL_LO_EU */ +#define DCORE0_MME_CTRL_LO_EU_POWER_SAVE_DISABLE_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EU_POWER_SAVE_DISABLE_MASK 0x1 +#define DCORE0_MME_CTRL_LO_EU_FP_PYR_CLOSE_CGATE_EN_SHIFT 1 +#define DCORE0_MME_CTRL_LO_EU_FP_PYR_CLOSE_CGATE_EN_MASK 0x2 +#define DCORE0_MME_CTRL_LO_EU_FP_CLS_CLOSE_CGATE_EN_SHIFT 2 +#define DCORE0_MME_CTRL_LO_EU_FP_CLS_CLOSE_CGATE_EN_MASK 0x4 +#define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_DLY_SHIFT 8 +#define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_DLY_MASK 0xFFF00 +#define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_ON_DESC_SHIFT 20 +#define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_ON_DESC_MASK 0x100000 +#define DCORE0_MME_CTRL_LO_EU_FP_ROLLUP_CDC_STALL_DIS_SHIFT 21 +#define DCORE0_MME_CTRL_LO_EU_FP_ROLLUP_CDC_STALL_DIS_MASK 0x200000 + +/* DCORE0_MME_CTRL_LO_SBTE */ +#define DCORE0_MME_CTRL_LO_SBTE_CLOSE_CGATE_SHIFT 0 +#define DCORE0_MME_CTRL_LO_SBTE_CLOSE_CGATE_MASK 0x1F + +/* DCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR */ +#define DCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR_V_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR */ +#define DCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR_V_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC */ +#define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_VAL_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_VAL_MASK 0xFFFFF +#define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_SEL_SHIFT 31 +#define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_SEL_MASK 0x80000000 + +/* DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32 */ +#define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32_V_NMB__SHIFT 0 +#define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32_V_NMB__MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33 */ +#define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33_V_NMB__SHIFT 0 +#define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33_V_NMB__MASK 0x1 + +/* DCORE0_MME_CTRL_LO_EU_ISOLATION_DIS */ +#define DCORE0_MME_CTRL_LO_EU_ISOLATION_DIS_FMA_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EU_ISOLATION_DIS_FMA_MASK 0x1 + +/* DCORE0_MME_CTRL_LO_QM_SLV_CLK_EN */ +#define DCORE0_MME_CTRL_LO_QM_SLV_CLK_EN_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_QM_SLV_CLK_EN_V_MASK 0x1 + +/* DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS */ +#define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_AXI_SHIFT 0 +#define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_AXI_MASK 0x1 +#define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_APB_SHIFT 1 +#define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_APB_MASK 0x2 + +/* DCORE0_MME_CTRL_LO_AGU */ +#define DCORE0_MME_CTRL_LO_AGU_COUT_H_FROM_SPATIAL_LOOP_SHIFT 0 +#define DCORE0_MME_CTRL_LO_AGU_COUT_H_FROM_SPATIAL_LOOP_MASK 0x1 + +/* DCORE0_MME_CTRL_LO_QM */ +#define DCORE0_MME_CTRL_LO_QM_STOP_ON_SBTE_ERR_SHIFT 0 +#define DCORE0_MME_CTRL_LO_QM_STOP_ON_SBTE_ERR_MASK 0x1 +#define DCORE0_MME_CTRL_LO_QM_EXT_ADDR_ERR_EN_SHIFT 1 +#define DCORE0_MME_CTRL_LO_QM_EXT_ADDR_ERR_EN_MASK 0x2 + +/* DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS */ +#define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT0_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT0_MASK 0xF +#define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT1_SHIFT 4 +#define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT1_MASK 0xF0 +#define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AP_BRAIN_SHIFT 8 +#define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AP_BRAIN_MASK 0xF00 +#define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_EU_BRAIN_SHIFT 12 +#define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_EU_BRAIN_MASK 0xF000 + +/* DCORE0_MME_CTRL_LO_INTR_CAUSE */ +#define DCORE0_MME_CTRL_LO_INTR_CAUSE_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_INTR_CAUSE_V_MASK 0xFFFF + +/* DCORE0_MME_CTRL_LO_INTR_MASK */ +#define DCORE0_MME_CTRL_LO_INTR_MASK_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_INTR_MASK_V_MASK 0x3FFFFF + +/* DCORE0_MME_CTRL_LO_INTR_CLEAR */ +#define DCORE0_MME_CTRL_LO_INTR_CLEAR_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_INTR_CLEAR_V_MASK 0xFFFF + +/* DCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC */ +#define DCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC_V_MASK 0x1 + +/* DCORE0_MME_CTRL_LO_BIST */ +#define DCORE0_MME_CTRL_LO_BIST_FUNC_MODE_SHIFT 0 +#define DCORE0_MME_CTRL_LO_BIST_FUNC_MODE_MASK 0x1 +#define DCORE0_MME_CTRL_LO_BIST_APB_SW_MODE_SHIFT 1 +#define DCORE0_MME_CTRL_LO_BIST_APB_SW_MODE_MASK 0x2 + +/* DCORE0_MME_CTRL_LO_EU_RL_ENABLE */ +#define DCORE0_MME_CTRL_LO_EU_RL_ENABLE_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EU_RL_ENABLE_V_MASK 0x1 + +/* DCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL */ +#define DCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL_STAT_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL_STAT_MASK 0x1 + +/* DCORE0_MME_CTRL_LO_EU_RL_CFG */ +#define DCORE0_MME_CTRL_LO_EU_RL_CFG_RST_TOKEN_SHIFT 0 +#define DCORE0_MME_CTRL_LO_EU_RL_CFG_RST_TOKEN_MASK 0xFF +#define DCORE0_MME_CTRL_LO_EU_RL_CFG_TIMEOUT_SHIFT 8 +#define DCORE0_MME_CTRL_LO_EU_RL_CFG_TIMEOUT_MASK 0xFF00 +#define DCORE0_MME_CTRL_LO_EU_RL_CFG_SATURATION_SHIFT 16 +#define DCORE0_MME_CTRL_LO_EU_RL_CFG_SATURATION_MASK 0xFF0000 +#define DCORE0_MME_CTRL_LO_EU_RL_CFG_DATA_SIZE_SHIFT 24 +#define DCORE0_MME_CTRL_LO_EU_RL_CFG_DATA_SIZE_MASK 0xFF000000 + +/* DCORE0_MME_CTRL_LO_PCU_DBG_DW0 */ +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_FSM_STATE_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_FSM_STATE_MASK 0x1 +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_REAL_POOL_TOKENS_SHIFT 8 +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_REAL_POOL_TOKENS_MASK 0xFFFFF00 + +/* DCORE0_MME_CTRL_LO_PCU_DBG_DW1 */ +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW1_ALL_POOL_TOKENS_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW1_ALL_POOL_TOKENS_MASK 0xFFFFF + +/* DCORE0_MME_CTRL_LO_PCU_DBG_DW2 */ +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_BUBBLE_CYC_CNTR_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_BUBBLE_CYC_CNTR_MASK 0xFFFF +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_DUMMY_CYC_CNTR_SHIFT 16 +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_DUMMY_CYC_CNTR_MASK 0xFFFF0000 + +/* DCORE0_MME_CTRL_LO_PCU_DBG_DW3 */ +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_REAL_MACS_HISTORY_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_REAL_MACS_HISTORY_MASK 0xFFFF +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_ALL_MACS_HISTORY_SHIFT 16 +#define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_ALL_MACS_HISTORY_MASK 0xFFFF0000 + +/* DCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID */ +#define DCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID_B_SHIFT 0 +#define DCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID_B_MASK 0xFFFFFFFF + +/* DCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM */ +#define DCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM_V_SHIFT 0 +#define DCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM_V_MASK 0x3FFFFFFF + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_mme_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_mme_axuser_regs.h new file mode 100644 index 000000000000..a51617a6f1fb --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_mme_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_MME_AXUSER_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_MME_AXUSER_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_MME_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_ASID 0x40CBE00 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_MMU_BP 0x40CBE04 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_STRONG_ORDER 0x40CBE08 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_NO_SNOOP 0x40CBE0C + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_WR_REDUCTION 0x40CBE10 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_RD_ATOMIC 0x40CBE14 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_QOS 0x40CBE18 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_RSVD 0x40CBE1C + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_EMEM_CPAGE 0x40CBE20 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_CORE 0x40CBE24 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_E2E_COORD 0x40CBE28 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_WR_OVRD_LO 0x40CBE30 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_WR_OVRD_HI 0x40CBE34 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_RD_OVRD_LO 0x40CBE38 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_RD_OVRD_HI 0x40CBE3C + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_LB_COORD 0x40CBE40 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_LB_LOCK 0x40CBE44 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_LB_RSVD 0x40CBE48 + +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_LB_OVRD 0x40CBE4C + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_MME_AXUSER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_regs.h new file mode 100644 index 000000000000..1b91c9c13132 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_regs.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO + * (Prototype: MME_CTRL_LO) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_STATUS 0x40CB000 + +#define mmDCORE0_MME_CTRL_LO_CMD 0x40CB004 + +#define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0 0x40CB148 + +#define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0 0x40CB14C + +#define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0 0x40CB150 + +#define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1 0x40CB154 + +#define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1 0x40CB158 + +#define mmDCORE0_MME_CTRL_LO_ARCH_A_SS 0x40CB224 + +#define mmDCORE0_MME_CTRL_LO_ARCH_B_SS 0x40CB228 + +#define mmDCORE0_MME_CTRL_LO_ARCH_COUT_SS 0x40CB27C + +#define mmDCORE0_MME_CTRL_LO_QM_STALL 0x40CB400 + +#define mmDCORE0_MME_CTRL_LO_LOG_SHADOW_LO 0x40CB404 + +#define mmDCORE0_MME_CTRL_LO_LOG_SHADOW_HI 0x40CB408 + +#define mmDCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH 0x40CB40C + +#define mmDCORE0_MME_CTRL_LO_REDUN 0x40CB410 + +#define mmDCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH 0x40CB414 + +#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0 0x40CB418 + +#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1 0x40CB41C + +#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16 0x40CB420 + +#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8 0x40CB424 + +#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32 0x40CB428 + +#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I 0x40CB42C + +#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32 0x40CB430 + +#define mmDCORE0_MME_CTRL_LO_PCU_RL_DESC0 0x40CB434 + +#define mmDCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE 0x40CB438 + +#define mmDCORE0_MME_CTRL_LO_PCU_RL_TH 0x40CB43C + +#define mmDCORE0_MME_CTRL_LO_PCU_RL_MIN 0x40CB440 + +#define mmDCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN 0x40CB444 + +#define mmDCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE 0x40CB448 + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16 0x40CB44C + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16 0x40CB450 + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16 0x40CB454 + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16 0x40CB458 + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_F8 0x40CB45C + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD 0x40CB460 + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN 0x40CB464 + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD 0x40CB468 + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN 0x40CB46C + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD 0x40CB470 + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN 0x40CB474 + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD 0x40CB478 + +#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN 0x40CB47C + +#define mmDCORE0_MME_CTRL_LO_PROT 0x40CB480 + +#define mmDCORE0_MME_CTRL_LO_EU 0x40CB484 + +#define mmDCORE0_MME_CTRL_LO_SBTE 0x40CB488 + +#define mmDCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR 0x40CB48C + +#define mmDCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR 0x40CB490 + +#define mmDCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC 0x40CB494 + +#define mmDCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32 0x40CB498 + +#define mmDCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33 0x40CB49C + +#define mmDCORE0_MME_CTRL_LO_EU_ISOLATION_DIS 0x40CB4A0 + +#define mmDCORE0_MME_CTRL_LO_QM_SLV_CLK_EN 0x40CB4A4 + +#define mmDCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS 0x40CB4A8 + +#define mmDCORE0_MME_CTRL_LO_AGU 0x40CB4AC + +#define mmDCORE0_MME_CTRL_LO_QM 0x40CB4B0 + +#define mmDCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS 0x40CB4B4 + +#define mmDCORE0_MME_CTRL_LO_INTR_CAUSE 0x40CB4B8 + +#define mmDCORE0_MME_CTRL_LO_INTR_MASK 0x40CB4BC + +#define mmDCORE0_MME_CTRL_LO_INTR_CLEAR 0x40CB4C0 + +#define mmDCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC 0x40CB4C4 + +#define mmDCORE0_MME_CTRL_LO_BIST 0x40CB4C8 + +#define mmDCORE0_MME_CTRL_LO_EU_RL_ENABLE 0x40CB4CC + +#define mmDCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL 0x40CB4D0 + +#define mmDCORE0_MME_CTRL_LO_EU_RL_CFG 0x40CB4D4 + +#define mmDCORE0_MME_CTRL_LO_PCU_DBG_DW0 0x40CB4D8 + +#define mmDCORE0_MME_CTRL_LO_PCU_DBG_DW1 0x40CB4DC + +#define mmDCORE0_MME_CTRL_LO_PCU_DBG_DW2 0x40CB4E0 + +#define mmDCORE0_MME_CTRL_LO_PCU_DBG_DW3 0x40CB4E4 + +#define mmDCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID 0x40CB4E8 + +#define mmDCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM 0x40CB4EC + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_acp_eng_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_acp_eng_regs.h new file mode 100644 index 000000000000..f702fe6e9365 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_acp_eng_regs.h @@ -0,0 +1,567 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_QM_ARC_ACP_ENG_REGS_H_ +#define ASIC_REG_DCORE0_MME_QM_ARC_ACP_ENG_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_QM_ARC_ACP_ENG + * (Prototype: ARC_ACP_ENG) + ***************************************** + */ + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_0 0x40CF000 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_1 0x40CF004 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_2 0x40CF008 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_3 0x40CF00C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_4 0x40CF010 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_5 0x40CF014 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_6 0x40CF018 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_7 0x40CF01C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_8 0x40CF020 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_9 0x40CF024 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_10 0x40CF028 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_11 0x40CF02C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_12 0x40CF030 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_13 0x40CF034 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_14 0x40CF038 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_15 0x40CF03C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_16 0x40CF040 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_17 0x40CF044 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_18 0x40CF048 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_19 0x40CF04C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_20 0x40CF050 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_21 0x40CF054 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_22 0x40CF058 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_23 0x40CF05C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_24 0x40CF060 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_25 0x40CF064 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_26 0x40CF068 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_27 0x40CF06C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_28 0x40CF070 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_29 0x40CF074 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_30 0x40CF078 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_31 0x40CF07C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_32 0x40CF080 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_33 0x40CF084 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_34 0x40CF088 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_35 0x40CF08C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_36 0x40CF090 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_37 0x40CF094 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_38 0x40CF098 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_39 0x40CF09C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_40 0x40CF0A0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_41 0x40CF0A4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_42 0x40CF0A8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_43 0x40CF0AC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_44 0x40CF0B0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_45 0x40CF0B4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_46 0x40CF0B8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_47 0x40CF0BC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_48 0x40CF0C0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_49 0x40CF0C4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_50 0x40CF0C8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_51 0x40CF0CC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_52 0x40CF0D0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_53 0x40CF0D4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_54 0x40CF0D8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_55 0x40CF0DC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_56 0x40CF0E0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_57 0x40CF0E4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_58 0x40CF0E8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_59 0x40CF0EC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_60 0x40CF0F0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_61 0x40CF0F4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_62 0x40CF0F8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_63 0x40CF0FC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_0 0x40CF100 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_1 0x40CF104 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_2 0x40CF108 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_3 0x40CF10C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_4 0x40CF110 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_5 0x40CF114 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_6 0x40CF118 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_7 0x40CF11C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_8 0x40CF120 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_9 0x40CF124 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_10 0x40CF128 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_11 0x40CF12C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_12 0x40CF130 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_13 0x40CF134 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_14 0x40CF138 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_15 0x40CF13C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_16 0x40CF140 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_17 0x40CF144 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_18 0x40CF148 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_19 0x40CF14C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_20 0x40CF150 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_21 0x40CF154 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_22 0x40CF158 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_23 0x40CF15C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_24 0x40CF160 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_25 0x40CF164 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_26 0x40CF168 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_27 0x40CF16C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_28 0x40CF170 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_29 0x40CF174 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_30 0x40CF178 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_31 0x40CF17C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_32 0x40CF180 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_33 0x40CF184 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_34 0x40CF188 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_35 0x40CF18C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_36 0x40CF190 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_37 0x40CF194 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_38 0x40CF198 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_39 0x40CF19C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_40 0x40CF1A0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_41 0x40CF1A4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_42 0x40CF1A8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_43 0x40CF1AC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_44 0x40CF1B0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_45 0x40CF1B4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_46 0x40CF1B8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_47 0x40CF1BC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_48 0x40CF1C0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_49 0x40CF1C4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_50 0x40CF1C8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_51 0x40CF1CC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_52 0x40CF1D0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_53 0x40CF1D4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_54 0x40CF1D8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_55 0x40CF1DC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_56 0x40CF1E0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_57 0x40CF1E4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_58 0x40CF1E8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_59 0x40CF1EC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_60 0x40CF1F0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_61 0x40CF1F4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_62 0x40CF1F8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_63 0x40CF1FC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_0 0x40CF200 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_1 0x40CF204 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_2 0x40CF208 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_3 0x40CF20C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_4 0x40CF210 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_5 0x40CF214 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_6 0x40CF218 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_7 0x40CF21C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_8 0x40CF220 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_9 0x40CF224 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_10 0x40CF228 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_11 0x40CF22C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_12 0x40CF230 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_13 0x40CF234 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_14 0x40CF238 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_15 0x40CF23C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_16 0x40CF240 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_17 0x40CF244 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_18 0x40CF248 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_19 0x40CF24C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_20 0x40CF250 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_21 0x40CF254 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_22 0x40CF258 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_23 0x40CF25C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_24 0x40CF260 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_25 0x40CF264 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_26 0x40CF268 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_27 0x40CF26C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_28 0x40CF270 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_29 0x40CF274 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_30 0x40CF278 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_31 0x40CF27C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_32 0x40CF280 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_33 0x40CF284 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_34 0x40CF288 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_35 0x40CF28C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_36 0x40CF290 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_37 0x40CF294 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_38 0x40CF298 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_39 0x40CF29C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_40 0x40CF2A0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_41 0x40CF2A4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_42 0x40CF2A8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_43 0x40CF2AC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_44 0x40CF2B0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_45 0x40CF2B4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_46 0x40CF2B8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_47 0x40CF2BC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_48 0x40CF2C0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_49 0x40CF2C4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_50 0x40CF2C8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_51 0x40CF2CC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_52 0x40CF2D0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_53 0x40CF2D4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_54 0x40CF2D8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_55 0x40CF2DC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_56 0x40CF2E0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_57 0x40CF2E4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_58 0x40CF2E8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_59 0x40CF2EC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_60 0x40CF2F0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_61 0x40CF2F4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_62 0x40CF2F8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_63 0x40CF2FC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_0 0x40CF300 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_1 0x40CF304 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_2 0x40CF308 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_3 0x40CF30C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_4 0x40CF310 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_5 0x40CF314 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_6 0x40CF318 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_7 0x40CF31C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_8 0x40CF320 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_9 0x40CF324 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_10 0x40CF328 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_11 0x40CF32C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_12 0x40CF330 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_13 0x40CF334 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_14 0x40CF338 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_15 0x40CF33C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_16 0x40CF340 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_17 0x40CF344 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_18 0x40CF348 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_19 0x40CF34C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_20 0x40CF350 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_21 0x40CF354 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_22 0x40CF358 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_23 0x40CF35C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_24 0x40CF360 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_25 0x40CF364 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_26 0x40CF368 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_27 0x40CF36C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_28 0x40CF370 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_29 0x40CF374 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_30 0x40CF378 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_31 0x40CF37C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_32 0x40CF380 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_33 0x40CF384 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_34 0x40CF388 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_35 0x40CF38C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_36 0x40CF390 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_37 0x40CF394 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_38 0x40CF398 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_39 0x40CF39C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_40 0x40CF3A0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_41 0x40CF3A4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_42 0x40CF3A8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_43 0x40CF3AC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_44 0x40CF3B0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_45 0x40CF3B4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_46 0x40CF3B8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_47 0x40CF3BC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_48 0x40CF3C0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_49 0x40CF3C4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_50 0x40CF3C8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_51 0x40CF3CC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_52 0x40CF3D0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_53 0x40CF3D4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_54 0x40CF3D8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_55 0x40CF3DC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_56 0x40CF3E0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_57 0x40CF3E4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_58 0x40CF3E8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_59 0x40CF3EC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_60 0x40CF3F0 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_61 0x40CF3F4 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_62 0x40CF3F8 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_63 0x40CF3FC + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_SELECTED_QUEUE_ID 0x40CF400 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_0 0x40CF404 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_1 0x40CF408 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_2 0x40CF40C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_0 0x40CF410 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_1 0x40CF414 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_2 0x40CF418 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_0 0x40CF41C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_1 0x40CF420 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_2 0x40CF424 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_3 0x40CF428 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_RD_CNT_0 0x40CF42C + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_RD_CNT_1 0x40CF430 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_RD_CNT_2 0x40CF434 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_RD_CNT_3 0x40CF438 + +#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_REG 0x40CF43C + +#endif /* ASIC_REG_DCORE0_MME_QM_ARC_ACP_ENG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_aux_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_aux_regs.h new file mode 100644 index 000000000000..917f8ab88373 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_aux_regs.h @@ -0,0 +1,591 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_QM_ARC_AUX_REGS_H_ +#define ASIC_REG_DCORE0_MME_QM_ARC_AUX_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_QM_ARC_AUX + * (Prototype: QMAN_ARC_AUX) + ***************************************** + */ + +#define mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_REQ 0x40C8100 + +#define mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_ACK 0x40C8104 + +#define mmDCORE0_MME_QM_ARC_AUX_RST_VEC_ADDR 0x40C8108 + +#define mmDCORE0_MME_QM_ARC_AUX_DBG_MODE 0x40C810C + +#define mmDCORE0_MME_QM_ARC_AUX_CLUSTER_NUM 0x40C8110 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_NUM 0x40C8114 + +#define mmDCORE0_MME_QM_ARC_AUX_WAKE_UP_EVENT 0x40C8118 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x40C811C + +#define mmDCORE0_MME_QM_ARC_AUX_CTI_AP_STS 0x40C8120 + +#define mmDCORE0_MME_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x40C8124 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_RST 0x40C8128 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_RST_REQ 0x40C812C + +#define mmDCORE0_MME_QM_ARC_AUX_SRAM_LSB_ADDR 0x40C8130 + +#define mmDCORE0_MME_QM_ARC_AUX_SRAM_MSB_ADDR 0x40C8134 + +#define mmDCORE0_MME_QM_ARC_AUX_PCIE_LSB_ADDR 0x40C8138 + +#define mmDCORE0_MME_QM_ARC_AUX_PCIE_MSB_ADDR 0x40C813C + +#define mmDCORE0_MME_QM_ARC_AUX_CFG_LSB_ADDR 0x40C8140 + +#define mmDCORE0_MME_QM_ARC_AUX_CFG_MSB_ADDR 0x40C8144 + +#define mmDCORE0_MME_QM_ARC_AUX_HBM0_LSB_ADDR 0x40C8150 + +#define mmDCORE0_MME_QM_ARC_AUX_HBM0_MSB_ADDR 0x40C8154 + +#define mmDCORE0_MME_QM_ARC_AUX_HBM1_LSB_ADDR 0x40C8158 + +#define mmDCORE0_MME_QM_ARC_AUX_HBM1_MSB_ADDR 0x40C815C + +#define mmDCORE0_MME_QM_ARC_AUX_HBM2_LSB_ADDR 0x40C8160 + +#define mmDCORE0_MME_QM_ARC_AUX_HBM2_MSB_ADDR 0x40C8164 + +#define mmDCORE0_MME_QM_ARC_AUX_HBM3_LSB_ADDR 0x40C8168 + +#define mmDCORE0_MME_QM_ARC_AUX_HBM3_MSB_ADDR 0x40C816C + +#define mmDCORE0_MME_QM_ARC_AUX_HBM0_OFFSET 0x40C8170 + +#define mmDCORE0_MME_QM_ARC_AUX_HBM1_OFFSET 0x40C8174 + +#define mmDCORE0_MME_QM_ARC_AUX_HBM2_OFFSET 0x40C8178 + +#define mmDCORE0_MME_QM_ARC_AUX_HBM3_OFFSET 0x40C817C + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x40C8180 + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x40C8184 + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x40C8188 + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x40C818C + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x40C8190 + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x40C8194 + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x40C8198 + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x40C819C + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x40C81A0 + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x40C81A4 + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x40C81A8 + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x40C81AC + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x40C81B0 + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x40C81B4 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_CBU_AWCACHE_OVR 0x40C81B8 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_LBU_AWCACHE_OVR 0x40C81BC + +#define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_0 0x40C81C0 + +#define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_1 0x40C81C4 + +#define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_2 0x40C81C8 + +#define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_3 0x40C81CC + +#define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_4 0x40C81D0 + +#define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_5 0x40C81D4 + +#define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_6 0x40C81D8 + +#define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_7 0x40C81DC + +#define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_0 0x40C81E0 + +#define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_1 0x40C81E4 + +#define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_2 0x40C81E8 + +#define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_3 0x40C81EC + +#define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_4 0x40C81F0 + +#define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_5 0x40C81F4 + +#define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_6 0x40C81F8 + +#define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_7 0x40C81FC + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_0 0x40C8200 + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_1 0x40C8204 + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_2 0x40C8208 + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_3 0x40C820C + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_4 0x40C8210 + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_5 0x40C8214 + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_6 0x40C8218 + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_7 0x40C821C + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_8 0x40C8220 + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_9 0x40C8224 + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_10 0x40C8228 + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_11 0x40C822C + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_12 0x40C8230 + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_13 0x40C8234 + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_14 0x40C8238 + +#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_15 0x40C823C + +#define mmDCORE0_MME_QM_ARC_AUX_IRQ_INTR_MASK_0 0x40C8280 + +#define mmDCORE0_MME_QM_ARC_AUX_IRQ_INTR_MASK_1 0x40C8284 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_SEI_INTR_STS 0x40C8290 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_SEI_INTR_CLR 0x40C8294 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_SEI_INTR_MASK 0x40C8298 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_EXCPTN_CAUSE 0x40C829C + +#define mmDCORE0_MME_QM_ARC_AUX_SEI_INTR_HALT_EN 0x40C82A0 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_SEI_INTR_HALT_MASK 0x40C82A4 + +#define mmDCORE0_MME_QM_ARC_AUX_QMAN_SEI_INTR_HALT_MASK 0x40C82A8 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REI_INTR_STS 0x40C82B0 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REI_INTR_CLR 0x40C82B4 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REI_INTR_MASK 0x40C82B8 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_ECC_ERR_ADDR 0x40C82BC + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_ECC_SYNDROME 0x40C82C0 + +#define mmDCORE0_MME_QM_ARC_AUX_I_CACHE_ECC_ERR_ADDR 0x40C82C4 + +#define mmDCORE0_MME_QM_ARC_AUX_I_CACHE_ECC_SYNDROME 0x40C82C8 + +#define mmDCORE0_MME_QM_ARC_AUX_D_CACHE_ECC_ERR_ADDR 0x40C82CC + +#define mmDCORE0_MME_QM_ARC_AUX_D_CACHE_ECC_SYNDROME 0x40C82D0 + +#define mmDCORE0_MME_QM_ARC_AUX_LBW_TRMINATE_AWADDR_ERR 0x40C82E0 + +#define mmDCORE0_MME_QM_ARC_AUX_LBW_TRMINATE_ARADDR_ERR 0x40C82E4 + +#define mmDCORE0_MME_QM_ARC_AUX_CFG_LBW_TERMINATE_BRESP 0x40C82E8 + +#define mmDCORE0_MME_QM_ARC_AUX_CFG_LBW_TERMINATE_RRESP 0x40C82EC + +#define mmDCORE0_MME_QM_ARC_AUX_CFG_LBW_TERMINATE_AXLEN 0x40C82F0 + +#define mmDCORE0_MME_QM_ARC_AUX_CFG_LBW_TERMINATE_AXSIZE 0x40C82F4 + +#define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_0 0x40C8300 + +#define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_1 0x40C8304 + +#define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_2 0x40C8308 + +#define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_3 0x40C830C + +#define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_4 0x40C8310 + +#define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_5 0x40C8314 + +#define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_6 0x40C8318 + +#define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_7 0x40C831C + +#define mmDCORE0_MME_QM_ARC_AUX_TOTAL_CBU_WR_CNT 0x40C8320 + +#define mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_CBU_WR_CNT 0x40C8324 + +#define mmDCORE0_MME_QM_ARC_AUX_TOTAL_CBU_RD_CNT 0x40C8328 + +#define mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_CBU_RD_CNT 0x40C832C + +#define mmDCORE0_MME_QM_ARC_AUX_TOTAL_LBU_WR_CNT 0x40C8330 + +#define mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_LBU_WR_CNT 0x40C8334 + +#define mmDCORE0_MME_QM_ARC_AUX_TOTAL_LBU_RD_CNT 0x40C8338 + +#define mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT 0x40C833C + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_ARUSER_OVR 0x40C8350 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_ARUSER_OVR_EN 0x40C8354 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_AWUSER_OVR 0x40C8358 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_AWUSER_OVR_EN 0x40C835C + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_ARUSER_MSB_OVR 0x40C8360 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_ARUSER_MSB_OVR_EN 0x40C8364 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_AWUSER_MSB_OVR 0x40C8368 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_AWUSER_MSB_OVR_EN 0x40C836C + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_AXCACHE_OVR 0x40C8370 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_LOCK_OVR 0x40C8374 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_PROT_OVR 0x40C8378 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_MAX_OUTSTANDING 0x40C837C + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_EARLY_BRESP_EN 0x40C8380 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORCE_RSP_OK 0x40C8384 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_NO_WR_INFLIGHT 0x40C838C + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_SEI_INTR_ID 0x40C8390 + +#define mmDCORE0_MME_QM_ARC_AUX_LBU_ARUSER_OVR 0x40C8400 + +#define mmDCORE0_MME_QM_ARC_AUX_LBU_ARUSER_OVR_EN 0x40C8404 + +#define mmDCORE0_MME_QM_ARC_AUX_LBU_AWUSER_OVR 0x40C8408 + +#define mmDCORE0_MME_QM_ARC_AUX_LBU_AWUSER_OVR_EN 0x40C840C + +#define mmDCORE0_MME_QM_ARC_AUX_LBU_AXCACHE_OVR 0x40C8420 + +#define mmDCORE0_MME_QM_ARC_AUX_LBU_LOCK_OVR 0x40C8424 + +#define mmDCORE0_MME_QM_ARC_AUX_LBU_PROT_OVR 0x40C8428 + +#define mmDCORE0_MME_QM_ARC_AUX_LBU_MAX_OUTSTANDING 0x40C842C + +#define mmDCORE0_MME_QM_ARC_AUX_LBU_EARLY_BRESP_EN 0x40C8430 + +#define mmDCORE0_MME_QM_ARC_AUX_LBU_FORCE_RSP_OK 0x40C8434 + +#define mmDCORE0_MME_QM_ARC_AUX_LBU_NO_WR_INFLIGHT 0x40C843C + +#define mmDCORE0_MME_QM_ARC_AUX_LBU_SEI_INTR_ID 0x40C8440 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0 0x40C8500 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_1 0x40C8504 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_2 0x40C8508 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_3 0x40C850C + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_4 0x40C8510 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_5 0x40C8514 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_6 0x40C8518 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_7 0x40C851C + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_0 0x40C8520 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_1 0x40C8524 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_2 0x40C8528 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_3 0x40C852C + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_4 0x40C8530 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_5 0x40C8534 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_6 0x40C8538 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_7 0x40C853C + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_0 0x40C8540 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_1 0x40C8544 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_2 0x40C8548 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_3 0x40C854C + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_4 0x40C8550 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_5 0x40C8554 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_6 0x40C8558 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_7 0x40C855C + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_0 0x40C8560 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_1 0x40C8564 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_2 0x40C8568 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_3 0x40C856C + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_4 0x40C8570 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_5 0x40C8574 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_6 0x40C8578 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_7 0x40C857C + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_0 0x40C8580 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_1 0x40C8584 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_2 0x40C8588 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_3 0x40C858C + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_4 0x40C8590 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_5 0x40C8594 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_6 0x40C8598 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_7 0x40C859C + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x40C85A0 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x40C85A4 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x40C85A8 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x40C85AC + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x40C85B0 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x40C85B4 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x40C85B8 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x40C85BC + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x40C85C0 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x40C85C4 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x40C85C8 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x40C85CC + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x40C85D0 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x40C85D4 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x40C85D8 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x40C85DC + +#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x40C85E0 + +#define mmDCORE0_MME_QM_ARC_AUX_NIC_Q_VLD_ENTRY_MASK 0x40C85E4 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_DROP_EN 0x40C8620 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_WARN_MSG 0x40C8624 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG 0x40C8628 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_GEN_AXI_AWPROT 0x40C8630 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_GEN_AXI_AWUSER 0x40C8634 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_GEN_AXI_AWBURST 0x40C8638 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_GEN_AXI_AWLOCK 0x40C863C + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_GEN_AXI_AWCACHE 0x40C8640 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_WRR_ARB_WEIGHT 0x40C8644 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x40C8648 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT 0x40C864C + +#define mmDCORE0_MME_QM_ARC_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x40C8650 + +#define mmDCORE0_MME_QM_ARC_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x40C8654 + +#define mmDCORE0_MME_QM_ARC_AUX_QMAN_CQ_SHADOW_CI 0x40C8658 + +#define mmDCORE0_MME_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI 0x40C865C + +#define mmDCORE0_MME_QM_ARC_AUX_AUX2APB_PROT 0x40C8700 + +#define mmDCORE0_MME_QM_ARC_AUX_LBW_FORK_WIN_EN 0x40C8704 + +#define mmDCORE0_MME_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x40C8708 + +#define mmDCORE0_MME_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x40C870C + +#define mmDCORE0_MME_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x40C8710 + +#define mmDCORE0_MME_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x40C8714 + +#define mmDCORE0_MME_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR0 0x40C8718 + +#define mmDCORE0_MME_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK0 0x40C871C + +#define mmDCORE0_MME_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR1 0x40C8720 + +#define mmDCORE0_MME_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK1 0x40C8724 + +#define mmDCORE0_MME_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR0 0x40C8728 + +#define mmDCORE0_MME_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR1 0x40C872C + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x40C8730 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x40C8734 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x40C8738 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x40C873C + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_WIN_EN 0x40C8740 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_LSB 0x40C8750 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_MSB 0x40C8754 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_LSB 0x40C8758 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_MSB 0x40C875C + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_LSB 0x40C8760 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_MSB 0x40C8764 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_LSB 0x40C8768 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_MSB 0x40C876C + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_LSB 0x40C8770 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_MSB 0x40C8774 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_LSB 0x40C8778 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_MSB 0x40C877C + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_LSB 0x40C8780 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_MSB 0x40C8784 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_LSB 0x40C8788 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_MSB 0x40C878C + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_TRMINATE_ARADDR_LSB 0x40C8790 + +#define mmDCORE0_MME_QM_ARC_AUX_CBU_TRMINATE_ARADDR_MSB 0x40C8794 + +#define mmDCORE0_MME_QM_ARC_AUX_CFG_CBU_TERMINATE_BRESP 0x40C8798 + +#define mmDCORE0_MME_QM_ARC_AUX_CFG_CBU_TERMINATE_RRESP 0x40C879C + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_0 0x40C8800 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_1 0x40C8804 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_2 0x40C8808 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_3 0x40C880C + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_4 0x40C8810 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_5 0x40C8814 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_6 0x40C8818 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_7 0x40C881C + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_8 0x40C8820 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_9 0x40C8824 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_10 0x40C8828 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_11 0x40C882C + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_12 0x40C8830 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_13 0x40C8834 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_14 0x40C8838 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_15 0x40C883C + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_TRMINATE_AWADDR_ERR 0x40C8840 + +#define mmDCORE0_MME_QM_ARC_AUX_DCCM_TRMINATE_ARADDR_ERR 0x40C8844 + +#define mmDCORE0_MME_QM_ARC_AUX_CFG_DCCM_TERMINATE_BRESP 0x40C8848 + +#define mmDCORE0_MME_QM_ARC_AUX_CFG_DCCM_TERMINATE_RRESP 0x40C884C + +#define mmDCORE0_MME_QM_ARC_AUX_CFG_DCCM_TERMINATE_EN 0x40C8850 + +#define mmDCORE0_MME_QM_ARC_AUX_CFG_DCCM_SECURE_REGION 0x40C8854 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x40C8900 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_CTL 0x40C8904 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x40C8908 + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR 0x40C890C + +#define mmDCORE0_MME_QM_ARC_AUX_ARC_ACC_ENGS_BUSER 0x40C8910 + +#define mmDCORE0_MME_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN 0x40C8920 + +#endif /* ASIC_REG_DCORE0_MME_QM_ARC_AUX_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_dup_eng_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_dup_eng_axuser_regs.h new file mode 100644 index 000000000000..c7ebaf73c51e --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_dup_eng_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_QM_ARC_DUP_ENG_AXUSER_REGS_H_ +#define ASIC_REG_DCORE0_MME_QM_ARC_DUP_ENG_AXUSER_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_QM_ARC_DUP_ENG_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_ASID 0x40C9900 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_MMU_BP 0x40C9904 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_STRONG_ORDER 0x40C9908 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_NO_SNOOP 0x40C990C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_WR_REDUCTION 0x40C9910 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_RD_ATOMIC 0x40C9914 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_QOS 0x40C9918 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_RSVD 0x40C991C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_EMEM_CPAGE 0x40C9920 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_CORE 0x40C9924 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_E2E_COORD 0x40C9928 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_WR_OVRD_LO 0x40C9930 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_WR_OVRD_HI 0x40C9934 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_RD_OVRD_LO 0x40C9938 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_RD_OVRD_HI 0x40C993C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_LB_COORD 0x40C9940 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_LB_LOCK 0x40C9944 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_LB_RSVD 0x40C9948 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_LB_OVRD 0x40C994C + +#endif /* ASIC_REG_DCORE0_MME_QM_ARC_DUP_ENG_AXUSER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_dup_eng_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_dup_eng_regs.h new file mode 100644 index 000000000000..61654e37335b --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_dup_eng_regs.h @@ -0,0 +1,575 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_QM_ARC_DUP_ENG_REGS_H_ +#define ASIC_REG_DCORE0_MME_QM_ARC_DUP_ENG_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_QM_ARC_DUP_ENG + * (Prototype: ARC_DUP_ENG) + ***************************************** + */ + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_0 0x40C9000 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_1 0x40C9004 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_2 0x40C9008 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_3 0x40C900C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_4 0x40C9010 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_5 0x40C9014 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_6 0x40C9018 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_7 0x40C901C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_8 0x40C9020 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_9 0x40C9024 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_10 0x40C9028 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_11 0x40C902C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_12 0x40C9030 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_13 0x40C9034 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_14 0x40C9038 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_15 0x40C903C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_16 0x40C9040 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_17 0x40C9044 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_18 0x40C9048 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_19 0x40C904C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_20 0x40C9050 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_21 0x40C9054 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_22 0x40C9058 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_23 0x40C905C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_24 0x40C9060 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_ADDR_0 0x40C9064 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_ADDR_1 0x40C9068 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_ADDR_2 0x40C906C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_ADDR_3 0x40C9070 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_0 0x40C9074 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_1 0x40C9078 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_2 0x40C907C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_3 0x40C9080 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_4 0x40C9084 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_5 0x40C9088 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_6 0x40C908C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_7 0x40C9090 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_8 0x40C9094 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_9 0x40C9098 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_10 0x40C909C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_11 0x40C90A0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_12 0x40C90A4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_13 0x40C90A8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_14 0x40C90AC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_15 0x40C90B0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_16 0x40C90B4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_17 0x40C90B8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_18 0x40C90BC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_19 0x40C90C0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_20 0x40C90C4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_21 0x40C90C8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_22 0x40C90CC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_23 0x40C90D0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_0 0x40C90D4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_1 0x40C90D8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_2 0x40C90DC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_3 0x40C90E0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_4 0x40C90E4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_5 0x40C90E8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_6 0x40C90EC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_7 0x40C90F0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_PDMA_ENG_ADDR_0 0x40C90F4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_PDMA_ENG_ADDR_1 0x40C90F8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_ROT_ENG_ADDR_0 0x40C90FC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_ROT_ENG_ADDR_1 0x40C9100 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_0 0x40C9104 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_1 0x40C9108 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_2 0x40C910C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_3 0x40C9110 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_4 0x40C9114 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_5 0x40C9118 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_6 0x40C911C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_7 0x40C9120 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_8 0x40C9124 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_9 0x40C9128 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_10 0x40C912C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_11 0x40C9130 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_12 0x40C9134 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_13 0x40C9138 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_14 0x40C913C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_15 0x40C9140 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_MASK 0x40C9200 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_MASK 0x40C9204 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_MASK 0x40C9208 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_PDMA_ENG_MASK 0x40C920C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_ROT_ENG_MASK 0x40C9210 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_MASK 0x40C9214 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_0 0x40C9218 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_1 0x40C921C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_2 0x40C9220 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_3 0x40C9224 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_4 0x40C9228 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_5 0x40C922C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_6 0x40C9230 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_7 0x40C9234 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_0 0x40C9238 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_1 0x40C923C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_2 0x40C9240 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_3 0x40C9244 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_4 0x40C9248 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_5 0x40C924C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_6 0x40C9250 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_7 0x40C9254 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_8 0x40C9258 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_9 0x40C925C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_10 0x40C9260 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_11 0x40C9264 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_12 0x40C9268 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_13 0x40C926C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_0 0x40C9288 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_1 0x40C928C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_2 0x40C9290 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_3 0x40C9294 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_4 0x40C9298 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_5 0x40C929C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_0 0x40C92A0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_1 0x40C92A4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_2 0x40C92A8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_3 0x40C92AC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_4 0x40C92B0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_5 0x40C92B4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_0 0x40C92B8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_1 0x40C92BC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_2 0x40C92C0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_3 0x40C92C4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_4 0x40C92C8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_5 0x40C92CC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GENERAL_CFG 0x40C92D0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_BP_CFG 0x40C92D4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_0 0x40C92D8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_1 0x40C92DC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_2 0x40C92E0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_3 0x40C92E4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_4 0x40C92E8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_5 0x40C92EC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_6 0x40C92F0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_7 0x40C92F4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_8 0x40C92F8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_9 0x40C92FC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_10 0x40C9300 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_11 0x40C9304 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_12 0x40C9308 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_13 0x40C930C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_IN_GRP_TRANS_0 0x40C94A0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_IN_GRP_TRANS_1 0x40C94A4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_IN_GRP_TRANS_2 0x40C94A8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_STS 0x40C94AC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_OUT_RQ_CNT 0x40C94B0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_0 0x40C94B4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_1 0x40C94B8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_2 0x40C94BC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_3 0x40C94C0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_4 0x40C94C4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_5 0x40C94C8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_6 0x40C94CC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_7 0x40C94D0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_8 0x40C94D4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_9 0x40C94D8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_10 0x40C94DC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_11 0x40C94E0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_12 0x40C94E4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_13 0x40C94E8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_14 0x40C94EC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_15 0x40C94F0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_16 0x40C94F4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_17 0x40C94F8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_18 0x40C94FC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_19 0x40C9500 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_20 0x40C9504 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_21 0x40C9508 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_22 0x40C950C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_23 0x40C9510 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_24 0x40C9514 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_25 0x40C9518 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_26 0x40C951C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_27 0x40C9520 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_28 0x40C9524 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_29 0x40C9528 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_30 0x40C952C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_31 0x40C9530 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_32 0x40C9534 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_33 0x40C9538 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_34 0x40C953C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_35 0x40C9540 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_36 0x40C9544 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_37 0x40C9548 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_38 0x40C954C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_39 0x40C9550 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_40 0x40C9554 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_41 0x40C9558 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_42 0x40C955C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_43 0x40C9560 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_44 0x40C9564 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_45 0x40C9568 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_46 0x40C956C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_47 0x40C9570 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_48 0x40C9574 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_49 0x40C9578 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_50 0x40C957C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_51 0x40C9580 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_52 0x40C9584 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_53 0x40C9588 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_54 0x40C958C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_55 0x40C9590 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_56 0x40C9594 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_57 0x40C9598 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_58 0x40C959C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_59 0x40C95A0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_60 0x40C95A4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_61 0x40C95A8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_62 0x40C95AC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_63 0x40C95B0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_0 0x40C95B4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_1 0x40C95B8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_2 0x40C95BC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_3 0x40C95C0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_4 0x40C95C4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_5 0x40C95C8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_6 0x40C95CC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_7 0x40C95D0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_8 0x40C95D4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_9 0x40C95D8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_10 0x40C95DC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_11 0x40C95E0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_12 0x40C95E4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_13 0x40C95E8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_14 0x40C95EC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_15 0x40C95F0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_16 0x40C95F4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_17 0x40C95F8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_18 0x40C95FC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_19 0x40C9600 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_20 0x40C9604 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_21 0x40C9608 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_22 0x40C960C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_23 0x40C9610 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_24 0x40C9614 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_25 0x40C9618 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_26 0x40C961C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_27 0x40C9620 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_28 0x40C9624 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_29 0x40C9628 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_30 0x40C962C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_31 0x40C9630 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_32 0x40C9634 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_33 0x40C9638 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_34 0x40C963C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_35 0x40C9640 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_36 0x40C9644 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_37 0x40C9648 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_38 0x40C964C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_39 0x40C9650 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_40 0x40C9654 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_41 0x40C9658 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_42 0x40C965C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_43 0x40C9660 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_44 0x40C9664 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_45 0x40C9668 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_46 0x40C966C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_47 0x40C9670 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_48 0x40C9674 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_49 0x40C9678 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_50 0x40C967C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_51 0x40C9680 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_52 0x40C9684 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_53 0x40C9688 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_54 0x40C968C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_55 0x40C9690 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_56 0x40C9694 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_57 0x40C9698 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_58 0x40C969C + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_59 0x40C96A0 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_60 0x40C96A4 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_61 0x40C96A8 + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_62 0x40C96AC + +#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_63 0x40C96B0 + +#endif /* ASIC_REG_DCORE0_MME_QM_ARC_DUP_ENG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_axuser_nonsecured_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_axuser_nonsecured_regs.h new file mode 100644 index 000000000000..32089b8250ed --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_axuser_nonsecured_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_QM_AXUSER_NONSECURED_REGS_H_ +#define ASIC_REG_DCORE0_MME_QM_AXUSER_NONSECURED_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_QM_AXUSER_NONSECURED + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_ASID 0x40CAB80 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_MMU_BP 0x40CAB84 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x40CAB88 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x40CAB8C + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x40CAB90 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x40CAB94 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_QOS 0x40CAB98 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_RSVD 0x40CAB9C + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x40CABA0 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_CORE 0x40CABA4 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_E2E_COORD 0x40CABA8 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x40CABB0 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x40CABB4 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x40CABB8 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x40CABBC + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_LB_COORD 0x40CABC0 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_LB_LOCK 0x40CABC4 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_LB_RSVD 0x40CABC8 + +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_LB_OVRD 0x40CABCC + +#endif /* ASIC_REG_DCORE0_MME_QM_AXUSER_NONSECURED_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_axuser_secured_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_axuser_secured_regs.h new file mode 100644 index 000000000000..e168c1cc2a7d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_axuser_secured_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_QM_AXUSER_SECURED_REGS_H_ +#define ASIC_REG_DCORE0_MME_QM_AXUSER_SECURED_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_QM_AXUSER_SECURED + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_ASID 0x40CAB00 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_MMU_BP 0x40CAB04 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_STRONG_ORDER 0x40CAB08 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_NO_SNOOP 0x40CAB0C + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_WR_REDUCTION 0x40CAB10 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_RD_ATOMIC 0x40CAB14 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_QOS 0x40CAB18 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_RSVD 0x40CAB1C + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_EMEM_CPAGE 0x40CAB20 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_CORE 0x40CAB24 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_E2E_COORD 0x40CAB28 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_WR_OVRD_LO 0x40CAB30 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_WR_OVRD_HI 0x40CAB34 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_RD_OVRD_LO 0x40CAB38 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_RD_OVRD_HI 0x40CAB3C + +#define mmDCORE0_MME_QM_AXUSER_SECURED_LB_COORD 0x40CAB40 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_LB_LOCK 0x40CAB44 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_LB_RSVD 0x40CAB48 + +#define mmDCORE0_MME_QM_AXUSER_SECURED_LB_OVRD 0x40CAB4C + +#endif /* ASIC_REG_DCORE0_MME_QM_AXUSER_SECURED_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_cgm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_cgm_regs.h new file mode 100644 index 000000000000..543aba18ef68 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_cgm_regs.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_QM_CGM_REGS_H_ +#define ASIC_REG_DCORE0_MME_QM_CGM_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_QM_CGM + * (Prototype: QMAN_CGM) + ***************************************** + */ + +#define mmDCORE0_MME_QM_CGM_CFG 0x40CAD80 + +#define mmDCORE0_MME_QM_CGM_STS 0x40CAD84 + +#define mmDCORE0_MME_QM_CGM_CFG1 0x40CAD88 + +#endif /* ASIC_REG_DCORE0_MME_QM_CGM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_regs.h new file mode 100644 index 000000000000..c45583fcc2cf --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_regs.h @@ -0,0 +1,1057 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_QM_REGS_H_ +#define ASIC_REG_DCORE0_MME_QM_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_QM + * (Prototype: QMAN) + ***************************************** + */ + +#define mmDCORE0_MME_QM_GLBL_CFG0 0x40CA000 + +#define mmDCORE0_MME_QM_GLBL_CFG1 0x40CA004 + +#define mmDCORE0_MME_QM_GLBL_CFG2 0x40CA008 + +#define mmDCORE0_MME_QM_GLBL_ERR_CFG 0x40CA00C + +#define mmDCORE0_MME_QM_GLBL_ERR_CFG1 0x40CA010 + +#define mmDCORE0_MME_QM_GLBL_ERR_ARC_HALT_EN 0x40CA014 + +#define mmDCORE0_MME_QM_GLBL_AXCACHE 0x40CA018 + +#define mmDCORE0_MME_QM_GLBL_STS0 0x40CA01C + +#define mmDCORE0_MME_QM_GLBL_STS1 0x40CA020 + +#define mmDCORE0_MME_QM_GLBL_ERR_STS_0 0x40CA024 + +#define mmDCORE0_MME_QM_GLBL_ERR_STS_1 0x40CA028 + +#define mmDCORE0_MME_QM_GLBL_ERR_STS_2 0x40CA02C + +#define mmDCORE0_MME_QM_GLBL_ERR_STS_3 0x40CA030 + +#define mmDCORE0_MME_QM_GLBL_ERR_STS_4 0x40CA034 + +#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_0 0x40CA038 + +#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_1 0x40CA03C + +#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_2 0x40CA040 + +#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_3 0x40CA044 + +#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_4 0x40CA048 + +#define mmDCORE0_MME_QM_GLBL_PROT 0x40CA04C + +#define mmDCORE0_MME_QM_PQ_BASE_LO_0 0x40CA050 + +#define mmDCORE0_MME_QM_PQ_BASE_LO_1 0x40CA054 + +#define mmDCORE0_MME_QM_PQ_BASE_LO_2 0x40CA058 + +#define mmDCORE0_MME_QM_PQ_BASE_LO_3 0x40CA05C + +#define mmDCORE0_MME_QM_PQ_BASE_HI_0 0x40CA060 + +#define mmDCORE0_MME_QM_PQ_BASE_HI_1 0x40CA064 + +#define mmDCORE0_MME_QM_PQ_BASE_HI_2 0x40CA068 + +#define mmDCORE0_MME_QM_PQ_BASE_HI_3 0x40CA06C + +#define mmDCORE0_MME_QM_PQ_SIZE_0 0x40CA070 + +#define mmDCORE0_MME_QM_PQ_SIZE_1 0x40CA074 + +#define mmDCORE0_MME_QM_PQ_SIZE_2 0x40CA078 + +#define mmDCORE0_MME_QM_PQ_SIZE_3 0x40CA07C + +#define mmDCORE0_MME_QM_PQ_PI_0 0x40CA080 + +#define mmDCORE0_MME_QM_PQ_PI_1 0x40CA084 + +#define mmDCORE0_MME_QM_PQ_PI_2 0x40CA088 + +#define mmDCORE0_MME_QM_PQ_PI_3 0x40CA08C + +#define mmDCORE0_MME_QM_PQ_CI_0 0x40CA090 + +#define mmDCORE0_MME_QM_PQ_CI_1 0x40CA094 + +#define mmDCORE0_MME_QM_PQ_CI_2 0x40CA098 + +#define mmDCORE0_MME_QM_PQ_CI_3 0x40CA09C + +#define mmDCORE0_MME_QM_PQ_CFG0_0 0x40CA0A0 + +#define mmDCORE0_MME_QM_PQ_CFG0_1 0x40CA0A4 + +#define mmDCORE0_MME_QM_PQ_CFG0_2 0x40CA0A8 + +#define mmDCORE0_MME_QM_PQ_CFG0_3 0x40CA0AC + +#define mmDCORE0_MME_QM_PQ_CFG1_0 0x40CA0B0 + +#define mmDCORE0_MME_QM_PQ_CFG1_1 0x40CA0B4 + +#define mmDCORE0_MME_QM_PQ_CFG1_2 0x40CA0B8 + +#define mmDCORE0_MME_QM_PQ_CFG1_3 0x40CA0BC + +#define mmDCORE0_MME_QM_PQ_STS0_0 0x40CA0C0 + +#define mmDCORE0_MME_QM_PQ_STS0_1 0x40CA0C4 + +#define mmDCORE0_MME_QM_PQ_STS0_2 0x40CA0C8 + +#define mmDCORE0_MME_QM_PQ_STS0_3 0x40CA0CC + +#define mmDCORE0_MME_QM_PQ_STS1_0 0x40CA0D0 + +#define mmDCORE0_MME_QM_PQ_STS1_1 0x40CA0D4 + +#define mmDCORE0_MME_QM_PQ_STS1_2 0x40CA0D8 + +#define mmDCORE0_MME_QM_PQ_STS1_3 0x40CA0DC + +#define mmDCORE0_MME_QM_CQ_CFG0_0 0x40CA0E0 + +#define mmDCORE0_MME_QM_CQ_CFG0_1 0x40CA0E4 + +#define mmDCORE0_MME_QM_CQ_CFG0_2 0x40CA0E8 + +#define mmDCORE0_MME_QM_CQ_CFG0_3 0x40CA0EC + +#define mmDCORE0_MME_QM_CQ_CFG0_4 0x40CA0F0 + +#define mmDCORE0_MME_QM_CQ_STS0_0 0x40CA0F4 + +#define mmDCORE0_MME_QM_CQ_STS0_1 0x40CA0F8 + +#define mmDCORE0_MME_QM_CQ_STS0_2 0x40CA0FC + +#define mmDCORE0_MME_QM_CQ_STS0_3 0x40CA100 + +#define mmDCORE0_MME_QM_CQ_STS0_4 0x40CA104 + +#define mmDCORE0_MME_QM_CQ_CFG1_0 0x40CA108 + +#define mmDCORE0_MME_QM_CQ_CFG1_1 0x40CA10C + +#define mmDCORE0_MME_QM_CQ_CFG1_2 0x40CA110 + +#define mmDCORE0_MME_QM_CQ_CFG1_3 0x40CA114 + +#define mmDCORE0_MME_QM_CQ_CFG1_4 0x40CA118 + +#define mmDCORE0_MME_QM_CQ_STS1_0 0x40CA11C + +#define mmDCORE0_MME_QM_CQ_STS1_1 0x40CA120 + +#define mmDCORE0_MME_QM_CQ_STS1_2 0x40CA124 + +#define mmDCORE0_MME_QM_CQ_STS1_3 0x40CA128 + +#define mmDCORE0_MME_QM_CQ_STS1_4 0x40CA12C + +#define mmDCORE0_MME_QM_CQ_PTR_LO_0 0x40CA150 + +#define mmDCORE0_MME_QM_CQ_PTR_HI_0 0x40CA154 + +#define mmDCORE0_MME_QM_CQ_TSIZE_0 0x40CA158 + +#define mmDCORE0_MME_QM_CQ_CTL_0 0x40CA15C + +#define mmDCORE0_MME_QM_CQ_PTR_LO_1 0x40CA160 + +#define mmDCORE0_MME_QM_CQ_PTR_HI_1 0x40CA164 + +#define mmDCORE0_MME_QM_CQ_TSIZE_1 0x40CA168 + +#define mmDCORE0_MME_QM_CQ_CTL_1 0x40CA16C + +#define mmDCORE0_MME_QM_CQ_PTR_LO_2 0x40CA170 + +#define mmDCORE0_MME_QM_CQ_PTR_HI_2 0x40CA174 + +#define mmDCORE0_MME_QM_CQ_TSIZE_2 0x40CA178 + +#define mmDCORE0_MME_QM_CQ_CTL_2 0x40CA17C + +#define mmDCORE0_MME_QM_CQ_PTR_LO_3 0x40CA180 + +#define mmDCORE0_MME_QM_CQ_PTR_HI_3 0x40CA184 + +#define mmDCORE0_MME_QM_CQ_TSIZE_3 0x40CA188 + +#define mmDCORE0_MME_QM_CQ_CTL_3 0x40CA18C + +#define mmDCORE0_MME_QM_CQ_PTR_LO_4 0x40CA190 + +#define mmDCORE0_MME_QM_CQ_PTR_HI_4 0x40CA194 + +#define mmDCORE0_MME_QM_CQ_TSIZE_4 0x40CA198 + +#define mmDCORE0_MME_QM_CQ_CTL_4 0x40CA19C + +#define mmDCORE0_MME_QM_CQ_TSIZE_STS_0 0x40CA1A0 + +#define mmDCORE0_MME_QM_CQ_TSIZE_STS_1 0x40CA1A4 + +#define mmDCORE0_MME_QM_CQ_TSIZE_STS_2 0x40CA1A8 + +#define mmDCORE0_MME_QM_CQ_TSIZE_STS_3 0x40CA1AC + +#define mmDCORE0_MME_QM_CQ_TSIZE_STS_4 0x40CA1B0 + +#define mmDCORE0_MME_QM_CQ_PTR_LO_STS_0 0x40CA1B4 + +#define mmDCORE0_MME_QM_CQ_PTR_LO_STS_1 0x40CA1B8 + +#define mmDCORE0_MME_QM_CQ_PTR_LO_STS_2 0x40CA1BC + +#define mmDCORE0_MME_QM_CQ_PTR_LO_STS_3 0x40CA1C0 + +#define mmDCORE0_MME_QM_CQ_PTR_LO_STS_4 0x40CA1C4 + +#define mmDCORE0_MME_QM_CQ_PTR_HI_STS_0 0x40CA1C8 + +#define mmDCORE0_MME_QM_CQ_PTR_HI_STS_1 0x40CA1CC + +#define mmDCORE0_MME_QM_CQ_PTR_HI_STS_2 0x40CA1D0 + +#define mmDCORE0_MME_QM_CQ_PTR_HI_STS_3 0x40CA1D4 + +#define mmDCORE0_MME_QM_CQ_PTR_HI_STS_4 0x40CA1D8 + +#define mmDCORE0_MME_QM_CQ_IFIFO_STS_0 0x40CA1DC + +#define mmDCORE0_MME_QM_CQ_IFIFO_STS_1 0x40CA1E0 + +#define mmDCORE0_MME_QM_CQ_IFIFO_STS_2 0x40CA1E4 + +#define mmDCORE0_MME_QM_CQ_IFIFO_STS_3 0x40CA1E8 + +#define mmDCORE0_MME_QM_CQ_IFIFO_STS_4 0x40CA1EC + +#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_0 0x40CA1F0 + +#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_1 0x40CA1F4 + +#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_2 0x40CA1F8 + +#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_3 0x40CA1FC + +#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_4 0x40CA200 + +#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_0 0x40CA204 + +#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_1 0x40CA208 + +#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_2 0x40CA20C + +#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_3 0x40CA210 + +#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_4 0x40CA214 + +#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_0 0x40CA218 + +#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_1 0x40CA21C + +#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_2 0x40CA220 + +#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_3 0x40CA224 + +#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_4 0x40CA228 + +#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_0 0x40CA22C + +#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_1 0x40CA230 + +#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_2 0x40CA234 + +#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_3 0x40CA238 + +#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_4 0x40CA23C + +#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_0 0x40CA240 + +#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_1 0x40CA244 + +#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_2 0x40CA248 + +#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_3 0x40CA24C + +#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_4 0x40CA250 + +#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_0 0x40CA254 + +#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_1 0x40CA258 + +#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_2 0x40CA25C + +#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_3 0x40CA260 + +#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_4 0x40CA264 + +#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_0 0x40CA268 + +#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_1 0x40CA26C + +#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_2 0x40CA270 + +#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_3 0x40CA274 + +#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_4 0x40CA278 + +#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_0 0x40CA27C + +#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_1 0x40CA280 + +#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_2 0x40CA284 + +#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_3 0x40CA288 + +#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_4 0x40CA28C + +#define mmDCORE0_MME_QM_CP_FENCE0_RDATA_0 0x40CA290 + +#define mmDCORE0_MME_QM_CP_FENCE0_RDATA_1 0x40CA294 + +#define mmDCORE0_MME_QM_CP_FENCE0_RDATA_2 0x40CA298 + +#define mmDCORE0_MME_QM_CP_FENCE0_RDATA_3 0x40CA29C + +#define mmDCORE0_MME_QM_CP_FENCE0_RDATA_4 0x40CA2A0 + +#define mmDCORE0_MME_QM_CP_FENCE1_RDATA_0 0x40CA2A4 + +#define mmDCORE0_MME_QM_CP_FENCE1_RDATA_1 0x40CA2A8 + +#define mmDCORE0_MME_QM_CP_FENCE1_RDATA_2 0x40CA2AC + +#define mmDCORE0_MME_QM_CP_FENCE1_RDATA_3 0x40CA2B0 + +#define mmDCORE0_MME_QM_CP_FENCE1_RDATA_4 0x40CA2B4 + +#define mmDCORE0_MME_QM_CP_FENCE2_RDATA_0 0x40CA2B8 + +#define mmDCORE0_MME_QM_CP_FENCE2_RDATA_1 0x40CA2BC + +#define mmDCORE0_MME_QM_CP_FENCE2_RDATA_2 0x40CA2C0 + +#define mmDCORE0_MME_QM_CP_FENCE2_RDATA_3 0x40CA2C4 + +#define mmDCORE0_MME_QM_CP_FENCE2_RDATA_4 0x40CA2C8 + +#define mmDCORE0_MME_QM_CP_FENCE3_RDATA_0 0x40CA2CC + +#define mmDCORE0_MME_QM_CP_FENCE3_RDATA_1 0x40CA2D0 + +#define mmDCORE0_MME_QM_CP_FENCE3_RDATA_2 0x40CA2D4 + +#define mmDCORE0_MME_QM_CP_FENCE3_RDATA_3 0x40CA2D8 + +#define mmDCORE0_MME_QM_CP_FENCE3_RDATA_4 0x40CA2DC + +#define mmDCORE0_MME_QM_CP_FENCE0_CNT_0 0x40CA2E0 + +#define mmDCORE0_MME_QM_CP_FENCE0_CNT_1 0x40CA2E4 + +#define mmDCORE0_MME_QM_CP_FENCE0_CNT_2 0x40CA2E8 + +#define mmDCORE0_MME_QM_CP_FENCE0_CNT_3 0x40CA2EC + +#define mmDCORE0_MME_QM_CP_FENCE0_CNT_4 0x40CA2F0 + +#define mmDCORE0_MME_QM_CP_FENCE1_CNT_0 0x40CA2F4 + +#define mmDCORE0_MME_QM_CP_FENCE1_CNT_1 0x40CA2F8 + +#define mmDCORE0_MME_QM_CP_FENCE1_CNT_2 0x40CA2FC + +#define mmDCORE0_MME_QM_CP_FENCE1_CNT_3 0x40CA300 + +#define mmDCORE0_MME_QM_CP_FENCE1_CNT_4 0x40CA304 + +#define mmDCORE0_MME_QM_CP_FENCE2_CNT_0 0x40CA308 + +#define mmDCORE0_MME_QM_CP_FENCE2_CNT_1 0x40CA30C + +#define mmDCORE0_MME_QM_CP_FENCE2_CNT_2 0x40CA310 + +#define mmDCORE0_MME_QM_CP_FENCE2_CNT_3 0x40CA314 + +#define mmDCORE0_MME_QM_CP_FENCE2_CNT_4 0x40CA318 + +#define mmDCORE0_MME_QM_CP_FENCE3_CNT_0 0x40CA31C + +#define mmDCORE0_MME_QM_CP_FENCE3_CNT_1 0x40CA320 + +#define mmDCORE0_MME_QM_CP_FENCE3_CNT_2 0x40CA324 + +#define mmDCORE0_MME_QM_CP_FENCE3_CNT_3 0x40CA328 + +#define mmDCORE0_MME_QM_CP_FENCE3_CNT_4 0x40CA32C + +#define mmDCORE0_MME_QM_CP_BARRIER_CFG 0x40CA330 + +#define mmDCORE0_MME_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0x40CA334 + +#define mmDCORE0_MME_QM_CP_LDMA_DST_BASE_LO_OFFSET 0x40CA338 + +#define mmDCORE0_MME_QM_CP_LDMA_TSIZE_OFFSET 0x40CA33C + +#define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_0 0x40CA340 + +#define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_1 0x40CA344 + +#define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_2 0x40CA348 + +#define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_3 0x40CA34C + +#define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_4 0x40CA350 + +#define mmDCORE0_MME_QM_CP_STS_0 0x40CA368 + +#define mmDCORE0_MME_QM_CP_STS_1 0x40CA36C + +#define mmDCORE0_MME_QM_CP_STS_2 0x40CA370 + +#define mmDCORE0_MME_QM_CP_STS_3 0x40CA374 + +#define mmDCORE0_MME_QM_CP_STS_4 0x40CA378 + +#define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_0 0x40CA37C + +#define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_1 0x40CA380 + +#define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_2 0x40CA384 + +#define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_3 0x40CA388 + +#define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_4 0x40CA38C + +#define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_0 0x40CA390 + +#define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_1 0x40CA394 + +#define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_2 0x40CA398 + +#define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_3 0x40CA39C + +#define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_4 0x40CA3A0 + +#define mmDCORE0_MME_QM_CP_PRED_0 0x40CA3A4 + +#define mmDCORE0_MME_QM_CP_PRED_1 0x40CA3A8 + +#define mmDCORE0_MME_QM_CP_PRED_2 0x40CA3AC + +#define mmDCORE0_MME_QM_CP_PRED_3 0x40CA3B0 + +#define mmDCORE0_MME_QM_CP_PRED_4 0x40CA3B4 + +#define mmDCORE0_MME_QM_CP_PRED_UPEN_0 0x40CA3B8 + +#define mmDCORE0_MME_QM_CP_PRED_UPEN_1 0x40CA3BC + +#define mmDCORE0_MME_QM_CP_PRED_UPEN_2 0x40CA3C0 + +#define mmDCORE0_MME_QM_CP_PRED_UPEN_3 0x40CA3C4 + +#define mmDCORE0_MME_QM_CP_PRED_UPEN_4 0x40CA3C8 + +#define mmDCORE0_MME_QM_CP_DBG_0_0 0x40CA3CC + +#define mmDCORE0_MME_QM_CP_DBG_0_1 0x40CA3D0 + +#define mmDCORE0_MME_QM_CP_DBG_0_2 0x40CA3D4 + +#define mmDCORE0_MME_QM_CP_DBG_0_3 0x40CA3D8 + +#define mmDCORE0_MME_QM_CP_DBG_0_4 0x40CA3DC + +#define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_0 0x40CA3E0 + +#define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_1 0x40CA3E4 + +#define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_2 0x40CA3E8 + +#define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_3 0x40CA3EC + +#define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_4 0x40CA3F0 + +#define mmDCORE0_MME_QM_CP_IN_DATA_LO_0 0x40CA3F4 + +#define mmDCORE0_MME_QM_CP_IN_DATA_LO_1 0x40CA3F8 + +#define mmDCORE0_MME_QM_CP_IN_DATA_LO_2 0x40CA3FC + +#define mmDCORE0_MME_QM_CP_IN_DATA_LO_3 0x40CA400 + +#define mmDCORE0_MME_QM_CP_IN_DATA_LO_4 0x40CA404 + +#define mmDCORE0_MME_QM_CP_IN_DATA_HI_0 0x40CA408 + +#define mmDCORE0_MME_QM_CP_IN_DATA_HI_1 0x40CA40C + +#define mmDCORE0_MME_QM_CP_IN_DATA_HI_2 0x40CA410 + +#define mmDCORE0_MME_QM_CP_IN_DATA_HI_3 0x40CA414 + +#define mmDCORE0_MME_QM_CP_IN_DATA_HI_4 0x40CA418 + +#define mmDCORE0_MME_QM_PQC_HBW_BASE_LO_0 0x40CA41C + +#define mmDCORE0_MME_QM_PQC_HBW_BASE_LO_1 0x40CA420 + +#define mmDCORE0_MME_QM_PQC_HBW_BASE_LO_2 0x40CA424 + +#define mmDCORE0_MME_QM_PQC_HBW_BASE_LO_3 0x40CA428 + +#define mmDCORE0_MME_QM_PQC_HBW_BASE_HI_0 0x40CA42C + +#define mmDCORE0_MME_QM_PQC_HBW_BASE_HI_1 0x40CA430 + +#define mmDCORE0_MME_QM_PQC_HBW_BASE_HI_2 0x40CA434 + +#define mmDCORE0_MME_QM_PQC_HBW_BASE_HI_3 0x40CA438 + +#define mmDCORE0_MME_QM_PQC_SIZE_0 0x40CA43C + +#define mmDCORE0_MME_QM_PQC_SIZE_1 0x40CA440 + +#define mmDCORE0_MME_QM_PQC_SIZE_2 0x40CA444 + +#define mmDCORE0_MME_QM_PQC_SIZE_3 0x40CA448 + +#define mmDCORE0_MME_QM_PQC_PI_0 0x40CA44C + +#define mmDCORE0_MME_QM_PQC_PI_1 0x40CA450 + +#define mmDCORE0_MME_QM_PQC_PI_2 0x40CA454 + +#define mmDCORE0_MME_QM_PQC_PI_3 0x40CA458 + +#define mmDCORE0_MME_QM_PQC_LBW_WDATA_0 0x40CA45C + +#define mmDCORE0_MME_QM_PQC_LBW_WDATA_1 0x40CA460 + +#define mmDCORE0_MME_QM_PQC_LBW_WDATA_2 0x40CA464 + +#define mmDCORE0_MME_QM_PQC_LBW_WDATA_3 0x40CA468 + +#define mmDCORE0_MME_QM_PQC_LBW_BASE_LO_0 0x40CA46C + +#define mmDCORE0_MME_QM_PQC_LBW_BASE_LO_1 0x40CA470 + +#define mmDCORE0_MME_QM_PQC_LBW_BASE_LO_2 0x40CA474 + +#define mmDCORE0_MME_QM_PQC_LBW_BASE_LO_3 0x40CA478 + +#define mmDCORE0_MME_QM_PQC_LBW_BASE_HI_0 0x40CA47C + +#define mmDCORE0_MME_QM_PQC_LBW_BASE_HI_1 0x40CA480 + +#define mmDCORE0_MME_QM_PQC_LBW_BASE_HI_2 0x40CA484 + +#define mmDCORE0_MME_QM_PQC_LBW_BASE_HI_3 0x40CA488 + +#define mmDCORE0_MME_QM_PQC_CFG 0x40CA48C + +#define mmDCORE0_MME_QM_PQC_SECURE_PUSH_IND 0x40CA490 + +#define mmDCORE0_MME_QM_ARB_MASK 0x40CA4A0 + +#define mmDCORE0_MME_QM_ARB_CFG_0 0x40CA4A4 + +#define mmDCORE0_MME_QM_ARB_CHOICE_Q_PUSH 0x40CA4A8 + +#define mmDCORE0_MME_QM_ARB_WRR_WEIGHT_0 0x40CA4AC + +#define mmDCORE0_MME_QM_ARB_WRR_WEIGHT_1 0x40CA4B0 + +#define mmDCORE0_MME_QM_ARB_WRR_WEIGHT_2 0x40CA4B4 + +#define mmDCORE0_MME_QM_ARB_WRR_WEIGHT_3 0x40CA4B8 + +#define mmDCORE0_MME_QM_ARB_CFG_1 0x40CA4BC + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_0 0x40CA4C0 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_1 0x40CA4C4 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_2 0x40CA4C8 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_3 0x40CA4CC + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_4 0x40CA4D0 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_5 0x40CA4D4 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_6 0x40CA4D8 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_7 0x40CA4DC + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_8 0x40CA4E0 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_9 0x40CA4E4 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_10 0x40CA4E8 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_11 0x40CA4EC + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_12 0x40CA4F0 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_13 0x40CA4F4 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_14 0x40CA4F8 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_15 0x40CA4FC + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_16 0x40CA500 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_17 0x40CA504 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_18 0x40CA508 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_19 0x40CA50C + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_20 0x40CA510 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_21 0x40CA514 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_22 0x40CA518 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_23 0x40CA51C + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_24 0x40CA520 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_25 0x40CA524 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_26 0x40CA528 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_27 0x40CA52C + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_28 0x40CA530 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_29 0x40CA534 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_30 0x40CA538 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_31 0x40CA53C + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_32 0x40CA540 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_33 0x40CA544 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_34 0x40CA548 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_35 0x40CA54C + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_36 0x40CA550 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_37 0x40CA554 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_38 0x40CA558 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_39 0x40CA55C + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_40 0x40CA560 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_41 0x40CA564 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_42 0x40CA568 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_43 0x40CA56C + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_44 0x40CA570 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_45 0x40CA574 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_46 0x40CA578 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_47 0x40CA57C + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_48 0x40CA580 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_49 0x40CA584 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_50 0x40CA588 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_51 0x40CA58C + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_52 0x40CA590 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_53 0x40CA594 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_54 0x40CA598 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_55 0x40CA59C + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_56 0x40CA5A0 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_57 0x40CA5A4 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_58 0x40CA5A8 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_59 0x40CA5AC + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_60 0x40CA5B0 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_61 0x40CA5B4 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_62 0x40CA5B8 + +#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_63 0x40CA5BC + +#define mmDCORE0_MME_QM_ARB_MST_CRED_INC 0x40CA5E0 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_0 0x40CA5E4 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_1 0x40CA5E8 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_2 0x40CA5EC + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_3 0x40CA5F0 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_4 0x40CA5F4 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_5 0x40CA5F8 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_6 0x40CA5FC + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_7 0x40CA600 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_8 0x40CA604 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_9 0x40CA608 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_10 0x40CA60C + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_11 0x40CA610 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_12 0x40CA614 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_13 0x40CA618 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_14 0x40CA61C + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_15 0x40CA620 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_16 0x40CA624 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_17 0x40CA628 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_18 0x40CA62C + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_19 0x40CA630 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_20 0x40CA634 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_21 0x40CA638 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_22 0x40CA63C + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_23 0x40CA640 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_24 0x40CA644 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_25 0x40CA648 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_26 0x40CA64C + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_27 0x40CA650 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_28 0x40CA654 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_29 0x40CA658 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_30 0x40CA65C + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_31 0x40CA660 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_32 0x40CA664 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_33 0x40CA668 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_34 0x40CA66C + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_35 0x40CA670 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_36 0x40CA674 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_37 0x40CA678 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_38 0x40CA67C + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_39 0x40CA680 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_40 0x40CA684 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_41 0x40CA688 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_42 0x40CA68C + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_43 0x40CA690 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_44 0x40CA694 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_45 0x40CA698 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_46 0x40CA69C + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_47 0x40CA6A0 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_48 0x40CA6A4 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_49 0x40CA6A8 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_50 0x40CA6AC + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_51 0x40CA6B0 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_52 0x40CA6B4 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_53 0x40CA6B8 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_54 0x40CA6BC + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_55 0x40CA6C0 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_56 0x40CA6C4 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_57 0x40CA6C8 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_58 0x40CA6CC + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_59 0x40CA6D0 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_60 0x40CA6D4 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_61 0x40CA6D8 + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_62 0x40CA6DC + +#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_63 0x40CA6E0 + +#define mmDCORE0_MME_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x40CA704 + +#define mmDCORE0_MME_QM_ARB_MST_SLAVE_EN 0x40CA708 + +#define mmDCORE0_MME_QM_ARB_MST_SLAVE_EN_1 0x40CA70C + +#define mmDCORE0_MME_QM_ARB_SLV_CHOICE_WDT 0x40CA710 + +#define mmDCORE0_MME_QM_ARB_SLV_ID 0x40CA714 + +#define mmDCORE0_MME_QM_ARB_MST_QUIET_PER 0x40CA718 + +#define mmDCORE0_MME_QM_ARB_MSG_MAX_INFLIGHT 0x40CA744 + +#define mmDCORE0_MME_QM_ARB_BASE_LO 0x40CA754 + +#define mmDCORE0_MME_QM_ARB_BASE_HI 0x40CA758 + +#define mmDCORE0_MME_QM_ARB_STATE_STS 0x40CA780 + +#define mmDCORE0_MME_QM_ARB_CHOICE_FULLNESS_STS 0x40CA784 + +#define mmDCORE0_MME_QM_ARB_MSG_STS 0x40CA788 + +#define mmDCORE0_MME_QM_ARB_SLV_CHOICE_Q_HEAD 0x40CA78C + +#define mmDCORE0_MME_QM_ARB_ERR_CAUSE 0x40CA79C + +#define mmDCORE0_MME_QM_ARB_ERR_MSG_EN 0x40CA7A0 + +#define mmDCORE0_MME_QM_ARB_ERR_STS_DRP 0x40CA7A8 + +#define mmDCORE0_MME_QM_ARB_MST_CRED_STS 0x40CA7B0 + +#define mmDCORE0_MME_QM_ARB_MST_CRED_STS_1 0x40CA7B4 + +#define mmDCORE0_MME_QM_CSMR_STRICT_PRIO_CFG 0x40CA7FC + +#define mmDCORE0_MME_QM_ARC_CQ_CFG0 0x40CA800 + +#define mmDCORE0_MME_QM_ARC_CQ_CFG1 0x40CA804 + +#define mmDCORE0_MME_QM_ARC_CQ_PTR_LO 0x40CA808 + +#define mmDCORE0_MME_QM_ARC_CQ_PTR_HI 0x40CA80C + +#define mmDCORE0_MME_QM_ARC_CQ_TSIZE 0x40CA810 + +#define mmDCORE0_MME_QM_ARC_CQ_CTL 0x40CA814 + +#define mmDCORE0_MME_QM_ARC_CQ_IFIFO_STS 0x40CA81C + +#define mmDCORE0_MME_QM_ARC_CQ_STS0 0x40CA820 + +#define mmDCORE0_MME_QM_ARC_CQ_STS1 0x40CA824 + +#define mmDCORE0_MME_QM_ARC_CQ_TSIZE_STS 0x40CA828 + +#define mmDCORE0_MME_QM_ARC_CQ_PTR_LO_STS 0x40CA82C + +#define mmDCORE0_MME_QM_ARC_CQ_PTR_HI_STS 0x40CA830 + +#define mmDCORE0_MME_QM_CP_WR_ARC_ADDR_HI 0x40CA834 + +#define mmDCORE0_MME_QM_CP_WR_ARC_ADDR_LO 0x40CA838 + +#define mmDCORE0_MME_QM_ARC_CQ_IFIFO_MSG_BASE_HI 0x40CA83C + +#define mmDCORE0_MME_QM_ARC_CQ_IFIFO_MSG_BASE_LO 0x40CA840 + +#define mmDCORE0_MME_QM_ARC_CQ_CTL_MSG_BASE_HI 0x40CA844 + +#define mmDCORE0_MME_QM_ARC_CQ_CTL_MSG_BASE_LO 0x40CA848 + +#define mmDCORE0_MME_QM_CQ_IFIFO_MSG_BASE_HI 0x40CA84C + +#define mmDCORE0_MME_QM_CQ_IFIFO_MSG_BASE_LO 0x40CA850 + +#define mmDCORE0_MME_QM_CQ_CTL_MSG_BASE_HI 0x40CA854 + +#define mmDCORE0_MME_QM_CQ_CTL_MSG_BASE_LO 0x40CA858 + +#define mmDCORE0_MME_QM_ADDR_OVRD 0x40CA85C + +#define mmDCORE0_MME_QM_CQ_IFIFO_CI_0 0x40CA860 + +#define mmDCORE0_MME_QM_CQ_IFIFO_CI_1 0x40CA864 + +#define mmDCORE0_MME_QM_CQ_IFIFO_CI_2 0x40CA868 + +#define mmDCORE0_MME_QM_CQ_IFIFO_CI_3 0x40CA86C + +#define mmDCORE0_MME_QM_CQ_IFIFO_CI_4 0x40CA870 + +#define mmDCORE0_MME_QM_ARC_CQ_IFIFO_CI 0x40CA874 + +#define mmDCORE0_MME_QM_CQ_CTL_CI_0 0x40CA878 + +#define mmDCORE0_MME_QM_CQ_CTL_CI_1 0x40CA87C + +#define mmDCORE0_MME_QM_CQ_CTL_CI_2 0x40CA880 + +#define mmDCORE0_MME_QM_CQ_CTL_CI_3 0x40CA884 + +#define mmDCORE0_MME_QM_CQ_CTL_CI_4 0x40CA888 + +#define mmDCORE0_MME_QM_ARC_CQ_CTL_CI 0x40CA88C + +#define mmDCORE0_MME_QM_CP_CFG 0x40CA890 + +#define mmDCORE0_MME_QM_CP_EXT_SWITCH 0x40CA894 + +#define mmDCORE0_MME_QM_CP_SWITCH_WD_SET 0x40CA898 + +#define mmDCORE0_MME_QM_CP_SWITCH_WD 0x40CA89C + +#define mmDCORE0_MME_QM_ARC_LB_ADDR_BASE_LO 0x40CA8A4 + +#define mmDCORE0_MME_QM_ARC_LB_ADDR_BASE_HI 0x40CA8A8 + +#define mmDCORE0_MME_QM_ENGINE_BASE_ADDR_HI 0x40CA8AC + +#define mmDCORE0_MME_QM_ENGINE_BASE_ADDR_LO 0x40CA8B0 + +#define mmDCORE0_MME_QM_ENGINE_ADDR_RANGE_SIZE 0x40CA8B4 + +#define mmDCORE0_MME_QM_QM_ARC_AUX_BASE_ADDR_HI 0x40CA8B8 + +#define mmDCORE0_MME_QM_QM_ARC_AUX_BASE_ADDR_LO 0x40CA8BC + +#define mmDCORE0_MME_QM_QM_BASE_ADDR_HI 0x40CA8C0 + +#define mmDCORE0_MME_QM_QM_BASE_ADDR_LO 0x40CA8C4 + +#define mmDCORE0_MME_QM_ARC_PQC_SECURE_PUSH_IND 0x40CA8C8 + +#define mmDCORE0_MME_QM_PQC_STS_0_0 0x40CA8D0 + +#define mmDCORE0_MME_QM_PQC_STS_0_1 0x40CA8D4 + +#define mmDCORE0_MME_QM_PQC_STS_0_2 0x40CA8D8 + +#define mmDCORE0_MME_QM_PQC_STS_0_3 0x40CA8DC + +#define mmDCORE0_MME_QM_PQC_STS_1_0 0x40CA8E0 + +#define mmDCORE0_MME_QM_PQC_STS_1_1 0x40CA8E4 + +#define mmDCORE0_MME_QM_PQC_STS_1_2 0x40CA8E8 + +#define mmDCORE0_MME_QM_PQC_STS_1_3 0x40CA8EC + +#define mmDCORE0_MME_QM_SEI_STATUS 0x40CA8F0 + +#define mmDCORE0_MME_QM_SEI_MASK 0x40CA8F4 + +#define mmDCORE0_MME_QM_GLBL_ERR_ADDR_LO 0x40CAD00 + +#define mmDCORE0_MME_QM_GLBL_ERR_ADDR_HI 0x40CAD04 + +#define mmDCORE0_MME_QM_GLBL_ERR_WDATA 0x40CAD08 + +#define mmDCORE0_MME_QM_L2H_MASK_LO 0x40CAD14 + +#define mmDCORE0_MME_QM_L2H_MASK_HI 0x40CAD18 + +#define mmDCORE0_MME_QM_L2H_CMPR_LO 0x40CAD1C + +#define mmDCORE0_MME_QM_L2H_CMPR_HI 0x40CAD20 + +#define mmDCORE0_MME_QM_LOCAL_RANGE_BASE 0x40CAD24 + +#define mmDCORE0_MME_QM_LOCAL_RANGE_SIZE 0x40CAD28 + +#define mmDCORE0_MME_QM_HBW_RD_RATE_LIM_CFG_1 0x40CAD30 + +#define mmDCORE0_MME_QM_LBW_WR_RATE_LIM_CFG_0 0x40CAD34 + +#define mmDCORE0_MME_QM_LBW_WR_RATE_LIM_CFG_1 0x40CAD38 + +#define mmDCORE0_MME_QM_HBW_RD_RATE_LIM_CFG_0 0x40CAD3C + +#define mmDCORE0_MME_QM_IND_GW_APB_CFG 0x40CAD40 + +#define mmDCORE0_MME_QM_IND_GW_APB_WDATA 0x40CAD44 + +#define mmDCORE0_MME_QM_IND_GW_APB_RDATA 0x40CAD48 + +#define mmDCORE0_MME_QM_IND_GW_APB_STATUS 0x40CAD4C + +#define mmDCORE0_MME_QM_PERF_CNT_FREE_LO 0x40CAD60 + +#define mmDCORE0_MME_QM_PERF_CNT_FREE_HI 0x40CAD64 + +#define mmDCORE0_MME_QM_PERF_CNT_IDLE_LO 0x40CAD68 + +#define mmDCORE0_MME_QM_PERF_CNT_IDLE_HI 0x40CAD6C + +#define mmDCORE0_MME_QM_PERF_CNT_CFG 0x40CAD70 + +#endif /* ASIC_REG_DCORE0_MME_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_sbte0_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_sbte0_masks.h new file mode 100644 index 000000000000..077ae5232790 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_sbte0_masks.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_SBTE0_MASKS_H_ +#define ASIC_REG_DCORE0_MME_SBTE0_MASKS_H_ + +/* + ***************************************** + * DCORE0_MME_SBTE0 + * (Prototype: SB) + ***************************************** + */ + +/* DCORE0_MME_SBTE0_MAX_SIZE */ +#define DCORE0_MME_SBTE0_MAX_SIZE_DATA_SHIFT 0 +#define DCORE0_MME_SBTE0_MAX_SIZE_DATA_MASK 0xFFFF +#define DCORE0_MME_SBTE0_MAX_SIZE_MD_SHIFT 16 +#define DCORE0_MME_SBTE0_MAX_SIZE_MD_MASK 0xFFFF0000 + +/* DCORE0_MME_SBTE0_FORCE_MISS */ +#define DCORE0_MME_SBTE0_FORCE_MISS_R_SHIFT 0 +#define DCORE0_MME_SBTE0_FORCE_MISS_R_MASK 0x1 + +/* DCORE0_MME_SBTE0_MAX */ +#define DCORE0_MME_SBTE0_MAX_OS_SHIFT 0 +#define DCORE0_MME_SBTE0_MAX_OS_MASK 0xFFFF + +/* DCORE0_MME_SBTE0_RL */ +#define DCORE0_MME_SBTE0_RL_SATURATION_SHIFT 0 +#define DCORE0_MME_SBTE0_RL_SATURATION_MASK 0xFF +#define DCORE0_MME_SBTE0_RL_TIMEOUT_SHIFT 8 +#define DCORE0_MME_SBTE0_RL_TIMEOUT_MASK 0xFF00 +#define DCORE0_MME_SBTE0_RL_RATE_LIMITER_EN_SHIFT 16 +#define DCORE0_MME_SBTE0_RL_RATE_LIMITER_EN_MASK 0x10000 + +/* DCORE0_MME_SBTE0_SB_STALL */ +#define DCORE0_MME_SBTE0_SB_STALL_R_SHIFT 0 +#define DCORE0_MME_SBTE0_SB_STALL_R_MASK 0x1 + +/* DCORE0_MME_SBTE0_INTR */ +#define DCORE0_MME_SBTE0_INTR_I0_SHIFT 0 +#define DCORE0_MME_SBTE0_INTR_I0_MASK 0x1 + +/* DCORE0_MME_SBTE0_ARUSER */ +#define DCORE0_MME_SBTE0_ARUSER_ASID_SHIFT 0 +#define DCORE0_MME_SBTE0_ARUSER_ASID_MASK 0x3FF +#define DCORE0_MME_SBTE0_ARUSER_MMBP_SHIFT 10 +#define DCORE0_MME_SBTE0_ARUSER_MMBP_MASK 0x400 +#define DCORE0_MME_SBTE0_ARUSER_DUMMY_SHIFT 11 +#define DCORE0_MME_SBTE0_ARUSER_DUMMY_MASK 0xFFFFF800 + +/* DCORE0_MME_SBTE0_ARCACHE */ +#define DCORE0_MME_SBTE0_ARCACHE_N_SHIFT 0 +#define DCORE0_MME_SBTE0_ARCACHE_N_MASK 0xF + +/* DCORE0_MME_SBTE0_STATUS */ +#define DCORE0_MME_SBTE0_STATUS_DROP_CNT_SHIFT 0 +#define DCORE0_MME_SBTE0_STATUS_DROP_CNT_MASK 0xFFFFFFFF + +/* DCORE0_MME_SBTE0_PRTN */ +#define DCORE0_MME_SBTE0_PRTN_CLK_EN_SHIFT 0 +#define DCORE0_MME_SBTE0_PRTN_CLK_EN_MASK 0x1 + +/* DCORE0_MME_SBTE0_CFG_SB_INFLIGHTS */ +#define DCORE0_MME_SBTE0_CFG_SB_INFLIGHTS_W_SHIFT 0 +#define DCORE0_MME_SBTE0_CFG_SB_INFLIGHTS_W_MASK 0xFFFFFFFF + +/* DCORE0_MME_SBTE0_PROT */ +#define DCORE0_MME_SBTE0_PROT_W_SHIFT 0 +#define DCORE0_MME_SBTE0_PROT_W_MASK 0x7 + +/* DCORE0_MME_SBTE0_INTR_MASK */ +#define DCORE0_MME_SBTE0_INTR_MASK_W_SHIFT 0 +#define DCORE0_MME_SBTE0_INTR_MASK_W_MASK 0x1 + +/* DCORE0_MME_SBTE0_ARUSER_MSB */ +#define DCORE0_MME_SBTE0_ARUSER_MSB_VAL_SHIFT 0 +#define DCORE0_MME_SBTE0_ARUSER_MSB_VAL_MASK 0xFFFFFFFF + +/* DCORE0_MME_SBTE0_CFG_SB_OCCUPIENCY */ +#define DCORE0_MME_SBTE0_CFG_SB_OCCUPIENCY_VAL_SHIFT 0 +#define DCORE0_MME_SBTE0_CFG_SB_OCCUPIENCY_VAL_MASK 0xFFFFFFFF + +/* DCORE0_MME_SBTE0_ENABLE_CGATE */ +#define DCORE0_MME_SBTE0_ENABLE_CGATE_TE_EN_SHIFT 0 +#define DCORE0_MME_SBTE0_ENABLE_CGATE_TE_EN_MASK 0x1 +#define DCORE0_MME_SBTE0_ENABLE_CGATE_SB_EN_SHIFT 4 +#define DCORE0_MME_SBTE0_ENABLE_CGATE_SB_EN_MASK 0x10 + +/* DCORE0_MME_SBTE0_INTF_VLD_DBG */ +#define DCORE0_MME_SBTE0_INTF_VLD_DBG_VLD_SHIFT 0 +#define DCORE0_MME_SBTE0_INTF_VLD_DBG_VLD_MASK 0xFFFFFFFF + +/* DCORE0_MME_SBTE0_INTF_RDY_DBG */ +#define DCORE0_MME_SBTE0_INTF_RDY_DBG_RDY_SHIFT 0 +#define DCORE0_MME_SBTE0_INTF_RDY_DBG_RDY_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_DCORE0_MME_SBTE0_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_sbte0_mstr_if_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_sbte0_mstr_if_axuser_regs.h new file mode 100644 index 000000000000..211fa2c2c35b --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_sbte0_mstr_if_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_SBTE0_MSTR_IF_AXUSER_REGS_H_ +#define ASIC_REG_DCORE0_MME_SBTE0_MSTR_IF_AXUSER_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_SBTE0_MSTR_IF_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_ASID 0x40D1A80 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_MMU_BP 0x40D1A84 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_STRONG_ORDER 0x40D1A88 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_NO_SNOOP 0x40D1A8C + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_WR_REDUCTION 0x40D1A90 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_RD_ATOMIC 0x40D1A94 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_QOS 0x40D1A98 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_RSVD 0x40D1A9C + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_EMEM_CPAGE 0x40D1AA0 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_CORE 0x40D1AA4 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_E2E_COORD 0x40D1AA8 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_WR_OVRD_LO 0x40D1AB0 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_WR_OVRD_HI 0x40D1AB4 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_RD_OVRD_LO 0x40D1AB8 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_RD_OVRD_HI 0x40D1ABC + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_LB_COORD 0x40D1AC0 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_LB_LOCK 0x40D1AC4 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_LB_RSVD 0x40D1AC8 + +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_LB_OVRD 0x40D1ACC + +#endif /* ASIC_REG_DCORE0_MME_SBTE0_MSTR_IF_AXUSER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_wb0_mstr_if_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_wb0_mstr_if_axuser_regs.h new file mode 100644 index 000000000000..374a01d2b8d5 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_wb0_mstr_if_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_WB0_MSTR_IF_AXUSER_REGS_H_ +#define ASIC_REG_DCORE0_MME_WB0_MSTR_IF_AXUSER_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_WB0_MSTR_IF_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_ASID 0x40F9A80 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_MMU_BP 0x40F9A84 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_STRONG_ORDER 0x40F9A88 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_NO_SNOOP 0x40F9A8C + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_WR_REDUCTION 0x40F9A90 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_RD_ATOMIC 0x40F9A94 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_QOS 0x40F9A98 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_RSVD 0x40F9A9C + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_EMEM_CPAGE 0x40F9AA0 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_CORE 0x40F9AA4 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_E2E_COORD 0x40F9AA8 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_WR_OVRD_LO 0x40F9AB0 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_WR_OVRD_HI 0x40F9AB4 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_RD_OVRD_LO 0x40F9AB8 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_RD_OVRD_HI 0x40F9ABC + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_LB_COORD 0x40F9AC0 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_LB_LOCK 0x40F9AC4 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_LB_RSVD 0x40F9AC8 + +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_LB_OVRD 0x40F9ACC + +#endif /* ASIC_REG_DCORE0_MME_WB0_MSTR_IF_AXUSER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_ctrl_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_ctrl_regs.h new file mode 100644 index 000000000000..22f4d6c805c5 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_ctrl_regs.h @@ -0,0 +1,291 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_RTR0_CTRL_REGS_H_ +#define ASIC_REG_DCORE0_RTR0_CTRL_REGS_H_ + +/* + ***************************************** + * DCORE0_RTR0_CTRL + * (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDCORE0_RTR0_CTRL_MEM_NUM 0x4140100 + +#define mmDCORE0_RTR0_CTRL_MEM_MAP 0x4140104 + +#define mmDCORE0_RTR0_CTRL_WR_RL_MEM 0x4140108 + +#define mmDCORE0_RTR0_CTRL_WR_RL_PCI 0x414010C + +#define mmDCORE0_RTR0_CTRL_WR_RL_SRAM 0x4140110 + +#define mmDCORE0_RTR0_CTRL_RD_RL_MEM 0x4140114 + +#define mmDCORE0_RTR0_CTRL_RD_RL_PCI 0x4140118 + +#define mmDCORE0_RTR0_CTRL_RD_RL_SRAM 0x414011C + +#define mmDCORE0_RTR0_CTRL_WR_RL_MEM_RED 0x4140120 + +#define mmDCORE0_RTR0_CTRL_RL_MEM_REDUCTION 0x4140124 + +#define mmDCORE0_RTR0_CTRL_WR_RL_SRAM_RED 0x4140128 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_CFG_0 0x4140400 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_CFG_1 0x4140404 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_SHIFT_0 0x4140408 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_SHIFT_1 0x414040C + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_0 0x4140410 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_1 0x4140414 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_2 0x4140418 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_3 0x414041C + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_4 0x4140420 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_5 0x4140424 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_6 0x4140428 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_7 0x414042C + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_8 0x4140430 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_9 0x4140434 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_10 0x4140438 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_11 0x414043C + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_12 0x4140440 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_13 0x4140444 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_14 0x4140448 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_15 0x414044C + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_0 0x4140450 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_1 0x4140454 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_2 0x4140458 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_3 0x414045C + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_4 0x4140460 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_5 0x4140464 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_6 0x4140468 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_7 0x414046C + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_8 0x4140470 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_9 0x4140474 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_10 0x4140478 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_11 0x414047C + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_12 0x4140480 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_13 0x4140484 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_14 0x4140488 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_15 0x414048C + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_0 0x4140490 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_1 0x4140494 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_2 0x4140498 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_3 0x414049C + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_4 0x41404A0 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_5 0x41404A4 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_6 0x41404A8 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_7 0x41404AC + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_8 0x41404B0 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_9 0x41404B4 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_10 0x41404B8 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_11 0x41404BC + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_12 0x41404C0 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_13 0x41404C4 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_14 0x41404C8 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_15 0x41404CC + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_WDT_0 0x41404D0 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_WDT_1 0x41404D4 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_DEC_TOKEN_0 0x41404D8 + +#define mmDCORE0_RTR0_CTRL_RGL_SRAM_DEC_TOKEN_1 0x41404DC + +#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_HI_ADDR 0x4140AB8 + +#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_LO_ADDR 0x4140ABC + +#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_SET 0x4140AC0 + +#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_HI_ADDR 0x4140AC4 + +#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_LO_ADDR 0x4140AC8 + +#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_SET 0x4140ACC + +#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AW_ADDR 0x4140AD0 + +#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AW_SET 0x4140AD4 + +#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AR_ADDR 0x4140AD8 + +#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AR_SET 0x4140ADC + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_CFG_0 0x4140AE4 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_CFG_1 0x4140AE8 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_SHIFT_0 0x4140AEC + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_SHIFT_1 0x4140AF0 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_0 0x4140AF4 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_1 0x4140AF8 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_2 0x4140AFC + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_3 0x4140B00 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_4 0x4140B04 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_5 0x4140B08 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_6 0x4140B0C + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_7 0x4140B10 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_8 0x4140B14 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_9 0x4140B18 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_10 0x4140B1C + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_11 0x4140B20 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_12 0x4140B24 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_13 0x4140B28 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_14 0x4140B2C + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_15 0x4140B30 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_0 0x4140B34 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_1 0x4140B38 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_2 0x4140B3C + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_3 0x4140B40 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_4 0x4140B44 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_5 0x4140B48 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_6 0x4140B4C + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_7 0x4140B50 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_8 0x4140B54 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_9 0x4140B58 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_10 0x4140B5C + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_11 0x4140B60 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_12 0x4140B64 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_13 0x4140B68 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_14 0x4140B6C + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_15 0x4140B70 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_0 0x4140B74 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_1 0x4140B78 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_2 0x4140B7C + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_3 0x4140B80 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_4 0x4140B84 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_5 0x4140B88 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_6 0x4140B8C + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_7 0x4140B90 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_8 0x4140B94 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_9 0x4140B98 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_10 0x4140B9C + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_11 0x4140BA0 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_12 0x4140BA4 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_13 0x4140BA8 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_14 0x4140BAC + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_15 0x4140BB0 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_WDT_0 0x4140BB4 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_WDT_1 0x4140BB8 + +#define mmDCORE0_RTR0_CTRL_RGL_WR_RED_CNT 0x4140BBC + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_DEC_TOKEN_0 0x4140BC0 + +#define mmDCORE0_RTR0_CTRL_RGL_MEM_DEC_TOKEN_1 0x4140BC4 + +#endif /* ASIC_REG_DCORE0_RTR0_CTRL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h new file mode 100644 index 000000000000..3a7290b3a5c9 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_REGS_H_ +#define ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_REGS_H_ + +/* + ***************************************** + * DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW + * (Prototype: RANGE_REG_HBW) + ***************************************** + */ + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_LO_0 0x4142200 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_LO_1 0x4142204 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_LO_2 0x4142208 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_LO_3 0x414220C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_LO_4 0x4142210 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_LO_5 0x4142214 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_HI_0 0x4142218 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_HI_1 0x414221C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_HI_2 0x4142220 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_HI_3 0x4142224 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_HI_4 0x4142228 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_HI_5 0x414222C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_LO_0 0x4142230 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_LO_1 0x4142234 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_LO_2 0x4142238 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_LO_3 0x414223C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_LO_4 0x4142240 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_LO_5 0x4142244 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_HI_0 0x4142248 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_HI_1 0x414224C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_HI_2 0x4142250 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_HI_3 0x4142254 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_HI_4 0x4142258 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_HI_5 0x414225C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_LO_0 0x4142260 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_LO_1 0x4142264 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_LO_2 0x4142268 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_LO_3 0x414226C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_LO_4 0x4142270 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_LO_5 0x4142274 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_HI_0 0x4142278 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_HI_1 0x414227C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_HI_2 0x4142280 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_HI_3 0x4142284 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_HI_4 0x4142288 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_HI_5 0x414228C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_LO_0 0x4142290 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_LO_1 0x4142294 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_LO_2 0x4142298 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_LO_3 0x414229C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_LO_4 0x41422A0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_LO_5 0x41422A4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_HI_0 0x41422A8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_HI_1 0x41422AC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_HI_2 0x41422B0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_HI_3 0x41422B4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_HI_4 0x41422B8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_HI_5 0x41422BC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_HI_0 0x41422C0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_HI_1 0x41422C4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_HI_2 0x41422C8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_HI_3 0x41422CC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_LO_0 0x41422D0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_LO_1 0x41422D4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_LO_2 0x41422D8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_LO_3 0x41422DC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_HI_0 0x41422E0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_HI_1 0x41422E4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_HI_2 0x41422E8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_HI_3 0x41422EC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_LO_0 0x41422F0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_LO_1 0x41422F4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_LO_2 0x41422F8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_LO_3 0x41422FC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_HI_0 0x4142300 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_HI_1 0x4142304 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_HI_2 0x4142308 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_HI_3 0x414230C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_LO_0 0x4142310 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_LO_1 0x4142314 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_LO_2 0x4142318 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_LO_3 0x414231C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_HI_0 0x4142320 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_HI_1 0x4142324 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_HI_2 0x4142328 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_HI_3 0x414232C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_LO_0 0x4142330 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_LO_1 0x4142334 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_LO_2 0x4142338 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_LO_3 0x414233C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_PCIE_EN 0x4142340 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_PCIE_EN 0x4142344 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_HIT_AW 0x4142348 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_HIT_AW 0x414234C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_HIT_AR 0x4142350 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_HIT_AR 0x4142354 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_AW_RAZWI_HI 0x4142358 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_AW_RAZWI_LO 0x414235C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_AR_RAZWI_HI 0x4142360 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_AR_RAZWI_LO 0x4142364 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_AW_RAZWI_XY 0x4142368 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_AR_RAZWI_XY 0x414236C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_AW_RAZWI_HAPPENED 0x4142370 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_AR_RAZWI_HAPPENED 0x4142374 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_RAZWI_ERR_RESP 0x4142378 + +#endif /* ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h new file mode 100644 index 000000000000..5b52b88fee0f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_REGS_H_ +#define ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_REGS_H_ + +/* + ***************************************** + * DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW + * (Prototype: RANGE_REG_LBW) + ***************************************** + */ + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_0 0x4142600 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_1 0x4142604 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_2 0x4142608 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_3 0x414260C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_4 0x4142610 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_5 0x4142614 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_6 0x4142618 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_7 0x414261C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_8 0x4142620 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_9 0x4142624 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_10 0x4142628 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_11 0x414262C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_12 0x4142630 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_13 0x4142634 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_0 0x4142638 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_1 0x414263C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_2 0x4142640 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_3 0x4142644 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_4 0x4142648 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_5 0x414264C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_6 0x4142650 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_7 0x4142654 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_8 0x4142658 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_9 0x414265C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_10 0x4142660 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_11 0x4142664 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_12 0x4142668 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_13 0x414266C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_0 0x4142670 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_1 0x4142674 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_2 0x4142678 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_3 0x414267C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_4 0x4142680 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_5 0x4142684 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_6 0x4142688 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_7 0x414268C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_8 0x4142690 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_9 0x4142694 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_10 0x4142698 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_11 0x414269C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_12 0x41426A0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_13 0x41426A4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_0 0x41426A8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_1 0x41426AC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_2 0x41426B0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_3 0x41426B4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_4 0x41426B8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_5 0x41426BC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_6 0x41426C0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_7 0x41426C4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_8 0x41426C8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_9 0x41426CC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_10 0x41426D0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_11 0x41426D4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_12 0x41426D8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_13 0x41426DC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_0 0x41426E0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_1 0x41426E4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_2 0x41426E8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_3 0x41426EC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_0 0x41426F0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_1 0x41426F4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_2 0x41426F8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_3 0x41426FC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_0 0x4142700 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_1 0x4142704 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_2 0x4142708 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_3 0x414270C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_0 0x4142710 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_1 0x4142714 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_2 0x4142718 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_3 0x414271C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_HIT_AW 0x4142720 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_HIT_AW 0x4142724 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_HIT_AR 0x4142728 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_HIT_AR 0x414272C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_AW_RAZWI 0x4142730 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_AR_RAZWI 0x4142734 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_AW_RAZWI_XY 0x4142738 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_AR_RAZWI_XY 0x414273C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_AW_RAZWI_HAPPENED 0x4142740 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_AR_RAZWI_HAPPENED 0x4142744 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_RAZWI_ERR_RESP 0x4142748 + +#endif /* ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h new file mode 100644 index 000000000000..d9b3f5cd392b --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_REGS_H_ +#define ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_REGS_H_ + +/* + ***************************************** + * DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW + * (Prototype: RANGE_REG_HBW) + ***************************************** + */ + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0 0x4142000 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_1 0x4142004 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_2 0x4142008 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_3 0x414200C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_4 0x4142010 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_5 0x4142014 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0 0x4142018 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_1 0x414201C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_2 0x4142020 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_3 0x4142024 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_4 0x4142028 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_5 0x414202C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0 0x4142030 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_1 0x4142034 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_2 0x4142038 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_3 0x414203C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_4 0x4142040 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_5 0x4142044 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0 0x4142048 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_1 0x414204C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_2 0x4142050 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_3 0x4142054 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_4 0x4142058 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_5 0x414205C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0 0x4142060 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_1 0x4142064 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_2 0x4142068 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_3 0x414206C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_4 0x4142070 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_5 0x4142074 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0 0x4142078 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_1 0x414207C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_2 0x4142080 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_3 0x4142084 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_4 0x4142088 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_5 0x414208C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0 0x4142090 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_1 0x4142094 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_2 0x4142098 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_3 0x414209C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_4 0x41420A0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_5 0x41420A4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0 0x41420A8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_1 0x41420AC + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_2 0x41420B0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_3 0x41420B4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_4 0x41420B8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_5 0x41420BC + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_HI_0 0x41420C0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_HI_1 0x41420C4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_HI_2 0x41420C8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_HI_3 0x41420CC + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_LO_0 0x41420D0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_LO_1 0x41420D4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_LO_2 0x41420D8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_LO_3 0x41420DC + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_HI_0 0x41420E0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_HI_1 0x41420E4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_HI_2 0x41420E8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_HI_3 0x41420EC + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_LO_0 0x41420F0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_LO_1 0x41420F4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_LO_2 0x41420F8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_LO_3 0x41420FC + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0 0x4142100 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_HI_1 0x4142104 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_HI_2 0x4142108 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_HI_3 0x414210C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0 0x4142110 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_LO_1 0x4142114 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_LO_2 0x4142118 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_LO_3 0x414211C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0 0x4142120 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_HI_1 0x4142124 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_HI_2 0x4142128 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_HI_3 0x414212C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0 0x4142130 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_LO_1 0x4142134 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_LO_2 0x4142138 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_LO_3 0x414213C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_PCIE_EN 0x4142140 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_PCIE_EN 0x4142144 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_HIT_AW 0x4142148 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_HIT_AW 0x414214C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_HIT_AR 0x4142150 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_HIT_AR 0x4142154 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_HI 0x4142158 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_LO 0x414215C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_HI 0x4142160 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_LO 0x4142164 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_XY 0x4142168 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_XY 0x414216C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_HAPPENED 0x4142170 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_HAPPENED 0x4142174 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_RAZWI_ERR_RESP 0x4142178 + +#endif /* ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h new file mode 100644 index 000000000000..1bba940d3031 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_REGS_H_ +#define ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_REGS_H_ + +/* + ***************************************** + * DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW + * (Prototype: RANGE_REG_LBW) + ***************************************** + */ + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_0 0x4142400 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_1 0x4142404 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_2 0x4142408 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_3 0x414240C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_4 0x4142410 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_5 0x4142414 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_6 0x4142418 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_7 0x414241C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_8 0x4142420 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_9 0x4142424 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_10 0x4142428 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_11 0x414242C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_12 0x4142430 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_13 0x4142434 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_0 0x4142438 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_1 0x414243C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_2 0x4142440 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_3 0x4142444 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_4 0x4142448 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_5 0x414244C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_6 0x4142450 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_7 0x4142454 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_8 0x4142458 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_9 0x414245C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_10 0x4142460 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_11 0x4142464 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_12 0x4142468 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_13 0x414246C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_0 0x4142470 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_1 0x4142474 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_2 0x4142478 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_3 0x414247C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_4 0x4142480 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_5 0x4142484 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_6 0x4142488 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_7 0x414248C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_8 0x4142490 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_9 0x4142494 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_10 0x4142498 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_11 0x414249C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_12 0x41424A0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_13 0x41424A4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_0 0x41424A8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_1 0x41424AC + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_2 0x41424B0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_3 0x41424B4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_4 0x41424B8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_5 0x41424BC + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_6 0x41424C0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_7 0x41424C4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_8 0x41424C8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_9 0x41424CC + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_10 0x41424D0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_11 0x41424D4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_12 0x41424D8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_13 0x41424DC + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_0 0x41424E0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_1 0x41424E4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_2 0x41424E8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_3 0x41424EC + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_0 0x41424F0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_1 0x41424F4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_2 0x41424F8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_3 0x41424FC + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_0 0x4142500 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_1 0x4142504 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_2 0x4142508 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_3 0x414250C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_0 0x4142510 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_1 0x4142514 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_2 0x4142518 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_3 0x414251C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_HIT_AW 0x4142520 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_HIT_AW 0x4142524 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_HIT_AR 0x4142528 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_HIT_AR 0x414252C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI 0x4142530 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI 0x4142534 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI_XY 0x4142538 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI_XY 0x414253C + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI_HAPPENED 0x4142540 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI_HAPPENED 0x4142544 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_RAZWI_ERR_RESP 0x4142548 + +#endif /* ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_glbl_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_glbl_masks.h new file mode 100644 index 000000000000..f21540501cdd --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_glbl_masks.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_SYNC_MNGR_GLBL_MASKS_H_ +#define ASIC_REG_DCORE0_SYNC_MNGR_GLBL_MASKS_H_ + +/* + ***************************************** + * DCORE0_SYNC_MNGR_GLBL + * (Prototype: SOB_GLBL) + ***************************************** + */ + +/* DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK */ +#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_SO_OVERFLOW_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_SO_OVERFLOW_MASK 0x1 +#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_MST_UNALIGN4B_SHIFT 1 +#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_MST_UNALIGN4B_MASK 0x2 +#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_MST_RSP_ERR_SHIFT 2 +#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_MST_RSP_ERR_MASK 0x4 + +/* DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE */ +#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE_CAUSE_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE_CAUSE_MASK 0x7 +#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE_LOG_SHIFT 4 +#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE_LOG_MASK 0xFFFF0 + +/* DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_L */ +#define DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_L_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_L_VAL_MASK 0xFFF + +/* DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_H */ +#define DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_H_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_H_VAL_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_GLBL_L2H_MASK_L */ +#define DCORE0_SYNC_MNGR_GLBL_L2H_MASK_L_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_L2H_MASK_L_VAL_MASK 0xFFF + +/* DCORE0_SYNC_MNGR_GLBL_L2H_MASK_H */ +#define DCORE0_SYNC_MNGR_GLBL_L2H_MASK_H_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_L2H_MASK_H_VAL_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_GLBL_ASID_SEC */ +#define DCORE0_SYNC_MNGR_GLBL_ASID_SEC_ASID_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_ASID_SEC_ASID_MASK 0xFFFF +#define DCORE0_SYNC_MNGR_GLBL_ASID_SEC_BP_MMU_SHIFT 16 +#define DCORE0_SYNC_MNGR_GLBL_ASID_SEC_BP_MMU_MASK 0x10000 + +/* DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY */ +#define DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY_ASID_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY_ASID_MASK 0xFFFF +#define DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY_BP_MMU_SHIFT 16 +#define DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY_BP_MMU_MASK 0x10000 + +/* DCORE0_SYNC_MNGR_GLBL_LBW_DELAY */ +#define DCORE0_SYNC_MNGR_GLBL_LBW_DELAY_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_LBW_DELAY_VAL_MASK 0xFFFF +#define DCORE0_SYNC_MNGR_GLBL_LBW_DELAY_EN_SHIFT 16 +#define DCORE0_SYNC_MNGR_GLBL_LBW_DELAY_EN_MASK 0x10000 + +/* DCORE0_SYNC_MNGR_GLBL_PI_SIZE */ +#define DCORE0_SYNC_MNGR_GLBL_PI_SIZE_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_PI_SIZE_VAL_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_GLBL_SOB_ONLY */ +#define DCORE0_SYNC_MNGR_GLBL_SOB_ONLY_EN_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_SOB_ONLY_EN_MASK 0x1 + +/* DCORE0_SYNC_MNGR_GLBL_CQ_INTR */ +#define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_SEC_INTR_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_SEC_INTR_MASK 0x1 +#define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_SEC_INTR_MASK_SHIFT 8 +#define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_SEC_INTR_MASK_MASK 0x100 +#define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_INTR_QUEUE_INDEX_SHIFT 16 +#define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_INTR_QUEUE_INDEX_MASK 0x3F0000 + +/* DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV */ +#define DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV_ASID_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV_ASID_MASK 0xFFFF +#define DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV_BP_MMU_SHIFT 16 +#define DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV_BP_MMU_MASK 0x10000 + +/* DCORE0_SYNC_MNGR_GLBL_PI_INC_MODE_SIZE */ +#define DCORE0_SYNC_MNGR_GLBL_PI_INC_MODE_SIZE_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_PI_INC_MODE_SIZE_VAL_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L */ +#define DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_VAL_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H */ +#define DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_VAL_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2 */ +#define DCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_VAL_MASK 0xFF + +/* DCORE0_SYNC_MNGR_GLBL_CQ_PI */ +#define DCORE0_SYNC_MNGR_GLBL_CQ_PI_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_CQ_PI_VAL_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_GLBL_CQ_SEC */ +#define DCORE0_SYNC_MNGR_GLBL_CQ_SEC_SEC_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_CQ_SEC_SEC_MASK 0x1 +#define DCORE0_SYNC_MNGR_GLBL_CQ_SEC_PRIV_SHIFT 4 +#define DCORE0_SYNC_MNGR_GLBL_CQ_SEC_PRIV_MASK 0x10 + +/* DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L */ +#define DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_ADDRL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_ADDRL_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H */ +#define DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_ADDRH_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_ADDRH_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_GLBL_LBW_DATA */ +#define DCORE0_SYNC_MNGR_GLBL_LBW_DATA_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_LBW_DATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE */ +#define DCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_MODE_SHIFT 0 +#define DCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_MODE_MASK 0x1 + +#endif /* ASIC_REG_DCORE0_SYNC_MNGR_GLBL_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_glbl_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_glbl_regs.h new file mode 100644 index 000000000000..c3c4991e6660 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_glbl_regs.h @@ -0,0 +1,1203 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_SYNC_MNGR_GLBL_REGS_H_ +#define ASIC_REG_DCORE0_SYNC_MNGR_GLBL_REGS_H_ + +/* + ***************************************** + * DCORE0_SYNC_MNGR_GLBL + * (Prototype: SOB_GLBL) + ***************************************** + */ + +#define mmDCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK 0x411E000 + +#define mmDCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE 0x411E004 + +#define mmDCORE0_SYNC_MNGR_GLBL_L2H_CPMR_L 0x411E008 + +#define mmDCORE0_SYNC_MNGR_GLBL_L2H_CPMR_H 0x411E00C + +#define mmDCORE0_SYNC_MNGR_GLBL_L2H_MASK_L 0x411E020 + +#define mmDCORE0_SYNC_MNGR_GLBL_L2H_MASK_H 0x411E024 + +#define mmDCORE0_SYNC_MNGR_GLBL_ASID_SEC 0x411E030 + +#define mmDCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY 0x411E034 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DELAY 0x411E038 + +#define mmDCORE0_SYNC_MNGR_GLBL_PI_SIZE 0x411E03C + +#define mmDCORE0_SYNC_MNGR_GLBL_SOB_ONLY 0x411E040 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INTR 0x411E044 + +#define mmDCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV 0x411E048 + +#define mmDCORE0_SYNC_MNGR_GLBL_PI_INC_MODE_SIZE 0x411E04C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0 0x411E050 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_1 0x411E054 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_2 0x411E058 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_3 0x411E05C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_4 0x411E060 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_5 0x411E064 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_6 0x411E068 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_7 0x411E06C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_8 0x411E070 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_9 0x411E074 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_10 0x411E078 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_11 0x411E07C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_12 0x411E080 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_13 0x411E084 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_14 0x411E088 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_15 0x411E08C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_16 0x411E090 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_17 0x411E094 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_18 0x411E098 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_19 0x411E09C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_20 0x411E0A0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_21 0x411E0A4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_22 0x411E0A8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_23 0x411E0AC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_24 0x411E0B0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_25 0x411E0B4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_26 0x411E0B8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_27 0x411E0BC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_28 0x411E0C0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_29 0x411E0C4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_30 0x411E0C8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_31 0x411E0CC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_32 0x411E0D0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_33 0x411E0D4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_34 0x411E0D8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_35 0x411E0DC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_36 0x411E0E0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_37 0x411E0E4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_38 0x411E0E8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_39 0x411E0EC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_40 0x411E0F0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_41 0x411E0F4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_42 0x411E0F8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_43 0x411E0FC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_44 0x411E100 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_45 0x411E104 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_46 0x411E108 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_47 0x411E10C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_48 0x411E110 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_49 0x411E114 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_50 0x411E118 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_51 0x411E11C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_52 0x411E120 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_53 0x411E124 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_54 0x411E128 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_55 0x411E12C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_56 0x411E130 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_57 0x411E134 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_58 0x411E138 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_59 0x411E13C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_60 0x411E140 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_61 0x411E144 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_62 0x411E148 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63 0x411E14C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0 0x411E150 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_1 0x411E154 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_2 0x411E158 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_3 0x411E15C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_4 0x411E160 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_5 0x411E164 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_6 0x411E168 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_7 0x411E16C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_8 0x411E170 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_9 0x411E174 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_10 0x411E178 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_11 0x411E17C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_12 0x411E180 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_13 0x411E184 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_14 0x411E188 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_15 0x411E18C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_16 0x411E190 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_17 0x411E194 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_18 0x411E198 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_19 0x411E19C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_20 0x411E1A0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_21 0x411E1A4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_22 0x411E1A8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_23 0x411E1AC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_24 0x411E1B0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_25 0x411E1B4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_26 0x411E1B8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_27 0x411E1BC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_28 0x411E1C0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_29 0x411E1C4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_30 0x411E1C8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_31 0x411E1CC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_32 0x411E1D0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_33 0x411E1D4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_34 0x411E1D8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_35 0x411E1DC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_36 0x411E1E0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_37 0x411E1E4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_38 0x411E1E8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_39 0x411E1EC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_40 0x411E1F0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_41 0x411E1F4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_42 0x411E1F8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_43 0x411E1FC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_44 0x411E200 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_45 0x411E204 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_46 0x411E208 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_47 0x411E20C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_48 0x411E210 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_49 0x411E214 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_50 0x411E218 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_51 0x411E21C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_52 0x411E220 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_53 0x411E224 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_54 0x411E228 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_55 0x411E22C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_56 0x411E230 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_57 0x411E234 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_58 0x411E238 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_59 0x411E23C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_60 0x411E240 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_61 0x411E244 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_62 0x411E248 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63 0x411E24C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0 0x411E250 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_1 0x411E254 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_2 0x411E258 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_3 0x411E25C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_4 0x411E260 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_5 0x411E264 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_6 0x411E268 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_7 0x411E26C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_8 0x411E270 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_9 0x411E274 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_10 0x411E278 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_11 0x411E27C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_12 0x411E280 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_13 0x411E284 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_14 0x411E288 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_15 0x411E28C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_16 0x411E290 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_17 0x411E294 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_18 0x411E298 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_19 0x411E29C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_20 0x411E2A0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_21 0x411E2A4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_22 0x411E2A8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_23 0x411E2AC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_24 0x411E2B0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_25 0x411E2B4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_26 0x411E2B8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_27 0x411E2BC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_28 0x411E2C0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_29 0x411E2C4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_30 0x411E2C8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_31 0x411E2CC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_32 0x411E2D0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_33 0x411E2D4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_34 0x411E2D8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_35 0x411E2DC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_36 0x411E2E0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_37 0x411E2E4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_38 0x411E2E8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_39 0x411E2EC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_40 0x411E2F0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_41 0x411E2F4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_42 0x411E2F8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_43 0x411E2FC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_44 0x411E300 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_45 0x411E304 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_46 0x411E308 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_47 0x411E30C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_48 0x411E310 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_49 0x411E314 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_50 0x411E318 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_51 0x411E31C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_52 0x411E320 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_53 0x411E324 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_54 0x411E328 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_55 0x411E32C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_56 0x411E330 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_57 0x411E334 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_58 0x411E338 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_59 0x411E33C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_60 0x411E340 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_61 0x411E344 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_62 0x411E348 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63 0x411E34C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_0 0x411E350 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_1 0x411E354 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_2 0x411E358 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_3 0x411E35C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_4 0x411E360 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_5 0x411E364 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_6 0x411E368 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_7 0x411E36C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_8 0x411E370 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_9 0x411E374 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_10 0x411E378 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_11 0x411E37C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_12 0x411E380 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_13 0x411E384 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_14 0x411E388 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_15 0x411E38C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_16 0x411E390 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_17 0x411E394 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_18 0x411E398 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_19 0x411E39C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_20 0x411E3A0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_21 0x411E3A4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_22 0x411E3A8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_23 0x411E3AC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_24 0x411E3B0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_25 0x411E3B4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_26 0x411E3B8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_27 0x411E3BC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_28 0x411E3C0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_29 0x411E3C4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_30 0x411E3C8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_31 0x411E3CC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_32 0x411E3D0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_33 0x411E3D4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_34 0x411E3D8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_35 0x411E3DC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_36 0x411E3E0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_37 0x411E3E4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_38 0x411E3E8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_39 0x411E3EC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_40 0x411E3F0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_41 0x411E3F4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_42 0x411E3F8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_43 0x411E3FC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_44 0x411E400 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_45 0x411E404 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_46 0x411E408 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_47 0x411E40C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_48 0x411E410 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_49 0x411E414 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_50 0x411E418 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_51 0x411E41C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_52 0x411E420 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_53 0x411E424 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_54 0x411E428 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_55 0x411E42C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_56 0x411E430 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_57 0x411E434 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_58 0x411E438 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_59 0x411E43C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_60 0x411E440 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_61 0x411E444 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_62 0x411E448 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_63 0x411E44C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_0 0x411E450 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_1 0x411E454 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_2 0x411E458 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_3 0x411E45C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_4 0x411E460 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_5 0x411E464 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_6 0x411E468 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_7 0x411E46C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_8 0x411E470 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_9 0x411E474 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_10 0x411E478 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_11 0x411E47C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_12 0x411E480 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_13 0x411E484 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_14 0x411E488 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_15 0x411E48C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_16 0x411E490 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_17 0x411E494 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_18 0x411E498 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_19 0x411E49C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_20 0x411E4A0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_21 0x411E4A4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_22 0x411E4A8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_23 0x411E4AC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_24 0x411E4B0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_25 0x411E4B4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_26 0x411E4B8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_27 0x411E4BC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_28 0x411E4C0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_29 0x411E4C4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_30 0x411E4C8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_31 0x411E4CC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_32 0x411E4D0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_33 0x411E4D4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_34 0x411E4D8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_35 0x411E4DC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_36 0x411E4E0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_37 0x411E4E4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_38 0x411E4E8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_39 0x411E4EC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_40 0x411E4F0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_41 0x411E4F4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_42 0x411E4F8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_43 0x411E4FC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_44 0x411E500 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_45 0x411E504 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_46 0x411E508 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_47 0x411E50C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_48 0x411E510 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_49 0x411E514 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_50 0x411E518 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_51 0x411E51C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_52 0x411E520 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_53 0x411E524 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_54 0x411E528 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_55 0x411E52C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_56 0x411E530 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_57 0x411E534 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_58 0x411E538 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_59 0x411E53C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_60 0x411E540 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_61 0x411E544 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_62 0x411E548 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_63 0x411E54C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_0 0x411E550 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_1 0x411E554 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_2 0x411E558 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_3 0x411E55C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_4 0x411E560 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_5 0x411E564 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_6 0x411E568 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_7 0x411E56C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_8 0x411E570 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_9 0x411E574 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_10 0x411E578 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_11 0x411E57C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_12 0x411E580 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_13 0x411E584 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_14 0x411E588 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_15 0x411E58C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_16 0x411E590 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_17 0x411E594 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_18 0x411E598 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_19 0x411E59C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_20 0x411E5A0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_21 0x411E5A4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_22 0x411E5A8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_23 0x411E5AC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_24 0x411E5B0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_25 0x411E5B4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_26 0x411E5B8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_27 0x411E5BC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_28 0x411E5C0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_29 0x411E5C4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_30 0x411E5C8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_31 0x411E5CC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_32 0x411E5D0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_33 0x411E5D4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_34 0x411E5D8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_35 0x411E5DC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_36 0x411E5E0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_37 0x411E5E4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_38 0x411E5E8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_39 0x411E5EC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_40 0x411E5F0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_41 0x411E5F4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_42 0x411E5F8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_43 0x411E5FC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_44 0x411E600 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_45 0x411E604 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_46 0x411E608 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_47 0x411E60C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_48 0x411E610 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_49 0x411E614 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_50 0x411E618 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_51 0x411E61C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_52 0x411E620 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_53 0x411E624 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_54 0x411E628 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_55 0x411E62C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_56 0x411E630 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_57 0x411E634 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_58 0x411E638 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_59 0x411E63C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_60 0x411E640 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_61 0x411E644 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_62 0x411E648 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_63 0x411E64C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0 0x411E650 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_1 0x411E654 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_2 0x411E658 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_3 0x411E65C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_4 0x411E660 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_5 0x411E664 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_6 0x411E668 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_7 0x411E66C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_8 0x411E670 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_9 0x411E674 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_10 0x411E678 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_11 0x411E67C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_12 0x411E680 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_13 0x411E684 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_14 0x411E688 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_15 0x411E68C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_16 0x411E690 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_17 0x411E694 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_18 0x411E698 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_19 0x411E69C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_20 0x411E6A0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_21 0x411E6A4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_22 0x411E6A8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_23 0x411E6AC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_24 0x411E6B0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_25 0x411E6B4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_26 0x411E6B8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_27 0x411E6BC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_28 0x411E6C0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_29 0x411E6C4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_30 0x411E6C8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_31 0x411E6CC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_32 0x411E6D0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_33 0x411E6D4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_34 0x411E6D8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_35 0x411E6DC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_36 0x411E6E0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_37 0x411E6E4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_38 0x411E6E8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_39 0x411E6EC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_40 0x411E6F0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_41 0x411E6F4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_42 0x411E6F8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_43 0x411E6FC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_44 0x411E700 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_45 0x411E704 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_46 0x411E708 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_47 0x411E70C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_48 0x411E710 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_49 0x411E714 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_50 0x411E718 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_51 0x411E71C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_52 0x411E720 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_53 0x411E724 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_54 0x411E728 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_55 0x411E72C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_56 0x411E730 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_57 0x411E734 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_58 0x411E738 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_59 0x411E73C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_60 0x411E740 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_61 0x411E744 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_62 0x411E748 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_63 0x411E74C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_0 0x411E750 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_1 0x411E754 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_2 0x411E758 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_3 0x411E75C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_4 0x411E760 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_5 0x411E764 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_6 0x411E768 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_7 0x411E76C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_8 0x411E770 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_9 0x411E774 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_10 0x411E778 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_11 0x411E77C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_12 0x411E780 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_13 0x411E784 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_14 0x411E788 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_15 0x411E78C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_16 0x411E790 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_17 0x411E794 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_18 0x411E798 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_19 0x411E79C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_20 0x411E7A0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_21 0x411E7A4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_22 0x411E7A8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_23 0x411E7AC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_24 0x411E7B0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_25 0x411E7B4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_26 0x411E7B8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_27 0x411E7BC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_28 0x411E7C0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_29 0x411E7C4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_30 0x411E7C8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_31 0x411E7CC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_32 0x411E7D0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_33 0x411E7D4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_34 0x411E7D8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_35 0x411E7DC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_36 0x411E7E0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_37 0x411E7E4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_38 0x411E7E8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_39 0x411E7EC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_40 0x411E7F0 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_41 0x411E7F4 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_42 0x411E7F8 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_43 0x411E7FC + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_44 0x411E800 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_45 0x411E804 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_46 0x411E808 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_47 0x411E80C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_48 0x411E810 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_49 0x411E814 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_50 0x411E818 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_51 0x411E81C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_52 0x411E820 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_53 0x411E824 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_54 0x411E828 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_55 0x411E82C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_56 0x411E830 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_57 0x411E834 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_58 0x411E838 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_59 0x411E83C + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_60 0x411E840 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_61 0x411E844 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_62 0x411E848 + +#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_63 0x411E84C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_0 0x411E850 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_1 0x411E854 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_2 0x411E858 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_3 0x411E85C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_4 0x411E860 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_5 0x411E864 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_6 0x411E868 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_7 0x411E86C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_8 0x411E870 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_9 0x411E874 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_10 0x411E878 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_11 0x411E87C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_12 0x411E880 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_13 0x411E884 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_14 0x411E888 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_15 0x411E88C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_16 0x411E890 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_17 0x411E894 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_18 0x411E898 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_19 0x411E89C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_20 0x411E8A0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_21 0x411E8A4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_22 0x411E8A8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_23 0x411E8AC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_24 0x411E8B0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_25 0x411E8B4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_26 0x411E8B8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_27 0x411E8BC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_28 0x411E8C0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_29 0x411E8C4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_30 0x411E8C8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_31 0x411E8CC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_32 0x411E8D0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_33 0x411E8D4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_34 0x411E8D8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_35 0x411E8DC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_36 0x411E8E0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_37 0x411E8E4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_38 0x411E8E8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_39 0x411E8EC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_40 0x411E8F0 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_41 0x411E8F4 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_42 0x411E8F8 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_43 0x411E8FC + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_44 0x411E900 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_45 0x411E904 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_46 0x411E908 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_47 0x411E90C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_48 0x411E910 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_49 0x411E914 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_50 0x411E918 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_51 0x411E91C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_52 0x411E920 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_53 0x411E924 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_54 0x411E928 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_55 0x411E92C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_56 0x411E930 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_57 0x411E934 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_58 0x411E938 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_59 0x411E93C + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_60 0x411E940 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_61 0x411E944 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_62 0x411E948 + +#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_63 0x411E94C + +#endif /* ASIC_REG_DCORE0_SYNC_MNGR_GLBL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_mstr_if_axuser_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_mstr_if_axuser_masks.h new file mode 100644 index 000000000000..76b273a41255 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_mstr_if_axuser_masks.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_MASKS_H_ +#define ASIC_REG_DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_MASKS_H_ + +/* + ***************************************** + * DCORE0_SYNC_MNGR_MSTR_IF_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_WR_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_WR_MASK 0x3FF +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_RD_SHIFT 16 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_RD_MASK 0x3FF0000 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP_WR_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP_WR_MASK 0x1 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP_RD_SHIFT 4 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP_RD_MASK 0x10 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER_WR_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER_WR_MASK 0x1 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER_RD_SHIFT 4 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER_RD_MASK 0x10 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP_WR_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP_WR_MASK 0x1 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP_RD_SHIFT 4 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP_RD_MASK 0x10 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_IND_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_IND_MASK 0x1 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_DTYPE_SHIFT 4 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_DTYPE_MASK 0xF0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_OP_SHIFT 8 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_OP_MASK 0x300 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_ROUND_SHIFT 12 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_ROUND_MASK 0x3000 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_MAX_SHIFT 16 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_MAX_MASK 0x10000 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC_IND_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC_IND_MASK 0x3 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC_ADDITION_SIZE_SHIFT 4 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC_ADDITION_SIZE_MASK 0xFF0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC_MSB_MASK_SHIFT 12 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC_MSB_MASK_MASK 0x1F000 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_QOS */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_QOS_WR_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_QOS_WR_MASK 0xF +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_QOS_RD_SHIFT 4 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_QOS_RD_MASK 0x70 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_27_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_27_MASK 0x1 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_28_SHIFT 1 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_28_MASK 0x2 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_30_SHIFT 2 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_30_MASK 0x4 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_31_SHIFT 3 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_31_MASK 0x8 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_EMEM_CPAGE */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_EMEM_CPAGE_WR_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_EMEM_CPAGE_WR_MASK 0x1 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_EMEM_CPAGE_RD_SHIFT 4 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_EMEM_CPAGE_RD_MASK 0x10 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_CORE */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_CORE_WR_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_CORE_WR_MASK 0x1 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_CORE_RD_SHIFT 4 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_CORE_RD_MASK 0x10 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_E2E_COORD */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_E2E_COORD_X_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_E2E_COORD_X_MASK 0x1F +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_E2E_COORD_Y_SHIFT 8 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_E2E_COORD_Y_MASK 0xF00 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_LO */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_LO_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_HI */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_HI_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_HI_VAL_MASK 0x3FF + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_LO */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_LO_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_LO_VAL_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_HI */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_HI_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_HI_VAL_MASK 0x3FF + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_COORD */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_COORD_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_COORD_VAL_MASK 0x3FF + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_LOCK */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_LOCK_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_LOCK_VAL_MASK 0x1 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_RSVD */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_RSVD_BIT_21_11_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_RSVD_BIT_21_11_MASK 0x7FF +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_RSVD_BIT_22_SHIFT 12 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_RSVD_BIT_22_MASK 0x1000 + +/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_OVRD */ +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_OVRD_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_OVRD_VAL_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_mstr_if_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_mstr_if_axuser_regs.h new file mode 100644 index 000000000000..0bddc734329f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_mstr_if_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_REGS_H_ +#define ASIC_REG_DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_REGS_H_ + +/* + ***************************************** + * DCORE0_SYNC_MNGR_MSTR_IF_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID 0x411FA80 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP 0x411FA84 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER 0x411FA88 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP 0x411FA8C + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION 0x411FA90 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC 0x411FA94 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_QOS 0x411FA98 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD 0x411FA9C + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_EMEM_CPAGE 0x411FAA0 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_CORE 0x411FAA4 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_E2E_COORD 0x411FAA8 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_LO 0x411FAB0 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_HI 0x411FAB4 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_LO 0x411FAB8 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_HI 0x411FABC + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_COORD 0x411FAC0 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_LOCK 0x411FAC4 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_RSVD 0x411FAC8 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_OVRD 0x411FACC + +#endif /* ASIC_REG_DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_objs_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_objs_masks.h new file mode 100644 index 000000000000..3a5b27df0ab4 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_objs_masks.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_SYNC_MNGR_OBJS_MASKS_H_ +#define ASIC_REG_DCORE0_SYNC_MNGR_OBJS_MASKS_H_ + +/* + ***************************************** + * DCORE0_SYNC_MNGR_OBJS + * (Prototype: SOB_OBJS) + ***************************************** + */ + +/* DCORE0_SYNC_MNGR_OBJS_SOB_OBJ */ +#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_SHIFT 0 +#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_MASK 0x7FFF +#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_LONG_SOB_SHIFT 24 +#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_LONG_SOB_MASK 0x1000000 +#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_TRACE_EVICT_SHIFT 30 +#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_TRACE_EVICT_MASK 0x40000000 +#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_SHIFT 31 +#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_MASK 0x80000000 + +/* DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL */ +#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_ADDRL_SHIFT 0 +#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_ADDRL_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH */ +#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_ADDRH_SHIFT 0 +#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_ADDRH_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA */ +#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_DATA_SHIFT 0 +#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_DATA_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_OBJS_MON_ARM */ +#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_SID_SHIFT 0 +#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_SID_MASK 0xFF +#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_MASK_SHIFT 8 +#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_MASK_MASK 0xFF00 +#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_SOP_SHIFT 16 +#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_SOP_MASK 0x10000 +#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_SOD_SHIFT 17 +#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_SOD_MASK 0xFFFE0000 + +/* DCORE0_SYNC_MNGR_OBJS_MON_CONFIG */ +#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_LONG_SOB_SHIFT 0 +#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_LONG_SOB_MASK 0x1 +#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_CQ_EN_SHIFT 4 +#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_CQ_EN_MASK 0x10 +#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_WR_NUM_SHIFT 5 +#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_WR_NUM_MASK 0x60 +#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_LBW_EN_SHIFT 8 +#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_LBW_EN_MASK 0x100 +#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_MSB_SID_SHIFT 16 +#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_MSB_SID_MASK 0xF0000 +#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_LONG_HIGH_GROUP_SHIFT 31 +#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_LONG_HIGH_GROUP_MASK 0x80000000 + +/* DCORE0_SYNC_MNGR_OBJS_MON_STATUS */ +#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_VALID_SHIFT 0 +#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_VALID_MASK 0x1 +#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_PENDING_SHIFT 1 +#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_PENDING_MASK 0x1FE +#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_PROT_SHIFT 9 +#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_PROT_MASK 0x200 +#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_PRIV_SHIFT 10 +#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_PRIV_MASK 0x400 + +/* DCORE0_SYNC_MNGR_OBJS_SM_SEC */ +#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_SEC_VEC_SHIFT 0 +#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_SEC_VEC_MASK 0xFFFFFFFF + +/* DCORE0_SYNC_MNGR_OBJS_SM_PRIV */ +#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_PRIV_SHIFT 0 +#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_PRIV_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_DCORE0_SYNC_MNGR_OBJS_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_objs_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_objs_regs.h new file mode 100644 index 000000000000..8f082a1c9b1b --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_objs_regs.h @@ -0,0 +1,43543 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_SYNC_MNGR_OBJS_REGS_H_ +#define ASIC_REG_DCORE0_SYNC_MNGR_OBJS_REGS_H_ + +/* + ***************************************** + * DCORE0_SYNC_MNGR_OBJS + * (Prototype: SOB_OBJS) + ***************************************** + */ + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4100000 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1 0x4100004 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2 0x4100008 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3 0x410000C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4 0x4100010 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5 0x4100014 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6 0x4100018 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7 0x410001C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8 0x4100020 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_9 0x4100024 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_10 0x4100028 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_11 0x410002C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_12 0x4100030 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_13 0x4100034 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_14 0x4100038 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_15 0x410003C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_16 0x4100040 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_17 0x4100044 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_18 0x4100048 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_19 0x410004C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_20 0x4100050 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_21 0x4100054 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_22 0x4100058 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_23 0x410005C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_24 0x4100060 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_25 0x4100064 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_26 0x4100068 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_27 0x410006C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_28 0x4100070 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_29 0x4100074 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_30 0x4100078 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_31 0x410007C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_32 0x4100080 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_33 0x4100084 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_34 0x4100088 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_35 0x410008C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_36 0x4100090 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_37 0x4100094 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_38 0x4100098 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_39 0x410009C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_40 0x41000A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_41 0x41000A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_42 0x41000A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_43 0x41000AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_44 0x41000B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_45 0x41000B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_46 0x41000B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_47 0x41000BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_48 0x41000C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_49 0x41000C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_50 0x41000C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_51 0x41000CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_52 0x41000D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_53 0x41000D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_54 0x41000D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_55 0x41000DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_56 0x41000E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_57 0x41000E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_58 0x41000E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_59 0x41000EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_60 0x41000F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_61 0x41000F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_62 0x41000F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_63 0x41000FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_64 0x4100100 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_65 0x4100104 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_66 0x4100108 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_67 0x410010C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_68 0x4100110 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_69 0x4100114 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_70 0x4100118 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_71 0x410011C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_72 0x4100120 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_73 0x4100124 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_74 0x4100128 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_75 0x410012C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_76 0x4100130 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_77 0x4100134 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_78 0x4100138 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_79 0x410013C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_80 0x4100140 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_81 0x4100144 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_82 0x4100148 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_83 0x410014C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_84 0x4100150 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_85 0x4100154 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_86 0x4100158 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_87 0x410015C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_88 0x4100160 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_89 0x4100164 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_90 0x4100168 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_91 0x410016C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_92 0x4100170 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_93 0x4100174 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_94 0x4100178 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_95 0x410017C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_96 0x4100180 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_97 0x4100184 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_98 0x4100188 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_99 0x410018C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_100 0x4100190 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_101 0x4100194 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_102 0x4100198 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_103 0x410019C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_104 0x41001A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_105 0x41001A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_106 0x41001A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_107 0x41001AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_108 0x41001B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_109 0x41001B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_110 0x41001B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_111 0x41001BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_112 0x41001C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_113 0x41001C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_114 0x41001C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_115 0x41001CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_116 0x41001D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_117 0x41001D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_118 0x41001D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_119 0x41001DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_120 0x41001E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_121 0x41001E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_122 0x41001E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_123 0x41001EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_124 0x41001F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_125 0x41001F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_126 0x41001F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_127 0x41001FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_128 0x4100200 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_129 0x4100204 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_130 0x4100208 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_131 0x410020C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_132 0x4100210 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_133 0x4100214 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_134 0x4100218 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_135 0x410021C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_136 0x4100220 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_137 0x4100224 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_138 0x4100228 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_139 0x410022C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_140 0x4100230 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_141 0x4100234 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_142 0x4100238 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_143 0x410023C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_144 0x4100240 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_145 0x4100244 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_146 0x4100248 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_147 0x410024C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_148 0x4100250 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_149 0x4100254 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_150 0x4100258 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_151 0x410025C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_152 0x4100260 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_153 0x4100264 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_154 0x4100268 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_155 0x410026C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_156 0x4100270 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_157 0x4100274 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_158 0x4100278 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_159 0x410027C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_160 0x4100280 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_161 0x4100284 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_162 0x4100288 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_163 0x410028C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_164 0x4100290 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_165 0x4100294 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_166 0x4100298 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_167 0x410029C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_168 0x41002A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_169 0x41002A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_170 0x41002A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_171 0x41002AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_172 0x41002B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_173 0x41002B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_174 0x41002B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_175 0x41002BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_176 0x41002C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_177 0x41002C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_178 0x41002C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_179 0x41002CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_180 0x41002D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_181 0x41002D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_182 0x41002D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_183 0x41002DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_184 0x41002E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_185 0x41002E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_186 0x41002E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_187 0x41002EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_188 0x41002F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_189 0x41002F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_190 0x41002F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_191 0x41002FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_192 0x4100300 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_193 0x4100304 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_194 0x4100308 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_195 0x410030C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_196 0x4100310 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_197 0x4100314 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_198 0x4100318 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_199 0x410031C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_200 0x4100320 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_201 0x4100324 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_202 0x4100328 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_203 0x410032C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_204 0x4100330 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_205 0x4100334 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_206 0x4100338 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_207 0x410033C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_208 0x4100340 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_209 0x4100344 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_210 0x4100348 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_211 0x410034C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_212 0x4100350 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_213 0x4100354 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_214 0x4100358 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_215 0x410035C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_216 0x4100360 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_217 0x4100364 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_218 0x4100368 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_219 0x410036C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_220 0x4100370 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_221 0x4100374 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_222 0x4100378 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_223 0x410037C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_224 0x4100380 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_225 0x4100384 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_226 0x4100388 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_227 0x410038C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_228 0x4100390 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_229 0x4100394 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_230 0x4100398 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_231 0x410039C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_232 0x41003A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_233 0x41003A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_234 0x41003A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_235 0x41003AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_236 0x41003B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_237 0x41003B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_238 0x41003B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_239 0x41003BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_240 0x41003C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_241 0x41003C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_242 0x41003C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_243 0x41003CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_244 0x41003D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_245 0x41003D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_246 0x41003D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_247 0x41003DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_248 0x41003E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_249 0x41003E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_250 0x41003E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_251 0x41003EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_252 0x41003F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_253 0x41003F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_254 0x41003F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_255 0x41003FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_256 0x4100400 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_257 0x4100404 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_258 0x4100408 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_259 0x410040C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_260 0x4100410 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_261 0x4100414 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_262 0x4100418 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_263 0x410041C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_264 0x4100420 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_265 0x4100424 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_266 0x4100428 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_267 0x410042C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_268 0x4100430 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_269 0x4100434 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_270 0x4100438 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_271 0x410043C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_272 0x4100440 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_273 0x4100444 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_274 0x4100448 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_275 0x410044C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_276 0x4100450 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_277 0x4100454 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_278 0x4100458 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_279 0x410045C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_280 0x4100460 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_281 0x4100464 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_282 0x4100468 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_283 0x410046C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_284 0x4100470 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_285 0x4100474 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_286 0x4100478 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_287 0x410047C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_288 0x4100480 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_289 0x4100484 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_290 0x4100488 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_291 0x410048C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_292 0x4100490 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_293 0x4100494 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_294 0x4100498 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_295 0x410049C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_296 0x41004A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_297 0x41004A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_298 0x41004A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_299 0x41004AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_300 0x41004B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_301 0x41004B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_302 0x41004B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_303 0x41004BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_304 0x41004C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_305 0x41004C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_306 0x41004C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_307 0x41004CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_308 0x41004D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_309 0x41004D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_310 0x41004D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_311 0x41004DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_312 0x41004E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_313 0x41004E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_314 0x41004E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_315 0x41004EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_316 0x41004F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_317 0x41004F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_318 0x41004F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_319 0x41004FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_320 0x4100500 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_321 0x4100504 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_322 0x4100508 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_323 0x410050C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_324 0x4100510 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_325 0x4100514 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_326 0x4100518 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_327 0x410051C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_328 0x4100520 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_329 0x4100524 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_330 0x4100528 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_331 0x410052C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_332 0x4100530 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_333 0x4100534 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_334 0x4100538 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_335 0x410053C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_336 0x4100540 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_337 0x4100544 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_338 0x4100548 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_339 0x410054C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_340 0x4100550 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_341 0x4100554 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_342 0x4100558 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_343 0x410055C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_344 0x4100560 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_345 0x4100564 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_346 0x4100568 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_347 0x410056C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_348 0x4100570 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_349 0x4100574 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_350 0x4100578 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_351 0x410057C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_352 0x4100580 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_353 0x4100584 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_354 0x4100588 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_355 0x410058C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_356 0x4100590 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_357 0x4100594 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_358 0x4100598 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_359 0x410059C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_360 0x41005A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_361 0x41005A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_362 0x41005A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_363 0x41005AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_364 0x41005B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_365 0x41005B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_366 0x41005B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_367 0x41005BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_368 0x41005C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_369 0x41005C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_370 0x41005C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_371 0x41005CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_372 0x41005D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_373 0x41005D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_374 0x41005D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_375 0x41005DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_376 0x41005E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_377 0x41005E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_378 0x41005E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_379 0x41005EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_380 0x41005F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_381 0x41005F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_382 0x41005F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_383 0x41005FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_384 0x4100600 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_385 0x4100604 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_386 0x4100608 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_387 0x410060C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_388 0x4100610 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_389 0x4100614 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_390 0x4100618 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_391 0x410061C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_392 0x4100620 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_393 0x4100624 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_394 0x4100628 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_395 0x410062C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_396 0x4100630 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_397 0x4100634 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_398 0x4100638 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_399 0x410063C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_400 0x4100640 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_401 0x4100644 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_402 0x4100648 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_403 0x410064C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_404 0x4100650 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_405 0x4100654 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_406 0x4100658 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_407 0x410065C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_408 0x4100660 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_409 0x4100664 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_410 0x4100668 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_411 0x410066C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_412 0x4100670 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_413 0x4100674 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_414 0x4100678 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_415 0x410067C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_416 0x4100680 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_417 0x4100684 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_418 0x4100688 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_419 0x410068C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_420 0x4100690 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_421 0x4100694 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_422 0x4100698 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_423 0x410069C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_424 0x41006A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_425 0x41006A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_426 0x41006A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_427 0x41006AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_428 0x41006B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_429 0x41006B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_430 0x41006B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_431 0x41006BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_432 0x41006C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_433 0x41006C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_434 0x41006C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_435 0x41006CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_436 0x41006D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_437 0x41006D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_438 0x41006D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_439 0x41006DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_440 0x41006E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_441 0x41006E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_442 0x41006E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_443 0x41006EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_444 0x41006F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_445 0x41006F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_446 0x41006F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_447 0x41006FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_448 0x4100700 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_449 0x4100704 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_450 0x4100708 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_451 0x410070C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_452 0x4100710 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_453 0x4100714 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_454 0x4100718 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_455 0x410071C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_456 0x4100720 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_457 0x4100724 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_458 0x4100728 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_459 0x410072C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_460 0x4100730 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_461 0x4100734 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_462 0x4100738 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_463 0x410073C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_464 0x4100740 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_465 0x4100744 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_466 0x4100748 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_467 0x410074C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_468 0x4100750 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_469 0x4100754 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_470 0x4100758 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_471 0x410075C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_472 0x4100760 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_473 0x4100764 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_474 0x4100768 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_475 0x410076C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_476 0x4100770 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_477 0x4100774 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_478 0x4100778 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_479 0x410077C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_480 0x4100780 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_481 0x4100784 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_482 0x4100788 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_483 0x410078C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_484 0x4100790 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_485 0x4100794 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_486 0x4100798 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_487 0x410079C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_488 0x41007A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_489 0x41007A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_490 0x41007A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_491 0x41007AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_492 0x41007B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_493 0x41007B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_494 0x41007B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_495 0x41007BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_496 0x41007C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_497 0x41007C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_498 0x41007C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_499 0x41007CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_500 0x41007D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_501 0x41007D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_502 0x41007D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_503 0x41007DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_504 0x41007E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_505 0x41007E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_506 0x41007E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_507 0x41007EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_508 0x41007F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_509 0x41007F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_510 0x41007F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_511 0x41007FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_512 0x4100800 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_513 0x4100804 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_514 0x4100808 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_515 0x410080C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_516 0x4100810 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_517 0x4100814 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_518 0x4100818 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_519 0x410081C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_520 0x4100820 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_521 0x4100824 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_522 0x4100828 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_523 0x410082C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_524 0x4100830 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_525 0x4100834 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_526 0x4100838 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_527 0x410083C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_528 0x4100840 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_529 0x4100844 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_530 0x4100848 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_531 0x410084C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_532 0x4100850 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_533 0x4100854 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_534 0x4100858 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_535 0x410085C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_536 0x4100860 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_537 0x4100864 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_538 0x4100868 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_539 0x410086C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_540 0x4100870 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_541 0x4100874 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_542 0x4100878 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_543 0x410087C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_544 0x4100880 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_545 0x4100884 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_546 0x4100888 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_547 0x410088C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_548 0x4100890 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_549 0x4100894 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_550 0x4100898 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_551 0x410089C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_552 0x41008A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_553 0x41008A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_554 0x41008A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_555 0x41008AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_556 0x41008B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_557 0x41008B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_558 0x41008B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_559 0x41008BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_560 0x41008C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_561 0x41008C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_562 0x41008C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_563 0x41008CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_564 0x41008D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_565 0x41008D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_566 0x41008D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_567 0x41008DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_568 0x41008E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_569 0x41008E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_570 0x41008E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_571 0x41008EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_572 0x41008F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_573 0x41008F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_574 0x41008F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_575 0x41008FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_576 0x4100900 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_577 0x4100904 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_578 0x4100908 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_579 0x410090C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_580 0x4100910 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_581 0x4100914 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_582 0x4100918 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_583 0x410091C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_584 0x4100920 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_585 0x4100924 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_586 0x4100928 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_587 0x410092C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_588 0x4100930 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_589 0x4100934 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_590 0x4100938 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_591 0x410093C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_592 0x4100940 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_593 0x4100944 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_594 0x4100948 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_595 0x410094C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_596 0x4100950 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_597 0x4100954 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_598 0x4100958 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_599 0x410095C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_600 0x4100960 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_601 0x4100964 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_602 0x4100968 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_603 0x410096C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_604 0x4100970 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_605 0x4100974 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_606 0x4100978 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_607 0x410097C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_608 0x4100980 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_609 0x4100984 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_610 0x4100988 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_611 0x410098C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_612 0x4100990 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_613 0x4100994 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_614 0x4100998 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_615 0x410099C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_616 0x41009A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_617 0x41009A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_618 0x41009A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_619 0x41009AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_620 0x41009B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_621 0x41009B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_622 0x41009B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_623 0x41009BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_624 0x41009C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_625 0x41009C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_626 0x41009C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_627 0x41009CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_628 0x41009D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_629 0x41009D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_630 0x41009D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_631 0x41009DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_632 0x41009E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_633 0x41009E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_634 0x41009E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_635 0x41009EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_636 0x41009F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_637 0x41009F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_638 0x41009F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_639 0x41009FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_640 0x4100A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_641 0x4100A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_642 0x4100A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_643 0x4100A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_644 0x4100A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_645 0x4100A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_646 0x4100A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_647 0x4100A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_648 0x4100A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_649 0x4100A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_650 0x4100A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_651 0x4100A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_652 0x4100A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_653 0x4100A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_654 0x4100A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_655 0x4100A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_656 0x4100A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_657 0x4100A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_658 0x4100A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_659 0x4100A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_660 0x4100A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_661 0x4100A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_662 0x4100A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_663 0x4100A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_664 0x4100A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_665 0x4100A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_666 0x4100A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_667 0x4100A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_668 0x4100A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_669 0x4100A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_670 0x4100A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_671 0x4100A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_672 0x4100A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_673 0x4100A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_674 0x4100A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_675 0x4100A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_676 0x4100A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_677 0x4100A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_678 0x4100A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_679 0x4100A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_680 0x4100AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_681 0x4100AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_682 0x4100AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_683 0x4100AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_684 0x4100AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_685 0x4100AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_686 0x4100AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_687 0x4100ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_688 0x4100AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_689 0x4100AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_690 0x4100AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_691 0x4100ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_692 0x4100AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_693 0x4100AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_694 0x4100AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_695 0x4100ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_696 0x4100AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_697 0x4100AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_698 0x4100AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_699 0x4100AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_700 0x4100AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_701 0x4100AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_702 0x4100AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_703 0x4100AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_704 0x4100B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_705 0x4100B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_706 0x4100B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_707 0x4100B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_708 0x4100B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_709 0x4100B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_710 0x4100B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_711 0x4100B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_712 0x4100B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_713 0x4100B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_714 0x4100B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_715 0x4100B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_716 0x4100B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_717 0x4100B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_718 0x4100B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_719 0x4100B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_720 0x4100B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_721 0x4100B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_722 0x4100B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_723 0x4100B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_724 0x4100B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_725 0x4100B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_726 0x4100B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_727 0x4100B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_728 0x4100B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_729 0x4100B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_730 0x4100B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_731 0x4100B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_732 0x4100B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_733 0x4100B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_734 0x4100B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_735 0x4100B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_736 0x4100B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_737 0x4100B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_738 0x4100B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_739 0x4100B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_740 0x4100B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_741 0x4100B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_742 0x4100B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_743 0x4100B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_744 0x4100BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_745 0x4100BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_746 0x4100BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_747 0x4100BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_748 0x4100BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_749 0x4100BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_750 0x4100BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_751 0x4100BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_752 0x4100BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_753 0x4100BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_754 0x4100BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_755 0x4100BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_756 0x4100BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_757 0x4100BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_758 0x4100BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_759 0x4100BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_760 0x4100BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_761 0x4100BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_762 0x4100BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_763 0x4100BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_764 0x4100BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_765 0x4100BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_766 0x4100BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_767 0x4100BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_768 0x4100C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_769 0x4100C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_770 0x4100C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_771 0x4100C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_772 0x4100C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_773 0x4100C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_774 0x4100C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_775 0x4100C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_776 0x4100C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_777 0x4100C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_778 0x4100C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_779 0x4100C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_780 0x4100C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_781 0x4100C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_782 0x4100C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_783 0x4100C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_784 0x4100C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_785 0x4100C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_786 0x4100C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_787 0x4100C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_788 0x4100C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_789 0x4100C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_790 0x4100C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_791 0x4100C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_792 0x4100C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_793 0x4100C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_794 0x4100C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_795 0x4100C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_796 0x4100C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_797 0x4100C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_798 0x4100C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_799 0x4100C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_800 0x4100C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_801 0x4100C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_802 0x4100C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_803 0x4100C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_804 0x4100C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_805 0x4100C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_806 0x4100C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_807 0x4100C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_808 0x4100CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_809 0x4100CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_810 0x4100CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_811 0x4100CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_812 0x4100CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_813 0x4100CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_814 0x4100CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_815 0x4100CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_816 0x4100CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_817 0x4100CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_818 0x4100CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_819 0x4100CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_820 0x4100CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_821 0x4100CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_822 0x4100CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_823 0x4100CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_824 0x4100CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_825 0x4100CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_826 0x4100CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_827 0x4100CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_828 0x4100CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_829 0x4100CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_830 0x4100CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_831 0x4100CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_832 0x4100D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_833 0x4100D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_834 0x4100D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_835 0x4100D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_836 0x4100D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_837 0x4100D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_838 0x4100D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_839 0x4100D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_840 0x4100D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_841 0x4100D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_842 0x4100D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_843 0x4100D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_844 0x4100D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_845 0x4100D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_846 0x4100D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_847 0x4100D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_848 0x4100D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_849 0x4100D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_850 0x4100D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_851 0x4100D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_852 0x4100D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_853 0x4100D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_854 0x4100D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_855 0x4100D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_856 0x4100D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_857 0x4100D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_858 0x4100D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_859 0x4100D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_860 0x4100D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_861 0x4100D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_862 0x4100D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_863 0x4100D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_864 0x4100D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_865 0x4100D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_866 0x4100D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_867 0x4100D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_868 0x4100D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_869 0x4100D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_870 0x4100D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_871 0x4100D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_872 0x4100DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_873 0x4100DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_874 0x4100DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_875 0x4100DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_876 0x4100DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_877 0x4100DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_878 0x4100DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_879 0x4100DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_880 0x4100DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_881 0x4100DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_882 0x4100DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_883 0x4100DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_884 0x4100DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_885 0x4100DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_886 0x4100DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_887 0x4100DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_888 0x4100DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_889 0x4100DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_890 0x4100DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_891 0x4100DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_892 0x4100DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_893 0x4100DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_894 0x4100DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_895 0x4100DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_896 0x4100E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_897 0x4100E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_898 0x4100E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_899 0x4100E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_900 0x4100E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_901 0x4100E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_902 0x4100E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_903 0x4100E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_904 0x4100E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_905 0x4100E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_906 0x4100E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_907 0x4100E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_908 0x4100E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_909 0x4100E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_910 0x4100E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_911 0x4100E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_912 0x4100E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_913 0x4100E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_914 0x4100E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_915 0x4100E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_916 0x4100E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_917 0x4100E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_918 0x4100E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_919 0x4100E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_920 0x4100E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_921 0x4100E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_922 0x4100E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_923 0x4100E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_924 0x4100E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_925 0x4100E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_926 0x4100E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_927 0x4100E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_928 0x4100E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_929 0x4100E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_930 0x4100E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_931 0x4100E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_932 0x4100E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_933 0x4100E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_934 0x4100E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_935 0x4100E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_936 0x4100EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_937 0x4100EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_938 0x4100EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_939 0x4100EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_940 0x4100EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_941 0x4100EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_942 0x4100EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_943 0x4100EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_944 0x4100EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_945 0x4100EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_946 0x4100EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_947 0x4100ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_948 0x4100ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_949 0x4100ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_950 0x4100ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_951 0x4100EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_952 0x4100EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_953 0x4100EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_954 0x4100EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_955 0x4100EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_956 0x4100EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_957 0x4100EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_958 0x4100EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_959 0x4100EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_960 0x4100F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_961 0x4100F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_962 0x4100F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_963 0x4100F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_964 0x4100F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_965 0x4100F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_966 0x4100F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_967 0x4100F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_968 0x4100F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_969 0x4100F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_970 0x4100F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_971 0x4100F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_972 0x4100F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_973 0x4100F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_974 0x4100F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_975 0x4100F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_976 0x4100F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_977 0x4100F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_978 0x4100F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_979 0x4100F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_980 0x4100F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_981 0x4100F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_982 0x4100F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_983 0x4100F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_984 0x4100F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_985 0x4100F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_986 0x4100F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_987 0x4100F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_988 0x4100F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_989 0x4100F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_990 0x4100F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_991 0x4100F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_992 0x4100F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_993 0x4100F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_994 0x4100F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_995 0x4100F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_996 0x4100F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_997 0x4100F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_998 0x4100F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_999 0x4100F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1000 0x4100FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1001 0x4100FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1002 0x4100FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1003 0x4100FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1004 0x4100FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1005 0x4100FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1006 0x4100FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1007 0x4100FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1008 0x4100FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1009 0x4100FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1010 0x4100FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1011 0x4100FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1012 0x4100FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1013 0x4100FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1014 0x4100FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1015 0x4100FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1016 0x4100FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1017 0x4100FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1018 0x4100FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1019 0x4100FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1020 0x4100FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1021 0x4100FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1022 0x4100FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1023 0x4100FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1024 0x4101000 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1025 0x4101004 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1026 0x4101008 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1027 0x410100C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1028 0x4101010 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1029 0x4101014 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1030 0x4101018 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1031 0x410101C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1032 0x4101020 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1033 0x4101024 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1034 0x4101028 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1035 0x410102C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1036 0x4101030 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1037 0x4101034 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1038 0x4101038 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1039 0x410103C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1040 0x4101040 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1041 0x4101044 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1042 0x4101048 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1043 0x410104C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1044 0x4101050 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1045 0x4101054 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1046 0x4101058 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1047 0x410105C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1048 0x4101060 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1049 0x4101064 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1050 0x4101068 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1051 0x410106C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1052 0x4101070 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1053 0x4101074 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1054 0x4101078 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1055 0x410107C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1056 0x4101080 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1057 0x4101084 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1058 0x4101088 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1059 0x410108C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1060 0x4101090 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1061 0x4101094 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1062 0x4101098 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1063 0x410109C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1064 0x41010A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1065 0x41010A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1066 0x41010A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1067 0x41010AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1068 0x41010B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1069 0x41010B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1070 0x41010B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1071 0x41010BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1072 0x41010C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1073 0x41010C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1074 0x41010C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1075 0x41010CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1076 0x41010D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1077 0x41010D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1078 0x41010D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1079 0x41010DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1080 0x41010E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1081 0x41010E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1082 0x41010E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1083 0x41010EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1084 0x41010F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1085 0x41010F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1086 0x41010F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1087 0x41010FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1088 0x4101100 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1089 0x4101104 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1090 0x4101108 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1091 0x410110C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1092 0x4101110 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1093 0x4101114 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1094 0x4101118 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1095 0x410111C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1096 0x4101120 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1097 0x4101124 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1098 0x4101128 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1099 0x410112C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1100 0x4101130 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1101 0x4101134 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1102 0x4101138 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1103 0x410113C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1104 0x4101140 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1105 0x4101144 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1106 0x4101148 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1107 0x410114C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1108 0x4101150 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1109 0x4101154 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1110 0x4101158 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1111 0x410115C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1112 0x4101160 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1113 0x4101164 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1114 0x4101168 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1115 0x410116C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1116 0x4101170 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1117 0x4101174 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1118 0x4101178 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1119 0x410117C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1120 0x4101180 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1121 0x4101184 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1122 0x4101188 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1123 0x410118C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1124 0x4101190 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1125 0x4101194 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1126 0x4101198 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1127 0x410119C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1128 0x41011A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1129 0x41011A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1130 0x41011A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1131 0x41011AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1132 0x41011B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1133 0x41011B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1134 0x41011B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1135 0x41011BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1136 0x41011C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1137 0x41011C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1138 0x41011C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1139 0x41011CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1140 0x41011D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1141 0x41011D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1142 0x41011D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1143 0x41011DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1144 0x41011E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1145 0x41011E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1146 0x41011E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1147 0x41011EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1148 0x41011F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1149 0x41011F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1150 0x41011F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1151 0x41011FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1152 0x4101200 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1153 0x4101204 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1154 0x4101208 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1155 0x410120C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1156 0x4101210 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1157 0x4101214 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1158 0x4101218 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1159 0x410121C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1160 0x4101220 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1161 0x4101224 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1162 0x4101228 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1163 0x410122C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1164 0x4101230 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1165 0x4101234 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1166 0x4101238 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1167 0x410123C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1168 0x4101240 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1169 0x4101244 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1170 0x4101248 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1171 0x410124C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1172 0x4101250 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1173 0x4101254 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1174 0x4101258 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1175 0x410125C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1176 0x4101260 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1177 0x4101264 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1178 0x4101268 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1179 0x410126C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1180 0x4101270 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1181 0x4101274 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1182 0x4101278 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1183 0x410127C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1184 0x4101280 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1185 0x4101284 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1186 0x4101288 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1187 0x410128C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1188 0x4101290 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1189 0x4101294 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1190 0x4101298 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1191 0x410129C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1192 0x41012A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1193 0x41012A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1194 0x41012A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1195 0x41012AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1196 0x41012B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1197 0x41012B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1198 0x41012B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1199 0x41012BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1200 0x41012C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1201 0x41012C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1202 0x41012C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1203 0x41012CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1204 0x41012D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1205 0x41012D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1206 0x41012D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1207 0x41012DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1208 0x41012E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1209 0x41012E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1210 0x41012E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1211 0x41012EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1212 0x41012F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1213 0x41012F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1214 0x41012F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1215 0x41012FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1216 0x4101300 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1217 0x4101304 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1218 0x4101308 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1219 0x410130C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1220 0x4101310 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1221 0x4101314 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1222 0x4101318 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1223 0x410131C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1224 0x4101320 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1225 0x4101324 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1226 0x4101328 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1227 0x410132C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1228 0x4101330 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1229 0x4101334 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1230 0x4101338 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1231 0x410133C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1232 0x4101340 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1233 0x4101344 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1234 0x4101348 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1235 0x410134C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1236 0x4101350 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1237 0x4101354 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1238 0x4101358 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1239 0x410135C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1240 0x4101360 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1241 0x4101364 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1242 0x4101368 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1243 0x410136C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1244 0x4101370 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1245 0x4101374 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1246 0x4101378 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1247 0x410137C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1248 0x4101380 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1249 0x4101384 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1250 0x4101388 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1251 0x410138C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1252 0x4101390 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1253 0x4101394 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1254 0x4101398 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1255 0x410139C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1256 0x41013A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1257 0x41013A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1258 0x41013A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1259 0x41013AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1260 0x41013B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1261 0x41013B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1262 0x41013B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1263 0x41013BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1264 0x41013C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1265 0x41013C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1266 0x41013C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1267 0x41013CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1268 0x41013D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1269 0x41013D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1270 0x41013D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1271 0x41013DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1272 0x41013E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1273 0x41013E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1274 0x41013E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1275 0x41013EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1276 0x41013F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1277 0x41013F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1278 0x41013F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1279 0x41013FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1280 0x4101400 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1281 0x4101404 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1282 0x4101408 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1283 0x410140C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1284 0x4101410 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1285 0x4101414 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1286 0x4101418 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1287 0x410141C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1288 0x4101420 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1289 0x4101424 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1290 0x4101428 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1291 0x410142C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1292 0x4101430 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1293 0x4101434 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1294 0x4101438 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1295 0x410143C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1296 0x4101440 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1297 0x4101444 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1298 0x4101448 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1299 0x410144C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1300 0x4101450 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1301 0x4101454 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1302 0x4101458 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1303 0x410145C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1304 0x4101460 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1305 0x4101464 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1306 0x4101468 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1307 0x410146C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1308 0x4101470 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1309 0x4101474 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1310 0x4101478 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1311 0x410147C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1312 0x4101480 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1313 0x4101484 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1314 0x4101488 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1315 0x410148C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1316 0x4101490 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1317 0x4101494 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1318 0x4101498 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1319 0x410149C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1320 0x41014A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1321 0x41014A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1322 0x41014A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1323 0x41014AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1324 0x41014B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1325 0x41014B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1326 0x41014B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1327 0x41014BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1328 0x41014C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1329 0x41014C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1330 0x41014C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1331 0x41014CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1332 0x41014D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1333 0x41014D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1334 0x41014D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1335 0x41014DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1336 0x41014E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1337 0x41014E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1338 0x41014E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1339 0x41014EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1340 0x41014F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1341 0x41014F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1342 0x41014F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1343 0x41014FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1344 0x4101500 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1345 0x4101504 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1346 0x4101508 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1347 0x410150C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1348 0x4101510 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1349 0x4101514 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1350 0x4101518 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1351 0x410151C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1352 0x4101520 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1353 0x4101524 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1354 0x4101528 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1355 0x410152C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1356 0x4101530 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1357 0x4101534 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1358 0x4101538 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1359 0x410153C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1360 0x4101540 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1361 0x4101544 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1362 0x4101548 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1363 0x410154C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1364 0x4101550 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1365 0x4101554 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1366 0x4101558 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1367 0x410155C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1368 0x4101560 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1369 0x4101564 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1370 0x4101568 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1371 0x410156C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1372 0x4101570 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1373 0x4101574 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1374 0x4101578 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1375 0x410157C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1376 0x4101580 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1377 0x4101584 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1378 0x4101588 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1379 0x410158C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1380 0x4101590 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1381 0x4101594 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1382 0x4101598 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1383 0x410159C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1384 0x41015A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1385 0x41015A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1386 0x41015A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1387 0x41015AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1388 0x41015B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1389 0x41015B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1390 0x41015B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1391 0x41015BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1392 0x41015C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1393 0x41015C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1394 0x41015C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1395 0x41015CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1396 0x41015D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1397 0x41015D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1398 0x41015D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1399 0x41015DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1400 0x41015E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1401 0x41015E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1402 0x41015E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1403 0x41015EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1404 0x41015F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1405 0x41015F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1406 0x41015F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1407 0x41015FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1408 0x4101600 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1409 0x4101604 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1410 0x4101608 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1411 0x410160C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1412 0x4101610 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1413 0x4101614 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1414 0x4101618 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1415 0x410161C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1416 0x4101620 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1417 0x4101624 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1418 0x4101628 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1419 0x410162C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1420 0x4101630 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1421 0x4101634 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1422 0x4101638 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1423 0x410163C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1424 0x4101640 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1425 0x4101644 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1426 0x4101648 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1427 0x410164C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1428 0x4101650 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1429 0x4101654 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1430 0x4101658 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1431 0x410165C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1432 0x4101660 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1433 0x4101664 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1434 0x4101668 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1435 0x410166C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1436 0x4101670 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1437 0x4101674 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1438 0x4101678 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1439 0x410167C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1440 0x4101680 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1441 0x4101684 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1442 0x4101688 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1443 0x410168C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1444 0x4101690 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1445 0x4101694 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1446 0x4101698 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1447 0x410169C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1448 0x41016A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1449 0x41016A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1450 0x41016A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1451 0x41016AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1452 0x41016B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1453 0x41016B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1454 0x41016B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1455 0x41016BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1456 0x41016C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1457 0x41016C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1458 0x41016C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1459 0x41016CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1460 0x41016D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1461 0x41016D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1462 0x41016D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1463 0x41016DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1464 0x41016E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1465 0x41016E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1466 0x41016E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1467 0x41016EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1468 0x41016F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1469 0x41016F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1470 0x41016F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1471 0x41016FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1472 0x4101700 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1473 0x4101704 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1474 0x4101708 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1475 0x410170C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1476 0x4101710 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1477 0x4101714 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1478 0x4101718 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1479 0x410171C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1480 0x4101720 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1481 0x4101724 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1482 0x4101728 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1483 0x410172C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1484 0x4101730 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1485 0x4101734 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1486 0x4101738 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1487 0x410173C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1488 0x4101740 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1489 0x4101744 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1490 0x4101748 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1491 0x410174C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1492 0x4101750 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1493 0x4101754 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1494 0x4101758 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1495 0x410175C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1496 0x4101760 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1497 0x4101764 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1498 0x4101768 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1499 0x410176C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1500 0x4101770 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1501 0x4101774 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1502 0x4101778 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1503 0x410177C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1504 0x4101780 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1505 0x4101784 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1506 0x4101788 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1507 0x410178C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1508 0x4101790 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1509 0x4101794 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1510 0x4101798 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1511 0x410179C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1512 0x41017A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1513 0x41017A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1514 0x41017A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1515 0x41017AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1516 0x41017B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1517 0x41017B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1518 0x41017B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1519 0x41017BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1520 0x41017C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1521 0x41017C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1522 0x41017C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1523 0x41017CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1524 0x41017D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1525 0x41017D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1526 0x41017D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1527 0x41017DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1528 0x41017E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1529 0x41017E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1530 0x41017E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1531 0x41017EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1532 0x41017F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1533 0x41017F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1534 0x41017F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1535 0x41017FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1536 0x4101800 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1537 0x4101804 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1538 0x4101808 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1539 0x410180C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1540 0x4101810 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1541 0x4101814 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1542 0x4101818 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1543 0x410181C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1544 0x4101820 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1545 0x4101824 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1546 0x4101828 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1547 0x410182C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1548 0x4101830 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1549 0x4101834 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1550 0x4101838 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1551 0x410183C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1552 0x4101840 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1553 0x4101844 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1554 0x4101848 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1555 0x410184C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1556 0x4101850 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1557 0x4101854 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1558 0x4101858 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1559 0x410185C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1560 0x4101860 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1561 0x4101864 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1562 0x4101868 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1563 0x410186C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1564 0x4101870 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1565 0x4101874 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1566 0x4101878 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1567 0x410187C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1568 0x4101880 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1569 0x4101884 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1570 0x4101888 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1571 0x410188C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1572 0x4101890 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1573 0x4101894 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1574 0x4101898 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1575 0x410189C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1576 0x41018A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1577 0x41018A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1578 0x41018A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1579 0x41018AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1580 0x41018B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1581 0x41018B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1582 0x41018B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1583 0x41018BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1584 0x41018C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1585 0x41018C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1586 0x41018C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1587 0x41018CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1588 0x41018D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1589 0x41018D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1590 0x41018D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1591 0x41018DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1592 0x41018E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1593 0x41018E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1594 0x41018E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1595 0x41018EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1596 0x41018F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1597 0x41018F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1598 0x41018F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1599 0x41018FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1600 0x4101900 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1601 0x4101904 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1602 0x4101908 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1603 0x410190C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1604 0x4101910 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1605 0x4101914 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1606 0x4101918 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1607 0x410191C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1608 0x4101920 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1609 0x4101924 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1610 0x4101928 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1611 0x410192C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1612 0x4101930 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1613 0x4101934 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1614 0x4101938 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1615 0x410193C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1616 0x4101940 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1617 0x4101944 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1618 0x4101948 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1619 0x410194C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1620 0x4101950 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1621 0x4101954 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1622 0x4101958 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1623 0x410195C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1624 0x4101960 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1625 0x4101964 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1626 0x4101968 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1627 0x410196C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1628 0x4101970 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1629 0x4101974 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1630 0x4101978 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1631 0x410197C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1632 0x4101980 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1633 0x4101984 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1634 0x4101988 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1635 0x410198C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1636 0x4101990 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1637 0x4101994 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1638 0x4101998 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1639 0x410199C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1640 0x41019A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1641 0x41019A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1642 0x41019A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1643 0x41019AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1644 0x41019B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1645 0x41019B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1646 0x41019B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1647 0x41019BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1648 0x41019C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1649 0x41019C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1650 0x41019C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1651 0x41019CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1652 0x41019D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1653 0x41019D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1654 0x41019D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1655 0x41019DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1656 0x41019E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1657 0x41019E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1658 0x41019E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1659 0x41019EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1660 0x41019F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1661 0x41019F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1662 0x41019F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1663 0x41019FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1664 0x4101A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1665 0x4101A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1666 0x4101A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1667 0x4101A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1668 0x4101A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1669 0x4101A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1670 0x4101A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1671 0x4101A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1672 0x4101A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1673 0x4101A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1674 0x4101A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1675 0x4101A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1676 0x4101A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1677 0x4101A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1678 0x4101A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1679 0x4101A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1680 0x4101A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1681 0x4101A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1682 0x4101A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1683 0x4101A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1684 0x4101A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1685 0x4101A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1686 0x4101A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1687 0x4101A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1688 0x4101A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1689 0x4101A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1690 0x4101A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1691 0x4101A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1692 0x4101A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1693 0x4101A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1694 0x4101A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1695 0x4101A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1696 0x4101A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1697 0x4101A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1698 0x4101A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1699 0x4101A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1700 0x4101A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1701 0x4101A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1702 0x4101A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1703 0x4101A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1704 0x4101AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1705 0x4101AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1706 0x4101AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1707 0x4101AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1708 0x4101AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1709 0x4101AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1710 0x4101AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1711 0x4101ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1712 0x4101AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1713 0x4101AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1714 0x4101AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1715 0x4101ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1716 0x4101AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1717 0x4101AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1718 0x4101AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1719 0x4101ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1720 0x4101AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1721 0x4101AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1722 0x4101AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1723 0x4101AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1724 0x4101AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1725 0x4101AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1726 0x4101AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1727 0x4101AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1728 0x4101B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1729 0x4101B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1730 0x4101B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1731 0x4101B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1732 0x4101B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1733 0x4101B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1734 0x4101B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1735 0x4101B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1736 0x4101B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1737 0x4101B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1738 0x4101B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1739 0x4101B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1740 0x4101B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1741 0x4101B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1742 0x4101B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1743 0x4101B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1744 0x4101B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1745 0x4101B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1746 0x4101B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1747 0x4101B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1748 0x4101B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1749 0x4101B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1750 0x4101B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1751 0x4101B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1752 0x4101B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1753 0x4101B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1754 0x4101B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1755 0x4101B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1756 0x4101B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1757 0x4101B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1758 0x4101B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1759 0x4101B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1760 0x4101B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1761 0x4101B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1762 0x4101B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1763 0x4101B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1764 0x4101B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1765 0x4101B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1766 0x4101B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1767 0x4101B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1768 0x4101BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1769 0x4101BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1770 0x4101BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1771 0x4101BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1772 0x4101BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1773 0x4101BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1774 0x4101BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1775 0x4101BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1776 0x4101BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1777 0x4101BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1778 0x4101BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1779 0x4101BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1780 0x4101BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1781 0x4101BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1782 0x4101BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1783 0x4101BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1784 0x4101BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1785 0x4101BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1786 0x4101BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1787 0x4101BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1788 0x4101BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1789 0x4101BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1790 0x4101BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1791 0x4101BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1792 0x4101C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1793 0x4101C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1794 0x4101C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1795 0x4101C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1796 0x4101C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1797 0x4101C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1798 0x4101C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1799 0x4101C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1800 0x4101C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1801 0x4101C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1802 0x4101C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1803 0x4101C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1804 0x4101C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1805 0x4101C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1806 0x4101C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1807 0x4101C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1808 0x4101C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1809 0x4101C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1810 0x4101C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1811 0x4101C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1812 0x4101C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1813 0x4101C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1814 0x4101C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1815 0x4101C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1816 0x4101C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1817 0x4101C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1818 0x4101C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1819 0x4101C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1820 0x4101C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1821 0x4101C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1822 0x4101C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1823 0x4101C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1824 0x4101C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1825 0x4101C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1826 0x4101C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1827 0x4101C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1828 0x4101C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1829 0x4101C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1830 0x4101C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1831 0x4101C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1832 0x4101CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1833 0x4101CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1834 0x4101CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1835 0x4101CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1836 0x4101CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1837 0x4101CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1838 0x4101CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1839 0x4101CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1840 0x4101CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1841 0x4101CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1842 0x4101CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1843 0x4101CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1844 0x4101CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1845 0x4101CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1846 0x4101CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1847 0x4101CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1848 0x4101CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1849 0x4101CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1850 0x4101CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1851 0x4101CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1852 0x4101CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1853 0x4101CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1854 0x4101CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1855 0x4101CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1856 0x4101D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1857 0x4101D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1858 0x4101D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1859 0x4101D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1860 0x4101D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1861 0x4101D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1862 0x4101D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1863 0x4101D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1864 0x4101D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1865 0x4101D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1866 0x4101D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1867 0x4101D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1868 0x4101D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1869 0x4101D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1870 0x4101D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1871 0x4101D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1872 0x4101D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1873 0x4101D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1874 0x4101D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1875 0x4101D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1876 0x4101D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1877 0x4101D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1878 0x4101D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1879 0x4101D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1880 0x4101D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1881 0x4101D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1882 0x4101D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1883 0x4101D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1884 0x4101D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1885 0x4101D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1886 0x4101D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1887 0x4101D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1888 0x4101D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1889 0x4101D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1890 0x4101D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1891 0x4101D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1892 0x4101D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1893 0x4101D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1894 0x4101D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1895 0x4101D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1896 0x4101DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1897 0x4101DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1898 0x4101DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1899 0x4101DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1900 0x4101DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1901 0x4101DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1902 0x4101DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1903 0x4101DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1904 0x4101DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1905 0x4101DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1906 0x4101DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1907 0x4101DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1908 0x4101DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1909 0x4101DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1910 0x4101DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1911 0x4101DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1912 0x4101DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1913 0x4101DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1914 0x4101DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1915 0x4101DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1916 0x4101DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1917 0x4101DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1918 0x4101DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1919 0x4101DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1920 0x4101E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1921 0x4101E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1922 0x4101E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1923 0x4101E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1924 0x4101E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1925 0x4101E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1926 0x4101E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1927 0x4101E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1928 0x4101E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1929 0x4101E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1930 0x4101E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1931 0x4101E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1932 0x4101E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1933 0x4101E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1934 0x4101E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1935 0x4101E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1936 0x4101E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1937 0x4101E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1938 0x4101E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1939 0x4101E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1940 0x4101E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1941 0x4101E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1942 0x4101E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1943 0x4101E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1944 0x4101E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1945 0x4101E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1946 0x4101E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1947 0x4101E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1948 0x4101E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1949 0x4101E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1950 0x4101E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1951 0x4101E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1952 0x4101E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1953 0x4101E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1954 0x4101E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1955 0x4101E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1956 0x4101E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1957 0x4101E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1958 0x4101E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1959 0x4101E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1960 0x4101EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1961 0x4101EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1962 0x4101EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1963 0x4101EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1964 0x4101EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1965 0x4101EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1966 0x4101EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1967 0x4101EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1968 0x4101EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1969 0x4101EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1970 0x4101EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1971 0x4101ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1972 0x4101ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1973 0x4101ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1974 0x4101ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1975 0x4101EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1976 0x4101EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1977 0x4101EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1978 0x4101EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1979 0x4101EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1980 0x4101EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1981 0x4101EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1982 0x4101EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1983 0x4101EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1984 0x4101F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1985 0x4101F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1986 0x4101F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1987 0x4101F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1988 0x4101F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1989 0x4101F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1990 0x4101F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1991 0x4101F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1992 0x4101F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1993 0x4101F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1994 0x4101F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1995 0x4101F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1996 0x4101F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1997 0x4101F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1998 0x4101F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1999 0x4101F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2000 0x4101F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2001 0x4101F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2002 0x4101F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2003 0x4101F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2004 0x4101F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2005 0x4101F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2006 0x4101F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2007 0x4101F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2008 0x4101F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2009 0x4101F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2010 0x4101F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2011 0x4101F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2012 0x4101F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2013 0x4101F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2014 0x4101F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2015 0x4101F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2016 0x4101F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2017 0x4101F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2018 0x4101F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2019 0x4101F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2020 0x4101F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2021 0x4101F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2022 0x4101F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2023 0x4101F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2024 0x4101FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2025 0x4101FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2026 0x4101FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2027 0x4101FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2028 0x4101FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2029 0x4101FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2030 0x4101FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2031 0x4101FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2032 0x4101FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2033 0x4101FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2034 0x4101FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2035 0x4101FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2036 0x4101FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2037 0x4101FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2038 0x4101FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2039 0x4101FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2040 0x4101FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2041 0x4101FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2042 0x4101FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2043 0x4101FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2044 0x4101FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2045 0x4101FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2046 0x4101FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2047 0x4101FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2048 0x4102000 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2049 0x4102004 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2050 0x4102008 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2051 0x410200C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2052 0x4102010 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2053 0x4102014 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2054 0x4102018 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2055 0x410201C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2056 0x4102020 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2057 0x4102024 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2058 0x4102028 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2059 0x410202C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2060 0x4102030 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2061 0x4102034 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2062 0x4102038 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2063 0x410203C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2064 0x4102040 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2065 0x4102044 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2066 0x4102048 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2067 0x410204C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2068 0x4102050 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2069 0x4102054 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2070 0x4102058 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2071 0x410205C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2072 0x4102060 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2073 0x4102064 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2074 0x4102068 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2075 0x410206C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2076 0x4102070 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2077 0x4102074 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2078 0x4102078 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2079 0x410207C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2080 0x4102080 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2081 0x4102084 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2082 0x4102088 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2083 0x410208C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2084 0x4102090 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2085 0x4102094 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2086 0x4102098 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2087 0x410209C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2088 0x41020A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2089 0x41020A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2090 0x41020A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2091 0x41020AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2092 0x41020B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2093 0x41020B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2094 0x41020B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2095 0x41020BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2096 0x41020C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2097 0x41020C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2098 0x41020C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2099 0x41020CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2100 0x41020D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2101 0x41020D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2102 0x41020D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2103 0x41020DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2104 0x41020E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2105 0x41020E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2106 0x41020E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2107 0x41020EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2108 0x41020F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2109 0x41020F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2110 0x41020F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2111 0x41020FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2112 0x4102100 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2113 0x4102104 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2114 0x4102108 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2115 0x410210C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2116 0x4102110 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2117 0x4102114 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2118 0x4102118 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2119 0x410211C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2120 0x4102120 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2121 0x4102124 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2122 0x4102128 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2123 0x410212C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2124 0x4102130 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2125 0x4102134 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2126 0x4102138 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2127 0x410213C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2128 0x4102140 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2129 0x4102144 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2130 0x4102148 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2131 0x410214C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2132 0x4102150 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2133 0x4102154 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2134 0x4102158 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2135 0x410215C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2136 0x4102160 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2137 0x4102164 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2138 0x4102168 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2139 0x410216C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2140 0x4102170 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2141 0x4102174 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2142 0x4102178 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2143 0x410217C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2144 0x4102180 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2145 0x4102184 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2146 0x4102188 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2147 0x410218C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2148 0x4102190 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2149 0x4102194 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2150 0x4102198 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2151 0x410219C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2152 0x41021A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2153 0x41021A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2154 0x41021A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2155 0x41021AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2156 0x41021B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2157 0x41021B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2158 0x41021B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2159 0x41021BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2160 0x41021C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2161 0x41021C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2162 0x41021C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2163 0x41021CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2164 0x41021D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2165 0x41021D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2166 0x41021D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2167 0x41021DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2168 0x41021E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2169 0x41021E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2170 0x41021E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2171 0x41021EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2172 0x41021F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2173 0x41021F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2174 0x41021F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2175 0x41021FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2176 0x4102200 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2177 0x4102204 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2178 0x4102208 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2179 0x410220C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2180 0x4102210 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2181 0x4102214 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2182 0x4102218 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2183 0x410221C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2184 0x4102220 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2185 0x4102224 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2186 0x4102228 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2187 0x410222C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2188 0x4102230 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2189 0x4102234 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2190 0x4102238 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2191 0x410223C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2192 0x4102240 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2193 0x4102244 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2194 0x4102248 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2195 0x410224C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2196 0x4102250 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2197 0x4102254 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2198 0x4102258 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2199 0x410225C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2200 0x4102260 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2201 0x4102264 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2202 0x4102268 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2203 0x410226C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2204 0x4102270 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2205 0x4102274 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2206 0x4102278 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2207 0x410227C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2208 0x4102280 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2209 0x4102284 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2210 0x4102288 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2211 0x410228C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2212 0x4102290 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2213 0x4102294 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2214 0x4102298 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2215 0x410229C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2216 0x41022A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2217 0x41022A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2218 0x41022A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2219 0x41022AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2220 0x41022B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2221 0x41022B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2222 0x41022B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2223 0x41022BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2224 0x41022C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2225 0x41022C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2226 0x41022C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2227 0x41022CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2228 0x41022D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2229 0x41022D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2230 0x41022D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2231 0x41022DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2232 0x41022E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2233 0x41022E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2234 0x41022E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2235 0x41022EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2236 0x41022F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2237 0x41022F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2238 0x41022F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2239 0x41022FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2240 0x4102300 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2241 0x4102304 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2242 0x4102308 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2243 0x410230C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2244 0x4102310 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2245 0x4102314 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2246 0x4102318 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2247 0x410231C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2248 0x4102320 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2249 0x4102324 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2250 0x4102328 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2251 0x410232C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2252 0x4102330 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2253 0x4102334 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2254 0x4102338 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2255 0x410233C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2256 0x4102340 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2257 0x4102344 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2258 0x4102348 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2259 0x410234C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2260 0x4102350 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2261 0x4102354 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2262 0x4102358 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2263 0x410235C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2264 0x4102360 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2265 0x4102364 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2266 0x4102368 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2267 0x410236C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2268 0x4102370 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2269 0x4102374 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2270 0x4102378 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2271 0x410237C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2272 0x4102380 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2273 0x4102384 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2274 0x4102388 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2275 0x410238C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2276 0x4102390 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2277 0x4102394 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2278 0x4102398 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2279 0x410239C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2280 0x41023A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2281 0x41023A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2282 0x41023A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2283 0x41023AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2284 0x41023B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2285 0x41023B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2286 0x41023B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2287 0x41023BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2288 0x41023C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2289 0x41023C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2290 0x41023C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2291 0x41023CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2292 0x41023D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2293 0x41023D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2294 0x41023D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2295 0x41023DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2296 0x41023E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2297 0x41023E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2298 0x41023E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2299 0x41023EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2300 0x41023F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2301 0x41023F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2302 0x41023F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2303 0x41023FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2304 0x4102400 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2305 0x4102404 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2306 0x4102408 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2307 0x410240C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2308 0x4102410 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2309 0x4102414 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2310 0x4102418 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2311 0x410241C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2312 0x4102420 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2313 0x4102424 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2314 0x4102428 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2315 0x410242C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2316 0x4102430 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2317 0x4102434 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2318 0x4102438 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2319 0x410243C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2320 0x4102440 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2321 0x4102444 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2322 0x4102448 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2323 0x410244C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2324 0x4102450 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2325 0x4102454 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2326 0x4102458 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2327 0x410245C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2328 0x4102460 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2329 0x4102464 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2330 0x4102468 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2331 0x410246C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2332 0x4102470 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2333 0x4102474 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2334 0x4102478 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2335 0x410247C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2336 0x4102480 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2337 0x4102484 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2338 0x4102488 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2339 0x410248C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2340 0x4102490 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2341 0x4102494 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2342 0x4102498 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2343 0x410249C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2344 0x41024A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2345 0x41024A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2346 0x41024A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2347 0x41024AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2348 0x41024B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2349 0x41024B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2350 0x41024B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2351 0x41024BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2352 0x41024C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2353 0x41024C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2354 0x41024C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2355 0x41024CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2356 0x41024D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2357 0x41024D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2358 0x41024D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2359 0x41024DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2360 0x41024E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2361 0x41024E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2362 0x41024E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2363 0x41024EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2364 0x41024F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2365 0x41024F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2366 0x41024F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2367 0x41024FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2368 0x4102500 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2369 0x4102504 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2370 0x4102508 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2371 0x410250C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2372 0x4102510 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2373 0x4102514 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2374 0x4102518 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2375 0x410251C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2376 0x4102520 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2377 0x4102524 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2378 0x4102528 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2379 0x410252C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2380 0x4102530 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2381 0x4102534 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2382 0x4102538 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2383 0x410253C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2384 0x4102540 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2385 0x4102544 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2386 0x4102548 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2387 0x410254C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2388 0x4102550 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2389 0x4102554 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2390 0x4102558 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2391 0x410255C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2392 0x4102560 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2393 0x4102564 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2394 0x4102568 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2395 0x410256C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2396 0x4102570 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2397 0x4102574 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2398 0x4102578 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2399 0x410257C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2400 0x4102580 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2401 0x4102584 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2402 0x4102588 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2403 0x410258C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2404 0x4102590 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2405 0x4102594 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2406 0x4102598 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2407 0x410259C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2408 0x41025A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2409 0x41025A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2410 0x41025A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2411 0x41025AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2412 0x41025B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2413 0x41025B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2414 0x41025B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2415 0x41025BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2416 0x41025C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2417 0x41025C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2418 0x41025C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2419 0x41025CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2420 0x41025D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2421 0x41025D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2422 0x41025D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2423 0x41025DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2424 0x41025E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2425 0x41025E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2426 0x41025E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2427 0x41025EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2428 0x41025F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2429 0x41025F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2430 0x41025F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2431 0x41025FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2432 0x4102600 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2433 0x4102604 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2434 0x4102608 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2435 0x410260C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2436 0x4102610 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2437 0x4102614 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2438 0x4102618 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2439 0x410261C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2440 0x4102620 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2441 0x4102624 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2442 0x4102628 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2443 0x410262C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2444 0x4102630 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2445 0x4102634 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2446 0x4102638 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2447 0x410263C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2448 0x4102640 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2449 0x4102644 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2450 0x4102648 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2451 0x410264C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2452 0x4102650 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2453 0x4102654 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2454 0x4102658 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2455 0x410265C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2456 0x4102660 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2457 0x4102664 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2458 0x4102668 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2459 0x410266C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2460 0x4102670 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2461 0x4102674 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2462 0x4102678 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2463 0x410267C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2464 0x4102680 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2465 0x4102684 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2466 0x4102688 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2467 0x410268C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2468 0x4102690 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2469 0x4102694 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2470 0x4102698 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2471 0x410269C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2472 0x41026A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2473 0x41026A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2474 0x41026A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2475 0x41026AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2476 0x41026B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2477 0x41026B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2478 0x41026B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2479 0x41026BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2480 0x41026C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2481 0x41026C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2482 0x41026C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2483 0x41026CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2484 0x41026D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2485 0x41026D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2486 0x41026D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2487 0x41026DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2488 0x41026E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2489 0x41026E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2490 0x41026E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2491 0x41026EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2492 0x41026F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2493 0x41026F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2494 0x41026F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2495 0x41026FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2496 0x4102700 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2497 0x4102704 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2498 0x4102708 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2499 0x410270C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2500 0x4102710 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2501 0x4102714 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2502 0x4102718 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2503 0x410271C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2504 0x4102720 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2505 0x4102724 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2506 0x4102728 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2507 0x410272C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2508 0x4102730 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2509 0x4102734 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2510 0x4102738 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2511 0x410273C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2512 0x4102740 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2513 0x4102744 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2514 0x4102748 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2515 0x410274C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2516 0x4102750 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2517 0x4102754 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2518 0x4102758 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2519 0x410275C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2520 0x4102760 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2521 0x4102764 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2522 0x4102768 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2523 0x410276C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2524 0x4102770 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2525 0x4102774 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2526 0x4102778 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2527 0x410277C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2528 0x4102780 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2529 0x4102784 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2530 0x4102788 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2531 0x410278C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2532 0x4102790 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2533 0x4102794 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2534 0x4102798 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2535 0x410279C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2536 0x41027A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2537 0x41027A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2538 0x41027A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2539 0x41027AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2540 0x41027B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2541 0x41027B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2542 0x41027B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2543 0x41027BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2544 0x41027C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2545 0x41027C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2546 0x41027C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2547 0x41027CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2548 0x41027D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2549 0x41027D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2550 0x41027D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2551 0x41027DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2552 0x41027E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2553 0x41027E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2554 0x41027E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2555 0x41027EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2556 0x41027F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2557 0x41027F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2558 0x41027F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2559 0x41027FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2560 0x4102800 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2561 0x4102804 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2562 0x4102808 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2563 0x410280C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2564 0x4102810 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2565 0x4102814 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2566 0x4102818 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2567 0x410281C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2568 0x4102820 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2569 0x4102824 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2570 0x4102828 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2571 0x410282C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2572 0x4102830 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2573 0x4102834 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2574 0x4102838 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2575 0x410283C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2576 0x4102840 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2577 0x4102844 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2578 0x4102848 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2579 0x410284C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2580 0x4102850 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2581 0x4102854 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2582 0x4102858 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2583 0x410285C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2584 0x4102860 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2585 0x4102864 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2586 0x4102868 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2587 0x410286C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2588 0x4102870 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2589 0x4102874 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2590 0x4102878 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2591 0x410287C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2592 0x4102880 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2593 0x4102884 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2594 0x4102888 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2595 0x410288C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2596 0x4102890 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2597 0x4102894 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2598 0x4102898 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2599 0x410289C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2600 0x41028A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2601 0x41028A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2602 0x41028A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2603 0x41028AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2604 0x41028B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2605 0x41028B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2606 0x41028B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2607 0x41028BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2608 0x41028C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2609 0x41028C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2610 0x41028C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2611 0x41028CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2612 0x41028D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2613 0x41028D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2614 0x41028D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2615 0x41028DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2616 0x41028E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2617 0x41028E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2618 0x41028E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2619 0x41028EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2620 0x41028F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2621 0x41028F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2622 0x41028F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2623 0x41028FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2624 0x4102900 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2625 0x4102904 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2626 0x4102908 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2627 0x410290C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2628 0x4102910 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2629 0x4102914 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2630 0x4102918 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2631 0x410291C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2632 0x4102920 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2633 0x4102924 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2634 0x4102928 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2635 0x410292C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2636 0x4102930 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2637 0x4102934 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2638 0x4102938 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2639 0x410293C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2640 0x4102940 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2641 0x4102944 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2642 0x4102948 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2643 0x410294C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2644 0x4102950 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2645 0x4102954 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2646 0x4102958 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2647 0x410295C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2648 0x4102960 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2649 0x4102964 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2650 0x4102968 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2651 0x410296C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2652 0x4102970 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2653 0x4102974 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2654 0x4102978 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2655 0x410297C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2656 0x4102980 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2657 0x4102984 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2658 0x4102988 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2659 0x410298C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2660 0x4102990 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2661 0x4102994 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2662 0x4102998 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2663 0x410299C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2664 0x41029A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2665 0x41029A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2666 0x41029A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2667 0x41029AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2668 0x41029B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2669 0x41029B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2670 0x41029B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2671 0x41029BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2672 0x41029C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2673 0x41029C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2674 0x41029C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2675 0x41029CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2676 0x41029D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2677 0x41029D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2678 0x41029D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2679 0x41029DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2680 0x41029E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2681 0x41029E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2682 0x41029E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2683 0x41029EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2684 0x41029F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2685 0x41029F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2686 0x41029F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2687 0x41029FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2688 0x4102A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2689 0x4102A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2690 0x4102A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2691 0x4102A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2692 0x4102A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2693 0x4102A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2694 0x4102A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2695 0x4102A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2696 0x4102A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2697 0x4102A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2698 0x4102A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2699 0x4102A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2700 0x4102A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2701 0x4102A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2702 0x4102A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2703 0x4102A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2704 0x4102A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2705 0x4102A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2706 0x4102A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2707 0x4102A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2708 0x4102A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2709 0x4102A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2710 0x4102A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2711 0x4102A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2712 0x4102A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2713 0x4102A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2714 0x4102A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2715 0x4102A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2716 0x4102A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2717 0x4102A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2718 0x4102A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2719 0x4102A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2720 0x4102A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2721 0x4102A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2722 0x4102A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2723 0x4102A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2724 0x4102A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2725 0x4102A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2726 0x4102A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2727 0x4102A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2728 0x4102AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2729 0x4102AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2730 0x4102AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2731 0x4102AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2732 0x4102AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2733 0x4102AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2734 0x4102AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2735 0x4102ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2736 0x4102AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2737 0x4102AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2738 0x4102AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2739 0x4102ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2740 0x4102AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2741 0x4102AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2742 0x4102AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2743 0x4102ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2744 0x4102AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2745 0x4102AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2746 0x4102AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2747 0x4102AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2748 0x4102AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2749 0x4102AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2750 0x4102AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2751 0x4102AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2752 0x4102B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2753 0x4102B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2754 0x4102B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2755 0x4102B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2756 0x4102B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2757 0x4102B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2758 0x4102B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2759 0x4102B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2760 0x4102B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2761 0x4102B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2762 0x4102B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2763 0x4102B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2764 0x4102B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2765 0x4102B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2766 0x4102B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2767 0x4102B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2768 0x4102B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2769 0x4102B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2770 0x4102B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2771 0x4102B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2772 0x4102B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2773 0x4102B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2774 0x4102B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2775 0x4102B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2776 0x4102B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2777 0x4102B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2778 0x4102B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2779 0x4102B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2780 0x4102B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2781 0x4102B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2782 0x4102B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2783 0x4102B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2784 0x4102B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2785 0x4102B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2786 0x4102B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2787 0x4102B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2788 0x4102B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2789 0x4102B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2790 0x4102B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2791 0x4102B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2792 0x4102BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2793 0x4102BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2794 0x4102BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2795 0x4102BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2796 0x4102BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2797 0x4102BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2798 0x4102BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2799 0x4102BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2800 0x4102BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2801 0x4102BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2802 0x4102BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2803 0x4102BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2804 0x4102BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2805 0x4102BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2806 0x4102BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2807 0x4102BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2808 0x4102BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2809 0x4102BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2810 0x4102BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2811 0x4102BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2812 0x4102BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2813 0x4102BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2814 0x4102BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2815 0x4102BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2816 0x4102C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2817 0x4102C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2818 0x4102C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2819 0x4102C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2820 0x4102C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2821 0x4102C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2822 0x4102C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2823 0x4102C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2824 0x4102C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2825 0x4102C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2826 0x4102C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2827 0x4102C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2828 0x4102C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2829 0x4102C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2830 0x4102C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2831 0x4102C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2832 0x4102C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2833 0x4102C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2834 0x4102C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2835 0x4102C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2836 0x4102C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2837 0x4102C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2838 0x4102C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2839 0x4102C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2840 0x4102C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2841 0x4102C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2842 0x4102C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2843 0x4102C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2844 0x4102C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2845 0x4102C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2846 0x4102C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2847 0x4102C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2848 0x4102C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2849 0x4102C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2850 0x4102C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2851 0x4102C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2852 0x4102C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2853 0x4102C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2854 0x4102C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2855 0x4102C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2856 0x4102CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2857 0x4102CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2858 0x4102CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2859 0x4102CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2860 0x4102CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2861 0x4102CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2862 0x4102CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2863 0x4102CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2864 0x4102CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2865 0x4102CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2866 0x4102CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2867 0x4102CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2868 0x4102CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2869 0x4102CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2870 0x4102CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2871 0x4102CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2872 0x4102CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2873 0x4102CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2874 0x4102CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2875 0x4102CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2876 0x4102CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2877 0x4102CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2878 0x4102CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2879 0x4102CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2880 0x4102D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2881 0x4102D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2882 0x4102D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2883 0x4102D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2884 0x4102D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2885 0x4102D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2886 0x4102D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2887 0x4102D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2888 0x4102D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2889 0x4102D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2890 0x4102D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2891 0x4102D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2892 0x4102D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2893 0x4102D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2894 0x4102D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2895 0x4102D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2896 0x4102D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2897 0x4102D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2898 0x4102D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2899 0x4102D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2900 0x4102D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2901 0x4102D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2902 0x4102D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2903 0x4102D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2904 0x4102D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2905 0x4102D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2906 0x4102D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2907 0x4102D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2908 0x4102D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2909 0x4102D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2910 0x4102D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2911 0x4102D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2912 0x4102D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2913 0x4102D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2914 0x4102D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2915 0x4102D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2916 0x4102D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2917 0x4102D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2918 0x4102D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2919 0x4102D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2920 0x4102DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2921 0x4102DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2922 0x4102DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2923 0x4102DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2924 0x4102DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2925 0x4102DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2926 0x4102DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2927 0x4102DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2928 0x4102DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2929 0x4102DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2930 0x4102DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2931 0x4102DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2932 0x4102DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2933 0x4102DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2934 0x4102DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2935 0x4102DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2936 0x4102DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2937 0x4102DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2938 0x4102DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2939 0x4102DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2940 0x4102DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2941 0x4102DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2942 0x4102DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2943 0x4102DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2944 0x4102E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2945 0x4102E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2946 0x4102E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2947 0x4102E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2948 0x4102E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2949 0x4102E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2950 0x4102E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2951 0x4102E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2952 0x4102E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2953 0x4102E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2954 0x4102E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2955 0x4102E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2956 0x4102E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2957 0x4102E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2958 0x4102E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2959 0x4102E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2960 0x4102E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2961 0x4102E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2962 0x4102E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2963 0x4102E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2964 0x4102E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2965 0x4102E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2966 0x4102E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2967 0x4102E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2968 0x4102E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2969 0x4102E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2970 0x4102E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2971 0x4102E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2972 0x4102E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2973 0x4102E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2974 0x4102E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2975 0x4102E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2976 0x4102E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2977 0x4102E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2978 0x4102E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2979 0x4102E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2980 0x4102E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2981 0x4102E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2982 0x4102E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2983 0x4102E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2984 0x4102EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2985 0x4102EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2986 0x4102EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2987 0x4102EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2988 0x4102EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2989 0x4102EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2990 0x4102EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2991 0x4102EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2992 0x4102EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2993 0x4102EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2994 0x4102EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2995 0x4102ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2996 0x4102ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2997 0x4102ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2998 0x4102ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2999 0x4102EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3000 0x4102EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3001 0x4102EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3002 0x4102EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3003 0x4102EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3004 0x4102EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3005 0x4102EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3006 0x4102EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3007 0x4102EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3008 0x4102F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3009 0x4102F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3010 0x4102F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3011 0x4102F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3012 0x4102F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3013 0x4102F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3014 0x4102F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3015 0x4102F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3016 0x4102F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3017 0x4102F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3018 0x4102F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3019 0x4102F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3020 0x4102F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3021 0x4102F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3022 0x4102F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3023 0x4102F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3024 0x4102F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3025 0x4102F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3026 0x4102F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3027 0x4102F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3028 0x4102F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3029 0x4102F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3030 0x4102F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3031 0x4102F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3032 0x4102F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3033 0x4102F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3034 0x4102F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3035 0x4102F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3036 0x4102F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3037 0x4102F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3038 0x4102F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3039 0x4102F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3040 0x4102F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3041 0x4102F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3042 0x4102F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3043 0x4102F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3044 0x4102F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3045 0x4102F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3046 0x4102F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3047 0x4102F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3048 0x4102FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3049 0x4102FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3050 0x4102FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3051 0x4102FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3052 0x4102FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3053 0x4102FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3054 0x4102FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3055 0x4102FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3056 0x4102FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3057 0x4102FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3058 0x4102FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3059 0x4102FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3060 0x4102FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3061 0x4102FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3062 0x4102FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3063 0x4102FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3064 0x4102FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3065 0x4102FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3066 0x4102FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3067 0x4102FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3068 0x4102FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3069 0x4102FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3070 0x4102FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3071 0x4102FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3072 0x4103000 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3073 0x4103004 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3074 0x4103008 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3075 0x410300C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3076 0x4103010 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3077 0x4103014 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3078 0x4103018 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3079 0x410301C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3080 0x4103020 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3081 0x4103024 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3082 0x4103028 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3083 0x410302C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3084 0x4103030 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3085 0x4103034 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3086 0x4103038 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3087 0x410303C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3088 0x4103040 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3089 0x4103044 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3090 0x4103048 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3091 0x410304C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3092 0x4103050 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3093 0x4103054 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3094 0x4103058 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3095 0x410305C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3096 0x4103060 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3097 0x4103064 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3098 0x4103068 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3099 0x410306C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3100 0x4103070 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3101 0x4103074 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3102 0x4103078 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3103 0x410307C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3104 0x4103080 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3105 0x4103084 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3106 0x4103088 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3107 0x410308C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3108 0x4103090 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3109 0x4103094 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3110 0x4103098 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3111 0x410309C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3112 0x41030A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3113 0x41030A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3114 0x41030A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3115 0x41030AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3116 0x41030B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3117 0x41030B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3118 0x41030B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3119 0x41030BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3120 0x41030C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3121 0x41030C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3122 0x41030C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3123 0x41030CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3124 0x41030D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3125 0x41030D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3126 0x41030D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3127 0x41030DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3128 0x41030E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3129 0x41030E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3130 0x41030E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3131 0x41030EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3132 0x41030F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3133 0x41030F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3134 0x41030F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3135 0x41030FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3136 0x4103100 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3137 0x4103104 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3138 0x4103108 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3139 0x410310C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3140 0x4103110 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3141 0x4103114 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3142 0x4103118 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3143 0x410311C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3144 0x4103120 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3145 0x4103124 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3146 0x4103128 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3147 0x410312C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3148 0x4103130 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3149 0x4103134 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3150 0x4103138 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3151 0x410313C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3152 0x4103140 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3153 0x4103144 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3154 0x4103148 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3155 0x410314C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3156 0x4103150 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3157 0x4103154 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3158 0x4103158 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3159 0x410315C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3160 0x4103160 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3161 0x4103164 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3162 0x4103168 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3163 0x410316C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3164 0x4103170 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3165 0x4103174 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3166 0x4103178 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3167 0x410317C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3168 0x4103180 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3169 0x4103184 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3170 0x4103188 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3171 0x410318C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3172 0x4103190 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3173 0x4103194 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3174 0x4103198 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3175 0x410319C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3176 0x41031A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3177 0x41031A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3178 0x41031A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3179 0x41031AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3180 0x41031B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3181 0x41031B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3182 0x41031B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3183 0x41031BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3184 0x41031C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3185 0x41031C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3186 0x41031C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3187 0x41031CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3188 0x41031D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3189 0x41031D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3190 0x41031D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3191 0x41031DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3192 0x41031E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3193 0x41031E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3194 0x41031E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3195 0x41031EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3196 0x41031F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3197 0x41031F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3198 0x41031F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3199 0x41031FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3200 0x4103200 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3201 0x4103204 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3202 0x4103208 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3203 0x410320C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3204 0x4103210 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3205 0x4103214 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3206 0x4103218 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3207 0x410321C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3208 0x4103220 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3209 0x4103224 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3210 0x4103228 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3211 0x410322C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3212 0x4103230 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3213 0x4103234 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3214 0x4103238 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3215 0x410323C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3216 0x4103240 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3217 0x4103244 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3218 0x4103248 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3219 0x410324C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3220 0x4103250 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3221 0x4103254 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3222 0x4103258 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3223 0x410325C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3224 0x4103260 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3225 0x4103264 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3226 0x4103268 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3227 0x410326C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3228 0x4103270 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3229 0x4103274 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3230 0x4103278 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3231 0x410327C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3232 0x4103280 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3233 0x4103284 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3234 0x4103288 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3235 0x410328C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3236 0x4103290 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3237 0x4103294 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3238 0x4103298 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3239 0x410329C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3240 0x41032A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3241 0x41032A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3242 0x41032A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3243 0x41032AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3244 0x41032B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3245 0x41032B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3246 0x41032B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3247 0x41032BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3248 0x41032C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3249 0x41032C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3250 0x41032C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3251 0x41032CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3252 0x41032D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3253 0x41032D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3254 0x41032D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3255 0x41032DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3256 0x41032E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3257 0x41032E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3258 0x41032E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3259 0x41032EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3260 0x41032F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3261 0x41032F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3262 0x41032F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3263 0x41032FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3264 0x4103300 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3265 0x4103304 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3266 0x4103308 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3267 0x410330C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3268 0x4103310 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3269 0x4103314 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3270 0x4103318 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3271 0x410331C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3272 0x4103320 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3273 0x4103324 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3274 0x4103328 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3275 0x410332C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3276 0x4103330 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3277 0x4103334 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3278 0x4103338 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3279 0x410333C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3280 0x4103340 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3281 0x4103344 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3282 0x4103348 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3283 0x410334C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3284 0x4103350 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3285 0x4103354 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3286 0x4103358 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3287 0x410335C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3288 0x4103360 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3289 0x4103364 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3290 0x4103368 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3291 0x410336C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3292 0x4103370 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3293 0x4103374 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3294 0x4103378 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3295 0x410337C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3296 0x4103380 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3297 0x4103384 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3298 0x4103388 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3299 0x410338C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3300 0x4103390 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3301 0x4103394 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3302 0x4103398 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3303 0x410339C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3304 0x41033A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3305 0x41033A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3306 0x41033A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3307 0x41033AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3308 0x41033B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3309 0x41033B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3310 0x41033B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3311 0x41033BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3312 0x41033C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3313 0x41033C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3314 0x41033C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3315 0x41033CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3316 0x41033D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3317 0x41033D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3318 0x41033D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3319 0x41033DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3320 0x41033E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3321 0x41033E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3322 0x41033E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3323 0x41033EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3324 0x41033F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3325 0x41033F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3326 0x41033F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3327 0x41033FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3328 0x4103400 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3329 0x4103404 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3330 0x4103408 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3331 0x410340C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3332 0x4103410 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3333 0x4103414 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3334 0x4103418 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3335 0x410341C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3336 0x4103420 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3337 0x4103424 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3338 0x4103428 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3339 0x410342C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3340 0x4103430 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3341 0x4103434 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3342 0x4103438 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3343 0x410343C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3344 0x4103440 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3345 0x4103444 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3346 0x4103448 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3347 0x410344C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3348 0x4103450 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3349 0x4103454 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3350 0x4103458 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3351 0x410345C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3352 0x4103460 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3353 0x4103464 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3354 0x4103468 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3355 0x410346C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3356 0x4103470 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3357 0x4103474 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3358 0x4103478 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3359 0x410347C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3360 0x4103480 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3361 0x4103484 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3362 0x4103488 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3363 0x410348C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3364 0x4103490 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3365 0x4103494 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3366 0x4103498 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3367 0x410349C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3368 0x41034A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3369 0x41034A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3370 0x41034A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3371 0x41034AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3372 0x41034B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3373 0x41034B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3374 0x41034B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3375 0x41034BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3376 0x41034C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3377 0x41034C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3378 0x41034C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3379 0x41034CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3380 0x41034D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3381 0x41034D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3382 0x41034D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3383 0x41034DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3384 0x41034E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3385 0x41034E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3386 0x41034E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3387 0x41034EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3388 0x41034F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3389 0x41034F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3390 0x41034F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3391 0x41034FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3392 0x4103500 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3393 0x4103504 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3394 0x4103508 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3395 0x410350C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3396 0x4103510 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3397 0x4103514 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3398 0x4103518 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3399 0x410351C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3400 0x4103520 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3401 0x4103524 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3402 0x4103528 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3403 0x410352C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3404 0x4103530 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3405 0x4103534 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3406 0x4103538 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3407 0x410353C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3408 0x4103540 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3409 0x4103544 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3410 0x4103548 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3411 0x410354C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3412 0x4103550 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3413 0x4103554 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3414 0x4103558 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3415 0x410355C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3416 0x4103560 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3417 0x4103564 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3418 0x4103568 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3419 0x410356C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3420 0x4103570 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3421 0x4103574 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3422 0x4103578 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3423 0x410357C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3424 0x4103580 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3425 0x4103584 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3426 0x4103588 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3427 0x410358C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3428 0x4103590 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3429 0x4103594 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3430 0x4103598 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3431 0x410359C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3432 0x41035A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3433 0x41035A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3434 0x41035A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3435 0x41035AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3436 0x41035B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3437 0x41035B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3438 0x41035B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3439 0x41035BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3440 0x41035C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3441 0x41035C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3442 0x41035C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3443 0x41035CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3444 0x41035D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3445 0x41035D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3446 0x41035D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3447 0x41035DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3448 0x41035E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3449 0x41035E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3450 0x41035E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3451 0x41035EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3452 0x41035F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3453 0x41035F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3454 0x41035F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3455 0x41035FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3456 0x4103600 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3457 0x4103604 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3458 0x4103608 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3459 0x410360C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3460 0x4103610 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3461 0x4103614 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3462 0x4103618 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3463 0x410361C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3464 0x4103620 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3465 0x4103624 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3466 0x4103628 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3467 0x410362C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3468 0x4103630 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3469 0x4103634 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3470 0x4103638 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3471 0x410363C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3472 0x4103640 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3473 0x4103644 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3474 0x4103648 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3475 0x410364C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3476 0x4103650 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3477 0x4103654 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3478 0x4103658 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3479 0x410365C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3480 0x4103660 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3481 0x4103664 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3482 0x4103668 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3483 0x410366C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3484 0x4103670 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3485 0x4103674 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3486 0x4103678 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3487 0x410367C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3488 0x4103680 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3489 0x4103684 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3490 0x4103688 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3491 0x410368C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3492 0x4103690 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3493 0x4103694 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3494 0x4103698 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3495 0x410369C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3496 0x41036A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3497 0x41036A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3498 0x41036A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3499 0x41036AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3500 0x41036B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3501 0x41036B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3502 0x41036B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3503 0x41036BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3504 0x41036C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3505 0x41036C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3506 0x41036C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3507 0x41036CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3508 0x41036D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3509 0x41036D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3510 0x41036D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3511 0x41036DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3512 0x41036E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3513 0x41036E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3514 0x41036E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3515 0x41036EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3516 0x41036F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3517 0x41036F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3518 0x41036F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3519 0x41036FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3520 0x4103700 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3521 0x4103704 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3522 0x4103708 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3523 0x410370C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3524 0x4103710 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3525 0x4103714 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3526 0x4103718 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3527 0x410371C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3528 0x4103720 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3529 0x4103724 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3530 0x4103728 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3531 0x410372C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3532 0x4103730 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3533 0x4103734 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3534 0x4103738 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3535 0x410373C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3536 0x4103740 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3537 0x4103744 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3538 0x4103748 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3539 0x410374C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3540 0x4103750 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3541 0x4103754 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3542 0x4103758 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3543 0x410375C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3544 0x4103760 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3545 0x4103764 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3546 0x4103768 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3547 0x410376C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3548 0x4103770 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3549 0x4103774 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3550 0x4103778 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3551 0x410377C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3552 0x4103780 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3553 0x4103784 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3554 0x4103788 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3555 0x410378C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3556 0x4103790 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3557 0x4103794 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3558 0x4103798 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3559 0x410379C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3560 0x41037A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3561 0x41037A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3562 0x41037A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3563 0x41037AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3564 0x41037B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3565 0x41037B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3566 0x41037B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3567 0x41037BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3568 0x41037C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3569 0x41037C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3570 0x41037C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3571 0x41037CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3572 0x41037D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3573 0x41037D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3574 0x41037D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3575 0x41037DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3576 0x41037E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3577 0x41037E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3578 0x41037E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3579 0x41037EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3580 0x41037F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3581 0x41037F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3582 0x41037F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3583 0x41037FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3584 0x4103800 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3585 0x4103804 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3586 0x4103808 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3587 0x410380C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3588 0x4103810 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3589 0x4103814 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3590 0x4103818 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3591 0x410381C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3592 0x4103820 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3593 0x4103824 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3594 0x4103828 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3595 0x410382C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3596 0x4103830 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3597 0x4103834 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3598 0x4103838 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3599 0x410383C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3600 0x4103840 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3601 0x4103844 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3602 0x4103848 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3603 0x410384C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3604 0x4103850 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3605 0x4103854 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3606 0x4103858 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3607 0x410385C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3608 0x4103860 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3609 0x4103864 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3610 0x4103868 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3611 0x410386C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3612 0x4103870 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3613 0x4103874 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3614 0x4103878 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3615 0x410387C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3616 0x4103880 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3617 0x4103884 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3618 0x4103888 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3619 0x410388C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3620 0x4103890 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3621 0x4103894 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3622 0x4103898 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3623 0x410389C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3624 0x41038A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3625 0x41038A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3626 0x41038A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3627 0x41038AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3628 0x41038B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3629 0x41038B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3630 0x41038B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3631 0x41038BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3632 0x41038C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3633 0x41038C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3634 0x41038C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3635 0x41038CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3636 0x41038D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3637 0x41038D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3638 0x41038D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3639 0x41038DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3640 0x41038E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3641 0x41038E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3642 0x41038E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3643 0x41038EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3644 0x41038F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3645 0x41038F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3646 0x41038F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3647 0x41038FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3648 0x4103900 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3649 0x4103904 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3650 0x4103908 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3651 0x410390C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3652 0x4103910 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3653 0x4103914 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3654 0x4103918 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3655 0x410391C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3656 0x4103920 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3657 0x4103924 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3658 0x4103928 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3659 0x410392C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3660 0x4103930 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3661 0x4103934 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3662 0x4103938 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3663 0x410393C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3664 0x4103940 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3665 0x4103944 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3666 0x4103948 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3667 0x410394C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3668 0x4103950 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3669 0x4103954 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3670 0x4103958 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3671 0x410395C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3672 0x4103960 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3673 0x4103964 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3674 0x4103968 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3675 0x410396C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3676 0x4103970 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3677 0x4103974 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3678 0x4103978 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3679 0x410397C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3680 0x4103980 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3681 0x4103984 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3682 0x4103988 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3683 0x410398C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3684 0x4103990 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3685 0x4103994 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3686 0x4103998 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3687 0x410399C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3688 0x41039A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3689 0x41039A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3690 0x41039A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3691 0x41039AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3692 0x41039B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3693 0x41039B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3694 0x41039B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3695 0x41039BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3696 0x41039C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3697 0x41039C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3698 0x41039C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3699 0x41039CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3700 0x41039D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3701 0x41039D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3702 0x41039D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3703 0x41039DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3704 0x41039E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3705 0x41039E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3706 0x41039E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3707 0x41039EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3708 0x41039F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3709 0x41039F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3710 0x41039F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3711 0x41039FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3712 0x4103A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3713 0x4103A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3714 0x4103A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3715 0x4103A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3716 0x4103A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3717 0x4103A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3718 0x4103A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3719 0x4103A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3720 0x4103A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3721 0x4103A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3722 0x4103A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3723 0x4103A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3724 0x4103A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3725 0x4103A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3726 0x4103A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3727 0x4103A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3728 0x4103A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3729 0x4103A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3730 0x4103A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3731 0x4103A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3732 0x4103A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3733 0x4103A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3734 0x4103A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3735 0x4103A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3736 0x4103A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3737 0x4103A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3738 0x4103A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3739 0x4103A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3740 0x4103A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3741 0x4103A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3742 0x4103A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3743 0x4103A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3744 0x4103A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3745 0x4103A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3746 0x4103A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3747 0x4103A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3748 0x4103A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3749 0x4103A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3750 0x4103A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3751 0x4103A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3752 0x4103AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3753 0x4103AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3754 0x4103AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3755 0x4103AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3756 0x4103AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3757 0x4103AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3758 0x4103AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3759 0x4103ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3760 0x4103AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3761 0x4103AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3762 0x4103AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3763 0x4103ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3764 0x4103AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3765 0x4103AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3766 0x4103AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3767 0x4103ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3768 0x4103AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3769 0x4103AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3770 0x4103AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3771 0x4103AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3772 0x4103AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3773 0x4103AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3774 0x4103AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3775 0x4103AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3776 0x4103B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3777 0x4103B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3778 0x4103B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3779 0x4103B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3780 0x4103B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3781 0x4103B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3782 0x4103B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3783 0x4103B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3784 0x4103B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3785 0x4103B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3786 0x4103B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3787 0x4103B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3788 0x4103B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3789 0x4103B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3790 0x4103B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3791 0x4103B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3792 0x4103B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3793 0x4103B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3794 0x4103B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3795 0x4103B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3796 0x4103B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3797 0x4103B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3798 0x4103B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3799 0x4103B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3800 0x4103B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3801 0x4103B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3802 0x4103B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3803 0x4103B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3804 0x4103B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3805 0x4103B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3806 0x4103B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3807 0x4103B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3808 0x4103B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3809 0x4103B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3810 0x4103B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3811 0x4103B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3812 0x4103B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3813 0x4103B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3814 0x4103B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3815 0x4103B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3816 0x4103BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3817 0x4103BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3818 0x4103BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3819 0x4103BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3820 0x4103BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3821 0x4103BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3822 0x4103BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3823 0x4103BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3824 0x4103BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3825 0x4103BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3826 0x4103BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3827 0x4103BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3828 0x4103BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3829 0x4103BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3830 0x4103BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3831 0x4103BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3832 0x4103BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3833 0x4103BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3834 0x4103BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3835 0x4103BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3836 0x4103BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3837 0x4103BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3838 0x4103BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3839 0x4103BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3840 0x4103C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3841 0x4103C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3842 0x4103C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3843 0x4103C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3844 0x4103C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3845 0x4103C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3846 0x4103C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3847 0x4103C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3848 0x4103C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3849 0x4103C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3850 0x4103C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3851 0x4103C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3852 0x4103C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3853 0x4103C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3854 0x4103C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3855 0x4103C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3856 0x4103C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3857 0x4103C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3858 0x4103C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3859 0x4103C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3860 0x4103C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3861 0x4103C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3862 0x4103C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3863 0x4103C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3864 0x4103C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3865 0x4103C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3866 0x4103C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3867 0x4103C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3868 0x4103C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3869 0x4103C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3870 0x4103C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3871 0x4103C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3872 0x4103C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3873 0x4103C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3874 0x4103C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3875 0x4103C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3876 0x4103C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3877 0x4103C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3878 0x4103C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3879 0x4103C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3880 0x4103CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3881 0x4103CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3882 0x4103CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3883 0x4103CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3884 0x4103CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3885 0x4103CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3886 0x4103CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3887 0x4103CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3888 0x4103CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3889 0x4103CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3890 0x4103CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3891 0x4103CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3892 0x4103CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3893 0x4103CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3894 0x4103CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3895 0x4103CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3896 0x4103CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3897 0x4103CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3898 0x4103CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3899 0x4103CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3900 0x4103CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3901 0x4103CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3902 0x4103CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3903 0x4103CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3904 0x4103D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3905 0x4103D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3906 0x4103D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3907 0x4103D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3908 0x4103D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3909 0x4103D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3910 0x4103D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3911 0x4103D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3912 0x4103D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3913 0x4103D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3914 0x4103D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3915 0x4103D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3916 0x4103D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3917 0x4103D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3918 0x4103D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3919 0x4103D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3920 0x4103D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3921 0x4103D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3922 0x4103D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3923 0x4103D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3924 0x4103D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3925 0x4103D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3926 0x4103D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3927 0x4103D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3928 0x4103D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3929 0x4103D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3930 0x4103D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3931 0x4103D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3932 0x4103D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3933 0x4103D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3934 0x4103D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3935 0x4103D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3936 0x4103D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3937 0x4103D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3938 0x4103D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3939 0x4103D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3940 0x4103D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3941 0x4103D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3942 0x4103D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3943 0x4103D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3944 0x4103DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3945 0x4103DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3946 0x4103DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3947 0x4103DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3948 0x4103DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3949 0x4103DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3950 0x4103DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3951 0x4103DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3952 0x4103DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3953 0x4103DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3954 0x4103DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3955 0x4103DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3956 0x4103DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3957 0x4103DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3958 0x4103DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3959 0x4103DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3960 0x4103DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3961 0x4103DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3962 0x4103DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3963 0x4103DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3964 0x4103DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3965 0x4103DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3966 0x4103DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3967 0x4103DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3968 0x4103E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3969 0x4103E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3970 0x4103E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3971 0x4103E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3972 0x4103E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3973 0x4103E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3974 0x4103E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3975 0x4103E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3976 0x4103E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3977 0x4103E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3978 0x4103E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3979 0x4103E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3980 0x4103E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3981 0x4103E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3982 0x4103E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3983 0x4103E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3984 0x4103E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3985 0x4103E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3986 0x4103E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3987 0x4103E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3988 0x4103E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3989 0x4103E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3990 0x4103E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3991 0x4103E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3992 0x4103E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3993 0x4103E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3994 0x4103E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3995 0x4103E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3996 0x4103E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3997 0x4103E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3998 0x4103E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3999 0x4103E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4000 0x4103E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4001 0x4103E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4002 0x4103E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4003 0x4103E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4004 0x4103E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4005 0x4103E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4006 0x4103E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4007 0x4103E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4008 0x4103EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4009 0x4103EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4010 0x4103EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4011 0x4103EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4012 0x4103EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4013 0x4103EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4014 0x4103EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4015 0x4103EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4016 0x4103EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4017 0x4103EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4018 0x4103EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4019 0x4103ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4020 0x4103ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4021 0x4103ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4022 0x4103ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4023 0x4103EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4024 0x4103EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4025 0x4103EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4026 0x4103EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4027 0x4103EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4028 0x4103EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4029 0x4103EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4030 0x4103EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4031 0x4103EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4032 0x4103F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4033 0x4103F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4034 0x4103F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4035 0x4103F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4036 0x4103F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4037 0x4103F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4038 0x4103F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4039 0x4103F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4040 0x4103F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4041 0x4103F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4042 0x4103F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4043 0x4103F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4044 0x4103F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4045 0x4103F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4046 0x4103F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4047 0x4103F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4048 0x4103F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4049 0x4103F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4050 0x4103F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4051 0x4103F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4052 0x4103F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4053 0x4103F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4054 0x4103F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4055 0x4103F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4056 0x4103F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4057 0x4103F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4058 0x4103F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4059 0x4103F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4060 0x4103F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4061 0x4103F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4062 0x4103F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4063 0x4103F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4064 0x4103F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4065 0x4103F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4066 0x4103F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4067 0x4103F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4068 0x4103F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4069 0x4103F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4070 0x4103F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4071 0x4103F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4072 0x4103FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4073 0x4103FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4074 0x4103FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4075 0x4103FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4076 0x4103FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4077 0x4103FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4078 0x4103FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4079 0x4103FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4080 0x4103FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4081 0x4103FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4082 0x4103FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4083 0x4103FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4084 0x4103FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4085 0x4103FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4086 0x4103FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4087 0x4103FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4088 0x4103FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4089 0x4103FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4090 0x4103FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4091 0x4103FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4092 0x4103FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4093 0x4103FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4094 0x4103FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4095 0x4103FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4096 0x4104000 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4097 0x4104004 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4098 0x4104008 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4099 0x410400C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4100 0x4104010 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4101 0x4104014 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4102 0x4104018 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4103 0x410401C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4104 0x4104020 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4105 0x4104024 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4106 0x4104028 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4107 0x410402C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4108 0x4104030 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4109 0x4104034 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4110 0x4104038 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4111 0x410403C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4112 0x4104040 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4113 0x4104044 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4114 0x4104048 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4115 0x410404C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4116 0x4104050 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4117 0x4104054 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4118 0x4104058 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4119 0x410405C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4120 0x4104060 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4121 0x4104064 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4122 0x4104068 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4123 0x410406C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4124 0x4104070 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4125 0x4104074 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4126 0x4104078 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4127 0x410407C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4128 0x4104080 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4129 0x4104084 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4130 0x4104088 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4131 0x410408C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4132 0x4104090 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4133 0x4104094 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4134 0x4104098 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4135 0x410409C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4136 0x41040A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4137 0x41040A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4138 0x41040A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4139 0x41040AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4140 0x41040B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4141 0x41040B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4142 0x41040B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4143 0x41040BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4144 0x41040C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4145 0x41040C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4146 0x41040C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4147 0x41040CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4148 0x41040D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4149 0x41040D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4150 0x41040D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4151 0x41040DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4152 0x41040E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4153 0x41040E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4154 0x41040E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4155 0x41040EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4156 0x41040F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4157 0x41040F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4158 0x41040F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4159 0x41040FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4160 0x4104100 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4161 0x4104104 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4162 0x4104108 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4163 0x410410C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4164 0x4104110 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4165 0x4104114 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4166 0x4104118 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4167 0x410411C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4168 0x4104120 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4169 0x4104124 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4170 0x4104128 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4171 0x410412C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4172 0x4104130 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4173 0x4104134 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4174 0x4104138 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4175 0x410413C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4176 0x4104140 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4177 0x4104144 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4178 0x4104148 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4179 0x410414C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4180 0x4104150 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4181 0x4104154 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4182 0x4104158 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4183 0x410415C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4184 0x4104160 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4185 0x4104164 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4186 0x4104168 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4187 0x410416C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4188 0x4104170 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4189 0x4104174 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4190 0x4104178 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4191 0x410417C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4192 0x4104180 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4193 0x4104184 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4194 0x4104188 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4195 0x410418C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4196 0x4104190 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4197 0x4104194 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4198 0x4104198 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4199 0x410419C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4200 0x41041A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4201 0x41041A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4202 0x41041A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4203 0x41041AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4204 0x41041B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4205 0x41041B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4206 0x41041B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4207 0x41041BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4208 0x41041C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4209 0x41041C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4210 0x41041C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4211 0x41041CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4212 0x41041D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4213 0x41041D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4214 0x41041D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4215 0x41041DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4216 0x41041E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4217 0x41041E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4218 0x41041E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4219 0x41041EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4220 0x41041F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4221 0x41041F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4222 0x41041F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4223 0x41041FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4224 0x4104200 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4225 0x4104204 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4226 0x4104208 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4227 0x410420C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4228 0x4104210 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4229 0x4104214 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4230 0x4104218 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4231 0x410421C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4232 0x4104220 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4233 0x4104224 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4234 0x4104228 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4235 0x410422C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4236 0x4104230 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4237 0x4104234 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4238 0x4104238 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4239 0x410423C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4240 0x4104240 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4241 0x4104244 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4242 0x4104248 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4243 0x410424C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4244 0x4104250 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4245 0x4104254 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4246 0x4104258 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4247 0x410425C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4248 0x4104260 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4249 0x4104264 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4250 0x4104268 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4251 0x410426C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4252 0x4104270 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4253 0x4104274 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4254 0x4104278 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4255 0x410427C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4256 0x4104280 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4257 0x4104284 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4258 0x4104288 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4259 0x410428C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4260 0x4104290 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4261 0x4104294 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4262 0x4104298 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4263 0x410429C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4264 0x41042A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4265 0x41042A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4266 0x41042A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4267 0x41042AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4268 0x41042B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4269 0x41042B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4270 0x41042B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4271 0x41042BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4272 0x41042C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4273 0x41042C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4274 0x41042C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4275 0x41042CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4276 0x41042D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4277 0x41042D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4278 0x41042D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4279 0x41042DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4280 0x41042E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4281 0x41042E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4282 0x41042E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4283 0x41042EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4284 0x41042F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4285 0x41042F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4286 0x41042F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4287 0x41042FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4288 0x4104300 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4289 0x4104304 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4290 0x4104308 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4291 0x410430C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4292 0x4104310 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4293 0x4104314 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4294 0x4104318 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4295 0x410431C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4296 0x4104320 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4297 0x4104324 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4298 0x4104328 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4299 0x410432C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4300 0x4104330 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4301 0x4104334 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4302 0x4104338 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4303 0x410433C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4304 0x4104340 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4305 0x4104344 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4306 0x4104348 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4307 0x410434C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4308 0x4104350 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4309 0x4104354 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4310 0x4104358 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4311 0x410435C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4312 0x4104360 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4313 0x4104364 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4314 0x4104368 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4315 0x410436C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4316 0x4104370 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4317 0x4104374 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4318 0x4104378 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4319 0x410437C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4320 0x4104380 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4321 0x4104384 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4322 0x4104388 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4323 0x410438C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4324 0x4104390 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4325 0x4104394 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4326 0x4104398 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4327 0x410439C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4328 0x41043A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4329 0x41043A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4330 0x41043A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4331 0x41043AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4332 0x41043B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4333 0x41043B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4334 0x41043B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4335 0x41043BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4336 0x41043C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4337 0x41043C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4338 0x41043C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4339 0x41043CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4340 0x41043D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4341 0x41043D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4342 0x41043D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4343 0x41043DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4344 0x41043E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4345 0x41043E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4346 0x41043E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4347 0x41043EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4348 0x41043F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4349 0x41043F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4350 0x41043F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4351 0x41043FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4352 0x4104400 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4353 0x4104404 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4354 0x4104408 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4355 0x410440C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4356 0x4104410 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4357 0x4104414 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4358 0x4104418 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4359 0x410441C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4360 0x4104420 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4361 0x4104424 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4362 0x4104428 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4363 0x410442C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4364 0x4104430 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4365 0x4104434 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4366 0x4104438 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4367 0x410443C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4368 0x4104440 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4369 0x4104444 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4370 0x4104448 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4371 0x410444C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4372 0x4104450 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4373 0x4104454 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4374 0x4104458 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4375 0x410445C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4376 0x4104460 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4377 0x4104464 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4378 0x4104468 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4379 0x410446C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4380 0x4104470 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4381 0x4104474 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4382 0x4104478 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4383 0x410447C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4384 0x4104480 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4385 0x4104484 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4386 0x4104488 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4387 0x410448C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4388 0x4104490 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4389 0x4104494 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4390 0x4104498 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4391 0x410449C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4392 0x41044A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4393 0x41044A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4394 0x41044A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4395 0x41044AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4396 0x41044B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4397 0x41044B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4398 0x41044B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4399 0x41044BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4400 0x41044C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4401 0x41044C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4402 0x41044C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4403 0x41044CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4404 0x41044D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4405 0x41044D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4406 0x41044D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4407 0x41044DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4408 0x41044E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4409 0x41044E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4410 0x41044E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4411 0x41044EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4412 0x41044F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4413 0x41044F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4414 0x41044F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4415 0x41044FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4416 0x4104500 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4417 0x4104504 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4418 0x4104508 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4419 0x410450C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4420 0x4104510 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4421 0x4104514 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4422 0x4104518 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4423 0x410451C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4424 0x4104520 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4425 0x4104524 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4426 0x4104528 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4427 0x410452C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4428 0x4104530 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4429 0x4104534 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4430 0x4104538 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4431 0x410453C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4432 0x4104540 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4433 0x4104544 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4434 0x4104548 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4435 0x410454C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4436 0x4104550 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4437 0x4104554 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4438 0x4104558 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4439 0x410455C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4440 0x4104560 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4441 0x4104564 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4442 0x4104568 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4443 0x410456C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4444 0x4104570 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4445 0x4104574 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4446 0x4104578 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4447 0x410457C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4448 0x4104580 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4449 0x4104584 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4450 0x4104588 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4451 0x410458C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4452 0x4104590 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4453 0x4104594 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4454 0x4104598 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4455 0x410459C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4456 0x41045A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4457 0x41045A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4458 0x41045A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4459 0x41045AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4460 0x41045B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4461 0x41045B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4462 0x41045B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4463 0x41045BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4464 0x41045C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4465 0x41045C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4466 0x41045C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4467 0x41045CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4468 0x41045D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4469 0x41045D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4470 0x41045D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4471 0x41045DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4472 0x41045E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4473 0x41045E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4474 0x41045E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4475 0x41045EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4476 0x41045F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4477 0x41045F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4478 0x41045F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4479 0x41045FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4480 0x4104600 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4481 0x4104604 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4482 0x4104608 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4483 0x410460C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4484 0x4104610 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4485 0x4104614 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4486 0x4104618 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4487 0x410461C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4488 0x4104620 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4489 0x4104624 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4490 0x4104628 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4491 0x410462C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4492 0x4104630 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4493 0x4104634 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4494 0x4104638 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4495 0x410463C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4496 0x4104640 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4497 0x4104644 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4498 0x4104648 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4499 0x410464C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4500 0x4104650 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4501 0x4104654 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4502 0x4104658 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4503 0x410465C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4504 0x4104660 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4505 0x4104664 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4506 0x4104668 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4507 0x410466C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4508 0x4104670 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4509 0x4104674 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4510 0x4104678 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4511 0x410467C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4512 0x4104680 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4513 0x4104684 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4514 0x4104688 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4515 0x410468C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4516 0x4104690 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4517 0x4104694 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4518 0x4104698 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4519 0x410469C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4520 0x41046A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4521 0x41046A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4522 0x41046A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4523 0x41046AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4524 0x41046B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4525 0x41046B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4526 0x41046B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4527 0x41046BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4528 0x41046C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4529 0x41046C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4530 0x41046C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4531 0x41046CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4532 0x41046D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4533 0x41046D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4534 0x41046D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4535 0x41046DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4536 0x41046E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4537 0x41046E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4538 0x41046E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4539 0x41046EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4540 0x41046F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4541 0x41046F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4542 0x41046F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4543 0x41046FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4544 0x4104700 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4545 0x4104704 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4546 0x4104708 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4547 0x410470C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4548 0x4104710 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4549 0x4104714 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4550 0x4104718 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4551 0x410471C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4552 0x4104720 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4553 0x4104724 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4554 0x4104728 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4555 0x410472C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4556 0x4104730 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4557 0x4104734 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4558 0x4104738 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4559 0x410473C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4560 0x4104740 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4561 0x4104744 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4562 0x4104748 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4563 0x410474C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4564 0x4104750 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4565 0x4104754 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4566 0x4104758 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4567 0x410475C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4568 0x4104760 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4569 0x4104764 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4570 0x4104768 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4571 0x410476C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4572 0x4104770 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4573 0x4104774 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4574 0x4104778 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4575 0x410477C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4576 0x4104780 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4577 0x4104784 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4578 0x4104788 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4579 0x410478C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4580 0x4104790 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4581 0x4104794 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4582 0x4104798 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4583 0x410479C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4584 0x41047A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4585 0x41047A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4586 0x41047A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4587 0x41047AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4588 0x41047B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4589 0x41047B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4590 0x41047B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4591 0x41047BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4592 0x41047C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4593 0x41047C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4594 0x41047C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4595 0x41047CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4596 0x41047D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4597 0x41047D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4598 0x41047D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4599 0x41047DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4600 0x41047E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4601 0x41047E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4602 0x41047E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4603 0x41047EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4604 0x41047F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4605 0x41047F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4606 0x41047F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4607 0x41047FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4608 0x4104800 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4609 0x4104804 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4610 0x4104808 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4611 0x410480C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4612 0x4104810 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4613 0x4104814 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4614 0x4104818 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4615 0x410481C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4616 0x4104820 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4617 0x4104824 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4618 0x4104828 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4619 0x410482C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4620 0x4104830 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4621 0x4104834 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4622 0x4104838 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4623 0x410483C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4624 0x4104840 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4625 0x4104844 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4626 0x4104848 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4627 0x410484C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4628 0x4104850 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4629 0x4104854 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4630 0x4104858 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4631 0x410485C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4632 0x4104860 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4633 0x4104864 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4634 0x4104868 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4635 0x410486C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4636 0x4104870 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4637 0x4104874 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4638 0x4104878 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4639 0x410487C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4640 0x4104880 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4641 0x4104884 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4642 0x4104888 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4643 0x410488C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4644 0x4104890 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4645 0x4104894 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4646 0x4104898 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4647 0x410489C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4648 0x41048A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4649 0x41048A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4650 0x41048A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4651 0x41048AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4652 0x41048B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4653 0x41048B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4654 0x41048B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4655 0x41048BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4656 0x41048C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4657 0x41048C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4658 0x41048C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4659 0x41048CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4660 0x41048D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4661 0x41048D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4662 0x41048D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4663 0x41048DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4664 0x41048E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4665 0x41048E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4666 0x41048E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4667 0x41048EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4668 0x41048F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4669 0x41048F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4670 0x41048F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4671 0x41048FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4672 0x4104900 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4673 0x4104904 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4674 0x4104908 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4675 0x410490C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4676 0x4104910 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4677 0x4104914 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4678 0x4104918 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4679 0x410491C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4680 0x4104920 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4681 0x4104924 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4682 0x4104928 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4683 0x410492C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4684 0x4104930 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4685 0x4104934 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4686 0x4104938 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4687 0x410493C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4688 0x4104940 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4689 0x4104944 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4690 0x4104948 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4691 0x410494C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4692 0x4104950 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4693 0x4104954 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4694 0x4104958 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4695 0x410495C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4696 0x4104960 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4697 0x4104964 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4698 0x4104968 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4699 0x410496C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4700 0x4104970 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4701 0x4104974 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4702 0x4104978 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4703 0x410497C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4704 0x4104980 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4705 0x4104984 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4706 0x4104988 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4707 0x410498C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4708 0x4104990 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4709 0x4104994 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4710 0x4104998 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4711 0x410499C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4712 0x41049A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4713 0x41049A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4714 0x41049A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4715 0x41049AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4716 0x41049B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4717 0x41049B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4718 0x41049B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4719 0x41049BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4720 0x41049C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4721 0x41049C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4722 0x41049C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4723 0x41049CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4724 0x41049D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4725 0x41049D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4726 0x41049D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4727 0x41049DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4728 0x41049E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4729 0x41049E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4730 0x41049E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4731 0x41049EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4732 0x41049F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4733 0x41049F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4734 0x41049F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4735 0x41049FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4736 0x4104A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4737 0x4104A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4738 0x4104A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4739 0x4104A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4740 0x4104A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4741 0x4104A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4742 0x4104A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4743 0x4104A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4744 0x4104A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4745 0x4104A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4746 0x4104A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4747 0x4104A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4748 0x4104A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4749 0x4104A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4750 0x4104A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4751 0x4104A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4752 0x4104A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4753 0x4104A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4754 0x4104A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4755 0x4104A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4756 0x4104A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4757 0x4104A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4758 0x4104A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4759 0x4104A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4760 0x4104A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4761 0x4104A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4762 0x4104A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4763 0x4104A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4764 0x4104A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4765 0x4104A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4766 0x4104A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4767 0x4104A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4768 0x4104A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4769 0x4104A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4770 0x4104A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4771 0x4104A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4772 0x4104A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4773 0x4104A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4774 0x4104A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4775 0x4104A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4776 0x4104AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4777 0x4104AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4778 0x4104AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4779 0x4104AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4780 0x4104AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4781 0x4104AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4782 0x4104AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4783 0x4104ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4784 0x4104AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4785 0x4104AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4786 0x4104AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4787 0x4104ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4788 0x4104AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4789 0x4104AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4790 0x4104AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4791 0x4104ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4792 0x4104AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4793 0x4104AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4794 0x4104AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4795 0x4104AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4796 0x4104AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4797 0x4104AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4798 0x4104AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4799 0x4104AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4800 0x4104B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4801 0x4104B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4802 0x4104B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4803 0x4104B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4804 0x4104B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4805 0x4104B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4806 0x4104B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4807 0x4104B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4808 0x4104B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4809 0x4104B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4810 0x4104B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4811 0x4104B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4812 0x4104B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4813 0x4104B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4814 0x4104B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4815 0x4104B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4816 0x4104B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4817 0x4104B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4818 0x4104B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4819 0x4104B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4820 0x4104B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4821 0x4104B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4822 0x4104B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4823 0x4104B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4824 0x4104B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4825 0x4104B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4826 0x4104B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4827 0x4104B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4828 0x4104B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4829 0x4104B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4830 0x4104B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4831 0x4104B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4832 0x4104B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4833 0x4104B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4834 0x4104B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4835 0x4104B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4836 0x4104B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4837 0x4104B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4838 0x4104B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4839 0x4104B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4840 0x4104BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4841 0x4104BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4842 0x4104BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4843 0x4104BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4844 0x4104BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4845 0x4104BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4846 0x4104BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4847 0x4104BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4848 0x4104BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4849 0x4104BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4850 0x4104BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4851 0x4104BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4852 0x4104BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4853 0x4104BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4854 0x4104BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4855 0x4104BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4856 0x4104BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4857 0x4104BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4858 0x4104BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4859 0x4104BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4860 0x4104BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4861 0x4104BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4862 0x4104BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4863 0x4104BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4864 0x4104C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4865 0x4104C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4866 0x4104C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4867 0x4104C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4868 0x4104C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4869 0x4104C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4870 0x4104C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4871 0x4104C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4872 0x4104C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4873 0x4104C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4874 0x4104C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4875 0x4104C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4876 0x4104C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4877 0x4104C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4878 0x4104C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4879 0x4104C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4880 0x4104C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4881 0x4104C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4882 0x4104C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4883 0x4104C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4884 0x4104C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4885 0x4104C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4886 0x4104C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4887 0x4104C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4888 0x4104C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4889 0x4104C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4890 0x4104C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4891 0x4104C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4892 0x4104C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4893 0x4104C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4894 0x4104C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4895 0x4104C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4896 0x4104C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4897 0x4104C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4898 0x4104C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4899 0x4104C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4900 0x4104C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4901 0x4104C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4902 0x4104C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4903 0x4104C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4904 0x4104CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4905 0x4104CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4906 0x4104CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4907 0x4104CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4908 0x4104CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4909 0x4104CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4910 0x4104CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4911 0x4104CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4912 0x4104CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4913 0x4104CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4914 0x4104CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4915 0x4104CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4916 0x4104CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4917 0x4104CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4918 0x4104CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4919 0x4104CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4920 0x4104CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4921 0x4104CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4922 0x4104CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4923 0x4104CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4924 0x4104CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4925 0x4104CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4926 0x4104CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4927 0x4104CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4928 0x4104D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4929 0x4104D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4930 0x4104D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4931 0x4104D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4932 0x4104D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4933 0x4104D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4934 0x4104D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4935 0x4104D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4936 0x4104D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4937 0x4104D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4938 0x4104D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4939 0x4104D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4940 0x4104D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4941 0x4104D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4942 0x4104D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4943 0x4104D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4944 0x4104D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4945 0x4104D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4946 0x4104D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4947 0x4104D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4948 0x4104D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4949 0x4104D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4950 0x4104D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4951 0x4104D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4952 0x4104D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4953 0x4104D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4954 0x4104D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4955 0x4104D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4956 0x4104D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4957 0x4104D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4958 0x4104D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4959 0x4104D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4960 0x4104D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4961 0x4104D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4962 0x4104D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4963 0x4104D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4964 0x4104D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4965 0x4104D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4966 0x4104D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4967 0x4104D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4968 0x4104DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4969 0x4104DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4970 0x4104DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4971 0x4104DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4972 0x4104DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4973 0x4104DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4974 0x4104DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4975 0x4104DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4976 0x4104DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4977 0x4104DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4978 0x4104DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4979 0x4104DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4980 0x4104DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4981 0x4104DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4982 0x4104DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4983 0x4104DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4984 0x4104DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4985 0x4104DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4986 0x4104DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4987 0x4104DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4988 0x4104DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4989 0x4104DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4990 0x4104DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4991 0x4104DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4992 0x4104E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4993 0x4104E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4994 0x4104E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4995 0x4104E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4996 0x4104E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4997 0x4104E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4998 0x4104E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4999 0x4104E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5000 0x4104E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5001 0x4104E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5002 0x4104E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5003 0x4104E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5004 0x4104E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5005 0x4104E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5006 0x4104E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5007 0x4104E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5008 0x4104E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5009 0x4104E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5010 0x4104E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5011 0x4104E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5012 0x4104E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5013 0x4104E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5014 0x4104E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5015 0x4104E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5016 0x4104E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5017 0x4104E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5018 0x4104E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5019 0x4104E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5020 0x4104E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5021 0x4104E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5022 0x4104E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5023 0x4104E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5024 0x4104E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5025 0x4104E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5026 0x4104E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5027 0x4104E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5028 0x4104E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5029 0x4104E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5030 0x4104E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5031 0x4104E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5032 0x4104EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5033 0x4104EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5034 0x4104EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5035 0x4104EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5036 0x4104EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5037 0x4104EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5038 0x4104EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5039 0x4104EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5040 0x4104EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5041 0x4104EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5042 0x4104EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5043 0x4104ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5044 0x4104ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5045 0x4104ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5046 0x4104ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5047 0x4104EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5048 0x4104EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5049 0x4104EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5050 0x4104EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5051 0x4104EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5052 0x4104EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5053 0x4104EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5054 0x4104EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5055 0x4104EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5056 0x4104F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5057 0x4104F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5058 0x4104F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5059 0x4104F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5060 0x4104F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5061 0x4104F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5062 0x4104F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5063 0x4104F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5064 0x4104F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5065 0x4104F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5066 0x4104F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5067 0x4104F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5068 0x4104F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5069 0x4104F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5070 0x4104F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5071 0x4104F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5072 0x4104F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5073 0x4104F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5074 0x4104F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5075 0x4104F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5076 0x4104F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5077 0x4104F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5078 0x4104F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5079 0x4104F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5080 0x4104F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5081 0x4104F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5082 0x4104F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5083 0x4104F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5084 0x4104F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5085 0x4104F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5086 0x4104F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5087 0x4104F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5088 0x4104F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5089 0x4104F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5090 0x4104F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5091 0x4104F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5092 0x4104F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5093 0x4104F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5094 0x4104F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5095 0x4104F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5096 0x4104FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5097 0x4104FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5098 0x4104FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5099 0x4104FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5100 0x4104FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5101 0x4104FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5102 0x4104FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5103 0x4104FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5104 0x4104FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5105 0x4104FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5106 0x4104FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5107 0x4104FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5108 0x4104FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5109 0x4104FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5110 0x4104FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5111 0x4104FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5112 0x4104FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5113 0x4104FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5114 0x4104FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5115 0x4104FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5116 0x4104FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5117 0x4104FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5118 0x4104FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5119 0x4104FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5120 0x4105000 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5121 0x4105004 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5122 0x4105008 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5123 0x410500C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5124 0x4105010 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5125 0x4105014 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5126 0x4105018 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5127 0x410501C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5128 0x4105020 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5129 0x4105024 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5130 0x4105028 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5131 0x410502C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5132 0x4105030 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5133 0x4105034 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5134 0x4105038 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5135 0x410503C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5136 0x4105040 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5137 0x4105044 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5138 0x4105048 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5139 0x410504C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5140 0x4105050 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5141 0x4105054 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5142 0x4105058 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5143 0x410505C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5144 0x4105060 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5145 0x4105064 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5146 0x4105068 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5147 0x410506C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5148 0x4105070 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5149 0x4105074 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5150 0x4105078 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5151 0x410507C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5152 0x4105080 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5153 0x4105084 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5154 0x4105088 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5155 0x410508C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5156 0x4105090 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5157 0x4105094 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5158 0x4105098 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5159 0x410509C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5160 0x41050A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5161 0x41050A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5162 0x41050A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5163 0x41050AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5164 0x41050B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5165 0x41050B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5166 0x41050B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5167 0x41050BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5168 0x41050C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5169 0x41050C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5170 0x41050C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5171 0x41050CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5172 0x41050D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5173 0x41050D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5174 0x41050D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5175 0x41050DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5176 0x41050E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5177 0x41050E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5178 0x41050E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5179 0x41050EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5180 0x41050F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5181 0x41050F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5182 0x41050F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5183 0x41050FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5184 0x4105100 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5185 0x4105104 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5186 0x4105108 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5187 0x410510C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5188 0x4105110 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5189 0x4105114 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5190 0x4105118 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5191 0x410511C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5192 0x4105120 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5193 0x4105124 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5194 0x4105128 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5195 0x410512C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5196 0x4105130 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5197 0x4105134 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5198 0x4105138 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5199 0x410513C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5200 0x4105140 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5201 0x4105144 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5202 0x4105148 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5203 0x410514C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5204 0x4105150 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5205 0x4105154 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5206 0x4105158 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5207 0x410515C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5208 0x4105160 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5209 0x4105164 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5210 0x4105168 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5211 0x410516C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5212 0x4105170 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5213 0x4105174 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5214 0x4105178 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5215 0x410517C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5216 0x4105180 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5217 0x4105184 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5218 0x4105188 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5219 0x410518C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5220 0x4105190 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5221 0x4105194 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5222 0x4105198 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5223 0x410519C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5224 0x41051A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5225 0x41051A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5226 0x41051A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5227 0x41051AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5228 0x41051B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5229 0x41051B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5230 0x41051B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5231 0x41051BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5232 0x41051C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5233 0x41051C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5234 0x41051C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5235 0x41051CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5236 0x41051D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5237 0x41051D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5238 0x41051D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5239 0x41051DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5240 0x41051E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5241 0x41051E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5242 0x41051E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5243 0x41051EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5244 0x41051F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5245 0x41051F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5246 0x41051F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5247 0x41051FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5248 0x4105200 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5249 0x4105204 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5250 0x4105208 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5251 0x410520C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5252 0x4105210 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5253 0x4105214 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5254 0x4105218 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5255 0x410521C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5256 0x4105220 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5257 0x4105224 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5258 0x4105228 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5259 0x410522C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5260 0x4105230 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5261 0x4105234 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5262 0x4105238 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5263 0x410523C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5264 0x4105240 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5265 0x4105244 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5266 0x4105248 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5267 0x410524C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5268 0x4105250 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5269 0x4105254 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5270 0x4105258 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5271 0x410525C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5272 0x4105260 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5273 0x4105264 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5274 0x4105268 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5275 0x410526C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5276 0x4105270 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5277 0x4105274 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5278 0x4105278 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5279 0x410527C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5280 0x4105280 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5281 0x4105284 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5282 0x4105288 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5283 0x410528C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5284 0x4105290 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5285 0x4105294 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5286 0x4105298 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5287 0x410529C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5288 0x41052A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5289 0x41052A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5290 0x41052A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5291 0x41052AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5292 0x41052B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5293 0x41052B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5294 0x41052B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5295 0x41052BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5296 0x41052C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5297 0x41052C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5298 0x41052C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5299 0x41052CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5300 0x41052D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5301 0x41052D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5302 0x41052D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5303 0x41052DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5304 0x41052E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5305 0x41052E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5306 0x41052E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5307 0x41052EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5308 0x41052F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5309 0x41052F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5310 0x41052F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5311 0x41052FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5312 0x4105300 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5313 0x4105304 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5314 0x4105308 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5315 0x410530C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5316 0x4105310 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5317 0x4105314 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5318 0x4105318 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5319 0x410531C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5320 0x4105320 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5321 0x4105324 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5322 0x4105328 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5323 0x410532C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5324 0x4105330 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5325 0x4105334 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5326 0x4105338 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5327 0x410533C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5328 0x4105340 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5329 0x4105344 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5330 0x4105348 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5331 0x410534C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5332 0x4105350 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5333 0x4105354 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5334 0x4105358 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5335 0x410535C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5336 0x4105360 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5337 0x4105364 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5338 0x4105368 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5339 0x410536C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5340 0x4105370 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5341 0x4105374 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5342 0x4105378 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5343 0x410537C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5344 0x4105380 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5345 0x4105384 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5346 0x4105388 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5347 0x410538C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5348 0x4105390 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5349 0x4105394 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5350 0x4105398 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5351 0x410539C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5352 0x41053A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5353 0x41053A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5354 0x41053A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5355 0x41053AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5356 0x41053B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5357 0x41053B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5358 0x41053B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5359 0x41053BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5360 0x41053C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5361 0x41053C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5362 0x41053C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5363 0x41053CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5364 0x41053D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5365 0x41053D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5366 0x41053D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5367 0x41053DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5368 0x41053E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5369 0x41053E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5370 0x41053E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5371 0x41053EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5372 0x41053F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5373 0x41053F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5374 0x41053F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5375 0x41053FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5376 0x4105400 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5377 0x4105404 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5378 0x4105408 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5379 0x410540C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5380 0x4105410 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5381 0x4105414 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5382 0x4105418 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5383 0x410541C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5384 0x4105420 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5385 0x4105424 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5386 0x4105428 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5387 0x410542C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5388 0x4105430 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5389 0x4105434 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5390 0x4105438 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5391 0x410543C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5392 0x4105440 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5393 0x4105444 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5394 0x4105448 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5395 0x410544C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5396 0x4105450 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5397 0x4105454 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5398 0x4105458 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5399 0x410545C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5400 0x4105460 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5401 0x4105464 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5402 0x4105468 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5403 0x410546C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5404 0x4105470 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5405 0x4105474 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5406 0x4105478 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5407 0x410547C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5408 0x4105480 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5409 0x4105484 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5410 0x4105488 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5411 0x410548C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5412 0x4105490 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5413 0x4105494 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5414 0x4105498 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5415 0x410549C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5416 0x41054A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5417 0x41054A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5418 0x41054A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5419 0x41054AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5420 0x41054B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5421 0x41054B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5422 0x41054B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5423 0x41054BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5424 0x41054C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5425 0x41054C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5426 0x41054C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5427 0x41054CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5428 0x41054D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5429 0x41054D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5430 0x41054D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5431 0x41054DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5432 0x41054E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5433 0x41054E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5434 0x41054E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5435 0x41054EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5436 0x41054F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5437 0x41054F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5438 0x41054F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5439 0x41054FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5440 0x4105500 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5441 0x4105504 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5442 0x4105508 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5443 0x410550C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5444 0x4105510 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5445 0x4105514 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5446 0x4105518 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5447 0x410551C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5448 0x4105520 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5449 0x4105524 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5450 0x4105528 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5451 0x410552C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5452 0x4105530 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5453 0x4105534 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5454 0x4105538 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5455 0x410553C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5456 0x4105540 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5457 0x4105544 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5458 0x4105548 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5459 0x410554C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5460 0x4105550 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5461 0x4105554 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5462 0x4105558 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5463 0x410555C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5464 0x4105560 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5465 0x4105564 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5466 0x4105568 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5467 0x410556C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5468 0x4105570 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5469 0x4105574 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5470 0x4105578 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5471 0x410557C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5472 0x4105580 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5473 0x4105584 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5474 0x4105588 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5475 0x410558C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5476 0x4105590 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5477 0x4105594 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5478 0x4105598 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5479 0x410559C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5480 0x41055A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5481 0x41055A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5482 0x41055A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5483 0x41055AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5484 0x41055B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5485 0x41055B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5486 0x41055B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5487 0x41055BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5488 0x41055C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5489 0x41055C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5490 0x41055C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5491 0x41055CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5492 0x41055D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5493 0x41055D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5494 0x41055D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5495 0x41055DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5496 0x41055E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5497 0x41055E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5498 0x41055E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5499 0x41055EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5500 0x41055F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5501 0x41055F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5502 0x41055F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5503 0x41055FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5504 0x4105600 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5505 0x4105604 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5506 0x4105608 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5507 0x410560C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5508 0x4105610 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5509 0x4105614 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5510 0x4105618 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5511 0x410561C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5512 0x4105620 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5513 0x4105624 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5514 0x4105628 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5515 0x410562C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5516 0x4105630 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5517 0x4105634 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5518 0x4105638 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5519 0x410563C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5520 0x4105640 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5521 0x4105644 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5522 0x4105648 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5523 0x410564C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5524 0x4105650 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5525 0x4105654 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5526 0x4105658 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5527 0x410565C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5528 0x4105660 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5529 0x4105664 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5530 0x4105668 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5531 0x410566C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5532 0x4105670 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5533 0x4105674 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5534 0x4105678 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5535 0x410567C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5536 0x4105680 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5537 0x4105684 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5538 0x4105688 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5539 0x410568C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5540 0x4105690 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5541 0x4105694 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5542 0x4105698 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5543 0x410569C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5544 0x41056A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5545 0x41056A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5546 0x41056A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5547 0x41056AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5548 0x41056B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5549 0x41056B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5550 0x41056B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5551 0x41056BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5552 0x41056C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5553 0x41056C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5554 0x41056C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5555 0x41056CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5556 0x41056D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5557 0x41056D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5558 0x41056D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5559 0x41056DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5560 0x41056E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5561 0x41056E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5562 0x41056E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5563 0x41056EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5564 0x41056F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5565 0x41056F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5566 0x41056F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5567 0x41056FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5568 0x4105700 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5569 0x4105704 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5570 0x4105708 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5571 0x410570C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5572 0x4105710 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5573 0x4105714 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5574 0x4105718 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5575 0x410571C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5576 0x4105720 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5577 0x4105724 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5578 0x4105728 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5579 0x410572C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5580 0x4105730 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5581 0x4105734 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5582 0x4105738 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5583 0x410573C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5584 0x4105740 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5585 0x4105744 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5586 0x4105748 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5587 0x410574C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5588 0x4105750 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5589 0x4105754 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5590 0x4105758 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5591 0x410575C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5592 0x4105760 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5593 0x4105764 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5594 0x4105768 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5595 0x410576C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5596 0x4105770 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5597 0x4105774 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5598 0x4105778 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5599 0x410577C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5600 0x4105780 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5601 0x4105784 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5602 0x4105788 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5603 0x410578C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5604 0x4105790 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5605 0x4105794 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5606 0x4105798 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5607 0x410579C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5608 0x41057A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5609 0x41057A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5610 0x41057A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5611 0x41057AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5612 0x41057B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5613 0x41057B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5614 0x41057B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5615 0x41057BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5616 0x41057C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5617 0x41057C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5618 0x41057C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5619 0x41057CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5620 0x41057D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5621 0x41057D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5622 0x41057D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5623 0x41057DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5624 0x41057E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5625 0x41057E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5626 0x41057E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5627 0x41057EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5628 0x41057F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5629 0x41057F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5630 0x41057F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5631 0x41057FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5632 0x4105800 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5633 0x4105804 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5634 0x4105808 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5635 0x410580C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5636 0x4105810 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5637 0x4105814 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5638 0x4105818 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5639 0x410581C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5640 0x4105820 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5641 0x4105824 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5642 0x4105828 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5643 0x410582C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5644 0x4105830 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5645 0x4105834 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5646 0x4105838 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5647 0x410583C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5648 0x4105840 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5649 0x4105844 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5650 0x4105848 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5651 0x410584C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5652 0x4105850 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5653 0x4105854 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5654 0x4105858 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5655 0x410585C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5656 0x4105860 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5657 0x4105864 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5658 0x4105868 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5659 0x410586C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5660 0x4105870 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5661 0x4105874 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5662 0x4105878 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5663 0x410587C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5664 0x4105880 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5665 0x4105884 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5666 0x4105888 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5667 0x410588C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5668 0x4105890 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5669 0x4105894 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5670 0x4105898 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5671 0x410589C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5672 0x41058A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5673 0x41058A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5674 0x41058A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5675 0x41058AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5676 0x41058B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5677 0x41058B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5678 0x41058B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5679 0x41058BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5680 0x41058C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5681 0x41058C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5682 0x41058C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5683 0x41058CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5684 0x41058D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5685 0x41058D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5686 0x41058D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5687 0x41058DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5688 0x41058E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5689 0x41058E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5690 0x41058E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5691 0x41058EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5692 0x41058F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5693 0x41058F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5694 0x41058F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5695 0x41058FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5696 0x4105900 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5697 0x4105904 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5698 0x4105908 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5699 0x410590C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5700 0x4105910 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5701 0x4105914 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5702 0x4105918 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5703 0x410591C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5704 0x4105920 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5705 0x4105924 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5706 0x4105928 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5707 0x410592C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5708 0x4105930 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5709 0x4105934 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5710 0x4105938 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5711 0x410593C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5712 0x4105940 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5713 0x4105944 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5714 0x4105948 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5715 0x410594C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5716 0x4105950 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5717 0x4105954 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5718 0x4105958 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5719 0x410595C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5720 0x4105960 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5721 0x4105964 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5722 0x4105968 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5723 0x410596C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5724 0x4105970 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5725 0x4105974 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5726 0x4105978 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5727 0x410597C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5728 0x4105980 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5729 0x4105984 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5730 0x4105988 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5731 0x410598C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5732 0x4105990 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5733 0x4105994 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5734 0x4105998 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5735 0x410599C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5736 0x41059A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5737 0x41059A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5738 0x41059A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5739 0x41059AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5740 0x41059B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5741 0x41059B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5742 0x41059B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5743 0x41059BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5744 0x41059C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5745 0x41059C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5746 0x41059C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5747 0x41059CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5748 0x41059D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5749 0x41059D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5750 0x41059D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5751 0x41059DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5752 0x41059E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5753 0x41059E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5754 0x41059E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5755 0x41059EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5756 0x41059F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5757 0x41059F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5758 0x41059F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5759 0x41059FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5760 0x4105A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5761 0x4105A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5762 0x4105A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5763 0x4105A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5764 0x4105A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5765 0x4105A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5766 0x4105A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5767 0x4105A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5768 0x4105A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5769 0x4105A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5770 0x4105A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5771 0x4105A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5772 0x4105A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5773 0x4105A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5774 0x4105A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5775 0x4105A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5776 0x4105A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5777 0x4105A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5778 0x4105A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5779 0x4105A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5780 0x4105A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5781 0x4105A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5782 0x4105A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5783 0x4105A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5784 0x4105A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5785 0x4105A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5786 0x4105A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5787 0x4105A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5788 0x4105A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5789 0x4105A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5790 0x4105A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5791 0x4105A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5792 0x4105A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5793 0x4105A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5794 0x4105A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5795 0x4105A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5796 0x4105A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5797 0x4105A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5798 0x4105A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5799 0x4105A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5800 0x4105AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5801 0x4105AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5802 0x4105AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5803 0x4105AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5804 0x4105AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5805 0x4105AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5806 0x4105AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5807 0x4105ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5808 0x4105AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5809 0x4105AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5810 0x4105AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5811 0x4105ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5812 0x4105AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5813 0x4105AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5814 0x4105AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5815 0x4105ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5816 0x4105AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5817 0x4105AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5818 0x4105AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5819 0x4105AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5820 0x4105AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5821 0x4105AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5822 0x4105AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5823 0x4105AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5824 0x4105B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5825 0x4105B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5826 0x4105B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5827 0x4105B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5828 0x4105B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5829 0x4105B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5830 0x4105B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5831 0x4105B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5832 0x4105B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5833 0x4105B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5834 0x4105B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5835 0x4105B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5836 0x4105B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5837 0x4105B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5838 0x4105B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5839 0x4105B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5840 0x4105B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5841 0x4105B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5842 0x4105B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5843 0x4105B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5844 0x4105B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5845 0x4105B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5846 0x4105B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5847 0x4105B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5848 0x4105B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5849 0x4105B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5850 0x4105B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5851 0x4105B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5852 0x4105B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5853 0x4105B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5854 0x4105B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5855 0x4105B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5856 0x4105B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5857 0x4105B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5858 0x4105B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5859 0x4105B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5860 0x4105B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5861 0x4105B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5862 0x4105B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5863 0x4105B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5864 0x4105BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5865 0x4105BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5866 0x4105BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5867 0x4105BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5868 0x4105BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5869 0x4105BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5870 0x4105BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5871 0x4105BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5872 0x4105BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5873 0x4105BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5874 0x4105BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5875 0x4105BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5876 0x4105BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5877 0x4105BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5878 0x4105BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5879 0x4105BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5880 0x4105BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5881 0x4105BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5882 0x4105BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5883 0x4105BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5884 0x4105BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5885 0x4105BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5886 0x4105BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5887 0x4105BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5888 0x4105C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5889 0x4105C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5890 0x4105C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5891 0x4105C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5892 0x4105C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5893 0x4105C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5894 0x4105C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5895 0x4105C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5896 0x4105C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5897 0x4105C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5898 0x4105C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5899 0x4105C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5900 0x4105C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5901 0x4105C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5902 0x4105C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5903 0x4105C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5904 0x4105C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5905 0x4105C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5906 0x4105C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5907 0x4105C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5908 0x4105C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5909 0x4105C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5910 0x4105C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5911 0x4105C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5912 0x4105C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5913 0x4105C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5914 0x4105C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5915 0x4105C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5916 0x4105C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5917 0x4105C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5918 0x4105C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5919 0x4105C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5920 0x4105C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5921 0x4105C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5922 0x4105C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5923 0x4105C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5924 0x4105C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5925 0x4105C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5926 0x4105C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5927 0x4105C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5928 0x4105CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5929 0x4105CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5930 0x4105CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5931 0x4105CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5932 0x4105CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5933 0x4105CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5934 0x4105CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5935 0x4105CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5936 0x4105CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5937 0x4105CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5938 0x4105CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5939 0x4105CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5940 0x4105CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5941 0x4105CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5942 0x4105CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5943 0x4105CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5944 0x4105CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5945 0x4105CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5946 0x4105CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5947 0x4105CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5948 0x4105CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5949 0x4105CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5950 0x4105CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5951 0x4105CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5952 0x4105D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5953 0x4105D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5954 0x4105D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5955 0x4105D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5956 0x4105D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5957 0x4105D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5958 0x4105D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5959 0x4105D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5960 0x4105D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5961 0x4105D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5962 0x4105D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5963 0x4105D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5964 0x4105D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5965 0x4105D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5966 0x4105D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5967 0x4105D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5968 0x4105D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5969 0x4105D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5970 0x4105D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5971 0x4105D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5972 0x4105D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5973 0x4105D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5974 0x4105D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5975 0x4105D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5976 0x4105D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5977 0x4105D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5978 0x4105D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5979 0x4105D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5980 0x4105D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5981 0x4105D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5982 0x4105D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5983 0x4105D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5984 0x4105D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5985 0x4105D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5986 0x4105D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5987 0x4105D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5988 0x4105D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5989 0x4105D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5990 0x4105D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5991 0x4105D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5992 0x4105DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5993 0x4105DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5994 0x4105DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5995 0x4105DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5996 0x4105DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5997 0x4105DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5998 0x4105DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5999 0x4105DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6000 0x4105DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6001 0x4105DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6002 0x4105DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6003 0x4105DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6004 0x4105DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6005 0x4105DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6006 0x4105DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6007 0x4105DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6008 0x4105DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6009 0x4105DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6010 0x4105DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6011 0x4105DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6012 0x4105DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6013 0x4105DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6014 0x4105DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6015 0x4105DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6016 0x4105E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6017 0x4105E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6018 0x4105E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6019 0x4105E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6020 0x4105E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6021 0x4105E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6022 0x4105E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6023 0x4105E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6024 0x4105E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6025 0x4105E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6026 0x4105E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6027 0x4105E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6028 0x4105E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6029 0x4105E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6030 0x4105E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6031 0x4105E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6032 0x4105E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6033 0x4105E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6034 0x4105E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6035 0x4105E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6036 0x4105E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6037 0x4105E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6038 0x4105E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6039 0x4105E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6040 0x4105E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6041 0x4105E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6042 0x4105E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6043 0x4105E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6044 0x4105E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6045 0x4105E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6046 0x4105E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6047 0x4105E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6048 0x4105E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6049 0x4105E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6050 0x4105E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6051 0x4105E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6052 0x4105E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6053 0x4105E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6054 0x4105E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6055 0x4105E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6056 0x4105EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6057 0x4105EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6058 0x4105EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6059 0x4105EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6060 0x4105EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6061 0x4105EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6062 0x4105EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6063 0x4105EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6064 0x4105EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6065 0x4105EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6066 0x4105EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6067 0x4105ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6068 0x4105ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6069 0x4105ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6070 0x4105ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6071 0x4105EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6072 0x4105EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6073 0x4105EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6074 0x4105EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6075 0x4105EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6076 0x4105EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6077 0x4105EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6078 0x4105EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6079 0x4105EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6080 0x4105F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6081 0x4105F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6082 0x4105F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6083 0x4105F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6084 0x4105F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6085 0x4105F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6086 0x4105F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6087 0x4105F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6088 0x4105F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6089 0x4105F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6090 0x4105F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6091 0x4105F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6092 0x4105F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6093 0x4105F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6094 0x4105F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6095 0x4105F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6096 0x4105F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6097 0x4105F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6098 0x4105F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6099 0x4105F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6100 0x4105F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6101 0x4105F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6102 0x4105F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6103 0x4105F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6104 0x4105F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6105 0x4105F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6106 0x4105F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6107 0x4105F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6108 0x4105F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6109 0x4105F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6110 0x4105F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6111 0x4105F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6112 0x4105F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6113 0x4105F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6114 0x4105F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6115 0x4105F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6116 0x4105F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6117 0x4105F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6118 0x4105F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6119 0x4105F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6120 0x4105FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6121 0x4105FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6122 0x4105FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6123 0x4105FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6124 0x4105FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6125 0x4105FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6126 0x4105FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6127 0x4105FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6128 0x4105FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6129 0x4105FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6130 0x4105FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6131 0x4105FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6132 0x4105FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6133 0x4105FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6134 0x4105FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6135 0x4105FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6136 0x4105FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6137 0x4105FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6138 0x4105FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6139 0x4105FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6140 0x4105FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6141 0x4105FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6142 0x4105FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6143 0x4105FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6144 0x4106000 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6145 0x4106004 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6146 0x4106008 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6147 0x410600C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6148 0x4106010 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6149 0x4106014 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6150 0x4106018 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6151 0x410601C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6152 0x4106020 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6153 0x4106024 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6154 0x4106028 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6155 0x410602C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6156 0x4106030 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6157 0x4106034 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6158 0x4106038 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6159 0x410603C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6160 0x4106040 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6161 0x4106044 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6162 0x4106048 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6163 0x410604C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6164 0x4106050 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6165 0x4106054 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6166 0x4106058 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6167 0x410605C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6168 0x4106060 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6169 0x4106064 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6170 0x4106068 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6171 0x410606C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6172 0x4106070 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6173 0x4106074 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6174 0x4106078 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6175 0x410607C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6176 0x4106080 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6177 0x4106084 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6178 0x4106088 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6179 0x410608C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6180 0x4106090 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6181 0x4106094 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6182 0x4106098 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6183 0x410609C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6184 0x41060A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6185 0x41060A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6186 0x41060A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6187 0x41060AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6188 0x41060B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6189 0x41060B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6190 0x41060B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6191 0x41060BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6192 0x41060C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6193 0x41060C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6194 0x41060C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6195 0x41060CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6196 0x41060D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6197 0x41060D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6198 0x41060D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6199 0x41060DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6200 0x41060E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6201 0x41060E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6202 0x41060E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6203 0x41060EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6204 0x41060F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6205 0x41060F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6206 0x41060F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6207 0x41060FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6208 0x4106100 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6209 0x4106104 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6210 0x4106108 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6211 0x410610C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6212 0x4106110 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6213 0x4106114 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6214 0x4106118 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6215 0x410611C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6216 0x4106120 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6217 0x4106124 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6218 0x4106128 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6219 0x410612C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6220 0x4106130 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6221 0x4106134 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6222 0x4106138 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6223 0x410613C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6224 0x4106140 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6225 0x4106144 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6226 0x4106148 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6227 0x410614C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6228 0x4106150 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6229 0x4106154 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6230 0x4106158 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6231 0x410615C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6232 0x4106160 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6233 0x4106164 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6234 0x4106168 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6235 0x410616C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6236 0x4106170 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6237 0x4106174 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6238 0x4106178 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6239 0x410617C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6240 0x4106180 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6241 0x4106184 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6242 0x4106188 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6243 0x410618C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6244 0x4106190 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6245 0x4106194 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6246 0x4106198 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6247 0x410619C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6248 0x41061A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6249 0x41061A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6250 0x41061A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6251 0x41061AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6252 0x41061B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6253 0x41061B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6254 0x41061B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6255 0x41061BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6256 0x41061C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6257 0x41061C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6258 0x41061C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6259 0x41061CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6260 0x41061D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6261 0x41061D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6262 0x41061D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6263 0x41061DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6264 0x41061E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6265 0x41061E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6266 0x41061E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6267 0x41061EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6268 0x41061F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6269 0x41061F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6270 0x41061F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6271 0x41061FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6272 0x4106200 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6273 0x4106204 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6274 0x4106208 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6275 0x410620C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6276 0x4106210 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6277 0x4106214 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6278 0x4106218 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6279 0x410621C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6280 0x4106220 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6281 0x4106224 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6282 0x4106228 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6283 0x410622C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6284 0x4106230 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6285 0x4106234 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6286 0x4106238 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6287 0x410623C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6288 0x4106240 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6289 0x4106244 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6290 0x4106248 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6291 0x410624C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6292 0x4106250 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6293 0x4106254 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6294 0x4106258 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6295 0x410625C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6296 0x4106260 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6297 0x4106264 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6298 0x4106268 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6299 0x410626C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6300 0x4106270 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6301 0x4106274 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6302 0x4106278 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6303 0x410627C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6304 0x4106280 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6305 0x4106284 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6306 0x4106288 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6307 0x410628C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6308 0x4106290 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6309 0x4106294 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6310 0x4106298 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6311 0x410629C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6312 0x41062A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6313 0x41062A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6314 0x41062A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6315 0x41062AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6316 0x41062B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6317 0x41062B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6318 0x41062B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6319 0x41062BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6320 0x41062C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6321 0x41062C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6322 0x41062C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6323 0x41062CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6324 0x41062D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6325 0x41062D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6326 0x41062D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6327 0x41062DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6328 0x41062E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6329 0x41062E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6330 0x41062E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6331 0x41062EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6332 0x41062F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6333 0x41062F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6334 0x41062F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6335 0x41062FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6336 0x4106300 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6337 0x4106304 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6338 0x4106308 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6339 0x410630C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6340 0x4106310 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6341 0x4106314 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6342 0x4106318 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6343 0x410631C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6344 0x4106320 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6345 0x4106324 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6346 0x4106328 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6347 0x410632C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6348 0x4106330 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6349 0x4106334 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6350 0x4106338 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6351 0x410633C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6352 0x4106340 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6353 0x4106344 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6354 0x4106348 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6355 0x410634C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6356 0x4106350 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6357 0x4106354 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6358 0x4106358 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6359 0x410635C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6360 0x4106360 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6361 0x4106364 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6362 0x4106368 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6363 0x410636C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6364 0x4106370 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6365 0x4106374 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6366 0x4106378 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6367 0x410637C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6368 0x4106380 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6369 0x4106384 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6370 0x4106388 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6371 0x410638C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6372 0x4106390 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6373 0x4106394 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6374 0x4106398 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6375 0x410639C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6376 0x41063A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6377 0x41063A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6378 0x41063A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6379 0x41063AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6380 0x41063B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6381 0x41063B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6382 0x41063B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6383 0x41063BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6384 0x41063C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6385 0x41063C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6386 0x41063C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6387 0x41063CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6388 0x41063D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6389 0x41063D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6390 0x41063D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6391 0x41063DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6392 0x41063E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6393 0x41063E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6394 0x41063E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6395 0x41063EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6396 0x41063F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6397 0x41063F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6398 0x41063F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6399 0x41063FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6400 0x4106400 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6401 0x4106404 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6402 0x4106408 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6403 0x410640C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6404 0x4106410 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6405 0x4106414 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6406 0x4106418 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6407 0x410641C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6408 0x4106420 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6409 0x4106424 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6410 0x4106428 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6411 0x410642C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6412 0x4106430 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6413 0x4106434 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6414 0x4106438 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6415 0x410643C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6416 0x4106440 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6417 0x4106444 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6418 0x4106448 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6419 0x410644C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6420 0x4106450 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6421 0x4106454 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6422 0x4106458 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6423 0x410645C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6424 0x4106460 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6425 0x4106464 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6426 0x4106468 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6427 0x410646C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6428 0x4106470 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6429 0x4106474 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6430 0x4106478 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6431 0x410647C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6432 0x4106480 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6433 0x4106484 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6434 0x4106488 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6435 0x410648C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6436 0x4106490 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6437 0x4106494 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6438 0x4106498 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6439 0x410649C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6440 0x41064A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6441 0x41064A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6442 0x41064A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6443 0x41064AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6444 0x41064B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6445 0x41064B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6446 0x41064B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6447 0x41064BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6448 0x41064C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6449 0x41064C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6450 0x41064C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6451 0x41064CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6452 0x41064D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6453 0x41064D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6454 0x41064D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6455 0x41064DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6456 0x41064E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6457 0x41064E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6458 0x41064E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6459 0x41064EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6460 0x41064F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6461 0x41064F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6462 0x41064F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6463 0x41064FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6464 0x4106500 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6465 0x4106504 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6466 0x4106508 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6467 0x410650C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6468 0x4106510 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6469 0x4106514 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6470 0x4106518 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6471 0x410651C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6472 0x4106520 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6473 0x4106524 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6474 0x4106528 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6475 0x410652C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6476 0x4106530 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6477 0x4106534 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6478 0x4106538 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6479 0x410653C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6480 0x4106540 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6481 0x4106544 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6482 0x4106548 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6483 0x410654C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6484 0x4106550 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6485 0x4106554 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6486 0x4106558 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6487 0x410655C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6488 0x4106560 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6489 0x4106564 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6490 0x4106568 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6491 0x410656C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6492 0x4106570 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6493 0x4106574 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6494 0x4106578 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6495 0x410657C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6496 0x4106580 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6497 0x4106584 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6498 0x4106588 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6499 0x410658C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6500 0x4106590 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6501 0x4106594 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6502 0x4106598 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6503 0x410659C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6504 0x41065A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6505 0x41065A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6506 0x41065A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6507 0x41065AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6508 0x41065B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6509 0x41065B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6510 0x41065B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6511 0x41065BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6512 0x41065C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6513 0x41065C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6514 0x41065C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6515 0x41065CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6516 0x41065D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6517 0x41065D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6518 0x41065D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6519 0x41065DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6520 0x41065E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6521 0x41065E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6522 0x41065E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6523 0x41065EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6524 0x41065F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6525 0x41065F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6526 0x41065F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6527 0x41065FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6528 0x4106600 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6529 0x4106604 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6530 0x4106608 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6531 0x410660C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6532 0x4106610 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6533 0x4106614 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6534 0x4106618 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6535 0x410661C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6536 0x4106620 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6537 0x4106624 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6538 0x4106628 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6539 0x410662C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6540 0x4106630 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6541 0x4106634 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6542 0x4106638 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6543 0x410663C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6544 0x4106640 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6545 0x4106644 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6546 0x4106648 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6547 0x410664C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6548 0x4106650 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6549 0x4106654 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6550 0x4106658 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6551 0x410665C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6552 0x4106660 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6553 0x4106664 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6554 0x4106668 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6555 0x410666C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6556 0x4106670 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6557 0x4106674 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6558 0x4106678 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6559 0x410667C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6560 0x4106680 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6561 0x4106684 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6562 0x4106688 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6563 0x410668C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6564 0x4106690 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6565 0x4106694 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6566 0x4106698 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6567 0x410669C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6568 0x41066A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6569 0x41066A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6570 0x41066A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6571 0x41066AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6572 0x41066B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6573 0x41066B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6574 0x41066B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6575 0x41066BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6576 0x41066C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6577 0x41066C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6578 0x41066C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6579 0x41066CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6580 0x41066D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6581 0x41066D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6582 0x41066D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6583 0x41066DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6584 0x41066E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6585 0x41066E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6586 0x41066E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6587 0x41066EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6588 0x41066F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6589 0x41066F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6590 0x41066F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6591 0x41066FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6592 0x4106700 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6593 0x4106704 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6594 0x4106708 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6595 0x410670C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6596 0x4106710 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6597 0x4106714 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6598 0x4106718 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6599 0x410671C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6600 0x4106720 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6601 0x4106724 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6602 0x4106728 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6603 0x410672C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6604 0x4106730 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6605 0x4106734 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6606 0x4106738 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6607 0x410673C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6608 0x4106740 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6609 0x4106744 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6610 0x4106748 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6611 0x410674C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6612 0x4106750 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6613 0x4106754 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6614 0x4106758 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6615 0x410675C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6616 0x4106760 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6617 0x4106764 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6618 0x4106768 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6619 0x410676C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6620 0x4106770 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6621 0x4106774 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6622 0x4106778 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6623 0x410677C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6624 0x4106780 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6625 0x4106784 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6626 0x4106788 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6627 0x410678C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6628 0x4106790 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6629 0x4106794 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6630 0x4106798 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6631 0x410679C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6632 0x41067A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6633 0x41067A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6634 0x41067A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6635 0x41067AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6636 0x41067B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6637 0x41067B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6638 0x41067B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6639 0x41067BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6640 0x41067C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6641 0x41067C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6642 0x41067C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6643 0x41067CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6644 0x41067D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6645 0x41067D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6646 0x41067D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6647 0x41067DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6648 0x41067E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6649 0x41067E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6650 0x41067E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6651 0x41067EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6652 0x41067F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6653 0x41067F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6654 0x41067F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6655 0x41067FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6656 0x4106800 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6657 0x4106804 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6658 0x4106808 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6659 0x410680C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6660 0x4106810 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6661 0x4106814 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6662 0x4106818 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6663 0x410681C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6664 0x4106820 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6665 0x4106824 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6666 0x4106828 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6667 0x410682C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6668 0x4106830 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6669 0x4106834 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6670 0x4106838 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6671 0x410683C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6672 0x4106840 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6673 0x4106844 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6674 0x4106848 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6675 0x410684C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6676 0x4106850 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6677 0x4106854 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6678 0x4106858 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6679 0x410685C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6680 0x4106860 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6681 0x4106864 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6682 0x4106868 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6683 0x410686C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6684 0x4106870 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6685 0x4106874 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6686 0x4106878 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6687 0x410687C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6688 0x4106880 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6689 0x4106884 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6690 0x4106888 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6691 0x410688C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6692 0x4106890 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6693 0x4106894 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6694 0x4106898 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6695 0x410689C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6696 0x41068A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6697 0x41068A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6698 0x41068A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6699 0x41068AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6700 0x41068B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6701 0x41068B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6702 0x41068B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6703 0x41068BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6704 0x41068C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6705 0x41068C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6706 0x41068C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6707 0x41068CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6708 0x41068D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6709 0x41068D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6710 0x41068D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6711 0x41068DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6712 0x41068E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6713 0x41068E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6714 0x41068E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6715 0x41068EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6716 0x41068F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6717 0x41068F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6718 0x41068F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6719 0x41068FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6720 0x4106900 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6721 0x4106904 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6722 0x4106908 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6723 0x410690C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6724 0x4106910 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6725 0x4106914 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6726 0x4106918 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6727 0x410691C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6728 0x4106920 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6729 0x4106924 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6730 0x4106928 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6731 0x410692C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6732 0x4106930 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6733 0x4106934 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6734 0x4106938 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6735 0x410693C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6736 0x4106940 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6737 0x4106944 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6738 0x4106948 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6739 0x410694C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6740 0x4106950 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6741 0x4106954 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6742 0x4106958 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6743 0x410695C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6744 0x4106960 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6745 0x4106964 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6746 0x4106968 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6747 0x410696C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6748 0x4106970 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6749 0x4106974 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6750 0x4106978 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6751 0x410697C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6752 0x4106980 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6753 0x4106984 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6754 0x4106988 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6755 0x410698C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6756 0x4106990 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6757 0x4106994 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6758 0x4106998 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6759 0x410699C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6760 0x41069A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6761 0x41069A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6762 0x41069A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6763 0x41069AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6764 0x41069B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6765 0x41069B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6766 0x41069B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6767 0x41069BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6768 0x41069C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6769 0x41069C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6770 0x41069C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6771 0x41069CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6772 0x41069D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6773 0x41069D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6774 0x41069D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6775 0x41069DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6776 0x41069E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6777 0x41069E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6778 0x41069E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6779 0x41069EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6780 0x41069F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6781 0x41069F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6782 0x41069F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6783 0x41069FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6784 0x4106A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6785 0x4106A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6786 0x4106A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6787 0x4106A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6788 0x4106A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6789 0x4106A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6790 0x4106A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6791 0x4106A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6792 0x4106A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6793 0x4106A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6794 0x4106A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6795 0x4106A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6796 0x4106A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6797 0x4106A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6798 0x4106A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6799 0x4106A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6800 0x4106A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6801 0x4106A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6802 0x4106A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6803 0x4106A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6804 0x4106A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6805 0x4106A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6806 0x4106A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6807 0x4106A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6808 0x4106A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6809 0x4106A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6810 0x4106A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6811 0x4106A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6812 0x4106A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6813 0x4106A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6814 0x4106A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6815 0x4106A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6816 0x4106A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6817 0x4106A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6818 0x4106A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6819 0x4106A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6820 0x4106A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6821 0x4106A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6822 0x4106A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6823 0x4106A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6824 0x4106AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6825 0x4106AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6826 0x4106AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6827 0x4106AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6828 0x4106AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6829 0x4106AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6830 0x4106AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6831 0x4106ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6832 0x4106AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6833 0x4106AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6834 0x4106AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6835 0x4106ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6836 0x4106AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6837 0x4106AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6838 0x4106AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6839 0x4106ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6840 0x4106AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6841 0x4106AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6842 0x4106AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6843 0x4106AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6844 0x4106AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6845 0x4106AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6846 0x4106AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6847 0x4106AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6848 0x4106B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6849 0x4106B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6850 0x4106B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6851 0x4106B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6852 0x4106B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6853 0x4106B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6854 0x4106B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6855 0x4106B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6856 0x4106B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6857 0x4106B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6858 0x4106B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6859 0x4106B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6860 0x4106B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6861 0x4106B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6862 0x4106B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6863 0x4106B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6864 0x4106B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6865 0x4106B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6866 0x4106B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6867 0x4106B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6868 0x4106B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6869 0x4106B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6870 0x4106B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6871 0x4106B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6872 0x4106B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6873 0x4106B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6874 0x4106B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6875 0x4106B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6876 0x4106B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6877 0x4106B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6878 0x4106B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6879 0x4106B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6880 0x4106B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6881 0x4106B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6882 0x4106B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6883 0x4106B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6884 0x4106B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6885 0x4106B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6886 0x4106B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6887 0x4106B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6888 0x4106BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6889 0x4106BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6890 0x4106BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6891 0x4106BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6892 0x4106BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6893 0x4106BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6894 0x4106BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6895 0x4106BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6896 0x4106BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6897 0x4106BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6898 0x4106BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6899 0x4106BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6900 0x4106BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6901 0x4106BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6902 0x4106BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6903 0x4106BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6904 0x4106BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6905 0x4106BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6906 0x4106BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6907 0x4106BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6908 0x4106BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6909 0x4106BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6910 0x4106BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6911 0x4106BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6912 0x4106C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6913 0x4106C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6914 0x4106C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6915 0x4106C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6916 0x4106C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6917 0x4106C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6918 0x4106C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6919 0x4106C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6920 0x4106C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6921 0x4106C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6922 0x4106C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6923 0x4106C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6924 0x4106C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6925 0x4106C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6926 0x4106C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6927 0x4106C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6928 0x4106C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6929 0x4106C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6930 0x4106C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6931 0x4106C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6932 0x4106C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6933 0x4106C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6934 0x4106C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6935 0x4106C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6936 0x4106C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6937 0x4106C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6938 0x4106C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6939 0x4106C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6940 0x4106C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6941 0x4106C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6942 0x4106C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6943 0x4106C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6944 0x4106C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6945 0x4106C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6946 0x4106C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6947 0x4106C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6948 0x4106C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6949 0x4106C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6950 0x4106C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6951 0x4106C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6952 0x4106CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6953 0x4106CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6954 0x4106CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6955 0x4106CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6956 0x4106CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6957 0x4106CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6958 0x4106CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6959 0x4106CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6960 0x4106CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6961 0x4106CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6962 0x4106CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6963 0x4106CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6964 0x4106CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6965 0x4106CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6966 0x4106CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6967 0x4106CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6968 0x4106CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6969 0x4106CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6970 0x4106CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6971 0x4106CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6972 0x4106CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6973 0x4106CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6974 0x4106CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6975 0x4106CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6976 0x4106D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6977 0x4106D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6978 0x4106D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6979 0x4106D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6980 0x4106D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6981 0x4106D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6982 0x4106D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6983 0x4106D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6984 0x4106D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6985 0x4106D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6986 0x4106D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6987 0x4106D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6988 0x4106D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6989 0x4106D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6990 0x4106D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6991 0x4106D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6992 0x4106D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6993 0x4106D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6994 0x4106D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6995 0x4106D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6996 0x4106D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6997 0x4106D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6998 0x4106D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6999 0x4106D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7000 0x4106D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7001 0x4106D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7002 0x4106D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7003 0x4106D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7004 0x4106D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7005 0x4106D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7006 0x4106D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7007 0x4106D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7008 0x4106D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7009 0x4106D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7010 0x4106D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7011 0x4106D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7012 0x4106D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7013 0x4106D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7014 0x4106D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7015 0x4106D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7016 0x4106DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7017 0x4106DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7018 0x4106DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7019 0x4106DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7020 0x4106DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7021 0x4106DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7022 0x4106DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7023 0x4106DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7024 0x4106DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7025 0x4106DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7026 0x4106DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7027 0x4106DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7028 0x4106DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7029 0x4106DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7030 0x4106DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7031 0x4106DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7032 0x4106DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7033 0x4106DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7034 0x4106DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7035 0x4106DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7036 0x4106DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7037 0x4106DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7038 0x4106DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7039 0x4106DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7040 0x4106E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7041 0x4106E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7042 0x4106E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7043 0x4106E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7044 0x4106E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7045 0x4106E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7046 0x4106E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7047 0x4106E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7048 0x4106E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7049 0x4106E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7050 0x4106E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7051 0x4106E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7052 0x4106E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7053 0x4106E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7054 0x4106E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7055 0x4106E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7056 0x4106E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7057 0x4106E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7058 0x4106E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7059 0x4106E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7060 0x4106E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7061 0x4106E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7062 0x4106E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7063 0x4106E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7064 0x4106E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7065 0x4106E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7066 0x4106E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7067 0x4106E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7068 0x4106E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7069 0x4106E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7070 0x4106E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7071 0x4106E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7072 0x4106E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7073 0x4106E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7074 0x4106E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7075 0x4106E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7076 0x4106E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7077 0x4106E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7078 0x4106E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7079 0x4106E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7080 0x4106EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7081 0x4106EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7082 0x4106EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7083 0x4106EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7084 0x4106EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7085 0x4106EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7086 0x4106EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7087 0x4106EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7088 0x4106EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7089 0x4106EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7090 0x4106EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7091 0x4106ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7092 0x4106ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7093 0x4106ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7094 0x4106ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7095 0x4106EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7096 0x4106EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7097 0x4106EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7098 0x4106EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7099 0x4106EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7100 0x4106EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7101 0x4106EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7102 0x4106EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7103 0x4106EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7104 0x4106F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7105 0x4106F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7106 0x4106F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7107 0x4106F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7108 0x4106F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7109 0x4106F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7110 0x4106F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7111 0x4106F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7112 0x4106F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7113 0x4106F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7114 0x4106F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7115 0x4106F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7116 0x4106F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7117 0x4106F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7118 0x4106F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7119 0x4106F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7120 0x4106F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7121 0x4106F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7122 0x4106F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7123 0x4106F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7124 0x4106F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7125 0x4106F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7126 0x4106F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7127 0x4106F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7128 0x4106F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7129 0x4106F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7130 0x4106F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7131 0x4106F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7132 0x4106F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7133 0x4106F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7134 0x4106F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7135 0x4106F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7136 0x4106F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7137 0x4106F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7138 0x4106F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7139 0x4106F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7140 0x4106F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7141 0x4106F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7142 0x4106F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7143 0x4106F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7144 0x4106FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7145 0x4106FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7146 0x4106FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7147 0x4106FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7148 0x4106FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7149 0x4106FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7150 0x4106FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7151 0x4106FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7152 0x4106FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7153 0x4106FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7154 0x4106FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7155 0x4106FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7156 0x4106FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7157 0x4106FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7158 0x4106FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7159 0x4106FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7160 0x4106FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7161 0x4106FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7162 0x4106FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7163 0x4106FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7164 0x4106FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7165 0x4106FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7166 0x4106FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7167 0x4106FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7168 0x4107000 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7169 0x4107004 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7170 0x4107008 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7171 0x410700C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7172 0x4107010 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7173 0x4107014 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7174 0x4107018 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7175 0x410701C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7176 0x4107020 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7177 0x4107024 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7178 0x4107028 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7179 0x410702C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7180 0x4107030 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7181 0x4107034 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7182 0x4107038 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7183 0x410703C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7184 0x4107040 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7185 0x4107044 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7186 0x4107048 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7187 0x410704C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7188 0x4107050 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7189 0x4107054 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7190 0x4107058 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7191 0x410705C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7192 0x4107060 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7193 0x4107064 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7194 0x4107068 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7195 0x410706C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7196 0x4107070 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7197 0x4107074 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7198 0x4107078 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7199 0x410707C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7200 0x4107080 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7201 0x4107084 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7202 0x4107088 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7203 0x410708C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7204 0x4107090 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7205 0x4107094 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7206 0x4107098 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7207 0x410709C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7208 0x41070A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7209 0x41070A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7210 0x41070A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7211 0x41070AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7212 0x41070B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7213 0x41070B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7214 0x41070B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7215 0x41070BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7216 0x41070C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7217 0x41070C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7218 0x41070C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7219 0x41070CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7220 0x41070D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7221 0x41070D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7222 0x41070D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7223 0x41070DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7224 0x41070E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7225 0x41070E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7226 0x41070E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7227 0x41070EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7228 0x41070F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7229 0x41070F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7230 0x41070F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7231 0x41070FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7232 0x4107100 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7233 0x4107104 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7234 0x4107108 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7235 0x410710C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7236 0x4107110 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7237 0x4107114 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7238 0x4107118 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7239 0x410711C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7240 0x4107120 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7241 0x4107124 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7242 0x4107128 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7243 0x410712C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7244 0x4107130 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7245 0x4107134 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7246 0x4107138 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7247 0x410713C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7248 0x4107140 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7249 0x4107144 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7250 0x4107148 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7251 0x410714C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7252 0x4107150 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7253 0x4107154 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7254 0x4107158 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7255 0x410715C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7256 0x4107160 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7257 0x4107164 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7258 0x4107168 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7259 0x410716C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7260 0x4107170 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7261 0x4107174 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7262 0x4107178 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7263 0x410717C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7264 0x4107180 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7265 0x4107184 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7266 0x4107188 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7267 0x410718C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7268 0x4107190 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7269 0x4107194 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7270 0x4107198 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7271 0x410719C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7272 0x41071A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7273 0x41071A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7274 0x41071A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7275 0x41071AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7276 0x41071B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7277 0x41071B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7278 0x41071B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7279 0x41071BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7280 0x41071C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7281 0x41071C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7282 0x41071C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7283 0x41071CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7284 0x41071D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7285 0x41071D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7286 0x41071D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7287 0x41071DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7288 0x41071E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7289 0x41071E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7290 0x41071E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7291 0x41071EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7292 0x41071F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7293 0x41071F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7294 0x41071F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7295 0x41071FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7296 0x4107200 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7297 0x4107204 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7298 0x4107208 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7299 0x410720C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7300 0x4107210 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7301 0x4107214 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7302 0x4107218 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7303 0x410721C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7304 0x4107220 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7305 0x4107224 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7306 0x4107228 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7307 0x410722C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7308 0x4107230 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7309 0x4107234 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7310 0x4107238 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7311 0x410723C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7312 0x4107240 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7313 0x4107244 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7314 0x4107248 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7315 0x410724C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7316 0x4107250 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7317 0x4107254 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7318 0x4107258 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7319 0x410725C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7320 0x4107260 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7321 0x4107264 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7322 0x4107268 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7323 0x410726C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7324 0x4107270 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7325 0x4107274 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7326 0x4107278 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7327 0x410727C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7328 0x4107280 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7329 0x4107284 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7330 0x4107288 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7331 0x410728C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7332 0x4107290 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7333 0x4107294 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7334 0x4107298 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7335 0x410729C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7336 0x41072A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7337 0x41072A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7338 0x41072A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7339 0x41072AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7340 0x41072B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7341 0x41072B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7342 0x41072B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7343 0x41072BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7344 0x41072C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7345 0x41072C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7346 0x41072C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7347 0x41072CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7348 0x41072D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7349 0x41072D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7350 0x41072D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7351 0x41072DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7352 0x41072E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7353 0x41072E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7354 0x41072E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7355 0x41072EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7356 0x41072F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7357 0x41072F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7358 0x41072F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7359 0x41072FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7360 0x4107300 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7361 0x4107304 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7362 0x4107308 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7363 0x410730C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7364 0x4107310 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7365 0x4107314 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7366 0x4107318 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7367 0x410731C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7368 0x4107320 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7369 0x4107324 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7370 0x4107328 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7371 0x410732C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7372 0x4107330 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7373 0x4107334 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7374 0x4107338 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7375 0x410733C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7376 0x4107340 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7377 0x4107344 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7378 0x4107348 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7379 0x410734C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7380 0x4107350 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7381 0x4107354 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7382 0x4107358 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7383 0x410735C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7384 0x4107360 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7385 0x4107364 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7386 0x4107368 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7387 0x410736C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7388 0x4107370 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7389 0x4107374 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7390 0x4107378 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7391 0x410737C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7392 0x4107380 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7393 0x4107384 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7394 0x4107388 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7395 0x410738C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7396 0x4107390 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7397 0x4107394 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7398 0x4107398 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7399 0x410739C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7400 0x41073A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7401 0x41073A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7402 0x41073A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7403 0x41073AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7404 0x41073B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7405 0x41073B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7406 0x41073B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7407 0x41073BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7408 0x41073C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7409 0x41073C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7410 0x41073C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7411 0x41073CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7412 0x41073D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7413 0x41073D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7414 0x41073D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7415 0x41073DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7416 0x41073E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7417 0x41073E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7418 0x41073E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7419 0x41073EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7420 0x41073F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7421 0x41073F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7422 0x41073F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7423 0x41073FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7424 0x4107400 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7425 0x4107404 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7426 0x4107408 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7427 0x410740C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7428 0x4107410 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7429 0x4107414 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7430 0x4107418 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7431 0x410741C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7432 0x4107420 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7433 0x4107424 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7434 0x4107428 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7435 0x410742C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7436 0x4107430 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7437 0x4107434 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7438 0x4107438 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7439 0x410743C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7440 0x4107440 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7441 0x4107444 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7442 0x4107448 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7443 0x410744C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7444 0x4107450 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7445 0x4107454 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7446 0x4107458 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7447 0x410745C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7448 0x4107460 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7449 0x4107464 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7450 0x4107468 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7451 0x410746C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7452 0x4107470 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7453 0x4107474 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7454 0x4107478 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7455 0x410747C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7456 0x4107480 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7457 0x4107484 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7458 0x4107488 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7459 0x410748C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7460 0x4107490 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7461 0x4107494 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7462 0x4107498 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7463 0x410749C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7464 0x41074A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7465 0x41074A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7466 0x41074A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7467 0x41074AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7468 0x41074B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7469 0x41074B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7470 0x41074B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7471 0x41074BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7472 0x41074C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7473 0x41074C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7474 0x41074C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7475 0x41074CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7476 0x41074D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7477 0x41074D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7478 0x41074D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7479 0x41074DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7480 0x41074E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7481 0x41074E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7482 0x41074E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7483 0x41074EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7484 0x41074F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7485 0x41074F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7486 0x41074F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7487 0x41074FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7488 0x4107500 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7489 0x4107504 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7490 0x4107508 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7491 0x410750C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7492 0x4107510 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7493 0x4107514 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7494 0x4107518 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7495 0x410751C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7496 0x4107520 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7497 0x4107524 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7498 0x4107528 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7499 0x410752C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7500 0x4107530 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7501 0x4107534 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7502 0x4107538 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7503 0x410753C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7504 0x4107540 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7505 0x4107544 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7506 0x4107548 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7507 0x410754C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7508 0x4107550 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7509 0x4107554 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7510 0x4107558 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7511 0x410755C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7512 0x4107560 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7513 0x4107564 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7514 0x4107568 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7515 0x410756C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7516 0x4107570 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7517 0x4107574 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7518 0x4107578 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7519 0x410757C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7520 0x4107580 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7521 0x4107584 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7522 0x4107588 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7523 0x410758C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7524 0x4107590 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7525 0x4107594 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7526 0x4107598 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7527 0x410759C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7528 0x41075A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7529 0x41075A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7530 0x41075A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7531 0x41075AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7532 0x41075B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7533 0x41075B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7534 0x41075B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7535 0x41075BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7536 0x41075C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7537 0x41075C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7538 0x41075C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7539 0x41075CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7540 0x41075D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7541 0x41075D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7542 0x41075D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7543 0x41075DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7544 0x41075E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7545 0x41075E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7546 0x41075E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7547 0x41075EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7548 0x41075F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7549 0x41075F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7550 0x41075F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7551 0x41075FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7552 0x4107600 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7553 0x4107604 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7554 0x4107608 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7555 0x410760C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7556 0x4107610 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7557 0x4107614 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7558 0x4107618 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7559 0x410761C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7560 0x4107620 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7561 0x4107624 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7562 0x4107628 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7563 0x410762C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7564 0x4107630 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7565 0x4107634 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7566 0x4107638 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7567 0x410763C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7568 0x4107640 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7569 0x4107644 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7570 0x4107648 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7571 0x410764C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7572 0x4107650 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7573 0x4107654 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7574 0x4107658 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7575 0x410765C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7576 0x4107660 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7577 0x4107664 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7578 0x4107668 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7579 0x410766C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7580 0x4107670 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7581 0x4107674 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7582 0x4107678 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7583 0x410767C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7584 0x4107680 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7585 0x4107684 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7586 0x4107688 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7587 0x410768C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7588 0x4107690 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7589 0x4107694 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7590 0x4107698 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7591 0x410769C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7592 0x41076A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7593 0x41076A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7594 0x41076A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7595 0x41076AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7596 0x41076B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7597 0x41076B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7598 0x41076B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7599 0x41076BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7600 0x41076C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7601 0x41076C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7602 0x41076C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7603 0x41076CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7604 0x41076D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7605 0x41076D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7606 0x41076D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7607 0x41076DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7608 0x41076E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7609 0x41076E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7610 0x41076E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7611 0x41076EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7612 0x41076F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7613 0x41076F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7614 0x41076F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7615 0x41076FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7616 0x4107700 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7617 0x4107704 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7618 0x4107708 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7619 0x410770C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7620 0x4107710 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7621 0x4107714 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7622 0x4107718 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7623 0x410771C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7624 0x4107720 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7625 0x4107724 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7626 0x4107728 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7627 0x410772C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7628 0x4107730 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7629 0x4107734 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7630 0x4107738 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7631 0x410773C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7632 0x4107740 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7633 0x4107744 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7634 0x4107748 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7635 0x410774C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7636 0x4107750 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7637 0x4107754 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7638 0x4107758 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7639 0x410775C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7640 0x4107760 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7641 0x4107764 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7642 0x4107768 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7643 0x410776C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7644 0x4107770 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7645 0x4107774 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7646 0x4107778 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7647 0x410777C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7648 0x4107780 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7649 0x4107784 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7650 0x4107788 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7651 0x410778C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7652 0x4107790 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7653 0x4107794 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7654 0x4107798 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7655 0x410779C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7656 0x41077A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7657 0x41077A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7658 0x41077A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7659 0x41077AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7660 0x41077B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7661 0x41077B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7662 0x41077B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7663 0x41077BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7664 0x41077C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7665 0x41077C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7666 0x41077C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7667 0x41077CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7668 0x41077D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7669 0x41077D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7670 0x41077D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7671 0x41077DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7672 0x41077E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7673 0x41077E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7674 0x41077E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7675 0x41077EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7676 0x41077F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7677 0x41077F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7678 0x41077F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7679 0x41077FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7680 0x4107800 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7681 0x4107804 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7682 0x4107808 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7683 0x410780C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7684 0x4107810 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7685 0x4107814 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7686 0x4107818 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7687 0x410781C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7688 0x4107820 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7689 0x4107824 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7690 0x4107828 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7691 0x410782C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7692 0x4107830 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7693 0x4107834 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7694 0x4107838 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7695 0x410783C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7696 0x4107840 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7697 0x4107844 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7698 0x4107848 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7699 0x410784C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7700 0x4107850 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7701 0x4107854 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7702 0x4107858 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7703 0x410785C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7704 0x4107860 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7705 0x4107864 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7706 0x4107868 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7707 0x410786C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7708 0x4107870 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7709 0x4107874 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7710 0x4107878 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7711 0x410787C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7712 0x4107880 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7713 0x4107884 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7714 0x4107888 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7715 0x410788C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7716 0x4107890 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7717 0x4107894 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7718 0x4107898 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7719 0x410789C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7720 0x41078A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7721 0x41078A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7722 0x41078A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7723 0x41078AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7724 0x41078B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7725 0x41078B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7726 0x41078B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7727 0x41078BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7728 0x41078C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7729 0x41078C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7730 0x41078C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7731 0x41078CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7732 0x41078D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7733 0x41078D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7734 0x41078D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7735 0x41078DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7736 0x41078E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7737 0x41078E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7738 0x41078E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7739 0x41078EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7740 0x41078F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7741 0x41078F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7742 0x41078F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7743 0x41078FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7744 0x4107900 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7745 0x4107904 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7746 0x4107908 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7747 0x410790C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7748 0x4107910 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7749 0x4107914 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7750 0x4107918 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7751 0x410791C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7752 0x4107920 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7753 0x4107924 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7754 0x4107928 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7755 0x410792C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7756 0x4107930 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7757 0x4107934 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7758 0x4107938 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7759 0x410793C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7760 0x4107940 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7761 0x4107944 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7762 0x4107948 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7763 0x410794C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7764 0x4107950 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7765 0x4107954 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7766 0x4107958 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7767 0x410795C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7768 0x4107960 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7769 0x4107964 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7770 0x4107968 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7771 0x410796C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7772 0x4107970 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7773 0x4107974 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7774 0x4107978 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7775 0x410797C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7776 0x4107980 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7777 0x4107984 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7778 0x4107988 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7779 0x410798C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7780 0x4107990 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7781 0x4107994 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7782 0x4107998 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7783 0x410799C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7784 0x41079A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7785 0x41079A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7786 0x41079A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7787 0x41079AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7788 0x41079B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7789 0x41079B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7790 0x41079B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7791 0x41079BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7792 0x41079C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7793 0x41079C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7794 0x41079C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7795 0x41079CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7796 0x41079D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7797 0x41079D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7798 0x41079D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7799 0x41079DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7800 0x41079E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7801 0x41079E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7802 0x41079E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7803 0x41079EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7804 0x41079F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7805 0x41079F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7806 0x41079F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7807 0x41079FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7808 0x4107A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7809 0x4107A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7810 0x4107A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7811 0x4107A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7812 0x4107A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7813 0x4107A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7814 0x4107A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7815 0x4107A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7816 0x4107A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7817 0x4107A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7818 0x4107A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7819 0x4107A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7820 0x4107A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7821 0x4107A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7822 0x4107A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7823 0x4107A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7824 0x4107A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7825 0x4107A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7826 0x4107A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7827 0x4107A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7828 0x4107A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7829 0x4107A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7830 0x4107A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7831 0x4107A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7832 0x4107A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7833 0x4107A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7834 0x4107A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7835 0x4107A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7836 0x4107A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7837 0x4107A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7838 0x4107A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7839 0x4107A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7840 0x4107A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7841 0x4107A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7842 0x4107A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7843 0x4107A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7844 0x4107A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7845 0x4107A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7846 0x4107A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7847 0x4107A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7848 0x4107AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7849 0x4107AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7850 0x4107AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7851 0x4107AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7852 0x4107AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7853 0x4107AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7854 0x4107AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7855 0x4107ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7856 0x4107AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7857 0x4107AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7858 0x4107AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7859 0x4107ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7860 0x4107AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7861 0x4107AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7862 0x4107AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7863 0x4107ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7864 0x4107AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7865 0x4107AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7866 0x4107AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7867 0x4107AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7868 0x4107AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7869 0x4107AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7870 0x4107AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7871 0x4107AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7872 0x4107B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7873 0x4107B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7874 0x4107B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7875 0x4107B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7876 0x4107B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7877 0x4107B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7878 0x4107B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7879 0x4107B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7880 0x4107B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7881 0x4107B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7882 0x4107B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7883 0x4107B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7884 0x4107B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7885 0x4107B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7886 0x4107B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7887 0x4107B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7888 0x4107B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7889 0x4107B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7890 0x4107B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7891 0x4107B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7892 0x4107B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7893 0x4107B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7894 0x4107B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7895 0x4107B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7896 0x4107B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7897 0x4107B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7898 0x4107B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7899 0x4107B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7900 0x4107B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7901 0x4107B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7902 0x4107B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7903 0x4107B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7904 0x4107B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7905 0x4107B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7906 0x4107B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7907 0x4107B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7908 0x4107B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7909 0x4107B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7910 0x4107B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7911 0x4107B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7912 0x4107BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7913 0x4107BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7914 0x4107BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7915 0x4107BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7916 0x4107BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7917 0x4107BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7918 0x4107BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7919 0x4107BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7920 0x4107BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7921 0x4107BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7922 0x4107BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7923 0x4107BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7924 0x4107BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7925 0x4107BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7926 0x4107BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7927 0x4107BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7928 0x4107BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7929 0x4107BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7930 0x4107BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7931 0x4107BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7932 0x4107BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7933 0x4107BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7934 0x4107BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7935 0x4107BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7936 0x4107C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7937 0x4107C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7938 0x4107C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7939 0x4107C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7940 0x4107C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7941 0x4107C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7942 0x4107C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7943 0x4107C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7944 0x4107C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7945 0x4107C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7946 0x4107C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7947 0x4107C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7948 0x4107C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7949 0x4107C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7950 0x4107C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7951 0x4107C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7952 0x4107C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7953 0x4107C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7954 0x4107C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7955 0x4107C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7956 0x4107C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7957 0x4107C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7958 0x4107C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7959 0x4107C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7960 0x4107C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7961 0x4107C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7962 0x4107C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7963 0x4107C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7964 0x4107C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7965 0x4107C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7966 0x4107C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7967 0x4107C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7968 0x4107C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7969 0x4107C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7970 0x4107C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7971 0x4107C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7972 0x4107C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7973 0x4107C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7974 0x4107C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7975 0x4107C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7976 0x4107CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7977 0x4107CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7978 0x4107CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7979 0x4107CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7980 0x4107CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7981 0x4107CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7982 0x4107CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7983 0x4107CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7984 0x4107CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7985 0x4107CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7986 0x4107CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7987 0x4107CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7988 0x4107CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7989 0x4107CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7990 0x4107CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7991 0x4107CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7992 0x4107CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7993 0x4107CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7994 0x4107CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7995 0x4107CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7996 0x4107CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7997 0x4107CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7998 0x4107CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7999 0x4107CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8000 0x4107D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8001 0x4107D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8002 0x4107D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8003 0x4107D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8004 0x4107D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8005 0x4107D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8006 0x4107D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8007 0x4107D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8008 0x4107D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8009 0x4107D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8010 0x4107D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8011 0x4107D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8012 0x4107D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8013 0x4107D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8014 0x4107D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8015 0x4107D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8016 0x4107D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8017 0x4107D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8018 0x4107D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8019 0x4107D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8020 0x4107D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8021 0x4107D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8022 0x4107D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8023 0x4107D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8024 0x4107D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8025 0x4107D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8026 0x4107D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8027 0x4107D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8028 0x4107D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8029 0x4107D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8030 0x4107D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8031 0x4107D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8032 0x4107D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8033 0x4107D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8034 0x4107D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8035 0x4107D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8036 0x4107D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8037 0x4107D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8038 0x4107D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8039 0x4107D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8040 0x4107DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8041 0x4107DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8042 0x4107DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8043 0x4107DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8044 0x4107DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8045 0x4107DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8046 0x4107DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8047 0x4107DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8048 0x4107DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8049 0x4107DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8050 0x4107DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8051 0x4107DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8052 0x4107DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8053 0x4107DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8054 0x4107DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8055 0x4107DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8056 0x4107DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8057 0x4107DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8058 0x4107DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8059 0x4107DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8060 0x4107DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8061 0x4107DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8062 0x4107DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8063 0x4107DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8064 0x4107E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8065 0x4107E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8066 0x4107E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8067 0x4107E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8068 0x4107E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8069 0x4107E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8070 0x4107E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8071 0x4107E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8072 0x4107E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8073 0x4107E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8074 0x4107E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8075 0x4107E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8076 0x4107E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8077 0x4107E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8078 0x4107E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8079 0x4107E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8080 0x4107E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8081 0x4107E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8082 0x4107E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8083 0x4107E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8084 0x4107E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8085 0x4107E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8086 0x4107E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8087 0x4107E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8088 0x4107E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8089 0x4107E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8090 0x4107E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8091 0x4107E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8092 0x4107E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8093 0x4107E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8094 0x4107E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8095 0x4107E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8096 0x4107E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8097 0x4107E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8098 0x4107E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8099 0x4107E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8100 0x4107E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8101 0x4107E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8102 0x4107E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8103 0x4107E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8104 0x4107EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8105 0x4107EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8106 0x4107EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8107 0x4107EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8108 0x4107EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8109 0x4107EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8110 0x4107EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8111 0x4107EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8112 0x4107EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8113 0x4107EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8114 0x4107EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8115 0x4107ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8116 0x4107ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8117 0x4107ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8118 0x4107ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8119 0x4107EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8120 0x4107EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8121 0x4107EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8122 0x4107EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8123 0x4107EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8124 0x4107EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8125 0x4107EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8126 0x4107EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8127 0x4107EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8128 0x4107F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8129 0x4107F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8130 0x4107F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8131 0x4107F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8132 0x4107F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8133 0x4107F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8134 0x4107F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8135 0x4107F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8136 0x4107F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8137 0x4107F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8138 0x4107F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8139 0x4107F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8140 0x4107F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8141 0x4107F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8142 0x4107F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8143 0x4107F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8144 0x4107F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8145 0x4107F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8146 0x4107F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8147 0x4107F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8148 0x4107F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8149 0x4107F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8150 0x4107F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8151 0x4107F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8152 0x4107F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8153 0x4107F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8154 0x4107F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8155 0x4107F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8156 0x4107F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8157 0x4107F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8158 0x4107F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8159 0x4107F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8160 0x4107F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8161 0x4107F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8162 0x4107F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8163 0x4107F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8164 0x4107F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8165 0x4107F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8166 0x4107F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8167 0x4107F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8168 0x4107FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8169 0x4107FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8170 0x4107FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8171 0x4107FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8172 0x4107FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8173 0x4107FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8174 0x4107FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8175 0x4107FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8176 0x4107FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8177 0x4107FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8178 0x4107FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8179 0x4107FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8180 0x4107FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8181 0x4107FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8182 0x4107FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8183 0x4107FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8184 0x4107FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8185 0x4107FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8186 0x4107FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8187 0x4107FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8188 0x4107FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8189 0x4107FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8190 0x4107FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8191 0x4107FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 0x4108000 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1 0x4108004 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2 0x4108008 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_3 0x410800C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_4 0x4108010 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_5 0x4108014 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_6 0x4108018 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_7 0x410801C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_8 0x4108020 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_9 0x4108024 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_10 0x4108028 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_11 0x410802C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_12 0x4108030 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_13 0x4108034 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_14 0x4108038 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_15 0x410803C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_16 0x4108040 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_17 0x4108044 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_18 0x4108048 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_19 0x410804C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_20 0x4108050 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_21 0x4108054 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_22 0x4108058 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_23 0x410805C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_24 0x4108060 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_25 0x4108064 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_26 0x4108068 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_27 0x410806C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_28 0x4108070 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_29 0x4108074 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_30 0x4108078 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_31 0x410807C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_32 0x4108080 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_33 0x4108084 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_34 0x4108088 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_35 0x410808C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_36 0x4108090 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_37 0x4108094 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_38 0x4108098 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_39 0x410809C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_40 0x41080A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_41 0x41080A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_42 0x41080A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_43 0x41080AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_44 0x41080B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_45 0x41080B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_46 0x41080B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_47 0x41080BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_48 0x41080C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_49 0x41080C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_50 0x41080C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_51 0x41080CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_52 0x41080D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_53 0x41080D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_54 0x41080D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_55 0x41080DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_56 0x41080E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_57 0x41080E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_58 0x41080E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_59 0x41080EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_60 0x41080F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_61 0x41080F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_62 0x41080F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_63 0x41080FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_64 0x4108100 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_65 0x4108104 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_66 0x4108108 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_67 0x410810C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_68 0x4108110 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_69 0x4108114 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_70 0x4108118 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_71 0x410811C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_72 0x4108120 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_73 0x4108124 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_74 0x4108128 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_75 0x410812C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_76 0x4108130 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_77 0x4108134 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_78 0x4108138 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_79 0x410813C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_80 0x4108140 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_81 0x4108144 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_82 0x4108148 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_83 0x410814C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_84 0x4108150 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_85 0x4108154 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_86 0x4108158 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_87 0x410815C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_88 0x4108160 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_89 0x4108164 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_90 0x4108168 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_91 0x410816C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_92 0x4108170 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_93 0x4108174 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_94 0x4108178 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_95 0x410817C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_96 0x4108180 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_97 0x4108184 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_98 0x4108188 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_99 0x410818C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_100 0x4108190 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_101 0x4108194 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_102 0x4108198 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_103 0x410819C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_104 0x41081A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_105 0x41081A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_106 0x41081A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_107 0x41081AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_108 0x41081B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_109 0x41081B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_110 0x41081B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_111 0x41081BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_112 0x41081C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_113 0x41081C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_114 0x41081C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_115 0x41081CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_116 0x41081D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_117 0x41081D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_118 0x41081D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_119 0x41081DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_120 0x41081E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_121 0x41081E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_122 0x41081E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_123 0x41081EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_124 0x41081F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_125 0x41081F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_126 0x41081F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_127 0x41081FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_128 0x4108200 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_129 0x4108204 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_130 0x4108208 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_131 0x410820C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_132 0x4108210 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_133 0x4108214 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_134 0x4108218 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_135 0x410821C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_136 0x4108220 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_137 0x4108224 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_138 0x4108228 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_139 0x410822C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_140 0x4108230 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_141 0x4108234 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_142 0x4108238 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_143 0x410823C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_144 0x4108240 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_145 0x4108244 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_146 0x4108248 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_147 0x410824C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_148 0x4108250 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_149 0x4108254 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_150 0x4108258 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_151 0x410825C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_152 0x4108260 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_153 0x4108264 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_154 0x4108268 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_155 0x410826C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_156 0x4108270 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_157 0x4108274 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_158 0x4108278 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_159 0x410827C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_160 0x4108280 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_161 0x4108284 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_162 0x4108288 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_163 0x410828C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_164 0x4108290 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_165 0x4108294 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_166 0x4108298 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_167 0x410829C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_168 0x41082A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_169 0x41082A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_170 0x41082A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_171 0x41082AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_172 0x41082B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_173 0x41082B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_174 0x41082B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_175 0x41082BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_176 0x41082C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_177 0x41082C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_178 0x41082C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_179 0x41082CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_180 0x41082D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_181 0x41082D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_182 0x41082D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_183 0x41082DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_184 0x41082E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_185 0x41082E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_186 0x41082E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_187 0x41082EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_188 0x41082F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_189 0x41082F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_190 0x41082F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_191 0x41082FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_192 0x4108300 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_193 0x4108304 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_194 0x4108308 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_195 0x410830C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_196 0x4108310 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_197 0x4108314 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_198 0x4108318 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_199 0x410831C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_200 0x4108320 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_201 0x4108324 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_202 0x4108328 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_203 0x410832C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_204 0x4108330 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_205 0x4108334 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_206 0x4108338 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_207 0x410833C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_208 0x4108340 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_209 0x4108344 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_210 0x4108348 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_211 0x410834C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_212 0x4108350 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_213 0x4108354 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_214 0x4108358 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_215 0x410835C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_216 0x4108360 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_217 0x4108364 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_218 0x4108368 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_219 0x410836C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_220 0x4108370 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_221 0x4108374 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_222 0x4108378 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_223 0x410837C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_224 0x4108380 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_225 0x4108384 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_226 0x4108388 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_227 0x410838C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_228 0x4108390 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_229 0x4108394 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_230 0x4108398 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_231 0x410839C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_232 0x41083A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_233 0x41083A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_234 0x41083A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_235 0x41083AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_236 0x41083B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_237 0x41083B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_238 0x41083B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_239 0x41083BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_240 0x41083C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_241 0x41083C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_242 0x41083C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_243 0x41083CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_244 0x41083D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_245 0x41083D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_246 0x41083D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_247 0x41083DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_248 0x41083E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_249 0x41083E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_250 0x41083E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_251 0x41083EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_252 0x41083F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_253 0x41083F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_254 0x41083F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_255 0x41083FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_256 0x4108400 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_257 0x4108404 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_258 0x4108408 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_259 0x410840C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_260 0x4108410 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_261 0x4108414 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_262 0x4108418 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_263 0x410841C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_264 0x4108420 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_265 0x4108424 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_266 0x4108428 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_267 0x410842C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_268 0x4108430 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_269 0x4108434 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_270 0x4108438 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_271 0x410843C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_272 0x4108440 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_273 0x4108444 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_274 0x4108448 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_275 0x410844C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_276 0x4108450 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_277 0x4108454 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_278 0x4108458 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_279 0x410845C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_280 0x4108460 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_281 0x4108464 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_282 0x4108468 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_283 0x410846C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_284 0x4108470 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_285 0x4108474 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_286 0x4108478 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_287 0x410847C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_288 0x4108480 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_289 0x4108484 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_290 0x4108488 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_291 0x410848C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_292 0x4108490 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_293 0x4108494 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_294 0x4108498 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_295 0x410849C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_296 0x41084A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_297 0x41084A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_298 0x41084A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_299 0x41084AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_300 0x41084B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_301 0x41084B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_302 0x41084B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_303 0x41084BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_304 0x41084C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_305 0x41084C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_306 0x41084C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_307 0x41084CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_308 0x41084D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_309 0x41084D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_310 0x41084D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_311 0x41084DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_312 0x41084E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_313 0x41084E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_314 0x41084E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_315 0x41084EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_316 0x41084F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_317 0x41084F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_318 0x41084F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_319 0x41084FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_320 0x4108500 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_321 0x4108504 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_322 0x4108508 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_323 0x410850C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_324 0x4108510 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_325 0x4108514 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_326 0x4108518 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_327 0x410851C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_328 0x4108520 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_329 0x4108524 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_330 0x4108528 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_331 0x410852C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_332 0x4108530 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_333 0x4108534 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_334 0x4108538 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_335 0x410853C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_336 0x4108540 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_337 0x4108544 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_338 0x4108548 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_339 0x410854C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_340 0x4108550 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_341 0x4108554 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_342 0x4108558 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_343 0x410855C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_344 0x4108560 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_345 0x4108564 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_346 0x4108568 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_347 0x410856C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_348 0x4108570 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_349 0x4108574 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_350 0x4108578 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_351 0x410857C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_352 0x4108580 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_353 0x4108584 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_354 0x4108588 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_355 0x410858C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_356 0x4108590 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_357 0x4108594 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_358 0x4108598 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_359 0x410859C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_360 0x41085A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_361 0x41085A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_362 0x41085A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_363 0x41085AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_364 0x41085B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_365 0x41085B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_366 0x41085B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_367 0x41085BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_368 0x41085C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_369 0x41085C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_370 0x41085C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_371 0x41085CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_372 0x41085D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_373 0x41085D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_374 0x41085D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_375 0x41085DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_376 0x41085E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_377 0x41085E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_378 0x41085E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_379 0x41085EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_380 0x41085F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_381 0x41085F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_382 0x41085F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_383 0x41085FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_384 0x4108600 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_385 0x4108604 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_386 0x4108608 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_387 0x410860C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_388 0x4108610 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_389 0x4108614 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_390 0x4108618 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_391 0x410861C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_392 0x4108620 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_393 0x4108624 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_394 0x4108628 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_395 0x410862C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_396 0x4108630 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_397 0x4108634 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_398 0x4108638 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_399 0x410863C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_400 0x4108640 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_401 0x4108644 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_402 0x4108648 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_403 0x410864C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_404 0x4108650 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_405 0x4108654 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_406 0x4108658 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_407 0x410865C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_408 0x4108660 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_409 0x4108664 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_410 0x4108668 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_411 0x410866C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_412 0x4108670 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_413 0x4108674 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_414 0x4108678 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_415 0x410867C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_416 0x4108680 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_417 0x4108684 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_418 0x4108688 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_419 0x410868C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_420 0x4108690 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_421 0x4108694 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_422 0x4108698 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_423 0x410869C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_424 0x41086A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_425 0x41086A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_426 0x41086A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_427 0x41086AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_428 0x41086B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_429 0x41086B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_430 0x41086B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_431 0x41086BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_432 0x41086C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_433 0x41086C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_434 0x41086C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_435 0x41086CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_436 0x41086D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_437 0x41086D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_438 0x41086D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_439 0x41086DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_440 0x41086E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_441 0x41086E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_442 0x41086E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_443 0x41086EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_444 0x41086F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_445 0x41086F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_446 0x41086F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_447 0x41086FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_448 0x4108700 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_449 0x4108704 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_450 0x4108708 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_451 0x410870C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_452 0x4108710 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_453 0x4108714 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_454 0x4108718 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_455 0x410871C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_456 0x4108720 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_457 0x4108724 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_458 0x4108728 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_459 0x410872C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_460 0x4108730 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_461 0x4108734 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_462 0x4108738 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_463 0x410873C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_464 0x4108740 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_465 0x4108744 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_466 0x4108748 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_467 0x410874C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_468 0x4108750 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_469 0x4108754 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_470 0x4108758 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_471 0x410875C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_472 0x4108760 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_473 0x4108764 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_474 0x4108768 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_475 0x410876C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_476 0x4108770 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_477 0x4108774 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_478 0x4108778 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_479 0x410877C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_480 0x4108780 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_481 0x4108784 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_482 0x4108788 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_483 0x410878C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_484 0x4108790 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_485 0x4108794 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_486 0x4108798 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_487 0x410879C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_488 0x41087A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_489 0x41087A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_490 0x41087A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_491 0x41087AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_492 0x41087B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_493 0x41087B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_494 0x41087B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_495 0x41087BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_496 0x41087C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_497 0x41087C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_498 0x41087C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_499 0x41087CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_500 0x41087D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_501 0x41087D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_502 0x41087D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_503 0x41087DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_504 0x41087E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_505 0x41087E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_506 0x41087E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_507 0x41087EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_508 0x41087F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_509 0x41087F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_510 0x41087F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_511 0x41087FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_512 0x4108800 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_513 0x4108804 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_514 0x4108808 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_515 0x410880C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_516 0x4108810 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_517 0x4108814 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_518 0x4108818 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_519 0x410881C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_520 0x4108820 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_521 0x4108824 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_522 0x4108828 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_523 0x410882C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_524 0x4108830 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_525 0x4108834 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_526 0x4108838 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_527 0x410883C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_528 0x4108840 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_529 0x4108844 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_530 0x4108848 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_531 0x410884C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_532 0x4108850 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_533 0x4108854 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_534 0x4108858 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_535 0x410885C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_536 0x4108860 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_537 0x4108864 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_538 0x4108868 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_539 0x410886C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_540 0x4108870 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_541 0x4108874 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_542 0x4108878 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_543 0x410887C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_544 0x4108880 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_545 0x4108884 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_546 0x4108888 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_547 0x410888C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_548 0x4108890 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_549 0x4108894 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_550 0x4108898 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_551 0x410889C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_552 0x41088A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_553 0x41088A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_554 0x41088A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_555 0x41088AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_556 0x41088B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_557 0x41088B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_558 0x41088B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_559 0x41088BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_560 0x41088C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_561 0x41088C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_562 0x41088C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_563 0x41088CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_564 0x41088D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_565 0x41088D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_566 0x41088D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_567 0x41088DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_568 0x41088E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_569 0x41088E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_570 0x41088E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_571 0x41088EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_572 0x41088F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_573 0x41088F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_574 0x41088F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_575 0x41088FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_576 0x4108900 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_577 0x4108904 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_578 0x4108908 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_579 0x410890C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_580 0x4108910 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_581 0x4108914 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_582 0x4108918 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_583 0x410891C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_584 0x4108920 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_585 0x4108924 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_586 0x4108928 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_587 0x410892C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_588 0x4108930 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_589 0x4108934 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_590 0x4108938 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_591 0x410893C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_592 0x4108940 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_593 0x4108944 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_594 0x4108948 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_595 0x410894C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_596 0x4108950 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_597 0x4108954 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_598 0x4108958 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_599 0x410895C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_600 0x4108960 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_601 0x4108964 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_602 0x4108968 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_603 0x410896C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_604 0x4108970 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_605 0x4108974 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_606 0x4108978 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_607 0x410897C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_608 0x4108980 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_609 0x4108984 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_610 0x4108988 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_611 0x410898C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_612 0x4108990 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_613 0x4108994 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_614 0x4108998 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_615 0x410899C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_616 0x41089A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_617 0x41089A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_618 0x41089A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_619 0x41089AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_620 0x41089B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_621 0x41089B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_622 0x41089B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_623 0x41089BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_624 0x41089C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_625 0x41089C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_626 0x41089C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_627 0x41089CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_628 0x41089D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_629 0x41089D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_630 0x41089D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_631 0x41089DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_632 0x41089E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_633 0x41089E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_634 0x41089E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_635 0x41089EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_636 0x41089F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_637 0x41089F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_638 0x41089F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_639 0x41089FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_640 0x4108A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_641 0x4108A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_642 0x4108A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_643 0x4108A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_644 0x4108A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_645 0x4108A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_646 0x4108A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_647 0x4108A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_648 0x4108A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_649 0x4108A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_650 0x4108A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_651 0x4108A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_652 0x4108A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_653 0x4108A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_654 0x4108A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_655 0x4108A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_656 0x4108A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_657 0x4108A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_658 0x4108A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_659 0x4108A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_660 0x4108A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_661 0x4108A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_662 0x4108A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_663 0x4108A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_664 0x4108A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_665 0x4108A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_666 0x4108A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_667 0x4108A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_668 0x4108A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_669 0x4108A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_670 0x4108A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_671 0x4108A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_672 0x4108A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_673 0x4108A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_674 0x4108A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_675 0x4108A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_676 0x4108A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_677 0x4108A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_678 0x4108A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_679 0x4108A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_680 0x4108AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_681 0x4108AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_682 0x4108AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_683 0x4108AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_684 0x4108AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_685 0x4108AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_686 0x4108AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_687 0x4108ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_688 0x4108AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_689 0x4108AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_690 0x4108AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_691 0x4108ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_692 0x4108AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_693 0x4108AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_694 0x4108AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_695 0x4108ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_696 0x4108AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_697 0x4108AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_698 0x4108AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_699 0x4108AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_700 0x4108AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_701 0x4108AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_702 0x4108AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_703 0x4108AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_704 0x4108B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_705 0x4108B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_706 0x4108B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_707 0x4108B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_708 0x4108B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_709 0x4108B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_710 0x4108B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_711 0x4108B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_712 0x4108B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_713 0x4108B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_714 0x4108B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_715 0x4108B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_716 0x4108B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_717 0x4108B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_718 0x4108B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_719 0x4108B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_720 0x4108B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_721 0x4108B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_722 0x4108B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_723 0x4108B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_724 0x4108B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_725 0x4108B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_726 0x4108B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_727 0x4108B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_728 0x4108B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_729 0x4108B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_730 0x4108B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_731 0x4108B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_732 0x4108B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_733 0x4108B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_734 0x4108B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_735 0x4108B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_736 0x4108B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_737 0x4108B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_738 0x4108B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_739 0x4108B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_740 0x4108B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_741 0x4108B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_742 0x4108B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_743 0x4108B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_744 0x4108BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_745 0x4108BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_746 0x4108BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_747 0x4108BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_748 0x4108BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_749 0x4108BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_750 0x4108BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_751 0x4108BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_752 0x4108BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_753 0x4108BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_754 0x4108BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_755 0x4108BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_756 0x4108BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_757 0x4108BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_758 0x4108BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_759 0x4108BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_760 0x4108BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_761 0x4108BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_762 0x4108BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_763 0x4108BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_764 0x4108BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_765 0x4108BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_766 0x4108BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_767 0x4108BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_768 0x4108C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_769 0x4108C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_770 0x4108C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_771 0x4108C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_772 0x4108C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_773 0x4108C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_774 0x4108C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_775 0x4108C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_776 0x4108C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_777 0x4108C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_778 0x4108C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_779 0x4108C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_780 0x4108C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_781 0x4108C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_782 0x4108C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_783 0x4108C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_784 0x4108C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_785 0x4108C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_786 0x4108C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_787 0x4108C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_788 0x4108C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_789 0x4108C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_790 0x4108C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_791 0x4108C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_792 0x4108C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_793 0x4108C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_794 0x4108C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_795 0x4108C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_796 0x4108C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_797 0x4108C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_798 0x4108C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_799 0x4108C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_800 0x4108C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_801 0x4108C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_802 0x4108C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_803 0x4108C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_804 0x4108C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_805 0x4108C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_806 0x4108C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_807 0x4108C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_808 0x4108CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_809 0x4108CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_810 0x4108CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_811 0x4108CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_812 0x4108CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_813 0x4108CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_814 0x4108CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_815 0x4108CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_816 0x4108CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_817 0x4108CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_818 0x4108CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_819 0x4108CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_820 0x4108CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_821 0x4108CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_822 0x4108CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_823 0x4108CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_824 0x4108CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_825 0x4108CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_826 0x4108CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_827 0x4108CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_828 0x4108CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_829 0x4108CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_830 0x4108CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_831 0x4108CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_832 0x4108D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_833 0x4108D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_834 0x4108D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_835 0x4108D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_836 0x4108D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_837 0x4108D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_838 0x4108D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_839 0x4108D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_840 0x4108D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_841 0x4108D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_842 0x4108D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_843 0x4108D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_844 0x4108D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_845 0x4108D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_846 0x4108D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_847 0x4108D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_848 0x4108D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_849 0x4108D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_850 0x4108D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_851 0x4108D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_852 0x4108D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_853 0x4108D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_854 0x4108D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_855 0x4108D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_856 0x4108D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_857 0x4108D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_858 0x4108D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_859 0x4108D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_860 0x4108D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_861 0x4108D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_862 0x4108D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_863 0x4108D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_864 0x4108D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_865 0x4108D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_866 0x4108D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_867 0x4108D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_868 0x4108D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_869 0x4108D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_870 0x4108D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_871 0x4108D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_872 0x4108DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_873 0x4108DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_874 0x4108DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_875 0x4108DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_876 0x4108DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_877 0x4108DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_878 0x4108DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_879 0x4108DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_880 0x4108DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_881 0x4108DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_882 0x4108DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_883 0x4108DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_884 0x4108DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_885 0x4108DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_886 0x4108DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_887 0x4108DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_888 0x4108DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_889 0x4108DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_890 0x4108DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_891 0x4108DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_892 0x4108DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_893 0x4108DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_894 0x4108DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_895 0x4108DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_896 0x4108E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_897 0x4108E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_898 0x4108E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_899 0x4108E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_900 0x4108E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_901 0x4108E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_902 0x4108E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_903 0x4108E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_904 0x4108E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_905 0x4108E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_906 0x4108E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_907 0x4108E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_908 0x4108E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_909 0x4108E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_910 0x4108E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_911 0x4108E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_912 0x4108E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_913 0x4108E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_914 0x4108E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_915 0x4108E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_916 0x4108E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_917 0x4108E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_918 0x4108E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_919 0x4108E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_920 0x4108E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_921 0x4108E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_922 0x4108E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_923 0x4108E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_924 0x4108E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_925 0x4108E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_926 0x4108E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_927 0x4108E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_928 0x4108E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_929 0x4108E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_930 0x4108E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_931 0x4108E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_932 0x4108E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_933 0x4108E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_934 0x4108E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_935 0x4108E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_936 0x4108EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_937 0x4108EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_938 0x4108EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_939 0x4108EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_940 0x4108EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_941 0x4108EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_942 0x4108EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_943 0x4108EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_944 0x4108EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_945 0x4108EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_946 0x4108EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_947 0x4108ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_948 0x4108ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_949 0x4108ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_950 0x4108ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_951 0x4108EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_952 0x4108EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_953 0x4108EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_954 0x4108EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_955 0x4108EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_956 0x4108EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_957 0x4108EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_958 0x4108EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_959 0x4108EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_960 0x4108F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_961 0x4108F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_962 0x4108F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_963 0x4108F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_964 0x4108F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_965 0x4108F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_966 0x4108F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_967 0x4108F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_968 0x4108F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_969 0x4108F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_970 0x4108F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_971 0x4108F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_972 0x4108F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_973 0x4108F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_974 0x4108F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_975 0x4108F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_976 0x4108F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_977 0x4108F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_978 0x4108F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_979 0x4108F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_980 0x4108F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_981 0x4108F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_982 0x4108F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_983 0x4108F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_984 0x4108F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_985 0x4108F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_986 0x4108F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_987 0x4108F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_988 0x4108F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_989 0x4108F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_990 0x4108F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_991 0x4108F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_992 0x4108F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_993 0x4108F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_994 0x4108F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_995 0x4108F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_996 0x4108F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_997 0x4108F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_998 0x4108F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_999 0x4108F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1000 0x4108FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1001 0x4108FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1002 0x4108FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1003 0x4108FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1004 0x4108FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1005 0x4108FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1006 0x4108FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1007 0x4108FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1008 0x4108FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1009 0x4108FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1010 0x4108FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1011 0x4108FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1012 0x4108FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1013 0x4108FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1014 0x4108FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1015 0x4108FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1016 0x4108FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1017 0x4108FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1018 0x4108FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1019 0x4108FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1020 0x4108FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1021 0x4108FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1022 0x4108FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1023 0x4108FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1024 0x4109000 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1025 0x4109004 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1026 0x4109008 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1027 0x410900C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1028 0x4109010 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1029 0x4109014 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1030 0x4109018 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1031 0x410901C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1032 0x4109020 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1033 0x4109024 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1034 0x4109028 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1035 0x410902C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1036 0x4109030 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1037 0x4109034 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1038 0x4109038 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1039 0x410903C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1040 0x4109040 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1041 0x4109044 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1042 0x4109048 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1043 0x410904C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1044 0x4109050 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1045 0x4109054 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1046 0x4109058 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1047 0x410905C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1048 0x4109060 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1049 0x4109064 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1050 0x4109068 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1051 0x410906C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1052 0x4109070 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1053 0x4109074 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1054 0x4109078 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1055 0x410907C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1056 0x4109080 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1057 0x4109084 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1058 0x4109088 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1059 0x410908C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1060 0x4109090 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1061 0x4109094 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1062 0x4109098 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1063 0x410909C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1064 0x41090A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1065 0x41090A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1066 0x41090A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1067 0x41090AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1068 0x41090B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1069 0x41090B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1070 0x41090B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1071 0x41090BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1072 0x41090C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1073 0x41090C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1074 0x41090C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1075 0x41090CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1076 0x41090D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1077 0x41090D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1078 0x41090D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1079 0x41090DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1080 0x41090E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1081 0x41090E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1082 0x41090E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1083 0x41090EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1084 0x41090F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1085 0x41090F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1086 0x41090F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1087 0x41090FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1088 0x4109100 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1089 0x4109104 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1090 0x4109108 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1091 0x410910C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1092 0x4109110 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1093 0x4109114 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1094 0x4109118 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1095 0x410911C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1096 0x4109120 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1097 0x4109124 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1098 0x4109128 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1099 0x410912C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1100 0x4109130 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1101 0x4109134 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1102 0x4109138 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1103 0x410913C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1104 0x4109140 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1105 0x4109144 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1106 0x4109148 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1107 0x410914C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1108 0x4109150 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1109 0x4109154 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1110 0x4109158 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1111 0x410915C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1112 0x4109160 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1113 0x4109164 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1114 0x4109168 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1115 0x410916C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1116 0x4109170 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1117 0x4109174 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1118 0x4109178 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1119 0x410917C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1120 0x4109180 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1121 0x4109184 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1122 0x4109188 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1123 0x410918C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1124 0x4109190 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1125 0x4109194 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1126 0x4109198 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1127 0x410919C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1128 0x41091A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1129 0x41091A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1130 0x41091A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1131 0x41091AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1132 0x41091B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1133 0x41091B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1134 0x41091B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1135 0x41091BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1136 0x41091C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1137 0x41091C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1138 0x41091C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1139 0x41091CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1140 0x41091D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1141 0x41091D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1142 0x41091D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1143 0x41091DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1144 0x41091E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1145 0x41091E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1146 0x41091E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1147 0x41091EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1148 0x41091F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1149 0x41091F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1150 0x41091F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1151 0x41091FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1152 0x4109200 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1153 0x4109204 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1154 0x4109208 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1155 0x410920C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1156 0x4109210 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1157 0x4109214 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1158 0x4109218 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1159 0x410921C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1160 0x4109220 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1161 0x4109224 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1162 0x4109228 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1163 0x410922C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1164 0x4109230 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1165 0x4109234 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1166 0x4109238 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1167 0x410923C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1168 0x4109240 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1169 0x4109244 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1170 0x4109248 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1171 0x410924C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1172 0x4109250 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1173 0x4109254 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1174 0x4109258 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1175 0x410925C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1176 0x4109260 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1177 0x4109264 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1178 0x4109268 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1179 0x410926C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1180 0x4109270 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1181 0x4109274 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1182 0x4109278 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1183 0x410927C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1184 0x4109280 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1185 0x4109284 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1186 0x4109288 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1187 0x410928C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1188 0x4109290 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1189 0x4109294 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1190 0x4109298 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1191 0x410929C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1192 0x41092A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1193 0x41092A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1194 0x41092A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1195 0x41092AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1196 0x41092B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1197 0x41092B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1198 0x41092B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1199 0x41092BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1200 0x41092C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1201 0x41092C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1202 0x41092C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1203 0x41092CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1204 0x41092D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1205 0x41092D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1206 0x41092D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1207 0x41092DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1208 0x41092E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1209 0x41092E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1210 0x41092E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1211 0x41092EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1212 0x41092F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1213 0x41092F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1214 0x41092F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1215 0x41092FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1216 0x4109300 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1217 0x4109304 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1218 0x4109308 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1219 0x410930C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1220 0x4109310 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1221 0x4109314 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1222 0x4109318 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1223 0x410931C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1224 0x4109320 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1225 0x4109324 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1226 0x4109328 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1227 0x410932C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1228 0x4109330 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1229 0x4109334 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1230 0x4109338 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1231 0x410933C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1232 0x4109340 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1233 0x4109344 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1234 0x4109348 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1235 0x410934C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1236 0x4109350 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1237 0x4109354 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1238 0x4109358 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1239 0x410935C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1240 0x4109360 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1241 0x4109364 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1242 0x4109368 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1243 0x410936C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1244 0x4109370 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1245 0x4109374 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1246 0x4109378 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1247 0x410937C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1248 0x4109380 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1249 0x4109384 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1250 0x4109388 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1251 0x410938C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1252 0x4109390 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1253 0x4109394 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1254 0x4109398 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1255 0x410939C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1256 0x41093A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1257 0x41093A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1258 0x41093A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1259 0x41093AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1260 0x41093B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1261 0x41093B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1262 0x41093B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1263 0x41093BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1264 0x41093C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1265 0x41093C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1266 0x41093C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1267 0x41093CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1268 0x41093D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1269 0x41093D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1270 0x41093D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1271 0x41093DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1272 0x41093E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1273 0x41093E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1274 0x41093E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1275 0x41093EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1276 0x41093F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1277 0x41093F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1278 0x41093F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1279 0x41093FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1280 0x4109400 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1281 0x4109404 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1282 0x4109408 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1283 0x410940C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1284 0x4109410 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1285 0x4109414 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1286 0x4109418 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1287 0x410941C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1288 0x4109420 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1289 0x4109424 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1290 0x4109428 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1291 0x410942C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1292 0x4109430 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1293 0x4109434 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1294 0x4109438 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1295 0x410943C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1296 0x4109440 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1297 0x4109444 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1298 0x4109448 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1299 0x410944C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1300 0x4109450 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1301 0x4109454 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1302 0x4109458 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1303 0x410945C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1304 0x4109460 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1305 0x4109464 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1306 0x4109468 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1307 0x410946C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1308 0x4109470 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1309 0x4109474 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1310 0x4109478 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1311 0x410947C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1312 0x4109480 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1313 0x4109484 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1314 0x4109488 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1315 0x410948C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1316 0x4109490 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1317 0x4109494 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1318 0x4109498 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1319 0x410949C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1320 0x41094A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1321 0x41094A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1322 0x41094A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1323 0x41094AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1324 0x41094B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1325 0x41094B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1326 0x41094B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1327 0x41094BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1328 0x41094C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1329 0x41094C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1330 0x41094C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1331 0x41094CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1332 0x41094D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1333 0x41094D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1334 0x41094D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1335 0x41094DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1336 0x41094E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1337 0x41094E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1338 0x41094E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1339 0x41094EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1340 0x41094F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1341 0x41094F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1342 0x41094F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1343 0x41094FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1344 0x4109500 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1345 0x4109504 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1346 0x4109508 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1347 0x410950C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1348 0x4109510 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1349 0x4109514 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1350 0x4109518 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1351 0x410951C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1352 0x4109520 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1353 0x4109524 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1354 0x4109528 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1355 0x410952C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1356 0x4109530 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1357 0x4109534 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1358 0x4109538 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1359 0x410953C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1360 0x4109540 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1361 0x4109544 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1362 0x4109548 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1363 0x410954C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1364 0x4109550 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1365 0x4109554 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1366 0x4109558 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1367 0x410955C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1368 0x4109560 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1369 0x4109564 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1370 0x4109568 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1371 0x410956C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1372 0x4109570 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1373 0x4109574 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1374 0x4109578 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1375 0x410957C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1376 0x4109580 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1377 0x4109584 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1378 0x4109588 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1379 0x410958C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1380 0x4109590 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1381 0x4109594 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1382 0x4109598 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1383 0x410959C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1384 0x41095A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1385 0x41095A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1386 0x41095A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1387 0x41095AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1388 0x41095B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1389 0x41095B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1390 0x41095B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1391 0x41095BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1392 0x41095C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1393 0x41095C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1394 0x41095C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1395 0x41095CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1396 0x41095D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1397 0x41095D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1398 0x41095D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1399 0x41095DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1400 0x41095E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1401 0x41095E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1402 0x41095E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1403 0x41095EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1404 0x41095F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1405 0x41095F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1406 0x41095F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1407 0x41095FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1408 0x4109600 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1409 0x4109604 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1410 0x4109608 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1411 0x410960C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1412 0x4109610 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1413 0x4109614 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1414 0x4109618 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1415 0x410961C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1416 0x4109620 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1417 0x4109624 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1418 0x4109628 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1419 0x410962C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1420 0x4109630 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1421 0x4109634 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1422 0x4109638 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1423 0x410963C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1424 0x4109640 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1425 0x4109644 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1426 0x4109648 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1427 0x410964C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1428 0x4109650 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1429 0x4109654 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1430 0x4109658 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1431 0x410965C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1432 0x4109660 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1433 0x4109664 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1434 0x4109668 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1435 0x410966C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1436 0x4109670 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1437 0x4109674 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1438 0x4109678 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1439 0x410967C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1440 0x4109680 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1441 0x4109684 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1442 0x4109688 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1443 0x410968C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1444 0x4109690 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1445 0x4109694 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1446 0x4109698 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1447 0x410969C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1448 0x41096A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1449 0x41096A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1450 0x41096A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1451 0x41096AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1452 0x41096B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1453 0x41096B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1454 0x41096B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1455 0x41096BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1456 0x41096C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1457 0x41096C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1458 0x41096C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1459 0x41096CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1460 0x41096D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1461 0x41096D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1462 0x41096D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1463 0x41096DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1464 0x41096E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1465 0x41096E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1466 0x41096E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1467 0x41096EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1468 0x41096F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1469 0x41096F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1470 0x41096F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1471 0x41096FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1472 0x4109700 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1473 0x4109704 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1474 0x4109708 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1475 0x410970C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1476 0x4109710 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1477 0x4109714 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1478 0x4109718 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1479 0x410971C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1480 0x4109720 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1481 0x4109724 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1482 0x4109728 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1483 0x410972C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1484 0x4109730 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1485 0x4109734 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1486 0x4109738 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1487 0x410973C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1488 0x4109740 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1489 0x4109744 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1490 0x4109748 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1491 0x410974C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1492 0x4109750 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1493 0x4109754 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1494 0x4109758 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1495 0x410975C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1496 0x4109760 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1497 0x4109764 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1498 0x4109768 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1499 0x410976C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1500 0x4109770 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1501 0x4109774 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1502 0x4109778 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1503 0x410977C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1504 0x4109780 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1505 0x4109784 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1506 0x4109788 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1507 0x410978C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1508 0x4109790 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1509 0x4109794 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1510 0x4109798 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1511 0x410979C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1512 0x41097A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1513 0x41097A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1514 0x41097A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1515 0x41097AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1516 0x41097B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1517 0x41097B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1518 0x41097B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1519 0x41097BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1520 0x41097C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1521 0x41097C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1522 0x41097C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1523 0x41097CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1524 0x41097D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1525 0x41097D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1526 0x41097D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1527 0x41097DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1528 0x41097E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1529 0x41097E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1530 0x41097E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1531 0x41097EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1532 0x41097F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1533 0x41097F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1534 0x41097F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1535 0x41097FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1536 0x4109800 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1537 0x4109804 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1538 0x4109808 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1539 0x410980C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1540 0x4109810 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1541 0x4109814 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1542 0x4109818 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1543 0x410981C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1544 0x4109820 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1545 0x4109824 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1546 0x4109828 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1547 0x410982C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1548 0x4109830 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1549 0x4109834 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1550 0x4109838 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1551 0x410983C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1552 0x4109840 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1553 0x4109844 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1554 0x4109848 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1555 0x410984C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1556 0x4109850 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1557 0x4109854 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1558 0x4109858 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1559 0x410985C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1560 0x4109860 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1561 0x4109864 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1562 0x4109868 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1563 0x410986C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1564 0x4109870 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1565 0x4109874 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1566 0x4109878 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1567 0x410987C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1568 0x4109880 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1569 0x4109884 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1570 0x4109888 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1571 0x410988C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1572 0x4109890 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1573 0x4109894 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1574 0x4109898 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1575 0x410989C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1576 0x41098A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1577 0x41098A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1578 0x41098A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1579 0x41098AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1580 0x41098B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1581 0x41098B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1582 0x41098B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1583 0x41098BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1584 0x41098C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1585 0x41098C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1586 0x41098C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1587 0x41098CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1588 0x41098D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1589 0x41098D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1590 0x41098D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1591 0x41098DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1592 0x41098E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1593 0x41098E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1594 0x41098E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1595 0x41098EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1596 0x41098F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1597 0x41098F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1598 0x41098F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1599 0x41098FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1600 0x4109900 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1601 0x4109904 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1602 0x4109908 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1603 0x410990C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1604 0x4109910 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1605 0x4109914 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1606 0x4109918 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1607 0x410991C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1608 0x4109920 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1609 0x4109924 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1610 0x4109928 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1611 0x410992C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1612 0x4109930 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1613 0x4109934 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1614 0x4109938 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1615 0x410993C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1616 0x4109940 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1617 0x4109944 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1618 0x4109948 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1619 0x410994C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1620 0x4109950 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1621 0x4109954 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1622 0x4109958 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1623 0x410995C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1624 0x4109960 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1625 0x4109964 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1626 0x4109968 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1627 0x410996C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1628 0x4109970 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1629 0x4109974 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1630 0x4109978 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1631 0x410997C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1632 0x4109980 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1633 0x4109984 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1634 0x4109988 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1635 0x410998C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1636 0x4109990 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1637 0x4109994 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1638 0x4109998 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1639 0x410999C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1640 0x41099A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1641 0x41099A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1642 0x41099A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1643 0x41099AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1644 0x41099B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1645 0x41099B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1646 0x41099B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1647 0x41099BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1648 0x41099C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1649 0x41099C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1650 0x41099C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1651 0x41099CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1652 0x41099D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1653 0x41099D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1654 0x41099D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1655 0x41099DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1656 0x41099E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1657 0x41099E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1658 0x41099E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1659 0x41099EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1660 0x41099F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1661 0x41099F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1662 0x41099F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1663 0x41099FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1664 0x4109A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1665 0x4109A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1666 0x4109A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1667 0x4109A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1668 0x4109A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1669 0x4109A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1670 0x4109A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1671 0x4109A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1672 0x4109A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1673 0x4109A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1674 0x4109A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1675 0x4109A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1676 0x4109A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1677 0x4109A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1678 0x4109A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1679 0x4109A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1680 0x4109A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1681 0x4109A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1682 0x4109A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1683 0x4109A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1684 0x4109A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1685 0x4109A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1686 0x4109A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1687 0x4109A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1688 0x4109A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1689 0x4109A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1690 0x4109A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1691 0x4109A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1692 0x4109A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1693 0x4109A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1694 0x4109A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1695 0x4109A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1696 0x4109A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1697 0x4109A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1698 0x4109A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1699 0x4109A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1700 0x4109A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1701 0x4109A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1702 0x4109A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1703 0x4109A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1704 0x4109AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1705 0x4109AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1706 0x4109AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1707 0x4109AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1708 0x4109AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1709 0x4109AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1710 0x4109AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1711 0x4109ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1712 0x4109AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1713 0x4109AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1714 0x4109AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1715 0x4109ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1716 0x4109AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1717 0x4109AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1718 0x4109AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1719 0x4109ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1720 0x4109AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1721 0x4109AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1722 0x4109AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1723 0x4109AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1724 0x4109AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1725 0x4109AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1726 0x4109AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1727 0x4109AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1728 0x4109B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1729 0x4109B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1730 0x4109B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1731 0x4109B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1732 0x4109B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1733 0x4109B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1734 0x4109B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1735 0x4109B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1736 0x4109B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1737 0x4109B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1738 0x4109B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1739 0x4109B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1740 0x4109B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1741 0x4109B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1742 0x4109B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1743 0x4109B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1744 0x4109B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1745 0x4109B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1746 0x4109B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1747 0x4109B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1748 0x4109B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1749 0x4109B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1750 0x4109B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1751 0x4109B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1752 0x4109B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1753 0x4109B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1754 0x4109B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1755 0x4109B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1756 0x4109B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1757 0x4109B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1758 0x4109B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1759 0x4109B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1760 0x4109B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1761 0x4109B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1762 0x4109B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1763 0x4109B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1764 0x4109B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1765 0x4109B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1766 0x4109B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1767 0x4109B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1768 0x4109BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1769 0x4109BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1770 0x4109BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1771 0x4109BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1772 0x4109BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1773 0x4109BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1774 0x4109BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1775 0x4109BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1776 0x4109BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1777 0x4109BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1778 0x4109BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1779 0x4109BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1780 0x4109BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1781 0x4109BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1782 0x4109BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1783 0x4109BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1784 0x4109BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1785 0x4109BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1786 0x4109BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1787 0x4109BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1788 0x4109BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1789 0x4109BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1790 0x4109BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1791 0x4109BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1792 0x4109C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1793 0x4109C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1794 0x4109C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1795 0x4109C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1796 0x4109C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1797 0x4109C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1798 0x4109C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1799 0x4109C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1800 0x4109C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1801 0x4109C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1802 0x4109C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1803 0x4109C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1804 0x4109C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1805 0x4109C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1806 0x4109C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1807 0x4109C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1808 0x4109C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1809 0x4109C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1810 0x4109C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1811 0x4109C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1812 0x4109C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1813 0x4109C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1814 0x4109C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1815 0x4109C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1816 0x4109C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1817 0x4109C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1818 0x4109C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1819 0x4109C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1820 0x4109C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1821 0x4109C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1822 0x4109C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1823 0x4109C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1824 0x4109C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1825 0x4109C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1826 0x4109C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1827 0x4109C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1828 0x4109C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1829 0x4109C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1830 0x4109C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1831 0x4109C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1832 0x4109CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1833 0x4109CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1834 0x4109CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1835 0x4109CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1836 0x4109CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1837 0x4109CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1838 0x4109CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1839 0x4109CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1840 0x4109CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1841 0x4109CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1842 0x4109CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1843 0x4109CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1844 0x4109CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1845 0x4109CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1846 0x4109CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1847 0x4109CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1848 0x4109CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1849 0x4109CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1850 0x4109CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1851 0x4109CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1852 0x4109CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1853 0x4109CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1854 0x4109CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1855 0x4109CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1856 0x4109D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1857 0x4109D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1858 0x4109D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1859 0x4109D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1860 0x4109D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1861 0x4109D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1862 0x4109D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1863 0x4109D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1864 0x4109D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1865 0x4109D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1866 0x4109D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1867 0x4109D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1868 0x4109D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1869 0x4109D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1870 0x4109D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1871 0x4109D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1872 0x4109D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1873 0x4109D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1874 0x4109D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1875 0x4109D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1876 0x4109D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1877 0x4109D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1878 0x4109D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1879 0x4109D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1880 0x4109D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1881 0x4109D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1882 0x4109D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1883 0x4109D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1884 0x4109D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1885 0x4109D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1886 0x4109D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1887 0x4109D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1888 0x4109D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1889 0x4109D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1890 0x4109D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1891 0x4109D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1892 0x4109D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1893 0x4109D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1894 0x4109D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1895 0x4109D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1896 0x4109DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1897 0x4109DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1898 0x4109DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1899 0x4109DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1900 0x4109DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1901 0x4109DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1902 0x4109DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1903 0x4109DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1904 0x4109DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1905 0x4109DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1906 0x4109DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1907 0x4109DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1908 0x4109DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1909 0x4109DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1910 0x4109DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1911 0x4109DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1912 0x4109DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1913 0x4109DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1914 0x4109DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1915 0x4109DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1916 0x4109DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1917 0x4109DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1918 0x4109DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1919 0x4109DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1920 0x4109E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1921 0x4109E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1922 0x4109E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1923 0x4109E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1924 0x4109E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1925 0x4109E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1926 0x4109E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1927 0x4109E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1928 0x4109E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1929 0x4109E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1930 0x4109E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1931 0x4109E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1932 0x4109E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1933 0x4109E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1934 0x4109E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1935 0x4109E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1936 0x4109E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1937 0x4109E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1938 0x4109E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1939 0x4109E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1940 0x4109E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1941 0x4109E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1942 0x4109E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1943 0x4109E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1944 0x4109E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1945 0x4109E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1946 0x4109E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1947 0x4109E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1948 0x4109E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1949 0x4109E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1950 0x4109E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1951 0x4109E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1952 0x4109E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1953 0x4109E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1954 0x4109E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1955 0x4109E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1956 0x4109E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1957 0x4109E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1958 0x4109E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1959 0x4109E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1960 0x4109EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1961 0x4109EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1962 0x4109EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1963 0x4109EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1964 0x4109EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1965 0x4109EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1966 0x4109EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1967 0x4109EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1968 0x4109EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1969 0x4109EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1970 0x4109EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1971 0x4109ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1972 0x4109ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1973 0x4109ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1974 0x4109ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1975 0x4109EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1976 0x4109EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1977 0x4109EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1978 0x4109EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1979 0x4109EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1980 0x4109EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1981 0x4109EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1982 0x4109EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1983 0x4109EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1984 0x4109F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1985 0x4109F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1986 0x4109F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1987 0x4109F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1988 0x4109F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1989 0x4109F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1990 0x4109F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1991 0x4109F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1992 0x4109F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1993 0x4109F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1994 0x4109F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1995 0x4109F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1996 0x4109F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1997 0x4109F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1998 0x4109F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1999 0x4109F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2000 0x4109F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2001 0x4109F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2002 0x4109F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2003 0x4109F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2004 0x4109F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2005 0x4109F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2006 0x4109F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2007 0x4109F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2008 0x4109F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2009 0x4109F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2010 0x4109F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2011 0x4109F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2012 0x4109F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2013 0x4109F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2014 0x4109F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2015 0x4109F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2016 0x4109F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2017 0x4109F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2018 0x4109F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2019 0x4109F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2020 0x4109F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2021 0x4109F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2022 0x4109F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2023 0x4109F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2024 0x4109FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2025 0x4109FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2026 0x4109FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2027 0x4109FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2028 0x4109FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2029 0x4109FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2030 0x4109FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2031 0x4109FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2032 0x4109FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2033 0x4109FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2034 0x4109FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2035 0x4109FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2036 0x4109FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2037 0x4109FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2038 0x4109FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2039 0x4109FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2040 0x4109FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2041 0x4109FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2042 0x4109FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2043 0x4109FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2044 0x4109FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2045 0x4109FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2046 0x4109FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2047 0x4109FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 0x410A000 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1 0x410A004 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2 0x410A008 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_3 0x410A00C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_4 0x410A010 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_5 0x410A014 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_6 0x410A018 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_7 0x410A01C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_8 0x410A020 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_9 0x410A024 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_10 0x410A028 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_11 0x410A02C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_12 0x410A030 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_13 0x410A034 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_14 0x410A038 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_15 0x410A03C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_16 0x410A040 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_17 0x410A044 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_18 0x410A048 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_19 0x410A04C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_20 0x410A050 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_21 0x410A054 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_22 0x410A058 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_23 0x410A05C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_24 0x410A060 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_25 0x410A064 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_26 0x410A068 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_27 0x410A06C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_28 0x410A070 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_29 0x410A074 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_30 0x410A078 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_31 0x410A07C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_32 0x410A080 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_33 0x410A084 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_34 0x410A088 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_35 0x410A08C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_36 0x410A090 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_37 0x410A094 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_38 0x410A098 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_39 0x410A09C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_40 0x410A0A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_41 0x410A0A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_42 0x410A0A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_43 0x410A0AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_44 0x410A0B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_45 0x410A0B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_46 0x410A0B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_47 0x410A0BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_48 0x410A0C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_49 0x410A0C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_50 0x410A0C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_51 0x410A0CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_52 0x410A0D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_53 0x410A0D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_54 0x410A0D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_55 0x410A0DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_56 0x410A0E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_57 0x410A0E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_58 0x410A0E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_59 0x410A0EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_60 0x410A0F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_61 0x410A0F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_62 0x410A0F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_63 0x410A0FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_64 0x410A100 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_65 0x410A104 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_66 0x410A108 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_67 0x410A10C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_68 0x410A110 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_69 0x410A114 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_70 0x410A118 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_71 0x410A11C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_72 0x410A120 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_73 0x410A124 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_74 0x410A128 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_75 0x410A12C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_76 0x410A130 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_77 0x410A134 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_78 0x410A138 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_79 0x410A13C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_80 0x410A140 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_81 0x410A144 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_82 0x410A148 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_83 0x410A14C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_84 0x410A150 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_85 0x410A154 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_86 0x410A158 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_87 0x410A15C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_88 0x410A160 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_89 0x410A164 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_90 0x410A168 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_91 0x410A16C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_92 0x410A170 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_93 0x410A174 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_94 0x410A178 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_95 0x410A17C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_96 0x410A180 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_97 0x410A184 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_98 0x410A188 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_99 0x410A18C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_100 0x410A190 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_101 0x410A194 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_102 0x410A198 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_103 0x410A19C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_104 0x410A1A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_105 0x410A1A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_106 0x410A1A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_107 0x410A1AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_108 0x410A1B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_109 0x410A1B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_110 0x410A1B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_111 0x410A1BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_112 0x410A1C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_113 0x410A1C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_114 0x410A1C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_115 0x410A1CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_116 0x410A1D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_117 0x410A1D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_118 0x410A1D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_119 0x410A1DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_120 0x410A1E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_121 0x410A1E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_122 0x410A1E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_123 0x410A1EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_124 0x410A1F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_125 0x410A1F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_126 0x410A1F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_127 0x410A1FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_128 0x410A200 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_129 0x410A204 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_130 0x410A208 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_131 0x410A20C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_132 0x410A210 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_133 0x410A214 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_134 0x410A218 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_135 0x410A21C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_136 0x410A220 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_137 0x410A224 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_138 0x410A228 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_139 0x410A22C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_140 0x410A230 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_141 0x410A234 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_142 0x410A238 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_143 0x410A23C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_144 0x410A240 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_145 0x410A244 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_146 0x410A248 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_147 0x410A24C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_148 0x410A250 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_149 0x410A254 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_150 0x410A258 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_151 0x410A25C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_152 0x410A260 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_153 0x410A264 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_154 0x410A268 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_155 0x410A26C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_156 0x410A270 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_157 0x410A274 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_158 0x410A278 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_159 0x410A27C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_160 0x410A280 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_161 0x410A284 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_162 0x410A288 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_163 0x410A28C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_164 0x410A290 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_165 0x410A294 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_166 0x410A298 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_167 0x410A29C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_168 0x410A2A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_169 0x410A2A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_170 0x410A2A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_171 0x410A2AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_172 0x410A2B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_173 0x410A2B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_174 0x410A2B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_175 0x410A2BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_176 0x410A2C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_177 0x410A2C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_178 0x410A2C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_179 0x410A2CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_180 0x410A2D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_181 0x410A2D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_182 0x410A2D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_183 0x410A2DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_184 0x410A2E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_185 0x410A2E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_186 0x410A2E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_187 0x410A2EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_188 0x410A2F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_189 0x410A2F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_190 0x410A2F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_191 0x410A2FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_192 0x410A300 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_193 0x410A304 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_194 0x410A308 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_195 0x410A30C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_196 0x410A310 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_197 0x410A314 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_198 0x410A318 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_199 0x410A31C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_200 0x410A320 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_201 0x410A324 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_202 0x410A328 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_203 0x410A32C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_204 0x410A330 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_205 0x410A334 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_206 0x410A338 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_207 0x410A33C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_208 0x410A340 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_209 0x410A344 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_210 0x410A348 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_211 0x410A34C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_212 0x410A350 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_213 0x410A354 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_214 0x410A358 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_215 0x410A35C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_216 0x410A360 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_217 0x410A364 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_218 0x410A368 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_219 0x410A36C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_220 0x410A370 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_221 0x410A374 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_222 0x410A378 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_223 0x410A37C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_224 0x410A380 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_225 0x410A384 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_226 0x410A388 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_227 0x410A38C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_228 0x410A390 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_229 0x410A394 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_230 0x410A398 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_231 0x410A39C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_232 0x410A3A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_233 0x410A3A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_234 0x410A3A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_235 0x410A3AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_236 0x410A3B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_237 0x410A3B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_238 0x410A3B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_239 0x410A3BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_240 0x410A3C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_241 0x410A3C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_242 0x410A3C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_243 0x410A3CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_244 0x410A3D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_245 0x410A3D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_246 0x410A3D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_247 0x410A3DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_248 0x410A3E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_249 0x410A3E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_250 0x410A3E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_251 0x410A3EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_252 0x410A3F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_253 0x410A3F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_254 0x410A3F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_255 0x410A3FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_256 0x410A400 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_257 0x410A404 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_258 0x410A408 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_259 0x410A40C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_260 0x410A410 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_261 0x410A414 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_262 0x410A418 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_263 0x410A41C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_264 0x410A420 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_265 0x410A424 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_266 0x410A428 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_267 0x410A42C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_268 0x410A430 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_269 0x410A434 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_270 0x410A438 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_271 0x410A43C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_272 0x410A440 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_273 0x410A444 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_274 0x410A448 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_275 0x410A44C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_276 0x410A450 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_277 0x410A454 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_278 0x410A458 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_279 0x410A45C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_280 0x410A460 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_281 0x410A464 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_282 0x410A468 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_283 0x410A46C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_284 0x410A470 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_285 0x410A474 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_286 0x410A478 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_287 0x410A47C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_288 0x410A480 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_289 0x410A484 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_290 0x410A488 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_291 0x410A48C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_292 0x410A490 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_293 0x410A494 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_294 0x410A498 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_295 0x410A49C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_296 0x410A4A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_297 0x410A4A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_298 0x410A4A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_299 0x410A4AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_300 0x410A4B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_301 0x410A4B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_302 0x410A4B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_303 0x410A4BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_304 0x410A4C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_305 0x410A4C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_306 0x410A4C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_307 0x410A4CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_308 0x410A4D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_309 0x410A4D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_310 0x410A4D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_311 0x410A4DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_312 0x410A4E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_313 0x410A4E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_314 0x410A4E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_315 0x410A4EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_316 0x410A4F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_317 0x410A4F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_318 0x410A4F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_319 0x410A4FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_320 0x410A500 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_321 0x410A504 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_322 0x410A508 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_323 0x410A50C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_324 0x410A510 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_325 0x410A514 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_326 0x410A518 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_327 0x410A51C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_328 0x410A520 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_329 0x410A524 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_330 0x410A528 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_331 0x410A52C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_332 0x410A530 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_333 0x410A534 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_334 0x410A538 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_335 0x410A53C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_336 0x410A540 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_337 0x410A544 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_338 0x410A548 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_339 0x410A54C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_340 0x410A550 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_341 0x410A554 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_342 0x410A558 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_343 0x410A55C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_344 0x410A560 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_345 0x410A564 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_346 0x410A568 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_347 0x410A56C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_348 0x410A570 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_349 0x410A574 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_350 0x410A578 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_351 0x410A57C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_352 0x410A580 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_353 0x410A584 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_354 0x410A588 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_355 0x410A58C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_356 0x410A590 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_357 0x410A594 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_358 0x410A598 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_359 0x410A59C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_360 0x410A5A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_361 0x410A5A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_362 0x410A5A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_363 0x410A5AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_364 0x410A5B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_365 0x410A5B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_366 0x410A5B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_367 0x410A5BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_368 0x410A5C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_369 0x410A5C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_370 0x410A5C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_371 0x410A5CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_372 0x410A5D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_373 0x410A5D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_374 0x410A5D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_375 0x410A5DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_376 0x410A5E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_377 0x410A5E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_378 0x410A5E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_379 0x410A5EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_380 0x410A5F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_381 0x410A5F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_382 0x410A5F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_383 0x410A5FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_384 0x410A600 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_385 0x410A604 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_386 0x410A608 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_387 0x410A60C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_388 0x410A610 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_389 0x410A614 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_390 0x410A618 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_391 0x410A61C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_392 0x410A620 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_393 0x410A624 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_394 0x410A628 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_395 0x410A62C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_396 0x410A630 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_397 0x410A634 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_398 0x410A638 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_399 0x410A63C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_400 0x410A640 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_401 0x410A644 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_402 0x410A648 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_403 0x410A64C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_404 0x410A650 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_405 0x410A654 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_406 0x410A658 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_407 0x410A65C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_408 0x410A660 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_409 0x410A664 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_410 0x410A668 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_411 0x410A66C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_412 0x410A670 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_413 0x410A674 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_414 0x410A678 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_415 0x410A67C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_416 0x410A680 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_417 0x410A684 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_418 0x410A688 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_419 0x410A68C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_420 0x410A690 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_421 0x410A694 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_422 0x410A698 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_423 0x410A69C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_424 0x410A6A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_425 0x410A6A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_426 0x410A6A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_427 0x410A6AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_428 0x410A6B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_429 0x410A6B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_430 0x410A6B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_431 0x410A6BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_432 0x410A6C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_433 0x410A6C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_434 0x410A6C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_435 0x410A6CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_436 0x410A6D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_437 0x410A6D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_438 0x410A6D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_439 0x410A6DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_440 0x410A6E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_441 0x410A6E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_442 0x410A6E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_443 0x410A6EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_444 0x410A6F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_445 0x410A6F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_446 0x410A6F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_447 0x410A6FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_448 0x410A700 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_449 0x410A704 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_450 0x410A708 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_451 0x410A70C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_452 0x410A710 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_453 0x410A714 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_454 0x410A718 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_455 0x410A71C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_456 0x410A720 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_457 0x410A724 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_458 0x410A728 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_459 0x410A72C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_460 0x410A730 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_461 0x410A734 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_462 0x410A738 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_463 0x410A73C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_464 0x410A740 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_465 0x410A744 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_466 0x410A748 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_467 0x410A74C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_468 0x410A750 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_469 0x410A754 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_470 0x410A758 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_471 0x410A75C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_472 0x410A760 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_473 0x410A764 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_474 0x410A768 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_475 0x410A76C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_476 0x410A770 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_477 0x410A774 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_478 0x410A778 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_479 0x410A77C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_480 0x410A780 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_481 0x410A784 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_482 0x410A788 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_483 0x410A78C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_484 0x410A790 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_485 0x410A794 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_486 0x410A798 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_487 0x410A79C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_488 0x410A7A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_489 0x410A7A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_490 0x410A7A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_491 0x410A7AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_492 0x410A7B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_493 0x410A7B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_494 0x410A7B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_495 0x410A7BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_496 0x410A7C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_497 0x410A7C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_498 0x410A7C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_499 0x410A7CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_500 0x410A7D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_501 0x410A7D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_502 0x410A7D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_503 0x410A7DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_504 0x410A7E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_505 0x410A7E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_506 0x410A7E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_507 0x410A7EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_508 0x410A7F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_509 0x410A7F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_510 0x410A7F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_511 0x410A7FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_512 0x410A800 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_513 0x410A804 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_514 0x410A808 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_515 0x410A80C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_516 0x410A810 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_517 0x410A814 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_518 0x410A818 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_519 0x410A81C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_520 0x410A820 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_521 0x410A824 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_522 0x410A828 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_523 0x410A82C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_524 0x410A830 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_525 0x410A834 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_526 0x410A838 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_527 0x410A83C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_528 0x410A840 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_529 0x410A844 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_530 0x410A848 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_531 0x410A84C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_532 0x410A850 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_533 0x410A854 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_534 0x410A858 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_535 0x410A85C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_536 0x410A860 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_537 0x410A864 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_538 0x410A868 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_539 0x410A86C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_540 0x410A870 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_541 0x410A874 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_542 0x410A878 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_543 0x410A87C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_544 0x410A880 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_545 0x410A884 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_546 0x410A888 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_547 0x410A88C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_548 0x410A890 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_549 0x410A894 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_550 0x410A898 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_551 0x410A89C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_552 0x410A8A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_553 0x410A8A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_554 0x410A8A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_555 0x410A8AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_556 0x410A8B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_557 0x410A8B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_558 0x410A8B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_559 0x410A8BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_560 0x410A8C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_561 0x410A8C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_562 0x410A8C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_563 0x410A8CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_564 0x410A8D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_565 0x410A8D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_566 0x410A8D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_567 0x410A8DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_568 0x410A8E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_569 0x410A8E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_570 0x410A8E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_571 0x410A8EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_572 0x410A8F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_573 0x410A8F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_574 0x410A8F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_575 0x410A8FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_576 0x410A900 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_577 0x410A904 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_578 0x410A908 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_579 0x410A90C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_580 0x410A910 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_581 0x410A914 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_582 0x410A918 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_583 0x410A91C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_584 0x410A920 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_585 0x410A924 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_586 0x410A928 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_587 0x410A92C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_588 0x410A930 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_589 0x410A934 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_590 0x410A938 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_591 0x410A93C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_592 0x410A940 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_593 0x410A944 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_594 0x410A948 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_595 0x410A94C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_596 0x410A950 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_597 0x410A954 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_598 0x410A958 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_599 0x410A95C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_600 0x410A960 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_601 0x410A964 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_602 0x410A968 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_603 0x410A96C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_604 0x410A970 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_605 0x410A974 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_606 0x410A978 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_607 0x410A97C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_608 0x410A980 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_609 0x410A984 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_610 0x410A988 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_611 0x410A98C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_612 0x410A990 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_613 0x410A994 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_614 0x410A998 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_615 0x410A99C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_616 0x410A9A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_617 0x410A9A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_618 0x410A9A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_619 0x410A9AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_620 0x410A9B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_621 0x410A9B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_622 0x410A9B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_623 0x410A9BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_624 0x410A9C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_625 0x410A9C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_626 0x410A9C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_627 0x410A9CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_628 0x410A9D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_629 0x410A9D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_630 0x410A9D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_631 0x410A9DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_632 0x410A9E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_633 0x410A9E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_634 0x410A9E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_635 0x410A9EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_636 0x410A9F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_637 0x410A9F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_638 0x410A9F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_639 0x410A9FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_640 0x410AA00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_641 0x410AA04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_642 0x410AA08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_643 0x410AA0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_644 0x410AA10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_645 0x410AA14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_646 0x410AA18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_647 0x410AA1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_648 0x410AA20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_649 0x410AA24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_650 0x410AA28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_651 0x410AA2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_652 0x410AA30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_653 0x410AA34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_654 0x410AA38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_655 0x410AA3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_656 0x410AA40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_657 0x410AA44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_658 0x410AA48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_659 0x410AA4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_660 0x410AA50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_661 0x410AA54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_662 0x410AA58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_663 0x410AA5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_664 0x410AA60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_665 0x410AA64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_666 0x410AA68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_667 0x410AA6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_668 0x410AA70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_669 0x410AA74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_670 0x410AA78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_671 0x410AA7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_672 0x410AA80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_673 0x410AA84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_674 0x410AA88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_675 0x410AA8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_676 0x410AA90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_677 0x410AA94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_678 0x410AA98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_679 0x410AA9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_680 0x410AAA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_681 0x410AAA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_682 0x410AAA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_683 0x410AAAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_684 0x410AAB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_685 0x410AAB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_686 0x410AAB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_687 0x410AABC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_688 0x410AAC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_689 0x410AAC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_690 0x410AAC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_691 0x410AACC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_692 0x410AAD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_693 0x410AAD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_694 0x410AAD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_695 0x410AADC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_696 0x410AAE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_697 0x410AAE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_698 0x410AAE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_699 0x410AAEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_700 0x410AAF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_701 0x410AAF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_702 0x410AAF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_703 0x410AAFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_704 0x410AB00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_705 0x410AB04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_706 0x410AB08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_707 0x410AB0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_708 0x410AB10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_709 0x410AB14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_710 0x410AB18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_711 0x410AB1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_712 0x410AB20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_713 0x410AB24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_714 0x410AB28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_715 0x410AB2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_716 0x410AB30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_717 0x410AB34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_718 0x410AB38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_719 0x410AB3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_720 0x410AB40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_721 0x410AB44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_722 0x410AB48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_723 0x410AB4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_724 0x410AB50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_725 0x410AB54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_726 0x410AB58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_727 0x410AB5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_728 0x410AB60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_729 0x410AB64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_730 0x410AB68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_731 0x410AB6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_732 0x410AB70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_733 0x410AB74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_734 0x410AB78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_735 0x410AB7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_736 0x410AB80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_737 0x410AB84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_738 0x410AB88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_739 0x410AB8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_740 0x410AB90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_741 0x410AB94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_742 0x410AB98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_743 0x410AB9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_744 0x410ABA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_745 0x410ABA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_746 0x410ABA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_747 0x410ABAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_748 0x410ABB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_749 0x410ABB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_750 0x410ABB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_751 0x410ABBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_752 0x410ABC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_753 0x410ABC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_754 0x410ABC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_755 0x410ABCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_756 0x410ABD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_757 0x410ABD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_758 0x410ABD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_759 0x410ABDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_760 0x410ABE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_761 0x410ABE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_762 0x410ABE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_763 0x410ABEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_764 0x410ABF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_765 0x410ABF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_766 0x410ABF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_767 0x410ABFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_768 0x410AC00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_769 0x410AC04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_770 0x410AC08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_771 0x410AC0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_772 0x410AC10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_773 0x410AC14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_774 0x410AC18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_775 0x410AC1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_776 0x410AC20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_777 0x410AC24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_778 0x410AC28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_779 0x410AC2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_780 0x410AC30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_781 0x410AC34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_782 0x410AC38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_783 0x410AC3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_784 0x410AC40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_785 0x410AC44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_786 0x410AC48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_787 0x410AC4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_788 0x410AC50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_789 0x410AC54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_790 0x410AC58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_791 0x410AC5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_792 0x410AC60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_793 0x410AC64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_794 0x410AC68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_795 0x410AC6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_796 0x410AC70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_797 0x410AC74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_798 0x410AC78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_799 0x410AC7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_800 0x410AC80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_801 0x410AC84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_802 0x410AC88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_803 0x410AC8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_804 0x410AC90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_805 0x410AC94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_806 0x410AC98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_807 0x410AC9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_808 0x410ACA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_809 0x410ACA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_810 0x410ACA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_811 0x410ACAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_812 0x410ACB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_813 0x410ACB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_814 0x410ACB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_815 0x410ACBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_816 0x410ACC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_817 0x410ACC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_818 0x410ACC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_819 0x410ACCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_820 0x410ACD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_821 0x410ACD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_822 0x410ACD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_823 0x410ACDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_824 0x410ACE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_825 0x410ACE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_826 0x410ACE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_827 0x410ACEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_828 0x410ACF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_829 0x410ACF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_830 0x410ACF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_831 0x410ACFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_832 0x410AD00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_833 0x410AD04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_834 0x410AD08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_835 0x410AD0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_836 0x410AD10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_837 0x410AD14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_838 0x410AD18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_839 0x410AD1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_840 0x410AD20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_841 0x410AD24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_842 0x410AD28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_843 0x410AD2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_844 0x410AD30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_845 0x410AD34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_846 0x410AD38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_847 0x410AD3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_848 0x410AD40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_849 0x410AD44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_850 0x410AD48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_851 0x410AD4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_852 0x410AD50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_853 0x410AD54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_854 0x410AD58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_855 0x410AD5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_856 0x410AD60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_857 0x410AD64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_858 0x410AD68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_859 0x410AD6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_860 0x410AD70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_861 0x410AD74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_862 0x410AD78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_863 0x410AD7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_864 0x410AD80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_865 0x410AD84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_866 0x410AD88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_867 0x410AD8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_868 0x410AD90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_869 0x410AD94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_870 0x410AD98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_871 0x410AD9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_872 0x410ADA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_873 0x410ADA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_874 0x410ADA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_875 0x410ADAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_876 0x410ADB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_877 0x410ADB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_878 0x410ADB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_879 0x410ADBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_880 0x410ADC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_881 0x410ADC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_882 0x410ADC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_883 0x410ADCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_884 0x410ADD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_885 0x410ADD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_886 0x410ADD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_887 0x410ADDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_888 0x410ADE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_889 0x410ADE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_890 0x410ADE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_891 0x410ADEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_892 0x410ADF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_893 0x410ADF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_894 0x410ADF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_895 0x410ADFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_896 0x410AE00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_897 0x410AE04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_898 0x410AE08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_899 0x410AE0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_900 0x410AE10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_901 0x410AE14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_902 0x410AE18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_903 0x410AE1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_904 0x410AE20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_905 0x410AE24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_906 0x410AE28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_907 0x410AE2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_908 0x410AE30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_909 0x410AE34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_910 0x410AE38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_911 0x410AE3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_912 0x410AE40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_913 0x410AE44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_914 0x410AE48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_915 0x410AE4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_916 0x410AE50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_917 0x410AE54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_918 0x410AE58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_919 0x410AE5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_920 0x410AE60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_921 0x410AE64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_922 0x410AE68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_923 0x410AE6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_924 0x410AE70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_925 0x410AE74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_926 0x410AE78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_927 0x410AE7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_928 0x410AE80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_929 0x410AE84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_930 0x410AE88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_931 0x410AE8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_932 0x410AE90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_933 0x410AE94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_934 0x410AE98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_935 0x410AE9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_936 0x410AEA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_937 0x410AEA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_938 0x410AEA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_939 0x410AEAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_940 0x410AEB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_941 0x410AEB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_942 0x410AEB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_943 0x410AEBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_944 0x410AEC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_945 0x410AEC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_946 0x410AEC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_947 0x410AECC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_948 0x410AED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_949 0x410AED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_950 0x410AED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_951 0x410AEDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_952 0x410AEE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_953 0x410AEE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_954 0x410AEE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_955 0x410AEEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_956 0x410AEF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_957 0x410AEF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_958 0x410AEF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_959 0x410AEFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_960 0x410AF00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_961 0x410AF04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_962 0x410AF08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_963 0x410AF0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_964 0x410AF10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_965 0x410AF14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_966 0x410AF18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_967 0x410AF1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_968 0x410AF20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_969 0x410AF24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_970 0x410AF28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_971 0x410AF2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_972 0x410AF30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_973 0x410AF34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_974 0x410AF38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_975 0x410AF3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_976 0x410AF40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_977 0x410AF44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_978 0x410AF48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_979 0x410AF4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_980 0x410AF50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_981 0x410AF54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_982 0x410AF58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_983 0x410AF5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_984 0x410AF60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_985 0x410AF64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_986 0x410AF68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_987 0x410AF6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_988 0x410AF70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_989 0x410AF74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_990 0x410AF78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_991 0x410AF7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_992 0x410AF80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_993 0x410AF84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_994 0x410AF88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_995 0x410AF8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_996 0x410AF90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_997 0x410AF94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_998 0x410AF98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_999 0x410AF9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1000 0x410AFA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1001 0x410AFA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1002 0x410AFA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1003 0x410AFAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1004 0x410AFB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1005 0x410AFB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1006 0x410AFB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1007 0x410AFBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1008 0x410AFC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1009 0x410AFC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1010 0x410AFC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1011 0x410AFCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1012 0x410AFD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1013 0x410AFD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1014 0x410AFD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1015 0x410AFDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1016 0x410AFE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1017 0x410AFE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1018 0x410AFE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1019 0x410AFEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1020 0x410AFF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1021 0x410AFF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1022 0x410AFF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1023 0x410AFFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1024 0x410B000 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1025 0x410B004 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1026 0x410B008 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1027 0x410B00C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1028 0x410B010 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1029 0x410B014 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1030 0x410B018 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1031 0x410B01C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1032 0x410B020 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1033 0x410B024 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1034 0x410B028 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1035 0x410B02C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1036 0x410B030 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1037 0x410B034 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1038 0x410B038 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1039 0x410B03C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1040 0x410B040 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1041 0x410B044 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1042 0x410B048 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1043 0x410B04C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1044 0x410B050 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1045 0x410B054 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1046 0x410B058 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1047 0x410B05C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1048 0x410B060 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1049 0x410B064 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1050 0x410B068 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1051 0x410B06C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1052 0x410B070 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1053 0x410B074 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1054 0x410B078 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1055 0x410B07C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1056 0x410B080 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1057 0x410B084 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1058 0x410B088 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1059 0x410B08C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1060 0x410B090 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1061 0x410B094 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1062 0x410B098 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1063 0x410B09C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1064 0x410B0A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1065 0x410B0A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1066 0x410B0A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1067 0x410B0AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1068 0x410B0B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1069 0x410B0B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1070 0x410B0B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1071 0x410B0BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1072 0x410B0C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1073 0x410B0C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1074 0x410B0C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1075 0x410B0CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1076 0x410B0D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1077 0x410B0D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1078 0x410B0D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1079 0x410B0DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1080 0x410B0E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1081 0x410B0E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1082 0x410B0E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1083 0x410B0EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1084 0x410B0F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1085 0x410B0F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1086 0x410B0F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1087 0x410B0FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1088 0x410B100 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1089 0x410B104 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1090 0x410B108 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1091 0x410B10C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1092 0x410B110 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1093 0x410B114 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1094 0x410B118 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1095 0x410B11C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1096 0x410B120 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1097 0x410B124 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1098 0x410B128 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1099 0x410B12C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1100 0x410B130 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1101 0x410B134 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1102 0x410B138 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1103 0x410B13C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1104 0x410B140 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1105 0x410B144 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1106 0x410B148 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1107 0x410B14C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1108 0x410B150 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1109 0x410B154 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1110 0x410B158 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1111 0x410B15C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1112 0x410B160 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1113 0x410B164 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1114 0x410B168 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1115 0x410B16C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1116 0x410B170 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1117 0x410B174 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1118 0x410B178 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1119 0x410B17C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1120 0x410B180 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1121 0x410B184 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1122 0x410B188 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1123 0x410B18C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1124 0x410B190 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1125 0x410B194 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1126 0x410B198 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1127 0x410B19C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1128 0x410B1A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1129 0x410B1A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1130 0x410B1A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1131 0x410B1AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1132 0x410B1B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1133 0x410B1B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1134 0x410B1B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1135 0x410B1BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1136 0x410B1C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1137 0x410B1C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1138 0x410B1C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1139 0x410B1CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1140 0x410B1D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1141 0x410B1D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1142 0x410B1D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1143 0x410B1DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1144 0x410B1E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1145 0x410B1E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1146 0x410B1E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1147 0x410B1EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1148 0x410B1F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1149 0x410B1F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1150 0x410B1F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1151 0x410B1FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1152 0x410B200 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1153 0x410B204 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1154 0x410B208 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1155 0x410B20C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1156 0x410B210 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1157 0x410B214 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1158 0x410B218 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1159 0x410B21C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1160 0x410B220 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1161 0x410B224 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1162 0x410B228 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1163 0x410B22C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1164 0x410B230 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1165 0x410B234 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1166 0x410B238 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1167 0x410B23C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1168 0x410B240 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1169 0x410B244 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1170 0x410B248 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1171 0x410B24C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1172 0x410B250 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1173 0x410B254 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1174 0x410B258 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1175 0x410B25C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1176 0x410B260 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1177 0x410B264 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1178 0x410B268 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1179 0x410B26C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1180 0x410B270 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1181 0x410B274 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1182 0x410B278 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1183 0x410B27C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1184 0x410B280 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1185 0x410B284 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1186 0x410B288 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1187 0x410B28C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1188 0x410B290 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1189 0x410B294 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1190 0x410B298 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1191 0x410B29C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1192 0x410B2A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1193 0x410B2A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1194 0x410B2A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1195 0x410B2AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1196 0x410B2B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1197 0x410B2B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1198 0x410B2B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1199 0x410B2BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1200 0x410B2C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1201 0x410B2C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1202 0x410B2C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1203 0x410B2CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1204 0x410B2D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1205 0x410B2D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1206 0x410B2D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1207 0x410B2DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1208 0x410B2E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1209 0x410B2E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1210 0x410B2E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1211 0x410B2EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1212 0x410B2F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1213 0x410B2F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1214 0x410B2F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1215 0x410B2FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1216 0x410B300 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1217 0x410B304 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1218 0x410B308 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1219 0x410B30C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1220 0x410B310 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1221 0x410B314 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1222 0x410B318 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1223 0x410B31C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1224 0x410B320 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1225 0x410B324 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1226 0x410B328 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1227 0x410B32C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1228 0x410B330 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1229 0x410B334 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1230 0x410B338 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1231 0x410B33C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1232 0x410B340 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1233 0x410B344 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1234 0x410B348 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1235 0x410B34C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1236 0x410B350 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1237 0x410B354 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1238 0x410B358 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1239 0x410B35C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1240 0x410B360 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1241 0x410B364 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1242 0x410B368 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1243 0x410B36C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1244 0x410B370 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1245 0x410B374 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1246 0x410B378 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1247 0x410B37C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1248 0x410B380 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1249 0x410B384 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1250 0x410B388 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1251 0x410B38C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1252 0x410B390 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1253 0x410B394 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1254 0x410B398 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1255 0x410B39C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1256 0x410B3A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1257 0x410B3A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1258 0x410B3A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1259 0x410B3AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1260 0x410B3B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1261 0x410B3B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1262 0x410B3B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1263 0x410B3BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1264 0x410B3C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1265 0x410B3C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1266 0x410B3C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1267 0x410B3CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1268 0x410B3D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1269 0x410B3D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1270 0x410B3D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1271 0x410B3DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1272 0x410B3E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1273 0x410B3E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1274 0x410B3E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1275 0x410B3EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1276 0x410B3F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1277 0x410B3F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1278 0x410B3F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1279 0x410B3FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1280 0x410B400 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1281 0x410B404 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1282 0x410B408 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1283 0x410B40C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1284 0x410B410 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1285 0x410B414 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1286 0x410B418 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1287 0x410B41C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1288 0x410B420 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1289 0x410B424 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1290 0x410B428 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1291 0x410B42C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1292 0x410B430 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1293 0x410B434 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1294 0x410B438 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1295 0x410B43C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1296 0x410B440 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1297 0x410B444 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1298 0x410B448 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1299 0x410B44C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1300 0x410B450 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1301 0x410B454 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1302 0x410B458 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1303 0x410B45C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1304 0x410B460 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1305 0x410B464 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1306 0x410B468 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1307 0x410B46C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1308 0x410B470 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1309 0x410B474 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1310 0x410B478 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1311 0x410B47C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1312 0x410B480 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1313 0x410B484 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1314 0x410B488 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1315 0x410B48C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1316 0x410B490 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1317 0x410B494 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1318 0x410B498 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1319 0x410B49C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1320 0x410B4A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1321 0x410B4A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1322 0x410B4A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1323 0x410B4AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1324 0x410B4B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1325 0x410B4B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1326 0x410B4B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1327 0x410B4BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1328 0x410B4C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1329 0x410B4C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1330 0x410B4C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1331 0x410B4CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1332 0x410B4D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1333 0x410B4D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1334 0x410B4D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1335 0x410B4DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1336 0x410B4E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1337 0x410B4E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1338 0x410B4E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1339 0x410B4EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1340 0x410B4F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1341 0x410B4F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1342 0x410B4F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1343 0x410B4FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1344 0x410B500 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1345 0x410B504 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1346 0x410B508 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1347 0x410B50C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1348 0x410B510 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1349 0x410B514 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1350 0x410B518 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1351 0x410B51C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1352 0x410B520 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1353 0x410B524 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1354 0x410B528 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1355 0x410B52C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1356 0x410B530 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1357 0x410B534 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1358 0x410B538 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1359 0x410B53C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1360 0x410B540 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1361 0x410B544 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1362 0x410B548 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1363 0x410B54C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1364 0x410B550 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1365 0x410B554 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1366 0x410B558 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1367 0x410B55C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1368 0x410B560 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1369 0x410B564 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1370 0x410B568 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1371 0x410B56C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1372 0x410B570 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1373 0x410B574 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1374 0x410B578 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1375 0x410B57C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1376 0x410B580 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1377 0x410B584 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1378 0x410B588 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1379 0x410B58C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1380 0x410B590 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1381 0x410B594 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1382 0x410B598 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1383 0x410B59C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1384 0x410B5A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1385 0x410B5A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1386 0x410B5A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1387 0x410B5AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1388 0x410B5B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1389 0x410B5B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1390 0x410B5B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1391 0x410B5BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1392 0x410B5C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1393 0x410B5C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1394 0x410B5C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1395 0x410B5CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1396 0x410B5D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1397 0x410B5D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1398 0x410B5D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1399 0x410B5DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1400 0x410B5E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1401 0x410B5E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1402 0x410B5E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1403 0x410B5EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1404 0x410B5F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1405 0x410B5F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1406 0x410B5F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1407 0x410B5FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1408 0x410B600 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1409 0x410B604 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1410 0x410B608 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1411 0x410B60C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1412 0x410B610 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1413 0x410B614 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1414 0x410B618 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1415 0x410B61C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1416 0x410B620 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1417 0x410B624 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1418 0x410B628 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1419 0x410B62C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1420 0x410B630 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1421 0x410B634 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1422 0x410B638 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1423 0x410B63C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1424 0x410B640 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1425 0x410B644 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1426 0x410B648 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1427 0x410B64C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1428 0x410B650 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1429 0x410B654 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1430 0x410B658 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1431 0x410B65C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1432 0x410B660 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1433 0x410B664 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1434 0x410B668 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1435 0x410B66C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1436 0x410B670 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1437 0x410B674 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1438 0x410B678 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1439 0x410B67C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1440 0x410B680 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1441 0x410B684 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1442 0x410B688 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1443 0x410B68C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1444 0x410B690 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1445 0x410B694 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1446 0x410B698 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1447 0x410B69C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1448 0x410B6A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1449 0x410B6A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1450 0x410B6A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1451 0x410B6AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1452 0x410B6B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1453 0x410B6B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1454 0x410B6B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1455 0x410B6BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1456 0x410B6C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1457 0x410B6C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1458 0x410B6C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1459 0x410B6CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1460 0x410B6D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1461 0x410B6D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1462 0x410B6D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1463 0x410B6DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1464 0x410B6E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1465 0x410B6E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1466 0x410B6E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1467 0x410B6EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1468 0x410B6F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1469 0x410B6F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1470 0x410B6F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1471 0x410B6FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1472 0x410B700 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1473 0x410B704 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1474 0x410B708 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1475 0x410B70C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1476 0x410B710 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1477 0x410B714 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1478 0x410B718 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1479 0x410B71C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1480 0x410B720 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1481 0x410B724 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1482 0x410B728 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1483 0x410B72C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1484 0x410B730 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1485 0x410B734 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1486 0x410B738 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1487 0x410B73C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1488 0x410B740 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1489 0x410B744 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1490 0x410B748 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1491 0x410B74C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1492 0x410B750 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1493 0x410B754 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1494 0x410B758 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1495 0x410B75C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1496 0x410B760 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1497 0x410B764 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1498 0x410B768 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1499 0x410B76C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1500 0x410B770 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1501 0x410B774 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1502 0x410B778 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1503 0x410B77C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1504 0x410B780 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1505 0x410B784 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1506 0x410B788 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1507 0x410B78C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1508 0x410B790 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1509 0x410B794 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1510 0x410B798 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1511 0x410B79C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1512 0x410B7A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1513 0x410B7A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1514 0x410B7A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1515 0x410B7AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1516 0x410B7B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1517 0x410B7B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1518 0x410B7B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1519 0x410B7BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1520 0x410B7C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1521 0x410B7C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1522 0x410B7C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1523 0x410B7CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1524 0x410B7D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1525 0x410B7D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1526 0x410B7D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1527 0x410B7DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1528 0x410B7E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1529 0x410B7E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1530 0x410B7E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1531 0x410B7EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1532 0x410B7F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1533 0x410B7F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1534 0x410B7F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1535 0x410B7FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1536 0x410B800 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1537 0x410B804 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1538 0x410B808 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1539 0x410B80C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1540 0x410B810 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1541 0x410B814 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1542 0x410B818 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1543 0x410B81C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1544 0x410B820 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1545 0x410B824 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1546 0x410B828 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1547 0x410B82C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1548 0x410B830 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1549 0x410B834 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1550 0x410B838 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1551 0x410B83C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1552 0x410B840 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1553 0x410B844 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1554 0x410B848 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1555 0x410B84C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1556 0x410B850 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1557 0x410B854 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1558 0x410B858 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1559 0x410B85C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1560 0x410B860 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1561 0x410B864 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1562 0x410B868 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1563 0x410B86C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1564 0x410B870 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1565 0x410B874 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1566 0x410B878 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1567 0x410B87C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1568 0x410B880 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1569 0x410B884 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1570 0x410B888 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1571 0x410B88C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1572 0x410B890 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1573 0x410B894 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1574 0x410B898 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1575 0x410B89C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1576 0x410B8A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1577 0x410B8A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1578 0x410B8A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1579 0x410B8AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1580 0x410B8B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1581 0x410B8B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1582 0x410B8B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1583 0x410B8BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1584 0x410B8C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1585 0x410B8C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1586 0x410B8C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1587 0x410B8CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1588 0x410B8D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1589 0x410B8D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1590 0x410B8D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1591 0x410B8DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1592 0x410B8E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1593 0x410B8E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1594 0x410B8E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1595 0x410B8EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1596 0x410B8F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1597 0x410B8F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1598 0x410B8F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1599 0x410B8FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1600 0x410B900 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1601 0x410B904 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1602 0x410B908 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1603 0x410B90C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1604 0x410B910 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1605 0x410B914 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1606 0x410B918 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1607 0x410B91C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1608 0x410B920 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1609 0x410B924 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1610 0x410B928 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1611 0x410B92C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1612 0x410B930 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1613 0x410B934 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1614 0x410B938 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1615 0x410B93C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1616 0x410B940 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1617 0x410B944 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1618 0x410B948 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1619 0x410B94C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1620 0x410B950 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1621 0x410B954 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1622 0x410B958 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1623 0x410B95C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1624 0x410B960 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1625 0x410B964 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1626 0x410B968 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1627 0x410B96C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1628 0x410B970 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1629 0x410B974 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1630 0x410B978 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1631 0x410B97C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1632 0x410B980 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1633 0x410B984 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1634 0x410B988 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1635 0x410B98C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1636 0x410B990 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1637 0x410B994 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1638 0x410B998 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1639 0x410B99C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1640 0x410B9A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1641 0x410B9A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1642 0x410B9A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1643 0x410B9AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1644 0x410B9B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1645 0x410B9B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1646 0x410B9B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1647 0x410B9BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1648 0x410B9C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1649 0x410B9C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1650 0x410B9C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1651 0x410B9CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1652 0x410B9D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1653 0x410B9D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1654 0x410B9D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1655 0x410B9DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1656 0x410B9E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1657 0x410B9E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1658 0x410B9E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1659 0x410B9EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1660 0x410B9F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1661 0x410B9F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1662 0x410B9F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1663 0x410B9FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1664 0x410BA00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1665 0x410BA04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1666 0x410BA08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1667 0x410BA0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1668 0x410BA10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1669 0x410BA14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1670 0x410BA18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1671 0x410BA1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1672 0x410BA20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1673 0x410BA24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1674 0x410BA28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1675 0x410BA2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1676 0x410BA30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1677 0x410BA34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1678 0x410BA38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1679 0x410BA3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1680 0x410BA40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1681 0x410BA44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1682 0x410BA48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1683 0x410BA4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1684 0x410BA50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1685 0x410BA54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1686 0x410BA58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1687 0x410BA5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1688 0x410BA60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1689 0x410BA64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1690 0x410BA68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1691 0x410BA6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1692 0x410BA70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1693 0x410BA74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1694 0x410BA78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1695 0x410BA7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1696 0x410BA80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1697 0x410BA84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1698 0x410BA88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1699 0x410BA8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1700 0x410BA90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1701 0x410BA94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1702 0x410BA98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1703 0x410BA9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1704 0x410BAA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1705 0x410BAA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1706 0x410BAA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1707 0x410BAAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1708 0x410BAB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1709 0x410BAB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1710 0x410BAB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1711 0x410BABC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1712 0x410BAC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1713 0x410BAC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1714 0x410BAC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1715 0x410BACC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1716 0x410BAD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1717 0x410BAD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1718 0x410BAD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1719 0x410BADC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1720 0x410BAE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1721 0x410BAE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1722 0x410BAE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1723 0x410BAEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1724 0x410BAF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1725 0x410BAF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1726 0x410BAF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1727 0x410BAFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1728 0x410BB00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1729 0x410BB04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1730 0x410BB08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1731 0x410BB0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1732 0x410BB10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1733 0x410BB14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1734 0x410BB18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1735 0x410BB1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1736 0x410BB20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1737 0x410BB24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1738 0x410BB28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1739 0x410BB2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1740 0x410BB30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1741 0x410BB34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1742 0x410BB38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1743 0x410BB3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1744 0x410BB40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1745 0x410BB44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1746 0x410BB48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1747 0x410BB4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1748 0x410BB50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1749 0x410BB54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1750 0x410BB58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1751 0x410BB5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1752 0x410BB60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1753 0x410BB64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1754 0x410BB68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1755 0x410BB6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1756 0x410BB70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1757 0x410BB74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1758 0x410BB78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1759 0x410BB7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1760 0x410BB80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1761 0x410BB84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1762 0x410BB88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1763 0x410BB8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1764 0x410BB90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1765 0x410BB94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1766 0x410BB98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1767 0x410BB9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1768 0x410BBA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1769 0x410BBA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1770 0x410BBA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1771 0x410BBAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1772 0x410BBB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1773 0x410BBB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1774 0x410BBB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1775 0x410BBBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1776 0x410BBC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1777 0x410BBC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1778 0x410BBC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1779 0x410BBCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1780 0x410BBD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1781 0x410BBD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1782 0x410BBD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1783 0x410BBDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1784 0x410BBE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1785 0x410BBE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1786 0x410BBE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1787 0x410BBEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1788 0x410BBF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1789 0x410BBF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1790 0x410BBF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1791 0x410BBFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1792 0x410BC00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1793 0x410BC04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1794 0x410BC08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1795 0x410BC0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1796 0x410BC10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1797 0x410BC14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1798 0x410BC18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1799 0x410BC1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1800 0x410BC20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1801 0x410BC24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1802 0x410BC28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1803 0x410BC2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1804 0x410BC30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1805 0x410BC34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1806 0x410BC38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1807 0x410BC3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1808 0x410BC40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1809 0x410BC44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1810 0x410BC48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1811 0x410BC4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1812 0x410BC50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1813 0x410BC54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1814 0x410BC58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1815 0x410BC5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1816 0x410BC60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1817 0x410BC64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1818 0x410BC68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1819 0x410BC6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1820 0x410BC70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1821 0x410BC74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1822 0x410BC78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1823 0x410BC7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1824 0x410BC80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1825 0x410BC84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1826 0x410BC88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1827 0x410BC8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1828 0x410BC90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1829 0x410BC94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1830 0x410BC98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1831 0x410BC9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1832 0x410BCA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1833 0x410BCA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1834 0x410BCA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1835 0x410BCAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1836 0x410BCB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1837 0x410BCB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1838 0x410BCB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1839 0x410BCBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1840 0x410BCC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1841 0x410BCC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1842 0x410BCC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1843 0x410BCCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1844 0x410BCD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1845 0x410BCD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1846 0x410BCD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1847 0x410BCDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1848 0x410BCE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1849 0x410BCE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1850 0x410BCE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1851 0x410BCEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1852 0x410BCF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1853 0x410BCF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1854 0x410BCF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1855 0x410BCFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1856 0x410BD00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1857 0x410BD04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1858 0x410BD08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1859 0x410BD0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1860 0x410BD10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1861 0x410BD14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1862 0x410BD18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1863 0x410BD1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1864 0x410BD20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1865 0x410BD24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1866 0x410BD28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1867 0x410BD2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1868 0x410BD30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1869 0x410BD34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1870 0x410BD38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1871 0x410BD3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1872 0x410BD40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1873 0x410BD44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1874 0x410BD48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1875 0x410BD4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1876 0x410BD50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1877 0x410BD54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1878 0x410BD58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1879 0x410BD5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1880 0x410BD60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1881 0x410BD64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1882 0x410BD68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1883 0x410BD6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1884 0x410BD70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1885 0x410BD74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1886 0x410BD78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1887 0x410BD7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1888 0x410BD80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1889 0x410BD84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1890 0x410BD88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1891 0x410BD8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1892 0x410BD90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1893 0x410BD94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1894 0x410BD98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1895 0x410BD9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1896 0x410BDA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1897 0x410BDA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1898 0x410BDA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1899 0x410BDAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1900 0x410BDB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1901 0x410BDB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1902 0x410BDB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1903 0x410BDBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1904 0x410BDC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1905 0x410BDC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1906 0x410BDC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1907 0x410BDCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1908 0x410BDD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1909 0x410BDD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1910 0x410BDD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1911 0x410BDDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1912 0x410BDE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1913 0x410BDE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1914 0x410BDE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1915 0x410BDEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1916 0x410BDF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1917 0x410BDF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1918 0x410BDF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1919 0x410BDFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1920 0x410BE00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1921 0x410BE04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1922 0x410BE08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1923 0x410BE0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1924 0x410BE10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1925 0x410BE14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1926 0x410BE18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1927 0x410BE1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1928 0x410BE20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1929 0x410BE24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1930 0x410BE28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1931 0x410BE2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1932 0x410BE30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1933 0x410BE34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1934 0x410BE38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1935 0x410BE3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1936 0x410BE40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1937 0x410BE44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1938 0x410BE48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1939 0x410BE4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1940 0x410BE50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1941 0x410BE54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1942 0x410BE58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1943 0x410BE5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1944 0x410BE60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1945 0x410BE64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1946 0x410BE68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1947 0x410BE6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1948 0x410BE70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1949 0x410BE74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1950 0x410BE78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1951 0x410BE7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1952 0x410BE80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1953 0x410BE84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1954 0x410BE88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1955 0x410BE8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1956 0x410BE90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1957 0x410BE94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1958 0x410BE98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1959 0x410BE9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1960 0x410BEA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1961 0x410BEA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1962 0x410BEA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1963 0x410BEAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1964 0x410BEB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1965 0x410BEB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1966 0x410BEB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1967 0x410BEBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1968 0x410BEC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1969 0x410BEC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1970 0x410BEC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1971 0x410BECC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1972 0x410BED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1973 0x410BED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1974 0x410BED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1975 0x410BEDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1976 0x410BEE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1977 0x410BEE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1978 0x410BEE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1979 0x410BEEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1980 0x410BEF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1981 0x410BEF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1982 0x410BEF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1983 0x410BEFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1984 0x410BF00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1985 0x410BF04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1986 0x410BF08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1987 0x410BF0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1988 0x410BF10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1989 0x410BF14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1990 0x410BF18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1991 0x410BF1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1992 0x410BF20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1993 0x410BF24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1994 0x410BF28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1995 0x410BF2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1996 0x410BF30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1997 0x410BF34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1998 0x410BF38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1999 0x410BF3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2000 0x410BF40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2001 0x410BF44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2002 0x410BF48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2003 0x410BF4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2004 0x410BF50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2005 0x410BF54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2006 0x410BF58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2007 0x410BF5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2008 0x410BF60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2009 0x410BF64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2010 0x410BF68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2011 0x410BF6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2012 0x410BF70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2013 0x410BF74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2014 0x410BF78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2015 0x410BF7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2016 0x410BF80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2017 0x410BF84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2018 0x410BF88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2019 0x410BF8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2020 0x410BF90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2021 0x410BF94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2022 0x410BF98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2023 0x410BF9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2024 0x410BFA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2025 0x410BFA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2026 0x410BFA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2027 0x410BFAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2028 0x410BFB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2029 0x410BFB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2030 0x410BFB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2031 0x410BFBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2032 0x410BFC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2033 0x410BFC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2034 0x410BFC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2035 0x410BFCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2036 0x410BFD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2037 0x410BFD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2038 0x410BFD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2039 0x410BFDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2040 0x410BFE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2041 0x410BFE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2042 0x410BFE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2043 0x410BFEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2044 0x410BFF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2045 0x410BFF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2046 0x410BFF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2047 0x410BFFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_0 0x410C000 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1 0x410C004 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2 0x410C008 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_3 0x410C00C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_4 0x410C010 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_5 0x410C014 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_6 0x410C018 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_7 0x410C01C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_8 0x410C020 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_9 0x410C024 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_10 0x410C028 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_11 0x410C02C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_12 0x410C030 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_13 0x410C034 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_14 0x410C038 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_15 0x410C03C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_16 0x410C040 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_17 0x410C044 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_18 0x410C048 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_19 0x410C04C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_20 0x410C050 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_21 0x410C054 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_22 0x410C058 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_23 0x410C05C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_24 0x410C060 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_25 0x410C064 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_26 0x410C068 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_27 0x410C06C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_28 0x410C070 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_29 0x410C074 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_30 0x410C078 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_31 0x410C07C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_32 0x410C080 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_33 0x410C084 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_34 0x410C088 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_35 0x410C08C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_36 0x410C090 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_37 0x410C094 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_38 0x410C098 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_39 0x410C09C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_40 0x410C0A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_41 0x410C0A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_42 0x410C0A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_43 0x410C0AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_44 0x410C0B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_45 0x410C0B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_46 0x410C0B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_47 0x410C0BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_48 0x410C0C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_49 0x410C0C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_50 0x410C0C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_51 0x410C0CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_52 0x410C0D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_53 0x410C0D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_54 0x410C0D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_55 0x410C0DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_56 0x410C0E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_57 0x410C0E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_58 0x410C0E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_59 0x410C0EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_60 0x410C0F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_61 0x410C0F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_62 0x410C0F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_63 0x410C0FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_64 0x410C100 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_65 0x410C104 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_66 0x410C108 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_67 0x410C10C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_68 0x410C110 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_69 0x410C114 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_70 0x410C118 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_71 0x410C11C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_72 0x410C120 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_73 0x410C124 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_74 0x410C128 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_75 0x410C12C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_76 0x410C130 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_77 0x410C134 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_78 0x410C138 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_79 0x410C13C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_80 0x410C140 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_81 0x410C144 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_82 0x410C148 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_83 0x410C14C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_84 0x410C150 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_85 0x410C154 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_86 0x410C158 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_87 0x410C15C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_88 0x410C160 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_89 0x410C164 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_90 0x410C168 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_91 0x410C16C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_92 0x410C170 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_93 0x410C174 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_94 0x410C178 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_95 0x410C17C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_96 0x410C180 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_97 0x410C184 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_98 0x410C188 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_99 0x410C18C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_100 0x410C190 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_101 0x410C194 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_102 0x410C198 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_103 0x410C19C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_104 0x410C1A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_105 0x410C1A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_106 0x410C1A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_107 0x410C1AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_108 0x410C1B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_109 0x410C1B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_110 0x410C1B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_111 0x410C1BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_112 0x410C1C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_113 0x410C1C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_114 0x410C1C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_115 0x410C1CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_116 0x410C1D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_117 0x410C1D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_118 0x410C1D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_119 0x410C1DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_120 0x410C1E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_121 0x410C1E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_122 0x410C1E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_123 0x410C1EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_124 0x410C1F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_125 0x410C1F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_126 0x410C1F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_127 0x410C1FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_128 0x410C200 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_129 0x410C204 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_130 0x410C208 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_131 0x410C20C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_132 0x410C210 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_133 0x410C214 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_134 0x410C218 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_135 0x410C21C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_136 0x410C220 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_137 0x410C224 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_138 0x410C228 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_139 0x410C22C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_140 0x410C230 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_141 0x410C234 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_142 0x410C238 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_143 0x410C23C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_144 0x410C240 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_145 0x410C244 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_146 0x410C248 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_147 0x410C24C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_148 0x410C250 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_149 0x410C254 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_150 0x410C258 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_151 0x410C25C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_152 0x410C260 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_153 0x410C264 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_154 0x410C268 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_155 0x410C26C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_156 0x410C270 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_157 0x410C274 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_158 0x410C278 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_159 0x410C27C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_160 0x410C280 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_161 0x410C284 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_162 0x410C288 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_163 0x410C28C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_164 0x410C290 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_165 0x410C294 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_166 0x410C298 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_167 0x410C29C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_168 0x410C2A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_169 0x410C2A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_170 0x410C2A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_171 0x410C2AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_172 0x410C2B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_173 0x410C2B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_174 0x410C2B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_175 0x410C2BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_176 0x410C2C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_177 0x410C2C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_178 0x410C2C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_179 0x410C2CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_180 0x410C2D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_181 0x410C2D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_182 0x410C2D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_183 0x410C2DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_184 0x410C2E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_185 0x410C2E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_186 0x410C2E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_187 0x410C2EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_188 0x410C2F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_189 0x410C2F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_190 0x410C2F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_191 0x410C2FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_192 0x410C300 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_193 0x410C304 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_194 0x410C308 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_195 0x410C30C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_196 0x410C310 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_197 0x410C314 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_198 0x410C318 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_199 0x410C31C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_200 0x410C320 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_201 0x410C324 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_202 0x410C328 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_203 0x410C32C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_204 0x410C330 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_205 0x410C334 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_206 0x410C338 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_207 0x410C33C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_208 0x410C340 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_209 0x410C344 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_210 0x410C348 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_211 0x410C34C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_212 0x410C350 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_213 0x410C354 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_214 0x410C358 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_215 0x410C35C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_216 0x410C360 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_217 0x410C364 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_218 0x410C368 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_219 0x410C36C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_220 0x410C370 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_221 0x410C374 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_222 0x410C378 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_223 0x410C37C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_224 0x410C380 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_225 0x410C384 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_226 0x410C388 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_227 0x410C38C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_228 0x410C390 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_229 0x410C394 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_230 0x410C398 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_231 0x410C39C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_232 0x410C3A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_233 0x410C3A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_234 0x410C3A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_235 0x410C3AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_236 0x410C3B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_237 0x410C3B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_238 0x410C3B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_239 0x410C3BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_240 0x410C3C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_241 0x410C3C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_242 0x410C3C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_243 0x410C3CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_244 0x410C3D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_245 0x410C3D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_246 0x410C3D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_247 0x410C3DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_248 0x410C3E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_249 0x410C3E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_250 0x410C3E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_251 0x410C3EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_252 0x410C3F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_253 0x410C3F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_254 0x410C3F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_255 0x410C3FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_256 0x410C400 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_257 0x410C404 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_258 0x410C408 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_259 0x410C40C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_260 0x410C410 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_261 0x410C414 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_262 0x410C418 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_263 0x410C41C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_264 0x410C420 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_265 0x410C424 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_266 0x410C428 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_267 0x410C42C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_268 0x410C430 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_269 0x410C434 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_270 0x410C438 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_271 0x410C43C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_272 0x410C440 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_273 0x410C444 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_274 0x410C448 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_275 0x410C44C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_276 0x410C450 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_277 0x410C454 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_278 0x410C458 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_279 0x410C45C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_280 0x410C460 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_281 0x410C464 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_282 0x410C468 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_283 0x410C46C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_284 0x410C470 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_285 0x410C474 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_286 0x410C478 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_287 0x410C47C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_288 0x410C480 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_289 0x410C484 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_290 0x410C488 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_291 0x410C48C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_292 0x410C490 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_293 0x410C494 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_294 0x410C498 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_295 0x410C49C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_296 0x410C4A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_297 0x410C4A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_298 0x410C4A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_299 0x410C4AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_300 0x410C4B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_301 0x410C4B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_302 0x410C4B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_303 0x410C4BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_304 0x410C4C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_305 0x410C4C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_306 0x410C4C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_307 0x410C4CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_308 0x410C4D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_309 0x410C4D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_310 0x410C4D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_311 0x410C4DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_312 0x410C4E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_313 0x410C4E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_314 0x410C4E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_315 0x410C4EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_316 0x410C4F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_317 0x410C4F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_318 0x410C4F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_319 0x410C4FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_320 0x410C500 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_321 0x410C504 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_322 0x410C508 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_323 0x410C50C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_324 0x410C510 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_325 0x410C514 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_326 0x410C518 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_327 0x410C51C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_328 0x410C520 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_329 0x410C524 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_330 0x410C528 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_331 0x410C52C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_332 0x410C530 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_333 0x410C534 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_334 0x410C538 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_335 0x410C53C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_336 0x410C540 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_337 0x410C544 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_338 0x410C548 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_339 0x410C54C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_340 0x410C550 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_341 0x410C554 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_342 0x410C558 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_343 0x410C55C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_344 0x410C560 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_345 0x410C564 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_346 0x410C568 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_347 0x410C56C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_348 0x410C570 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_349 0x410C574 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_350 0x410C578 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_351 0x410C57C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_352 0x410C580 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_353 0x410C584 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_354 0x410C588 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_355 0x410C58C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_356 0x410C590 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_357 0x410C594 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_358 0x410C598 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_359 0x410C59C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_360 0x410C5A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_361 0x410C5A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_362 0x410C5A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_363 0x410C5AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_364 0x410C5B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_365 0x410C5B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_366 0x410C5B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_367 0x410C5BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_368 0x410C5C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_369 0x410C5C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_370 0x410C5C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_371 0x410C5CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_372 0x410C5D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_373 0x410C5D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_374 0x410C5D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_375 0x410C5DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_376 0x410C5E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_377 0x410C5E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_378 0x410C5E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_379 0x410C5EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_380 0x410C5F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_381 0x410C5F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_382 0x410C5F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_383 0x410C5FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_384 0x410C600 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_385 0x410C604 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_386 0x410C608 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_387 0x410C60C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_388 0x410C610 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_389 0x410C614 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_390 0x410C618 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_391 0x410C61C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_392 0x410C620 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_393 0x410C624 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_394 0x410C628 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_395 0x410C62C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_396 0x410C630 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_397 0x410C634 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_398 0x410C638 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_399 0x410C63C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_400 0x410C640 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_401 0x410C644 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_402 0x410C648 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_403 0x410C64C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_404 0x410C650 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_405 0x410C654 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_406 0x410C658 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_407 0x410C65C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_408 0x410C660 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_409 0x410C664 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_410 0x410C668 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_411 0x410C66C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_412 0x410C670 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_413 0x410C674 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_414 0x410C678 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_415 0x410C67C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_416 0x410C680 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_417 0x410C684 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_418 0x410C688 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_419 0x410C68C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_420 0x410C690 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_421 0x410C694 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_422 0x410C698 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_423 0x410C69C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_424 0x410C6A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_425 0x410C6A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_426 0x410C6A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_427 0x410C6AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_428 0x410C6B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_429 0x410C6B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_430 0x410C6B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_431 0x410C6BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_432 0x410C6C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_433 0x410C6C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_434 0x410C6C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_435 0x410C6CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_436 0x410C6D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_437 0x410C6D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_438 0x410C6D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_439 0x410C6DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_440 0x410C6E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_441 0x410C6E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_442 0x410C6E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_443 0x410C6EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_444 0x410C6F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_445 0x410C6F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_446 0x410C6F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_447 0x410C6FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_448 0x410C700 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_449 0x410C704 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_450 0x410C708 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_451 0x410C70C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_452 0x410C710 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_453 0x410C714 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_454 0x410C718 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_455 0x410C71C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_456 0x410C720 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_457 0x410C724 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_458 0x410C728 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_459 0x410C72C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_460 0x410C730 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_461 0x410C734 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_462 0x410C738 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_463 0x410C73C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_464 0x410C740 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_465 0x410C744 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_466 0x410C748 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_467 0x410C74C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_468 0x410C750 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_469 0x410C754 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_470 0x410C758 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_471 0x410C75C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_472 0x410C760 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_473 0x410C764 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_474 0x410C768 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_475 0x410C76C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_476 0x410C770 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_477 0x410C774 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_478 0x410C778 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_479 0x410C77C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_480 0x410C780 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_481 0x410C784 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_482 0x410C788 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_483 0x410C78C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_484 0x410C790 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_485 0x410C794 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_486 0x410C798 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_487 0x410C79C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_488 0x410C7A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_489 0x410C7A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_490 0x410C7A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_491 0x410C7AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_492 0x410C7B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_493 0x410C7B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_494 0x410C7B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_495 0x410C7BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_496 0x410C7C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_497 0x410C7C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_498 0x410C7C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_499 0x410C7CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_500 0x410C7D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_501 0x410C7D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_502 0x410C7D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_503 0x410C7DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_504 0x410C7E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_505 0x410C7E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_506 0x410C7E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_507 0x410C7EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_508 0x410C7F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_509 0x410C7F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_510 0x410C7F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_511 0x410C7FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_512 0x410C800 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_513 0x410C804 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_514 0x410C808 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_515 0x410C80C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_516 0x410C810 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_517 0x410C814 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_518 0x410C818 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_519 0x410C81C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_520 0x410C820 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_521 0x410C824 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_522 0x410C828 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_523 0x410C82C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_524 0x410C830 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_525 0x410C834 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_526 0x410C838 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_527 0x410C83C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_528 0x410C840 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_529 0x410C844 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_530 0x410C848 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_531 0x410C84C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_532 0x410C850 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_533 0x410C854 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_534 0x410C858 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_535 0x410C85C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_536 0x410C860 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_537 0x410C864 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_538 0x410C868 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_539 0x410C86C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_540 0x410C870 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_541 0x410C874 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_542 0x410C878 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_543 0x410C87C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_544 0x410C880 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_545 0x410C884 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_546 0x410C888 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_547 0x410C88C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_548 0x410C890 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_549 0x410C894 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_550 0x410C898 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_551 0x410C89C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_552 0x410C8A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_553 0x410C8A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_554 0x410C8A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_555 0x410C8AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_556 0x410C8B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_557 0x410C8B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_558 0x410C8B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_559 0x410C8BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_560 0x410C8C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_561 0x410C8C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_562 0x410C8C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_563 0x410C8CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_564 0x410C8D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_565 0x410C8D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_566 0x410C8D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_567 0x410C8DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_568 0x410C8E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_569 0x410C8E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_570 0x410C8E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_571 0x410C8EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_572 0x410C8F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_573 0x410C8F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_574 0x410C8F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_575 0x410C8FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_576 0x410C900 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_577 0x410C904 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_578 0x410C908 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_579 0x410C90C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_580 0x410C910 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_581 0x410C914 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_582 0x410C918 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_583 0x410C91C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_584 0x410C920 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_585 0x410C924 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_586 0x410C928 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_587 0x410C92C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_588 0x410C930 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_589 0x410C934 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_590 0x410C938 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_591 0x410C93C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_592 0x410C940 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_593 0x410C944 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_594 0x410C948 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_595 0x410C94C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_596 0x410C950 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_597 0x410C954 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_598 0x410C958 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_599 0x410C95C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_600 0x410C960 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_601 0x410C964 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_602 0x410C968 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_603 0x410C96C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_604 0x410C970 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_605 0x410C974 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_606 0x410C978 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_607 0x410C97C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_608 0x410C980 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_609 0x410C984 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_610 0x410C988 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_611 0x410C98C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_612 0x410C990 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_613 0x410C994 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_614 0x410C998 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_615 0x410C99C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_616 0x410C9A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_617 0x410C9A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_618 0x410C9A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_619 0x410C9AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_620 0x410C9B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_621 0x410C9B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_622 0x410C9B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_623 0x410C9BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_624 0x410C9C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_625 0x410C9C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_626 0x410C9C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_627 0x410C9CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_628 0x410C9D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_629 0x410C9D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_630 0x410C9D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_631 0x410C9DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_632 0x410C9E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_633 0x410C9E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_634 0x410C9E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_635 0x410C9EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_636 0x410C9F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_637 0x410C9F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_638 0x410C9F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_639 0x410C9FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_640 0x410CA00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_641 0x410CA04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_642 0x410CA08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_643 0x410CA0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_644 0x410CA10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_645 0x410CA14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_646 0x410CA18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_647 0x410CA1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_648 0x410CA20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_649 0x410CA24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_650 0x410CA28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_651 0x410CA2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_652 0x410CA30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_653 0x410CA34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_654 0x410CA38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_655 0x410CA3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_656 0x410CA40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_657 0x410CA44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_658 0x410CA48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_659 0x410CA4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_660 0x410CA50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_661 0x410CA54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_662 0x410CA58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_663 0x410CA5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_664 0x410CA60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_665 0x410CA64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_666 0x410CA68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_667 0x410CA6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_668 0x410CA70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_669 0x410CA74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_670 0x410CA78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_671 0x410CA7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_672 0x410CA80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_673 0x410CA84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_674 0x410CA88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_675 0x410CA8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_676 0x410CA90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_677 0x410CA94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_678 0x410CA98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_679 0x410CA9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_680 0x410CAA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_681 0x410CAA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_682 0x410CAA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_683 0x410CAAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_684 0x410CAB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_685 0x410CAB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_686 0x410CAB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_687 0x410CABC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_688 0x410CAC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_689 0x410CAC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_690 0x410CAC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_691 0x410CACC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_692 0x410CAD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_693 0x410CAD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_694 0x410CAD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_695 0x410CADC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_696 0x410CAE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_697 0x410CAE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_698 0x410CAE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_699 0x410CAEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_700 0x410CAF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_701 0x410CAF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_702 0x410CAF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_703 0x410CAFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_704 0x410CB00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_705 0x410CB04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_706 0x410CB08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_707 0x410CB0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_708 0x410CB10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_709 0x410CB14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_710 0x410CB18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_711 0x410CB1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_712 0x410CB20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_713 0x410CB24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_714 0x410CB28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_715 0x410CB2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_716 0x410CB30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_717 0x410CB34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_718 0x410CB38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_719 0x410CB3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_720 0x410CB40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_721 0x410CB44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_722 0x410CB48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_723 0x410CB4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_724 0x410CB50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_725 0x410CB54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_726 0x410CB58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_727 0x410CB5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_728 0x410CB60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_729 0x410CB64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_730 0x410CB68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_731 0x410CB6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_732 0x410CB70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_733 0x410CB74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_734 0x410CB78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_735 0x410CB7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_736 0x410CB80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_737 0x410CB84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_738 0x410CB88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_739 0x410CB8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_740 0x410CB90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_741 0x410CB94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_742 0x410CB98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_743 0x410CB9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_744 0x410CBA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_745 0x410CBA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_746 0x410CBA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_747 0x410CBAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_748 0x410CBB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_749 0x410CBB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_750 0x410CBB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_751 0x410CBBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_752 0x410CBC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_753 0x410CBC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_754 0x410CBC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_755 0x410CBCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_756 0x410CBD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_757 0x410CBD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_758 0x410CBD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_759 0x410CBDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_760 0x410CBE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_761 0x410CBE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_762 0x410CBE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_763 0x410CBEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_764 0x410CBF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_765 0x410CBF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_766 0x410CBF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_767 0x410CBFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_768 0x410CC00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_769 0x410CC04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_770 0x410CC08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_771 0x410CC0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_772 0x410CC10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_773 0x410CC14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_774 0x410CC18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_775 0x410CC1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_776 0x410CC20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_777 0x410CC24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_778 0x410CC28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_779 0x410CC2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_780 0x410CC30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_781 0x410CC34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_782 0x410CC38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_783 0x410CC3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_784 0x410CC40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_785 0x410CC44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_786 0x410CC48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_787 0x410CC4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_788 0x410CC50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_789 0x410CC54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_790 0x410CC58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_791 0x410CC5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_792 0x410CC60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_793 0x410CC64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_794 0x410CC68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_795 0x410CC6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_796 0x410CC70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_797 0x410CC74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_798 0x410CC78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_799 0x410CC7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_800 0x410CC80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_801 0x410CC84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_802 0x410CC88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_803 0x410CC8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_804 0x410CC90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_805 0x410CC94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_806 0x410CC98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_807 0x410CC9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_808 0x410CCA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_809 0x410CCA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_810 0x410CCA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_811 0x410CCAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_812 0x410CCB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_813 0x410CCB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_814 0x410CCB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_815 0x410CCBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_816 0x410CCC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_817 0x410CCC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_818 0x410CCC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_819 0x410CCCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_820 0x410CCD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_821 0x410CCD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_822 0x410CCD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_823 0x410CCDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_824 0x410CCE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_825 0x410CCE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_826 0x410CCE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_827 0x410CCEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_828 0x410CCF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_829 0x410CCF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_830 0x410CCF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_831 0x410CCFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_832 0x410CD00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_833 0x410CD04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_834 0x410CD08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_835 0x410CD0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_836 0x410CD10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_837 0x410CD14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_838 0x410CD18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_839 0x410CD1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_840 0x410CD20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_841 0x410CD24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_842 0x410CD28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_843 0x410CD2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_844 0x410CD30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_845 0x410CD34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_846 0x410CD38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_847 0x410CD3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_848 0x410CD40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_849 0x410CD44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_850 0x410CD48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_851 0x410CD4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_852 0x410CD50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_853 0x410CD54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_854 0x410CD58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_855 0x410CD5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_856 0x410CD60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_857 0x410CD64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_858 0x410CD68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_859 0x410CD6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_860 0x410CD70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_861 0x410CD74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_862 0x410CD78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_863 0x410CD7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_864 0x410CD80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_865 0x410CD84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_866 0x410CD88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_867 0x410CD8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_868 0x410CD90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_869 0x410CD94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_870 0x410CD98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_871 0x410CD9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_872 0x410CDA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_873 0x410CDA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_874 0x410CDA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_875 0x410CDAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_876 0x410CDB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_877 0x410CDB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_878 0x410CDB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_879 0x410CDBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_880 0x410CDC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_881 0x410CDC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_882 0x410CDC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_883 0x410CDCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_884 0x410CDD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_885 0x410CDD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_886 0x410CDD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_887 0x410CDDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_888 0x410CDE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_889 0x410CDE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_890 0x410CDE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_891 0x410CDEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_892 0x410CDF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_893 0x410CDF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_894 0x410CDF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_895 0x410CDFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_896 0x410CE00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_897 0x410CE04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_898 0x410CE08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_899 0x410CE0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_900 0x410CE10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_901 0x410CE14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_902 0x410CE18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_903 0x410CE1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_904 0x410CE20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_905 0x410CE24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_906 0x410CE28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_907 0x410CE2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_908 0x410CE30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_909 0x410CE34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_910 0x410CE38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_911 0x410CE3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_912 0x410CE40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_913 0x410CE44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_914 0x410CE48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_915 0x410CE4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_916 0x410CE50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_917 0x410CE54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_918 0x410CE58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_919 0x410CE5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_920 0x410CE60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_921 0x410CE64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_922 0x410CE68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_923 0x410CE6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_924 0x410CE70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_925 0x410CE74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_926 0x410CE78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_927 0x410CE7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_928 0x410CE80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_929 0x410CE84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_930 0x410CE88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_931 0x410CE8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_932 0x410CE90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_933 0x410CE94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_934 0x410CE98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_935 0x410CE9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_936 0x410CEA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_937 0x410CEA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_938 0x410CEA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_939 0x410CEAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_940 0x410CEB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_941 0x410CEB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_942 0x410CEB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_943 0x410CEBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_944 0x410CEC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_945 0x410CEC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_946 0x410CEC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_947 0x410CECC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_948 0x410CED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_949 0x410CED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_950 0x410CED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_951 0x410CEDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_952 0x410CEE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_953 0x410CEE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_954 0x410CEE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_955 0x410CEEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_956 0x410CEF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_957 0x410CEF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_958 0x410CEF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_959 0x410CEFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_960 0x410CF00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_961 0x410CF04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_962 0x410CF08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_963 0x410CF0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_964 0x410CF10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_965 0x410CF14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_966 0x410CF18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_967 0x410CF1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_968 0x410CF20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_969 0x410CF24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_970 0x410CF28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_971 0x410CF2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_972 0x410CF30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_973 0x410CF34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_974 0x410CF38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_975 0x410CF3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_976 0x410CF40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_977 0x410CF44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_978 0x410CF48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_979 0x410CF4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_980 0x410CF50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_981 0x410CF54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_982 0x410CF58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_983 0x410CF5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_984 0x410CF60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_985 0x410CF64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_986 0x410CF68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_987 0x410CF6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_988 0x410CF70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_989 0x410CF74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_990 0x410CF78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_991 0x410CF7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_992 0x410CF80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_993 0x410CF84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_994 0x410CF88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_995 0x410CF8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_996 0x410CF90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_997 0x410CF94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_998 0x410CF98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_999 0x410CF9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1000 0x410CFA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1001 0x410CFA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1002 0x410CFA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1003 0x410CFAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1004 0x410CFB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1005 0x410CFB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1006 0x410CFB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1007 0x410CFBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1008 0x410CFC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1009 0x410CFC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1010 0x410CFC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1011 0x410CFCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1012 0x410CFD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1013 0x410CFD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1014 0x410CFD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1015 0x410CFDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1016 0x410CFE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1017 0x410CFE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1018 0x410CFE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1019 0x410CFEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1020 0x410CFF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1021 0x410CFF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1022 0x410CFF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1023 0x410CFFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1024 0x410D000 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1025 0x410D004 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1026 0x410D008 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1027 0x410D00C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1028 0x410D010 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1029 0x410D014 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1030 0x410D018 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1031 0x410D01C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1032 0x410D020 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1033 0x410D024 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1034 0x410D028 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1035 0x410D02C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1036 0x410D030 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1037 0x410D034 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1038 0x410D038 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1039 0x410D03C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1040 0x410D040 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1041 0x410D044 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1042 0x410D048 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1043 0x410D04C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1044 0x410D050 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1045 0x410D054 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1046 0x410D058 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1047 0x410D05C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1048 0x410D060 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1049 0x410D064 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1050 0x410D068 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1051 0x410D06C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1052 0x410D070 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1053 0x410D074 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1054 0x410D078 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1055 0x410D07C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1056 0x410D080 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1057 0x410D084 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1058 0x410D088 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1059 0x410D08C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1060 0x410D090 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1061 0x410D094 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1062 0x410D098 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1063 0x410D09C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1064 0x410D0A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1065 0x410D0A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1066 0x410D0A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1067 0x410D0AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1068 0x410D0B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1069 0x410D0B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1070 0x410D0B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1071 0x410D0BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1072 0x410D0C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1073 0x410D0C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1074 0x410D0C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1075 0x410D0CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1076 0x410D0D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1077 0x410D0D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1078 0x410D0D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1079 0x410D0DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1080 0x410D0E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1081 0x410D0E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1082 0x410D0E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1083 0x410D0EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1084 0x410D0F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1085 0x410D0F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1086 0x410D0F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1087 0x410D0FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1088 0x410D100 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1089 0x410D104 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1090 0x410D108 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1091 0x410D10C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1092 0x410D110 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1093 0x410D114 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1094 0x410D118 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1095 0x410D11C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1096 0x410D120 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1097 0x410D124 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1098 0x410D128 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1099 0x410D12C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1100 0x410D130 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1101 0x410D134 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1102 0x410D138 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1103 0x410D13C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1104 0x410D140 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1105 0x410D144 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1106 0x410D148 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1107 0x410D14C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1108 0x410D150 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1109 0x410D154 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1110 0x410D158 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1111 0x410D15C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1112 0x410D160 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1113 0x410D164 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1114 0x410D168 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1115 0x410D16C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1116 0x410D170 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1117 0x410D174 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1118 0x410D178 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1119 0x410D17C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1120 0x410D180 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1121 0x410D184 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1122 0x410D188 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1123 0x410D18C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1124 0x410D190 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1125 0x410D194 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1126 0x410D198 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1127 0x410D19C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1128 0x410D1A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1129 0x410D1A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1130 0x410D1A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1131 0x410D1AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1132 0x410D1B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1133 0x410D1B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1134 0x410D1B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1135 0x410D1BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1136 0x410D1C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1137 0x410D1C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1138 0x410D1C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1139 0x410D1CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1140 0x410D1D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1141 0x410D1D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1142 0x410D1D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1143 0x410D1DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1144 0x410D1E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1145 0x410D1E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1146 0x410D1E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1147 0x410D1EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1148 0x410D1F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1149 0x410D1F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1150 0x410D1F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1151 0x410D1FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1152 0x410D200 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1153 0x410D204 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1154 0x410D208 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1155 0x410D20C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1156 0x410D210 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1157 0x410D214 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1158 0x410D218 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1159 0x410D21C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1160 0x410D220 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1161 0x410D224 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1162 0x410D228 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1163 0x410D22C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1164 0x410D230 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1165 0x410D234 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1166 0x410D238 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1167 0x410D23C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1168 0x410D240 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1169 0x410D244 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1170 0x410D248 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1171 0x410D24C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1172 0x410D250 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1173 0x410D254 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1174 0x410D258 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1175 0x410D25C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1176 0x410D260 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1177 0x410D264 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1178 0x410D268 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1179 0x410D26C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1180 0x410D270 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1181 0x410D274 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1182 0x410D278 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1183 0x410D27C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1184 0x410D280 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1185 0x410D284 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1186 0x410D288 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1187 0x410D28C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1188 0x410D290 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1189 0x410D294 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1190 0x410D298 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1191 0x410D29C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1192 0x410D2A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1193 0x410D2A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1194 0x410D2A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1195 0x410D2AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1196 0x410D2B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1197 0x410D2B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1198 0x410D2B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1199 0x410D2BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1200 0x410D2C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1201 0x410D2C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1202 0x410D2C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1203 0x410D2CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1204 0x410D2D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1205 0x410D2D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1206 0x410D2D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1207 0x410D2DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1208 0x410D2E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1209 0x410D2E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1210 0x410D2E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1211 0x410D2EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1212 0x410D2F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1213 0x410D2F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1214 0x410D2F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1215 0x410D2FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1216 0x410D300 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1217 0x410D304 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1218 0x410D308 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1219 0x410D30C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1220 0x410D310 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1221 0x410D314 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1222 0x410D318 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1223 0x410D31C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1224 0x410D320 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1225 0x410D324 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1226 0x410D328 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1227 0x410D32C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1228 0x410D330 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1229 0x410D334 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1230 0x410D338 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1231 0x410D33C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1232 0x410D340 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1233 0x410D344 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1234 0x410D348 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1235 0x410D34C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1236 0x410D350 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1237 0x410D354 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1238 0x410D358 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1239 0x410D35C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1240 0x410D360 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1241 0x410D364 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1242 0x410D368 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1243 0x410D36C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1244 0x410D370 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1245 0x410D374 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1246 0x410D378 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1247 0x410D37C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1248 0x410D380 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1249 0x410D384 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1250 0x410D388 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1251 0x410D38C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1252 0x410D390 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1253 0x410D394 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1254 0x410D398 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1255 0x410D39C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1256 0x410D3A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1257 0x410D3A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1258 0x410D3A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1259 0x410D3AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1260 0x410D3B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1261 0x410D3B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1262 0x410D3B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1263 0x410D3BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1264 0x410D3C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1265 0x410D3C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1266 0x410D3C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1267 0x410D3CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1268 0x410D3D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1269 0x410D3D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1270 0x410D3D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1271 0x410D3DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1272 0x410D3E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1273 0x410D3E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1274 0x410D3E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1275 0x410D3EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1276 0x410D3F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1277 0x410D3F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1278 0x410D3F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1279 0x410D3FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1280 0x410D400 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1281 0x410D404 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1282 0x410D408 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1283 0x410D40C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1284 0x410D410 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1285 0x410D414 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1286 0x410D418 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1287 0x410D41C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1288 0x410D420 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1289 0x410D424 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1290 0x410D428 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1291 0x410D42C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1292 0x410D430 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1293 0x410D434 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1294 0x410D438 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1295 0x410D43C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1296 0x410D440 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1297 0x410D444 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1298 0x410D448 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1299 0x410D44C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1300 0x410D450 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1301 0x410D454 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1302 0x410D458 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1303 0x410D45C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1304 0x410D460 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1305 0x410D464 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1306 0x410D468 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1307 0x410D46C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1308 0x410D470 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1309 0x410D474 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1310 0x410D478 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1311 0x410D47C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1312 0x410D480 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1313 0x410D484 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1314 0x410D488 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1315 0x410D48C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1316 0x410D490 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1317 0x410D494 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1318 0x410D498 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1319 0x410D49C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1320 0x410D4A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1321 0x410D4A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1322 0x410D4A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1323 0x410D4AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1324 0x410D4B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1325 0x410D4B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1326 0x410D4B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1327 0x410D4BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1328 0x410D4C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1329 0x410D4C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1330 0x410D4C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1331 0x410D4CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1332 0x410D4D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1333 0x410D4D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1334 0x410D4D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1335 0x410D4DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1336 0x410D4E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1337 0x410D4E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1338 0x410D4E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1339 0x410D4EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1340 0x410D4F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1341 0x410D4F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1342 0x410D4F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1343 0x410D4FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1344 0x410D500 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1345 0x410D504 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1346 0x410D508 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1347 0x410D50C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1348 0x410D510 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1349 0x410D514 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1350 0x410D518 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1351 0x410D51C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1352 0x410D520 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1353 0x410D524 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1354 0x410D528 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1355 0x410D52C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1356 0x410D530 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1357 0x410D534 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1358 0x410D538 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1359 0x410D53C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1360 0x410D540 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1361 0x410D544 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1362 0x410D548 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1363 0x410D54C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1364 0x410D550 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1365 0x410D554 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1366 0x410D558 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1367 0x410D55C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1368 0x410D560 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1369 0x410D564 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1370 0x410D568 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1371 0x410D56C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1372 0x410D570 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1373 0x410D574 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1374 0x410D578 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1375 0x410D57C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1376 0x410D580 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1377 0x410D584 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1378 0x410D588 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1379 0x410D58C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1380 0x410D590 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1381 0x410D594 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1382 0x410D598 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1383 0x410D59C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1384 0x410D5A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1385 0x410D5A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1386 0x410D5A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1387 0x410D5AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1388 0x410D5B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1389 0x410D5B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1390 0x410D5B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1391 0x410D5BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1392 0x410D5C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1393 0x410D5C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1394 0x410D5C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1395 0x410D5CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1396 0x410D5D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1397 0x410D5D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1398 0x410D5D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1399 0x410D5DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1400 0x410D5E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1401 0x410D5E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1402 0x410D5E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1403 0x410D5EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1404 0x410D5F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1405 0x410D5F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1406 0x410D5F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1407 0x410D5FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1408 0x410D600 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1409 0x410D604 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1410 0x410D608 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1411 0x410D60C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1412 0x410D610 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1413 0x410D614 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1414 0x410D618 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1415 0x410D61C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1416 0x410D620 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1417 0x410D624 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1418 0x410D628 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1419 0x410D62C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1420 0x410D630 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1421 0x410D634 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1422 0x410D638 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1423 0x410D63C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1424 0x410D640 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1425 0x410D644 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1426 0x410D648 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1427 0x410D64C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1428 0x410D650 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1429 0x410D654 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1430 0x410D658 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1431 0x410D65C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1432 0x410D660 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1433 0x410D664 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1434 0x410D668 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1435 0x410D66C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1436 0x410D670 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1437 0x410D674 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1438 0x410D678 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1439 0x410D67C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1440 0x410D680 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1441 0x410D684 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1442 0x410D688 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1443 0x410D68C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1444 0x410D690 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1445 0x410D694 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1446 0x410D698 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1447 0x410D69C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1448 0x410D6A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1449 0x410D6A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1450 0x410D6A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1451 0x410D6AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1452 0x410D6B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1453 0x410D6B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1454 0x410D6B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1455 0x410D6BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1456 0x410D6C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1457 0x410D6C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1458 0x410D6C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1459 0x410D6CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1460 0x410D6D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1461 0x410D6D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1462 0x410D6D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1463 0x410D6DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1464 0x410D6E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1465 0x410D6E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1466 0x410D6E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1467 0x410D6EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1468 0x410D6F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1469 0x410D6F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1470 0x410D6F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1471 0x410D6FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1472 0x410D700 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1473 0x410D704 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1474 0x410D708 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1475 0x410D70C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1476 0x410D710 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1477 0x410D714 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1478 0x410D718 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1479 0x410D71C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1480 0x410D720 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1481 0x410D724 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1482 0x410D728 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1483 0x410D72C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1484 0x410D730 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1485 0x410D734 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1486 0x410D738 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1487 0x410D73C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1488 0x410D740 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1489 0x410D744 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1490 0x410D748 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1491 0x410D74C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1492 0x410D750 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1493 0x410D754 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1494 0x410D758 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1495 0x410D75C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1496 0x410D760 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1497 0x410D764 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1498 0x410D768 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1499 0x410D76C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1500 0x410D770 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1501 0x410D774 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1502 0x410D778 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1503 0x410D77C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1504 0x410D780 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1505 0x410D784 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1506 0x410D788 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1507 0x410D78C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1508 0x410D790 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1509 0x410D794 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1510 0x410D798 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1511 0x410D79C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1512 0x410D7A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1513 0x410D7A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1514 0x410D7A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1515 0x410D7AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1516 0x410D7B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1517 0x410D7B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1518 0x410D7B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1519 0x410D7BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1520 0x410D7C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1521 0x410D7C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1522 0x410D7C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1523 0x410D7CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1524 0x410D7D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1525 0x410D7D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1526 0x410D7D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1527 0x410D7DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1528 0x410D7E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1529 0x410D7E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1530 0x410D7E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1531 0x410D7EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1532 0x410D7F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1533 0x410D7F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1534 0x410D7F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1535 0x410D7FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1536 0x410D800 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1537 0x410D804 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1538 0x410D808 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1539 0x410D80C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1540 0x410D810 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1541 0x410D814 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1542 0x410D818 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1543 0x410D81C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1544 0x410D820 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1545 0x410D824 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1546 0x410D828 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1547 0x410D82C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1548 0x410D830 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1549 0x410D834 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1550 0x410D838 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1551 0x410D83C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1552 0x410D840 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1553 0x410D844 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1554 0x410D848 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1555 0x410D84C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1556 0x410D850 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1557 0x410D854 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1558 0x410D858 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1559 0x410D85C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1560 0x410D860 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1561 0x410D864 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1562 0x410D868 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1563 0x410D86C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1564 0x410D870 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1565 0x410D874 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1566 0x410D878 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1567 0x410D87C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1568 0x410D880 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1569 0x410D884 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1570 0x410D888 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1571 0x410D88C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1572 0x410D890 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1573 0x410D894 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1574 0x410D898 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1575 0x410D89C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1576 0x410D8A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1577 0x410D8A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1578 0x410D8A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1579 0x410D8AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1580 0x410D8B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1581 0x410D8B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1582 0x410D8B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1583 0x410D8BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1584 0x410D8C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1585 0x410D8C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1586 0x410D8C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1587 0x410D8CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1588 0x410D8D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1589 0x410D8D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1590 0x410D8D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1591 0x410D8DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1592 0x410D8E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1593 0x410D8E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1594 0x410D8E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1595 0x410D8EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1596 0x410D8F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1597 0x410D8F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1598 0x410D8F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1599 0x410D8FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1600 0x410D900 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1601 0x410D904 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1602 0x410D908 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1603 0x410D90C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1604 0x410D910 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1605 0x410D914 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1606 0x410D918 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1607 0x410D91C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1608 0x410D920 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1609 0x410D924 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1610 0x410D928 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1611 0x410D92C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1612 0x410D930 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1613 0x410D934 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1614 0x410D938 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1615 0x410D93C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1616 0x410D940 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1617 0x410D944 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1618 0x410D948 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1619 0x410D94C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1620 0x410D950 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1621 0x410D954 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1622 0x410D958 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1623 0x410D95C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1624 0x410D960 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1625 0x410D964 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1626 0x410D968 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1627 0x410D96C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1628 0x410D970 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1629 0x410D974 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1630 0x410D978 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1631 0x410D97C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1632 0x410D980 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1633 0x410D984 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1634 0x410D988 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1635 0x410D98C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1636 0x410D990 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1637 0x410D994 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1638 0x410D998 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1639 0x410D99C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1640 0x410D9A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1641 0x410D9A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1642 0x410D9A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1643 0x410D9AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1644 0x410D9B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1645 0x410D9B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1646 0x410D9B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1647 0x410D9BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1648 0x410D9C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1649 0x410D9C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1650 0x410D9C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1651 0x410D9CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1652 0x410D9D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1653 0x410D9D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1654 0x410D9D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1655 0x410D9DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1656 0x410D9E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1657 0x410D9E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1658 0x410D9E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1659 0x410D9EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1660 0x410D9F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1661 0x410D9F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1662 0x410D9F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1663 0x410D9FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1664 0x410DA00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1665 0x410DA04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1666 0x410DA08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1667 0x410DA0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1668 0x410DA10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1669 0x410DA14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1670 0x410DA18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1671 0x410DA1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1672 0x410DA20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1673 0x410DA24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1674 0x410DA28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1675 0x410DA2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1676 0x410DA30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1677 0x410DA34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1678 0x410DA38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1679 0x410DA3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1680 0x410DA40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1681 0x410DA44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1682 0x410DA48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1683 0x410DA4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1684 0x410DA50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1685 0x410DA54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1686 0x410DA58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1687 0x410DA5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1688 0x410DA60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1689 0x410DA64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1690 0x410DA68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1691 0x410DA6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1692 0x410DA70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1693 0x410DA74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1694 0x410DA78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1695 0x410DA7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1696 0x410DA80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1697 0x410DA84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1698 0x410DA88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1699 0x410DA8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1700 0x410DA90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1701 0x410DA94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1702 0x410DA98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1703 0x410DA9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1704 0x410DAA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1705 0x410DAA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1706 0x410DAA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1707 0x410DAAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1708 0x410DAB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1709 0x410DAB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1710 0x410DAB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1711 0x410DABC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1712 0x410DAC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1713 0x410DAC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1714 0x410DAC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1715 0x410DACC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1716 0x410DAD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1717 0x410DAD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1718 0x410DAD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1719 0x410DADC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1720 0x410DAE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1721 0x410DAE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1722 0x410DAE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1723 0x410DAEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1724 0x410DAF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1725 0x410DAF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1726 0x410DAF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1727 0x410DAFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1728 0x410DB00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1729 0x410DB04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1730 0x410DB08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1731 0x410DB0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1732 0x410DB10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1733 0x410DB14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1734 0x410DB18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1735 0x410DB1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1736 0x410DB20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1737 0x410DB24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1738 0x410DB28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1739 0x410DB2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1740 0x410DB30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1741 0x410DB34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1742 0x410DB38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1743 0x410DB3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1744 0x410DB40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1745 0x410DB44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1746 0x410DB48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1747 0x410DB4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1748 0x410DB50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1749 0x410DB54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1750 0x410DB58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1751 0x410DB5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1752 0x410DB60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1753 0x410DB64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1754 0x410DB68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1755 0x410DB6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1756 0x410DB70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1757 0x410DB74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1758 0x410DB78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1759 0x410DB7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1760 0x410DB80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1761 0x410DB84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1762 0x410DB88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1763 0x410DB8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1764 0x410DB90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1765 0x410DB94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1766 0x410DB98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1767 0x410DB9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1768 0x410DBA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1769 0x410DBA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1770 0x410DBA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1771 0x410DBAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1772 0x410DBB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1773 0x410DBB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1774 0x410DBB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1775 0x410DBBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1776 0x410DBC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1777 0x410DBC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1778 0x410DBC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1779 0x410DBCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1780 0x410DBD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1781 0x410DBD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1782 0x410DBD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1783 0x410DBDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1784 0x410DBE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1785 0x410DBE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1786 0x410DBE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1787 0x410DBEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1788 0x410DBF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1789 0x410DBF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1790 0x410DBF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1791 0x410DBFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1792 0x410DC00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1793 0x410DC04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1794 0x410DC08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1795 0x410DC0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1796 0x410DC10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1797 0x410DC14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1798 0x410DC18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1799 0x410DC1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1800 0x410DC20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1801 0x410DC24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1802 0x410DC28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1803 0x410DC2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1804 0x410DC30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1805 0x410DC34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1806 0x410DC38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1807 0x410DC3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1808 0x410DC40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1809 0x410DC44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1810 0x410DC48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1811 0x410DC4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1812 0x410DC50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1813 0x410DC54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1814 0x410DC58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1815 0x410DC5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1816 0x410DC60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1817 0x410DC64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1818 0x410DC68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1819 0x410DC6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1820 0x410DC70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1821 0x410DC74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1822 0x410DC78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1823 0x410DC7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1824 0x410DC80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1825 0x410DC84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1826 0x410DC88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1827 0x410DC8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1828 0x410DC90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1829 0x410DC94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1830 0x410DC98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1831 0x410DC9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1832 0x410DCA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1833 0x410DCA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1834 0x410DCA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1835 0x410DCAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1836 0x410DCB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1837 0x410DCB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1838 0x410DCB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1839 0x410DCBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1840 0x410DCC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1841 0x410DCC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1842 0x410DCC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1843 0x410DCCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1844 0x410DCD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1845 0x410DCD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1846 0x410DCD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1847 0x410DCDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1848 0x410DCE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1849 0x410DCE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1850 0x410DCE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1851 0x410DCEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1852 0x410DCF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1853 0x410DCF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1854 0x410DCF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1855 0x410DCFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1856 0x410DD00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1857 0x410DD04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1858 0x410DD08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1859 0x410DD0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1860 0x410DD10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1861 0x410DD14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1862 0x410DD18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1863 0x410DD1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1864 0x410DD20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1865 0x410DD24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1866 0x410DD28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1867 0x410DD2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1868 0x410DD30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1869 0x410DD34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1870 0x410DD38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1871 0x410DD3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1872 0x410DD40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1873 0x410DD44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1874 0x410DD48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1875 0x410DD4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1876 0x410DD50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1877 0x410DD54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1878 0x410DD58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1879 0x410DD5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1880 0x410DD60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1881 0x410DD64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1882 0x410DD68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1883 0x410DD6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1884 0x410DD70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1885 0x410DD74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1886 0x410DD78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1887 0x410DD7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1888 0x410DD80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1889 0x410DD84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1890 0x410DD88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1891 0x410DD8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1892 0x410DD90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1893 0x410DD94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1894 0x410DD98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1895 0x410DD9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1896 0x410DDA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1897 0x410DDA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1898 0x410DDA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1899 0x410DDAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1900 0x410DDB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1901 0x410DDB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1902 0x410DDB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1903 0x410DDBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1904 0x410DDC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1905 0x410DDC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1906 0x410DDC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1907 0x410DDCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1908 0x410DDD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1909 0x410DDD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1910 0x410DDD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1911 0x410DDDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1912 0x410DDE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1913 0x410DDE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1914 0x410DDE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1915 0x410DDEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1916 0x410DDF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1917 0x410DDF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1918 0x410DDF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1919 0x410DDFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1920 0x410DE00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1921 0x410DE04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1922 0x410DE08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1923 0x410DE0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1924 0x410DE10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1925 0x410DE14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1926 0x410DE18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1927 0x410DE1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1928 0x410DE20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1929 0x410DE24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1930 0x410DE28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1931 0x410DE2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1932 0x410DE30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1933 0x410DE34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1934 0x410DE38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1935 0x410DE3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1936 0x410DE40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1937 0x410DE44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1938 0x410DE48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1939 0x410DE4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1940 0x410DE50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1941 0x410DE54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1942 0x410DE58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1943 0x410DE5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1944 0x410DE60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1945 0x410DE64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1946 0x410DE68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1947 0x410DE6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1948 0x410DE70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1949 0x410DE74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1950 0x410DE78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1951 0x410DE7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1952 0x410DE80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1953 0x410DE84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1954 0x410DE88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1955 0x410DE8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1956 0x410DE90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1957 0x410DE94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1958 0x410DE98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1959 0x410DE9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1960 0x410DEA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1961 0x410DEA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1962 0x410DEA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1963 0x410DEAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1964 0x410DEB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1965 0x410DEB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1966 0x410DEB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1967 0x410DEBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1968 0x410DEC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1969 0x410DEC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1970 0x410DEC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1971 0x410DECC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1972 0x410DED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1973 0x410DED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1974 0x410DED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1975 0x410DEDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1976 0x410DEE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1977 0x410DEE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1978 0x410DEE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1979 0x410DEEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1980 0x410DEF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1981 0x410DEF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1982 0x410DEF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1983 0x410DEFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1984 0x410DF00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1985 0x410DF04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1986 0x410DF08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1987 0x410DF0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1988 0x410DF10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1989 0x410DF14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1990 0x410DF18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1991 0x410DF1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1992 0x410DF20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1993 0x410DF24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1994 0x410DF28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1995 0x410DF2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1996 0x410DF30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1997 0x410DF34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1998 0x410DF38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1999 0x410DF3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2000 0x410DF40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2001 0x410DF44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2002 0x410DF48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2003 0x410DF4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2004 0x410DF50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2005 0x410DF54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2006 0x410DF58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2007 0x410DF5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2008 0x410DF60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2009 0x410DF64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2010 0x410DF68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2011 0x410DF6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2012 0x410DF70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2013 0x410DF74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2014 0x410DF78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2015 0x410DF7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2016 0x410DF80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2017 0x410DF84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2018 0x410DF88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2019 0x410DF8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2020 0x410DF90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2021 0x410DF94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2022 0x410DF98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2023 0x410DF9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2024 0x410DFA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2025 0x410DFA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2026 0x410DFA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2027 0x410DFAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2028 0x410DFB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2029 0x410DFB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2030 0x410DFB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2031 0x410DFBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2032 0x410DFC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2033 0x410DFC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2034 0x410DFC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2035 0x410DFCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2036 0x410DFD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2037 0x410DFD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2038 0x410DFD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2039 0x410DFDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2040 0x410DFE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2041 0x410DFE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2042 0x410DFE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2043 0x410DFEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2044 0x410DFF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2045 0x410DFF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2046 0x410DFF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2047 0x410DFFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_0 0x410E000 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1 0x410E004 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2 0x410E008 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_3 0x410E00C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_4 0x410E010 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_5 0x410E014 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_6 0x410E018 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_7 0x410E01C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_8 0x410E020 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_9 0x410E024 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_10 0x410E028 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_11 0x410E02C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_12 0x410E030 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_13 0x410E034 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_14 0x410E038 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_15 0x410E03C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_16 0x410E040 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_17 0x410E044 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_18 0x410E048 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_19 0x410E04C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_20 0x410E050 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_21 0x410E054 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_22 0x410E058 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_23 0x410E05C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_24 0x410E060 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_25 0x410E064 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_26 0x410E068 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_27 0x410E06C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_28 0x410E070 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_29 0x410E074 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_30 0x410E078 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_31 0x410E07C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_32 0x410E080 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_33 0x410E084 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_34 0x410E088 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_35 0x410E08C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_36 0x410E090 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_37 0x410E094 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_38 0x410E098 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_39 0x410E09C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_40 0x410E0A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_41 0x410E0A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_42 0x410E0A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_43 0x410E0AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_44 0x410E0B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_45 0x410E0B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_46 0x410E0B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_47 0x410E0BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_48 0x410E0C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_49 0x410E0C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_50 0x410E0C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_51 0x410E0CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_52 0x410E0D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_53 0x410E0D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_54 0x410E0D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_55 0x410E0DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_56 0x410E0E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_57 0x410E0E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_58 0x410E0E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_59 0x410E0EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_60 0x410E0F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_61 0x410E0F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_62 0x410E0F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_63 0x410E0FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_64 0x410E100 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_65 0x410E104 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_66 0x410E108 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_67 0x410E10C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_68 0x410E110 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_69 0x410E114 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_70 0x410E118 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_71 0x410E11C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_72 0x410E120 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_73 0x410E124 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_74 0x410E128 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_75 0x410E12C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_76 0x410E130 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_77 0x410E134 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_78 0x410E138 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_79 0x410E13C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_80 0x410E140 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_81 0x410E144 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_82 0x410E148 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_83 0x410E14C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_84 0x410E150 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_85 0x410E154 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_86 0x410E158 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_87 0x410E15C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_88 0x410E160 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_89 0x410E164 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_90 0x410E168 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_91 0x410E16C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_92 0x410E170 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_93 0x410E174 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_94 0x410E178 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_95 0x410E17C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_96 0x410E180 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_97 0x410E184 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_98 0x410E188 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_99 0x410E18C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_100 0x410E190 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_101 0x410E194 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_102 0x410E198 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_103 0x410E19C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_104 0x410E1A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_105 0x410E1A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_106 0x410E1A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_107 0x410E1AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_108 0x410E1B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_109 0x410E1B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_110 0x410E1B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_111 0x410E1BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_112 0x410E1C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_113 0x410E1C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_114 0x410E1C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_115 0x410E1CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_116 0x410E1D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_117 0x410E1D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_118 0x410E1D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_119 0x410E1DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_120 0x410E1E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_121 0x410E1E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_122 0x410E1E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_123 0x410E1EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_124 0x410E1F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_125 0x410E1F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_126 0x410E1F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_127 0x410E1FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_128 0x410E200 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_129 0x410E204 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_130 0x410E208 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_131 0x410E20C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_132 0x410E210 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_133 0x410E214 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_134 0x410E218 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_135 0x410E21C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_136 0x410E220 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_137 0x410E224 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_138 0x410E228 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_139 0x410E22C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_140 0x410E230 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_141 0x410E234 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_142 0x410E238 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_143 0x410E23C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_144 0x410E240 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_145 0x410E244 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_146 0x410E248 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_147 0x410E24C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_148 0x410E250 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_149 0x410E254 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_150 0x410E258 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_151 0x410E25C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_152 0x410E260 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_153 0x410E264 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_154 0x410E268 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_155 0x410E26C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_156 0x410E270 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_157 0x410E274 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_158 0x410E278 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_159 0x410E27C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_160 0x410E280 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_161 0x410E284 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_162 0x410E288 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_163 0x410E28C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_164 0x410E290 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_165 0x410E294 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_166 0x410E298 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_167 0x410E29C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_168 0x410E2A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_169 0x410E2A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_170 0x410E2A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_171 0x410E2AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_172 0x410E2B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_173 0x410E2B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_174 0x410E2B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_175 0x410E2BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_176 0x410E2C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_177 0x410E2C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_178 0x410E2C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_179 0x410E2CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_180 0x410E2D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_181 0x410E2D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_182 0x410E2D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_183 0x410E2DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_184 0x410E2E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_185 0x410E2E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_186 0x410E2E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_187 0x410E2EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_188 0x410E2F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_189 0x410E2F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_190 0x410E2F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_191 0x410E2FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_192 0x410E300 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_193 0x410E304 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_194 0x410E308 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_195 0x410E30C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_196 0x410E310 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_197 0x410E314 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_198 0x410E318 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_199 0x410E31C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_200 0x410E320 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_201 0x410E324 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_202 0x410E328 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_203 0x410E32C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_204 0x410E330 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_205 0x410E334 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_206 0x410E338 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_207 0x410E33C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_208 0x410E340 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_209 0x410E344 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_210 0x410E348 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_211 0x410E34C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_212 0x410E350 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_213 0x410E354 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_214 0x410E358 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_215 0x410E35C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_216 0x410E360 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_217 0x410E364 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_218 0x410E368 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_219 0x410E36C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_220 0x410E370 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_221 0x410E374 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_222 0x410E378 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_223 0x410E37C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_224 0x410E380 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_225 0x410E384 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_226 0x410E388 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_227 0x410E38C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_228 0x410E390 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_229 0x410E394 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_230 0x410E398 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_231 0x410E39C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_232 0x410E3A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_233 0x410E3A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_234 0x410E3A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_235 0x410E3AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_236 0x410E3B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_237 0x410E3B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_238 0x410E3B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_239 0x410E3BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_240 0x410E3C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_241 0x410E3C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_242 0x410E3C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_243 0x410E3CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_244 0x410E3D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_245 0x410E3D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_246 0x410E3D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_247 0x410E3DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_248 0x410E3E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_249 0x410E3E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_250 0x410E3E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_251 0x410E3EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_252 0x410E3F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_253 0x410E3F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_254 0x410E3F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_255 0x410E3FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_256 0x410E400 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_257 0x410E404 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_258 0x410E408 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_259 0x410E40C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_260 0x410E410 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_261 0x410E414 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_262 0x410E418 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_263 0x410E41C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_264 0x410E420 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_265 0x410E424 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_266 0x410E428 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_267 0x410E42C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_268 0x410E430 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_269 0x410E434 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_270 0x410E438 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_271 0x410E43C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_272 0x410E440 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_273 0x410E444 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_274 0x410E448 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_275 0x410E44C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_276 0x410E450 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_277 0x410E454 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_278 0x410E458 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_279 0x410E45C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_280 0x410E460 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_281 0x410E464 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_282 0x410E468 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_283 0x410E46C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_284 0x410E470 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_285 0x410E474 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_286 0x410E478 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_287 0x410E47C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_288 0x410E480 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_289 0x410E484 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_290 0x410E488 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_291 0x410E48C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_292 0x410E490 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_293 0x410E494 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_294 0x410E498 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_295 0x410E49C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_296 0x410E4A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_297 0x410E4A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_298 0x410E4A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_299 0x410E4AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_300 0x410E4B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_301 0x410E4B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_302 0x410E4B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_303 0x410E4BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_304 0x410E4C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_305 0x410E4C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_306 0x410E4C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_307 0x410E4CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_308 0x410E4D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_309 0x410E4D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_310 0x410E4D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_311 0x410E4DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_312 0x410E4E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_313 0x410E4E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_314 0x410E4E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_315 0x410E4EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_316 0x410E4F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_317 0x410E4F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_318 0x410E4F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_319 0x410E4FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_320 0x410E500 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_321 0x410E504 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_322 0x410E508 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_323 0x410E50C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_324 0x410E510 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_325 0x410E514 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_326 0x410E518 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_327 0x410E51C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_328 0x410E520 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_329 0x410E524 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_330 0x410E528 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_331 0x410E52C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_332 0x410E530 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_333 0x410E534 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_334 0x410E538 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_335 0x410E53C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_336 0x410E540 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_337 0x410E544 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_338 0x410E548 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_339 0x410E54C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_340 0x410E550 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_341 0x410E554 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_342 0x410E558 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_343 0x410E55C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_344 0x410E560 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_345 0x410E564 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_346 0x410E568 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_347 0x410E56C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_348 0x410E570 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_349 0x410E574 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_350 0x410E578 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_351 0x410E57C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_352 0x410E580 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_353 0x410E584 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_354 0x410E588 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_355 0x410E58C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_356 0x410E590 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_357 0x410E594 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_358 0x410E598 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_359 0x410E59C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_360 0x410E5A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_361 0x410E5A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_362 0x410E5A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_363 0x410E5AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_364 0x410E5B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_365 0x410E5B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_366 0x410E5B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_367 0x410E5BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_368 0x410E5C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_369 0x410E5C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_370 0x410E5C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_371 0x410E5CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_372 0x410E5D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_373 0x410E5D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_374 0x410E5D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_375 0x410E5DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_376 0x410E5E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_377 0x410E5E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_378 0x410E5E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_379 0x410E5EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_380 0x410E5F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_381 0x410E5F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_382 0x410E5F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_383 0x410E5FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_384 0x410E600 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_385 0x410E604 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_386 0x410E608 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_387 0x410E60C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_388 0x410E610 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_389 0x410E614 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_390 0x410E618 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_391 0x410E61C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_392 0x410E620 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_393 0x410E624 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_394 0x410E628 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_395 0x410E62C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_396 0x410E630 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_397 0x410E634 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_398 0x410E638 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_399 0x410E63C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_400 0x410E640 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_401 0x410E644 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_402 0x410E648 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_403 0x410E64C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_404 0x410E650 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_405 0x410E654 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_406 0x410E658 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_407 0x410E65C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_408 0x410E660 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_409 0x410E664 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_410 0x410E668 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_411 0x410E66C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_412 0x410E670 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_413 0x410E674 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_414 0x410E678 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_415 0x410E67C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_416 0x410E680 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_417 0x410E684 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_418 0x410E688 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_419 0x410E68C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_420 0x410E690 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_421 0x410E694 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_422 0x410E698 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_423 0x410E69C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_424 0x410E6A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_425 0x410E6A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_426 0x410E6A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_427 0x410E6AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_428 0x410E6B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_429 0x410E6B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_430 0x410E6B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_431 0x410E6BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_432 0x410E6C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_433 0x410E6C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_434 0x410E6C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_435 0x410E6CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_436 0x410E6D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_437 0x410E6D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_438 0x410E6D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_439 0x410E6DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_440 0x410E6E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_441 0x410E6E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_442 0x410E6E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_443 0x410E6EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_444 0x410E6F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_445 0x410E6F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_446 0x410E6F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_447 0x410E6FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_448 0x410E700 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_449 0x410E704 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_450 0x410E708 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_451 0x410E70C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_452 0x410E710 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_453 0x410E714 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_454 0x410E718 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_455 0x410E71C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_456 0x410E720 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_457 0x410E724 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_458 0x410E728 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_459 0x410E72C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_460 0x410E730 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_461 0x410E734 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_462 0x410E738 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_463 0x410E73C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_464 0x410E740 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_465 0x410E744 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_466 0x410E748 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_467 0x410E74C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_468 0x410E750 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_469 0x410E754 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_470 0x410E758 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_471 0x410E75C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_472 0x410E760 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_473 0x410E764 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_474 0x410E768 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_475 0x410E76C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_476 0x410E770 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_477 0x410E774 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_478 0x410E778 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_479 0x410E77C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_480 0x410E780 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_481 0x410E784 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_482 0x410E788 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_483 0x410E78C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_484 0x410E790 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_485 0x410E794 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_486 0x410E798 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_487 0x410E79C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_488 0x410E7A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_489 0x410E7A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_490 0x410E7A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_491 0x410E7AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_492 0x410E7B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_493 0x410E7B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_494 0x410E7B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_495 0x410E7BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_496 0x410E7C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_497 0x410E7C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_498 0x410E7C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_499 0x410E7CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_500 0x410E7D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_501 0x410E7D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_502 0x410E7D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_503 0x410E7DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_504 0x410E7E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_505 0x410E7E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_506 0x410E7E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_507 0x410E7EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_508 0x410E7F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_509 0x410E7F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_510 0x410E7F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_511 0x410E7FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_512 0x410E800 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_513 0x410E804 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_514 0x410E808 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_515 0x410E80C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_516 0x410E810 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_517 0x410E814 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_518 0x410E818 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_519 0x410E81C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_520 0x410E820 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_521 0x410E824 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_522 0x410E828 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_523 0x410E82C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_524 0x410E830 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_525 0x410E834 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_526 0x410E838 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_527 0x410E83C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_528 0x410E840 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_529 0x410E844 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_530 0x410E848 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_531 0x410E84C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_532 0x410E850 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_533 0x410E854 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_534 0x410E858 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_535 0x410E85C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_536 0x410E860 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_537 0x410E864 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_538 0x410E868 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_539 0x410E86C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_540 0x410E870 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_541 0x410E874 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_542 0x410E878 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_543 0x410E87C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_544 0x410E880 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_545 0x410E884 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_546 0x410E888 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_547 0x410E88C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_548 0x410E890 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_549 0x410E894 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_550 0x410E898 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_551 0x410E89C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_552 0x410E8A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_553 0x410E8A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_554 0x410E8A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_555 0x410E8AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_556 0x410E8B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_557 0x410E8B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_558 0x410E8B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_559 0x410E8BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_560 0x410E8C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_561 0x410E8C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_562 0x410E8C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_563 0x410E8CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_564 0x410E8D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_565 0x410E8D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_566 0x410E8D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_567 0x410E8DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_568 0x410E8E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_569 0x410E8E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_570 0x410E8E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_571 0x410E8EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_572 0x410E8F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_573 0x410E8F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_574 0x410E8F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_575 0x410E8FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_576 0x410E900 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_577 0x410E904 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_578 0x410E908 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_579 0x410E90C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_580 0x410E910 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_581 0x410E914 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_582 0x410E918 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_583 0x410E91C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_584 0x410E920 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_585 0x410E924 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_586 0x410E928 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_587 0x410E92C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_588 0x410E930 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_589 0x410E934 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_590 0x410E938 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_591 0x410E93C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_592 0x410E940 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_593 0x410E944 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_594 0x410E948 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_595 0x410E94C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_596 0x410E950 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_597 0x410E954 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_598 0x410E958 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_599 0x410E95C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_600 0x410E960 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_601 0x410E964 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_602 0x410E968 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_603 0x410E96C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_604 0x410E970 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_605 0x410E974 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_606 0x410E978 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_607 0x410E97C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_608 0x410E980 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_609 0x410E984 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_610 0x410E988 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_611 0x410E98C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_612 0x410E990 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_613 0x410E994 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_614 0x410E998 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_615 0x410E99C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_616 0x410E9A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_617 0x410E9A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_618 0x410E9A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_619 0x410E9AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_620 0x410E9B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_621 0x410E9B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_622 0x410E9B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_623 0x410E9BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_624 0x410E9C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_625 0x410E9C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_626 0x410E9C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_627 0x410E9CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_628 0x410E9D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_629 0x410E9D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_630 0x410E9D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_631 0x410E9DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_632 0x410E9E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_633 0x410E9E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_634 0x410E9E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_635 0x410E9EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_636 0x410E9F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_637 0x410E9F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_638 0x410E9F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_639 0x410E9FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_640 0x410EA00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_641 0x410EA04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_642 0x410EA08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_643 0x410EA0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_644 0x410EA10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_645 0x410EA14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_646 0x410EA18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_647 0x410EA1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_648 0x410EA20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_649 0x410EA24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_650 0x410EA28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_651 0x410EA2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_652 0x410EA30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_653 0x410EA34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_654 0x410EA38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_655 0x410EA3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_656 0x410EA40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_657 0x410EA44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_658 0x410EA48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_659 0x410EA4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_660 0x410EA50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_661 0x410EA54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_662 0x410EA58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_663 0x410EA5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_664 0x410EA60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_665 0x410EA64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_666 0x410EA68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_667 0x410EA6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_668 0x410EA70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_669 0x410EA74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_670 0x410EA78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_671 0x410EA7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_672 0x410EA80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_673 0x410EA84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_674 0x410EA88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_675 0x410EA8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_676 0x410EA90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_677 0x410EA94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_678 0x410EA98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_679 0x410EA9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_680 0x410EAA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_681 0x410EAA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_682 0x410EAA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_683 0x410EAAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_684 0x410EAB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_685 0x410EAB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_686 0x410EAB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_687 0x410EABC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_688 0x410EAC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_689 0x410EAC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_690 0x410EAC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_691 0x410EACC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_692 0x410EAD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_693 0x410EAD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_694 0x410EAD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_695 0x410EADC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_696 0x410EAE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_697 0x410EAE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_698 0x410EAE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_699 0x410EAEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_700 0x410EAF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_701 0x410EAF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_702 0x410EAF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_703 0x410EAFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_704 0x410EB00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_705 0x410EB04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_706 0x410EB08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_707 0x410EB0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_708 0x410EB10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_709 0x410EB14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_710 0x410EB18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_711 0x410EB1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_712 0x410EB20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_713 0x410EB24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_714 0x410EB28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_715 0x410EB2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_716 0x410EB30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_717 0x410EB34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_718 0x410EB38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_719 0x410EB3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_720 0x410EB40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_721 0x410EB44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_722 0x410EB48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_723 0x410EB4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_724 0x410EB50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_725 0x410EB54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_726 0x410EB58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_727 0x410EB5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_728 0x410EB60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_729 0x410EB64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_730 0x410EB68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_731 0x410EB6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_732 0x410EB70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_733 0x410EB74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_734 0x410EB78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_735 0x410EB7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_736 0x410EB80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_737 0x410EB84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_738 0x410EB88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_739 0x410EB8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_740 0x410EB90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_741 0x410EB94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_742 0x410EB98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_743 0x410EB9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_744 0x410EBA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_745 0x410EBA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_746 0x410EBA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_747 0x410EBAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_748 0x410EBB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_749 0x410EBB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_750 0x410EBB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_751 0x410EBBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_752 0x410EBC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_753 0x410EBC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_754 0x410EBC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_755 0x410EBCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_756 0x410EBD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_757 0x410EBD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_758 0x410EBD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_759 0x410EBDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_760 0x410EBE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_761 0x410EBE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_762 0x410EBE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_763 0x410EBEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_764 0x410EBF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_765 0x410EBF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_766 0x410EBF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_767 0x410EBFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_768 0x410EC00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_769 0x410EC04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_770 0x410EC08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_771 0x410EC0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_772 0x410EC10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_773 0x410EC14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_774 0x410EC18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_775 0x410EC1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_776 0x410EC20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_777 0x410EC24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_778 0x410EC28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_779 0x410EC2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_780 0x410EC30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_781 0x410EC34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_782 0x410EC38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_783 0x410EC3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_784 0x410EC40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_785 0x410EC44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_786 0x410EC48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_787 0x410EC4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_788 0x410EC50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_789 0x410EC54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_790 0x410EC58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_791 0x410EC5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_792 0x410EC60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_793 0x410EC64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_794 0x410EC68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_795 0x410EC6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_796 0x410EC70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_797 0x410EC74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_798 0x410EC78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_799 0x410EC7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_800 0x410EC80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_801 0x410EC84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_802 0x410EC88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_803 0x410EC8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_804 0x410EC90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_805 0x410EC94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_806 0x410EC98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_807 0x410EC9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_808 0x410ECA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_809 0x410ECA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_810 0x410ECA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_811 0x410ECAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_812 0x410ECB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_813 0x410ECB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_814 0x410ECB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_815 0x410ECBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_816 0x410ECC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_817 0x410ECC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_818 0x410ECC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_819 0x410ECCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_820 0x410ECD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_821 0x410ECD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_822 0x410ECD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_823 0x410ECDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_824 0x410ECE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_825 0x410ECE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_826 0x410ECE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_827 0x410ECEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_828 0x410ECF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_829 0x410ECF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_830 0x410ECF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_831 0x410ECFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_832 0x410ED00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_833 0x410ED04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_834 0x410ED08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_835 0x410ED0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_836 0x410ED10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_837 0x410ED14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_838 0x410ED18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_839 0x410ED1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_840 0x410ED20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_841 0x410ED24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_842 0x410ED28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_843 0x410ED2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_844 0x410ED30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_845 0x410ED34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_846 0x410ED38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_847 0x410ED3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_848 0x410ED40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_849 0x410ED44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_850 0x410ED48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_851 0x410ED4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_852 0x410ED50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_853 0x410ED54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_854 0x410ED58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_855 0x410ED5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_856 0x410ED60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_857 0x410ED64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_858 0x410ED68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_859 0x410ED6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_860 0x410ED70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_861 0x410ED74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_862 0x410ED78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_863 0x410ED7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_864 0x410ED80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_865 0x410ED84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_866 0x410ED88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_867 0x410ED8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_868 0x410ED90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_869 0x410ED94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_870 0x410ED98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_871 0x410ED9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_872 0x410EDA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_873 0x410EDA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_874 0x410EDA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_875 0x410EDAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_876 0x410EDB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_877 0x410EDB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_878 0x410EDB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_879 0x410EDBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_880 0x410EDC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_881 0x410EDC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_882 0x410EDC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_883 0x410EDCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_884 0x410EDD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_885 0x410EDD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_886 0x410EDD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_887 0x410EDDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_888 0x410EDE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_889 0x410EDE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_890 0x410EDE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_891 0x410EDEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_892 0x410EDF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_893 0x410EDF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_894 0x410EDF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_895 0x410EDFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_896 0x410EE00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_897 0x410EE04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_898 0x410EE08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_899 0x410EE0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_900 0x410EE10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_901 0x410EE14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_902 0x410EE18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_903 0x410EE1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_904 0x410EE20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_905 0x410EE24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_906 0x410EE28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_907 0x410EE2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_908 0x410EE30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_909 0x410EE34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_910 0x410EE38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_911 0x410EE3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_912 0x410EE40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_913 0x410EE44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_914 0x410EE48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_915 0x410EE4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_916 0x410EE50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_917 0x410EE54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_918 0x410EE58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_919 0x410EE5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_920 0x410EE60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_921 0x410EE64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_922 0x410EE68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_923 0x410EE6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_924 0x410EE70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_925 0x410EE74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_926 0x410EE78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_927 0x410EE7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_928 0x410EE80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_929 0x410EE84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_930 0x410EE88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_931 0x410EE8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_932 0x410EE90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_933 0x410EE94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_934 0x410EE98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_935 0x410EE9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_936 0x410EEA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_937 0x410EEA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_938 0x410EEA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_939 0x410EEAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_940 0x410EEB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_941 0x410EEB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_942 0x410EEB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_943 0x410EEBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_944 0x410EEC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_945 0x410EEC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_946 0x410EEC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_947 0x410EECC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_948 0x410EED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_949 0x410EED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_950 0x410EED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_951 0x410EEDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_952 0x410EEE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_953 0x410EEE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_954 0x410EEE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_955 0x410EEEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_956 0x410EEF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_957 0x410EEF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_958 0x410EEF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_959 0x410EEFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_960 0x410EF00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_961 0x410EF04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_962 0x410EF08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_963 0x410EF0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_964 0x410EF10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_965 0x410EF14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_966 0x410EF18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_967 0x410EF1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_968 0x410EF20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_969 0x410EF24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_970 0x410EF28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_971 0x410EF2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_972 0x410EF30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_973 0x410EF34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_974 0x410EF38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_975 0x410EF3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_976 0x410EF40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_977 0x410EF44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_978 0x410EF48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_979 0x410EF4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_980 0x410EF50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_981 0x410EF54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_982 0x410EF58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_983 0x410EF5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_984 0x410EF60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_985 0x410EF64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_986 0x410EF68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_987 0x410EF6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_988 0x410EF70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_989 0x410EF74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_990 0x410EF78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_991 0x410EF7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_992 0x410EF80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_993 0x410EF84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_994 0x410EF88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_995 0x410EF8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_996 0x410EF90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_997 0x410EF94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_998 0x410EF98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_999 0x410EF9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1000 0x410EFA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1001 0x410EFA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1002 0x410EFA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1003 0x410EFAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1004 0x410EFB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1005 0x410EFB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1006 0x410EFB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1007 0x410EFBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1008 0x410EFC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1009 0x410EFC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1010 0x410EFC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1011 0x410EFCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1012 0x410EFD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1013 0x410EFD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1014 0x410EFD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1015 0x410EFDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1016 0x410EFE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1017 0x410EFE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1018 0x410EFE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1019 0x410EFEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1020 0x410EFF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1021 0x410EFF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1022 0x410EFF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1023 0x410EFFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1024 0x410F000 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1025 0x410F004 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1026 0x410F008 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1027 0x410F00C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1028 0x410F010 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1029 0x410F014 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1030 0x410F018 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1031 0x410F01C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1032 0x410F020 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1033 0x410F024 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1034 0x410F028 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1035 0x410F02C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1036 0x410F030 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1037 0x410F034 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1038 0x410F038 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1039 0x410F03C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1040 0x410F040 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1041 0x410F044 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1042 0x410F048 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1043 0x410F04C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1044 0x410F050 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1045 0x410F054 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1046 0x410F058 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1047 0x410F05C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1048 0x410F060 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1049 0x410F064 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1050 0x410F068 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1051 0x410F06C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1052 0x410F070 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1053 0x410F074 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1054 0x410F078 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1055 0x410F07C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1056 0x410F080 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1057 0x410F084 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1058 0x410F088 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1059 0x410F08C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1060 0x410F090 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1061 0x410F094 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1062 0x410F098 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1063 0x410F09C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1064 0x410F0A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1065 0x410F0A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1066 0x410F0A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1067 0x410F0AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1068 0x410F0B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1069 0x410F0B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1070 0x410F0B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1071 0x410F0BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1072 0x410F0C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1073 0x410F0C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1074 0x410F0C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1075 0x410F0CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1076 0x410F0D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1077 0x410F0D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1078 0x410F0D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1079 0x410F0DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1080 0x410F0E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1081 0x410F0E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1082 0x410F0E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1083 0x410F0EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1084 0x410F0F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1085 0x410F0F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1086 0x410F0F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1087 0x410F0FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1088 0x410F100 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1089 0x410F104 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1090 0x410F108 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1091 0x410F10C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1092 0x410F110 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1093 0x410F114 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1094 0x410F118 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1095 0x410F11C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1096 0x410F120 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1097 0x410F124 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1098 0x410F128 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1099 0x410F12C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1100 0x410F130 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1101 0x410F134 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1102 0x410F138 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1103 0x410F13C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1104 0x410F140 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1105 0x410F144 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1106 0x410F148 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1107 0x410F14C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1108 0x410F150 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1109 0x410F154 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1110 0x410F158 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1111 0x410F15C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1112 0x410F160 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1113 0x410F164 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1114 0x410F168 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1115 0x410F16C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1116 0x410F170 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1117 0x410F174 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1118 0x410F178 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1119 0x410F17C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1120 0x410F180 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1121 0x410F184 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1122 0x410F188 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1123 0x410F18C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1124 0x410F190 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1125 0x410F194 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1126 0x410F198 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1127 0x410F19C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1128 0x410F1A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1129 0x410F1A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1130 0x410F1A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1131 0x410F1AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1132 0x410F1B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1133 0x410F1B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1134 0x410F1B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1135 0x410F1BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1136 0x410F1C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1137 0x410F1C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1138 0x410F1C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1139 0x410F1CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1140 0x410F1D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1141 0x410F1D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1142 0x410F1D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1143 0x410F1DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1144 0x410F1E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1145 0x410F1E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1146 0x410F1E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1147 0x410F1EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1148 0x410F1F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1149 0x410F1F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1150 0x410F1F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1151 0x410F1FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1152 0x410F200 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1153 0x410F204 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1154 0x410F208 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1155 0x410F20C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1156 0x410F210 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1157 0x410F214 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1158 0x410F218 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1159 0x410F21C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1160 0x410F220 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1161 0x410F224 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1162 0x410F228 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1163 0x410F22C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1164 0x410F230 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1165 0x410F234 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1166 0x410F238 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1167 0x410F23C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1168 0x410F240 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1169 0x410F244 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1170 0x410F248 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1171 0x410F24C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1172 0x410F250 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1173 0x410F254 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1174 0x410F258 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1175 0x410F25C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1176 0x410F260 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1177 0x410F264 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1178 0x410F268 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1179 0x410F26C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1180 0x410F270 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1181 0x410F274 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1182 0x410F278 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1183 0x410F27C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1184 0x410F280 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1185 0x410F284 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1186 0x410F288 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1187 0x410F28C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1188 0x410F290 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1189 0x410F294 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1190 0x410F298 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1191 0x410F29C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1192 0x410F2A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1193 0x410F2A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1194 0x410F2A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1195 0x410F2AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1196 0x410F2B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1197 0x410F2B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1198 0x410F2B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1199 0x410F2BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1200 0x410F2C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1201 0x410F2C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1202 0x410F2C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1203 0x410F2CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1204 0x410F2D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1205 0x410F2D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1206 0x410F2D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1207 0x410F2DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1208 0x410F2E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1209 0x410F2E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1210 0x410F2E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1211 0x410F2EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1212 0x410F2F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1213 0x410F2F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1214 0x410F2F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1215 0x410F2FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1216 0x410F300 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1217 0x410F304 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1218 0x410F308 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1219 0x410F30C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1220 0x410F310 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1221 0x410F314 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1222 0x410F318 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1223 0x410F31C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1224 0x410F320 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1225 0x410F324 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1226 0x410F328 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1227 0x410F32C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1228 0x410F330 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1229 0x410F334 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1230 0x410F338 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1231 0x410F33C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1232 0x410F340 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1233 0x410F344 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1234 0x410F348 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1235 0x410F34C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1236 0x410F350 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1237 0x410F354 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1238 0x410F358 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1239 0x410F35C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1240 0x410F360 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1241 0x410F364 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1242 0x410F368 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1243 0x410F36C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1244 0x410F370 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1245 0x410F374 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1246 0x410F378 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1247 0x410F37C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1248 0x410F380 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1249 0x410F384 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1250 0x410F388 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1251 0x410F38C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1252 0x410F390 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1253 0x410F394 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1254 0x410F398 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1255 0x410F39C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1256 0x410F3A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1257 0x410F3A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1258 0x410F3A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1259 0x410F3AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1260 0x410F3B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1261 0x410F3B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1262 0x410F3B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1263 0x410F3BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1264 0x410F3C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1265 0x410F3C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1266 0x410F3C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1267 0x410F3CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1268 0x410F3D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1269 0x410F3D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1270 0x410F3D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1271 0x410F3DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1272 0x410F3E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1273 0x410F3E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1274 0x410F3E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1275 0x410F3EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1276 0x410F3F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1277 0x410F3F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1278 0x410F3F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1279 0x410F3FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1280 0x410F400 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1281 0x410F404 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1282 0x410F408 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1283 0x410F40C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1284 0x410F410 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1285 0x410F414 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1286 0x410F418 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1287 0x410F41C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1288 0x410F420 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1289 0x410F424 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1290 0x410F428 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1291 0x410F42C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1292 0x410F430 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1293 0x410F434 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1294 0x410F438 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1295 0x410F43C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1296 0x410F440 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1297 0x410F444 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1298 0x410F448 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1299 0x410F44C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1300 0x410F450 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1301 0x410F454 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1302 0x410F458 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1303 0x410F45C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1304 0x410F460 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1305 0x410F464 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1306 0x410F468 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1307 0x410F46C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1308 0x410F470 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1309 0x410F474 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1310 0x410F478 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1311 0x410F47C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1312 0x410F480 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1313 0x410F484 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1314 0x410F488 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1315 0x410F48C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1316 0x410F490 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1317 0x410F494 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1318 0x410F498 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1319 0x410F49C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1320 0x410F4A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1321 0x410F4A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1322 0x410F4A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1323 0x410F4AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1324 0x410F4B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1325 0x410F4B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1326 0x410F4B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1327 0x410F4BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1328 0x410F4C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1329 0x410F4C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1330 0x410F4C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1331 0x410F4CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1332 0x410F4D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1333 0x410F4D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1334 0x410F4D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1335 0x410F4DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1336 0x410F4E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1337 0x410F4E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1338 0x410F4E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1339 0x410F4EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1340 0x410F4F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1341 0x410F4F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1342 0x410F4F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1343 0x410F4FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1344 0x410F500 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1345 0x410F504 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1346 0x410F508 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1347 0x410F50C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1348 0x410F510 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1349 0x410F514 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1350 0x410F518 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1351 0x410F51C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1352 0x410F520 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1353 0x410F524 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1354 0x410F528 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1355 0x410F52C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1356 0x410F530 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1357 0x410F534 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1358 0x410F538 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1359 0x410F53C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1360 0x410F540 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1361 0x410F544 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1362 0x410F548 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1363 0x410F54C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1364 0x410F550 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1365 0x410F554 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1366 0x410F558 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1367 0x410F55C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1368 0x410F560 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1369 0x410F564 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1370 0x410F568 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1371 0x410F56C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1372 0x410F570 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1373 0x410F574 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1374 0x410F578 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1375 0x410F57C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1376 0x410F580 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1377 0x410F584 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1378 0x410F588 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1379 0x410F58C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1380 0x410F590 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1381 0x410F594 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1382 0x410F598 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1383 0x410F59C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1384 0x410F5A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1385 0x410F5A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1386 0x410F5A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1387 0x410F5AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1388 0x410F5B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1389 0x410F5B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1390 0x410F5B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1391 0x410F5BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1392 0x410F5C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1393 0x410F5C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1394 0x410F5C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1395 0x410F5CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1396 0x410F5D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1397 0x410F5D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1398 0x410F5D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1399 0x410F5DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1400 0x410F5E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1401 0x410F5E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1402 0x410F5E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1403 0x410F5EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1404 0x410F5F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1405 0x410F5F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1406 0x410F5F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1407 0x410F5FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1408 0x410F600 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1409 0x410F604 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1410 0x410F608 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1411 0x410F60C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1412 0x410F610 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1413 0x410F614 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1414 0x410F618 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1415 0x410F61C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1416 0x410F620 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1417 0x410F624 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1418 0x410F628 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1419 0x410F62C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1420 0x410F630 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1421 0x410F634 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1422 0x410F638 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1423 0x410F63C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1424 0x410F640 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1425 0x410F644 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1426 0x410F648 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1427 0x410F64C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1428 0x410F650 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1429 0x410F654 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1430 0x410F658 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1431 0x410F65C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1432 0x410F660 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1433 0x410F664 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1434 0x410F668 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1435 0x410F66C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1436 0x410F670 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1437 0x410F674 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1438 0x410F678 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1439 0x410F67C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1440 0x410F680 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1441 0x410F684 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1442 0x410F688 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1443 0x410F68C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1444 0x410F690 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1445 0x410F694 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1446 0x410F698 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1447 0x410F69C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1448 0x410F6A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1449 0x410F6A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1450 0x410F6A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1451 0x410F6AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1452 0x410F6B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1453 0x410F6B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1454 0x410F6B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1455 0x410F6BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1456 0x410F6C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1457 0x410F6C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1458 0x410F6C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1459 0x410F6CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1460 0x410F6D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1461 0x410F6D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1462 0x410F6D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1463 0x410F6DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1464 0x410F6E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1465 0x410F6E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1466 0x410F6E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1467 0x410F6EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1468 0x410F6F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1469 0x410F6F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1470 0x410F6F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1471 0x410F6FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1472 0x410F700 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1473 0x410F704 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1474 0x410F708 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1475 0x410F70C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1476 0x410F710 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1477 0x410F714 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1478 0x410F718 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1479 0x410F71C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1480 0x410F720 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1481 0x410F724 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1482 0x410F728 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1483 0x410F72C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1484 0x410F730 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1485 0x410F734 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1486 0x410F738 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1487 0x410F73C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1488 0x410F740 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1489 0x410F744 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1490 0x410F748 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1491 0x410F74C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1492 0x410F750 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1493 0x410F754 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1494 0x410F758 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1495 0x410F75C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1496 0x410F760 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1497 0x410F764 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1498 0x410F768 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1499 0x410F76C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1500 0x410F770 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1501 0x410F774 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1502 0x410F778 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1503 0x410F77C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1504 0x410F780 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1505 0x410F784 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1506 0x410F788 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1507 0x410F78C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1508 0x410F790 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1509 0x410F794 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1510 0x410F798 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1511 0x410F79C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1512 0x410F7A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1513 0x410F7A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1514 0x410F7A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1515 0x410F7AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1516 0x410F7B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1517 0x410F7B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1518 0x410F7B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1519 0x410F7BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1520 0x410F7C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1521 0x410F7C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1522 0x410F7C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1523 0x410F7CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1524 0x410F7D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1525 0x410F7D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1526 0x410F7D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1527 0x410F7DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1528 0x410F7E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1529 0x410F7E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1530 0x410F7E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1531 0x410F7EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1532 0x410F7F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1533 0x410F7F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1534 0x410F7F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1535 0x410F7FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1536 0x410F800 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1537 0x410F804 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1538 0x410F808 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1539 0x410F80C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1540 0x410F810 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1541 0x410F814 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1542 0x410F818 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1543 0x410F81C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1544 0x410F820 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1545 0x410F824 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1546 0x410F828 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1547 0x410F82C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1548 0x410F830 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1549 0x410F834 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1550 0x410F838 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1551 0x410F83C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1552 0x410F840 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1553 0x410F844 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1554 0x410F848 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1555 0x410F84C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1556 0x410F850 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1557 0x410F854 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1558 0x410F858 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1559 0x410F85C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1560 0x410F860 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1561 0x410F864 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1562 0x410F868 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1563 0x410F86C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1564 0x410F870 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1565 0x410F874 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1566 0x410F878 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1567 0x410F87C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1568 0x410F880 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1569 0x410F884 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1570 0x410F888 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1571 0x410F88C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1572 0x410F890 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1573 0x410F894 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1574 0x410F898 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1575 0x410F89C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1576 0x410F8A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1577 0x410F8A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1578 0x410F8A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1579 0x410F8AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1580 0x410F8B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1581 0x410F8B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1582 0x410F8B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1583 0x410F8BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1584 0x410F8C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1585 0x410F8C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1586 0x410F8C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1587 0x410F8CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1588 0x410F8D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1589 0x410F8D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1590 0x410F8D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1591 0x410F8DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1592 0x410F8E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1593 0x410F8E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1594 0x410F8E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1595 0x410F8EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1596 0x410F8F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1597 0x410F8F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1598 0x410F8F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1599 0x410F8FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1600 0x410F900 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1601 0x410F904 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1602 0x410F908 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1603 0x410F90C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1604 0x410F910 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1605 0x410F914 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1606 0x410F918 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1607 0x410F91C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1608 0x410F920 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1609 0x410F924 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1610 0x410F928 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1611 0x410F92C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1612 0x410F930 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1613 0x410F934 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1614 0x410F938 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1615 0x410F93C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1616 0x410F940 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1617 0x410F944 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1618 0x410F948 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1619 0x410F94C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1620 0x410F950 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1621 0x410F954 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1622 0x410F958 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1623 0x410F95C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1624 0x410F960 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1625 0x410F964 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1626 0x410F968 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1627 0x410F96C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1628 0x410F970 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1629 0x410F974 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1630 0x410F978 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1631 0x410F97C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1632 0x410F980 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1633 0x410F984 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1634 0x410F988 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1635 0x410F98C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1636 0x410F990 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1637 0x410F994 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1638 0x410F998 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1639 0x410F99C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1640 0x410F9A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1641 0x410F9A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1642 0x410F9A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1643 0x410F9AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1644 0x410F9B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1645 0x410F9B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1646 0x410F9B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1647 0x410F9BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1648 0x410F9C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1649 0x410F9C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1650 0x410F9C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1651 0x410F9CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1652 0x410F9D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1653 0x410F9D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1654 0x410F9D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1655 0x410F9DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1656 0x410F9E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1657 0x410F9E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1658 0x410F9E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1659 0x410F9EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1660 0x410F9F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1661 0x410F9F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1662 0x410F9F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1663 0x410F9FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1664 0x410FA00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1665 0x410FA04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1666 0x410FA08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1667 0x410FA0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1668 0x410FA10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1669 0x410FA14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1670 0x410FA18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1671 0x410FA1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1672 0x410FA20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1673 0x410FA24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1674 0x410FA28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1675 0x410FA2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1676 0x410FA30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1677 0x410FA34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1678 0x410FA38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1679 0x410FA3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1680 0x410FA40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1681 0x410FA44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1682 0x410FA48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1683 0x410FA4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1684 0x410FA50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1685 0x410FA54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1686 0x410FA58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1687 0x410FA5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1688 0x410FA60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1689 0x410FA64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1690 0x410FA68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1691 0x410FA6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1692 0x410FA70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1693 0x410FA74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1694 0x410FA78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1695 0x410FA7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1696 0x410FA80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1697 0x410FA84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1698 0x410FA88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1699 0x410FA8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1700 0x410FA90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1701 0x410FA94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1702 0x410FA98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1703 0x410FA9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1704 0x410FAA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1705 0x410FAA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1706 0x410FAA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1707 0x410FAAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1708 0x410FAB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1709 0x410FAB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1710 0x410FAB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1711 0x410FABC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1712 0x410FAC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1713 0x410FAC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1714 0x410FAC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1715 0x410FACC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1716 0x410FAD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1717 0x410FAD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1718 0x410FAD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1719 0x410FADC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1720 0x410FAE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1721 0x410FAE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1722 0x410FAE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1723 0x410FAEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1724 0x410FAF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1725 0x410FAF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1726 0x410FAF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1727 0x410FAFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1728 0x410FB00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1729 0x410FB04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1730 0x410FB08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1731 0x410FB0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1732 0x410FB10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1733 0x410FB14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1734 0x410FB18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1735 0x410FB1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1736 0x410FB20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1737 0x410FB24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1738 0x410FB28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1739 0x410FB2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1740 0x410FB30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1741 0x410FB34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1742 0x410FB38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1743 0x410FB3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1744 0x410FB40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1745 0x410FB44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1746 0x410FB48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1747 0x410FB4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1748 0x410FB50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1749 0x410FB54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1750 0x410FB58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1751 0x410FB5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1752 0x410FB60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1753 0x410FB64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1754 0x410FB68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1755 0x410FB6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1756 0x410FB70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1757 0x410FB74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1758 0x410FB78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1759 0x410FB7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1760 0x410FB80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1761 0x410FB84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1762 0x410FB88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1763 0x410FB8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1764 0x410FB90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1765 0x410FB94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1766 0x410FB98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1767 0x410FB9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1768 0x410FBA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1769 0x410FBA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1770 0x410FBA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1771 0x410FBAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1772 0x410FBB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1773 0x410FBB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1774 0x410FBB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1775 0x410FBBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1776 0x410FBC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1777 0x410FBC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1778 0x410FBC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1779 0x410FBCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1780 0x410FBD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1781 0x410FBD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1782 0x410FBD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1783 0x410FBDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1784 0x410FBE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1785 0x410FBE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1786 0x410FBE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1787 0x410FBEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1788 0x410FBF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1789 0x410FBF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1790 0x410FBF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1791 0x410FBFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1792 0x410FC00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1793 0x410FC04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1794 0x410FC08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1795 0x410FC0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1796 0x410FC10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1797 0x410FC14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1798 0x410FC18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1799 0x410FC1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1800 0x410FC20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1801 0x410FC24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1802 0x410FC28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1803 0x410FC2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1804 0x410FC30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1805 0x410FC34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1806 0x410FC38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1807 0x410FC3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1808 0x410FC40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1809 0x410FC44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1810 0x410FC48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1811 0x410FC4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1812 0x410FC50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1813 0x410FC54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1814 0x410FC58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1815 0x410FC5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1816 0x410FC60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1817 0x410FC64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1818 0x410FC68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1819 0x410FC6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1820 0x410FC70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1821 0x410FC74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1822 0x410FC78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1823 0x410FC7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1824 0x410FC80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1825 0x410FC84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1826 0x410FC88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1827 0x410FC8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1828 0x410FC90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1829 0x410FC94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1830 0x410FC98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1831 0x410FC9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1832 0x410FCA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1833 0x410FCA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1834 0x410FCA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1835 0x410FCAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1836 0x410FCB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1837 0x410FCB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1838 0x410FCB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1839 0x410FCBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1840 0x410FCC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1841 0x410FCC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1842 0x410FCC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1843 0x410FCCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1844 0x410FCD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1845 0x410FCD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1846 0x410FCD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1847 0x410FCDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1848 0x410FCE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1849 0x410FCE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1850 0x410FCE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1851 0x410FCEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1852 0x410FCF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1853 0x410FCF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1854 0x410FCF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1855 0x410FCFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1856 0x410FD00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1857 0x410FD04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1858 0x410FD08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1859 0x410FD0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1860 0x410FD10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1861 0x410FD14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1862 0x410FD18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1863 0x410FD1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1864 0x410FD20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1865 0x410FD24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1866 0x410FD28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1867 0x410FD2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1868 0x410FD30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1869 0x410FD34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1870 0x410FD38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1871 0x410FD3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1872 0x410FD40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1873 0x410FD44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1874 0x410FD48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1875 0x410FD4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1876 0x410FD50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1877 0x410FD54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1878 0x410FD58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1879 0x410FD5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1880 0x410FD60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1881 0x410FD64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1882 0x410FD68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1883 0x410FD6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1884 0x410FD70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1885 0x410FD74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1886 0x410FD78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1887 0x410FD7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1888 0x410FD80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1889 0x410FD84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1890 0x410FD88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1891 0x410FD8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1892 0x410FD90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1893 0x410FD94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1894 0x410FD98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1895 0x410FD9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1896 0x410FDA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1897 0x410FDA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1898 0x410FDA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1899 0x410FDAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1900 0x410FDB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1901 0x410FDB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1902 0x410FDB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1903 0x410FDBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1904 0x410FDC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1905 0x410FDC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1906 0x410FDC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1907 0x410FDCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1908 0x410FDD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1909 0x410FDD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1910 0x410FDD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1911 0x410FDDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1912 0x410FDE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1913 0x410FDE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1914 0x410FDE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1915 0x410FDEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1916 0x410FDF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1917 0x410FDF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1918 0x410FDF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1919 0x410FDFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1920 0x410FE00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1921 0x410FE04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1922 0x410FE08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1923 0x410FE0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1924 0x410FE10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1925 0x410FE14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1926 0x410FE18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1927 0x410FE1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1928 0x410FE20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1929 0x410FE24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1930 0x410FE28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1931 0x410FE2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1932 0x410FE30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1933 0x410FE34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1934 0x410FE38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1935 0x410FE3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1936 0x410FE40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1937 0x410FE44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1938 0x410FE48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1939 0x410FE4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1940 0x410FE50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1941 0x410FE54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1942 0x410FE58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1943 0x410FE5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1944 0x410FE60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1945 0x410FE64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1946 0x410FE68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1947 0x410FE6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1948 0x410FE70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1949 0x410FE74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1950 0x410FE78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1951 0x410FE7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1952 0x410FE80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1953 0x410FE84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1954 0x410FE88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1955 0x410FE8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1956 0x410FE90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1957 0x410FE94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1958 0x410FE98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1959 0x410FE9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1960 0x410FEA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1961 0x410FEA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1962 0x410FEA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1963 0x410FEAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1964 0x410FEB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1965 0x410FEB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1966 0x410FEB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1967 0x410FEBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1968 0x410FEC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1969 0x410FEC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1970 0x410FEC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1971 0x410FECC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1972 0x410FED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1973 0x410FED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1974 0x410FED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1975 0x410FEDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1976 0x410FEE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1977 0x410FEE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1978 0x410FEE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1979 0x410FEEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1980 0x410FEF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1981 0x410FEF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1982 0x410FEF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1983 0x410FEFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1984 0x410FF00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1985 0x410FF04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1986 0x410FF08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1987 0x410FF0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1988 0x410FF10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1989 0x410FF14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1990 0x410FF18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1991 0x410FF1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1992 0x410FF20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1993 0x410FF24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1994 0x410FF28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1995 0x410FF2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1996 0x410FF30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1997 0x410FF34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1998 0x410FF38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1999 0x410FF3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2000 0x410FF40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2001 0x410FF44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2002 0x410FF48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2003 0x410FF4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2004 0x410FF50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2005 0x410FF54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2006 0x410FF58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2007 0x410FF5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2008 0x410FF60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2009 0x410FF64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2010 0x410FF68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2011 0x410FF6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2012 0x410FF70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2013 0x410FF74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2014 0x410FF78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2015 0x410FF7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2016 0x410FF80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2017 0x410FF84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2018 0x410FF88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2019 0x410FF8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2020 0x410FF90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2021 0x410FF94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2022 0x410FF98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2023 0x410FF9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2024 0x410FFA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2025 0x410FFA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2026 0x410FFA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2027 0x410FFAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2028 0x410FFB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2029 0x410FFB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2030 0x410FFB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2031 0x410FFBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2032 0x410FFC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2033 0x410FFC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2034 0x410FFC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2035 0x410FFCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2036 0x410FFD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2037 0x410FFD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2038 0x410FFD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2039 0x410FFDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2040 0x410FFE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2041 0x410FFE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2042 0x410FFE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2043 0x410FFEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2044 0x410FFF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2045 0x410FFF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2046 0x410FFF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2047 0x410FFFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_0 0x4110000 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1 0x4110004 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2 0x4110008 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_3 0x411000C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_4 0x4110010 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_5 0x4110014 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_6 0x4110018 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_7 0x411001C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_8 0x4110020 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_9 0x4110024 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_10 0x4110028 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_11 0x411002C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_12 0x4110030 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_13 0x4110034 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_14 0x4110038 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_15 0x411003C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_16 0x4110040 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_17 0x4110044 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_18 0x4110048 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_19 0x411004C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_20 0x4110050 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_21 0x4110054 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_22 0x4110058 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_23 0x411005C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_24 0x4110060 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_25 0x4110064 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_26 0x4110068 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_27 0x411006C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_28 0x4110070 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_29 0x4110074 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_30 0x4110078 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_31 0x411007C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_32 0x4110080 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_33 0x4110084 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_34 0x4110088 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_35 0x411008C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_36 0x4110090 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_37 0x4110094 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_38 0x4110098 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_39 0x411009C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_40 0x41100A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_41 0x41100A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_42 0x41100A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_43 0x41100AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_44 0x41100B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_45 0x41100B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_46 0x41100B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_47 0x41100BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_48 0x41100C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_49 0x41100C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_50 0x41100C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_51 0x41100CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_52 0x41100D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_53 0x41100D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_54 0x41100D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_55 0x41100DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_56 0x41100E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_57 0x41100E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_58 0x41100E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_59 0x41100EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_60 0x41100F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_61 0x41100F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_62 0x41100F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_63 0x41100FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_64 0x4110100 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_65 0x4110104 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_66 0x4110108 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_67 0x411010C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_68 0x4110110 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_69 0x4110114 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_70 0x4110118 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_71 0x411011C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_72 0x4110120 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_73 0x4110124 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_74 0x4110128 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_75 0x411012C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_76 0x4110130 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_77 0x4110134 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_78 0x4110138 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_79 0x411013C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_80 0x4110140 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_81 0x4110144 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_82 0x4110148 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_83 0x411014C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_84 0x4110150 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_85 0x4110154 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_86 0x4110158 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_87 0x411015C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_88 0x4110160 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_89 0x4110164 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_90 0x4110168 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_91 0x411016C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_92 0x4110170 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_93 0x4110174 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_94 0x4110178 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_95 0x411017C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_96 0x4110180 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_97 0x4110184 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_98 0x4110188 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_99 0x411018C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_100 0x4110190 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_101 0x4110194 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_102 0x4110198 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_103 0x411019C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_104 0x41101A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_105 0x41101A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_106 0x41101A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_107 0x41101AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_108 0x41101B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_109 0x41101B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_110 0x41101B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_111 0x41101BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_112 0x41101C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_113 0x41101C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_114 0x41101C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_115 0x41101CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_116 0x41101D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_117 0x41101D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_118 0x41101D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_119 0x41101DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_120 0x41101E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_121 0x41101E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_122 0x41101E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_123 0x41101EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_124 0x41101F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_125 0x41101F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_126 0x41101F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_127 0x41101FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_128 0x4110200 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_129 0x4110204 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_130 0x4110208 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_131 0x411020C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_132 0x4110210 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_133 0x4110214 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_134 0x4110218 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_135 0x411021C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_136 0x4110220 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_137 0x4110224 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_138 0x4110228 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_139 0x411022C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_140 0x4110230 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_141 0x4110234 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_142 0x4110238 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_143 0x411023C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_144 0x4110240 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_145 0x4110244 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_146 0x4110248 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_147 0x411024C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_148 0x4110250 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_149 0x4110254 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_150 0x4110258 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_151 0x411025C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_152 0x4110260 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_153 0x4110264 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_154 0x4110268 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_155 0x411026C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_156 0x4110270 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_157 0x4110274 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_158 0x4110278 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_159 0x411027C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_160 0x4110280 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_161 0x4110284 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_162 0x4110288 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_163 0x411028C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_164 0x4110290 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_165 0x4110294 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_166 0x4110298 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_167 0x411029C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_168 0x41102A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_169 0x41102A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_170 0x41102A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_171 0x41102AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_172 0x41102B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_173 0x41102B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_174 0x41102B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_175 0x41102BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_176 0x41102C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_177 0x41102C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_178 0x41102C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_179 0x41102CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_180 0x41102D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_181 0x41102D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_182 0x41102D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_183 0x41102DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_184 0x41102E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_185 0x41102E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_186 0x41102E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_187 0x41102EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_188 0x41102F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_189 0x41102F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_190 0x41102F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_191 0x41102FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_192 0x4110300 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_193 0x4110304 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_194 0x4110308 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_195 0x411030C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_196 0x4110310 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_197 0x4110314 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_198 0x4110318 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_199 0x411031C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_200 0x4110320 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_201 0x4110324 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_202 0x4110328 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_203 0x411032C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_204 0x4110330 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_205 0x4110334 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_206 0x4110338 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_207 0x411033C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_208 0x4110340 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_209 0x4110344 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_210 0x4110348 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_211 0x411034C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_212 0x4110350 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_213 0x4110354 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_214 0x4110358 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_215 0x411035C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_216 0x4110360 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_217 0x4110364 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_218 0x4110368 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_219 0x411036C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_220 0x4110370 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_221 0x4110374 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_222 0x4110378 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_223 0x411037C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_224 0x4110380 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_225 0x4110384 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_226 0x4110388 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_227 0x411038C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_228 0x4110390 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_229 0x4110394 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_230 0x4110398 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_231 0x411039C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_232 0x41103A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_233 0x41103A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_234 0x41103A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_235 0x41103AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_236 0x41103B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_237 0x41103B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_238 0x41103B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_239 0x41103BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_240 0x41103C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_241 0x41103C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_242 0x41103C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_243 0x41103CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_244 0x41103D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_245 0x41103D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_246 0x41103D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_247 0x41103DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_248 0x41103E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_249 0x41103E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_250 0x41103E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_251 0x41103EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_252 0x41103F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_253 0x41103F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_254 0x41103F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_255 0x41103FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_256 0x4110400 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_257 0x4110404 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_258 0x4110408 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_259 0x411040C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_260 0x4110410 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_261 0x4110414 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_262 0x4110418 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_263 0x411041C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_264 0x4110420 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_265 0x4110424 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_266 0x4110428 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_267 0x411042C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_268 0x4110430 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_269 0x4110434 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_270 0x4110438 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_271 0x411043C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_272 0x4110440 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_273 0x4110444 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_274 0x4110448 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_275 0x411044C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_276 0x4110450 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_277 0x4110454 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_278 0x4110458 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_279 0x411045C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_280 0x4110460 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_281 0x4110464 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_282 0x4110468 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_283 0x411046C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_284 0x4110470 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_285 0x4110474 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_286 0x4110478 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_287 0x411047C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_288 0x4110480 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_289 0x4110484 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_290 0x4110488 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_291 0x411048C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_292 0x4110490 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_293 0x4110494 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_294 0x4110498 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_295 0x411049C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_296 0x41104A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_297 0x41104A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_298 0x41104A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_299 0x41104AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_300 0x41104B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_301 0x41104B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_302 0x41104B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_303 0x41104BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_304 0x41104C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_305 0x41104C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_306 0x41104C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_307 0x41104CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_308 0x41104D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_309 0x41104D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_310 0x41104D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_311 0x41104DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_312 0x41104E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_313 0x41104E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_314 0x41104E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_315 0x41104EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_316 0x41104F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_317 0x41104F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_318 0x41104F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_319 0x41104FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_320 0x4110500 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_321 0x4110504 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_322 0x4110508 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_323 0x411050C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_324 0x4110510 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_325 0x4110514 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_326 0x4110518 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_327 0x411051C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_328 0x4110520 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_329 0x4110524 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_330 0x4110528 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_331 0x411052C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_332 0x4110530 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_333 0x4110534 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_334 0x4110538 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_335 0x411053C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_336 0x4110540 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_337 0x4110544 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_338 0x4110548 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_339 0x411054C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_340 0x4110550 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_341 0x4110554 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_342 0x4110558 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_343 0x411055C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_344 0x4110560 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_345 0x4110564 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_346 0x4110568 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_347 0x411056C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_348 0x4110570 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_349 0x4110574 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_350 0x4110578 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_351 0x411057C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_352 0x4110580 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_353 0x4110584 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_354 0x4110588 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_355 0x411058C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_356 0x4110590 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_357 0x4110594 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_358 0x4110598 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_359 0x411059C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_360 0x41105A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_361 0x41105A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_362 0x41105A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_363 0x41105AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_364 0x41105B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_365 0x41105B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_366 0x41105B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_367 0x41105BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_368 0x41105C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_369 0x41105C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_370 0x41105C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_371 0x41105CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_372 0x41105D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_373 0x41105D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_374 0x41105D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_375 0x41105DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_376 0x41105E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_377 0x41105E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_378 0x41105E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_379 0x41105EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_380 0x41105F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_381 0x41105F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_382 0x41105F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_383 0x41105FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_384 0x4110600 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_385 0x4110604 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_386 0x4110608 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_387 0x411060C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_388 0x4110610 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_389 0x4110614 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_390 0x4110618 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_391 0x411061C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_392 0x4110620 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_393 0x4110624 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_394 0x4110628 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_395 0x411062C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_396 0x4110630 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_397 0x4110634 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_398 0x4110638 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_399 0x411063C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_400 0x4110640 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_401 0x4110644 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_402 0x4110648 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_403 0x411064C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_404 0x4110650 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_405 0x4110654 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_406 0x4110658 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_407 0x411065C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_408 0x4110660 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_409 0x4110664 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_410 0x4110668 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_411 0x411066C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_412 0x4110670 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_413 0x4110674 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_414 0x4110678 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_415 0x411067C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_416 0x4110680 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_417 0x4110684 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_418 0x4110688 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_419 0x411068C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_420 0x4110690 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_421 0x4110694 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_422 0x4110698 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_423 0x411069C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_424 0x41106A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_425 0x41106A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_426 0x41106A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_427 0x41106AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_428 0x41106B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_429 0x41106B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_430 0x41106B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_431 0x41106BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_432 0x41106C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_433 0x41106C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_434 0x41106C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_435 0x41106CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_436 0x41106D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_437 0x41106D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_438 0x41106D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_439 0x41106DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_440 0x41106E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_441 0x41106E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_442 0x41106E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_443 0x41106EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_444 0x41106F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_445 0x41106F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_446 0x41106F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_447 0x41106FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_448 0x4110700 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_449 0x4110704 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_450 0x4110708 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_451 0x411070C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_452 0x4110710 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_453 0x4110714 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_454 0x4110718 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_455 0x411071C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_456 0x4110720 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_457 0x4110724 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_458 0x4110728 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_459 0x411072C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_460 0x4110730 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_461 0x4110734 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_462 0x4110738 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_463 0x411073C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_464 0x4110740 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_465 0x4110744 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_466 0x4110748 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_467 0x411074C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_468 0x4110750 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_469 0x4110754 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_470 0x4110758 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_471 0x411075C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_472 0x4110760 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_473 0x4110764 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_474 0x4110768 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_475 0x411076C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_476 0x4110770 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_477 0x4110774 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_478 0x4110778 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_479 0x411077C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_480 0x4110780 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_481 0x4110784 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_482 0x4110788 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_483 0x411078C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_484 0x4110790 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_485 0x4110794 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_486 0x4110798 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_487 0x411079C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_488 0x41107A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_489 0x41107A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_490 0x41107A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_491 0x41107AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_492 0x41107B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_493 0x41107B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_494 0x41107B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_495 0x41107BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_496 0x41107C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_497 0x41107C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_498 0x41107C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_499 0x41107CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_500 0x41107D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_501 0x41107D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_502 0x41107D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_503 0x41107DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_504 0x41107E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_505 0x41107E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_506 0x41107E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_507 0x41107EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_508 0x41107F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_509 0x41107F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_510 0x41107F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_511 0x41107FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_512 0x4110800 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_513 0x4110804 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_514 0x4110808 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_515 0x411080C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_516 0x4110810 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_517 0x4110814 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_518 0x4110818 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_519 0x411081C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_520 0x4110820 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_521 0x4110824 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_522 0x4110828 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_523 0x411082C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_524 0x4110830 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_525 0x4110834 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_526 0x4110838 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_527 0x411083C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_528 0x4110840 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_529 0x4110844 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_530 0x4110848 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_531 0x411084C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_532 0x4110850 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_533 0x4110854 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_534 0x4110858 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_535 0x411085C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_536 0x4110860 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_537 0x4110864 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_538 0x4110868 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_539 0x411086C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_540 0x4110870 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_541 0x4110874 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_542 0x4110878 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_543 0x411087C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_544 0x4110880 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_545 0x4110884 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_546 0x4110888 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_547 0x411088C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_548 0x4110890 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_549 0x4110894 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_550 0x4110898 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_551 0x411089C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_552 0x41108A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_553 0x41108A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_554 0x41108A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_555 0x41108AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_556 0x41108B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_557 0x41108B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_558 0x41108B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_559 0x41108BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_560 0x41108C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_561 0x41108C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_562 0x41108C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_563 0x41108CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_564 0x41108D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_565 0x41108D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_566 0x41108D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_567 0x41108DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_568 0x41108E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_569 0x41108E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_570 0x41108E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_571 0x41108EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_572 0x41108F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_573 0x41108F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_574 0x41108F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_575 0x41108FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_576 0x4110900 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_577 0x4110904 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_578 0x4110908 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_579 0x411090C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_580 0x4110910 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_581 0x4110914 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_582 0x4110918 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_583 0x411091C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_584 0x4110920 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_585 0x4110924 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_586 0x4110928 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_587 0x411092C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_588 0x4110930 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_589 0x4110934 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_590 0x4110938 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_591 0x411093C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_592 0x4110940 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_593 0x4110944 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_594 0x4110948 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_595 0x411094C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_596 0x4110950 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_597 0x4110954 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_598 0x4110958 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_599 0x411095C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_600 0x4110960 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_601 0x4110964 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_602 0x4110968 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_603 0x411096C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_604 0x4110970 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_605 0x4110974 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_606 0x4110978 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_607 0x411097C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_608 0x4110980 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_609 0x4110984 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_610 0x4110988 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_611 0x411098C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_612 0x4110990 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_613 0x4110994 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_614 0x4110998 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_615 0x411099C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_616 0x41109A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_617 0x41109A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_618 0x41109A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_619 0x41109AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_620 0x41109B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_621 0x41109B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_622 0x41109B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_623 0x41109BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_624 0x41109C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_625 0x41109C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_626 0x41109C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_627 0x41109CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_628 0x41109D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_629 0x41109D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_630 0x41109D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_631 0x41109DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_632 0x41109E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_633 0x41109E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_634 0x41109E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_635 0x41109EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_636 0x41109F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_637 0x41109F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_638 0x41109F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_639 0x41109FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_640 0x4110A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_641 0x4110A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_642 0x4110A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_643 0x4110A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_644 0x4110A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_645 0x4110A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_646 0x4110A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_647 0x4110A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_648 0x4110A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_649 0x4110A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_650 0x4110A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_651 0x4110A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_652 0x4110A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_653 0x4110A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_654 0x4110A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_655 0x4110A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_656 0x4110A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_657 0x4110A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_658 0x4110A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_659 0x4110A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_660 0x4110A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_661 0x4110A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_662 0x4110A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_663 0x4110A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_664 0x4110A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_665 0x4110A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_666 0x4110A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_667 0x4110A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_668 0x4110A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_669 0x4110A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_670 0x4110A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_671 0x4110A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_672 0x4110A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_673 0x4110A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_674 0x4110A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_675 0x4110A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_676 0x4110A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_677 0x4110A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_678 0x4110A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_679 0x4110A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_680 0x4110AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_681 0x4110AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_682 0x4110AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_683 0x4110AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_684 0x4110AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_685 0x4110AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_686 0x4110AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_687 0x4110ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_688 0x4110AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_689 0x4110AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_690 0x4110AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_691 0x4110ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_692 0x4110AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_693 0x4110AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_694 0x4110AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_695 0x4110ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_696 0x4110AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_697 0x4110AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_698 0x4110AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_699 0x4110AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_700 0x4110AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_701 0x4110AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_702 0x4110AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_703 0x4110AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_704 0x4110B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_705 0x4110B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_706 0x4110B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_707 0x4110B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_708 0x4110B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_709 0x4110B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_710 0x4110B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_711 0x4110B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_712 0x4110B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_713 0x4110B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_714 0x4110B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_715 0x4110B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_716 0x4110B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_717 0x4110B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_718 0x4110B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_719 0x4110B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_720 0x4110B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_721 0x4110B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_722 0x4110B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_723 0x4110B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_724 0x4110B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_725 0x4110B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_726 0x4110B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_727 0x4110B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_728 0x4110B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_729 0x4110B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_730 0x4110B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_731 0x4110B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_732 0x4110B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_733 0x4110B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_734 0x4110B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_735 0x4110B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_736 0x4110B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_737 0x4110B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_738 0x4110B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_739 0x4110B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_740 0x4110B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_741 0x4110B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_742 0x4110B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_743 0x4110B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_744 0x4110BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_745 0x4110BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_746 0x4110BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_747 0x4110BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_748 0x4110BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_749 0x4110BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_750 0x4110BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_751 0x4110BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_752 0x4110BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_753 0x4110BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_754 0x4110BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_755 0x4110BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_756 0x4110BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_757 0x4110BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_758 0x4110BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_759 0x4110BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_760 0x4110BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_761 0x4110BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_762 0x4110BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_763 0x4110BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_764 0x4110BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_765 0x4110BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_766 0x4110BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_767 0x4110BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_768 0x4110C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_769 0x4110C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_770 0x4110C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_771 0x4110C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_772 0x4110C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_773 0x4110C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_774 0x4110C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_775 0x4110C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_776 0x4110C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_777 0x4110C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_778 0x4110C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_779 0x4110C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_780 0x4110C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_781 0x4110C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_782 0x4110C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_783 0x4110C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_784 0x4110C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_785 0x4110C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_786 0x4110C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_787 0x4110C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_788 0x4110C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_789 0x4110C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_790 0x4110C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_791 0x4110C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_792 0x4110C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_793 0x4110C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_794 0x4110C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_795 0x4110C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_796 0x4110C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_797 0x4110C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_798 0x4110C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_799 0x4110C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_800 0x4110C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_801 0x4110C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_802 0x4110C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_803 0x4110C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_804 0x4110C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_805 0x4110C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_806 0x4110C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_807 0x4110C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_808 0x4110CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_809 0x4110CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_810 0x4110CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_811 0x4110CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_812 0x4110CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_813 0x4110CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_814 0x4110CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_815 0x4110CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_816 0x4110CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_817 0x4110CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_818 0x4110CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_819 0x4110CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_820 0x4110CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_821 0x4110CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_822 0x4110CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_823 0x4110CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_824 0x4110CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_825 0x4110CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_826 0x4110CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_827 0x4110CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_828 0x4110CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_829 0x4110CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_830 0x4110CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_831 0x4110CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_832 0x4110D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_833 0x4110D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_834 0x4110D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_835 0x4110D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_836 0x4110D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_837 0x4110D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_838 0x4110D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_839 0x4110D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_840 0x4110D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_841 0x4110D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_842 0x4110D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_843 0x4110D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_844 0x4110D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_845 0x4110D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_846 0x4110D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_847 0x4110D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_848 0x4110D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_849 0x4110D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_850 0x4110D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_851 0x4110D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_852 0x4110D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_853 0x4110D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_854 0x4110D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_855 0x4110D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_856 0x4110D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_857 0x4110D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_858 0x4110D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_859 0x4110D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_860 0x4110D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_861 0x4110D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_862 0x4110D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_863 0x4110D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_864 0x4110D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_865 0x4110D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_866 0x4110D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_867 0x4110D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_868 0x4110D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_869 0x4110D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_870 0x4110D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_871 0x4110D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_872 0x4110DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_873 0x4110DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_874 0x4110DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_875 0x4110DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_876 0x4110DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_877 0x4110DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_878 0x4110DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_879 0x4110DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_880 0x4110DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_881 0x4110DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_882 0x4110DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_883 0x4110DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_884 0x4110DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_885 0x4110DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_886 0x4110DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_887 0x4110DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_888 0x4110DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_889 0x4110DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_890 0x4110DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_891 0x4110DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_892 0x4110DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_893 0x4110DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_894 0x4110DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_895 0x4110DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_896 0x4110E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_897 0x4110E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_898 0x4110E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_899 0x4110E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_900 0x4110E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_901 0x4110E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_902 0x4110E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_903 0x4110E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_904 0x4110E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_905 0x4110E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_906 0x4110E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_907 0x4110E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_908 0x4110E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_909 0x4110E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_910 0x4110E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_911 0x4110E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_912 0x4110E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_913 0x4110E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_914 0x4110E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_915 0x4110E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_916 0x4110E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_917 0x4110E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_918 0x4110E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_919 0x4110E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_920 0x4110E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_921 0x4110E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_922 0x4110E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_923 0x4110E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_924 0x4110E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_925 0x4110E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_926 0x4110E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_927 0x4110E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_928 0x4110E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_929 0x4110E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_930 0x4110E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_931 0x4110E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_932 0x4110E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_933 0x4110E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_934 0x4110E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_935 0x4110E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_936 0x4110EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_937 0x4110EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_938 0x4110EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_939 0x4110EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_940 0x4110EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_941 0x4110EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_942 0x4110EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_943 0x4110EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_944 0x4110EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_945 0x4110EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_946 0x4110EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_947 0x4110ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_948 0x4110ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_949 0x4110ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_950 0x4110ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_951 0x4110EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_952 0x4110EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_953 0x4110EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_954 0x4110EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_955 0x4110EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_956 0x4110EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_957 0x4110EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_958 0x4110EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_959 0x4110EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_960 0x4110F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_961 0x4110F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_962 0x4110F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_963 0x4110F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_964 0x4110F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_965 0x4110F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_966 0x4110F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_967 0x4110F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_968 0x4110F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_969 0x4110F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_970 0x4110F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_971 0x4110F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_972 0x4110F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_973 0x4110F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_974 0x4110F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_975 0x4110F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_976 0x4110F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_977 0x4110F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_978 0x4110F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_979 0x4110F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_980 0x4110F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_981 0x4110F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_982 0x4110F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_983 0x4110F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_984 0x4110F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_985 0x4110F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_986 0x4110F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_987 0x4110F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_988 0x4110F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_989 0x4110F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_990 0x4110F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_991 0x4110F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_992 0x4110F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_993 0x4110F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_994 0x4110F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_995 0x4110F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_996 0x4110F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_997 0x4110F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_998 0x4110F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_999 0x4110F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1000 0x4110FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1001 0x4110FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1002 0x4110FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1003 0x4110FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1004 0x4110FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1005 0x4110FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1006 0x4110FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1007 0x4110FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1008 0x4110FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1009 0x4110FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1010 0x4110FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1011 0x4110FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1012 0x4110FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1013 0x4110FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1014 0x4110FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1015 0x4110FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1016 0x4110FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1017 0x4110FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1018 0x4110FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1019 0x4110FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1020 0x4110FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1021 0x4110FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1022 0x4110FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1023 0x4110FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1024 0x4111000 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1025 0x4111004 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1026 0x4111008 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1027 0x411100C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1028 0x4111010 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1029 0x4111014 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1030 0x4111018 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1031 0x411101C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1032 0x4111020 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1033 0x4111024 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1034 0x4111028 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1035 0x411102C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1036 0x4111030 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1037 0x4111034 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1038 0x4111038 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1039 0x411103C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1040 0x4111040 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1041 0x4111044 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1042 0x4111048 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1043 0x411104C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1044 0x4111050 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1045 0x4111054 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1046 0x4111058 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1047 0x411105C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1048 0x4111060 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1049 0x4111064 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1050 0x4111068 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1051 0x411106C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1052 0x4111070 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1053 0x4111074 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1054 0x4111078 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1055 0x411107C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1056 0x4111080 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1057 0x4111084 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1058 0x4111088 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1059 0x411108C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1060 0x4111090 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1061 0x4111094 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1062 0x4111098 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1063 0x411109C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1064 0x41110A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1065 0x41110A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1066 0x41110A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1067 0x41110AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1068 0x41110B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1069 0x41110B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1070 0x41110B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1071 0x41110BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1072 0x41110C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1073 0x41110C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1074 0x41110C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1075 0x41110CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1076 0x41110D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1077 0x41110D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1078 0x41110D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1079 0x41110DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1080 0x41110E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1081 0x41110E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1082 0x41110E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1083 0x41110EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1084 0x41110F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1085 0x41110F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1086 0x41110F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1087 0x41110FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1088 0x4111100 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1089 0x4111104 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1090 0x4111108 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1091 0x411110C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1092 0x4111110 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1093 0x4111114 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1094 0x4111118 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1095 0x411111C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1096 0x4111120 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1097 0x4111124 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1098 0x4111128 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1099 0x411112C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1100 0x4111130 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1101 0x4111134 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1102 0x4111138 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1103 0x411113C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1104 0x4111140 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1105 0x4111144 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1106 0x4111148 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1107 0x411114C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1108 0x4111150 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1109 0x4111154 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1110 0x4111158 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1111 0x411115C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1112 0x4111160 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1113 0x4111164 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1114 0x4111168 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1115 0x411116C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1116 0x4111170 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1117 0x4111174 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1118 0x4111178 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1119 0x411117C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1120 0x4111180 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1121 0x4111184 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1122 0x4111188 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1123 0x411118C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1124 0x4111190 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1125 0x4111194 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1126 0x4111198 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1127 0x411119C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1128 0x41111A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1129 0x41111A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1130 0x41111A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1131 0x41111AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1132 0x41111B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1133 0x41111B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1134 0x41111B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1135 0x41111BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1136 0x41111C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1137 0x41111C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1138 0x41111C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1139 0x41111CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1140 0x41111D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1141 0x41111D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1142 0x41111D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1143 0x41111DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1144 0x41111E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1145 0x41111E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1146 0x41111E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1147 0x41111EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1148 0x41111F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1149 0x41111F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1150 0x41111F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1151 0x41111FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1152 0x4111200 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1153 0x4111204 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1154 0x4111208 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1155 0x411120C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1156 0x4111210 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1157 0x4111214 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1158 0x4111218 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1159 0x411121C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1160 0x4111220 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1161 0x4111224 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1162 0x4111228 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1163 0x411122C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1164 0x4111230 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1165 0x4111234 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1166 0x4111238 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1167 0x411123C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1168 0x4111240 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1169 0x4111244 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1170 0x4111248 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1171 0x411124C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1172 0x4111250 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1173 0x4111254 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1174 0x4111258 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1175 0x411125C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1176 0x4111260 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1177 0x4111264 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1178 0x4111268 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1179 0x411126C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1180 0x4111270 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1181 0x4111274 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1182 0x4111278 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1183 0x411127C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1184 0x4111280 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1185 0x4111284 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1186 0x4111288 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1187 0x411128C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1188 0x4111290 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1189 0x4111294 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1190 0x4111298 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1191 0x411129C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1192 0x41112A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1193 0x41112A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1194 0x41112A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1195 0x41112AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1196 0x41112B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1197 0x41112B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1198 0x41112B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1199 0x41112BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1200 0x41112C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1201 0x41112C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1202 0x41112C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1203 0x41112CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1204 0x41112D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1205 0x41112D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1206 0x41112D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1207 0x41112DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1208 0x41112E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1209 0x41112E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1210 0x41112E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1211 0x41112EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1212 0x41112F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1213 0x41112F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1214 0x41112F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1215 0x41112FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1216 0x4111300 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1217 0x4111304 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1218 0x4111308 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1219 0x411130C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1220 0x4111310 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1221 0x4111314 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1222 0x4111318 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1223 0x411131C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1224 0x4111320 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1225 0x4111324 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1226 0x4111328 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1227 0x411132C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1228 0x4111330 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1229 0x4111334 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1230 0x4111338 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1231 0x411133C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1232 0x4111340 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1233 0x4111344 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1234 0x4111348 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1235 0x411134C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1236 0x4111350 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1237 0x4111354 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1238 0x4111358 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1239 0x411135C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1240 0x4111360 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1241 0x4111364 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1242 0x4111368 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1243 0x411136C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1244 0x4111370 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1245 0x4111374 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1246 0x4111378 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1247 0x411137C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1248 0x4111380 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1249 0x4111384 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1250 0x4111388 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1251 0x411138C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1252 0x4111390 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1253 0x4111394 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1254 0x4111398 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1255 0x411139C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1256 0x41113A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1257 0x41113A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1258 0x41113A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1259 0x41113AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1260 0x41113B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1261 0x41113B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1262 0x41113B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1263 0x41113BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1264 0x41113C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1265 0x41113C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1266 0x41113C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1267 0x41113CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1268 0x41113D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1269 0x41113D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1270 0x41113D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1271 0x41113DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1272 0x41113E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1273 0x41113E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1274 0x41113E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1275 0x41113EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1276 0x41113F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1277 0x41113F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1278 0x41113F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1279 0x41113FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1280 0x4111400 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1281 0x4111404 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1282 0x4111408 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1283 0x411140C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1284 0x4111410 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1285 0x4111414 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1286 0x4111418 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1287 0x411141C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1288 0x4111420 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1289 0x4111424 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1290 0x4111428 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1291 0x411142C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1292 0x4111430 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1293 0x4111434 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1294 0x4111438 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1295 0x411143C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1296 0x4111440 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1297 0x4111444 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1298 0x4111448 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1299 0x411144C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1300 0x4111450 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1301 0x4111454 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1302 0x4111458 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1303 0x411145C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1304 0x4111460 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1305 0x4111464 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1306 0x4111468 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1307 0x411146C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1308 0x4111470 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1309 0x4111474 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1310 0x4111478 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1311 0x411147C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1312 0x4111480 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1313 0x4111484 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1314 0x4111488 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1315 0x411148C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1316 0x4111490 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1317 0x4111494 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1318 0x4111498 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1319 0x411149C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1320 0x41114A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1321 0x41114A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1322 0x41114A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1323 0x41114AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1324 0x41114B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1325 0x41114B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1326 0x41114B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1327 0x41114BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1328 0x41114C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1329 0x41114C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1330 0x41114C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1331 0x41114CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1332 0x41114D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1333 0x41114D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1334 0x41114D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1335 0x41114DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1336 0x41114E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1337 0x41114E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1338 0x41114E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1339 0x41114EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1340 0x41114F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1341 0x41114F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1342 0x41114F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1343 0x41114FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1344 0x4111500 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1345 0x4111504 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1346 0x4111508 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1347 0x411150C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1348 0x4111510 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1349 0x4111514 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1350 0x4111518 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1351 0x411151C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1352 0x4111520 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1353 0x4111524 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1354 0x4111528 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1355 0x411152C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1356 0x4111530 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1357 0x4111534 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1358 0x4111538 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1359 0x411153C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1360 0x4111540 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1361 0x4111544 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1362 0x4111548 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1363 0x411154C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1364 0x4111550 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1365 0x4111554 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1366 0x4111558 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1367 0x411155C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1368 0x4111560 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1369 0x4111564 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1370 0x4111568 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1371 0x411156C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1372 0x4111570 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1373 0x4111574 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1374 0x4111578 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1375 0x411157C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1376 0x4111580 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1377 0x4111584 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1378 0x4111588 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1379 0x411158C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1380 0x4111590 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1381 0x4111594 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1382 0x4111598 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1383 0x411159C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1384 0x41115A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1385 0x41115A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1386 0x41115A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1387 0x41115AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1388 0x41115B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1389 0x41115B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1390 0x41115B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1391 0x41115BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1392 0x41115C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1393 0x41115C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1394 0x41115C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1395 0x41115CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1396 0x41115D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1397 0x41115D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1398 0x41115D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1399 0x41115DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1400 0x41115E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1401 0x41115E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1402 0x41115E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1403 0x41115EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1404 0x41115F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1405 0x41115F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1406 0x41115F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1407 0x41115FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1408 0x4111600 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1409 0x4111604 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1410 0x4111608 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1411 0x411160C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1412 0x4111610 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1413 0x4111614 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1414 0x4111618 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1415 0x411161C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1416 0x4111620 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1417 0x4111624 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1418 0x4111628 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1419 0x411162C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1420 0x4111630 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1421 0x4111634 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1422 0x4111638 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1423 0x411163C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1424 0x4111640 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1425 0x4111644 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1426 0x4111648 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1427 0x411164C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1428 0x4111650 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1429 0x4111654 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1430 0x4111658 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1431 0x411165C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1432 0x4111660 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1433 0x4111664 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1434 0x4111668 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1435 0x411166C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1436 0x4111670 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1437 0x4111674 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1438 0x4111678 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1439 0x411167C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1440 0x4111680 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1441 0x4111684 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1442 0x4111688 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1443 0x411168C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1444 0x4111690 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1445 0x4111694 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1446 0x4111698 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1447 0x411169C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1448 0x41116A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1449 0x41116A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1450 0x41116A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1451 0x41116AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1452 0x41116B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1453 0x41116B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1454 0x41116B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1455 0x41116BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1456 0x41116C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1457 0x41116C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1458 0x41116C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1459 0x41116CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1460 0x41116D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1461 0x41116D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1462 0x41116D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1463 0x41116DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1464 0x41116E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1465 0x41116E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1466 0x41116E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1467 0x41116EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1468 0x41116F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1469 0x41116F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1470 0x41116F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1471 0x41116FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1472 0x4111700 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1473 0x4111704 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1474 0x4111708 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1475 0x411170C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1476 0x4111710 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1477 0x4111714 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1478 0x4111718 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1479 0x411171C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1480 0x4111720 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1481 0x4111724 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1482 0x4111728 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1483 0x411172C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1484 0x4111730 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1485 0x4111734 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1486 0x4111738 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1487 0x411173C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1488 0x4111740 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1489 0x4111744 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1490 0x4111748 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1491 0x411174C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1492 0x4111750 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1493 0x4111754 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1494 0x4111758 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1495 0x411175C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1496 0x4111760 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1497 0x4111764 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1498 0x4111768 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1499 0x411176C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1500 0x4111770 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1501 0x4111774 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1502 0x4111778 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1503 0x411177C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1504 0x4111780 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1505 0x4111784 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1506 0x4111788 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1507 0x411178C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1508 0x4111790 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1509 0x4111794 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1510 0x4111798 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1511 0x411179C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1512 0x41117A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1513 0x41117A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1514 0x41117A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1515 0x41117AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1516 0x41117B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1517 0x41117B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1518 0x41117B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1519 0x41117BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1520 0x41117C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1521 0x41117C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1522 0x41117C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1523 0x41117CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1524 0x41117D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1525 0x41117D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1526 0x41117D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1527 0x41117DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1528 0x41117E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1529 0x41117E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1530 0x41117E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1531 0x41117EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1532 0x41117F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1533 0x41117F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1534 0x41117F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1535 0x41117FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1536 0x4111800 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1537 0x4111804 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1538 0x4111808 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1539 0x411180C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1540 0x4111810 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1541 0x4111814 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1542 0x4111818 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1543 0x411181C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1544 0x4111820 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1545 0x4111824 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1546 0x4111828 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1547 0x411182C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1548 0x4111830 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1549 0x4111834 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1550 0x4111838 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1551 0x411183C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1552 0x4111840 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1553 0x4111844 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1554 0x4111848 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1555 0x411184C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1556 0x4111850 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1557 0x4111854 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1558 0x4111858 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1559 0x411185C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1560 0x4111860 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1561 0x4111864 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1562 0x4111868 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1563 0x411186C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1564 0x4111870 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1565 0x4111874 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1566 0x4111878 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1567 0x411187C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1568 0x4111880 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1569 0x4111884 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1570 0x4111888 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1571 0x411188C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1572 0x4111890 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1573 0x4111894 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1574 0x4111898 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1575 0x411189C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1576 0x41118A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1577 0x41118A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1578 0x41118A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1579 0x41118AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1580 0x41118B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1581 0x41118B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1582 0x41118B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1583 0x41118BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1584 0x41118C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1585 0x41118C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1586 0x41118C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1587 0x41118CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1588 0x41118D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1589 0x41118D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1590 0x41118D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1591 0x41118DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1592 0x41118E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1593 0x41118E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1594 0x41118E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1595 0x41118EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1596 0x41118F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1597 0x41118F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1598 0x41118F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1599 0x41118FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1600 0x4111900 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1601 0x4111904 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1602 0x4111908 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1603 0x411190C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1604 0x4111910 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1605 0x4111914 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1606 0x4111918 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1607 0x411191C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1608 0x4111920 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1609 0x4111924 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1610 0x4111928 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1611 0x411192C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1612 0x4111930 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1613 0x4111934 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1614 0x4111938 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1615 0x411193C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1616 0x4111940 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1617 0x4111944 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1618 0x4111948 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1619 0x411194C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1620 0x4111950 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1621 0x4111954 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1622 0x4111958 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1623 0x411195C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1624 0x4111960 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1625 0x4111964 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1626 0x4111968 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1627 0x411196C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1628 0x4111970 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1629 0x4111974 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1630 0x4111978 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1631 0x411197C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1632 0x4111980 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1633 0x4111984 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1634 0x4111988 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1635 0x411198C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1636 0x4111990 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1637 0x4111994 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1638 0x4111998 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1639 0x411199C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1640 0x41119A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1641 0x41119A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1642 0x41119A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1643 0x41119AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1644 0x41119B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1645 0x41119B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1646 0x41119B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1647 0x41119BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1648 0x41119C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1649 0x41119C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1650 0x41119C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1651 0x41119CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1652 0x41119D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1653 0x41119D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1654 0x41119D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1655 0x41119DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1656 0x41119E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1657 0x41119E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1658 0x41119E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1659 0x41119EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1660 0x41119F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1661 0x41119F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1662 0x41119F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1663 0x41119FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1664 0x4111A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1665 0x4111A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1666 0x4111A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1667 0x4111A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1668 0x4111A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1669 0x4111A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1670 0x4111A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1671 0x4111A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1672 0x4111A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1673 0x4111A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1674 0x4111A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1675 0x4111A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1676 0x4111A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1677 0x4111A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1678 0x4111A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1679 0x4111A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1680 0x4111A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1681 0x4111A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1682 0x4111A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1683 0x4111A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1684 0x4111A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1685 0x4111A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1686 0x4111A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1687 0x4111A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1688 0x4111A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1689 0x4111A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1690 0x4111A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1691 0x4111A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1692 0x4111A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1693 0x4111A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1694 0x4111A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1695 0x4111A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1696 0x4111A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1697 0x4111A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1698 0x4111A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1699 0x4111A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1700 0x4111A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1701 0x4111A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1702 0x4111A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1703 0x4111A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1704 0x4111AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1705 0x4111AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1706 0x4111AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1707 0x4111AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1708 0x4111AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1709 0x4111AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1710 0x4111AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1711 0x4111ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1712 0x4111AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1713 0x4111AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1714 0x4111AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1715 0x4111ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1716 0x4111AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1717 0x4111AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1718 0x4111AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1719 0x4111ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1720 0x4111AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1721 0x4111AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1722 0x4111AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1723 0x4111AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1724 0x4111AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1725 0x4111AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1726 0x4111AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1727 0x4111AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1728 0x4111B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1729 0x4111B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1730 0x4111B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1731 0x4111B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1732 0x4111B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1733 0x4111B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1734 0x4111B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1735 0x4111B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1736 0x4111B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1737 0x4111B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1738 0x4111B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1739 0x4111B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1740 0x4111B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1741 0x4111B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1742 0x4111B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1743 0x4111B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1744 0x4111B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1745 0x4111B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1746 0x4111B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1747 0x4111B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1748 0x4111B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1749 0x4111B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1750 0x4111B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1751 0x4111B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1752 0x4111B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1753 0x4111B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1754 0x4111B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1755 0x4111B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1756 0x4111B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1757 0x4111B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1758 0x4111B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1759 0x4111B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1760 0x4111B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1761 0x4111B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1762 0x4111B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1763 0x4111B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1764 0x4111B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1765 0x4111B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1766 0x4111B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1767 0x4111B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1768 0x4111BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1769 0x4111BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1770 0x4111BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1771 0x4111BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1772 0x4111BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1773 0x4111BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1774 0x4111BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1775 0x4111BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1776 0x4111BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1777 0x4111BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1778 0x4111BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1779 0x4111BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1780 0x4111BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1781 0x4111BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1782 0x4111BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1783 0x4111BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1784 0x4111BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1785 0x4111BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1786 0x4111BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1787 0x4111BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1788 0x4111BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1789 0x4111BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1790 0x4111BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1791 0x4111BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1792 0x4111C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1793 0x4111C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1794 0x4111C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1795 0x4111C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1796 0x4111C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1797 0x4111C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1798 0x4111C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1799 0x4111C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1800 0x4111C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1801 0x4111C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1802 0x4111C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1803 0x4111C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1804 0x4111C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1805 0x4111C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1806 0x4111C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1807 0x4111C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1808 0x4111C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1809 0x4111C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1810 0x4111C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1811 0x4111C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1812 0x4111C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1813 0x4111C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1814 0x4111C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1815 0x4111C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1816 0x4111C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1817 0x4111C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1818 0x4111C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1819 0x4111C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1820 0x4111C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1821 0x4111C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1822 0x4111C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1823 0x4111C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1824 0x4111C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1825 0x4111C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1826 0x4111C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1827 0x4111C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1828 0x4111C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1829 0x4111C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1830 0x4111C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1831 0x4111C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1832 0x4111CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1833 0x4111CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1834 0x4111CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1835 0x4111CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1836 0x4111CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1837 0x4111CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1838 0x4111CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1839 0x4111CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1840 0x4111CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1841 0x4111CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1842 0x4111CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1843 0x4111CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1844 0x4111CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1845 0x4111CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1846 0x4111CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1847 0x4111CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1848 0x4111CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1849 0x4111CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1850 0x4111CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1851 0x4111CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1852 0x4111CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1853 0x4111CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1854 0x4111CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1855 0x4111CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1856 0x4111D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1857 0x4111D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1858 0x4111D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1859 0x4111D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1860 0x4111D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1861 0x4111D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1862 0x4111D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1863 0x4111D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1864 0x4111D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1865 0x4111D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1866 0x4111D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1867 0x4111D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1868 0x4111D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1869 0x4111D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1870 0x4111D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1871 0x4111D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1872 0x4111D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1873 0x4111D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1874 0x4111D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1875 0x4111D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1876 0x4111D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1877 0x4111D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1878 0x4111D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1879 0x4111D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1880 0x4111D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1881 0x4111D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1882 0x4111D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1883 0x4111D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1884 0x4111D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1885 0x4111D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1886 0x4111D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1887 0x4111D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1888 0x4111D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1889 0x4111D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1890 0x4111D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1891 0x4111D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1892 0x4111D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1893 0x4111D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1894 0x4111D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1895 0x4111D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1896 0x4111DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1897 0x4111DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1898 0x4111DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1899 0x4111DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1900 0x4111DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1901 0x4111DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1902 0x4111DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1903 0x4111DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1904 0x4111DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1905 0x4111DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1906 0x4111DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1907 0x4111DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1908 0x4111DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1909 0x4111DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1910 0x4111DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1911 0x4111DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1912 0x4111DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1913 0x4111DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1914 0x4111DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1915 0x4111DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1916 0x4111DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1917 0x4111DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1918 0x4111DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1919 0x4111DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1920 0x4111E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1921 0x4111E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1922 0x4111E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1923 0x4111E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1924 0x4111E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1925 0x4111E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1926 0x4111E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1927 0x4111E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1928 0x4111E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1929 0x4111E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1930 0x4111E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1931 0x4111E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1932 0x4111E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1933 0x4111E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1934 0x4111E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1935 0x4111E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1936 0x4111E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1937 0x4111E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1938 0x4111E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1939 0x4111E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1940 0x4111E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1941 0x4111E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1942 0x4111E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1943 0x4111E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1944 0x4111E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1945 0x4111E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1946 0x4111E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1947 0x4111E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1948 0x4111E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1949 0x4111E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1950 0x4111E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1951 0x4111E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1952 0x4111E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1953 0x4111E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1954 0x4111E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1955 0x4111E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1956 0x4111E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1957 0x4111E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1958 0x4111E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1959 0x4111E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1960 0x4111EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1961 0x4111EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1962 0x4111EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1963 0x4111EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1964 0x4111EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1965 0x4111EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1966 0x4111EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1967 0x4111EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1968 0x4111EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1969 0x4111EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1970 0x4111EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1971 0x4111ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1972 0x4111ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1973 0x4111ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1974 0x4111ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1975 0x4111EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1976 0x4111EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1977 0x4111EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1978 0x4111EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1979 0x4111EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1980 0x4111EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1981 0x4111EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1982 0x4111EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1983 0x4111EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1984 0x4111F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1985 0x4111F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1986 0x4111F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1987 0x4111F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1988 0x4111F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1989 0x4111F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1990 0x4111F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1991 0x4111F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1992 0x4111F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1993 0x4111F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1994 0x4111F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1995 0x4111F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1996 0x4111F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1997 0x4111F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1998 0x4111F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1999 0x4111F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2000 0x4111F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2001 0x4111F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2002 0x4111F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2003 0x4111F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2004 0x4111F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2005 0x4111F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2006 0x4111F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2007 0x4111F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2008 0x4111F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2009 0x4111F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2010 0x4111F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2011 0x4111F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2012 0x4111F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2013 0x4111F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2014 0x4111F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2015 0x4111F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2016 0x4111F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2017 0x4111F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2018 0x4111F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2019 0x4111F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2020 0x4111F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2021 0x4111F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2022 0x4111F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2023 0x4111F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2024 0x4111FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2025 0x4111FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2026 0x4111FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2027 0x4111FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2028 0x4111FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2029 0x4111FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2030 0x4111FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2031 0x4111FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2032 0x4111FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2033 0x4111FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2034 0x4111FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2035 0x4111FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2036 0x4111FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2037 0x4111FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2038 0x4111FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2039 0x4111FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2040 0x4111FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2041 0x4111FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2042 0x4111FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2043 0x4111FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2044 0x4111FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2045 0x4111FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2046 0x4111FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2047 0x4111FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_0 0x4112000 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1 0x4112004 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2 0x4112008 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_3 0x411200C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_4 0x4112010 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_5 0x4112014 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_6 0x4112018 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_7 0x411201C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_8 0x4112020 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_9 0x4112024 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_10 0x4112028 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_11 0x411202C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_12 0x4112030 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_13 0x4112034 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_14 0x4112038 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_15 0x411203C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_16 0x4112040 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_17 0x4112044 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_18 0x4112048 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_19 0x411204C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_20 0x4112050 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_21 0x4112054 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_22 0x4112058 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_23 0x411205C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_24 0x4112060 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_25 0x4112064 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_26 0x4112068 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_27 0x411206C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_28 0x4112070 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_29 0x4112074 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_30 0x4112078 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_31 0x411207C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_32 0x4112080 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_33 0x4112084 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_34 0x4112088 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_35 0x411208C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_36 0x4112090 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_37 0x4112094 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_38 0x4112098 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_39 0x411209C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_40 0x41120A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_41 0x41120A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_42 0x41120A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_43 0x41120AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_44 0x41120B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_45 0x41120B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_46 0x41120B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_47 0x41120BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_48 0x41120C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_49 0x41120C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_50 0x41120C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_51 0x41120CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_52 0x41120D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_53 0x41120D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_54 0x41120D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_55 0x41120DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_56 0x41120E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_57 0x41120E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_58 0x41120E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_59 0x41120EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_60 0x41120F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_61 0x41120F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_62 0x41120F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_63 0x41120FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_64 0x4112100 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_65 0x4112104 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_66 0x4112108 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_67 0x411210C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_68 0x4112110 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_69 0x4112114 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_70 0x4112118 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_71 0x411211C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_72 0x4112120 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_73 0x4112124 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_74 0x4112128 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_75 0x411212C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_76 0x4112130 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_77 0x4112134 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_78 0x4112138 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_79 0x411213C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_80 0x4112140 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_81 0x4112144 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_82 0x4112148 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_83 0x411214C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_84 0x4112150 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_85 0x4112154 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_86 0x4112158 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_87 0x411215C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_88 0x4112160 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_89 0x4112164 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_90 0x4112168 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_91 0x411216C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_92 0x4112170 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_93 0x4112174 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_94 0x4112178 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_95 0x411217C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_96 0x4112180 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_97 0x4112184 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_98 0x4112188 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_99 0x411218C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_100 0x4112190 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_101 0x4112194 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_102 0x4112198 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_103 0x411219C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_104 0x41121A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_105 0x41121A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_106 0x41121A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_107 0x41121AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_108 0x41121B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_109 0x41121B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_110 0x41121B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_111 0x41121BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_112 0x41121C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_113 0x41121C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_114 0x41121C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_115 0x41121CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_116 0x41121D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_117 0x41121D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_118 0x41121D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_119 0x41121DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_120 0x41121E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_121 0x41121E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_122 0x41121E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_123 0x41121EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_124 0x41121F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_125 0x41121F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_126 0x41121F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_127 0x41121FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_128 0x4112200 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_129 0x4112204 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_130 0x4112208 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_131 0x411220C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_132 0x4112210 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_133 0x4112214 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_134 0x4112218 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_135 0x411221C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_136 0x4112220 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_137 0x4112224 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_138 0x4112228 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_139 0x411222C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_140 0x4112230 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_141 0x4112234 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_142 0x4112238 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_143 0x411223C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_144 0x4112240 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_145 0x4112244 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_146 0x4112248 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_147 0x411224C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_148 0x4112250 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_149 0x4112254 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_150 0x4112258 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_151 0x411225C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_152 0x4112260 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_153 0x4112264 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_154 0x4112268 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_155 0x411226C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_156 0x4112270 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_157 0x4112274 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_158 0x4112278 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_159 0x411227C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_160 0x4112280 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_161 0x4112284 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_162 0x4112288 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_163 0x411228C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_164 0x4112290 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_165 0x4112294 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_166 0x4112298 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_167 0x411229C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_168 0x41122A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_169 0x41122A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_170 0x41122A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_171 0x41122AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_172 0x41122B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_173 0x41122B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_174 0x41122B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_175 0x41122BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_176 0x41122C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_177 0x41122C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_178 0x41122C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_179 0x41122CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_180 0x41122D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_181 0x41122D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_182 0x41122D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_183 0x41122DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_184 0x41122E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_185 0x41122E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_186 0x41122E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_187 0x41122EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_188 0x41122F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_189 0x41122F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_190 0x41122F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_191 0x41122FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_192 0x4112300 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_193 0x4112304 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_194 0x4112308 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_195 0x411230C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_196 0x4112310 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_197 0x4112314 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_198 0x4112318 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_199 0x411231C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_200 0x4112320 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_201 0x4112324 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_202 0x4112328 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_203 0x411232C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_204 0x4112330 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_205 0x4112334 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_206 0x4112338 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_207 0x411233C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_208 0x4112340 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_209 0x4112344 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_210 0x4112348 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_211 0x411234C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_212 0x4112350 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_213 0x4112354 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_214 0x4112358 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_215 0x411235C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_216 0x4112360 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_217 0x4112364 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_218 0x4112368 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_219 0x411236C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_220 0x4112370 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_221 0x4112374 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_222 0x4112378 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_223 0x411237C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_224 0x4112380 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_225 0x4112384 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_226 0x4112388 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_227 0x411238C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_228 0x4112390 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_229 0x4112394 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_230 0x4112398 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_231 0x411239C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_232 0x41123A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_233 0x41123A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_234 0x41123A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_235 0x41123AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_236 0x41123B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_237 0x41123B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_238 0x41123B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_239 0x41123BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_240 0x41123C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_241 0x41123C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_242 0x41123C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_243 0x41123CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_244 0x41123D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_245 0x41123D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_246 0x41123D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_247 0x41123DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_248 0x41123E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_249 0x41123E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_250 0x41123E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_251 0x41123EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_252 0x41123F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_253 0x41123F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_254 0x41123F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_255 0x41123FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_256 0x4112400 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_257 0x4112404 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_258 0x4112408 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_259 0x411240C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_260 0x4112410 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_261 0x4112414 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_262 0x4112418 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_263 0x411241C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_264 0x4112420 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_265 0x4112424 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_266 0x4112428 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_267 0x411242C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_268 0x4112430 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_269 0x4112434 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_270 0x4112438 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_271 0x411243C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_272 0x4112440 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_273 0x4112444 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_274 0x4112448 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_275 0x411244C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_276 0x4112450 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_277 0x4112454 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_278 0x4112458 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_279 0x411245C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_280 0x4112460 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_281 0x4112464 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_282 0x4112468 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_283 0x411246C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_284 0x4112470 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_285 0x4112474 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_286 0x4112478 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_287 0x411247C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_288 0x4112480 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_289 0x4112484 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_290 0x4112488 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_291 0x411248C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_292 0x4112490 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_293 0x4112494 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_294 0x4112498 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_295 0x411249C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_296 0x41124A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_297 0x41124A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_298 0x41124A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_299 0x41124AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_300 0x41124B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_301 0x41124B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_302 0x41124B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_303 0x41124BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_304 0x41124C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_305 0x41124C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_306 0x41124C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_307 0x41124CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_308 0x41124D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_309 0x41124D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_310 0x41124D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_311 0x41124DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_312 0x41124E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_313 0x41124E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_314 0x41124E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_315 0x41124EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_316 0x41124F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_317 0x41124F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_318 0x41124F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_319 0x41124FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_320 0x4112500 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_321 0x4112504 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_322 0x4112508 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_323 0x411250C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_324 0x4112510 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_325 0x4112514 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_326 0x4112518 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_327 0x411251C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_328 0x4112520 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_329 0x4112524 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_330 0x4112528 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_331 0x411252C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_332 0x4112530 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_333 0x4112534 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_334 0x4112538 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_335 0x411253C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_336 0x4112540 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_337 0x4112544 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_338 0x4112548 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_339 0x411254C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_340 0x4112550 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_341 0x4112554 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_342 0x4112558 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_343 0x411255C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_344 0x4112560 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_345 0x4112564 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_346 0x4112568 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_347 0x411256C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_348 0x4112570 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_349 0x4112574 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_350 0x4112578 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_351 0x411257C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_352 0x4112580 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_353 0x4112584 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_354 0x4112588 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_355 0x411258C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_356 0x4112590 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_357 0x4112594 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_358 0x4112598 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_359 0x411259C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_360 0x41125A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_361 0x41125A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_362 0x41125A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_363 0x41125AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_364 0x41125B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_365 0x41125B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_366 0x41125B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_367 0x41125BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_368 0x41125C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_369 0x41125C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_370 0x41125C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_371 0x41125CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_372 0x41125D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_373 0x41125D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_374 0x41125D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_375 0x41125DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_376 0x41125E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_377 0x41125E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_378 0x41125E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_379 0x41125EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_380 0x41125F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_381 0x41125F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_382 0x41125F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_383 0x41125FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_384 0x4112600 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_385 0x4112604 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_386 0x4112608 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_387 0x411260C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_388 0x4112610 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_389 0x4112614 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_390 0x4112618 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_391 0x411261C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_392 0x4112620 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_393 0x4112624 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_394 0x4112628 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_395 0x411262C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_396 0x4112630 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_397 0x4112634 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_398 0x4112638 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_399 0x411263C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_400 0x4112640 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_401 0x4112644 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_402 0x4112648 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_403 0x411264C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_404 0x4112650 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_405 0x4112654 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_406 0x4112658 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_407 0x411265C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_408 0x4112660 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_409 0x4112664 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_410 0x4112668 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_411 0x411266C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_412 0x4112670 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_413 0x4112674 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_414 0x4112678 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_415 0x411267C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_416 0x4112680 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_417 0x4112684 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_418 0x4112688 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_419 0x411268C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_420 0x4112690 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_421 0x4112694 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_422 0x4112698 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_423 0x411269C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_424 0x41126A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_425 0x41126A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_426 0x41126A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_427 0x41126AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_428 0x41126B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_429 0x41126B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_430 0x41126B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_431 0x41126BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_432 0x41126C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_433 0x41126C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_434 0x41126C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_435 0x41126CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_436 0x41126D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_437 0x41126D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_438 0x41126D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_439 0x41126DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_440 0x41126E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_441 0x41126E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_442 0x41126E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_443 0x41126EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_444 0x41126F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_445 0x41126F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_446 0x41126F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_447 0x41126FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_448 0x4112700 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_449 0x4112704 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_450 0x4112708 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_451 0x411270C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_452 0x4112710 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_453 0x4112714 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_454 0x4112718 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_455 0x411271C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_456 0x4112720 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_457 0x4112724 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_458 0x4112728 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_459 0x411272C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_460 0x4112730 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_461 0x4112734 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_462 0x4112738 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_463 0x411273C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_464 0x4112740 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_465 0x4112744 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_466 0x4112748 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_467 0x411274C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_468 0x4112750 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_469 0x4112754 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_470 0x4112758 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_471 0x411275C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_472 0x4112760 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_473 0x4112764 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_474 0x4112768 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_475 0x411276C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_476 0x4112770 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_477 0x4112774 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_478 0x4112778 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_479 0x411277C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_480 0x4112780 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_481 0x4112784 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_482 0x4112788 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_483 0x411278C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_484 0x4112790 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_485 0x4112794 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_486 0x4112798 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_487 0x411279C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_488 0x41127A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_489 0x41127A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_490 0x41127A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_491 0x41127AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_492 0x41127B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_493 0x41127B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_494 0x41127B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_495 0x41127BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_496 0x41127C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_497 0x41127C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_498 0x41127C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_499 0x41127CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_500 0x41127D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_501 0x41127D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_502 0x41127D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_503 0x41127DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_504 0x41127E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_505 0x41127E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_506 0x41127E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_507 0x41127EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_508 0x41127F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_509 0x41127F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_510 0x41127F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_511 0x41127FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_512 0x4112800 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_513 0x4112804 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_514 0x4112808 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_515 0x411280C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_516 0x4112810 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_517 0x4112814 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_518 0x4112818 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_519 0x411281C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_520 0x4112820 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_521 0x4112824 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_522 0x4112828 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_523 0x411282C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_524 0x4112830 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_525 0x4112834 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_526 0x4112838 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_527 0x411283C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_528 0x4112840 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_529 0x4112844 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_530 0x4112848 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_531 0x411284C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_532 0x4112850 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_533 0x4112854 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_534 0x4112858 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_535 0x411285C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_536 0x4112860 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_537 0x4112864 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_538 0x4112868 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_539 0x411286C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_540 0x4112870 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_541 0x4112874 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_542 0x4112878 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_543 0x411287C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_544 0x4112880 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_545 0x4112884 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_546 0x4112888 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_547 0x411288C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_548 0x4112890 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_549 0x4112894 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_550 0x4112898 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_551 0x411289C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_552 0x41128A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_553 0x41128A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_554 0x41128A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_555 0x41128AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_556 0x41128B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_557 0x41128B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_558 0x41128B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_559 0x41128BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_560 0x41128C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_561 0x41128C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_562 0x41128C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_563 0x41128CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_564 0x41128D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_565 0x41128D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_566 0x41128D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_567 0x41128DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_568 0x41128E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_569 0x41128E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_570 0x41128E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_571 0x41128EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_572 0x41128F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_573 0x41128F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_574 0x41128F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_575 0x41128FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_576 0x4112900 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_577 0x4112904 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_578 0x4112908 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_579 0x411290C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_580 0x4112910 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_581 0x4112914 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_582 0x4112918 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_583 0x411291C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_584 0x4112920 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_585 0x4112924 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_586 0x4112928 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_587 0x411292C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_588 0x4112930 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_589 0x4112934 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_590 0x4112938 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_591 0x411293C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_592 0x4112940 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_593 0x4112944 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_594 0x4112948 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_595 0x411294C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_596 0x4112950 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_597 0x4112954 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_598 0x4112958 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_599 0x411295C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_600 0x4112960 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_601 0x4112964 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_602 0x4112968 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_603 0x411296C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_604 0x4112970 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_605 0x4112974 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_606 0x4112978 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_607 0x411297C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_608 0x4112980 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_609 0x4112984 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_610 0x4112988 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_611 0x411298C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_612 0x4112990 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_613 0x4112994 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_614 0x4112998 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_615 0x411299C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_616 0x41129A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_617 0x41129A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_618 0x41129A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_619 0x41129AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_620 0x41129B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_621 0x41129B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_622 0x41129B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_623 0x41129BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_624 0x41129C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_625 0x41129C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_626 0x41129C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_627 0x41129CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_628 0x41129D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_629 0x41129D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_630 0x41129D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_631 0x41129DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_632 0x41129E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_633 0x41129E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_634 0x41129E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_635 0x41129EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_636 0x41129F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_637 0x41129F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_638 0x41129F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_639 0x41129FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_640 0x4112A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_641 0x4112A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_642 0x4112A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_643 0x4112A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_644 0x4112A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_645 0x4112A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_646 0x4112A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_647 0x4112A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_648 0x4112A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_649 0x4112A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_650 0x4112A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_651 0x4112A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_652 0x4112A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_653 0x4112A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_654 0x4112A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_655 0x4112A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_656 0x4112A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_657 0x4112A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_658 0x4112A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_659 0x4112A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_660 0x4112A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_661 0x4112A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_662 0x4112A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_663 0x4112A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_664 0x4112A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_665 0x4112A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_666 0x4112A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_667 0x4112A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_668 0x4112A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_669 0x4112A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_670 0x4112A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_671 0x4112A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_672 0x4112A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_673 0x4112A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_674 0x4112A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_675 0x4112A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_676 0x4112A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_677 0x4112A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_678 0x4112A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_679 0x4112A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_680 0x4112AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_681 0x4112AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_682 0x4112AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_683 0x4112AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_684 0x4112AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_685 0x4112AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_686 0x4112AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_687 0x4112ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_688 0x4112AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_689 0x4112AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_690 0x4112AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_691 0x4112ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_692 0x4112AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_693 0x4112AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_694 0x4112AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_695 0x4112ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_696 0x4112AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_697 0x4112AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_698 0x4112AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_699 0x4112AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_700 0x4112AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_701 0x4112AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_702 0x4112AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_703 0x4112AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_704 0x4112B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_705 0x4112B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_706 0x4112B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_707 0x4112B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_708 0x4112B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_709 0x4112B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_710 0x4112B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_711 0x4112B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_712 0x4112B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_713 0x4112B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_714 0x4112B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_715 0x4112B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_716 0x4112B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_717 0x4112B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_718 0x4112B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_719 0x4112B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_720 0x4112B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_721 0x4112B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_722 0x4112B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_723 0x4112B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_724 0x4112B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_725 0x4112B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_726 0x4112B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_727 0x4112B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_728 0x4112B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_729 0x4112B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_730 0x4112B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_731 0x4112B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_732 0x4112B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_733 0x4112B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_734 0x4112B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_735 0x4112B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_736 0x4112B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_737 0x4112B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_738 0x4112B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_739 0x4112B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_740 0x4112B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_741 0x4112B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_742 0x4112B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_743 0x4112B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_744 0x4112BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_745 0x4112BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_746 0x4112BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_747 0x4112BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_748 0x4112BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_749 0x4112BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_750 0x4112BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_751 0x4112BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_752 0x4112BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_753 0x4112BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_754 0x4112BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_755 0x4112BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_756 0x4112BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_757 0x4112BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_758 0x4112BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_759 0x4112BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_760 0x4112BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_761 0x4112BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_762 0x4112BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_763 0x4112BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_764 0x4112BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_765 0x4112BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_766 0x4112BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_767 0x4112BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_768 0x4112C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_769 0x4112C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_770 0x4112C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_771 0x4112C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_772 0x4112C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_773 0x4112C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_774 0x4112C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_775 0x4112C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_776 0x4112C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_777 0x4112C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_778 0x4112C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_779 0x4112C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_780 0x4112C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_781 0x4112C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_782 0x4112C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_783 0x4112C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_784 0x4112C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_785 0x4112C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_786 0x4112C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_787 0x4112C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_788 0x4112C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_789 0x4112C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_790 0x4112C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_791 0x4112C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_792 0x4112C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_793 0x4112C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_794 0x4112C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_795 0x4112C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_796 0x4112C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_797 0x4112C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_798 0x4112C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_799 0x4112C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_800 0x4112C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_801 0x4112C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_802 0x4112C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_803 0x4112C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_804 0x4112C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_805 0x4112C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_806 0x4112C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_807 0x4112C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_808 0x4112CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_809 0x4112CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_810 0x4112CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_811 0x4112CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_812 0x4112CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_813 0x4112CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_814 0x4112CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_815 0x4112CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_816 0x4112CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_817 0x4112CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_818 0x4112CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_819 0x4112CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_820 0x4112CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_821 0x4112CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_822 0x4112CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_823 0x4112CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_824 0x4112CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_825 0x4112CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_826 0x4112CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_827 0x4112CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_828 0x4112CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_829 0x4112CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_830 0x4112CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_831 0x4112CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_832 0x4112D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_833 0x4112D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_834 0x4112D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_835 0x4112D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_836 0x4112D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_837 0x4112D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_838 0x4112D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_839 0x4112D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_840 0x4112D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_841 0x4112D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_842 0x4112D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_843 0x4112D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_844 0x4112D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_845 0x4112D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_846 0x4112D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_847 0x4112D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_848 0x4112D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_849 0x4112D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_850 0x4112D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_851 0x4112D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_852 0x4112D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_853 0x4112D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_854 0x4112D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_855 0x4112D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_856 0x4112D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_857 0x4112D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_858 0x4112D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_859 0x4112D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_860 0x4112D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_861 0x4112D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_862 0x4112D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_863 0x4112D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_864 0x4112D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_865 0x4112D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_866 0x4112D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_867 0x4112D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_868 0x4112D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_869 0x4112D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_870 0x4112D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_871 0x4112D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_872 0x4112DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_873 0x4112DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_874 0x4112DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_875 0x4112DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_876 0x4112DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_877 0x4112DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_878 0x4112DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_879 0x4112DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_880 0x4112DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_881 0x4112DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_882 0x4112DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_883 0x4112DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_884 0x4112DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_885 0x4112DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_886 0x4112DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_887 0x4112DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_888 0x4112DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_889 0x4112DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_890 0x4112DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_891 0x4112DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_892 0x4112DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_893 0x4112DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_894 0x4112DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_895 0x4112DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_896 0x4112E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_897 0x4112E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_898 0x4112E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_899 0x4112E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_900 0x4112E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_901 0x4112E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_902 0x4112E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_903 0x4112E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_904 0x4112E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_905 0x4112E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_906 0x4112E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_907 0x4112E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_908 0x4112E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_909 0x4112E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_910 0x4112E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_911 0x4112E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_912 0x4112E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_913 0x4112E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_914 0x4112E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_915 0x4112E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_916 0x4112E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_917 0x4112E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_918 0x4112E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_919 0x4112E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_920 0x4112E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_921 0x4112E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_922 0x4112E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_923 0x4112E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_924 0x4112E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_925 0x4112E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_926 0x4112E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_927 0x4112E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_928 0x4112E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_929 0x4112E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_930 0x4112E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_931 0x4112E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_932 0x4112E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_933 0x4112E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_934 0x4112E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_935 0x4112E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_936 0x4112EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_937 0x4112EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_938 0x4112EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_939 0x4112EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_940 0x4112EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_941 0x4112EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_942 0x4112EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_943 0x4112EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_944 0x4112EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_945 0x4112EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_946 0x4112EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_947 0x4112ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_948 0x4112ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_949 0x4112ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_950 0x4112ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_951 0x4112EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_952 0x4112EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_953 0x4112EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_954 0x4112EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_955 0x4112EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_956 0x4112EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_957 0x4112EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_958 0x4112EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_959 0x4112EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_960 0x4112F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_961 0x4112F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_962 0x4112F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_963 0x4112F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_964 0x4112F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_965 0x4112F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_966 0x4112F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_967 0x4112F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_968 0x4112F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_969 0x4112F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_970 0x4112F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_971 0x4112F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_972 0x4112F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_973 0x4112F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_974 0x4112F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_975 0x4112F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_976 0x4112F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_977 0x4112F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_978 0x4112F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_979 0x4112F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_980 0x4112F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_981 0x4112F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_982 0x4112F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_983 0x4112F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_984 0x4112F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_985 0x4112F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_986 0x4112F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_987 0x4112F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_988 0x4112F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_989 0x4112F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_990 0x4112F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_991 0x4112F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_992 0x4112F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_993 0x4112F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_994 0x4112F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_995 0x4112F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_996 0x4112F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_997 0x4112F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_998 0x4112F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_999 0x4112F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1000 0x4112FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1001 0x4112FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1002 0x4112FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1003 0x4112FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1004 0x4112FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1005 0x4112FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1006 0x4112FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1007 0x4112FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1008 0x4112FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1009 0x4112FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1010 0x4112FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1011 0x4112FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1012 0x4112FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1013 0x4112FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1014 0x4112FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1015 0x4112FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1016 0x4112FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1017 0x4112FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1018 0x4112FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1019 0x4112FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1020 0x4112FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1021 0x4112FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1022 0x4112FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1023 0x4112FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1024 0x4113000 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1025 0x4113004 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1026 0x4113008 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1027 0x411300C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1028 0x4113010 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1029 0x4113014 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1030 0x4113018 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1031 0x411301C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1032 0x4113020 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1033 0x4113024 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1034 0x4113028 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1035 0x411302C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1036 0x4113030 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1037 0x4113034 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1038 0x4113038 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1039 0x411303C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1040 0x4113040 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1041 0x4113044 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1042 0x4113048 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1043 0x411304C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1044 0x4113050 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1045 0x4113054 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1046 0x4113058 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1047 0x411305C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1048 0x4113060 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1049 0x4113064 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1050 0x4113068 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1051 0x411306C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1052 0x4113070 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1053 0x4113074 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1054 0x4113078 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1055 0x411307C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1056 0x4113080 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1057 0x4113084 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1058 0x4113088 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1059 0x411308C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1060 0x4113090 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1061 0x4113094 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1062 0x4113098 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1063 0x411309C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1064 0x41130A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1065 0x41130A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1066 0x41130A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1067 0x41130AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1068 0x41130B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1069 0x41130B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1070 0x41130B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1071 0x41130BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1072 0x41130C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1073 0x41130C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1074 0x41130C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1075 0x41130CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1076 0x41130D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1077 0x41130D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1078 0x41130D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1079 0x41130DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1080 0x41130E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1081 0x41130E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1082 0x41130E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1083 0x41130EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1084 0x41130F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1085 0x41130F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1086 0x41130F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1087 0x41130FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1088 0x4113100 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1089 0x4113104 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1090 0x4113108 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1091 0x411310C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1092 0x4113110 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1093 0x4113114 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1094 0x4113118 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1095 0x411311C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1096 0x4113120 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1097 0x4113124 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1098 0x4113128 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1099 0x411312C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1100 0x4113130 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1101 0x4113134 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1102 0x4113138 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1103 0x411313C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1104 0x4113140 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1105 0x4113144 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1106 0x4113148 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1107 0x411314C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1108 0x4113150 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1109 0x4113154 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1110 0x4113158 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1111 0x411315C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1112 0x4113160 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1113 0x4113164 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1114 0x4113168 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1115 0x411316C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1116 0x4113170 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1117 0x4113174 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1118 0x4113178 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1119 0x411317C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1120 0x4113180 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1121 0x4113184 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1122 0x4113188 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1123 0x411318C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1124 0x4113190 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1125 0x4113194 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1126 0x4113198 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1127 0x411319C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1128 0x41131A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1129 0x41131A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1130 0x41131A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1131 0x41131AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1132 0x41131B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1133 0x41131B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1134 0x41131B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1135 0x41131BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1136 0x41131C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1137 0x41131C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1138 0x41131C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1139 0x41131CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1140 0x41131D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1141 0x41131D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1142 0x41131D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1143 0x41131DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1144 0x41131E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1145 0x41131E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1146 0x41131E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1147 0x41131EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1148 0x41131F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1149 0x41131F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1150 0x41131F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1151 0x41131FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1152 0x4113200 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1153 0x4113204 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1154 0x4113208 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1155 0x411320C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1156 0x4113210 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1157 0x4113214 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1158 0x4113218 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1159 0x411321C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1160 0x4113220 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1161 0x4113224 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1162 0x4113228 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1163 0x411322C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1164 0x4113230 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1165 0x4113234 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1166 0x4113238 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1167 0x411323C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1168 0x4113240 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1169 0x4113244 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1170 0x4113248 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1171 0x411324C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1172 0x4113250 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1173 0x4113254 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1174 0x4113258 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1175 0x411325C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1176 0x4113260 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1177 0x4113264 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1178 0x4113268 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1179 0x411326C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1180 0x4113270 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1181 0x4113274 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1182 0x4113278 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1183 0x411327C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1184 0x4113280 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1185 0x4113284 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1186 0x4113288 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1187 0x411328C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1188 0x4113290 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1189 0x4113294 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1190 0x4113298 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1191 0x411329C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1192 0x41132A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1193 0x41132A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1194 0x41132A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1195 0x41132AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1196 0x41132B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1197 0x41132B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1198 0x41132B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1199 0x41132BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1200 0x41132C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1201 0x41132C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1202 0x41132C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1203 0x41132CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1204 0x41132D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1205 0x41132D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1206 0x41132D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1207 0x41132DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1208 0x41132E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1209 0x41132E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1210 0x41132E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1211 0x41132EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1212 0x41132F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1213 0x41132F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1214 0x41132F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1215 0x41132FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1216 0x4113300 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1217 0x4113304 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1218 0x4113308 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1219 0x411330C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1220 0x4113310 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1221 0x4113314 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1222 0x4113318 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1223 0x411331C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1224 0x4113320 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1225 0x4113324 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1226 0x4113328 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1227 0x411332C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1228 0x4113330 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1229 0x4113334 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1230 0x4113338 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1231 0x411333C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1232 0x4113340 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1233 0x4113344 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1234 0x4113348 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1235 0x411334C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1236 0x4113350 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1237 0x4113354 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1238 0x4113358 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1239 0x411335C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1240 0x4113360 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1241 0x4113364 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1242 0x4113368 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1243 0x411336C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1244 0x4113370 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1245 0x4113374 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1246 0x4113378 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1247 0x411337C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1248 0x4113380 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1249 0x4113384 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1250 0x4113388 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1251 0x411338C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1252 0x4113390 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1253 0x4113394 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1254 0x4113398 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1255 0x411339C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1256 0x41133A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1257 0x41133A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1258 0x41133A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1259 0x41133AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1260 0x41133B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1261 0x41133B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1262 0x41133B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1263 0x41133BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1264 0x41133C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1265 0x41133C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1266 0x41133C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1267 0x41133CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1268 0x41133D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1269 0x41133D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1270 0x41133D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1271 0x41133DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1272 0x41133E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1273 0x41133E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1274 0x41133E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1275 0x41133EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1276 0x41133F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1277 0x41133F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1278 0x41133F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1279 0x41133FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1280 0x4113400 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1281 0x4113404 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1282 0x4113408 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1283 0x411340C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1284 0x4113410 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1285 0x4113414 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1286 0x4113418 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1287 0x411341C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1288 0x4113420 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1289 0x4113424 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1290 0x4113428 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1291 0x411342C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1292 0x4113430 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1293 0x4113434 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1294 0x4113438 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1295 0x411343C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1296 0x4113440 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1297 0x4113444 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1298 0x4113448 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1299 0x411344C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1300 0x4113450 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1301 0x4113454 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1302 0x4113458 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1303 0x411345C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1304 0x4113460 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1305 0x4113464 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1306 0x4113468 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1307 0x411346C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1308 0x4113470 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1309 0x4113474 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1310 0x4113478 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1311 0x411347C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1312 0x4113480 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1313 0x4113484 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1314 0x4113488 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1315 0x411348C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1316 0x4113490 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1317 0x4113494 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1318 0x4113498 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1319 0x411349C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1320 0x41134A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1321 0x41134A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1322 0x41134A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1323 0x41134AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1324 0x41134B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1325 0x41134B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1326 0x41134B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1327 0x41134BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1328 0x41134C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1329 0x41134C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1330 0x41134C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1331 0x41134CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1332 0x41134D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1333 0x41134D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1334 0x41134D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1335 0x41134DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1336 0x41134E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1337 0x41134E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1338 0x41134E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1339 0x41134EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1340 0x41134F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1341 0x41134F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1342 0x41134F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1343 0x41134FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1344 0x4113500 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1345 0x4113504 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1346 0x4113508 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1347 0x411350C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1348 0x4113510 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1349 0x4113514 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1350 0x4113518 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1351 0x411351C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1352 0x4113520 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1353 0x4113524 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1354 0x4113528 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1355 0x411352C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1356 0x4113530 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1357 0x4113534 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1358 0x4113538 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1359 0x411353C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1360 0x4113540 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1361 0x4113544 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1362 0x4113548 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1363 0x411354C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1364 0x4113550 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1365 0x4113554 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1366 0x4113558 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1367 0x411355C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1368 0x4113560 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1369 0x4113564 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1370 0x4113568 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1371 0x411356C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1372 0x4113570 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1373 0x4113574 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1374 0x4113578 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1375 0x411357C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1376 0x4113580 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1377 0x4113584 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1378 0x4113588 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1379 0x411358C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1380 0x4113590 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1381 0x4113594 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1382 0x4113598 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1383 0x411359C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1384 0x41135A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1385 0x41135A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1386 0x41135A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1387 0x41135AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1388 0x41135B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1389 0x41135B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1390 0x41135B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1391 0x41135BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1392 0x41135C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1393 0x41135C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1394 0x41135C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1395 0x41135CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1396 0x41135D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1397 0x41135D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1398 0x41135D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1399 0x41135DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1400 0x41135E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1401 0x41135E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1402 0x41135E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1403 0x41135EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1404 0x41135F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1405 0x41135F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1406 0x41135F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1407 0x41135FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1408 0x4113600 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1409 0x4113604 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1410 0x4113608 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1411 0x411360C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1412 0x4113610 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1413 0x4113614 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1414 0x4113618 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1415 0x411361C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1416 0x4113620 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1417 0x4113624 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1418 0x4113628 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1419 0x411362C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1420 0x4113630 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1421 0x4113634 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1422 0x4113638 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1423 0x411363C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1424 0x4113640 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1425 0x4113644 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1426 0x4113648 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1427 0x411364C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1428 0x4113650 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1429 0x4113654 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1430 0x4113658 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1431 0x411365C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1432 0x4113660 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1433 0x4113664 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1434 0x4113668 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1435 0x411366C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1436 0x4113670 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1437 0x4113674 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1438 0x4113678 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1439 0x411367C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1440 0x4113680 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1441 0x4113684 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1442 0x4113688 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1443 0x411368C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1444 0x4113690 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1445 0x4113694 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1446 0x4113698 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1447 0x411369C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1448 0x41136A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1449 0x41136A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1450 0x41136A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1451 0x41136AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1452 0x41136B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1453 0x41136B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1454 0x41136B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1455 0x41136BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1456 0x41136C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1457 0x41136C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1458 0x41136C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1459 0x41136CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1460 0x41136D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1461 0x41136D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1462 0x41136D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1463 0x41136DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1464 0x41136E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1465 0x41136E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1466 0x41136E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1467 0x41136EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1468 0x41136F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1469 0x41136F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1470 0x41136F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1471 0x41136FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1472 0x4113700 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1473 0x4113704 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1474 0x4113708 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1475 0x411370C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1476 0x4113710 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1477 0x4113714 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1478 0x4113718 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1479 0x411371C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1480 0x4113720 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1481 0x4113724 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1482 0x4113728 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1483 0x411372C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1484 0x4113730 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1485 0x4113734 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1486 0x4113738 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1487 0x411373C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1488 0x4113740 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1489 0x4113744 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1490 0x4113748 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1491 0x411374C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1492 0x4113750 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1493 0x4113754 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1494 0x4113758 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1495 0x411375C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1496 0x4113760 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1497 0x4113764 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1498 0x4113768 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1499 0x411376C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1500 0x4113770 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1501 0x4113774 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1502 0x4113778 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1503 0x411377C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1504 0x4113780 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1505 0x4113784 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1506 0x4113788 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1507 0x411378C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1508 0x4113790 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1509 0x4113794 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1510 0x4113798 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1511 0x411379C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1512 0x41137A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1513 0x41137A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1514 0x41137A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1515 0x41137AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1516 0x41137B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1517 0x41137B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1518 0x41137B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1519 0x41137BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1520 0x41137C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1521 0x41137C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1522 0x41137C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1523 0x41137CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1524 0x41137D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1525 0x41137D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1526 0x41137D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1527 0x41137DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1528 0x41137E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1529 0x41137E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1530 0x41137E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1531 0x41137EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1532 0x41137F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1533 0x41137F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1534 0x41137F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1535 0x41137FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1536 0x4113800 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1537 0x4113804 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1538 0x4113808 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1539 0x411380C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1540 0x4113810 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1541 0x4113814 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1542 0x4113818 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1543 0x411381C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1544 0x4113820 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1545 0x4113824 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1546 0x4113828 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1547 0x411382C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1548 0x4113830 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1549 0x4113834 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1550 0x4113838 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1551 0x411383C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1552 0x4113840 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1553 0x4113844 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1554 0x4113848 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1555 0x411384C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1556 0x4113850 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1557 0x4113854 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1558 0x4113858 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1559 0x411385C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1560 0x4113860 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1561 0x4113864 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1562 0x4113868 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1563 0x411386C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1564 0x4113870 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1565 0x4113874 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1566 0x4113878 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1567 0x411387C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1568 0x4113880 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1569 0x4113884 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1570 0x4113888 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1571 0x411388C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1572 0x4113890 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1573 0x4113894 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1574 0x4113898 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1575 0x411389C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1576 0x41138A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1577 0x41138A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1578 0x41138A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1579 0x41138AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1580 0x41138B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1581 0x41138B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1582 0x41138B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1583 0x41138BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1584 0x41138C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1585 0x41138C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1586 0x41138C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1587 0x41138CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1588 0x41138D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1589 0x41138D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1590 0x41138D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1591 0x41138DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1592 0x41138E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1593 0x41138E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1594 0x41138E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1595 0x41138EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1596 0x41138F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1597 0x41138F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1598 0x41138F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1599 0x41138FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1600 0x4113900 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1601 0x4113904 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1602 0x4113908 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1603 0x411390C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1604 0x4113910 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1605 0x4113914 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1606 0x4113918 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1607 0x411391C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1608 0x4113920 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1609 0x4113924 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1610 0x4113928 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1611 0x411392C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1612 0x4113930 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1613 0x4113934 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1614 0x4113938 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1615 0x411393C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1616 0x4113940 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1617 0x4113944 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1618 0x4113948 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1619 0x411394C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1620 0x4113950 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1621 0x4113954 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1622 0x4113958 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1623 0x411395C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1624 0x4113960 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1625 0x4113964 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1626 0x4113968 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1627 0x411396C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1628 0x4113970 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1629 0x4113974 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1630 0x4113978 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1631 0x411397C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1632 0x4113980 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1633 0x4113984 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1634 0x4113988 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1635 0x411398C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1636 0x4113990 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1637 0x4113994 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1638 0x4113998 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1639 0x411399C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1640 0x41139A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1641 0x41139A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1642 0x41139A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1643 0x41139AC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1644 0x41139B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1645 0x41139B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1646 0x41139B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1647 0x41139BC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1648 0x41139C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1649 0x41139C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1650 0x41139C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1651 0x41139CC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1652 0x41139D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1653 0x41139D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1654 0x41139D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1655 0x41139DC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1656 0x41139E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1657 0x41139E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1658 0x41139E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1659 0x41139EC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1660 0x41139F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1661 0x41139F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1662 0x41139F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1663 0x41139FC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1664 0x4113A00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1665 0x4113A04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1666 0x4113A08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1667 0x4113A0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1668 0x4113A10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1669 0x4113A14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1670 0x4113A18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1671 0x4113A1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1672 0x4113A20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1673 0x4113A24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1674 0x4113A28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1675 0x4113A2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1676 0x4113A30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1677 0x4113A34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1678 0x4113A38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1679 0x4113A3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1680 0x4113A40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1681 0x4113A44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1682 0x4113A48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1683 0x4113A4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1684 0x4113A50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1685 0x4113A54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1686 0x4113A58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1687 0x4113A5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1688 0x4113A60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1689 0x4113A64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1690 0x4113A68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1691 0x4113A6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1692 0x4113A70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1693 0x4113A74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1694 0x4113A78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1695 0x4113A7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1696 0x4113A80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1697 0x4113A84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1698 0x4113A88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1699 0x4113A8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1700 0x4113A90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1701 0x4113A94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1702 0x4113A98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1703 0x4113A9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1704 0x4113AA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1705 0x4113AA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1706 0x4113AA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1707 0x4113AAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1708 0x4113AB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1709 0x4113AB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1710 0x4113AB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1711 0x4113ABC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1712 0x4113AC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1713 0x4113AC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1714 0x4113AC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1715 0x4113ACC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1716 0x4113AD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1717 0x4113AD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1718 0x4113AD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1719 0x4113ADC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1720 0x4113AE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1721 0x4113AE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1722 0x4113AE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1723 0x4113AEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1724 0x4113AF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1725 0x4113AF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1726 0x4113AF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1727 0x4113AFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1728 0x4113B00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1729 0x4113B04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1730 0x4113B08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1731 0x4113B0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1732 0x4113B10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1733 0x4113B14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1734 0x4113B18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1735 0x4113B1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1736 0x4113B20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1737 0x4113B24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1738 0x4113B28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1739 0x4113B2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1740 0x4113B30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1741 0x4113B34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1742 0x4113B38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1743 0x4113B3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1744 0x4113B40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1745 0x4113B44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1746 0x4113B48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1747 0x4113B4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1748 0x4113B50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1749 0x4113B54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1750 0x4113B58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1751 0x4113B5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1752 0x4113B60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1753 0x4113B64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1754 0x4113B68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1755 0x4113B6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1756 0x4113B70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1757 0x4113B74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1758 0x4113B78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1759 0x4113B7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1760 0x4113B80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1761 0x4113B84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1762 0x4113B88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1763 0x4113B8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1764 0x4113B90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1765 0x4113B94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1766 0x4113B98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1767 0x4113B9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1768 0x4113BA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1769 0x4113BA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1770 0x4113BA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1771 0x4113BAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1772 0x4113BB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1773 0x4113BB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1774 0x4113BB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1775 0x4113BBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1776 0x4113BC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1777 0x4113BC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1778 0x4113BC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1779 0x4113BCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1780 0x4113BD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1781 0x4113BD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1782 0x4113BD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1783 0x4113BDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1784 0x4113BE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1785 0x4113BE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1786 0x4113BE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1787 0x4113BEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1788 0x4113BF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1789 0x4113BF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1790 0x4113BF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1791 0x4113BFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1792 0x4113C00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1793 0x4113C04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1794 0x4113C08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1795 0x4113C0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1796 0x4113C10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1797 0x4113C14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1798 0x4113C18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1799 0x4113C1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1800 0x4113C20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1801 0x4113C24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1802 0x4113C28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1803 0x4113C2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1804 0x4113C30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1805 0x4113C34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1806 0x4113C38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1807 0x4113C3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1808 0x4113C40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1809 0x4113C44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1810 0x4113C48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1811 0x4113C4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1812 0x4113C50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1813 0x4113C54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1814 0x4113C58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1815 0x4113C5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1816 0x4113C60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1817 0x4113C64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1818 0x4113C68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1819 0x4113C6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1820 0x4113C70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1821 0x4113C74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1822 0x4113C78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1823 0x4113C7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1824 0x4113C80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1825 0x4113C84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1826 0x4113C88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1827 0x4113C8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1828 0x4113C90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1829 0x4113C94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1830 0x4113C98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1831 0x4113C9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1832 0x4113CA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1833 0x4113CA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1834 0x4113CA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1835 0x4113CAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1836 0x4113CB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1837 0x4113CB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1838 0x4113CB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1839 0x4113CBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1840 0x4113CC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1841 0x4113CC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1842 0x4113CC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1843 0x4113CCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1844 0x4113CD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1845 0x4113CD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1846 0x4113CD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1847 0x4113CDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1848 0x4113CE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1849 0x4113CE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1850 0x4113CE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1851 0x4113CEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1852 0x4113CF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1853 0x4113CF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1854 0x4113CF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1855 0x4113CFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1856 0x4113D00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1857 0x4113D04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1858 0x4113D08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1859 0x4113D0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1860 0x4113D10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1861 0x4113D14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1862 0x4113D18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1863 0x4113D1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1864 0x4113D20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1865 0x4113D24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1866 0x4113D28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1867 0x4113D2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1868 0x4113D30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1869 0x4113D34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1870 0x4113D38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1871 0x4113D3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1872 0x4113D40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1873 0x4113D44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1874 0x4113D48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1875 0x4113D4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1876 0x4113D50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1877 0x4113D54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1878 0x4113D58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1879 0x4113D5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1880 0x4113D60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1881 0x4113D64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1882 0x4113D68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1883 0x4113D6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1884 0x4113D70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1885 0x4113D74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1886 0x4113D78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1887 0x4113D7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1888 0x4113D80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1889 0x4113D84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1890 0x4113D88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1891 0x4113D8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1892 0x4113D90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1893 0x4113D94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1894 0x4113D98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1895 0x4113D9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1896 0x4113DA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1897 0x4113DA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1898 0x4113DA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1899 0x4113DAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1900 0x4113DB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1901 0x4113DB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1902 0x4113DB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1903 0x4113DBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1904 0x4113DC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1905 0x4113DC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1906 0x4113DC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1907 0x4113DCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1908 0x4113DD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1909 0x4113DD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1910 0x4113DD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1911 0x4113DDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1912 0x4113DE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1913 0x4113DE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1914 0x4113DE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1915 0x4113DEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1916 0x4113DF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1917 0x4113DF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1918 0x4113DF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1919 0x4113DFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1920 0x4113E00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1921 0x4113E04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1922 0x4113E08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1923 0x4113E0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1924 0x4113E10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1925 0x4113E14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1926 0x4113E18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1927 0x4113E1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1928 0x4113E20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1929 0x4113E24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1930 0x4113E28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1931 0x4113E2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1932 0x4113E30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1933 0x4113E34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1934 0x4113E38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1935 0x4113E3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1936 0x4113E40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1937 0x4113E44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1938 0x4113E48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1939 0x4113E4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1940 0x4113E50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1941 0x4113E54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1942 0x4113E58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1943 0x4113E5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1944 0x4113E60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1945 0x4113E64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1946 0x4113E68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1947 0x4113E6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1948 0x4113E70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1949 0x4113E74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1950 0x4113E78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1951 0x4113E7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1952 0x4113E80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1953 0x4113E84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1954 0x4113E88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1955 0x4113E8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1956 0x4113E90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1957 0x4113E94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1958 0x4113E98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1959 0x4113E9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1960 0x4113EA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1961 0x4113EA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1962 0x4113EA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1963 0x4113EAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1964 0x4113EB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1965 0x4113EB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1966 0x4113EB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1967 0x4113EBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1968 0x4113EC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1969 0x4113EC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1970 0x4113EC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1971 0x4113ECC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1972 0x4113ED0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1973 0x4113ED4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1974 0x4113ED8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1975 0x4113EDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1976 0x4113EE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1977 0x4113EE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1978 0x4113EE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1979 0x4113EEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1980 0x4113EF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1981 0x4113EF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1982 0x4113EF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1983 0x4113EFC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1984 0x4113F00 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1985 0x4113F04 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1986 0x4113F08 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1987 0x4113F0C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1988 0x4113F10 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1989 0x4113F14 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1990 0x4113F18 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1991 0x4113F1C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1992 0x4113F20 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1993 0x4113F24 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1994 0x4113F28 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1995 0x4113F2C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1996 0x4113F30 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1997 0x4113F34 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1998 0x4113F38 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1999 0x4113F3C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2000 0x4113F40 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2001 0x4113F44 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2002 0x4113F48 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2003 0x4113F4C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2004 0x4113F50 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2005 0x4113F54 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2006 0x4113F58 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2007 0x4113F5C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2008 0x4113F60 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2009 0x4113F64 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2010 0x4113F68 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2011 0x4113F6C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2012 0x4113F70 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2013 0x4113F74 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2014 0x4113F78 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2015 0x4113F7C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2016 0x4113F80 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2017 0x4113F84 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2018 0x4113F88 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2019 0x4113F8C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2020 0x4113F90 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2021 0x4113F94 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2022 0x4113F98 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2023 0x4113F9C + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2024 0x4113FA0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2025 0x4113FA4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2026 0x4113FA8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2027 0x4113FAC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2028 0x4113FB0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2029 0x4113FB4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2030 0x4113FB8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2031 0x4113FBC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2032 0x4113FC0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2033 0x4113FC4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2034 0x4113FC8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2035 0x4113FCC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2036 0x4113FD0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2037 0x4113FD4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2038 0x4113FD8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2039 0x4113FDC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2040 0x4113FE0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2041 0x4113FE4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2042 0x4113FE8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2043 0x4113FEC + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2044 0x4113FF0 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2045 0x4113FF4 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2046 0x4113FF8 + +#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2047 0x4113FFC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_0 0x4114000 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_1 0x4114004 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_2 0x4114008 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_3 0x411400C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_4 0x4114010 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_5 0x4114014 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_6 0x4114018 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_7 0x411401C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_8 0x4114020 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_9 0x4114024 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_10 0x4114028 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_11 0x411402C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_12 0x4114030 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_13 0x4114034 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_14 0x4114038 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_15 0x411403C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_16 0x4114040 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_17 0x4114044 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_18 0x4114048 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_19 0x411404C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_20 0x4114050 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_21 0x4114054 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_22 0x4114058 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_23 0x411405C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_24 0x4114060 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_25 0x4114064 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_26 0x4114068 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_27 0x411406C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_28 0x4114070 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_29 0x4114074 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_30 0x4114078 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_31 0x411407C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_32 0x4114080 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_33 0x4114084 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_34 0x4114088 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_35 0x411408C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_36 0x4114090 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_37 0x4114094 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_38 0x4114098 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_39 0x411409C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_40 0x41140A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_41 0x41140A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_42 0x41140A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_43 0x41140AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_44 0x41140B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_45 0x41140B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_46 0x41140B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_47 0x41140BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_48 0x41140C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_49 0x41140C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_50 0x41140C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_51 0x41140CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_52 0x41140D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_53 0x41140D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_54 0x41140D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_55 0x41140DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_56 0x41140E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_57 0x41140E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_58 0x41140E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_59 0x41140EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_60 0x41140F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_61 0x41140F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_62 0x41140F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_63 0x41140FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_64 0x4114100 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_65 0x4114104 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_66 0x4114108 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_67 0x411410C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_68 0x4114110 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_69 0x4114114 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_70 0x4114118 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_71 0x411411C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_72 0x4114120 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_73 0x4114124 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_74 0x4114128 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_75 0x411412C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_76 0x4114130 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_77 0x4114134 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_78 0x4114138 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_79 0x411413C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_80 0x4114140 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_81 0x4114144 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_82 0x4114148 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_83 0x411414C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_84 0x4114150 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_85 0x4114154 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_86 0x4114158 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_87 0x411415C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_88 0x4114160 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_89 0x4114164 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_90 0x4114168 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_91 0x411416C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_92 0x4114170 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_93 0x4114174 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_94 0x4114178 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_95 0x411417C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_96 0x4114180 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_97 0x4114184 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_98 0x4114188 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_99 0x411418C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_100 0x4114190 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_101 0x4114194 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_102 0x4114198 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_103 0x411419C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_104 0x41141A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_105 0x41141A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_106 0x41141A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_107 0x41141AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_108 0x41141B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_109 0x41141B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_110 0x41141B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_111 0x41141BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_112 0x41141C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_113 0x41141C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_114 0x41141C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_115 0x41141CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_116 0x41141D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_117 0x41141D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_118 0x41141D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_119 0x41141DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_120 0x41141E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_121 0x41141E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_122 0x41141E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_123 0x41141EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_124 0x41141F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_125 0x41141F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_126 0x41141F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_127 0x41141FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_128 0x4114200 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_129 0x4114204 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_130 0x4114208 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_131 0x411420C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_132 0x4114210 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_133 0x4114214 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_134 0x4114218 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_135 0x411421C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_136 0x4114220 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_137 0x4114224 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_138 0x4114228 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_139 0x411422C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_140 0x4114230 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_141 0x4114234 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_142 0x4114238 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_143 0x411423C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_144 0x4114240 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_145 0x4114244 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_146 0x4114248 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_147 0x411424C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_148 0x4114250 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_149 0x4114254 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_150 0x4114258 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_151 0x411425C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_152 0x4114260 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_153 0x4114264 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_154 0x4114268 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_155 0x411426C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_156 0x4114270 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_157 0x4114274 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_158 0x4114278 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_159 0x411427C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_160 0x4114280 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_161 0x4114284 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_162 0x4114288 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_163 0x411428C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_164 0x4114290 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_165 0x4114294 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_166 0x4114298 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_167 0x411429C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_168 0x41142A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_169 0x41142A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_170 0x41142A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_171 0x41142AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_172 0x41142B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_173 0x41142B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_174 0x41142B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_175 0x41142BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_176 0x41142C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_177 0x41142C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_178 0x41142C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_179 0x41142CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_180 0x41142D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_181 0x41142D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_182 0x41142D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_183 0x41142DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_184 0x41142E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_185 0x41142E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_186 0x41142E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_187 0x41142EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_188 0x41142F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_189 0x41142F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_190 0x41142F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_191 0x41142FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_192 0x4114300 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_193 0x4114304 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_194 0x4114308 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_195 0x411430C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_196 0x4114310 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_197 0x4114314 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_198 0x4114318 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_199 0x411431C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_200 0x4114320 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_201 0x4114324 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_202 0x4114328 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_203 0x411432C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_204 0x4114330 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_205 0x4114334 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_206 0x4114338 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_207 0x411433C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_208 0x4114340 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_209 0x4114344 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_210 0x4114348 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_211 0x411434C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_212 0x4114350 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_213 0x4114354 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_214 0x4114358 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_215 0x411435C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_216 0x4114360 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_217 0x4114364 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_218 0x4114368 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_219 0x411436C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_220 0x4114370 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_221 0x4114374 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_222 0x4114378 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_223 0x411437C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_224 0x4114380 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_225 0x4114384 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_226 0x4114388 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_227 0x411438C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_228 0x4114390 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_229 0x4114394 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_230 0x4114398 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_231 0x411439C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_232 0x41143A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_233 0x41143A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_234 0x41143A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_235 0x41143AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_236 0x41143B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_237 0x41143B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_238 0x41143B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_239 0x41143BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_240 0x41143C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_241 0x41143C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_242 0x41143C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_243 0x41143CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_244 0x41143D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_245 0x41143D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_246 0x41143D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_247 0x41143DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_248 0x41143E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_249 0x41143E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_250 0x41143E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_251 0x41143EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_252 0x41143F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_253 0x41143F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_254 0x41143F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_255 0x41143FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_256 0x4114400 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_257 0x4114404 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_258 0x4114408 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_259 0x411440C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_260 0x4114410 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_261 0x4114414 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_262 0x4114418 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_263 0x411441C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_264 0x4114420 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_265 0x4114424 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_266 0x4114428 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_267 0x411442C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_268 0x4114430 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_269 0x4114434 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_270 0x4114438 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_271 0x411443C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_272 0x4114440 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_273 0x4114444 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_274 0x4114448 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_275 0x411444C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_276 0x4114450 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_277 0x4114454 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_278 0x4114458 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_279 0x411445C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_280 0x4114460 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_281 0x4114464 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_282 0x4114468 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_283 0x411446C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_284 0x4114470 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_285 0x4114474 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_286 0x4114478 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_287 0x411447C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_288 0x4114480 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_289 0x4114484 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_290 0x4114488 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_291 0x411448C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_292 0x4114490 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_293 0x4114494 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_294 0x4114498 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_295 0x411449C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_296 0x41144A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_297 0x41144A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_298 0x41144A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_299 0x41144AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_300 0x41144B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_301 0x41144B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_302 0x41144B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_303 0x41144BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_304 0x41144C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_305 0x41144C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_306 0x41144C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_307 0x41144CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_308 0x41144D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_309 0x41144D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_310 0x41144D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_311 0x41144DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_312 0x41144E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_313 0x41144E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_314 0x41144E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_315 0x41144EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_316 0x41144F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_317 0x41144F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_318 0x41144F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_319 0x41144FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_320 0x4114500 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_321 0x4114504 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_322 0x4114508 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_323 0x411450C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_324 0x4114510 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_325 0x4114514 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_326 0x4114518 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_327 0x411451C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_328 0x4114520 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_329 0x4114524 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_330 0x4114528 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_331 0x411452C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_332 0x4114530 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_333 0x4114534 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_334 0x4114538 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_335 0x411453C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_336 0x4114540 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_337 0x4114544 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_338 0x4114548 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_339 0x411454C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_340 0x4114550 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_341 0x4114554 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_342 0x4114558 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_343 0x411455C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_344 0x4114560 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_345 0x4114564 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_346 0x4114568 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_347 0x411456C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_348 0x4114570 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_349 0x4114574 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_350 0x4114578 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_351 0x411457C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_352 0x4114580 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_353 0x4114584 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_354 0x4114588 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_355 0x411458C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_356 0x4114590 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_357 0x4114594 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_358 0x4114598 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_359 0x411459C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_360 0x41145A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_361 0x41145A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_362 0x41145A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_363 0x41145AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_364 0x41145B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_365 0x41145B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_366 0x41145B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_367 0x41145BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_368 0x41145C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_369 0x41145C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_370 0x41145C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_371 0x41145CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_372 0x41145D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_373 0x41145D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_374 0x41145D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_375 0x41145DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_376 0x41145E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_377 0x41145E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_378 0x41145E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_379 0x41145EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_380 0x41145F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_381 0x41145F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_382 0x41145F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_383 0x41145FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_384 0x4114600 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_385 0x4114604 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_386 0x4114608 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_387 0x411460C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_388 0x4114610 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_389 0x4114614 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_390 0x4114618 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_391 0x411461C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_392 0x4114620 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_393 0x4114624 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_394 0x4114628 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_395 0x411462C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_396 0x4114630 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_397 0x4114634 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_398 0x4114638 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_399 0x411463C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_400 0x4114640 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_401 0x4114644 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_402 0x4114648 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_403 0x411464C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_404 0x4114650 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_405 0x4114654 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_406 0x4114658 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_407 0x411465C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_408 0x4114660 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_409 0x4114664 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_410 0x4114668 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_411 0x411466C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_412 0x4114670 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_413 0x4114674 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_414 0x4114678 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_415 0x411467C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_416 0x4114680 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_417 0x4114684 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_418 0x4114688 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_419 0x411468C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_420 0x4114690 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_421 0x4114694 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_422 0x4114698 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_423 0x411469C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_424 0x41146A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_425 0x41146A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_426 0x41146A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_427 0x41146AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_428 0x41146B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_429 0x41146B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_430 0x41146B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_431 0x41146BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_432 0x41146C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_433 0x41146C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_434 0x41146C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_435 0x41146CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_436 0x41146D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_437 0x41146D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_438 0x41146D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_439 0x41146DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_440 0x41146E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_441 0x41146E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_442 0x41146E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_443 0x41146EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_444 0x41146F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_445 0x41146F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_446 0x41146F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_447 0x41146FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_448 0x4114700 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_449 0x4114704 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_450 0x4114708 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_451 0x411470C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_452 0x4114710 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_453 0x4114714 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_454 0x4114718 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_455 0x411471C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_456 0x4114720 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_457 0x4114724 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_458 0x4114728 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_459 0x411472C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_460 0x4114730 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_461 0x4114734 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_462 0x4114738 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_463 0x411473C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_464 0x4114740 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_465 0x4114744 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_466 0x4114748 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_467 0x411474C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_468 0x4114750 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_469 0x4114754 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_470 0x4114758 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_471 0x411475C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_472 0x4114760 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_473 0x4114764 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_474 0x4114768 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_475 0x411476C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_476 0x4114770 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_477 0x4114774 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_478 0x4114778 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_479 0x411477C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_480 0x4114780 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_481 0x4114784 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_482 0x4114788 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_483 0x411478C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_484 0x4114790 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_485 0x4114794 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_486 0x4114798 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_487 0x411479C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_488 0x41147A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_489 0x41147A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_490 0x41147A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_491 0x41147AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_492 0x41147B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_493 0x41147B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_494 0x41147B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_495 0x41147BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_496 0x41147C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_497 0x41147C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_498 0x41147C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_499 0x41147CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_500 0x41147D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_501 0x41147D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_502 0x41147D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_503 0x41147DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_504 0x41147E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_505 0x41147E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_506 0x41147E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_507 0x41147EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_508 0x41147F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_509 0x41147F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_510 0x41147F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_511 0x41147FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_512 0x4114800 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_513 0x4114804 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_514 0x4114808 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_515 0x411480C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_516 0x4114810 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_517 0x4114814 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_518 0x4114818 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_519 0x411481C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_520 0x4114820 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_521 0x4114824 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_522 0x4114828 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_523 0x411482C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_524 0x4114830 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_525 0x4114834 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_526 0x4114838 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_527 0x411483C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_528 0x4114840 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_529 0x4114844 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_530 0x4114848 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_531 0x411484C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_532 0x4114850 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_533 0x4114854 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_534 0x4114858 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_535 0x411485C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_536 0x4114860 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_537 0x4114864 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_538 0x4114868 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_539 0x411486C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_540 0x4114870 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_541 0x4114874 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_542 0x4114878 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_543 0x411487C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_544 0x4114880 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_545 0x4114884 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_546 0x4114888 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_547 0x411488C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_548 0x4114890 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_549 0x4114894 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_550 0x4114898 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_551 0x411489C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_552 0x41148A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_553 0x41148A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_554 0x41148A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_555 0x41148AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_556 0x41148B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_557 0x41148B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_558 0x41148B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_559 0x41148BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_560 0x41148C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_561 0x41148C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_562 0x41148C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_563 0x41148CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_564 0x41148D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_565 0x41148D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_566 0x41148D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_567 0x41148DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_568 0x41148E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_569 0x41148E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_570 0x41148E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_571 0x41148EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_572 0x41148F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_573 0x41148F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_574 0x41148F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_575 0x41148FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_576 0x4114900 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_577 0x4114904 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_578 0x4114908 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_579 0x411490C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_580 0x4114910 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_581 0x4114914 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_582 0x4114918 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_583 0x411491C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_584 0x4114920 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_585 0x4114924 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_586 0x4114928 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_587 0x411492C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_588 0x4114930 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_589 0x4114934 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_590 0x4114938 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_591 0x411493C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_592 0x4114940 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_593 0x4114944 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_594 0x4114948 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_595 0x411494C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_596 0x4114950 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_597 0x4114954 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_598 0x4114958 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_599 0x411495C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_600 0x4114960 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_601 0x4114964 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_602 0x4114968 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_603 0x411496C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_604 0x4114970 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_605 0x4114974 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_606 0x4114978 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_607 0x411497C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_608 0x4114980 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_609 0x4114984 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_610 0x4114988 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_611 0x411498C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_612 0x4114990 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_613 0x4114994 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_614 0x4114998 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_615 0x411499C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_616 0x41149A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_617 0x41149A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_618 0x41149A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_619 0x41149AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_620 0x41149B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_621 0x41149B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_622 0x41149B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_623 0x41149BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_624 0x41149C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_625 0x41149C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_626 0x41149C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_627 0x41149CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_628 0x41149D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_629 0x41149D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_630 0x41149D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_631 0x41149DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_632 0x41149E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_633 0x41149E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_634 0x41149E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_635 0x41149EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_636 0x41149F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_637 0x41149F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_638 0x41149F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_639 0x41149FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_0 0x4115000 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_1 0x4115004 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_2 0x4115008 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_3 0x411500C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_4 0x4115010 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_5 0x4115014 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_6 0x4115018 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_7 0x411501C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_8 0x4115020 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_9 0x4115024 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_10 0x4115028 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_11 0x411502C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_12 0x4115030 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_13 0x4115034 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_14 0x4115038 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_15 0x411503C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_16 0x4115040 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_17 0x4115044 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_18 0x4115048 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_19 0x411504C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_20 0x4115050 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_21 0x4115054 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_22 0x4115058 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_23 0x411505C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_24 0x4115060 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_25 0x4115064 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_26 0x4115068 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_27 0x411506C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_28 0x4115070 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_29 0x4115074 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_30 0x4115078 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_31 0x411507C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_32 0x4115080 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_33 0x4115084 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_34 0x4115088 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_35 0x411508C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_36 0x4115090 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_37 0x4115094 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_38 0x4115098 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_39 0x411509C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_40 0x41150A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_41 0x41150A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_42 0x41150A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_43 0x41150AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_44 0x41150B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_45 0x41150B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_46 0x41150B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_47 0x41150BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_48 0x41150C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_49 0x41150C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_50 0x41150C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_51 0x41150CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_52 0x41150D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_53 0x41150D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_54 0x41150D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_55 0x41150DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_56 0x41150E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_57 0x41150E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_58 0x41150E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_59 0x41150EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_60 0x41150F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_61 0x41150F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_62 0x41150F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_63 0x41150FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_64 0x4115100 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_65 0x4115104 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_66 0x4115108 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_67 0x411510C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_68 0x4115110 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_69 0x4115114 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_70 0x4115118 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_71 0x411511C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_72 0x4115120 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_73 0x4115124 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_74 0x4115128 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_75 0x411512C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_76 0x4115130 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_77 0x4115134 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_78 0x4115138 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_79 0x411513C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_80 0x4115140 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_81 0x4115144 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_82 0x4115148 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_83 0x411514C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_84 0x4115150 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_85 0x4115154 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_86 0x4115158 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_87 0x411515C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_88 0x4115160 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_89 0x4115164 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_90 0x4115168 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_91 0x411516C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_92 0x4115170 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_93 0x4115174 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_94 0x4115178 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_95 0x411517C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_96 0x4115180 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_97 0x4115184 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_98 0x4115188 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_99 0x411518C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_100 0x4115190 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_101 0x4115194 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_102 0x4115198 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_103 0x411519C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_104 0x41151A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_105 0x41151A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_106 0x41151A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_107 0x41151AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_108 0x41151B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_109 0x41151B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_110 0x41151B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_111 0x41151BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_112 0x41151C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_113 0x41151C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_114 0x41151C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_115 0x41151CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_116 0x41151D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_117 0x41151D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_118 0x41151D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_119 0x41151DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_120 0x41151E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_121 0x41151E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_122 0x41151E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_123 0x41151EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_124 0x41151F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_125 0x41151F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_126 0x41151F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_127 0x41151FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_128 0x4115200 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_129 0x4115204 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_130 0x4115208 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_131 0x411520C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_132 0x4115210 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_133 0x4115214 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_134 0x4115218 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_135 0x411521C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_136 0x4115220 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_137 0x4115224 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_138 0x4115228 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_139 0x411522C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_140 0x4115230 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_141 0x4115234 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_142 0x4115238 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_143 0x411523C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_144 0x4115240 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_145 0x4115244 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_146 0x4115248 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_147 0x411524C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_148 0x4115250 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_149 0x4115254 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_150 0x4115258 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_151 0x411525C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_152 0x4115260 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_153 0x4115264 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_154 0x4115268 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_155 0x411526C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_156 0x4115270 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_157 0x4115274 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_158 0x4115278 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_159 0x411527C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_160 0x4115280 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_161 0x4115284 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_162 0x4115288 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_163 0x411528C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_164 0x4115290 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_165 0x4115294 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_166 0x4115298 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_167 0x411529C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_168 0x41152A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_169 0x41152A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_170 0x41152A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_171 0x41152AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_172 0x41152B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_173 0x41152B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_174 0x41152B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_175 0x41152BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_176 0x41152C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_177 0x41152C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_178 0x41152C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_179 0x41152CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_180 0x41152D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_181 0x41152D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_182 0x41152D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_183 0x41152DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_184 0x41152E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_185 0x41152E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_186 0x41152E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_187 0x41152EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_188 0x41152F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_189 0x41152F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_190 0x41152F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_191 0x41152FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_192 0x4115300 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_193 0x4115304 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_194 0x4115308 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_195 0x411530C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_196 0x4115310 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_197 0x4115314 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_198 0x4115318 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_199 0x411531C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_200 0x4115320 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_201 0x4115324 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_202 0x4115328 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_203 0x411532C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_204 0x4115330 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_205 0x4115334 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_206 0x4115338 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_207 0x411533C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_208 0x4115340 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_209 0x4115344 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_210 0x4115348 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_211 0x411534C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_212 0x4115350 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_213 0x4115354 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_214 0x4115358 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_215 0x411535C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_216 0x4115360 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_217 0x4115364 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_218 0x4115368 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_219 0x411536C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_220 0x4115370 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_221 0x4115374 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_222 0x4115378 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_223 0x411537C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_224 0x4115380 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_225 0x4115384 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_226 0x4115388 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_227 0x411538C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_228 0x4115390 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_229 0x4115394 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_230 0x4115398 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_231 0x411539C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_232 0x41153A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_233 0x41153A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_234 0x41153A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_235 0x41153AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_236 0x41153B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_237 0x41153B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_238 0x41153B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_239 0x41153BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_240 0x41153C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_241 0x41153C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_242 0x41153C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_243 0x41153CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_244 0x41153D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_245 0x41153D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_246 0x41153D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_247 0x41153DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_248 0x41153E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_249 0x41153E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_250 0x41153E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_251 0x41153EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_252 0x41153F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_253 0x41153F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_254 0x41153F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_255 0x41153FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_256 0x4115400 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_257 0x4115404 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_258 0x4115408 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_259 0x411540C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_260 0x4115410 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_261 0x4115414 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_262 0x4115418 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_263 0x411541C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_264 0x4115420 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_265 0x4115424 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_266 0x4115428 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_267 0x411542C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_268 0x4115430 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_269 0x4115434 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_270 0x4115438 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_271 0x411543C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_272 0x4115440 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_273 0x4115444 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_274 0x4115448 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_275 0x411544C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_276 0x4115450 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_277 0x4115454 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_278 0x4115458 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_279 0x411545C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_280 0x4115460 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_281 0x4115464 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_282 0x4115468 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_283 0x411546C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_284 0x4115470 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_285 0x4115474 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_286 0x4115478 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_287 0x411547C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_288 0x4115480 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_289 0x4115484 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_290 0x4115488 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_291 0x411548C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_292 0x4115490 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_293 0x4115494 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_294 0x4115498 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_295 0x411549C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_296 0x41154A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_297 0x41154A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_298 0x41154A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_299 0x41154AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_300 0x41154B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_301 0x41154B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_302 0x41154B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_303 0x41154BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_304 0x41154C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_305 0x41154C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_306 0x41154C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_307 0x41154CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_308 0x41154D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_309 0x41154D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_310 0x41154D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_311 0x41154DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_312 0x41154E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_313 0x41154E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_314 0x41154E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_315 0x41154EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_316 0x41154F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_317 0x41154F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_318 0x41154F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_319 0x41154FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_320 0x4115500 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_321 0x4115504 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_322 0x4115508 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_323 0x411550C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_324 0x4115510 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_325 0x4115514 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_326 0x4115518 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_327 0x411551C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_328 0x4115520 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_329 0x4115524 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_330 0x4115528 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_331 0x411552C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_332 0x4115530 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_333 0x4115534 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_334 0x4115538 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_335 0x411553C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_336 0x4115540 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_337 0x4115544 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_338 0x4115548 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_339 0x411554C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_340 0x4115550 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_341 0x4115554 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_342 0x4115558 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_343 0x411555C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_344 0x4115560 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_345 0x4115564 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_346 0x4115568 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_347 0x411556C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_348 0x4115570 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_349 0x4115574 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_350 0x4115578 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_351 0x411557C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_352 0x4115580 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_353 0x4115584 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_354 0x4115588 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_355 0x411558C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_356 0x4115590 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_357 0x4115594 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_358 0x4115598 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_359 0x411559C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_360 0x41155A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_361 0x41155A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_362 0x41155A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_363 0x41155AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_364 0x41155B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_365 0x41155B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_366 0x41155B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_367 0x41155BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_368 0x41155C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_369 0x41155C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_370 0x41155C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_371 0x41155CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_372 0x41155D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_373 0x41155D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_374 0x41155D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_375 0x41155DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_376 0x41155E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_377 0x41155E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_378 0x41155E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_379 0x41155EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_380 0x41155F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_381 0x41155F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_382 0x41155F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_383 0x41155FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_384 0x4115600 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_385 0x4115604 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_386 0x4115608 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_387 0x411560C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_388 0x4115610 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_389 0x4115614 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_390 0x4115618 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_391 0x411561C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_392 0x4115620 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_393 0x4115624 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_394 0x4115628 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_395 0x411562C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_396 0x4115630 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_397 0x4115634 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_398 0x4115638 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_399 0x411563C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_400 0x4115640 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_401 0x4115644 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_402 0x4115648 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_403 0x411564C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_404 0x4115650 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_405 0x4115654 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_406 0x4115658 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_407 0x411565C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_408 0x4115660 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_409 0x4115664 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_410 0x4115668 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_411 0x411566C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_412 0x4115670 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_413 0x4115674 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_414 0x4115678 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_415 0x411567C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_416 0x4115680 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_417 0x4115684 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_418 0x4115688 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_419 0x411568C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_420 0x4115690 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_421 0x4115694 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_422 0x4115698 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_423 0x411569C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_424 0x41156A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_425 0x41156A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_426 0x41156A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_427 0x41156AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_428 0x41156B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_429 0x41156B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_430 0x41156B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_431 0x41156BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_432 0x41156C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_433 0x41156C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_434 0x41156C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_435 0x41156CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_436 0x41156D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_437 0x41156D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_438 0x41156D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_439 0x41156DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_440 0x41156E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_441 0x41156E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_442 0x41156E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_443 0x41156EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_444 0x41156F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_445 0x41156F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_446 0x41156F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_447 0x41156FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_448 0x4115700 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_449 0x4115704 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_450 0x4115708 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_451 0x411570C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_452 0x4115710 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_453 0x4115714 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_454 0x4115718 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_455 0x411571C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_456 0x4115720 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_457 0x4115724 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_458 0x4115728 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_459 0x411572C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_460 0x4115730 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_461 0x4115734 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_462 0x4115738 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_463 0x411573C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_464 0x4115740 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_465 0x4115744 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_466 0x4115748 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_467 0x411574C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_468 0x4115750 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_469 0x4115754 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_470 0x4115758 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_471 0x411575C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_472 0x4115760 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_473 0x4115764 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_474 0x4115768 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_475 0x411576C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_476 0x4115770 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_477 0x4115774 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_478 0x4115778 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_479 0x411577C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_480 0x4115780 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_481 0x4115784 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_482 0x4115788 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_483 0x411578C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_484 0x4115790 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_485 0x4115794 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_486 0x4115798 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_487 0x411579C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_488 0x41157A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_489 0x41157A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_490 0x41157A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_491 0x41157AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_492 0x41157B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_493 0x41157B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_494 0x41157B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_495 0x41157BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_496 0x41157C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_497 0x41157C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_498 0x41157C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_499 0x41157CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_500 0x41157D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_501 0x41157D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_502 0x41157D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_503 0x41157DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_504 0x41157E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_505 0x41157E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_506 0x41157E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_507 0x41157EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_508 0x41157F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_509 0x41157F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_510 0x41157F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_511 0x41157FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_512 0x4115800 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_513 0x4115804 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_514 0x4115808 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_515 0x411580C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_516 0x4115810 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_517 0x4115814 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_518 0x4115818 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_519 0x411581C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_520 0x4115820 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_521 0x4115824 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_522 0x4115828 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_523 0x411582C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_524 0x4115830 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_525 0x4115834 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_526 0x4115838 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_527 0x411583C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_528 0x4115840 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_529 0x4115844 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_530 0x4115848 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_531 0x411584C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_532 0x4115850 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_533 0x4115854 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_534 0x4115858 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_535 0x411585C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_536 0x4115860 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_537 0x4115864 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_538 0x4115868 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_539 0x411586C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_540 0x4115870 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_541 0x4115874 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_542 0x4115878 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_543 0x411587C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_544 0x4115880 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_545 0x4115884 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_546 0x4115888 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_547 0x411588C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_548 0x4115890 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_549 0x4115894 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_550 0x4115898 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_551 0x411589C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_552 0x41158A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_553 0x41158A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_554 0x41158A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_555 0x41158AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_556 0x41158B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_557 0x41158B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_558 0x41158B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_559 0x41158BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_560 0x41158C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_561 0x41158C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_562 0x41158C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_563 0x41158CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_564 0x41158D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_565 0x41158D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_566 0x41158D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_567 0x41158DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_568 0x41158E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_569 0x41158E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_570 0x41158E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_571 0x41158EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_572 0x41158F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_573 0x41158F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_574 0x41158F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_575 0x41158FC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_576 0x4115900 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_577 0x4115904 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_578 0x4115908 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_579 0x411590C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_580 0x4115910 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_581 0x4115914 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_582 0x4115918 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_583 0x411591C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_584 0x4115920 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_585 0x4115924 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_586 0x4115928 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_587 0x411592C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_588 0x4115930 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_589 0x4115934 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_590 0x4115938 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_591 0x411593C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_592 0x4115940 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_593 0x4115944 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_594 0x4115948 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_595 0x411594C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_596 0x4115950 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_597 0x4115954 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_598 0x4115958 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_599 0x411595C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_600 0x4115960 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_601 0x4115964 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_602 0x4115968 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_603 0x411596C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_604 0x4115970 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_605 0x4115974 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_606 0x4115978 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_607 0x411597C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_608 0x4115980 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_609 0x4115984 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_610 0x4115988 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_611 0x411598C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_612 0x4115990 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_613 0x4115994 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_614 0x4115998 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_615 0x411599C + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_616 0x41159A0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_617 0x41159A4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_618 0x41159A8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_619 0x41159AC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_620 0x41159B0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_621 0x41159B4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_622 0x41159B8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_623 0x41159BC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_624 0x41159C0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_625 0x41159C4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_626 0x41159C8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_627 0x41159CC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_628 0x41159D0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_629 0x41159D4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_630 0x41159D8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_631 0x41159DC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_632 0x41159E0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_633 0x41159E4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_634 0x41159E8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_635 0x41159EC + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_636 0x41159F0 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_637 0x41159F4 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_638 0x41159F8 + +#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_639 0x41159FC + +#endif /* ASIC_REG_DCORE0_SYNC_MNGR_OBJS_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_axuser_regs.h new file mode 100644 index 000000000000..2d4a22680a23 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_CFG_AXUSER_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_CFG_AXUSER_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_CFG_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_ASID 0x400BE00 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_MMU_BP 0x400BE04 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_STRONG_ORDER 0x400BE08 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_NO_SNOOP 0x400BE0C + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_WR_REDUCTION 0x400BE10 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_RD_ATOMIC 0x400BE14 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_QOS 0x400BE18 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_RSVD 0x400BE1C + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_EMEM_CPAGE 0x400BE20 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_CORE 0x400BE24 + +#define mmDCORE0_TPC0_CFG_AXUSER_E2E_COORD 0x400BE28 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_WR_OVRD_LO 0x400BE30 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_WR_OVRD_HI 0x400BE34 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_RD_OVRD_LO 0x400BE38 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_RD_OVRD_HI 0x400BE3C + +#define mmDCORE0_TPC0_CFG_AXUSER_LB_COORD 0x400BE40 + +#define mmDCORE0_TPC0_CFG_AXUSER_LB_LOCK 0x400BE44 + +#define mmDCORE0_TPC0_CFG_AXUSER_LB_RSVD 0x400BE48 + +#define mmDCORE0_TPC0_CFG_AXUSER_LB_OVRD 0x400BE4C + +#endif /* ASIC_REG_DCORE0_TPC0_CFG_AXUSER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_kernel_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_kernel_regs.h new file mode 100644 index 000000000000..cdab39debd2c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_kernel_regs.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_CFG_KERNEL_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_CFG_KERNEL_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_CFG_KERNEL + * (Prototype: TPC_NON_TENSOR_DESCRIPTOR) + ***************************************** + */ + +#define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0x400B508 + +#define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0x400B50C + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_0 0x400B510 + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_0 0x400B514 + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_1 0x400B518 + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_1 0x400B51C + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_2 0x400B520 + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_2 0x400B524 + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_3 0x400B528 + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_3 0x400B52C + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_4 0x400B530 + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_4 0x400B534 + +#define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_CONFIG 0x400B538 + +#define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_ID 0x400B53C + +#define mmDCORE0_TPC0_CFG_KERNEL_POWER_LOOP 0x400B540 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_0 0x400B544 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_1 0x400B548 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_2 0x400B54C + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_3 0x400B550 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_4 0x400B554 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_5 0x400B558 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_6 0x400B55C + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_7 0x400B560 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_8 0x400B564 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_9 0x400B568 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_10 0x400B56C + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_11 0x400B570 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_12 0x400B574 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_13 0x400B578 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_14 0x400B57C + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_15 0x400B580 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_16 0x400B584 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_17 0x400B588 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_18 0x400B58C + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_19 0x400B590 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_20 0x400B594 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_21 0x400B598 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_22 0x400B59C + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_23 0x400B5A0 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_24 0x400B5A4 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_25 0x400B5A8 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_26 0x400B5AC + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_27 0x400B5B0 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_28 0x400B5B4 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_29 0x400B5B8 + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_30 0x400B5BC + +#define mmDCORE0_TPC0_CFG_KERNEL_SRF_31 0x400B5C0 + +#define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_ID_INC 0x400B5C4 + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_0 0x400B5C8 + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_1 0x400B5CC + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_2 0x400B5D0 + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_3 0x400B5D4 + +#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_4 0x400B5D8 + +#endif /* ASIC_REG_DCORE0_TPC0_CFG_KERNEL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_kernel_tensor_0_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_kernel_tensor_0_regs.h new file mode 100644 index 000000000000..4ef1c1edc5f7 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_kernel_tensor_0_regs.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_CFG_KERNEL_TENSOR_0_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_CFG_KERNEL_TENSOR_0_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_CFG_KERNEL_TENSOR_0 + * (Prototype: TPC_TENSOR) + ***************************************** + */ + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0x400B000 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0x400B004 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0x400B008 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0x400B00C + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0x400B010 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0x400B014 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0x400B018 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0x400B01C + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0x400B020 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0x400B024 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0x400B028 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0x400B02C + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0x400B030 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0x400B034 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PREF_STRIDE 0x400B038 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH 0x400B03C + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH 0x400B040 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH 0x400B044 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH 0x400B048 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH 0x400B04C + +#endif /* ASIC_REG_DCORE0_TPC0_CFG_KERNEL_TENSOR_0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_masks.h new file mode 100644 index 000000000000..cdecbd0f9d84 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_masks.h @@ -0,0 +1,509 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_CFG_MASKS_H_ +#define ASIC_REG_DCORE0_TPC0_CFG_MASKS_H_ + +/* + ***************************************** + * DCORE0_TPC0_CFG + * (Prototype: TPC) + ***************************************** + */ + +/* DCORE0_TPC0_CFG_TPC_COUNT */ +#define DCORE0_TPC0_CFG_TPC_COUNT_V_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_COUNT_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_TPC_ID */ +#define DCORE0_TPC0_CFG_TPC_ID_V_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_ID_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_STALL_ON_ERR */ +#define DCORE0_TPC0_CFG_STALL_ON_ERR_V_SHIFT 0 +#define DCORE0_TPC0_CFG_STALL_ON_ERR_V_MASK 0x1 + +/* DCORE0_TPC0_CFG_CLK_EN */ +#define DCORE0_TPC0_CFG_CLK_EN_LBW_CFG_DIS_SHIFT 0 +#define DCORE0_TPC0_CFG_CLK_EN_LBW_CFG_DIS_MASK 0x1 +#define DCORE0_TPC0_CFG_CLK_EN_DBG_CFG_DIS_SHIFT 4 +#define DCORE0_TPC0_CFG_CLK_EN_DBG_CFG_DIS_MASK 0x10 + +/* DCORE0_TPC0_CFG_IQ_RL_EN */ +#define DCORE0_TPC0_CFG_IQ_RL_EN_V_SHIFT 0 +#define DCORE0_TPC0_CFG_IQ_RL_EN_V_MASK 0x1 + +/* DCORE0_TPC0_CFG_IQ_RL_SAT */ +#define DCORE0_TPC0_CFG_IQ_RL_SAT_V_SHIFT 0 +#define DCORE0_TPC0_CFG_IQ_RL_SAT_V_MASK 0xFF + +/* DCORE0_TPC0_CFG_IQ_RL_RST_TOKEN */ +#define DCORE0_TPC0_CFG_IQ_RL_RST_TOKEN_V_SHIFT 0 +#define DCORE0_TPC0_CFG_IQ_RL_RST_TOKEN_V_MASK 0xFF + +/* DCORE0_TPC0_CFG_IQ_RL_TIMEOUT */ +#define DCORE0_TPC0_CFG_IQ_RL_TIMEOUT_V_SHIFT 0 +#define DCORE0_TPC0_CFG_IQ_RL_TIMEOUT_V_MASK 0xFF + +/* DCORE0_TPC0_CFG_TSB_CFG_MTRR_2 */ +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_2_PHY_BASE_ADD_LO_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_2_PHY_BASE_ADD_LO_MASK 0xFFFFFF + +/* DCORE0_TPC0_CFG_IQ_LBW_CLK_EN */ +#define DCORE0_TPC0_CFG_IQ_LBW_CLK_EN_V_SHIFT 0 +#define DCORE0_TPC0_CFG_IQ_LBW_CLK_EN_V_MASK 0x1 + +/* DCORE0_TPC0_CFG_TPC_LOCK_VALUE */ +#define DCORE0_TPC0_CFG_TPC_LOCK_VALUE_VALUE_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_LOCK_VALUE_VALUE_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_TPC_LOCK */ +#define DCORE0_TPC0_CFG_TPC_LOCK_LOCK_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_LOCK_LOCK_MASK 0x1 + +/* DCORE0_TPC0_CFG_CGU_SB */ +#define DCORE0_TPC0_CFG_CGU_SB_TSB_DISABLE_SHIFT 0 +#define DCORE0_TPC0_CFG_CGU_SB_TSB_DISABLE_MASK 0x1 + +/* DCORE0_TPC0_CFG_CGU_CNT */ +#define DCORE0_TPC0_CFG_CGU_CNT_DCACHE_DISABLE_SHIFT 0 +#define DCORE0_TPC0_CFG_CGU_CNT_DCACHE_DISABLE_MASK 0x1 +#define DCORE0_TPC0_CFG_CGU_CNT_WQ_DISABLE_SHIFT 1 +#define DCORE0_TPC0_CFG_CGU_CNT_WQ_DISABLE_MASK 0x2 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_0_DISABLE_SHIFT 2 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_0_DISABLE_MASK 0x4 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_1_DISABLE_SHIFT 3 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_1_DISABLE_MASK 0x8 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_2_DISABLE_SHIFT 4 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_2_DISABLE_MASK 0x10 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_3_DISABLE_SHIFT 5 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_3_DISABLE_MASK 0x20 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_4_DISABLE_SHIFT 6 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_4_DISABLE_MASK 0x40 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_0_DISABLE_SHIFT 7 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_0_DISABLE_MASK 0x80 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_1_DISABLE_SHIFT 8 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_1_DISABLE_MASK 0x100 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_2_DISABLE_SHIFT 9 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_2_DISABLE_MASK 0x200 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_3_DISABLE_SHIFT 10 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_3_DISABLE_MASK 0x400 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_4_DISABLE_SHIFT 11 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_4_DISABLE_MASK 0x800 +#define DCORE0_TPC0_CFG_CGU_CNT_MSAC_DISABLE_SHIFT 12 +#define DCORE0_TPC0_CFG_CGU_CNT_MSAC_DISABLE_MASK 0x1000 +#define DCORE0_TPC0_CFG_CGU_CNT_CONV_DISABLE_SHIFT 13 +#define DCORE0_TPC0_CFG_CGU_CNT_CONV_DISABLE_MASK 0x2000 +#define DCORE0_TPC0_CFG_CGU_CNT_NEARBYINT_DISABLE_SHIFT 14 +#define DCORE0_TPC0_CFG_CGU_CNT_NEARBYINT_DISABLE_MASK 0x4000 +#define DCORE0_TPC0_CFG_CGU_CNT_CMP_DISABLE_SHIFT 15 +#define DCORE0_TPC0_CFG_CGU_CNT_CMP_DISABLE_MASK 0x8000 +#define DCORE0_TPC0_CFG_CGU_CNT_FP_MAC_DISABLE_SHIFT 16 +#define DCORE0_TPC0_CFG_CGU_CNT_FP_MAC_DISABLE_MASK 0x10000 +#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_A_D2_DISABLE_SHIFT 17 +#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_A_D2_DISABLE_MASK 0x20000 +#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_B_D2_DISABLE_SHIFT 18 +#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_B_D2_DISABLE_MASK 0x40000 +#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_E_D2_DISABLE_SHIFT 19 +#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_E_D2_DISABLE_MASK 0x80000 +#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_FMA_SRC_C_E1_DISABLE_SHIFT 20 +#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_FMA_SRC_C_E1_DISABLE_MASK 0x100000 +#define DCORE0_TPC0_CFG_CGU_CNT_LD_SOPS_SRC_A_D2_DISABLE_SHIFT 21 +#define DCORE0_TPC0_CFG_CGU_CNT_LD_SOPS_SRC_A_D2_DISABLE_MASK 0x200000 +#define DCORE0_TPC0_CFG_CGU_CNT_ST_SOPS_SRC_A_D2_DISABLE_SHIFT 22 +#define DCORE0_TPC0_CFG_CGU_CNT_ST_SOPS_SRC_A_D2_DISABLE_MASK 0x400000 +#define DCORE0_TPC0_CFG_CGU_CNT_FP_ADDSUB_DISABLE_SHIFT 23 +#define DCORE0_TPC0_CFG_CGU_CNT_FP_ADDSUB_DISABLE_MASK 0x800000 + +/* DCORE0_TPC0_CFG_CGU_CPE */ +#define DCORE0_TPC0_CFG_CGU_CPE_NEARBYINT_DISABLE_SHIFT 0 +#define DCORE0_TPC0_CFG_CGU_CPE_NEARBYINT_DISABLE_MASK 0x1 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_A_DISABLE_SHIFT 1 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_A_DISABLE_MASK 0x2 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_B_DISABLE_SHIFT 2 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_B_DISABLE_MASK 0x4 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_E_DISABLE_SHIFT 3 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_E_DISABLE_MASK 0x8 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_D_DISABLE_SHIFT 4 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_D_DISABLE_MASK 0x10 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_C_DISABLE_SHIFT 5 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_C_DISABLE_MASK 0x20 +#define DCORE0_TPC0_CFG_CGU_CPE_LD_SOPS_SRC_A_DISABLE_SHIFT 6 +#define DCORE0_TPC0_CFG_CGU_CPE_LD_SOPS_SRC_A_DISABLE_MASK 0x40 +#define DCORE0_TPC0_CFG_CGU_CPE_MSAC_DISABLE_SHIFT 7 +#define DCORE0_TPC0_CFG_CGU_CPE_MSAC_DISABLE_MASK 0x80 +#define DCORE0_TPC0_CFG_CGU_CPE_ADDSUB_DISABLE_SHIFT 8 +#define DCORE0_TPC0_CFG_CGU_CPE_ADDSUB_DISABLE_MASK 0x100 +#define DCORE0_TPC0_CFG_CGU_CPE_SHIFT_DISABLE_SHIFT 9 +#define DCORE0_TPC0_CFG_CGU_CPE_SHIFT_DISABLE_MASK 0x200 +#define DCORE0_TPC0_CFG_CGU_CPE_GLE_DISABLE_SHIFT 10 +#define DCORE0_TPC0_CFG_CGU_CPE_GLE_DISABLE_MASK 0x400 +#define DCORE0_TPC0_CFG_CGU_CPE_CMP_DISABLE_SHIFT 11 +#define DCORE0_TPC0_CFG_CGU_CPE_CMP_DISABLE_MASK 0x800 +#define DCORE0_TPC0_CFG_CGU_CPE_CONV_DISABLE_SHIFT 12 +#define DCORE0_TPC0_CFG_CGU_CPE_CONV_DISABLE_MASK 0x1000 +#define DCORE0_TPC0_CFG_CGU_CPE_SB_DISABLE_SHIFT 13 +#define DCORE0_TPC0_CFG_CGU_CPE_SB_DISABLE_MASK 0x2000 +#define DCORE0_TPC0_CFG_CGU_CPE_TBUF_DISABLE_SHIFT 14 +#define DCORE0_TPC0_CFG_CGU_CPE_TBUF_DISABLE_MASK 0x4000 +#define DCORE0_TPC0_CFG_CGU_CPE_ST_G_DISABLE_SHIFT 15 +#define DCORE0_TPC0_CFG_CGU_CPE_ST_G_DISABLE_MASK 0x8000 +#define DCORE0_TPC0_CFG_CGU_CPE_FP_MAC_0_DISABLE_SHIFT 16 +#define DCORE0_TPC0_CFG_CGU_CPE_FP_MAC_0_DISABLE_MASK 0x10000 +#define DCORE0_TPC0_CFG_CGU_CPE_FP_MAC_1_DISABLE_SHIFT 17 +#define DCORE0_TPC0_CFG_CGU_CPE_FP_MAC_1_DISABLE_MASK 0x20000 +#define DCORE0_TPC0_CFG_CGU_CPE_FP_ADDSUB_DISABLE_SHIFT 18 +#define DCORE0_TPC0_CFG_CGU_CPE_FP_ADDSUB_DISABLE_MASK 0x40000 +#define DCORE0_TPC0_CFG_CGU_CPE_ST_SOPS_SRC_C_DISABLE_SHIFT 19 +#define DCORE0_TPC0_CFG_CGU_CPE_ST_SOPS_SRC_C_DISABLE_MASK 0x80000 + +/* DCORE0_TPC0_CFG_FP16_FTZ_IN */ +#define DCORE0_TPC0_CFG_FP16_FTZ_IN_MODE_SHIFT 0 +#define DCORE0_TPC0_CFG_FP16_FTZ_IN_MODE_MASK 0x1 + +/* DCORE0_TPC0_CFG_DCACHE_CFG */ +#define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_DIS_SHIFT 0 +#define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_DIS_MASK 0x1 +#define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_VLD_CLR_SHIFT 1 +#define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_VLD_CLR_MASK 0x2 +#define DCORE0_TPC0_CFG_DCACHE_CFG_HALT_FLUSH_SHIFT 2 +#define DCORE0_TPC0_CFG_DCACHE_CFG_HALT_FLUSH_MASK 0x4 +#define DCORE0_TPC0_CFG_DCACHE_CFG_DEALIGN_DIS_SHIFT 3 +#define DCORE0_TPC0_CFG_DCACHE_CFG_DEALIGN_DIS_MASK 0x8 + +/* DCORE0_TPC0_CFG_E2E_CRDT_TOP */ +#define DCORE0_TPC0_CFG_E2E_CRDT_TOP_FORCE_EN_SHIFT 0 +#define DCORE0_TPC0_CFG_E2E_CRDT_TOP_FORCE_EN_MASK 0x1 +#define DCORE0_TPC0_CFG_E2E_CRDT_TOP_Y_X_FORCE_SHIFT 4 +#define DCORE0_TPC0_CFG_E2E_CRDT_TOP_Y_X_FORCE_MASK 0x1FF0 + +/* DCORE0_TPC0_CFG_TPC_DCACHE_L0CD */ +#define DCORE0_TPC0_CFG_TPC_DCACHE_L0CD_VAL_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_DCACHE_L0CD_VAL_MASK 0x1 + +/* DCORE0_TPC0_CFG_TPC_SB_L0CD */ +#define DCORE0_TPC0_CFG_TPC_SB_L0CD_VAL_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_SB_L0CD_VAL_MASK 0x1 + +/* DCORE0_TPC0_CFG_CONV_ROUND_CSR */ +#define DCORE0_TPC0_CFG_CONV_ROUND_CSR_MODE_SHIFT 0 +#define DCORE0_TPC0_CFG_CONV_ROUND_CSR_MODE_MASK 0x7 + +/* DCORE0_TPC0_CFG_TSB_OCCUPANCY */ +#define DCORE0_TPC0_CFG_TSB_OCCUPANCY_V_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_OCCUPANCY_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT */ +#define DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT_AR_SHIFT 0 +#define DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT_AR_MASK 0xFFF +#define DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT_AW_SHIFT 12 +#define DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT_AW_MASK 0xFF000 + +/* DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT */ +#define DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT_AW_SHIFT 0 +#define DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT_AW_MASK 0xFF +#define DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT_AR_SHIFT 8 +#define DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT_AR_MASK 0xFF00 + +/* DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT */ +#define DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT_AR_SHIFT 0 +#define DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT_AR_MASK 0xFFF +#define DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT_AW_SHIFT 12 +#define DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT_AW_MASK 0xFFF000 + +/* DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT */ +#define DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT_AR_SHIFT 0 +#define DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT_AR_MASK 0xFF +#define DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT_AW_SHIFT 8 +#define DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT_AW_MASK 0xFFF00 + +/* DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO */ +#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI */ +#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO */ +#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI */ +#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO */ +#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI */ +#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO */ +#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI */ +#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_SPE_LFSR_POLYNOM */ +#define DCORE0_TPC0_CFG_SPE_LFSR_POLYNOM_V_SHIFT 0 +#define DCORE0_TPC0_CFG_SPE_LFSR_POLYNOM_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL */ +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL_EN_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL_EN_MASK 0x1 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL_DEFAULT_MEMORY_TYPE_SHIFT 4 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL_DEFAULT_MEMORY_TYPE_MASK 0x10 + +/* DCORE0_TPC0_CFG_TSB_CFG_MTRR */ +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_VALID_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_VALID_MASK 0x1 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MEMORY_TYPE_SHIFT 4 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MEMORY_TYPE_MASK 0x10 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_PHY_BASE_ADD_SHIFT 8 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_PHY_BASE_ADD_MASK 0xFFFF00 + +/* DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO */ +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI */ +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_V_MASK 0xFF + +/* DCORE0_TPC0_CFG_FP8_143_BIAS */ +#define DCORE0_TPC0_CFG_FP8_143_BIAS_BIAS_143_SHIFT 0 +#define DCORE0_TPC0_CFG_FP8_143_BIAS_BIAS_143_MASK 0xF + +/* DCORE0_TPC0_CFG_ROUND_CSR */ +#define DCORE0_TPC0_CFG_ROUND_CSR_MODE_SHIFT 0 +#define DCORE0_TPC0_CFG_ROUND_CSR_MODE_MASK 0x7 + +/* DCORE0_TPC0_CFG_HB_PROT */ +#define DCORE0_TPC0_CFG_HB_PROT_AWPROT_SHIFT 0 +#define DCORE0_TPC0_CFG_HB_PROT_AWPROT_MASK 0x7 +#define DCORE0_TPC0_CFG_HB_PROT_ARPROT_SHIFT 3 +#define DCORE0_TPC0_CFG_HB_PROT_ARPROT_MASK 0x38 + +/* DCORE0_TPC0_CFG_LB_PROT */ +#define DCORE0_TPC0_CFG_LB_PROT_AWPROT_SHIFT 0 +#define DCORE0_TPC0_CFG_LB_PROT_AWPROT_MASK 0x7 +#define DCORE0_TPC0_CFG_LB_PROT_ARPROT_SHIFT 3 +#define DCORE0_TPC0_CFG_LB_PROT_ARPROT_MASK 0x38 + +/* DCORE0_TPC0_CFG_SEMAPHORE */ +#define DCORE0_TPC0_CFG_SEMAPHORE_V_SHIFT 0 +#define DCORE0_TPC0_CFG_SEMAPHORE_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_VFLAGS */ +#define DCORE0_TPC0_CFG_VFLAGS_V_SHIFT 0 +#define DCORE0_TPC0_CFG_VFLAGS_V_MASK 0x7F + +/* DCORE0_TPC0_CFG_SFLAGS */ +#define DCORE0_TPC0_CFG_SFLAGS_V_SHIFT 0 +#define DCORE0_TPC0_CFG_SFLAGS_V_MASK 0x7F + +/* DCORE0_TPC0_CFG_LFSR_POLYNOM */ +#define DCORE0_TPC0_CFG_LFSR_POLYNOM_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LFSR_POLYNOM_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_STATUS */ +#define DCORE0_TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT 1 +#define DCORE0_TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK 0x2 +#define DCORE0_TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT 2 +#define DCORE0_TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK 0x4 +#define DCORE0_TPC0_CFG_STATUS_IQ_EMPTY_SHIFT 3 +#define DCORE0_TPC0_CFG_STATUS_IQ_EMPTY_MASK 0x8 +#define DCORE0_TPC0_CFG_STATUS_SB_EMPTY_SHIFT 5 +#define DCORE0_TPC0_CFG_STATUS_SB_EMPTY_MASK 0x20 +#define DCORE0_TPC0_CFG_STATUS_QM_IDLE_SHIFT 6 +#define DCORE0_TPC0_CFG_STATUS_QM_IDLE_MASK 0x40 +#define DCORE0_TPC0_CFG_STATUS_QM_RDY_SHIFT 7 +#define DCORE0_TPC0_CFG_STATUS_QM_RDY_MASK 0x80 + +/* DCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH */ +#define DCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define DCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_CFG_SUBTRACT_VALUE */ +#define DCORE0_TPC0_CFG_CFG_SUBTRACT_VALUE_V_SHIFT 0 +#define DCORE0_TPC0_CFG_CFG_SUBTRACT_VALUE_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH */ +#define DCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define DCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_TPC_CMD */ +#define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_MASK 0x1 +#define DCORE0_TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_SHIFT 1 +#define DCORE0_TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_MASK 0x2 +#define DCORE0_TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_SHIFT 2 +#define DCORE0_TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_MASK 0x4 +#define DCORE0_TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_SHIFT 3 +#define DCORE0_TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_MASK 0x8 +#define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT 4 +#define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_MASK 0x10 +#define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_SHIFT 5 +#define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_MASK 0x20 +#define DCORE0_TPC0_CFG_TPC_CMD_QMAN_STOP_SHIFT 6 +#define DCORE0_TPC0_CFG_TPC_CMD_QMAN_STOP_MASK 0x40 + +/* DCORE0_TPC0_CFG_TPC_EXECUTE */ +#define DCORE0_TPC0_CFG_TPC_EXECUTE_V_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_EXECUTE_V_MASK 0x1 + +/* DCORE0_TPC0_CFG_TPC_STALL */ +#define DCORE0_TPC0_CFG_TPC_STALL_V_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_STALL_V_MASK 0x1 + +/* DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW */ +#define DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_SHIFT 0 +#define DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH */ +#define DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_SHIFT 0 +#define DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_RD_RATE_LIMIT */ +#define DCORE0_TPC0_CFG_RD_RATE_LIMIT_ENABLE_SHIFT 0 +#define DCORE0_TPC0_CFG_RD_RATE_LIMIT_ENABLE_MASK 0x1 +#define DCORE0_TPC0_CFG_RD_RATE_LIMIT_SATURATION_SHIFT 1 +#define DCORE0_TPC0_CFG_RD_RATE_LIMIT_SATURATION_MASK 0x1FE +#define DCORE0_TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_SHIFT 9 +#define DCORE0_TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_MASK 0x1FE00 + +/* DCORE0_TPC0_CFG_WR_RATE_LIMIT */ +#define DCORE0_TPC0_CFG_WR_RATE_LIMIT_ENABLE_SHIFT 0 +#define DCORE0_TPC0_CFG_WR_RATE_LIMIT_ENABLE_MASK 0x1 +#define DCORE0_TPC0_CFG_WR_RATE_LIMIT_SATURATION_SHIFT 1 +#define DCORE0_TPC0_CFG_WR_RATE_LIMIT_SATURATION_MASK 0x1FE +#define DCORE0_TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_SHIFT 9 +#define DCORE0_TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_MASK 0x1FE00 + +/* DCORE0_TPC0_CFG_MSS_CONFIG */ +#define DCORE0_TPC0_CFG_MSS_CONFIG_AWCACHE_SHIFT 0 +#define DCORE0_TPC0_CFG_MSS_CONFIG_AWCACHE_MASK 0xF +#define DCORE0_TPC0_CFG_MSS_CONFIG_ARCACHE_SHIFT 4 +#define DCORE0_TPC0_CFG_MSS_CONFIG_ARCACHE_MASK 0xF0 +#define DCORE0_TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_SHIFT 8 +#define DCORE0_TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_MASK 0x300 +#define DCORE0_TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_SHIFT 10 +#define DCORE0_TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_MASK 0x400 +#define DCORE0_TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_SHIFT 11 +#define DCORE0_TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_MASK 0x800 + +/* DCORE0_TPC0_CFG_TPC_INTR_CAUSE */ +#define DCORE0_TPC0_CFG_TPC_INTR_CAUSE_CAUSE_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_TPC_INTR_MASK */ +#define DCORE0_TPC0_CFG_TPC_INTR_MASK_MASK_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_INTR_MASK_MASK_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_WQ_CREDITS */ +#define DCORE0_TPC0_CFG_WQ_CREDITS_ST_G_SHIFT 0 +#define DCORE0_TPC0_CFG_WQ_CREDITS_ST_G_MASK 0xF +#define DCORE0_TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_SHIFT 4 +#define DCORE0_TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_MASK 0x70 + +/* DCORE0_TPC0_CFG_OPCODE_EXEC */ +#define DCORE0_TPC0_CFG_OPCODE_EXEC_SPU_OP_SHIFT 0 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_SPU_OP_MASK 0x7F +#define DCORE0_TPC0_CFG_OPCODE_EXEC_SPU_EN_SHIFT 7 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_SPU_EN_MASK 0x80 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_VPU_OP_SHIFT 8 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_VPU_OP_MASK 0x7F00 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_VPU_EN_SHIFT 15 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_VPU_EN_MASK 0x8000 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_LD_OP_SHIFT 16 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_LD_OP_MASK 0x7F0000 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_LD_EN_SHIFT 23 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_LD_EN_MASK 0x800000 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_ST_OP_SHIFT 24 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_ST_OP_MASK 0x7F000000 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_ST_EN_SHIFT 31 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_ST_EN_MASK 0x80000000 + +/* DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO */ +#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI */ +#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO */ +#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI */ +#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO */ +#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI */ +#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO */ +#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI */ +#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE */ +#define DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_MASK 0xFFFF +#define DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE_MD_SHIFT 16 +#define DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE_MD_MASK 0xFFFF0000 + +/* DCORE0_TPC0_CFG_TSB_CFG */ +#define DCORE0_TPC0_CFG_TSB_CFG_CACHE_DISABLE_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_CFG_CACHE_DISABLE_MASK 0x1 +#define DCORE0_TPC0_CFG_TSB_CFG_MAX_OS_SHIFT 1 +#define DCORE0_TPC0_CFG_TSB_CFG_MAX_OS_MASK 0x1FFFE +#define DCORE0_TPC0_CFG_TSB_CFG_ENABLE_CGATE_SHIFT 17 +#define DCORE0_TPC0_CFG_TSB_CFG_ENABLE_CGATE_MASK 0x20000 + +/* DCORE0_TPC0_CFG_TSB_INFLIGHT_CNTR */ +#define DCORE0_TPC0_CFG_TSB_INFLIGHT_CNTR_V_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_INFLIGHT_CNTR_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR */ +#define DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_SHIFT 0 +#define DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_MASK 0xFFFF +#define DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_SHIFT 16 +#define DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_MASK 0x1FF0000 + +/* DCORE0_TPC0_CFG_WQ_LBW_TOTAL_CNTR */ +#define DCORE0_TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_SHIFT 0 +#define DCORE0_TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_WQ_HBW_TOTAL_CNTR */ +#define DCORE0_TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_SHIFT 0 +#define DCORE0_TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_IRQ_OCCOUPY_CNTR */ +#define DCORE0_TPC0_CFG_IRQ_OCCOUPY_CNTR_V_SHIFT 0 +#define DCORE0_TPC0_CFG_IRQ_OCCOUPY_CNTR_V_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_DCORE0_TPC0_CFG_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_regs.h new file mode 100644 index 000000000000..4cd9e26a150f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_regs.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_CFG_QM_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_CFG_QM_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_CFG_QM + * (Prototype: TPC_NON_TENSOR_DESCRIPTOR) + ***************************************** + */ + +#define mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0x400BAE4 + +#define mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0x400BAE8 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_0 0x400BAEC + +#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_0 0x400BAF0 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_1 0x400BAF4 + +#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_1 0x400BAF8 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_2 0x400BAFC + +#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_2 0x400BB00 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_3 0x400BB04 + +#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_3 0x400BB08 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_4 0x400BB0C + +#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_4 0x400BB10 + +#define mmDCORE0_TPC0_CFG_QM_KERNEL_CONFIG 0x400BB14 + +#define mmDCORE0_TPC0_CFG_QM_KERNEL_ID 0x400BB18 + +#define mmDCORE0_TPC0_CFG_QM_POWER_LOOP 0x400BB1C + +#define mmDCORE0_TPC0_CFG_QM_SRF_0 0x400BB20 + +#define mmDCORE0_TPC0_CFG_QM_SRF_1 0x400BB24 + +#define mmDCORE0_TPC0_CFG_QM_SRF_2 0x400BB28 + +#define mmDCORE0_TPC0_CFG_QM_SRF_3 0x400BB2C + +#define mmDCORE0_TPC0_CFG_QM_SRF_4 0x400BB30 + +#define mmDCORE0_TPC0_CFG_QM_SRF_5 0x400BB34 + +#define mmDCORE0_TPC0_CFG_QM_SRF_6 0x400BB38 + +#define mmDCORE0_TPC0_CFG_QM_SRF_7 0x400BB3C + +#define mmDCORE0_TPC0_CFG_QM_SRF_8 0x400BB40 + +#define mmDCORE0_TPC0_CFG_QM_SRF_9 0x400BB44 + +#define mmDCORE0_TPC0_CFG_QM_SRF_10 0x400BB48 + +#define mmDCORE0_TPC0_CFG_QM_SRF_11 0x400BB4C + +#define mmDCORE0_TPC0_CFG_QM_SRF_12 0x400BB50 + +#define mmDCORE0_TPC0_CFG_QM_SRF_13 0x400BB54 + +#define mmDCORE0_TPC0_CFG_QM_SRF_14 0x400BB58 + +#define mmDCORE0_TPC0_CFG_QM_SRF_15 0x400BB5C + +#define mmDCORE0_TPC0_CFG_QM_SRF_16 0x400BB60 + +#define mmDCORE0_TPC0_CFG_QM_SRF_17 0x400BB64 + +#define mmDCORE0_TPC0_CFG_QM_SRF_18 0x400BB68 + +#define mmDCORE0_TPC0_CFG_QM_SRF_19 0x400BB6C + +#define mmDCORE0_TPC0_CFG_QM_SRF_20 0x400BB70 + +#define mmDCORE0_TPC0_CFG_QM_SRF_21 0x400BB74 + +#define mmDCORE0_TPC0_CFG_QM_SRF_22 0x400BB78 + +#define mmDCORE0_TPC0_CFG_QM_SRF_23 0x400BB7C + +#define mmDCORE0_TPC0_CFG_QM_SRF_24 0x400BB80 + +#define mmDCORE0_TPC0_CFG_QM_SRF_25 0x400BB84 + +#define mmDCORE0_TPC0_CFG_QM_SRF_26 0x400BB88 + +#define mmDCORE0_TPC0_CFG_QM_SRF_27 0x400BB8C + +#define mmDCORE0_TPC0_CFG_QM_SRF_28 0x400BB90 + +#define mmDCORE0_TPC0_CFG_QM_SRF_29 0x400BB94 + +#define mmDCORE0_TPC0_CFG_QM_SRF_30 0x400BB98 + +#define mmDCORE0_TPC0_CFG_QM_SRF_31 0x400BB9C + +#define mmDCORE0_TPC0_CFG_QM_KERNEL_ID_INC 0x400BBA0 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_0 0x400BBA4 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_1 0x400BBA8 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_2 0x400BBAC + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_3 0x400BBB0 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_4 0x400BBB4 + +#endif /* ASIC_REG_DCORE0_TPC0_CFG_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_sync_object_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_sync_object_regs.h new file mode 100644 index 000000000000..8da278a3f3fe --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_sync_object_regs.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_CFG_QM_SYNC_OBJECT_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_CFG_QM_SYNC_OBJECT_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_CFG_QM_SYNC_OBJECT + * (Prototype: SYNC_OBJECT) + ***************************************** + */ + +#define mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_MESSAGE 0x400BADC + +#define mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_ADDR 0x400BAE0 + +#endif /* ASIC_REG_DCORE0_TPC0_CFG_QM_SYNC_OBJECT_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_tensor_0_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_tensor_0_regs.h new file mode 100644 index 000000000000..2e4ff06e4858 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_tensor_0_regs.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_CFG_QM_TENSOR_0_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_CFG_QM_TENSOR_0_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_CFG_QM_TENSOR_0 + * (Prototype: TPC_TENSOR) + ***************************************** + */ + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0x400B5DC + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0x400B5E0 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_PADDING_VALUE 0x400B5E4 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG 0x400B5E8 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE 0x400B5EC + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE 0x400B5F0 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE 0x400B5F4 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE 0x400B5F8 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE 0x400B5FC + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE 0x400B600 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE 0x400B604 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE 0x400B608 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE 0x400B60C + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE 0x400B610 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_PREF_STRIDE 0x400B614 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH 0x400B618 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH 0x400B61C + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH 0x400B620 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH 0x400B624 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH 0x400B628 + +#endif /* ASIC_REG_DCORE0_TPC0_CFG_QM_TENSOR_0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_regs.h new file mode 100644 index 000000000000..4d48f0c6880b --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_regs.h @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_CFG_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_CFG_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_CFG + * (Prototype: TPC) + ***************************************** + */ + +#define mmDCORE0_TPC0_CFG_TPC_COUNT 0x400BC18 + +#define mmDCORE0_TPC0_CFG_TPC_ID 0x400BC1C + +#define mmDCORE0_TPC0_CFG_STALL_ON_ERR 0x400BC20 + +#define mmDCORE0_TPC0_CFG_CLK_EN 0x400BC24 + +#define mmDCORE0_TPC0_CFG_IQ_RL_EN 0x400BC28 + +#define mmDCORE0_TPC0_CFG_IQ_RL_SAT 0x400BC2C + +#define mmDCORE0_TPC0_CFG_IQ_RL_RST_TOKEN 0x400BC30 + +#define mmDCORE0_TPC0_CFG_IQ_RL_TIMEOUT 0x400BC34 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_0 0x400BC38 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_1 0x400BC3C + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_2 0x400BC40 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_3 0x400BC44 + +#define mmDCORE0_TPC0_CFG_IQ_LBW_CLK_EN 0x400BC48 + +#define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0 0x400BC4C + +#define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_1 0x400BC50 + +#define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_2 0x400BC54 + +#define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_3 0x400BC58 + +#define mmDCORE0_TPC0_CFG_TPC_LOCK_0 0x400BC5C + +#define mmDCORE0_TPC0_CFG_TPC_LOCK_1 0x400BC60 + +#define mmDCORE0_TPC0_CFG_TPC_LOCK_2 0x400BC64 + +#define mmDCORE0_TPC0_CFG_TPC_LOCK_3 0x400BC68 + +#define mmDCORE0_TPC0_CFG_CGU_SB 0x400BC6C + +#define mmDCORE0_TPC0_CFG_CGU_CNT 0x400BC70 + +#define mmDCORE0_TPC0_CFG_CGU_CPE_0 0x400BC74 + +#define mmDCORE0_TPC0_CFG_CGU_CPE_1 0x400BC78 + +#define mmDCORE0_TPC0_CFG_CGU_CPE_2 0x400BC7C + +#define mmDCORE0_TPC0_CFG_CGU_CPE_3 0x400BC80 + +#define mmDCORE0_TPC0_CFG_CGU_CPE_4 0x400BC84 + +#define mmDCORE0_TPC0_CFG_CGU_CPE_5 0x400BC88 + +#define mmDCORE0_TPC0_CFG_CGU_CPE_6 0x400BC8C + +#define mmDCORE0_TPC0_CFG_CGU_CPE_7 0x400BC90 + +#define mmDCORE0_TPC0_CFG_FP16_FTZ_IN 0x400BC94 + +#define mmDCORE0_TPC0_CFG_DCACHE_CFG 0x400BC98 + +#define mmDCORE0_TPC0_CFG_E2E_CRDT_TOP 0x400BC9C + +#define mmDCORE0_TPC0_CFG_TPC_DCACHE_L0CD 0x400BCA0 + +#define mmDCORE0_TPC0_CFG_TPC_SB_L0CD 0x400BCA4 + +#define mmDCORE0_TPC0_CFG_CONV_ROUND_CSR 0x400BCA8 + +#define mmDCORE0_TPC0_CFG_TSB_OCCUPANCY 0x400BCAC + +#define mmDCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT 0x400BCB0 + +#define mmDCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT 0x400BCB4 + +#define mmDCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT 0x400BCB8 + +#define mmDCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT 0x400BCBC + +#define mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO 0x400BCC0 + +#define mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI 0x400BCC4 + +#define mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO 0x400BCC8 + +#define mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI 0x400BCCC + +#define mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO 0x400BCD0 + +#define mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI 0x400BCD4 + +#define mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO 0x400BCD8 + +#define mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI 0x400BCDC + +#define mmDCORE0_TPC0_CFG_SPE_LFSR_POLYNOM 0x400BCE0 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL 0x400BCE4 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_0 0x400BCE8 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_1 0x400BCEC + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2 0x400BCF0 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_3 0x400BCF4 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_0 0x400BCF8 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_1 0x400BCFC + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_2 0x400BD00 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_3 0x400BD04 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_0 0x400BD08 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_1 0x400BD0C + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_2 0x400BD10 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_3 0x400BD14 + +#define mmDCORE0_TPC0_CFG_FP8_143_BIAS 0x400BD64 + +#define mmDCORE0_TPC0_CFG_ROUND_CSR 0x400BD68 + +#define mmDCORE0_TPC0_CFG_HB_PROT 0x400BD6C + +#define mmDCORE0_TPC0_CFG_LB_PROT 0x400BD70 + +#define mmDCORE0_TPC0_CFG_SEMAPHORE 0x400BD74 + +#define mmDCORE0_TPC0_CFG_VFLAGS 0x400BD78 + +#define mmDCORE0_TPC0_CFG_SFLAGS 0x400BD7C + +#define mmDCORE0_TPC0_CFG_LFSR_POLYNOM 0x400BD80 + +#define mmDCORE0_TPC0_CFG_STATUS 0x400BD84 + +#define mmDCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH 0x400BD88 + +#define mmDCORE0_TPC0_CFG_CFG_SUBTRACT_VALUE 0x400BD8C + +#define mmDCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH 0x400BD90 + +#define mmDCORE0_TPC0_CFG_TPC_CMD 0x400BD94 + +#define mmDCORE0_TPC0_CFG_TPC_EXECUTE 0x400BD98 + +#define mmDCORE0_TPC0_CFG_TPC_STALL 0x400BD9C + +#define mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW 0x400BDA0 + +#define mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH 0x400BDA4 + +#define mmDCORE0_TPC0_CFG_RD_RATE_LIMIT 0x400BDA8 + +#define mmDCORE0_TPC0_CFG_WR_RATE_LIMIT 0x400BDAC + +#define mmDCORE0_TPC0_CFG_MSS_CONFIG 0x400BDB0 + +#define mmDCORE0_TPC0_CFG_TPC_INTR_CAUSE 0x400BDB4 + +#define mmDCORE0_TPC0_CFG_TPC_INTR_MASK 0x400BDB8 + +#define mmDCORE0_TPC0_CFG_WQ_CREDITS 0x400BDBC + +#define mmDCORE0_TPC0_CFG_OPCODE_EXEC 0x400BDC0 + +#define mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO 0x400BDC4 + +#define mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI 0x400BDC8 + +#define mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO 0x400BDCC + +#define mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI 0x400BDD0 + +#define mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO 0x400BDD4 + +#define mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI 0x400BDD8 + +#define mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO 0x400BDDC + +#define mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI 0x400BDE0 + +#define mmDCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE 0x400BDE4 + +#define mmDCORE0_TPC0_CFG_TSB_CFG 0x400BDE8 + +#define mmDCORE0_TPC0_CFG_TSB_INFLIGHT_CNTR 0x400BDEC + +#define mmDCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR 0x400BDF0 + +#define mmDCORE0_TPC0_CFG_WQ_LBW_TOTAL_CNTR 0x400BDF4 + +#define mmDCORE0_TPC0_CFG_WQ_HBW_TOTAL_CNTR 0x400BDF8 + +#define mmDCORE0_TPC0_CFG_IRQ_OCCOUPY_CNTR 0x400BDFC + +#endif /* ASIC_REG_DCORE0_TPC0_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_special_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_special_regs.h new file mode 100644 index 000000000000..76ab8a1a7f31 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_special_regs.h @@ -0,0 +1,185 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_CFG_SPECIAL_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_CFG_SPECIAL_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_CFG_SPECIAL + * (Prototype: SPECIAL_REGS) + ***************************************** + */ + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_0 0x400BE80 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_1 0x400BE84 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_2 0x400BE88 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_3 0x400BE8C + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_4 0x400BE90 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_5 0x400BE94 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_6 0x400BE98 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_7 0x400BE9C + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_8 0x400BEA0 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_9 0x400BEA4 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_10 0x400BEA8 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_11 0x400BEAC + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_12 0x400BEB0 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_13 0x400BEB4 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_14 0x400BEB8 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_15 0x400BEBC + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_16 0x400BEC0 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_17 0x400BEC4 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_18 0x400BEC8 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_19 0x400BECC + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_20 0x400BED0 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_21 0x400BED4 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_22 0x400BED8 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_23 0x400BEDC + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_24 0x400BEE0 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_25 0x400BEE4 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_26 0x400BEE8 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_27 0x400BEEC + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_28 0x400BEF0 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_29 0x400BEF4 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_30 0x400BEF8 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_31 0x400BEFC + +#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_GW_DATA 0x400BF00 + +#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_GW_REQ 0x400BF04 + +#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_NUMOF 0x400BF0C + +#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_SEL 0x400BF10 + +#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_CTL 0x400BF14 + +#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_ERR_MASK 0x400BF18 + +#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_GLBL_ERR_MASK 0x400BF1C + +#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_ERR_STS 0x400BF20 + +#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_ERR_ADDR 0x400BF24 + +#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_RM 0x400BF28 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_ERR_MASK 0x400BF40 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_ERR_ADDR 0x400BF44 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_ERR_CAUSE 0x400BF48 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_0 0x400BF60 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_1 0x400BF64 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_2 0x400BF68 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_3 0x400BF6C + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_0 0x400BF80 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_1 0x400BF84 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_2 0x400BF88 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_3 0x400BF8C + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_4 0x400BF90 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_5 0x400BF94 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_6 0x400BF98 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_7 0x400BF9C + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_8 0x400BFA0 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_9 0x400BFA4 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_10 0x400BFA8 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_11 0x400BFAC + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_12 0x400BFB0 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_13 0x400BFB4 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_14 0x400BFB8 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_15 0x400BFBC + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_16 0x400BFC0 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_17 0x400BFC4 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_18 0x400BFC8 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_19 0x400BFCC + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_20 0x400BFD0 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_21 0x400BFD4 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_22 0x400BFD8 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_23 0x400BFDC + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_24 0x400BFE0 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_25 0x400BFE4 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_26 0x400BFE8 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_27 0x400BFEC + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_28 0x400BFF0 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_29 0x400BFF4 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_30 0x400BFF8 + +#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_31 0x400BFFC + +#endif /* ASIC_REG_DCORE0_TPC0_CFG_SPECIAL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_busmon_0_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_busmon_0_regs.h new file mode 100644 index 000000000000..f07da4a24f06 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_busmon_0_regs.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_EML_BUSMON_0_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_EML_BUSMON_0_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_EML_BUSMON_0 + * (Prototype: BMON) + ***************************************** + */ + +#define mmDCORE0_TPC0_EML_BUSMON_0_CR 0x7000 + +#define mmDCORE0_TPC0_EML_BUSMON_0_REG_RESET 0x7004 + +#define mmDCORE0_TPC0_EML_BUSMON_0_INT_CLR 0x7008 + +#define mmDCORE0_TPC0_EML_BUSMON_0_TRIG_TH 0x700C + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S0 0x7020 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S0 0x7024 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E0 0x7028 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E0 0x702C + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S1 0x7030 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S1 0x7034 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E1 0x7038 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E1 0x703C + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S2 0x7040 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S2 0x7044 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E2 0x7048 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E2 0x704C + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S3 0x7050 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S3 0x7054 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E3 0x7058 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E3 0x705C + +#define mmDCORE0_TPC0_EML_BUSMON_0_REDUCTION 0x7060 + +#define mmDCORE0_TPC0_EML_BUSMON_0_IDL 0x7070 + +#define mmDCORE0_TPC0_EML_BUSMON_0_IDH 0x7074 + +#define mmDCORE0_TPC0_EML_BUSMON_0_IDENL 0x7078 + +#define mmDCORE0_TPC0_EML_BUSMON_0_IDENH 0x707C + +#define mmDCORE0_TPC0_EML_BUSMON_0_LATENCY_SMP 0x7090 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ATTR 0x7100 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ATTREN 0x7104 + +#define mmDCORE0_TPC0_EML_BUSMON_0_USRENL 0x7108 + +#define mmDCORE0_TPC0_EML_BUSMON_0_USRL 0x710C + +#define mmDCORE0_TPC0_EML_BUSMON_0_USRENH 0x7120 + +#define mmDCORE0_TPC0_EML_BUSMON_0_USRH 0x7124 + +#define mmDCORE0_TPC0_EML_BUSMON_0_CAPTURE 0x7200 + +#define mmDCORE0_TPC0_EML_BUSMON_0_RELEASE 0x7204 + +#define mmDCORE0_TPC0_EML_BUSMON_0_WIN_CAPTURE 0x7208 + +#define mmDCORE0_TPC0_EML_BUSMON_0_BW_WIN 0x720C + +#define mmDCORE0_TPC0_EML_BUSMON_0_MATCH_CNT_SOD 0x7220 + +#define mmDCORE0_TPC0_EML_BUSMON_0_MATCH_CNT_WIN 0x7224 + +#define mmDCORE0_TPC0_EML_BUSMON_0_CYCCNT_L 0x7228 + +#define mmDCORE0_TPC0_EML_BUSMON_0_CYCCNT_H 0x722C + +#define mmDCORE0_TPC0_EML_BUSMON_0_MAXLAT_SOD 0x7304 + +#define mmDCORE0_TPC0_EML_BUSMON_0_MINLAT_SOD 0x7308 + +#define mmDCORE0_TPC0_EML_BUSMON_0_MAXBW_SOD 0x7310 + +#define mmDCORE0_TPC0_EML_BUSMON_0_MINBW_SOD 0x7314 + +#define mmDCORE0_TPC0_EML_BUSMON_0_MAXOS_SOD 0x7320 + +#define mmDCORE0_TPC0_EML_BUSMON_0_MINOS_SOD 0x7324 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_SNAPSHOT 0x7400 + +#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_SNAPSHOT 0x7404 + +#define mmDCORE0_TPC0_EML_BUSMON_0_IDL_SNAPSHOT 0x7408 + +#define mmDCORE0_TPC0_EML_BUSMON_0_IDH_SNAPSHOT 0x740C + +#define mmDCORE0_TPC0_EML_BUSMON_0_ATTR_SNAPSHOT 0x7410 + +#define mmDCORE0_TPC0_EML_BUSMON_0_STM_TRC 0x7420 + +#define mmDCORE0_TPC0_EML_BUSMON_0_STM_TRC_DROP 0x7424 + +#define mmDCORE0_TPC0_EML_BUSMON_0_DEVARCH 0x7FBC + +#define mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID2 0x7FC0 + +#define mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID1 0x7FC4 + +#define mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID 0x7FC8 + +#define mmDCORE0_TPC0_EML_BUSMON_0_DEVTYPE 0x7FCC + +#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR4 0x7FD0 + +#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR5 0x7FD4 + +#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR6 0x7FD8 + +#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR7 0x7FDC + +#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR0 0x7FE0 + +#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR1 0x7FE4 + +#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR2 0x7FE8 + +#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR3 0x7FEC + +#define mmDCORE0_TPC0_EML_BUSMON_0_CIDR0 0x7FF0 + +#define mmDCORE0_TPC0_EML_BUSMON_0_CIDR1 0x7FF4 + +#define mmDCORE0_TPC0_EML_BUSMON_0_CIDR2 0x7FF8 + +#define mmDCORE0_TPC0_EML_BUSMON_0_CIDR3 0x7FFC + +#endif /* ASIC_REG_DCORE0_TPC0_EML_BUSMON_0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_etf_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_etf_regs.h new file mode 100644 index 000000000000..aee9cbc78c3d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_etf_regs.h @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_EML_ETF_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_EML_ETF_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_EML_ETF + * (Prototype: ETF_1KB) + ***************************************** + */ + +#define mmDCORE0_TPC0_EML_ETF_RSZ 0x2004 + +#define mmDCORE0_TPC0_EML_ETF_STS 0x200C + +#define mmDCORE0_TPC0_EML_ETF_RRD 0x2010 + +#define mmDCORE0_TPC0_EML_ETF_RRP 0x2014 + +#define mmDCORE0_TPC0_EML_ETF_RWP 0x2018 + +#define mmDCORE0_TPC0_EML_ETF_TRG 0x201C + +#define mmDCORE0_TPC0_EML_ETF_CTL 0x2020 + +#define mmDCORE0_TPC0_EML_ETF_RWD 0x2024 + +#define mmDCORE0_TPC0_EML_ETF_MODE 0x2028 + +#define mmDCORE0_TPC0_EML_ETF_LBUFLEVEL 0x202C + +#define mmDCORE0_TPC0_EML_ETF_CBUFLEVEL 0x2030 + +#define mmDCORE0_TPC0_EML_ETF_BUFWM 0x2034 + +#define mmDCORE0_TPC0_EML_ETF_FFSR 0x2300 + +#define mmDCORE0_TPC0_EML_ETF_FFCR 0x2304 + +#define mmDCORE0_TPC0_EML_ETF_PSCR 0x2308 + +#define mmDCORE0_TPC0_EML_ETF_ITATBMDATA0 0x2ED0 + +#define mmDCORE0_TPC0_EML_ETF_ITATBMCTR2 0x2ED4 + +#define mmDCORE0_TPC0_EML_ETF_ITATBMCTR1 0x2ED8 + +#define mmDCORE0_TPC0_EML_ETF_ITATBMCTR0 0x2EDC + +#define mmDCORE0_TPC0_EML_ETF_ITMISCOP0 0x2EE0 + +#define mmDCORE0_TPC0_EML_ETF_ITTRFLIN 0x2EE8 + +#define mmDCORE0_TPC0_EML_ETF_ITATBDATA0 0x2EEC + +#define mmDCORE0_TPC0_EML_ETF_ITATBCTR2 0x2EF0 + +#define mmDCORE0_TPC0_EML_ETF_ITATBCTR1 0x2EF4 + +#define mmDCORE0_TPC0_EML_ETF_ITATBCTR0 0x2EF8 + +#define mmDCORE0_TPC0_EML_ETF_ITCTRL 0x2F00 + +#define mmDCORE0_TPC0_EML_ETF_CLAIMSET 0x2FA0 + +#define mmDCORE0_TPC0_EML_ETF_CLAIMCLR 0x2FA4 + +#define mmDCORE0_TPC0_EML_ETF_LAR 0x2FB0 + +#define mmDCORE0_TPC0_EML_ETF_LSR 0x2FB4 + +#define mmDCORE0_TPC0_EML_ETF_AUTHSTATUS 0x2FB8 + +#define mmDCORE0_TPC0_EML_ETF_DEVID 0x2FC8 + +#define mmDCORE0_TPC0_EML_ETF_DEVTYPE 0x2FCC + +#define mmDCORE0_TPC0_EML_ETF_PERIPHID4 0x2FD0 + +#define mmDCORE0_TPC0_EML_ETF_PERIPHID5 0x2FD4 + +#define mmDCORE0_TPC0_EML_ETF_PERIPHID6 0x2FD8 + +#define mmDCORE0_TPC0_EML_ETF_PERIPHID7 0x2FDC + +#define mmDCORE0_TPC0_EML_ETF_PERIPHID0 0x2FE0 + +#define mmDCORE0_TPC0_EML_ETF_PERIPHID1 0x2FE4 + +#define mmDCORE0_TPC0_EML_ETF_PERIPHID2 0x2FE8 + +#define mmDCORE0_TPC0_EML_ETF_PERIPHID3 0x2FEC + +#define mmDCORE0_TPC0_EML_ETF_COMPID0 0x2FF0 + +#define mmDCORE0_TPC0_EML_ETF_COMPID1 0x2FF4 + +#define mmDCORE0_TPC0_EML_ETF_COMPID2 0x2FF8 + +#define mmDCORE0_TPC0_EML_ETF_COMPID3 0x2FFC + +#endif /* ASIC_REG_DCORE0_TPC0_EML_ETF_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_funnel_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_funnel_regs.h new file mode 100644 index 000000000000..dee670b666ee --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_funnel_regs.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_EML_FUNNEL_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_EML_FUNNEL_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_EML_FUNNEL + * (Prototype: FUNNEL_2X1) + ***************************************** + */ + +#define mmDCORE0_TPC0_EML_FUNNEL_CTRL_REG 0x6000 + +#define mmDCORE0_TPC0_EML_FUNNEL_PRIORITY_CTRL_REG 0x6004 + +#define mmDCORE0_TPC0_EML_FUNNEL_ITATBDATA0 0x6EEC + +#define mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR2 0x6EF0 + +#define mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR1 0x6EF4 + +#define mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR0 0x6EF8 + +#define mmDCORE0_TPC0_EML_FUNNEL_ITCTRL 0x6F00 + +#define mmDCORE0_TPC0_EML_FUNNEL_CLAIMSET 0x6FA0 + +#define mmDCORE0_TPC0_EML_FUNNEL_CLAIMCLR 0x6FA4 + +#define mmDCORE0_TPC0_EML_FUNNEL_LOCKACCESS 0x6FB0 + +#define mmDCORE0_TPC0_EML_FUNNEL_LOCKSTATUS 0x6FB4 + +#define mmDCORE0_TPC0_EML_FUNNEL_AUTHSTATUS 0x6FB8 + +#define mmDCORE0_TPC0_EML_FUNNEL_DEVID 0x6FC8 + +#define mmDCORE0_TPC0_EML_FUNNEL_DEVTYPE 0x6FCC + +#define mmDCORE0_TPC0_EML_FUNNEL_PIDR4 0x6FD0 + +#define mmDCORE0_TPC0_EML_FUNNEL_PERIPHID5 0x6FD4 + +#define mmDCORE0_TPC0_EML_FUNNEL_PERIPHID6 0x6FD8 + +#define mmDCORE0_TPC0_EML_FUNNEL_PERIPHID7 0x6FDC + +#define mmDCORE0_TPC0_EML_FUNNEL_PIDR0 0x6FE0 + +#define mmDCORE0_TPC0_EML_FUNNEL_PIDR1 0x6FE4 + +#define mmDCORE0_TPC0_EML_FUNNEL_PIDR2 0x6FE8 + +#define mmDCORE0_TPC0_EML_FUNNEL_PIDR3 0x6FEC + +#define mmDCORE0_TPC0_EML_FUNNEL_CID0 0x6FF0 + +#define mmDCORE0_TPC0_EML_FUNNEL_CID1 0x6FF4 + +#define mmDCORE0_TPC0_EML_FUNNEL_CID2 0x6FF8 + +#define mmDCORE0_TPC0_EML_FUNNEL_CID3 0x6FFC + +#endif /* ASIC_REG_DCORE0_TPC0_EML_FUNNEL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_spmu_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_spmu_regs.h new file mode 100644 index 000000000000..580ae57476bd --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_spmu_regs.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_EML_SPMU_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_EML_SPMU_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_EML_SPMU + * (Prototype: SPMU) + ***************************************** + */ + +#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR0_EL0 0x1000 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR1_EL0 0x1008 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR2_EL0 0x1010 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR3_EL0 0x1018 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR4_EL0 0x1020 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR5_EL0 0x1028 + +#define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_L_EL0 0x10F8 + +#define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_H_EL0 0x10FC + +#define mmDCORE0_TPC0_EML_SPMU_PMTRC 0x1200 + +#define mmDCORE0_TPC0_EML_SPMU_TRC_CTRL_HOST 0x1204 + +#define mmDCORE0_TPC0_EML_SPMU_TRC_STAT_HOST 0x1208 + +#define mmDCORE0_TPC0_EML_SPMU_TRC_EN_HOST 0x120C + +#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER0_EL0 0x1400 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER1_EL0 0x1404 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER2_EL0 0x1408 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER3_EL0 0x140C + +#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER4_EL0 0x1410 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER5_EL0 0x1414 + +#define mmDCORE0_TPC0_EML_SPMU_PMSSR 0x1610 + +#define mmDCORE0_TPC0_EML_SPMU_PMOVSSR 0x1614 + +#define mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_L 0x1618 + +#define mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_H 0x161C + +#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR0 0x1620 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR1 0x1624 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR2 0x1628 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR3 0x162C + +#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR4 0x1630 + +#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR5 0x1634 + +#define mmDCORE0_TPC0_EML_SPMU_PMSCR 0x16F0 + +#define mmDCORE0_TPC0_EML_SPMU_PMSRR 0x16F4 + +#define mmDCORE0_TPC0_EML_SPMU_PMCNTENSET_EL0 0x1C00 + +#define mmDCORE0_TPC0_EML_SPMU_PMCNTENCLR_EL0 0x1C20 + +#define mmDCORE0_TPC0_EML_SPMU_PMINTENSET_EL1 0x1C40 + +#define mmDCORE0_TPC0_EML_SPMU_PMINTENCLR_EL1 0x1C60 + +#define mmDCORE0_TPC0_EML_SPMU_PMOVSCLR_EL0 0x1C80 + +#define mmDCORE0_TPC0_EML_SPMU_PMSWINC_EL0 0x1CA0 + +#define mmDCORE0_TPC0_EML_SPMU_PMOVSSET_EL0 0x1CC0 + +#define mmDCORE0_TPC0_EML_SPMU_PMCFGR 0x1E00 + +#define mmDCORE0_TPC0_EML_SPMU_PMCR_EL0 0x1E04 + +#define mmDCORE0_TPC0_EML_SPMU_PMITCTRL 0x1F00 + +#define mmDCORE0_TPC0_EML_SPMU_PMCLAIMSET 0x1FA0 + +#define mmDCORE0_TPC0_EML_SPMU_PMCLAIMCLR 0x1FA4 + +#define mmDCORE0_TPC0_EML_SPMU_PMDEVAFF0 0x1FA8 + +#define mmDCORE0_TPC0_EML_SPMU_PMDEVAFF1 0x1FAC + +#define mmDCORE0_TPC0_EML_SPMU_PMLAR 0x1FB0 + +#define mmDCORE0_TPC0_EML_SPMU_PMLSR 0x1FB4 + +#define mmDCORE0_TPC0_EML_SPMU_PMAUTHSTATUS 0x1FB8 + +#define mmDCORE0_TPC0_EML_SPMU_PMDEVARCH 0x1FBC + +#define mmDCORE0_TPC0_EML_SPMU_PMDEVID2 0x1FC0 + +#define mmDCORE0_TPC0_EML_SPMU_PMDEVID1 0x1FC4 + +#define mmDCORE0_TPC0_EML_SPMU_PMDEVID 0x1FC8 + +#define mmDCORE0_TPC0_EML_SPMU_PMDEVTYPE 0x1FCC + +#define mmDCORE0_TPC0_EML_SPMU_PMPIDR4 0x1FD0 + +#define mmDCORE0_TPC0_EML_SPMU_PMPIDR5 0x1FD4 + +#define mmDCORE0_TPC0_EML_SPMU_PMPIDR6 0x1FD8 + +#define mmDCORE0_TPC0_EML_SPMU_PMPIDR7 0x1FDC + +#define mmDCORE0_TPC0_EML_SPMU_PMPIDR0 0x1FE0 + +#define mmDCORE0_TPC0_EML_SPMU_PMPIDR1 0x1FE4 + +#define mmDCORE0_TPC0_EML_SPMU_PMPIDR2 0x1FE8 + +#define mmDCORE0_TPC0_EML_SPMU_PMPIDR3 0x1FEC + +#define mmDCORE0_TPC0_EML_SPMU_PMCIDR0 0x1FF0 + +#define mmDCORE0_TPC0_EML_SPMU_PMCIDR1 0x1FF4 + +#define mmDCORE0_TPC0_EML_SPMU_PMCIDR2 0x1FF8 + +#define mmDCORE0_TPC0_EML_SPMU_PMCIDR3 0x1FFC + +#endif /* ASIC_REG_DCORE0_TPC0_EML_SPMU_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_stm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_stm_regs.h new file mode 100644 index 000000000000..91686c563fe5 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_stm_regs.h @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_EML_STM_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_EML_STM_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_EML_STM + * (Prototype: STM) + ***************************************** + */ + +#define mmDCORE0_TPC0_EML_STM_STMDMASTARTR 0x3C04 + +#define mmDCORE0_TPC0_EML_STM_STMDMASTOPR 0x3C08 + +#define mmDCORE0_TPC0_EML_STM_STMDMASTATR 0x3C0C + +#define mmDCORE0_TPC0_EML_STM_STMDMACTLR 0x3C10 + +#define mmDCORE0_TPC0_EML_STM_STMDMAIDR 0x3CFC + +#define mmDCORE0_TPC0_EML_STM_STMHEER 0x3D00 + +#define mmDCORE0_TPC0_EML_STM_STMHETER 0x3D20 + +#define mmDCORE0_TPC0_EML_STM_STMHEBSR 0x3D60 + +#define mmDCORE0_TPC0_EML_STM_STMHEMCR 0x3D64 + +#define mmDCORE0_TPC0_EML_STM_STMHEEXTMUXR 0x3D68 + +#define mmDCORE0_TPC0_EML_STM_STMHEMASTR 0x3DF4 + +#define mmDCORE0_TPC0_EML_STM_STMHEFEAT1R 0x3DF8 + +#define mmDCORE0_TPC0_EML_STM_STMHEIDR 0x3DFC + +#define mmDCORE0_TPC0_EML_STM_STMSPER 0x3E00 + +#define mmDCORE0_TPC0_EML_STM_STMSPTER 0x3E20 + +#define mmDCORE0_TPC0_EML_STM_STMSPSCR 0x3E60 + +#define mmDCORE0_TPC0_EML_STM_STMSPMSCR 0x3E64 + +#define mmDCORE0_TPC0_EML_STM_STMSPOVERRIDER 0x3E68 + +#define mmDCORE0_TPC0_EML_STM_STMSPMOVERRIDER 0x3E6C + +#define mmDCORE0_TPC0_EML_STM_STMSPTRIGCSR 0x3E70 + +#define mmDCORE0_TPC0_EML_STM_STMTCSR 0x3E80 + +#define mmDCORE0_TPC0_EML_STM_STMTSSTIMR 0x3E84 + +#define mmDCORE0_TPC0_EML_STM_STMTSFREQR 0x3E8C + +#define mmDCORE0_TPC0_EML_STM_STMSYNCR 0x3E90 + +#define mmDCORE0_TPC0_EML_STM_STMAUXCR 0x3E94 + +#define mmDCORE0_TPC0_EML_STM_STMFEAT1R 0x3EA0 + +#define mmDCORE0_TPC0_EML_STM_STMFEAT2R 0x3EA4 + +#define mmDCORE0_TPC0_EML_STM_STMFEAT3R 0x3EA8 + +#define mmDCORE0_TPC0_EML_STM_STMITTRIGGER 0x3EE8 + +#define mmDCORE0_TPC0_EML_STM_STMITATBDATA0 0x3EEC + +#define mmDCORE0_TPC0_EML_STM_STMITATBCTR2 0x3EF0 + +#define mmDCORE0_TPC0_EML_STM_STMITATBID 0x3EF4 + +#define mmDCORE0_TPC0_EML_STM_STMITATBCTR0 0x3EF8 + +#define mmDCORE0_TPC0_EML_STM_STMITCTRL 0x3F00 + +#define mmDCORE0_TPC0_EML_STM_STMCLAIMSET 0x3FA0 + +#define mmDCORE0_TPC0_EML_STM_STMCLAIMCLR 0x3FA4 + +#define mmDCORE0_TPC0_EML_STM_STMLAR 0x3FB0 + +#define mmDCORE0_TPC0_EML_STM_STMLSR 0x3FB4 + +#define mmDCORE0_TPC0_EML_STM_STMAUTHSTATUS 0x3FB8 + +#define mmDCORE0_TPC0_EML_STM_STMDEVARCH 0x3FBC + +#define mmDCORE0_TPC0_EML_STM_STMDEVID 0x3FC8 + +#define mmDCORE0_TPC0_EML_STM_STMDEVTYPE 0x3FCC + +#define mmDCORE0_TPC0_EML_STM_STMPIDR4 0x3FD0 + +#define mmDCORE0_TPC0_EML_STM_STMPIDR5 0x3FD4 + +#define mmDCORE0_TPC0_EML_STM_STMPIDR6 0x3FD8 + +#define mmDCORE0_TPC0_EML_STM_STMPIDR7 0x3FDC + +#define mmDCORE0_TPC0_EML_STM_STMPIDR0 0x3FE0 + +#define mmDCORE0_TPC0_EML_STM_STMPIDR1 0x3FE4 + +#define mmDCORE0_TPC0_EML_STM_STMPIDR2 0x3FE8 + +#define mmDCORE0_TPC0_EML_STM_STMPIDR3 0x3FEC + +#define mmDCORE0_TPC0_EML_STM_STMCIDR0 0x3FF0 + +#define mmDCORE0_TPC0_EML_STM_STMCIDR1 0x3FF4 + +#define mmDCORE0_TPC0_EML_STM_STMCIDR2 0x3FF8 + +#define mmDCORE0_TPC0_EML_STM_STMCIDR3 0x3FFC + +#endif /* ASIC_REG_DCORE0_TPC0_EML_STM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_arc_aux_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_arc_aux_regs.h new file mode 100644 index 000000000000..e007dabc5382 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_arc_aux_regs.h @@ -0,0 +1,591 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_QM_ARC_AUX_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_QM_ARC_AUX_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_QM_ARC_AUX + * (Prototype: QMAN_ARC_AUX) + ***************************************** + */ + +#define mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_REQ 0x4008100 + +#define mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_ACK 0x4008104 + +#define mmDCORE0_TPC0_QM_ARC_AUX_RST_VEC_ADDR 0x4008108 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DBG_MODE 0x400810C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CLUSTER_NUM 0x4008110 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_NUM 0x4008114 + +#define mmDCORE0_TPC0_QM_ARC_AUX_WAKE_UP_EVENT 0x4008118 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x400811C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CTI_AP_STS 0x4008120 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x4008124 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST 0x4008128 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST_REQ 0x400812C + +#define mmDCORE0_TPC0_QM_ARC_AUX_SRAM_LSB_ADDR 0x4008130 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SRAM_MSB_ADDR 0x4008134 + +#define mmDCORE0_TPC0_QM_ARC_AUX_PCIE_LSB_ADDR 0x4008138 + +#define mmDCORE0_TPC0_QM_ARC_AUX_PCIE_MSB_ADDR 0x400813C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LSB_ADDR 0x4008140 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_MSB_ADDR 0x4008144 + +#define mmDCORE0_TPC0_QM_ARC_AUX_HBM0_LSB_ADDR 0x4008150 + +#define mmDCORE0_TPC0_QM_ARC_AUX_HBM0_MSB_ADDR 0x4008154 + +#define mmDCORE0_TPC0_QM_ARC_AUX_HBM1_LSB_ADDR 0x4008158 + +#define mmDCORE0_TPC0_QM_ARC_AUX_HBM1_MSB_ADDR 0x400815C + +#define mmDCORE0_TPC0_QM_ARC_AUX_HBM2_LSB_ADDR 0x4008160 + +#define mmDCORE0_TPC0_QM_ARC_AUX_HBM2_MSB_ADDR 0x4008164 + +#define mmDCORE0_TPC0_QM_ARC_AUX_HBM3_LSB_ADDR 0x4008168 + +#define mmDCORE0_TPC0_QM_ARC_AUX_HBM3_MSB_ADDR 0x400816C + +#define mmDCORE0_TPC0_QM_ARC_AUX_HBM0_OFFSET 0x4008170 + +#define mmDCORE0_TPC0_QM_ARC_AUX_HBM1_OFFSET 0x4008174 + +#define mmDCORE0_TPC0_QM_ARC_AUX_HBM2_OFFSET 0x4008178 + +#define mmDCORE0_TPC0_QM_ARC_AUX_HBM3_OFFSET 0x400817C + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x4008180 + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x4008184 + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x4008188 + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x400818C + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x4008190 + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x4008194 + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x4008198 + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x400819C + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x40081A0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x40081A4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x40081A8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x40081AC + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x40081B0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x40081B4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_CBU_AWCACHE_OVR 0x40081B8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_LBU_AWCACHE_OVR 0x40081BC + +#define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_0 0x40081C0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_1 0x40081C4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_2 0x40081C8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_3 0x40081CC + +#define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_4 0x40081D0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_5 0x40081D4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_6 0x40081D8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_7 0x40081DC + +#define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_0 0x40081E0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_1 0x40081E4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_2 0x40081E8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_3 0x40081EC + +#define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_4 0x40081F0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_5 0x40081F4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_6 0x40081F8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_7 0x40081FC + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_0 0x4008200 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_1 0x4008204 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_2 0x4008208 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_3 0x400820C + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_4 0x4008210 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_5 0x4008214 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_6 0x4008218 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_7 0x400821C + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_8 0x4008220 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_9 0x4008224 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_10 0x4008228 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_11 0x400822C + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_12 0x4008230 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_13 0x4008234 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_14 0x4008238 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_15 0x400823C + +#define mmDCORE0_TPC0_QM_ARC_AUX_IRQ_INTR_MASK_0 0x4008280 + +#define mmDCORE0_TPC0_QM_ARC_AUX_IRQ_INTR_MASK_1 0x4008284 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_STS 0x4008290 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_CLR 0x4008294 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_MASK 0x4008298 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_EXCPTN_CAUSE 0x400829C + +#define mmDCORE0_TPC0_QM_ARC_AUX_SEI_INTR_HALT_EN 0x40082A0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_HALT_MASK 0x40082A4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_SEI_INTR_HALT_MASK 0x40082A8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REI_INTR_STS 0x40082B0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REI_INTR_CLR 0x40082B4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REI_INTR_MASK 0x40082B8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_ECC_ERR_ADDR 0x40082BC + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_ECC_SYNDROME 0x40082C0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_I_CACHE_ECC_ERR_ADDR 0x40082C4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_I_CACHE_ECC_SYNDROME 0x40082C8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_D_CACHE_ECC_ERR_ADDR 0x40082CC + +#define mmDCORE0_TPC0_QM_ARC_AUX_D_CACHE_ECC_SYNDROME 0x40082D0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBW_TRMINATE_AWADDR_ERR 0x40082E0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBW_TRMINATE_ARADDR_ERR 0x40082E4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_BRESP 0x40082E8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_RRESP 0x40082EC + +#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXLEN 0x40082F0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXSIZE 0x40082F4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_0 0x4008300 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_1 0x4008304 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_2 0x4008308 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_3 0x400830C + +#define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_4 0x4008310 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_5 0x4008314 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_6 0x4008318 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_7 0x400831C + +#define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_CBU_WR_CNT 0x4008320 + +#define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_CBU_WR_CNT 0x4008324 + +#define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_CBU_RD_CNT 0x4008328 + +#define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_CBU_RD_CNT 0x400832C + +#define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_LBU_WR_CNT 0x4008330 + +#define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_LBU_WR_CNT 0x4008334 + +#define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_LBU_RD_CNT 0x4008338 + +#define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT 0x400833C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_OVR 0x4008350 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_OVR_EN 0x4008354 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_OVR 0x4008358 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_OVR_EN 0x400835C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR 0x4008360 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR_EN 0x4008364 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR 0x4008368 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR_EN 0x400836C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AXCACHE_OVR 0x4008370 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_LOCK_OVR 0x4008374 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_PROT_OVR 0x4008378 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_MAX_OUTSTANDING 0x400837C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN 0x4008380 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORCE_RSP_OK 0x4008384 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_NO_WR_INFLIGHT 0x400838C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_SEI_INTR_ID 0x4008390 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_ARUSER_OVR 0x4008400 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_ARUSER_OVR_EN 0x4008404 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_AWUSER_OVR 0x4008408 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_AWUSER_OVR_EN 0x400840C + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_AXCACHE_OVR 0x4008420 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_LOCK_OVR 0x4008424 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_PROT_OVR 0x4008428 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_MAX_OUTSTANDING 0x400842C + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN 0x4008430 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_FORCE_RSP_OK 0x4008434 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_NO_WR_INFLIGHT 0x400843C + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_SEI_INTR_ID 0x4008440 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0 0x4008500 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_1 0x4008504 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_2 0x4008508 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_3 0x400850C + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_4 0x4008510 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_5 0x4008514 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_6 0x4008518 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_7 0x400851C + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_0 0x4008520 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_1 0x4008524 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_2 0x4008528 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_3 0x400852C + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_4 0x4008530 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_5 0x4008534 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_6 0x4008538 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_7 0x400853C + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_0 0x4008540 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_1 0x4008544 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_2 0x4008548 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_3 0x400854C + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_4 0x4008550 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_5 0x4008554 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_6 0x4008558 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_7 0x400855C + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_0 0x4008560 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_1 0x4008564 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_2 0x4008568 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_3 0x400856C + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_4 0x4008570 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_5 0x4008574 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_6 0x4008578 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_7 0x400857C + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_0 0x4008580 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_1 0x4008584 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_2 0x4008588 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_3 0x400858C + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_4 0x4008590 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_5 0x4008594 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_6 0x4008598 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_7 0x400859C + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x40085A0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x40085A4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x40085A8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x40085AC + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x40085B0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x40085B4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x40085B8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x40085BC + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x40085C0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x40085C4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x40085C8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x40085CC + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x40085D0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x40085D4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x40085D8 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x40085DC + +#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x40085E0 + +#define mmDCORE0_TPC0_QM_ARC_AUX_NIC_Q_VLD_ENTRY_MASK 0x40085E4 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_DROP_EN 0x4008620 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_WARN_MSG 0x4008624 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG 0x4008628 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWPROT 0x4008630 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWUSER 0x4008634 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWBURST 0x4008638 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWLOCK 0x400863C + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWCACHE 0x4008640 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_WRR_ARB_WEIGHT 0x4008644 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x4008648 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT 0x400864C + +#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x4008650 + +#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x4008654 + +#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_CQ_SHADOW_CI 0x4008658 + +#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI 0x400865C + +#define mmDCORE0_TPC0_QM_ARC_AUX_AUX2APB_PROT 0x4008700 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBW_FORK_WIN_EN 0x4008704 + +#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x4008708 + +#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x400870C + +#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x4008710 + +#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x4008714 + +#define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR0 0x4008718 + +#define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK0 0x400871C + +#define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR1 0x4008720 + +#define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK1 0x4008724 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR0 0x4008728 + +#define mmDCORE0_TPC0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR1 0x400872C + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x4008730 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x4008734 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x4008738 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x400873C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_WIN_EN 0x4008740 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_LSB 0x4008750 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_MSB 0x4008754 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_LSB 0x4008758 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_MSB 0x400875C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_LSB 0x4008760 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_MSB 0x4008764 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_LSB 0x4008768 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_MSB 0x400876C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_LSB 0x4008770 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_MSB 0x4008774 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_LSB 0x4008778 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_MSB 0x400877C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_LSB 0x4008780 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_MSB 0x4008784 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_LSB 0x4008788 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_MSB 0x400878C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_LSB 0x4008790 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_MSB 0x4008794 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_CBU_TERMINATE_BRESP 0x4008798 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_CBU_TERMINATE_RRESP 0x400879C + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_0 0x4008800 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_1 0x4008804 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_2 0x4008808 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_3 0x400880C + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_4 0x4008810 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_5 0x4008814 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_6 0x4008818 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_7 0x400881C + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_8 0x4008820 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_9 0x4008824 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_10 0x4008828 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_11 0x400882C + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_12 0x4008830 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_13 0x4008834 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_14 0x4008838 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_15 0x400883C + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_TRMINATE_AWADDR_ERR 0x4008840 + +#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_TRMINATE_ARADDR_ERR 0x4008844 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_TERMINATE_BRESP 0x4008848 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_TERMINATE_RRESP 0x400884C + +#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_TERMINATE_EN 0x4008850 + +#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_SECURE_REGION 0x4008854 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x4008900 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_CTL 0x4008904 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x4008908 + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR 0x400890C + +#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACC_ENGS_BUSER 0x4008910 + +#define mmDCORE0_TPC0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN 0x4008920 + +#endif /* ASIC_REG_DCORE0_TPC0_QM_ARC_AUX_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_axuser_nonsecured_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_axuser_nonsecured_regs.h new file mode 100644 index 000000000000..149b85f5f045 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_axuser_nonsecured_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_QM_AXUSER_NONSECURED_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_QM_AXUSER_NONSECURED_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_QM_AXUSER_NONSECURED + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_ASID 0x400AB80 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_MMU_BP 0x400AB84 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x400AB88 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x400AB8C + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x400AB90 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x400AB94 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_QOS 0x400AB98 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_RSVD 0x400AB9C + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x400ABA0 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_CORE 0x400ABA4 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_E2E_COORD 0x400ABA8 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x400ABB0 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x400ABB4 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x400ABB8 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x400ABBC + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_LB_COORD 0x400ABC0 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_LB_LOCK 0x400ABC4 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_LB_RSVD 0x400ABC8 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_LB_OVRD 0x400ABCC + +#endif /* ASIC_REG_DCORE0_TPC0_QM_AXUSER_NONSECURED_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_cgm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_cgm_regs.h new file mode 100644 index 000000000000..d4aad1875ad6 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_cgm_regs.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_QM_CGM_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_QM_CGM_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_QM_CGM + * (Prototype: QMAN_CGM) + ***************************************** + */ + +#define mmDCORE0_TPC0_QM_CGM_CFG 0x400AD80 + +#define mmDCORE0_TPC0_QM_CGM_STS 0x400AD84 + +#define mmDCORE0_TPC0_QM_CGM_CFG1 0x400AD88 + +#endif /* ASIC_REG_DCORE0_TPC0_QM_CGM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_regs.h new file mode 100644 index 000000000000..cca8683cbca1 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_regs.h @@ -0,0 +1,1057 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_QM_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_QM_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_QM + * (Prototype: QMAN) + ***************************************** + */ + +#define mmDCORE0_TPC0_QM_GLBL_CFG0 0x400A000 + +#define mmDCORE0_TPC0_QM_GLBL_CFG1 0x400A004 + +#define mmDCORE0_TPC0_QM_GLBL_CFG2 0x400A008 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_CFG 0x400A00C + +#define mmDCORE0_TPC0_QM_GLBL_ERR_CFG1 0x400A010 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_ARC_HALT_EN 0x400A014 + +#define mmDCORE0_TPC0_QM_GLBL_AXCACHE 0x400A018 + +#define mmDCORE0_TPC0_QM_GLBL_STS0 0x400A01C + +#define mmDCORE0_TPC0_QM_GLBL_STS1 0x400A020 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_STS_0 0x400A024 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_STS_1 0x400A028 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_STS_2 0x400A02C + +#define mmDCORE0_TPC0_QM_GLBL_ERR_STS_3 0x400A030 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_STS_4 0x400A034 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_0 0x400A038 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_1 0x400A03C + +#define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_2 0x400A040 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_3 0x400A044 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_4 0x400A048 + +#define mmDCORE0_TPC0_QM_GLBL_PROT 0x400A04C + +#define mmDCORE0_TPC0_QM_PQ_BASE_LO_0 0x400A050 + +#define mmDCORE0_TPC0_QM_PQ_BASE_LO_1 0x400A054 + +#define mmDCORE0_TPC0_QM_PQ_BASE_LO_2 0x400A058 + +#define mmDCORE0_TPC0_QM_PQ_BASE_LO_3 0x400A05C + +#define mmDCORE0_TPC0_QM_PQ_BASE_HI_0 0x400A060 + +#define mmDCORE0_TPC0_QM_PQ_BASE_HI_1 0x400A064 + +#define mmDCORE0_TPC0_QM_PQ_BASE_HI_2 0x400A068 + +#define mmDCORE0_TPC0_QM_PQ_BASE_HI_3 0x400A06C + +#define mmDCORE0_TPC0_QM_PQ_SIZE_0 0x400A070 + +#define mmDCORE0_TPC0_QM_PQ_SIZE_1 0x400A074 + +#define mmDCORE0_TPC0_QM_PQ_SIZE_2 0x400A078 + +#define mmDCORE0_TPC0_QM_PQ_SIZE_3 0x400A07C + +#define mmDCORE0_TPC0_QM_PQ_PI_0 0x400A080 + +#define mmDCORE0_TPC0_QM_PQ_PI_1 0x400A084 + +#define mmDCORE0_TPC0_QM_PQ_PI_2 0x400A088 + +#define mmDCORE0_TPC0_QM_PQ_PI_3 0x400A08C + +#define mmDCORE0_TPC0_QM_PQ_CI_0 0x400A090 + +#define mmDCORE0_TPC0_QM_PQ_CI_1 0x400A094 + +#define mmDCORE0_TPC0_QM_PQ_CI_2 0x400A098 + +#define mmDCORE0_TPC0_QM_PQ_CI_3 0x400A09C + +#define mmDCORE0_TPC0_QM_PQ_CFG0_0 0x400A0A0 + +#define mmDCORE0_TPC0_QM_PQ_CFG0_1 0x400A0A4 + +#define mmDCORE0_TPC0_QM_PQ_CFG0_2 0x400A0A8 + +#define mmDCORE0_TPC0_QM_PQ_CFG0_3 0x400A0AC + +#define mmDCORE0_TPC0_QM_PQ_CFG1_0 0x400A0B0 + +#define mmDCORE0_TPC0_QM_PQ_CFG1_1 0x400A0B4 + +#define mmDCORE0_TPC0_QM_PQ_CFG1_2 0x400A0B8 + +#define mmDCORE0_TPC0_QM_PQ_CFG1_3 0x400A0BC + +#define mmDCORE0_TPC0_QM_PQ_STS0_0 0x400A0C0 + +#define mmDCORE0_TPC0_QM_PQ_STS0_1 0x400A0C4 + +#define mmDCORE0_TPC0_QM_PQ_STS0_2 0x400A0C8 + +#define mmDCORE0_TPC0_QM_PQ_STS0_3 0x400A0CC + +#define mmDCORE0_TPC0_QM_PQ_STS1_0 0x400A0D0 + +#define mmDCORE0_TPC0_QM_PQ_STS1_1 0x400A0D4 + +#define mmDCORE0_TPC0_QM_PQ_STS1_2 0x400A0D8 + +#define mmDCORE0_TPC0_QM_PQ_STS1_3 0x400A0DC + +#define mmDCORE0_TPC0_QM_CQ_CFG0_0 0x400A0E0 + +#define mmDCORE0_TPC0_QM_CQ_CFG0_1 0x400A0E4 + +#define mmDCORE0_TPC0_QM_CQ_CFG0_2 0x400A0E8 + +#define mmDCORE0_TPC0_QM_CQ_CFG0_3 0x400A0EC + +#define mmDCORE0_TPC0_QM_CQ_CFG0_4 0x400A0F0 + +#define mmDCORE0_TPC0_QM_CQ_STS0_0 0x400A0F4 + +#define mmDCORE0_TPC0_QM_CQ_STS0_1 0x400A0F8 + +#define mmDCORE0_TPC0_QM_CQ_STS0_2 0x400A0FC + +#define mmDCORE0_TPC0_QM_CQ_STS0_3 0x400A100 + +#define mmDCORE0_TPC0_QM_CQ_STS0_4 0x400A104 + +#define mmDCORE0_TPC0_QM_CQ_CFG1_0 0x400A108 + +#define mmDCORE0_TPC0_QM_CQ_CFG1_1 0x400A10C + +#define mmDCORE0_TPC0_QM_CQ_CFG1_2 0x400A110 + +#define mmDCORE0_TPC0_QM_CQ_CFG1_3 0x400A114 + +#define mmDCORE0_TPC0_QM_CQ_CFG1_4 0x400A118 + +#define mmDCORE0_TPC0_QM_CQ_STS1_0 0x400A11C + +#define mmDCORE0_TPC0_QM_CQ_STS1_1 0x400A120 + +#define mmDCORE0_TPC0_QM_CQ_STS1_2 0x400A124 + +#define mmDCORE0_TPC0_QM_CQ_STS1_3 0x400A128 + +#define mmDCORE0_TPC0_QM_CQ_STS1_4 0x400A12C + +#define mmDCORE0_TPC0_QM_CQ_PTR_LO_0 0x400A150 + +#define mmDCORE0_TPC0_QM_CQ_PTR_HI_0 0x400A154 + +#define mmDCORE0_TPC0_QM_CQ_TSIZE_0 0x400A158 + +#define mmDCORE0_TPC0_QM_CQ_CTL_0 0x400A15C + +#define mmDCORE0_TPC0_QM_CQ_PTR_LO_1 0x400A160 + +#define mmDCORE0_TPC0_QM_CQ_PTR_HI_1 0x400A164 + +#define mmDCORE0_TPC0_QM_CQ_TSIZE_1 0x400A168 + +#define mmDCORE0_TPC0_QM_CQ_CTL_1 0x400A16C + +#define mmDCORE0_TPC0_QM_CQ_PTR_LO_2 0x400A170 + +#define mmDCORE0_TPC0_QM_CQ_PTR_HI_2 0x400A174 + +#define mmDCORE0_TPC0_QM_CQ_TSIZE_2 0x400A178 + +#define mmDCORE0_TPC0_QM_CQ_CTL_2 0x400A17C + +#define mmDCORE0_TPC0_QM_CQ_PTR_LO_3 0x400A180 + +#define mmDCORE0_TPC0_QM_CQ_PTR_HI_3 0x400A184 + +#define mmDCORE0_TPC0_QM_CQ_TSIZE_3 0x400A188 + +#define mmDCORE0_TPC0_QM_CQ_CTL_3 0x400A18C + +#define mmDCORE0_TPC0_QM_CQ_PTR_LO_4 0x400A190 + +#define mmDCORE0_TPC0_QM_CQ_PTR_HI_4 0x400A194 + +#define mmDCORE0_TPC0_QM_CQ_TSIZE_4 0x400A198 + +#define mmDCORE0_TPC0_QM_CQ_CTL_4 0x400A19C + +#define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_0 0x400A1A0 + +#define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_1 0x400A1A4 + +#define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_2 0x400A1A8 + +#define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_3 0x400A1AC + +#define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_4 0x400A1B0 + +#define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_0 0x400A1B4 + +#define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_1 0x400A1B8 + +#define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_2 0x400A1BC + +#define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_3 0x400A1C0 + +#define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_4 0x400A1C4 + +#define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_0 0x400A1C8 + +#define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_1 0x400A1CC + +#define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_2 0x400A1D0 + +#define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_3 0x400A1D4 + +#define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_4 0x400A1D8 + +#define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_0 0x400A1DC + +#define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_1 0x400A1E0 + +#define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_2 0x400A1E4 + +#define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_3 0x400A1E8 + +#define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_4 0x400A1EC + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_0 0x400A1F0 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_1 0x400A1F4 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_2 0x400A1F8 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_3 0x400A1FC + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_4 0x400A200 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_0 0x400A204 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_1 0x400A208 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_2 0x400A20C + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_3 0x400A210 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_4 0x400A214 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_0 0x400A218 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_1 0x400A21C + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_2 0x400A220 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_3 0x400A224 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_4 0x400A228 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_0 0x400A22C + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_1 0x400A230 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_2 0x400A234 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_3 0x400A238 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_4 0x400A23C + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_0 0x400A240 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_1 0x400A244 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_2 0x400A248 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_3 0x400A24C + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_4 0x400A250 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_0 0x400A254 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_1 0x400A258 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_2 0x400A25C + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_3 0x400A260 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_4 0x400A264 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_0 0x400A268 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_1 0x400A26C + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_2 0x400A270 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_3 0x400A274 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_4 0x400A278 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_0 0x400A27C + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_1 0x400A280 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_2 0x400A284 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_3 0x400A288 + +#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_4 0x400A28C + +#define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_0 0x400A290 + +#define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_1 0x400A294 + +#define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_2 0x400A298 + +#define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_3 0x400A29C + +#define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_4 0x400A2A0 + +#define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_0 0x400A2A4 + +#define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_1 0x400A2A8 + +#define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_2 0x400A2AC + +#define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_3 0x400A2B0 + +#define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_4 0x400A2B4 + +#define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_0 0x400A2B8 + +#define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_1 0x400A2BC + +#define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_2 0x400A2C0 + +#define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_3 0x400A2C4 + +#define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_4 0x400A2C8 + +#define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_0 0x400A2CC + +#define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_1 0x400A2D0 + +#define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_2 0x400A2D4 + +#define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_3 0x400A2D8 + +#define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_4 0x400A2DC + +#define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_0 0x400A2E0 + +#define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_1 0x400A2E4 + +#define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_2 0x400A2E8 + +#define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_3 0x400A2EC + +#define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_4 0x400A2F0 + +#define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_0 0x400A2F4 + +#define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_1 0x400A2F8 + +#define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_2 0x400A2FC + +#define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_3 0x400A300 + +#define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_4 0x400A304 + +#define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_0 0x400A308 + +#define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_1 0x400A30C + +#define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_2 0x400A310 + +#define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_3 0x400A314 + +#define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_4 0x400A318 + +#define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_0 0x400A31C + +#define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_1 0x400A320 + +#define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_2 0x400A324 + +#define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_3 0x400A328 + +#define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_4 0x400A32C + +#define mmDCORE0_TPC0_QM_CP_BARRIER_CFG 0x400A330 + +#define mmDCORE0_TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0x400A334 + +#define mmDCORE0_TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET 0x400A338 + +#define mmDCORE0_TPC0_QM_CP_LDMA_TSIZE_OFFSET 0x400A33C + +#define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_0 0x400A340 + +#define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_1 0x400A344 + +#define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_2 0x400A348 + +#define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_3 0x400A34C + +#define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_4 0x400A350 + +#define mmDCORE0_TPC0_QM_CP_STS_0 0x400A368 + +#define mmDCORE0_TPC0_QM_CP_STS_1 0x400A36C + +#define mmDCORE0_TPC0_QM_CP_STS_2 0x400A370 + +#define mmDCORE0_TPC0_QM_CP_STS_3 0x400A374 + +#define mmDCORE0_TPC0_QM_CP_STS_4 0x400A378 + +#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_0 0x400A37C + +#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_1 0x400A380 + +#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_2 0x400A384 + +#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_3 0x400A388 + +#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_4 0x400A38C + +#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_0 0x400A390 + +#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_1 0x400A394 + +#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_2 0x400A398 + +#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_3 0x400A39C + +#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_4 0x400A3A0 + +#define mmDCORE0_TPC0_QM_CP_PRED_0 0x400A3A4 + +#define mmDCORE0_TPC0_QM_CP_PRED_1 0x400A3A8 + +#define mmDCORE0_TPC0_QM_CP_PRED_2 0x400A3AC + +#define mmDCORE0_TPC0_QM_CP_PRED_3 0x400A3B0 + +#define mmDCORE0_TPC0_QM_CP_PRED_4 0x400A3B4 + +#define mmDCORE0_TPC0_QM_CP_PRED_UPEN_0 0x400A3B8 + +#define mmDCORE0_TPC0_QM_CP_PRED_UPEN_1 0x400A3BC + +#define mmDCORE0_TPC0_QM_CP_PRED_UPEN_2 0x400A3C0 + +#define mmDCORE0_TPC0_QM_CP_PRED_UPEN_3 0x400A3C4 + +#define mmDCORE0_TPC0_QM_CP_PRED_UPEN_4 0x400A3C8 + +#define mmDCORE0_TPC0_QM_CP_DBG_0_0 0x400A3CC + +#define mmDCORE0_TPC0_QM_CP_DBG_0_1 0x400A3D0 + +#define mmDCORE0_TPC0_QM_CP_DBG_0_2 0x400A3D4 + +#define mmDCORE0_TPC0_QM_CP_DBG_0_3 0x400A3D8 + +#define mmDCORE0_TPC0_QM_CP_DBG_0_4 0x400A3DC + +#define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_0 0x400A3E0 + +#define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_1 0x400A3E4 + +#define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_2 0x400A3E8 + +#define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_3 0x400A3EC + +#define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_4 0x400A3F0 + +#define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_0 0x400A3F4 + +#define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_1 0x400A3F8 + +#define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_2 0x400A3FC + +#define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_3 0x400A400 + +#define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_4 0x400A404 + +#define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_0 0x400A408 + +#define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_1 0x400A40C + +#define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_2 0x400A410 + +#define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_3 0x400A414 + +#define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_4 0x400A418 + +#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_LO_0 0x400A41C + +#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_LO_1 0x400A420 + +#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_LO_2 0x400A424 + +#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_LO_3 0x400A428 + +#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_HI_0 0x400A42C + +#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_HI_1 0x400A430 + +#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_HI_2 0x400A434 + +#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_HI_3 0x400A438 + +#define mmDCORE0_TPC0_QM_PQC_SIZE_0 0x400A43C + +#define mmDCORE0_TPC0_QM_PQC_SIZE_1 0x400A440 + +#define mmDCORE0_TPC0_QM_PQC_SIZE_2 0x400A444 + +#define mmDCORE0_TPC0_QM_PQC_SIZE_3 0x400A448 + +#define mmDCORE0_TPC0_QM_PQC_PI_0 0x400A44C + +#define mmDCORE0_TPC0_QM_PQC_PI_1 0x400A450 + +#define mmDCORE0_TPC0_QM_PQC_PI_2 0x400A454 + +#define mmDCORE0_TPC0_QM_PQC_PI_3 0x400A458 + +#define mmDCORE0_TPC0_QM_PQC_LBW_WDATA_0 0x400A45C + +#define mmDCORE0_TPC0_QM_PQC_LBW_WDATA_1 0x400A460 + +#define mmDCORE0_TPC0_QM_PQC_LBW_WDATA_2 0x400A464 + +#define mmDCORE0_TPC0_QM_PQC_LBW_WDATA_3 0x400A468 + +#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_LO_0 0x400A46C + +#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_LO_1 0x400A470 + +#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_LO_2 0x400A474 + +#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_LO_3 0x400A478 + +#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_HI_0 0x400A47C + +#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_HI_1 0x400A480 + +#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_HI_2 0x400A484 + +#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_HI_3 0x400A488 + +#define mmDCORE0_TPC0_QM_PQC_CFG 0x400A48C + +#define mmDCORE0_TPC0_QM_PQC_SECURE_PUSH_IND 0x400A490 + +#define mmDCORE0_TPC0_QM_ARB_MASK 0x400A4A0 + +#define mmDCORE0_TPC0_QM_ARB_CFG_0 0x400A4A4 + +#define mmDCORE0_TPC0_QM_ARB_CHOICE_Q_PUSH 0x400A4A8 + +#define mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_0 0x400A4AC + +#define mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_1 0x400A4B0 + +#define mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_2 0x400A4B4 + +#define mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_3 0x400A4B8 + +#define mmDCORE0_TPC0_QM_ARB_CFG_1 0x400A4BC + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_0 0x400A4C0 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_1 0x400A4C4 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_2 0x400A4C8 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_3 0x400A4CC + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_4 0x400A4D0 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_5 0x400A4D4 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_6 0x400A4D8 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_7 0x400A4DC + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_8 0x400A4E0 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_9 0x400A4E4 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_10 0x400A4E8 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_11 0x400A4EC + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_12 0x400A4F0 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_13 0x400A4F4 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_14 0x400A4F8 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_15 0x400A4FC + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_16 0x400A500 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_17 0x400A504 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_18 0x400A508 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_19 0x400A50C + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_20 0x400A510 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_21 0x400A514 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_22 0x400A518 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_23 0x400A51C + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_24 0x400A520 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_25 0x400A524 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_26 0x400A528 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_27 0x400A52C + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_28 0x400A530 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_29 0x400A534 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_30 0x400A538 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_31 0x400A53C + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_32 0x400A540 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_33 0x400A544 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_34 0x400A548 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_35 0x400A54C + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_36 0x400A550 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_37 0x400A554 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_38 0x400A558 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_39 0x400A55C + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_40 0x400A560 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_41 0x400A564 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_42 0x400A568 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_43 0x400A56C + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_44 0x400A570 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_45 0x400A574 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_46 0x400A578 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_47 0x400A57C + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_48 0x400A580 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_49 0x400A584 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_50 0x400A588 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_51 0x400A58C + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_52 0x400A590 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_53 0x400A594 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_54 0x400A598 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_55 0x400A59C + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_56 0x400A5A0 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_57 0x400A5A4 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_58 0x400A5A8 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_59 0x400A5AC + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_60 0x400A5B0 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_61 0x400A5B4 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_62 0x400A5B8 + +#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_63 0x400A5BC + +#define mmDCORE0_TPC0_QM_ARB_MST_CRED_INC 0x400A5E0 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_0 0x400A5E4 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_1 0x400A5E8 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_2 0x400A5EC + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_3 0x400A5F0 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_4 0x400A5F4 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_5 0x400A5F8 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_6 0x400A5FC + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_7 0x400A600 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_8 0x400A604 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_9 0x400A608 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_10 0x400A60C + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_11 0x400A610 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_12 0x400A614 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_13 0x400A618 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_14 0x400A61C + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_15 0x400A620 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_16 0x400A624 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_17 0x400A628 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_18 0x400A62C + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_19 0x400A630 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_20 0x400A634 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_21 0x400A638 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_22 0x400A63C + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_23 0x400A640 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_24 0x400A644 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_25 0x400A648 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_26 0x400A64C + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_27 0x400A650 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_28 0x400A654 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_29 0x400A658 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_30 0x400A65C + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_31 0x400A660 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_32 0x400A664 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_33 0x400A668 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_34 0x400A66C + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_35 0x400A670 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_36 0x400A674 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_37 0x400A678 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_38 0x400A67C + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_39 0x400A680 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_40 0x400A684 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_41 0x400A688 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_42 0x400A68C + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_43 0x400A690 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_44 0x400A694 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_45 0x400A698 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_46 0x400A69C + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_47 0x400A6A0 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_48 0x400A6A4 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_49 0x400A6A8 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_50 0x400A6AC + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_51 0x400A6B0 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_52 0x400A6B4 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_53 0x400A6B8 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_54 0x400A6BC + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_55 0x400A6C0 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_56 0x400A6C4 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_57 0x400A6C8 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_58 0x400A6CC + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_59 0x400A6D0 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_60 0x400A6D4 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_61 0x400A6D8 + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_62 0x400A6DC + +#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_63 0x400A6E0 + +#define mmDCORE0_TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x400A704 + +#define mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN 0x400A708 + +#define mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN_1 0x400A70C + +#define mmDCORE0_TPC0_QM_ARB_SLV_CHOICE_WDT 0x400A710 + +#define mmDCORE0_TPC0_QM_ARB_SLV_ID 0x400A714 + +#define mmDCORE0_TPC0_QM_ARB_MST_QUIET_PER 0x400A718 + +#define mmDCORE0_TPC0_QM_ARB_MSG_MAX_INFLIGHT 0x400A744 + +#define mmDCORE0_TPC0_QM_ARB_BASE_LO 0x400A754 + +#define mmDCORE0_TPC0_QM_ARB_BASE_HI 0x400A758 + +#define mmDCORE0_TPC0_QM_ARB_STATE_STS 0x400A780 + +#define mmDCORE0_TPC0_QM_ARB_CHOICE_FULLNESS_STS 0x400A784 + +#define mmDCORE0_TPC0_QM_ARB_MSG_STS 0x400A788 + +#define mmDCORE0_TPC0_QM_ARB_SLV_CHOICE_Q_HEAD 0x400A78C + +#define mmDCORE0_TPC0_QM_ARB_ERR_CAUSE 0x400A79C + +#define mmDCORE0_TPC0_QM_ARB_ERR_MSG_EN 0x400A7A0 + +#define mmDCORE0_TPC0_QM_ARB_ERR_STS_DRP 0x400A7A8 + +#define mmDCORE0_TPC0_QM_ARB_MST_CRED_STS 0x400A7B0 + +#define mmDCORE0_TPC0_QM_ARB_MST_CRED_STS_1 0x400A7B4 + +#define mmDCORE0_TPC0_QM_CSMR_STRICT_PRIO_CFG 0x400A7FC + +#define mmDCORE0_TPC0_QM_ARC_CQ_CFG0 0x400A800 + +#define mmDCORE0_TPC0_QM_ARC_CQ_CFG1 0x400A804 + +#define mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO 0x400A808 + +#define mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI 0x400A80C + +#define mmDCORE0_TPC0_QM_ARC_CQ_TSIZE 0x400A810 + +#define mmDCORE0_TPC0_QM_ARC_CQ_CTL 0x400A814 + +#define mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_STS 0x400A81C + +#define mmDCORE0_TPC0_QM_ARC_CQ_STS0 0x400A820 + +#define mmDCORE0_TPC0_QM_ARC_CQ_STS1 0x400A824 + +#define mmDCORE0_TPC0_QM_ARC_CQ_TSIZE_STS 0x400A828 + +#define mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO_STS 0x400A82C + +#define mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI_STS 0x400A830 + +#define mmDCORE0_TPC0_QM_CP_WR_ARC_ADDR_HI 0x400A834 + +#define mmDCORE0_TPC0_QM_CP_WR_ARC_ADDR_LO 0x400A838 + +#define mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_MSG_BASE_HI 0x400A83C + +#define mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_MSG_BASE_LO 0x400A840 + +#define mmDCORE0_TPC0_QM_ARC_CQ_CTL_MSG_BASE_HI 0x400A844 + +#define mmDCORE0_TPC0_QM_ARC_CQ_CTL_MSG_BASE_LO 0x400A848 + +#define mmDCORE0_TPC0_QM_CQ_IFIFO_MSG_BASE_HI 0x400A84C + +#define mmDCORE0_TPC0_QM_CQ_IFIFO_MSG_BASE_LO 0x400A850 + +#define mmDCORE0_TPC0_QM_CQ_CTL_MSG_BASE_HI 0x400A854 + +#define mmDCORE0_TPC0_QM_CQ_CTL_MSG_BASE_LO 0x400A858 + +#define mmDCORE0_TPC0_QM_ADDR_OVRD 0x400A85C + +#define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_0 0x400A860 + +#define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_1 0x400A864 + +#define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_2 0x400A868 + +#define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_3 0x400A86C + +#define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_4 0x400A870 + +#define mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_CI 0x400A874 + +#define mmDCORE0_TPC0_QM_CQ_CTL_CI_0 0x400A878 + +#define mmDCORE0_TPC0_QM_CQ_CTL_CI_1 0x400A87C + +#define mmDCORE0_TPC0_QM_CQ_CTL_CI_2 0x400A880 + +#define mmDCORE0_TPC0_QM_CQ_CTL_CI_3 0x400A884 + +#define mmDCORE0_TPC0_QM_CQ_CTL_CI_4 0x400A888 + +#define mmDCORE0_TPC0_QM_ARC_CQ_CTL_CI 0x400A88C + +#define mmDCORE0_TPC0_QM_CP_CFG 0x400A890 + +#define mmDCORE0_TPC0_QM_CP_EXT_SWITCH 0x400A894 + +#define mmDCORE0_TPC0_QM_CP_SWITCH_WD_SET 0x400A898 + +#define mmDCORE0_TPC0_QM_CP_SWITCH_WD 0x400A89C + +#define mmDCORE0_TPC0_QM_ARC_LB_ADDR_BASE_LO 0x400A8A4 + +#define mmDCORE0_TPC0_QM_ARC_LB_ADDR_BASE_HI 0x400A8A8 + +#define mmDCORE0_TPC0_QM_ENGINE_BASE_ADDR_HI 0x400A8AC + +#define mmDCORE0_TPC0_QM_ENGINE_BASE_ADDR_LO 0x400A8B0 + +#define mmDCORE0_TPC0_QM_ENGINE_ADDR_RANGE_SIZE 0x400A8B4 + +#define mmDCORE0_TPC0_QM_QM_ARC_AUX_BASE_ADDR_HI 0x400A8B8 + +#define mmDCORE0_TPC0_QM_QM_ARC_AUX_BASE_ADDR_LO 0x400A8BC + +#define mmDCORE0_TPC0_QM_QM_BASE_ADDR_HI 0x400A8C0 + +#define mmDCORE0_TPC0_QM_QM_BASE_ADDR_LO 0x400A8C4 + +#define mmDCORE0_TPC0_QM_ARC_PQC_SECURE_PUSH_IND 0x400A8C8 + +#define mmDCORE0_TPC0_QM_PQC_STS_0_0 0x400A8D0 + +#define mmDCORE0_TPC0_QM_PQC_STS_0_1 0x400A8D4 + +#define mmDCORE0_TPC0_QM_PQC_STS_0_2 0x400A8D8 + +#define mmDCORE0_TPC0_QM_PQC_STS_0_3 0x400A8DC + +#define mmDCORE0_TPC0_QM_PQC_STS_1_0 0x400A8E0 + +#define mmDCORE0_TPC0_QM_PQC_STS_1_1 0x400A8E4 + +#define mmDCORE0_TPC0_QM_PQC_STS_1_2 0x400A8E8 + +#define mmDCORE0_TPC0_QM_PQC_STS_1_3 0x400A8EC + +#define mmDCORE0_TPC0_QM_SEI_STATUS 0x400A8F0 + +#define mmDCORE0_TPC0_QM_SEI_MASK 0x400A8F4 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_ADDR_LO 0x400AD00 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_ADDR_HI 0x400AD04 + +#define mmDCORE0_TPC0_QM_GLBL_ERR_WDATA 0x400AD08 + +#define mmDCORE0_TPC0_QM_L2H_MASK_LO 0x400AD14 + +#define mmDCORE0_TPC0_QM_L2H_MASK_HI 0x400AD18 + +#define mmDCORE0_TPC0_QM_L2H_CMPR_LO 0x400AD1C + +#define mmDCORE0_TPC0_QM_L2H_CMPR_HI 0x400AD20 + +#define mmDCORE0_TPC0_QM_LOCAL_RANGE_BASE 0x400AD24 + +#define mmDCORE0_TPC0_QM_LOCAL_RANGE_SIZE 0x400AD28 + +#define mmDCORE0_TPC0_QM_HBW_RD_RATE_LIM_CFG_1 0x400AD30 + +#define mmDCORE0_TPC0_QM_LBW_WR_RATE_LIM_CFG_0 0x400AD34 + +#define mmDCORE0_TPC0_QM_LBW_WR_RATE_LIM_CFG_1 0x400AD38 + +#define mmDCORE0_TPC0_QM_HBW_RD_RATE_LIM_CFG_0 0x400AD3C + +#define mmDCORE0_TPC0_QM_IND_GW_APB_CFG 0x400AD40 + +#define mmDCORE0_TPC0_QM_IND_GW_APB_WDATA 0x400AD44 + +#define mmDCORE0_TPC0_QM_IND_GW_APB_RDATA 0x400AD48 + +#define mmDCORE0_TPC0_QM_IND_GW_APB_STATUS 0x400AD4C + +#define mmDCORE0_TPC0_QM_PERF_CNT_FREE_LO 0x400AD60 + +#define mmDCORE0_TPC0_QM_PERF_CNT_FREE_HI 0x400AD64 + +#define mmDCORE0_TPC0_QM_PERF_CNT_IDLE_LO 0x400AD68 + +#define mmDCORE0_TPC0_QM_PERF_CNT_IDLE_HI 0x400AD6C + +#define mmDCORE0_TPC0_QM_PERF_CNT_CFG 0x400AD70 + +#endif /* ASIC_REG_DCORE0_TPC0_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h new file mode 100644 index 000000000000..e68667cc795a --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_REGS_H_ +#define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_REGS_H_ + +/* + ***************************************** + * DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_ASID 0x41E3C00 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_MMU_BP 0x41E3C04 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_STRONG_ORDER 0x41E3C08 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_NO_SNOOP 0x41E3C0C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_WR_REDUCTION 0x41E3C10 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RD_ATOMIC 0x41E3C14 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_QOS 0x41E3C18 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RSVD 0x41E3C1C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_EMEM_CPAGE 0x41E3C20 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_CORE 0x41E3C24 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_E2E_COORD 0x41E3C28 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_WR_OVRD_LO 0x41E3C30 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_WR_OVRD_HI 0x41E3C34 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RD_OVRD_LO 0x41E3C38 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RD_OVRD_HI 0x41E3C3C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_COORD 0x41E3C40 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_LOCK 0x41E3C44 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_RSVD 0x41E3C48 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_OVRD 0x41E3C4C + +#endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h new file mode 100644 index 000000000000..f7ffdcbd1a76 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_REGS_H_ +#define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_REGS_H_ + +/* + ***************************************** + * DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_ASID 0x41E3B00 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_MMU_BP 0x41E3B04 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_STRONG_ORDER 0x41E3B08 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_NO_SNOOP 0x41E3B0C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_WR_REDUCTION 0x41E3B10 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_RD_ATOMIC 0x41E3B14 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_QOS 0x41E3B18 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_RSVD 0x41E3B1C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_EMEM_CPAGE 0x41E3B20 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_CORE 0x41E3B24 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_E2E_COORD 0x41E3B28 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_WR_OVRD_LO 0x41E3B30 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_WR_OVRD_HI 0x41E3B34 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_RD_OVRD_LO 0x41E3B38 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_RD_OVRD_HI 0x41E3B3C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_LB_COORD 0x41E3B40 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_LB_LOCK 0x41E3B44 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_LB_RSVD 0x41E3B48 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_LB_OVRD 0x41E3B4C + +#endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h new file mode 100644 index 000000000000..4c1bb5306cba --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_REGS_H_ +#define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_REGS_H_ + +/* + ***************************************** + * DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_ASID 0x41E3900 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_MMU_BP 0x41E3904 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_STRONG_ORDER 0x41E3908 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_NO_SNOOP 0x41E390C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_WR_REDUCTION 0x41E3910 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_RD_ATOMIC 0x41E3914 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_QOS 0x41E3918 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_RSVD 0x41E391C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_EMEM_CPAGE 0x41E3920 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_CORE 0x41E3924 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_E2E_COORD 0x41E3928 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_WR_OVRD_LO 0x41E3930 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_WR_OVRD_HI 0x41E3934 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_RD_OVRD_LO 0x41E3938 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_RD_OVRD_HI 0x41E393C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_LB_COORD 0x41E3940 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_LB_LOCK 0x41E3944 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_LB_RSVD 0x41E3948 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_LB_OVRD 0x41E394C + +#endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h new file mode 100644 index 000000000000..e413905ffe25 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_REGS_H_ +#define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_REGS_H_ + +/* + ***************************************** + * DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_ASID 0x41E3A00 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_MMU_BP 0x41E3A04 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_STRONG_ORDER 0x41E3A08 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_NO_SNOOP 0x41E3A0C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_WR_REDUCTION 0x41E3A10 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_RD_ATOMIC 0x41E3A14 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_QOS 0x41E3A18 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_RSVD 0x41E3A1C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_EMEM_CPAGE 0x41E3A20 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_CORE 0x41E3A24 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_E2E_COORD 0x41E3A28 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_WR_OVRD_LO 0x41E3A30 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_WR_OVRD_HI 0x41E3A34 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_RD_OVRD_LO 0x41E3A38 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_RD_OVRD_HI 0x41E3A3C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_LB_COORD 0x41E3A40 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_LB_LOCK 0x41E3A44 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_LB_RSVD 0x41E3A48 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_LB_OVRD 0x41E3A4C + +#endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h new file mode 100644 index 000000000000..bce75ac6e279 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_REGS_H_ +#define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_REGS_H_ + +/* + ***************************************** + * DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_ASID 0x41E3800 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_MMU_BP 0x41E3804 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_STRONG_ORDER 0x41E3808 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_NO_SNOOP 0x41E380C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_WR_REDUCTION 0x41E3810 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RD_ATOMIC 0x41E3814 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_QOS 0x41E3818 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RSVD 0x41E381C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_EMEM_CPAGE 0x41E3820 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_CORE 0x41E3824 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_E2E_COORD 0x41E3828 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_WR_OVRD_LO 0x41E3830 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_WR_OVRD_HI 0x41E3834 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RD_OVRD_LO 0x41E3838 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RD_OVRD_HI 0x41E383C + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_COORD 0x41E3840 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_LOCK 0x41E3844 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_RSVD 0x41E3848 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_OVRD 0x41E384C + +#endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_masks.h new file mode 100644 index 000000000000..68dd98459c86 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_masks.h @@ -0,0 +1,581 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_MASKS_H_ +#define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_MASKS_H_ + +/* + ***************************************** + * DCORE0_VDEC0_BRDG_CTRL + * (Prototype: VDEC_BRDG_CTRL) + ***************************************** + */ + +/* DCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE */ +#define DCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_MASK 0x1 + +/* DCORE0_VDEC0_BRDG_CTRL_IDLE_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT */ +#define DCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_MASK 0xFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT */ +#define DCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_MASK 0xFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_GRACEFUL */ +#define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK 0x1 +#define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_PEND_SHIFT 4 +#define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_PEND_MASK 0x10 + +/* DCORE0_VDEC0_BRDG_CTRL_IDLE_CGM_CNT */ +#define DCORE0_VDEC0_BRDG_CTRL_IDLE_CGM_CNT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_IDLE_CGM_CNT_VAL_MASK 0xFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR */ +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_HBW_SEI_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_HBW_SEI_MASK 0x1 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_HBW_SEI_SHIFT 1 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_HBW_SEI_MASK 0x2 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_HBW_SEI_SHIFT 2 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_HBW_SEI_MASK 0x4 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_HBW_SEI_SHIFT 3 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_HBW_SEI_MASK 0x8 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_LBW_SEI_SHIFT 4 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_LBW_SEI_MASK 0x10 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_LBW_SEI_SHIFT 5 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_LBW_SEI_MASK 0x20 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_LBW_SEI_SHIFT 6 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_LBW_SEI_MASK 0x40 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_LBW_SEI_SHIFT 7 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_LBW_SEI_MASK 0x80 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_VCD_LBW_SEI_SHIFT 8 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_VCD_LBW_SEI_MASK 0x100 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_L2C_LBW_SEI_SHIFT 9 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_L2C_LBW_SEI_MASK 0x200 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_NRM_LBW_SEI_SHIFT 10 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_NRM_LBW_SEI_MASK 0x400 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_ABNRM_LBW_SEI_SHIFT 11 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_ABNRM_LBW_SEI_MASK 0x800 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_SEI_SHIFT 12 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_SEI_MASK 0x1000 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_APB_SEI_SHIFT 13 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_APB_SEI_MASK 0x2000 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_TRC_APB_SEI_SHIFT 14 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_TRC_APB_SEI_MASK 0x4000 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_MSTR_IF_SEI_SHIFT 15 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_MSTR_IF_SEI_MASK 0x8000 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_AXI_SPLIT_BRESP_ERR_SEI_SHIFT 16 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_AXI_SPLIT_BRESP_ERR_SEI_MASK 0x10000 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_WR_VIOL_SEI_SHIFT 17 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_WR_VIOL_SEI_MASK 0x20000 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_RD_VIOL_SEI_SHIFT 18 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_RD_VIOL_SEI_MASK 0x40000 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_WR_VIOL_SEI_SHIFT 19 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_WR_VIOL_SEI_MASK 0x80000 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_RD_VIOL_SEI_SHIFT 20 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_RD_VIOL_SEI_MASK 0x100000 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_VCD_SPI_SHIFT 21 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_VCD_SPI_MASK 0x200000 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_L2C_SPI_SHIFT 22 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_L2C_SPI_MASK 0x400000 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_NRM_SPI_SHIFT 23 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_NRM_SPI_MASK 0x800000 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_ABNRM_SPI_SHIFT 24 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_ABNRM_SPI_MASK 0x1000000 + +/* DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE */ +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLEN_GT_31_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLEN_GT_31_MASK 0x1 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_SHIFT 1 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_MASK 0x2 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWBURST_VIOL_SHIFT 2 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWBURST_VIOL_MASK 0x4 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWADDR_SIZE_ALIGN_VIOL_SHIFT 3 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWADDR_SIZE_ALIGN_VIOL_MASK \ +0x8 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_SHIFT 4 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_MASK 0x10 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLEN_GT_31_SHIFT 5 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLEN_GT_31_MASK 0x20 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLOCK_VIOL_SHIFT 6 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLOCK_VIOL_MASK 0x40 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_SHIFT 7 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_MASK 0x80 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_SHIFT 8 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_MASK \ +0x100 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_SHIFT 9 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_MASK 0x200 + +/* DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE */ +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_READ_ACCESS_VIOL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_READ_ACCESS_VIOL_MASK 0x1 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_SHIFT 1 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_MASK 0x2 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWADDR_ALIGN_VIOL_SHIFT 2 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWADDR_ALIGN_VIOL_MASK 0x4 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_SHIFT 3 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_MASK 0x8 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLEN_VIOL_SHIFT 4 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLEN_VIOL_MASK 0x10 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_WSTRB_VIOL_SHIFT 5 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_WSTRB_VIOL_MASK 0x20 + +/* DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM */ +#define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AW_VIOL_CLR_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AW_VIOL_CLR_MASK 0x1 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AR_VIOL_CLR_SHIFT 1 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AR_VIOL_CLR_MASK 0x2 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_LBW_AW_VIOL_CLR_SHIFT 2 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_LBW_AW_VIOL_CLR_MASK 0x4 + +/* DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK_MASK_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK_MASK_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK_MASK_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK_MASK_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK_VAL_MASK 0x1 + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK_VAL_MASK 0x1 + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK_VAL_MASK 0x1 + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK_VAL_MASK 0x1 + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_AWSIZE_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_AWSIZE_MASK 0x7 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_ARSIZE_SHIFT 3 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_ARSIZE_MASK 0x38 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_LBW_LEGAL_AWSIZE_SHIFT 6 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_LBW_LEGAL_AWSIZE_MASK 0x1C0 + +/* DCORE0_VDEC0_BRDG_CTRL_ARC_MSG_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_ARC_MSG_MASK_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ARC_MSG_MASK_VAL_MASK 0x1 + +/* DCORE0_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA */ +#define DCORE0_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA_VAL_MASK 0xFF + +/* DCORE0_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA */ +#define DCORE0_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA_VAL_MASK 0xFF + +/* DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL */ +#define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L_IND_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L_IND_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H_IND_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H_IND_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L_IND_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L_IND_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H_IND_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H_IND_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_STAT_CNTR_EN */ +#define DCORE0_VDEC0_BRDG_CTRL_STAT_CNTR_EN_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_STAT_CNTR_EN_VAL_MASK 0x1 + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_INTR_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_INTR_MASK_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_INTR_MASK_VAL_MASK 0x1 + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_WR_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_WR_MASK 0x1 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_RD_SHIFT 1 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_RD_MASK 0x2 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_LBW_SHIFT 2 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_LBW_MASK 0x4 + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA */ +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_INTR_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_INTR_MASK_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_INTR_MASK_VAL_MASK 0x1 + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_WR_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_WR_MASK 0x1 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_RD_SHIFT 1 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_RD_MASK 0x2 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_LBW_SHIFT 2 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_LBW_MASK 0x4 + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA */ +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_INTR_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_INTR_MASK_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_INTR_MASK_VAL_MASK 0x1 + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_WR_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_WR_MASK 0x1 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_RD_SHIFT 1 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_RD_MASK 0x2 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_LBW_SHIFT 2 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_LBW_MASK 0x4 + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA */ +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK_VAL_MASK 0x1 + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_WR_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_WR_MASK 0x1 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_RD_SHIFT 1 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_RD_MASK 0x2 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_LBW_SHIFT 2 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_LBW_MASK 0x4 + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR */ +#define DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT_VAL_MASK 0x7 + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA */ +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID */ +#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID_ID_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID_ID_MASK 0xFF + +/* DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG */ +#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_RESP_OK_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_RESP_OK_MASK 0x1 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_WR_BUF_SHIFT 1 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_WR_BUF_MASK 0x2 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_RD_OS_SHIFT 8 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_RD_OS_MASK 0xFF00 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_WR_OS_SHIFT 16 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_WR_OS_MASK 0xFF0000 + +/* DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT */ +#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT_VAL_MASK 0x1 + +/* DCORE0_VDEC0_BRDG_CTRL_HWEVENT_MASK */ +#define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_MASK_MASK_SHIFT 1 +#define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_MASK_MASK_MASK 0x2 + +/* DCORE0_VDEC0_BRDG_CTRL_HWEVENT_CNTXT */ +#define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_CNTXT_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_CNTXT_VAL_MASK 0xFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP */ +#define DCORE0_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP_ERR_RESP_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP_ERR_RESP_MASK 0x3 + +/* DCORE0_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP */ +#define DCORE0_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP_ERR_RESP_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP_ERR_RESP_MASK 0x3 + +/* DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP */ +#define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_WR_ERR_RESP_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_WR_ERR_RESP_MASK 0x3 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_RD_ERR_RESP_SHIFT 2 +#define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_RD_ERR_RESP_MASK 0xC + +/* DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS */ +#define DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AW_STA_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AW_STA_MASK 0x1 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AR_STA_SHIFT 1 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AR_STA_MASK 0x2 + +/* DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L */ +#define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H */ +#define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L */ +#define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L_VAL_MASK 0xFFFFFFFF + +/* DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H */ +#define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H_VAL_SHIFT 0 +#define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H_VAL_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_regs.h new file mode 100644 index 000000000000..d2844307a6bf --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_regs.h @@ -0,0 +1,245 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_REGS_H_ +#define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_REGS_H_ + +/* + ***************************************** + * DCORE0_VDEC0_BRDG_CTRL + * (Prototype: VDEC_BRDG_CTRL) + ***************************************** + */ + +#define mmDCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE 0x41E3100 + +#define mmDCORE0_VDEC0_BRDG_CTRL_IDLE_MASK 0x41E3104 + +#define mmDCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT 0x41E3108 + +#define mmDCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT 0x41E310C + +#define mmDCORE0_VDEC0_BRDG_CTRL_GRACEFUL 0x41E3110 + +#define mmDCORE0_VDEC0_BRDG_CTRL_IDLE_CGM_CNT 0x41E3114 + +#define mmDCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR 0x41E3120 + +#define mmDCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE 0x41E3124 + +#define mmDCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE 0x41E3128 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM 0x41E312C + +#define mmDCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK 0x41E3130 + +#define mmDCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK 0x41E3134 + +#define mmDCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK 0x41E3138 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK 0x41E3160 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK 0x41E3170 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK 0x41E3180 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK 0x41E3190 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT 0x41E31A0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT 0x41E31A4 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT 0x41E31B0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT 0x41E31B4 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT 0x41E31C0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT 0x41E31C4 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE 0x41E31D0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ARC_MSG_MASK 0x41E3200 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA 0x41E3230 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA 0x41E3260 + +#define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL 0x41E3270 + +#define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR 0x41E3280 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L 0x41E3290 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H 0x41E3294 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L 0x41E32A0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H 0x41E32A4 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L 0x41E32B0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H 0x41E32B4 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L 0x41E32C0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H 0x41E32C4 + +#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_CNTR_EN 0x41E32D0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_INTR_MASK 0x41E3300 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK 0x41E3310 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR 0x41E3320 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR 0x41E3330 + +#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR 0x41E3334 + +#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR 0x41E3338 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR 0x41E3340 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR 0x41E3350 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA 0x41E3360 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT 0x41E3380 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L 0x41E3390 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H 0x41E3394 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT 0x41E33C0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR 0x41E33D0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA 0x41E33E0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_INTR_MASK 0x41E3400 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK 0x41E3410 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR 0x41E3420 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR 0x41E3430 + +#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR 0x41E3434 + +#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR 0x41E3438 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR 0x41E3440 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR 0x41E3450 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA 0x41E3460 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT 0x41E3480 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L 0x41E3490 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H 0x41E3494 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT 0x41E34C0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR 0x41E34D0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA 0x41E34E0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_INTR_MASK 0x41E3500 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK 0x41E3510 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR 0x41E3520 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR 0x41E3530 + +#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR 0x41E3534 + +#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR 0x41E3538 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR 0x41E3540 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR 0x41E3550 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA 0x41E3560 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT 0x41E3580 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L 0x41E3590 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H 0x41E3594 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT 0x41E35C0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR 0x41E35D0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA 0x41E35E0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK 0x41E3600 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK 0x41E3610 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR 0x41E3620 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR 0x41E3630 + +#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR 0x41E3634 + +#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR 0x41E3638 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR 0x41E3640 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR 0x41E3650 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA 0x41E3660 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT 0x41E3680 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L 0x41E3690 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H 0x41E3694 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT 0x41E36C0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR 0x41E36D0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA 0x41E36E0 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID 0x41E3700 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG 0x41E3704 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT 0x41E3708 + +#define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_MASK 0x41E370C + +#define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_CNTXT 0x41E3714 + +#define mmDCORE0_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP 0x41E3718 + +#define mmDCORE0_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP 0x41E371C + +#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP 0x41E3720 + +#define mmDCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS 0x41E3724 + +#define mmDCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L 0x41E3728 + +#define mmDCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H 0x41E372C + +#define mmDCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L 0x41E3730 + +#define mmDCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H 0x41E3734 + +#endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_ctrl_special_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_ctrl_special_regs.h new file mode 100644 index 000000000000..89b522b12998 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_ctrl_special_regs.h @@ -0,0 +1,185 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_VDEC0_CTRL_SPECIAL_REGS_H_ +#define ASIC_REG_DCORE0_VDEC0_CTRL_SPECIAL_REGS_H_ + +/* + ***************************************** + * DCORE0_VDEC0_CTRL_SPECIAL + * (Prototype: SPECIAL_REGS) + ***************************************** + */ + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_0 0x41E4E80 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_1 0x41E4E84 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_2 0x41E4E88 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_3 0x41E4E8C + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_4 0x41E4E90 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_5 0x41E4E94 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_6 0x41E4E98 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_7 0x41E4E9C + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_8 0x41E4EA0 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_9 0x41E4EA4 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_10 0x41E4EA8 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_11 0x41E4EAC + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_12 0x41E4EB0 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_13 0x41E4EB4 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_14 0x41E4EB8 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_15 0x41E4EBC + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_16 0x41E4EC0 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_17 0x41E4EC4 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_18 0x41E4EC8 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_19 0x41E4ECC + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_20 0x41E4ED0 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_21 0x41E4ED4 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_22 0x41E4ED8 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_23 0x41E4EDC + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_24 0x41E4EE0 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_25 0x41E4EE4 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_26 0x41E4EE8 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_27 0x41E4EEC + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_28 0x41E4EF0 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_29 0x41E4EF4 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_30 0x41E4EF8 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_31 0x41E4EFC + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_GW_DATA 0x41E4F00 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_GW_REQ 0x41E4F04 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_NUMOF 0x41E4F0C + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_ECC_SEL 0x41E4F10 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_ECC_CTL 0x41E4F14 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_ECC_ERR_MASK 0x41E4F18 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_ECC_GLBL_ERR_MASK 0x41E4F1C + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_ECC_ERR_STS 0x41E4F20 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_ECC_ERR_ADDR 0x41E4F24 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_RM 0x41E4F28 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_ERR_MASK 0x41E4F40 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_ERR_ADDR 0x41E4F44 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_ERR_CAUSE 0x41E4F48 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SPARE_0 0x41E4F60 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SPARE_1 0x41E4F64 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SPARE_2 0x41E4F68 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SPARE_3 0x41E4F6C + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_0 0x41E4F80 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_1 0x41E4F84 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_2 0x41E4F88 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_3 0x41E4F8C + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_4 0x41E4F90 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_5 0x41E4F94 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_6 0x41E4F98 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_7 0x41E4F9C + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_8 0x41E4FA0 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_9 0x41E4FA4 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_10 0x41E4FA8 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_11 0x41E4FAC + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_12 0x41E4FB0 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_13 0x41E4FB4 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_14 0x41E4FB8 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_15 0x41E4FBC + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_16 0x41E4FC0 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_17 0x41E4FC4 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_18 0x41E4FC8 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_19 0x41E4FCC + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_20 0x41E4FD0 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_21 0x41E4FD4 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_22 0x41E4FD8 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_23 0x41E4FDC + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_24 0x41E4FE0 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_25 0x41E4FE4 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_26 0x41E4FE8 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_27 0x41E4FEC + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_28 0x41E4FF0 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_29 0x41E4FF4 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_30 0x41E4FF8 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_31 0x41E4FFC + +#endif /* ASIC_REG_DCORE0_VDEC0_CTRL_SPECIAL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore1_mme_ctrl_lo_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore1_mme_ctrl_lo_regs.h new file mode 100644 index 000000000000..622613dc76fb --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore1_mme_ctrl_lo_regs.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE1_MME_CTRL_LO_REGS_H_ +#define ASIC_REG_DCORE1_MME_CTRL_LO_REGS_H_ + +/* + ***************************************** + * DCORE1_MME_CTRL_LO + * (Prototype: MME_CTRL_LO) + ***************************************** + */ + +#define mmDCORE1_MME_CTRL_LO_ARCH_STATUS 0x42CB000 + +#define mmDCORE1_MME_CTRL_LO_CMD 0x42CB004 + +#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0 0x42CB148 + +#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0 0x42CB14C + +#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0 0x42CB150 + +#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1 0x42CB154 + +#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1 0x42CB158 + +#define mmDCORE1_MME_CTRL_LO_ARCH_A_SS 0x42CB224 + +#define mmDCORE1_MME_CTRL_LO_ARCH_B_SS 0x42CB228 + +#define mmDCORE1_MME_CTRL_LO_ARCH_COUT_SS 0x42CB27C + +#define mmDCORE1_MME_CTRL_LO_QM_STALL 0x42CB400 + +#define mmDCORE1_MME_CTRL_LO_LOG_SHADOW_LO 0x42CB404 + +#define mmDCORE1_MME_CTRL_LO_LOG_SHADOW_HI 0x42CB408 + +#define mmDCORE1_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH 0x42CB40C + +#define mmDCORE1_MME_CTRL_LO_REDUN 0x42CB410 + +#define mmDCORE1_MME_CTRL_LO_EUS_LOCAL_FIFO_TH 0x42CB414 + +#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0 0x42CB418 + +#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1 0x42CB41C + +#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16 0x42CB420 + +#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8 0x42CB424 + +#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32 0x42CB428 + +#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I 0x42CB42C + +#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32 0x42CB430 + +#define mmDCORE1_MME_CTRL_LO_PCU_RL_DESC0 0x42CB434 + +#define mmDCORE1_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE 0x42CB438 + +#define mmDCORE1_MME_CTRL_LO_PCU_RL_TH 0x42CB43C + +#define mmDCORE1_MME_CTRL_LO_PCU_RL_MIN 0x42CB440 + +#define mmDCORE1_MME_CTRL_LO_PCU_RL_CTRL_EN 0x42CB444 + +#define mmDCORE1_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE 0x42CB448 + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_BF16 0x42CB44C + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_BF16 0x42CB450 + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_FP16 0x42CB454 + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_FP16 0x42CB458 + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_F8 0x42CB45C + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD 0x42CB460 + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN 0x42CB464 + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD 0x42CB468 + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN 0x42CB46C + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD 0x42CB470 + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN 0x42CB474 + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD 0x42CB478 + +#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN 0x42CB47C + +#define mmDCORE1_MME_CTRL_LO_PROT 0x42CB480 + +#define mmDCORE1_MME_CTRL_LO_EU 0x42CB484 + +#define mmDCORE1_MME_CTRL_LO_SBTE 0x42CB488 + +#define mmDCORE1_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR 0x42CB48C + +#define mmDCORE1_MME_CTRL_LO_AGU_SM_TOTAL_CNTR 0x42CB490 + +#define mmDCORE1_MME_CTRL_LO_PCU_RL_SAT_SEC 0x42CB494 + +#define mmDCORE1_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32 0x42CB498 + +#define mmDCORE1_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33 0x42CB49C + +#define mmDCORE1_MME_CTRL_LO_EU_ISOLATION_DIS 0x42CB4A0 + +#define mmDCORE1_MME_CTRL_LO_QM_SLV_CLK_EN 0x42CB4A4 + +#define mmDCORE1_MME_CTRL_LO_HBW_CLK_ENABLER_DIS 0x42CB4A8 + +#define mmDCORE1_MME_CTRL_LO_AGU 0x42CB4AC + +#define mmDCORE1_MME_CTRL_LO_QM 0x42CB4B0 + +#define mmDCORE1_MME_CTRL_LO_EARLY_RELEASE_STATUS 0x42CB4B4 + +#define mmDCORE1_MME_CTRL_LO_INTR_CAUSE 0x42CB4B8 + +#define mmDCORE1_MME_CTRL_LO_INTR_MASK 0x42CB4BC + +#define mmDCORE1_MME_CTRL_LO_INTR_CLEAR 0x42CB4C0 + +#define mmDCORE1_MME_CTRL_LO_REDUN_PSOC_SEL_SEC 0x42CB4C4 + +#define mmDCORE1_MME_CTRL_LO_BIST 0x42CB4C8 + +#define mmDCORE1_MME_CTRL_LO_EU_RL_ENABLE 0x42CB4CC + +#define mmDCORE1_MME_CTRL_LO_EU_RL_TOKEN_SEL 0x42CB4D0 + +#define mmDCORE1_MME_CTRL_LO_EU_RL_CFG 0x42CB4D4 + +#define mmDCORE1_MME_CTRL_LO_PCU_DBG_DW0 0x42CB4D8 + +#define mmDCORE1_MME_CTRL_LO_PCU_DBG_DW1 0x42CB4DC + +#define mmDCORE1_MME_CTRL_LO_PCU_DBG_DW2 0x42CB4E0 + +#define mmDCORE1_MME_CTRL_LO_PCU_DBG_DW3 0x42CB4E4 + +#define mmDCORE1_MME_CTRL_LO_PCU_DBG_WKL_ID 0x42CB4E8 + +#define mmDCORE1_MME_CTRL_LO_ETF_MEM_WRAP_RM 0x42CB4EC + +#endif /* ASIC_REG_DCORE1_MME_CTRL_LO_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore3_mme_ctrl_lo_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore3_mme_ctrl_lo_regs.h new file mode 100644 index 000000000000..b06469f5a279 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore3_mme_ctrl_lo_regs.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE3_MME_CTRL_LO_REGS_H_ +#define ASIC_REG_DCORE3_MME_CTRL_LO_REGS_H_ + +/* + ***************************************** + * DCORE3_MME_CTRL_LO + * (Prototype: MME_CTRL_LO) + ***************************************** + */ + +#define mmDCORE3_MME_CTRL_LO_ARCH_STATUS 0x46CB000 + +#define mmDCORE3_MME_CTRL_LO_CMD 0x46CB004 + +#define mmDCORE3_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0 0x46CB148 + +#define mmDCORE3_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0 0x46CB14C + +#define mmDCORE3_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0 0x46CB150 + +#define mmDCORE3_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1 0x46CB154 + +#define mmDCORE3_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1 0x46CB158 + +#define mmDCORE3_MME_CTRL_LO_ARCH_A_SS 0x46CB224 + +#define mmDCORE3_MME_CTRL_LO_ARCH_B_SS 0x46CB228 + +#define mmDCORE3_MME_CTRL_LO_ARCH_COUT_SS 0x46CB27C + +#define mmDCORE3_MME_CTRL_LO_QM_STALL 0x46CB400 + +#define mmDCORE3_MME_CTRL_LO_LOG_SHADOW_LO 0x46CB404 + +#define mmDCORE3_MME_CTRL_LO_LOG_SHADOW_HI 0x46CB408 + +#define mmDCORE3_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH 0x46CB40C + +#define mmDCORE3_MME_CTRL_LO_REDUN 0x46CB410 + +#define mmDCORE3_MME_CTRL_LO_EUS_LOCAL_FIFO_TH 0x46CB414 + +#define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0 0x46CB418 + +#define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1 0x46CB41C + +#define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16 0x46CB420 + +#define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8 0x46CB424 + +#define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32 0x46CB428 + +#define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I 0x46CB42C + +#define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32 0x46CB430 + +#define mmDCORE3_MME_CTRL_LO_PCU_RL_DESC0 0x46CB434 + +#define mmDCORE3_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE 0x46CB438 + +#define mmDCORE3_MME_CTRL_LO_PCU_RL_TH 0x46CB43C + +#define mmDCORE3_MME_CTRL_LO_PCU_RL_MIN 0x46CB440 + +#define mmDCORE3_MME_CTRL_LO_PCU_RL_CTRL_EN 0x46CB444 + +#define mmDCORE3_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE 0x46CB448 + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_A_BF16 0x46CB44C + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_B_BF16 0x46CB450 + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_A_FP16 0x46CB454 + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_B_FP16 0x46CB458 + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_F8 0x46CB45C + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD 0x46CB460 + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN 0x46CB464 + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD 0x46CB468 + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN 0x46CB46C + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD 0x46CB470 + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN 0x46CB474 + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD 0x46CB478 + +#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN 0x46CB47C + +#define mmDCORE3_MME_CTRL_LO_PROT 0x46CB480 + +#define mmDCORE3_MME_CTRL_LO_EU 0x46CB484 + +#define mmDCORE3_MME_CTRL_LO_SBTE 0x46CB488 + +#define mmDCORE3_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR 0x46CB48C + +#define mmDCORE3_MME_CTRL_LO_AGU_SM_TOTAL_CNTR 0x46CB490 + +#define mmDCORE3_MME_CTRL_LO_PCU_RL_SAT_SEC 0x46CB494 + +#define mmDCORE3_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32 0x46CB498 + +#define mmDCORE3_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33 0x46CB49C + +#define mmDCORE3_MME_CTRL_LO_EU_ISOLATION_DIS 0x46CB4A0 + +#define mmDCORE3_MME_CTRL_LO_QM_SLV_CLK_EN 0x46CB4A4 + +#define mmDCORE3_MME_CTRL_LO_HBW_CLK_ENABLER_DIS 0x46CB4A8 + +#define mmDCORE3_MME_CTRL_LO_AGU 0x46CB4AC + +#define mmDCORE3_MME_CTRL_LO_QM 0x46CB4B0 + +#define mmDCORE3_MME_CTRL_LO_EARLY_RELEASE_STATUS 0x46CB4B4 + +#define mmDCORE3_MME_CTRL_LO_INTR_CAUSE 0x46CB4B8 + +#define mmDCORE3_MME_CTRL_LO_INTR_MASK 0x46CB4BC + +#define mmDCORE3_MME_CTRL_LO_INTR_CLEAR 0x46CB4C0 + +#define mmDCORE3_MME_CTRL_LO_REDUN_PSOC_SEL_SEC 0x46CB4C4 + +#define mmDCORE3_MME_CTRL_LO_BIST 0x46CB4C8 + +#define mmDCORE3_MME_CTRL_LO_EU_RL_ENABLE 0x46CB4CC + +#define mmDCORE3_MME_CTRL_LO_EU_RL_TOKEN_SEL 0x46CB4D0 + +#define mmDCORE3_MME_CTRL_LO_EU_RL_CFG 0x46CB4D4 + +#define mmDCORE3_MME_CTRL_LO_PCU_DBG_DW0 0x46CB4D8 + +#define mmDCORE3_MME_CTRL_LO_PCU_DBG_DW1 0x46CB4DC + +#define mmDCORE3_MME_CTRL_LO_PCU_DBG_DW2 0x46CB4E0 + +#define mmDCORE3_MME_CTRL_LO_PCU_DBG_DW3 0x46CB4E4 + +#define mmDCORE3_MME_CTRL_LO_PCU_DBG_WKL_ID 0x46CB4E8 + +#define mmDCORE3_MME_CTRL_LO_ETF_MEM_WRAP_RM 0x46CB4EC + +#endif /* ASIC_REG_DCORE3_MME_CTRL_LO_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/gaudi2_blocks_linux_driver.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/gaudi2_blocks_linux_driver.h new file mode 100644 index 000000000000..3caee4515ad6 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/gaudi2_blocks_linux_driver.h @@ -0,0 +1,45067 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef GAUDI2_BLOCKS_LINUX_DRIVER_H_ +#define GAUDI2_BLOCKS_LINUX_DRIVER_H_ + +#define mmDCORE0_TPC0_ROM_TABLE_BASE 0x0ull +#define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000 +#define mmDCORE0_TPC0_EML_SPMU_BASE 0x1000ull +#define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_SPMU_SECTION 0x1000 +#define mmDCORE0_TPC0_EML_ETF_BASE 0x2000ull +#define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_ETF_SECTION 0x1000 +#define mmDCORE0_TPC0_EML_STM_BASE 0x3000ull +#define DCORE0_TPC0_EML_STM_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_STM_SECTION 0x2000 +#define mmDCORE0_TPC0_EML_CTI_BASE 0x5000ull +#define DCORE0_TPC0_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_CTI_SECTION 0x1000 +#define mmDCORE0_TPC0_EML_FUNNEL_BASE 0x6000ull +#define DCORE0_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE0_TPC0_EML_BUSMON_0_BASE 0x7000ull +#define DCORE0_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE0_TPC0_EML_BUSMON_1_BASE 0x8000ull +#define DCORE0_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE0_TPC0_EML_BUSMON_2_BASE 0x9000ull +#define DCORE0_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE0_TPC0_EML_BUSMON_3_BASE 0xA000ull +#define DCORE0_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE0_TPC0_QM_ARC_RTT_BASE 0xB000ull +#define DCORE0_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_TPC0_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE0_TPC0_EML_CFG_BASE 0x40000ull +#define DCORE0_TPC0_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_CFG_SECTION 0xE800 +#define mmDCORE0_TPC0_EML_CFG_SPECIAL_BASE 0x40E80ull +#define DCORE0_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x41000ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC0_EML_TPC_CFG_BASE 0x41000ull +#define DCORE0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x41050ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x410A0ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x410F0ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x41140ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x41190ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x411E0ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x41230ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x41280ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x412D0ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x41320ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x41370ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x413C0ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x41410ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x41460ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x414B0ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x41500ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_BASE 0x41508ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x415DCull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x4162Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x4167Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x416CCull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x4171Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x4176Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x417BCull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x4180Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x4185Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x418ACull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x418FCull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x4194Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x4199Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x419ECull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x41A3Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x41A8Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x41ADCull +#define DCORE0_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_BASE 0x41AE4ull +#define DCORE0_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC0_EML_TPC_CFG_AXUSER_BASE 0x41E00ull +#define DCORE0_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x41E80ull +#define DCORE0_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC0_EML_QM_DCCM_BASE 0x42000ull +#define DCORE0_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC0_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_QM_ARCAUX_BASE 0x4A000ull +#define DCORE0_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE0_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x4AE80ull +#define DCORE0_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC0_EML_TPC_QM_BASE 0x4C000ull +#define DCORE0_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4C900ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4C908ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4C910ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4C918ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4C920ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4C928ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4C930ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4C938ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4C940ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4C948ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4C950ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4C958ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4C960ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4C968ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4C970ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4C978ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x4CB00ull +#define DCORE0_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x4CB80ull +#define DCORE0_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x4CC00ull +#define DCORE0_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x4CC80ull +#define DCORE0_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC0_EML_TPC_QM_CGM_BASE 0x4CD80ull +#define DCORE0_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC0_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC0_EML_TPC_QM_SPECIAL_BASE 0x4CE80ull +#define DCORE0_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE0_TPC0_EML_CS_BASE 0x1FF000ull +#define DCORE0_TPC0_EML_CS_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_CS_SECTION 0x1000 +#define mmDCORE0_TPC1_ROM_TABLE_BASE 0x200000ull +#define DCORE0_TPC1_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_ROM_TABLE_SECTION 0x1000 +#define mmDCORE0_TPC1_EML_SPMU_BASE 0x201000ull +#define DCORE0_TPC1_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_SPMU_SECTION 0x1000 +#define mmDCORE0_TPC1_EML_ETF_BASE 0x202000ull +#define DCORE0_TPC1_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_ETF_SECTION 0x1000 +#define mmDCORE0_TPC1_EML_STM_BASE 0x203000ull +#define DCORE0_TPC1_EML_STM_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_STM_SECTION 0x2000 +#define mmDCORE0_TPC1_EML_CTI_BASE 0x205000ull +#define DCORE0_TPC1_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_CTI_SECTION 0x1000 +#define mmDCORE0_TPC1_EML_FUNNEL_BASE 0x206000ull +#define DCORE0_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE0_TPC1_EML_BUSMON_0_BASE 0x207000ull +#define DCORE0_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE0_TPC1_EML_BUSMON_1_BASE 0x208000ull +#define DCORE0_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE0_TPC1_EML_BUSMON_2_BASE 0x209000ull +#define DCORE0_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE0_TPC1_EML_BUSMON_3_BASE 0x20A000ull +#define DCORE0_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE0_TPC1_QM_ARC_RTT_BASE 0x20B000ull +#define DCORE0_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_TPC1_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE0_TPC1_EML_CFG_BASE 0x240000ull +#define DCORE0_TPC1_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_CFG_SECTION 0xE800 +#define mmDCORE0_TPC1_EML_CFG_SPECIAL_BASE 0x240E80ull +#define DCORE0_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x241000ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC1_EML_TPC_CFG_BASE 0x241000ull +#define DCORE0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x241050ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x2410A0ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x2410F0ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x241140ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x241190ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x2411E0ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x241230ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x241280ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x2412D0ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x241320ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x241370ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x2413C0ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x241410ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x241460ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x2414B0ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x241500ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_BASE 0x241508ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x2415DCull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x24162Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x24167Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x2416CCull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x24171Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x24176Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x2417BCull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x24180Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x24185Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x2418ACull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x2418FCull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x24194Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x24199Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x2419ECull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x241A3Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x241A8Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x241ADCull +#define DCORE0_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_BASE 0x241AE4ull +#define DCORE0_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC1_EML_TPC_CFG_AXUSER_BASE 0x241E00ull +#define DCORE0_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x241E80ull +#define DCORE0_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC1_EML_QM_DCCM_BASE 0x242000ull +#define DCORE0_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC1_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_QM_ARCAUX_BASE 0x24A000ull +#define DCORE0_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE0_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x24AE80ull +#define DCORE0_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC1_EML_TPC_QM_BASE 0x24C000ull +#define DCORE0_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x24C900ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x24C908ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x24C910ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x24C918ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x24C920ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x24C928ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x24C930ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x24C938ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x24C940ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x24C948ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x24C950ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x24C958ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x24C960ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x24C968ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x24C970ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x24C978ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x24CB00ull +#define DCORE0_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x24CB80ull +#define DCORE0_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x24CC00ull +#define DCORE0_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x24CC80ull +#define DCORE0_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC1_EML_TPC_QM_CGM_BASE 0x24CD80ull +#define DCORE0_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC1_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC1_EML_TPC_QM_SPECIAL_BASE 0x24CE80ull +#define DCORE0_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE0_TPC1_EML_CS_BASE 0x3FF000ull +#define DCORE0_TPC1_EML_CS_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_CS_SECTION 0x1000 +#define mmDCORE0_TPC2_ROM_TABLE_BASE 0x400000ull +#define DCORE0_TPC2_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_ROM_TABLE_SECTION 0x1000 +#define mmDCORE0_TPC2_EML_SPMU_BASE 0x401000ull +#define DCORE0_TPC2_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_SPMU_SECTION 0x1000 +#define mmDCORE0_TPC2_EML_ETF_BASE 0x402000ull +#define DCORE0_TPC2_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_ETF_SECTION 0x1000 +#define mmDCORE0_TPC2_EML_STM_BASE 0x403000ull +#define DCORE0_TPC2_EML_STM_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_STM_SECTION 0x2000 +#define mmDCORE0_TPC2_EML_CTI_BASE 0x405000ull +#define DCORE0_TPC2_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_CTI_SECTION 0x1000 +#define mmDCORE0_TPC2_EML_FUNNEL_BASE 0x406000ull +#define DCORE0_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE0_TPC2_EML_BUSMON_0_BASE 0x407000ull +#define DCORE0_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE0_TPC2_EML_BUSMON_1_BASE 0x408000ull +#define DCORE0_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE0_TPC2_EML_BUSMON_2_BASE 0x409000ull +#define DCORE0_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE0_TPC2_EML_BUSMON_3_BASE 0x40A000ull +#define DCORE0_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE0_TPC2_QM_ARC_RTT_BASE 0x40B000ull +#define DCORE0_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_TPC2_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE0_TPC2_EML_CFG_BASE 0x440000ull +#define DCORE0_TPC2_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_CFG_SECTION 0xE800 +#define mmDCORE0_TPC2_EML_CFG_SPECIAL_BASE 0x440E80ull +#define DCORE0_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x441000ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC2_EML_TPC_CFG_BASE 0x441000ull +#define DCORE0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x441050ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x4410A0ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x4410F0ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x441140ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x441190ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x4411E0ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x441230ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x441280ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x4412D0ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x441320ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x441370ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x4413C0ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x441410ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x441460ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x4414B0ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x441500ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_BASE 0x441508ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x4415DCull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x44162Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x44167Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x4416CCull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x44171Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x44176Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x4417BCull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x44180Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x44185Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x4418ACull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x4418FCull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x44194Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x44199Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x4419ECull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x441A3Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x441A8Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x441ADCull +#define DCORE0_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_BASE 0x441AE4ull +#define DCORE0_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC2_EML_TPC_CFG_AXUSER_BASE 0x441E00ull +#define DCORE0_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x441E80ull +#define DCORE0_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC2_EML_QM_DCCM_BASE 0x442000ull +#define DCORE0_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC2_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_QM_ARCAUX_BASE 0x44A000ull +#define DCORE0_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE0_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x44AE80ull +#define DCORE0_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC2_EML_TPC_QM_BASE 0x44C000ull +#define DCORE0_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x44C900ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x44C908ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x44C910ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x44C918ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x44C920ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x44C928ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x44C930ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x44C938ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x44C940ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x44C948ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x44C950ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x44C958ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x44C960ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x44C968ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x44C970ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x44C978ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x44CB00ull +#define DCORE0_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x44CB80ull +#define DCORE0_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x44CC00ull +#define DCORE0_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x44CC80ull +#define DCORE0_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC2_EML_TPC_QM_CGM_BASE 0x44CD80ull +#define DCORE0_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC2_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC2_EML_TPC_QM_SPECIAL_BASE 0x44CE80ull +#define DCORE0_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE0_TPC2_EML_CS_BASE 0x5FF000ull +#define DCORE0_TPC2_EML_CS_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_CS_SECTION 0x1000 +#define mmDCORE0_TPC3_ROM_TABLE_BASE 0x600000ull +#define DCORE0_TPC3_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_ROM_TABLE_SECTION 0x1000 +#define mmDCORE0_TPC3_EML_SPMU_BASE 0x601000ull +#define DCORE0_TPC3_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_SPMU_SECTION 0x1000 +#define mmDCORE0_TPC3_EML_ETF_BASE 0x602000ull +#define DCORE0_TPC3_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_ETF_SECTION 0x1000 +#define mmDCORE0_TPC3_EML_STM_BASE 0x603000ull +#define DCORE0_TPC3_EML_STM_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_STM_SECTION 0x2000 +#define mmDCORE0_TPC3_EML_CTI_BASE 0x605000ull +#define DCORE0_TPC3_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_CTI_SECTION 0x1000 +#define mmDCORE0_TPC3_EML_FUNNEL_BASE 0x606000ull +#define DCORE0_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE0_TPC3_EML_BUSMON_0_BASE 0x607000ull +#define DCORE0_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE0_TPC3_EML_BUSMON_1_BASE 0x608000ull +#define DCORE0_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE0_TPC3_EML_BUSMON_2_BASE 0x609000ull +#define DCORE0_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE0_TPC3_EML_BUSMON_3_BASE 0x60A000ull +#define DCORE0_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE0_TPC3_QM_ARC_RTT_BASE 0x60B000ull +#define DCORE0_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_TPC3_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE0_TPC3_EML_CFG_BASE 0x640000ull +#define DCORE0_TPC3_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_CFG_SECTION 0xE800 +#define mmDCORE0_TPC3_EML_CFG_SPECIAL_BASE 0x640E80ull +#define DCORE0_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x641000ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC3_EML_TPC_CFG_BASE 0x641000ull +#define DCORE0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x641050ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x6410A0ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x6410F0ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x641140ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x641190ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x6411E0ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x641230ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x641280ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x6412D0ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x641320ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x641370ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x6413C0ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x641410ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x641460ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x6414B0ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x641500ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_BASE 0x641508ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x6415DCull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x64162Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x64167Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x6416CCull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x64171Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x64176Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x6417BCull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x64180Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x64185Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x6418ACull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x6418FCull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x64194Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x64199Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x6419ECull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x641A3Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x641A8Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x641ADCull +#define DCORE0_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_BASE 0x641AE4ull +#define DCORE0_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC3_EML_TPC_CFG_AXUSER_BASE 0x641E00ull +#define DCORE0_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x641E80ull +#define DCORE0_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC3_EML_QM_DCCM_BASE 0x642000ull +#define DCORE0_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC3_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_QM_ARCAUX_BASE 0x64A000ull +#define DCORE0_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE0_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x64AE80ull +#define DCORE0_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC3_EML_TPC_QM_BASE 0x64C000ull +#define DCORE0_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x64C900ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x64C908ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x64C910ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x64C918ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x64C920ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x64C928ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x64C930ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x64C938ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x64C940ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x64C948ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x64C950ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x64C958ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x64C960ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x64C968ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x64C970ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x64C978ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x64CB00ull +#define DCORE0_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x64CB80ull +#define DCORE0_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x64CC00ull +#define DCORE0_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x64CC80ull +#define DCORE0_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC3_EML_TPC_QM_CGM_BASE 0x64CD80ull +#define DCORE0_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC3_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC3_EML_TPC_QM_SPECIAL_BASE 0x64CE80ull +#define DCORE0_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE0_TPC3_EML_CS_BASE 0x7FF000ull +#define DCORE0_TPC3_EML_CS_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_CS_SECTION 0x1000 +#define mmDCORE0_TPC4_ROM_TABLE_BASE 0x800000ull +#define DCORE0_TPC4_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_ROM_TABLE_SECTION 0x1000 +#define mmDCORE0_TPC4_EML_SPMU_BASE 0x801000ull +#define DCORE0_TPC4_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_SPMU_SECTION 0x1000 +#define mmDCORE0_TPC4_EML_ETF_BASE 0x802000ull +#define DCORE0_TPC4_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_ETF_SECTION 0x1000 +#define mmDCORE0_TPC4_EML_STM_BASE 0x803000ull +#define DCORE0_TPC4_EML_STM_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_STM_SECTION 0x2000 +#define mmDCORE0_TPC4_EML_CTI_BASE 0x805000ull +#define DCORE0_TPC4_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_CTI_SECTION 0x1000 +#define mmDCORE0_TPC4_EML_FUNNEL_BASE 0x806000ull +#define DCORE0_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE0_TPC4_EML_BUSMON_0_BASE 0x807000ull +#define DCORE0_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE0_TPC4_EML_BUSMON_1_BASE 0x808000ull +#define DCORE0_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE0_TPC4_EML_BUSMON_2_BASE 0x809000ull +#define DCORE0_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE0_TPC4_EML_BUSMON_3_BASE 0x80A000ull +#define DCORE0_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE0_TPC4_QM_ARC_RTT_BASE 0x80B000ull +#define DCORE0_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_TPC4_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE0_TPC4_EML_CFG_BASE 0x840000ull +#define DCORE0_TPC4_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_CFG_SECTION 0xE800 +#define mmDCORE0_TPC4_EML_CFG_SPECIAL_BASE 0x840E80ull +#define DCORE0_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x841000ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC4_EML_TPC_CFG_BASE 0x841000ull +#define DCORE0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x841050ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x8410A0ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x8410F0ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x841140ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x841190ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x8411E0ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x841230ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x841280ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x8412D0ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x841320ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x841370ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x8413C0ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x841410ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x841460ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x8414B0ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x841500ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_BASE 0x841508ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x8415DCull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x84162Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x84167Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x8416CCull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x84171Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x84176Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x8417BCull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x84180Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x84185Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x8418ACull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x8418FCull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x84194Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x84199Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x8419ECull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x841A3Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x841A8Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x841ADCull +#define DCORE0_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_BASE 0x841AE4ull +#define DCORE0_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC4_EML_TPC_CFG_AXUSER_BASE 0x841E00ull +#define DCORE0_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x841E80ull +#define DCORE0_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC4_EML_QM_DCCM_BASE 0x842000ull +#define DCORE0_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC4_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_QM_ARCAUX_BASE 0x84A000ull +#define DCORE0_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE0_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x84AE80ull +#define DCORE0_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC4_EML_TPC_QM_BASE 0x84C000ull +#define DCORE0_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x84C900ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x84C908ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x84C910ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x84C918ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x84C920ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x84C928ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x84C930ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x84C938ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x84C940ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x84C948ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x84C950ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x84C958ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x84C960ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x84C968ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x84C970ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x84C978ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x84CB00ull +#define DCORE0_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x84CB80ull +#define DCORE0_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x84CC00ull +#define DCORE0_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x84CC80ull +#define DCORE0_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC4_EML_TPC_QM_CGM_BASE 0x84CD80ull +#define DCORE0_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC4_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC4_EML_TPC_QM_SPECIAL_BASE 0x84CE80ull +#define DCORE0_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE0_TPC4_EML_CS_BASE 0x9FF000ull +#define DCORE0_TPC4_EML_CS_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_CS_SECTION 0x1000 +#define mmDCORE0_TPC5_ROM_TABLE_BASE 0xA00000ull +#define DCORE0_TPC5_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_ROM_TABLE_SECTION 0x1000 +#define mmDCORE0_TPC5_EML_SPMU_BASE 0xA01000ull +#define DCORE0_TPC5_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_SPMU_SECTION 0x1000 +#define mmDCORE0_TPC5_EML_ETF_BASE 0xA02000ull +#define DCORE0_TPC5_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_ETF_SECTION 0x1000 +#define mmDCORE0_TPC5_EML_STM_BASE 0xA03000ull +#define DCORE0_TPC5_EML_STM_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_STM_SECTION 0x2000 +#define mmDCORE0_TPC5_EML_CTI_BASE 0xA05000ull +#define DCORE0_TPC5_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_CTI_SECTION 0x1000 +#define mmDCORE0_TPC5_EML_FUNNEL_BASE 0xA06000ull +#define DCORE0_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE0_TPC5_EML_BUSMON_0_BASE 0xA07000ull +#define DCORE0_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE0_TPC5_EML_BUSMON_1_BASE 0xA08000ull +#define DCORE0_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE0_TPC5_EML_BUSMON_2_BASE 0xA09000ull +#define DCORE0_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE0_TPC5_EML_BUSMON_3_BASE 0xA0A000ull +#define DCORE0_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE0_TPC5_QM_ARC_RTT_BASE 0xA0B000ull +#define DCORE0_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_TPC5_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE0_TPC5_EML_CFG_BASE 0xA40000ull +#define DCORE0_TPC5_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_CFG_SECTION 0xE800 +#define mmDCORE0_TPC5_EML_CFG_SPECIAL_BASE 0xA40E80ull +#define DCORE0_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0xA41000ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC5_EML_TPC_CFG_BASE 0xA41000ull +#define DCORE0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0xA41050ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0xA410A0ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0xA410F0ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0xA41140ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0xA41190ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0xA411E0ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0xA41230ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0xA41280ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0xA412D0ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0xA41320ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0xA41370ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0xA413C0ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0xA41410ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0xA41460ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0xA414B0ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0xA41500ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_BASE 0xA41508ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0xA415DCull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0xA4162Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0xA4167Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0xA416CCull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0xA4171Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0xA4176Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0xA417BCull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0xA4180Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0xA4185Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0xA418ACull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0xA418FCull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0xA4194Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0xA4199Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0xA419ECull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0xA41A3Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0xA41A8Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0xA41ADCull +#define DCORE0_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_BASE 0xA41AE4ull +#define DCORE0_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC5_EML_TPC_CFG_AXUSER_BASE 0xA41E00ull +#define DCORE0_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_CFG_SPECIAL_BASE 0xA41E80ull +#define DCORE0_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC5_EML_QM_DCCM_BASE 0xA42000ull +#define DCORE0_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC5_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_QM_ARCAUX_BASE 0xA4A000ull +#define DCORE0_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE0_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0xA4AE80ull +#define DCORE0_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC5_EML_TPC_QM_BASE 0xA4C000ull +#define DCORE0_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0xA4C900ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0xA4C908ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0xA4C910ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0xA4C918ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0xA4C920ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0xA4C928ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0xA4C930ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0xA4C938ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0xA4C940ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0xA4C948ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0xA4C950ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0xA4C958ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0xA4C960ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0xA4C968ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0xA4C970ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0xA4C978ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0xA4CB00ull +#define DCORE0_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0xA4CB80ull +#define DCORE0_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_DBG_HBW_BASE 0xA4CC00ull +#define DCORE0_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC5_EML_TPC_QM_DBG_LBW_BASE 0xA4CC80ull +#define DCORE0_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC5_EML_TPC_QM_CGM_BASE 0xA4CD80ull +#define DCORE0_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC5_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC5_EML_TPC_QM_SPECIAL_BASE 0xA4CE80ull +#define DCORE0_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE0_TPC5_EML_CS_BASE 0xBFF000ull +#define DCORE0_TPC5_EML_CS_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_CS_SECTION 0x1000 +#define mmDCORE0_TPC6_ROM_TABLE_BASE 0xC00000ull +#define DCORE0_TPC6_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_ROM_TABLE_SECTION 0x1000 +#define mmDCORE0_TPC6_EML_SPMU_BASE 0xC01000ull +#define DCORE0_TPC6_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_SPMU_SECTION 0x1000 +#define mmDCORE0_TPC6_EML_ETF_BASE 0xC02000ull +#define DCORE0_TPC6_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_ETF_SECTION 0x1000 +#define mmDCORE0_TPC6_EML_STM_BASE 0xC03000ull +#define DCORE0_TPC6_EML_STM_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_STM_SECTION 0x2000 +#define mmDCORE0_TPC6_EML_CTI_BASE 0xC05000ull +#define DCORE0_TPC6_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_CTI_SECTION 0x1000 +#define mmDCORE0_TPC6_EML_FUNNEL_BASE 0xC06000ull +#define DCORE0_TPC6_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE0_TPC6_EML_BUSMON_0_BASE 0xC07000ull +#define DCORE0_TPC6_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE0_TPC6_EML_BUSMON_1_BASE 0xC08000ull +#define DCORE0_TPC6_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE0_TPC6_EML_BUSMON_2_BASE 0xC09000ull +#define DCORE0_TPC6_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE0_TPC6_EML_BUSMON_3_BASE 0xC0A000ull +#define DCORE0_TPC6_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE0_TPC6_QM_ARC_RTT_BASE 0xC0B000ull +#define DCORE0_TPC6_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_TPC6_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE0_TPC6_EML_CFG_BASE 0xC40000ull +#define DCORE0_TPC6_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_CFG_SECTION 0xE800 +#define mmDCORE0_TPC6_EML_CFG_SPECIAL_BASE 0xC40E80ull +#define DCORE0_TPC6_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC6_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0xC41000ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC6_EML_TPC_CFG_BASE 0xC41000ull +#define DCORE0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0xC41050ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0xC410A0ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0xC410F0ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0xC41140ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0xC41190ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0xC411E0ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0xC41230ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0xC41280ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0xC412D0ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0xC41320ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0xC41370ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0xC413C0ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0xC41410ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0xC41460ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0xC414B0ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0xC41500ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_BASE 0xC41508ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_0_BASE 0xC415DCull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_1_BASE 0xC4162Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_2_BASE 0xC4167Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_3_BASE 0xC416CCull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_4_BASE 0xC4171Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_5_BASE 0xC4176Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_6_BASE 0xC417BCull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_7_BASE 0xC4180Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_8_BASE 0xC4185Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_9_BASE 0xC418ACull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_10_BASE 0xC418FCull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_11_BASE 0xC4194Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_12_BASE 0xC4199Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_13_BASE 0xC419ECull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_14_BASE 0xC41A3Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_15_BASE 0xC41A8Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0xC41ADCull +#define DCORE0_TPC6_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_BASE 0xC41AE4ull +#define DCORE0_TPC6_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC6_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC6_EML_TPC_CFG_AXUSER_BASE 0xC41E00ull +#define DCORE0_TPC6_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_CFG_SPECIAL_BASE 0xC41E80ull +#define DCORE0_TPC6_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC6_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC6_EML_QM_DCCM_BASE 0xC42000ull +#define DCORE0_TPC6_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC6_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_QM_ARCAUX_BASE 0xC4A000ull +#define DCORE0_TPC6_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE0_TPC6_EML_QM_ARCAUX_SPECIAL_BASE 0xC4AE80ull +#define DCORE0_TPC6_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC6_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC6_EML_TPC_QM_BASE 0xC4C000ull +#define DCORE0_TPC6_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0xC4C900ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0xC4C908ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0xC4C910ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0xC4C918ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0xC4C920ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0xC4C928ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0xC4C930ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0xC4C938ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0xC4C940ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0xC4C948ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0xC4C950ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0xC4C958ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0xC4C960ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0xC4C968ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0xC4C970ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0xC4C978ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC6_EML_TPC_QM_AXUSER_SECURED_BASE 0xC4CB00ull +#define DCORE0_TPC6_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_AXUSER_NONSECURED_BASE 0xC4CB80ull +#define DCORE0_TPC6_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_DBG_HBW_BASE 0xC4CC00ull +#define DCORE0_TPC6_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC6_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC6_EML_TPC_QM_DBG_LBW_BASE 0xC4CC80ull +#define DCORE0_TPC6_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC6_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC6_EML_TPC_QM_CGM_BASE 0xC4CD80ull +#define DCORE0_TPC6_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC6_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC6_EML_TPC_QM_SPECIAL_BASE 0xC4CE80ull +#define DCORE0_TPC6_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC6_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE0_TPC6_EML_CS_BASE 0xDFF000ull +#define DCORE0_TPC6_EML_CS_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_CS_SECTION 0x201000 +#define mmDCORE1_TPC0_ROM_TABLE_BASE 0x1000000ull +#define DCORE1_TPC0_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_ROM_TABLE_SECTION 0x1000 +#define mmDCORE1_TPC0_EML_SPMU_BASE 0x1001000ull +#define DCORE1_TPC0_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_SPMU_SECTION 0x1000 +#define mmDCORE1_TPC0_EML_ETF_BASE 0x1002000ull +#define DCORE1_TPC0_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_ETF_SECTION 0x1000 +#define mmDCORE1_TPC0_EML_STM_BASE 0x1003000ull +#define DCORE1_TPC0_EML_STM_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_STM_SECTION 0x2000 +#define mmDCORE1_TPC0_EML_CTI_BASE 0x1005000ull +#define DCORE1_TPC0_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_CTI_SECTION 0x1000 +#define mmDCORE1_TPC0_EML_FUNNEL_BASE 0x1006000ull +#define DCORE1_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE1_TPC0_EML_BUSMON_0_BASE 0x1007000ull +#define DCORE1_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE1_TPC0_EML_BUSMON_1_BASE 0x1008000ull +#define DCORE1_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE1_TPC0_EML_BUSMON_2_BASE 0x1009000ull +#define DCORE1_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE1_TPC0_EML_BUSMON_3_BASE 0x100A000ull +#define DCORE1_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE1_TPC0_QM_ARC_RTT_BASE 0x100B000ull +#define DCORE1_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_TPC0_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE1_TPC0_EML_CFG_BASE 0x1040000ull +#define DCORE1_TPC0_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_CFG_SECTION 0xE800 +#define mmDCORE1_TPC0_EML_CFG_SPECIAL_BASE 0x1040E80ull +#define DCORE1_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1041000ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC0_EML_TPC_CFG_BASE 0x1041000ull +#define DCORE1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1041050ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x10410A0ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x10410F0ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1041140ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1041190ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x10411E0ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1041230ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1041280ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x10412D0ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1041320ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1041370ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x10413C0ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1041410ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1041460ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x10414B0ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1041500ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_BASE 0x1041508ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x10415DCull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x104162Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x104167Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x10416CCull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x104171Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x104176Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x10417BCull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x104180Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x104185Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x10418ACull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x10418FCull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x104194Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x104199Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x10419ECull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1041A3Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1041A8Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1041ADCull +#define DCORE1_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_BASE 0x1041AE4ull +#define DCORE1_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE1_TPC0_EML_TPC_CFG_AXUSER_BASE 0x1041E00ull +#define DCORE1_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x1041E80ull +#define DCORE1_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC0_EML_QM_DCCM_BASE 0x1042000ull +#define DCORE1_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC0_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_QM_ARCAUX_BASE 0x104A000ull +#define DCORE1_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE1_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x104AE80ull +#define DCORE1_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TPC0_EML_TPC_QM_BASE 0x104C000ull +#define DCORE1_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x104C900ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x104C908ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x104C910ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x104C918ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x104C920ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x104C928ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x104C930ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x104C938ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x104C940ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x104C948ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x104C950ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x104C958ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x104C960ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x104C968ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x104C970ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x104C978ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x104CB00ull +#define DCORE1_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x104CB80ull +#define DCORE1_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x104CC00ull +#define DCORE1_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x104CC80ull +#define DCORE1_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_TPC0_EML_TPC_QM_CGM_BASE 0x104CD80ull +#define DCORE1_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC0_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE1_TPC0_EML_TPC_QM_SPECIAL_BASE 0x104CE80ull +#define DCORE1_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE1_TPC0_EML_CS_BASE 0x11FF000ull +#define DCORE1_TPC0_EML_CS_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_CS_SECTION 0x1000 +#define mmDCORE1_TPC1_ROM_TABLE_BASE 0x1200000ull +#define DCORE1_TPC1_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_ROM_TABLE_SECTION 0x1000 +#define mmDCORE1_TPC1_EML_SPMU_BASE 0x1201000ull +#define DCORE1_TPC1_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_SPMU_SECTION 0x1000 +#define mmDCORE1_TPC1_EML_ETF_BASE 0x1202000ull +#define DCORE1_TPC1_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_ETF_SECTION 0x1000 +#define mmDCORE1_TPC1_EML_STM_BASE 0x1203000ull +#define DCORE1_TPC1_EML_STM_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_STM_SECTION 0x2000 +#define mmDCORE1_TPC1_EML_CTI_BASE 0x1205000ull +#define DCORE1_TPC1_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_CTI_SECTION 0x1000 +#define mmDCORE1_TPC1_EML_FUNNEL_BASE 0x1206000ull +#define DCORE1_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE1_TPC1_EML_BUSMON_0_BASE 0x1207000ull +#define DCORE1_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE1_TPC1_EML_BUSMON_1_BASE 0x1208000ull +#define DCORE1_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE1_TPC1_EML_BUSMON_2_BASE 0x1209000ull +#define DCORE1_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE1_TPC1_EML_BUSMON_3_BASE 0x120A000ull +#define DCORE1_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE1_TPC1_QM_ARC_RTT_BASE 0x120B000ull +#define DCORE1_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_TPC1_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE1_TPC1_EML_CFG_BASE 0x1240000ull +#define DCORE1_TPC1_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_CFG_SECTION 0xE800 +#define mmDCORE1_TPC1_EML_CFG_SPECIAL_BASE 0x1240E80ull +#define DCORE1_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1241000ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC1_EML_TPC_CFG_BASE 0x1241000ull +#define DCORE1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1241050ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x12410A0ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x12410F0ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1241140ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1241190ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x12411E0ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1241230ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1241280ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x12412D0ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1241320ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1241370ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x12413C0ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1241410ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1241460ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x12414B0ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1241500ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_BASE 0x1241508ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x12415DCull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x124162Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x124167Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x12416CCull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x124171Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x124176Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x12417BCull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x124180Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x124185Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x12418ACull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x12418FCull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x124194Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x124199Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x12419ECull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1241A3Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1241A8Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1241ADCull +#define DCORE1_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_BASE 0x1241AE4ull +#define DCORE1_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE1_TPC1_EML_TPC_CFG_AXUSER_BASE 0x1241E00ull +#define DCORE1_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x1241E80ull +#define DCORE1_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC1_EML_QM_DCCM_BASE 0x1242000ull +#define DCORE1_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC1_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_QM_ARCAUX_BASE 0x124A000ull +#define DCORE1_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE1_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x124AE80ull +#define DCORE1_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TPC1_EML_TPC_QM_BASE 0x124C000ull +#define DCORE1_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x124C900ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x124C908ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x124C910ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x124C918ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x124C920ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x124C928ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x124C930ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x124C938ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x124C940ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x124C948ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x124C950ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x124C958ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x124C960ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x124C968ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x124C970ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x124C978ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x124CB00ull +#define DCORE1_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x124CB80ull +#define DCORE1_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x124CC00ull +#define DCORE1_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x124CC80ull +#define DCORE1_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_TPC1_EML_TPC_QM_CGM_BASE 0x124CD80ull +#define DCORE1_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC1_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE1_TPC1_EML_TPC_QM_SPECIAL_BASE 0x124CE80ull +#define DCORE1_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE1_TPC1_EML_CS_BASE 0x13FF000ull +#define DCORE1_TPC1_EML_CS_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_CS_SECTION 0x1000 +#define mmDCORE1_TPC2_ROM_TABLE_BASE 0x1400000ull +#define DCORE1_TPC2_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_ROM_TABLE_SECTION 0x1000 +#define mmDCORE1_TPC2_EML_SPMU_BASE 0x1401000ull +#define DCORE1_TPC2_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_SPMU_SECTION 0x1000 +#define mmDCORE1_TPC2_EML_ETF_BASE 0x1402000ull +#define DCORE1_TPC2_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_ETF_SECTION 0x1000 +#define mmDCORE1_TPC2_EML_STM_BASE 0x1403000ull +#define DCORE1_TPC2_EML_STM_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_STM_SECTION 0x2000 +#define mmDCORE1_TPC2_EML_CTI_BASE 0x1405000ull +#define DCORE1_TPC2_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_CTI_SECTION 0x1000 +#define mmDCORE1_TPC2_EML_FUNNEL_BASE 0x1406000ull +#define DCORE1_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE1_TPC2_EML_BUSMON_0_BASE 0x1407000ull +#define DCORE1_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE1_TPC2_EML_BUSMON_1_BASE 0x1408000ull +#define DCORE1_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE1_TPC2_EML_BUSMON_2_BASE 0x1409000ull +#define DCORE1_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE1_TPC2_EML_BUSMON_3_BASE 0x140A000ull +#define DCORE1_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE1_TPC2_QM_ARC_RTT_BASE 0x140B000ull +#define DCORE1_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_TPC2_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE1_TPC2_EML_CFG_BASE 0x1440000ull +#define DCORE1_TPC2_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_CFG_SECTION 0xE800 +#define mmDCORE1_TPC2_EML_CFG_SPECIAL_BASE 0x1440E80ull +#define DCORE1_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1441000ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC2_EML_TPC_CFG_BASE 0x1441000ull +#define DCORE1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1441050ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x14410A0ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x14410F0ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1441140ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1441190ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x14411E0ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1441230ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1441280ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x14412D0ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1441320ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1441370ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x14413C0ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1441410ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1441460ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x14414B0ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1441500ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_BASE 0x1441508ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x14415DCull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x144162Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x144167Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x14416CCull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x144171Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x144176Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x14417BCull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x144180Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x144185Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x14418ACull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x14418FCull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x144194Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x144199Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x14419ECull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1441A3Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1441A8Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1441ADCull +#define DCORE1_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_BASE 0x1441AE4ull +#define DCORE1_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE1_TPC2_EML_TPC_CFG_AXUSER_BASE 0x1441E00ull +#define DCORE1_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x1441E80ull +#define DCORE1_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC2_EML_QM_DCCM_BASE 0x1442000ull +#define DCORE1_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC2_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_QM_ARCAUX_BASE 0x144A000ull +#define DCORE1_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE1_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x144AE80ull +#define DCORE1_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TPC2_EML_TPC_QM_BASE 0x144C000ull +#define DCORE1_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x144C900ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x144C908ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x144C910ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x144C918ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x144C920ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x144C928ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x144C930ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x144C938ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x144C940ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x144C948ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x144C950ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x144C958ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x144C960ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x144C968ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x144C970ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x144C978ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x144CB00ull +#define DCORE1_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x144CB80ull +#define DCORE1_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x144CC00ull +#define DCORE1_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x144CC80ull +#define DCORE1_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_TPC2_EML_TPC_QM_CGM_BASE 0x144CD80ull +#define DCORE1_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC2_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE1_TPC2_EML_TPC_QM_SPECIAL_BASE 0x144CE80ull +#define DCORE1_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE1_TPC2_EML_CS_BASE 0x15FF000ull +#define DCORE1_TPC2_EML_CS_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_CS_SECTION 0x1000 +#define mmDCORE1_TPC3_ROM_TABLE_BASE 0x1600000ull +#define DCORE1_TPC3_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_ROM_TABLE_SECTION 0x1000 +#define mmDCORE1_TPC3_EML_SPMU_BASE 0x1601000ull +#define DCORE1_TPC3_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_SPMU_SECTION 0x1000 +#define mmDCORE1_TPC3_EML_ETF_BASE 0x1602000ull +#define DCORE1_TPC3_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_ETF_SECTION 0x1000 +#define mmDCORE1_TPC3_EML_STM_BASE 0x1603000ull +#define DCORE1_TPC3_EML_STM_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_STM_SECTION 0x2000 +#define mmDCORE1_TPC3_EML_CTI_BASE 0x1605000ull +#define DCORE1_TPC3_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_CTI_SECTION 0x1000 +#define mmDCORE1_TPC3_EML_FUNNEL_BASE 0x1606000ull +#define DCORE1_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE1_TPC3_EML_BUSMON_0_BASE 0x1607000ull +#define DCORE1_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE1_TPC3_EML_BUSMON_1_BASE 0x1608000ull +#define DCORE1_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE1_TPC3_EML_BUSMON_2_BASE 0x1609000ull +#define DCORE1_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE1_TPC3_EML_BUSMON_3_BASE 0x160A000ull +#define DCORE1_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE1_TPC3_QM_ARC_RTT_BASE 0x160B000ull +#define DCORE1_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_TPC3_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE1_TPC3_EML_CFG_BASE 0x1640000ull +#define DCORE1_TPC3_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_CFG_SECTION 0xE800 +#define mmDCORE1_TPC3_EML_CFG_SPECIAL_BASE 0x1640E80ull +#define DCORE1_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1641000ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC3_EML_TPC_CFG_BASE 0x1641000ull +#define DCORE1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1641050ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x16410A0ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x16410F0ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1641140ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1641190ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x16411E0ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1641230ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1641280ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x16412D0ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1641320ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1641370ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x16413C0ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1641410ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1641460ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x16414B0ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1641500ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_BASE 0x1641508ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x16415DCull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x164162Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x164167Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x16416CCull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x164171Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x164176Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x16417BCull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x164180Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x164185Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x16418ACull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x16418FCull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x164194Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x164199Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x16419ECull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1641A3Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1641A8Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1641ADCull +#define DCORE1_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_BASE 0x1641AE4ull +#define DCORE1_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE1_TPC3_EML_TPC_CFG_AXUSER_BASE 0x1641E00ull +#define DCORE1_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x1641E80ull +#define DCORE1_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC3_EML_QM_DCCM_BASE 0x1642000ull +#define DCORE1_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC3_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_QM_ARCAUX_BASE 0x164A000ull +#define DCORE1_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE1_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x164AE80ull +#define DCORE1_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TPC3_EML_TPC_QM_BASE 0x164C000ull +#define DCORE1_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x164C900ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x164C908ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x164C910ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x164C918ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x164C920ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x164C928ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x164C930ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x164C938ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x164C940ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x164C948ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x164C950ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x164C958ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x164C960ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x164C968ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x164C970ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x164C978ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x164CB00ull +#define DCORE1_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x164CB80ull +#define DCORE1_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x164CC00ull +#define DCORE1_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x164CC80ull +#define DCORE1_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_TPC3_EML_TPC_QM_CGM_BASE 0x164CD80ull +#define DCORE1_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC3_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE1_TPC3_EML_TPC_QM_SPECIAL_BASE 0x164CE80ull +#define DCORE1_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE1_TPC3_EML_CS_BASE 0x17FF000ull +#define DCORE1_TPC3_EML_CS_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_CS_SECTION 0x1000 +#define mmDCORE1_TPC4_ROM_TABLE_BASE 0x1800000ull +#define DCORE1_TPC4_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_ROM_TABLE_SECTION 0x1000 +#define mmDCORE1_TPC4_EML_SPMU_BASE 0x1801000ull +#define DCORE1_TPC4_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_SPMU_SECTION 0x1000 +#define mmDCORE1_TPC4_EML_ETF_BASE 0x1802000ull +#define DCORE1_TPC4_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_ETF_SECTION 0x1000 +#define mmDCORE1_TPC4_EML_STM_BASE 0x1803000ull +#define DCORE1_TPC4_EML_STM_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_STM_SECTION 0x2000 +#define mmDCORE1_TPC4_EML_CTI_BASE 0x1805000ull +#define DCORE1_TPC4_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_CTI_SECTION 0x1000 +#define mmDCORE1_TPC4_EML_FUNNEL_BASE 0x1806000ull +#define DCORE1_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE1_TPC4_EML_BUSMON_0_BASE 0x1807000ull +#define DCORE1_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE1_TPC4_EML_BUSMON_1_BASE 0x1808000ull +#define DCORE1_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE1_TPC4_EML_BUSMON_2_BASE 0x1809000ull +#define DCORE1_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE1_TPC4_EML_BUSMON_3_BASE 0x180A000ull +#define DCORE1_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE1_TPC4_QM_ARC_RTT_BASE 0x180B000ull +#define DCORE1_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_TPC4_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE1_TPC4_EML_CFG_BASE 0x1840000ull +#define DCORE1_TPC4_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_CFG_SECTION 0xE800 +#define mmDCORE1_TPC4_EML_CFG_SPECIAL_BASE 0x1840E80ull +#define DCORE1_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1841000ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC4_EML_TPC_CFG_BASE 0x1841000ull +#define DCORE1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1841050ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x18410A0ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x18410F0ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1841140ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1841190ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x18411E0ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1841230ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1841280ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x18412D0ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1841320ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1841370ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x18413C0ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1841410ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1841460ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x18414B0ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1841500ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_BASE 0x1841508ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x18415DCull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x184162Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x184167Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x18416CCull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x184171Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x184176Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x18417BCull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x184180Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x184185Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x18418ACull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x18418FCull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x184194Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x184199Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x18419ECull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1841A3Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1841A8Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1841ADCull +#define DCORE1_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_BASE 0x1841AE4ull +#define DCORE1_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE1_TPC4_EML_TPC_CFG_AXUSER_BASE 0x1841E00ull +#define DCORE1_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x1841E80ull +#define DCORE1_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC4_EML_QM_DCCM_BASE 0x1842000ull +#define DCORE1_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC4_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_QM_ARCAUX_BASE 0x184A000ull +#define DCORE1_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE1_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x184AE80ull +#define DCORE1_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TPC4_EML_TPC_QM_BASE 0x184C000ull +#define DCORE1_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x184C900ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x184C908ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x184C910ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x184C918ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x184C920ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x184C928ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x184C930ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x184C938ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x184C940ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x184C948ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x184C950ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x184C958ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x184C960ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x184C968ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x184C970ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x184C978ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x184CB00ull +#define DCORE1_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x184CB80ull +#define DCORE1_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x184CC00ull +#define DCORE1_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x184CC80ull +#define DCORE1_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_TPC4_EML_TPC_QM_CGM_BASE 0x184CD80ull +#define DCORE1_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC4_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE1_TPC4_EML_TPC_QM_SPECIAL_BASE 0x184CE80ull +#define DCORE1_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE1_TPC4_EML_CS_BASE 0x19FF000ull +#define DCORE1_TPC4_EML_CS_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_CS_SECTION 0x1000 +#define mmDCORE1_TPC5_ROM_TABLE_BASE 0x1A00000ull +#define DCORE1_TPC5_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_ROM_TABLE_SECTION 0x1000 +#define mmDCORE1_TPC5_EML_SPMU_BASE 0x1A01000ull +#define DCORE1_TPC5_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_SPMU_SECTION 0x1000 +#define mmDCORE1_TPC5_EML_ETF_BASE 0x1A02000ull +#define DCORE1_TPC5_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_ETF_SECTION 0x1000 +#define mmDCORE1_TPC5_EML_STM_BASE 0x1A03000ull +#define DCORE1_TPC5_EML_STM_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_STM_SECTION 0x2000 +#define mmDCORE1_TPC5_EML_CTI_BASE 0x1A05000ull +#define DCORE1_TPC5_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_CTI_SECTION 0x1000 +#define mmDCORE1_TPC5_EML_FUNNEL_BASE 0x1A06000ull +#define DCORE1_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE1_TPC5_EML_BUSMON_0_BASE 0x1A07000ull +#define DCORE1_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE1_TPC5_EML_BUSMON_1_BASE 0x1A08000ull +#define DCORE1_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE1_TPC5_EML_BUSMON_2_BASE 0x1A09000ull +#define DCORE1_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE1_TPC5_EML_BUSMON_3_BASE 0x1A0A000ull +#define DCORE1_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE1_TPC5_QM_ARC_RTT_BASE 0x1A0B000ull +#define DCORE1_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_TPC5_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE1_TPC5_EML_CFG_BASE 0x1A40000ull +#define DCORE1_TPC5_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_CFG_SECTION 0xE800 +#define mmDCORE1_TPC5_EML_CFG_SPECIAL_BASE 0x1A40E80ull +#define DCORE1_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1A41000ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC5_EML_TPC_CFG_BASE 0x1A41000ull +#define DCORE1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1A41050ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1A410A0ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1A410F0ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1A41140ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1A41190ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1A411E0ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1A41230ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1A41280ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1A412D0ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1A41320ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1A41370ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1A413C0ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1A41410ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1A41460ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1A414B0ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1A41500ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_BASE 0x1A41508ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1A415DCull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1A4162Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1A4167Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1A416CCull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1A4171Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1A4176Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1A417BCull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1A4180Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1A4185Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1A418ACull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1A418FCull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1A4194Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1A4199Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1A419ECull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1A41A3Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1A41A8Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1A41ADCull +#define DCORE1_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_BASE 0x1A41AE4ull +#define DCORE1_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE1_TPC5_EML_TPC_CFG_AXUSER_BASE 0x1A41E00ull +#define DCORE1_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_CFG_SPECIAL_BASE 0x1A41E80ull +#define DCORE1_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC5_EML_QM_DCCM_BASE 0x1A42000ull +#define DCORE1_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC5_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_QM_ARCAUX_BASE 0x1A4A000ull +#define DCORE1_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE1_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0x1A4AE80ull +#define DCORE1_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TPC5_EML_TPC_QM_BASE 0x1A4C000ull +#define DCORE1_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1A4C900ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1A4C908ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1A4C910ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1A4C918ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1A4C920ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1A4C928ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1A4C930ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1A4C938ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1A4C940ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1A4C948ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1A4C950ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1A4C958ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1A4C960ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1A4C968ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1A4C970ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1A4C978ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0x1A4CB00ull +#define DCORE1_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1A4CB80ull +#define DCORE1_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_DBG_HBW_BASE 0x1A4CC00ull +#define DCORE1_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC5_EML_TPC_QM_DBG_LBW_BASE 0x1A4CC80ull +#define DCORE1_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_TPC5_EML_TPC_QM_CGM_BASE 0x1A4CD80ull +#define DCORE1_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC5_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE1_TPC5_EML_TPC_QM_SPECIAL_BASE 0x1A4CE80ull +#define DCORE1_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE1_TPC5_EML_CS_BASE 0x1BFF000ull +#define DCORE1_TPC5_EML_CS_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_CS_SECTION 0x401000 +#define mmDCORE2_TPC0_ROM_TABLE_BASE 0x2000000ull +#define DCORE2_TPC0_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_ROM_TABLE_SECTION 0x1000 +#define mmDCORE2_TPC0_EML_SPMU_BASE 0x2001000ull +#define DCORE2_TPC0_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_SPMU_SECTION 0x1000 +#define mmDCORE2_TPC0_EML_ETF_BASE 0x2002000ull +#define DCORE2_TPC0_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_ETF_SECTION 0x1000 +#define mmDCORE2_TPC0_EML_STM_BASE 0x2003000ull +#define DCORE2_TPC0_EML_STM_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_STM_SECTION 0x2000 +#define mmDCORE2_TPC0_EML_CTI_BASE 0x2005000ull +#define DCORE2_TPC0_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_CTI_SECTION 0x1000 +#define mmDCORE2_TPC0_EML_FUNNEL_BASE 0x2006000ull +#define DCORE2_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE2_TPC0_EML_BUSMON_0_BASE 0x2007000ull +#define DCORE2_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE2_TPC0_EML_BUSMON_1_BASE 0x2008000ull +#define DCORE2_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE2_TPC0_EML_BUSMON_2_BASE 0x2009000ull +#define DCORE2_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE2_TPC0_EML_BUSMON_3_BASE 0x200A000ull +#define DCORE2_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE2_TPC0_QM_ARC_RTT_BASE 0x200B000ull +#define DCORE2_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_TPC0_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE2_TPC0_EML_CFG_BASE 0x2040000ull +#define DCORE2_TPC0_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_CFG_SECTION 0xE800 +#define mmDCORE2_TPC0_EML_CFG_SPECIAL_BASE 0x2040E80ull +#define DCORE2_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2041000ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC0_EML_TPC_CFG_BASE 0x2041000ull +#define DCORE2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2041050ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x20410A0ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x20410F0ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2041140ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2041190ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x20411E0ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2041230ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2041280ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x20412D0ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2041320ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2041370ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x20413C0ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2041410ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2041460ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x20414B0ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2041500ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_BASE 0x2041508ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x20415DCull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x204162Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x204167Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x20416CCull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x204171Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x204176Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x20417BCull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x204180Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x204185Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x20418ACull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x20418FCull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x204194Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x204199Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x20419ECull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2041A3Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2041A8Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2041ADCull +#define DCORE2_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_BASE 0x2041AE4ull +#define DCORE2_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE2_TPC0_EML_TPC_CFG_AXUSER_BASE 0x2041E00ull +#define DCORE2_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x2041E80ull +#define DCORE2_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC0_EML_QM_DCCM_BASE 0x2042000ull +#define DCORE2_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC0_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_QM_ARCAUX_BASE 0x204A000ull +#define DCORE2_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE2_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x204AE80ull +#define DCORE2_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_TPC0_EML_TPC_QM_BASE 0x204C000ull +#define DCORE2_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x204C900ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x204C908ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x204C910ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x204C918ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x204C920ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x204C928ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x204C930ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x204C938ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x204C940ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x204C948ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x204C950ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x204C958ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x204C960ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x204C968ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x204C970ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x204C978ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x204CB00ull +#define DCORE2_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x204CB80ull +#define DCORE2_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x204CC00ull +#define DCORE2_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x204CC80ull +#define DCORE2_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_TPC0_EML_TPC_QM_CGM_BASE 0x204CD80ull +#define DCORE2_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC0_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE2_TPC0_EML_TPC_QM_SPECIAL_BASE 0x204CE80ull +#define DCORE2_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE2_TPC0_EML_CS_BASE 0x21FF000ull +#define DCORE2_TPC0_EML_CS_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_CS_SECTION 0x1000 +#define mmDCORE2_TPC1_ROM_TABLE_BASE 0x2200000ull +#define DCORE2_TPC1_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_ROM_TABLE_SECTION 0x1000 +#define mmDCORE2_TPC1_EML_SPMU_BASE 0x2201000ull +#define DCORE2_TPC1_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_SPMU_SECTION 0x1000 +#define mmDCORE2_TPC1_EML_ETF_BASE 0x2202000ull +#define DCORE2_TPC1_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_ETF_SECTION 0x1000 +#define mmDCORE2_TPC1_EML_STM_BASE 0x2203000ull +#define DCORE2_TPC1_EML_STM_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_STM_SECTION 0x2000 +#define mmDCORE2_TPC1_EML_CTI_BASE 0x2205000ull +#define DCORE2_TPC1_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_CTI_SECTION 0x1000 +#define mmDCORE2_TPC1_EML_FUNNEL_BASE 0x2206000ull +#define DCORE2_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE2_TPC1_EML_BUSMON_0_BASE 0x2207000ull +#define DCORE2_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE2_TPC1_EML_BUSMON_1_BASE 0x2208000ull +#define DCORE2_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE2_TPC1_EML_BUSMON_2_BASE 0x2209000ull +#define DCORE2_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE2_TPC1_EML_BUSMON_3_BASE 0x220A000ull +#define DCORE2_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE2_TPC1_QM_ARC_RTT_BASE 0x220B000ull +#define DCORE2_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_TPC1_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE2_TPC1_EML_CFG_BASE 0x2240000ull +#define DCORE2_TPC1_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_CFG_SECTION 0xE800 +#define mmDCORE2_TPC1_EML_CFG_SPECIAL_BASE 0x2240E80ull +#define DCORE2_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2241000ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC1_EML_TPC_CFG_BASE 0x2241000ull +#define DCORE2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2241050ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x22410A0ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x22410F0ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2241140ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2241190ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x22411E0ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2241230ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2241280ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x22412D0ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2241320ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2241370ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x22413C0ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2241410ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2241460ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x22414B0ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2241500ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_BASE 0x2241508ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x22415DCull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x224162Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x224167Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x22416CCull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x224171Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x224176Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x22417BCull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x224180Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x224185Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x22418ACull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x22418FCull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x224194Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x224199Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x22419ECull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2241A3Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2241A8Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2241ADCull +#define DCORE2_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_BASE 0x2241AE4ull +#define DCORE2_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE2_TPC1_EML_TPC_CFG_AXUSER_BASE 0x2241E00ull +#define DCORE2_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x2241E80ull +#define DCORE2_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC1_EML_QM_DCCM_BASE 0x2242000ull +#define DCORE2_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC1_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_QM_ARCAUX_BASE 0x224A000ull +#define DCORE2_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE2_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x224AE80ull +#define DCORE2_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_TPC1_EML_TPC_QM_BASE 0x224C000ull +#define DCORE2_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x224C900ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x224C908ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x224C910ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x224C918ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x224C920ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x224C928ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x224C930ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x224C938ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x224C940ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x224C948ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x224C950ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x224C958ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x224C960ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x224C968ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x224C970ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x224C978ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x224CB00ull +#define DCORE2_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x224CB80ull +#define DCORE2_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x224CC00ull +#define DCORE2_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x224CC80ull +#define DCORE2_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_TPC1_EML_TPC_QM_CGM_BASE 0x224CD80ull +#define DCORE2_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC1_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE2_TPC1_EML_TPC_QM_SPECIAL_BASE 0x224CE80ull +#define DCORE2_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE2_TPC1_EML_CS_BASE 0x23FF000ull +#define DCORE2_TPC1_EML_CS_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_CS_SECTION 0x1000 +#define mmDCORE2_TPC2_ROM_TABLE_BASE 0x2400000ull +#define DCORE2_TPC2_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_ROM_TABLE_SECTION 0x1000 +#define mmDCORE2_TPC2_EML_SPMU_BASE 0x2401000ull +#define DCORE2_TPC2_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_SPMU_SECTION 0x1000 +#define mmDCORE2_TPC2_EML_ETF_BASE 0x2402000ull +#define DCORE2_TPC2_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_ETF_SECTION 0x1000 +#define mmDCORE2_TPC2_EML_STM_BASE 0x2403000ull +#define DCORE2_TPC2_EML_STM_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_STM_SECTION 0x2000 +#define mmDCORE2_TPC2_EML_CTI_BASE 0x2405000ull +#define DCORE2_TPC2_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_CTI_SECTION 0x1000 +#define mmDCORE2_TPC2_EML_FUNNEL_BASE 0x2406000ull +#define DCORE2_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE2_TPC2_EML_BUSMON_0_BASE 0x2407000ull +#define DCORE2_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE2_TPC2_EML_BUSMON_1_BASE 0x2408000ull +#define DCORE2_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE2_TPC2_EML_BUSMON_2_BASE 0x2409000ull +#define DCORE2_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE2_TPC2_EML_BUSMON_3_BASE 0x240A000ull +#define DCORE2_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE2_TPC2_QM_ARC_RTT_BASE 0x240B000ull +#define DCORE2_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_TPC2_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE2_TPC2_EML_CFG_BASE 0x2440000ull +#define DCORE2_TPC2_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_CFG_SECTION 0xE800 +#define mmDCORE2_TPC2_EML_CFG_SPECIAL_BASE 0x2440E80ull +#define DCORE2_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2441000ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC2_EML_TPC_CFG_BASE 0x2441000ull +#define DCORE2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2441050ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x24410A0ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x24410F0ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2441140ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2441190ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x24411E0ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2441230ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2441280ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x24412D0ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2441320ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2441370ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x24413C0ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2441410ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2441460ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x24414B0ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2441500ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_BASE 0x2441508ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x24415DCull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x244162Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x244167Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x24416CCull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x244171Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x244176Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x24417BCull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x244180Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x244185Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x24418ACull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x24418FCull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x244194Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x244199Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x24419ECull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2441A3Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2441A8Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2441ADCull +#define DCORE2_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_BASE 0x2441AE4ull +#define DCORE2_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE2_TPC2_EML_TPC_CFG_AXUSER_BASE 0x2441E00ull +#define DCORE2_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x2441E80ull +#define DCORE2_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC2_EML_QM_DCCM_BASE 0x2442000ull +#define DCORE2_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC2_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_QM_ARCAUX_BASE 0x244A000ull +#define DCORE2_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE2_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x244AE80ull +#define DCORE2_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_TPC2_EML_TPC_QM_BASE 0x244C000ull +#define DCORE2_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x244C900ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x244C908ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x244C910ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x244C918ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x244C920ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x244C928ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x244C930ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x244C938ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x244C940ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x244C948ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x244C950ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x244C958ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x244C960ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x244C968ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x244C970ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x244C978ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x244CB00ull +#define DCORE2_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x244CB80ull +#define DCORE2_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x244CC00ull +#define DCORE2_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x244CC80ull +#define DCORE2_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_TPC2_EML_TPC_QM_CGM_BASE 0x244CD80ull +#define DCORE2_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC2_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE2_TPC2_EML_TPC_QM_SPECIAL_BASE 0x244CE80ull +#define DCORE2_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE2_TPC2_EML_CS_BASE 0x25FF000ull +#define DCORE2_TPC2_EML_CS_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_CS_SECTION 0x1000 +#define mmDCORE2_TPC3_ROM_TABLE_BASE 0x2600000ull +#define DCORE2_TPC3_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_ROM_TABLE_SECTION 0x1000 +#define mmDCORE2_TPC3_EML_SPMU_BASE 0x2601000ull +#define DCORE2_TPC3_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_SPMU_SECTION 0x1000 +#define mmDCORE2_TPC3_EML_ETF_BASE 0x2602000ull +#define DCORE2_TPC3_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_ETF_SECTION 0x1000 +#define mmDCORE2_TPC3_EML_STM_BASE 0x2603000ull +#define DCORE2_TPC3_EML_STM_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_STM_SECTION 0x2000 +#define mmDCORE2_TPC3_EML_CTI_BASE 0x2605000ull +#define DCORE2_TPC3_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_CTI_SECTION 0x1000 +#define mmDCORE2_TPC3_EML_FUNNEL_BASE 0x2606000ull +#define DCORE2_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE2_TPC3_EML_BUSMON_0_BASE 0x2607000ull +#define DCORE2_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE2_TPC3_EML_BUSMON_1_BASE 0x2608000ull +#define DCORE2_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE2_TPC3_EML_BUSMON_2_BASE 0x2609000ull +#define DCORE2_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE2_TPC3_EML_BUSMON_3_BASE 0x260A000ull +#define DCORE2_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE2_TPC3_QM_ARC_RTT_BASE 0x260B000ull +#define DCORE2_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_TPC3_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE2_TPC3_EML_CFG_BASE 0x2640000ull +#define DCORE2_TPC3_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_CFG_SECTION 0xE800 +#define mmDCORE2_TPC3_EML_CFG_SPECIAL_BASE 0x2640E80ull +#define DCORE2_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2641000ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC3_EML_TPC_CFG_BASE 0x2641000ull +#define DCORE2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2641050ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x26410A0ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x26410F0ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2641140ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2641190ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x26411E0ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2641230ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2641280ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x26412D0ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2641320ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2641370ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x26413C0ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2641410ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2641460ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x26414B0ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2641500ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_BASE 0x2641508ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x26415DCull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x264162Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x264167Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x26416CCull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x264171Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x264176Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x26417BCull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x264180Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x264185Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x26418ACull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x26418FCull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x264194Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x264199Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x26419ECull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2641A3Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2641A8Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2641ADCull +#define DCORE2_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_BASE 0x2641AE4ull +#define DCORE2_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE2_TPC3_EML_TPC_CFG_AXUSER_BASE 0x2641E00ull +#define DCORE2_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x2641E80ull +#define DCORE2_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC3_EML_QM_DCCM_BASE 0x2642000ull +#define DCORE2_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC3_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_QM_ARCAUX_BASE 0x264A000ull +#define DCORE2_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE2_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x264AE80ull +#define DCORE2_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_TPC3_EML_TPC_QM_BASE 0x264C000ull +#define DCORE2_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x264C900ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x264C908ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x264C910ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x264C918ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x264C920ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x264C928ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x264C930ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x264C938ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x264C940ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x264C948ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x264C950ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x264C958ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x264C960ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x264C968ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x264C970ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x264C978ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x264CB00ull +#define DCORE2_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x264CB80ull +#define DCORE2_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x264CC00ull +#define DCORE2_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x264CC80ull +#define DCORE2_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_TPC3_EML_TPC_QM_CGM_BASE 0x264CD80ull +#define DCORE2_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC3_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE2_TPC3_EML_TPC_QM_SPECIAL_BASE 0x264CE80ull +#define DCORE2_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE2_TPC3_EML_CS_BASE 0x27FF000ull +#define DCORE2_TPC3_EML_CS_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_CS_SECTION 0x1000 +#define mmDCORE2_TPC4_ROM_TABLE_BASE 0x2800000ull +#define DCORE2_TPC4_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_ROM_TABLE_SECTION 0x1000 +#define mmDCORE2_TPC4_EML_SPMU_BASE 0x2801000ull +#define DCORE2_TPC4_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_SPMU_SECTION 0x1000 +#define mmDCORE2_TPC4_EML_ETF_BASE 0x2802000ull +#define DCORE2_TPC4_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_ETF_SECTION 0x1000 +#define mmDCORE2_TPC4_EML_STM_BASE 0x2803000ull +#define DCORE2_TPC4_EML_STM_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_STM_SECTION 0x2000 +#define mmDCORE2_TPC4_EML_CTI_BASE 0x2805000ull +#define DCORE2_TPC4_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_CTI_SECTION 0x1000 +#define mmDCORE2_TPC4_EML_FUNNEL_BASE 0x2806000ull +#define DCORE2_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE2_TPC4_EML_BUSMON_0_BASE 0x2807000ull +#define DCORE2_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE2_TPC4_EML_BUSMON_1_BASE 0x2808000ull +#define DCORE2_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE2_TPC4_EML_BUSMON_2_BASE 0x2809000ull +#define DCORE2_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE2_TPC4_EML_BUSMON_3_BASE 0x280A000ull +#define DCORE2_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE2_TPC4_QM_ARC_RTT_BASE 0x280B000ull +#define DCORE2_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_TPC4_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE2_TPC4_EML_CFG_BASE 0x2840000ull +#define DCORE2_TPC4_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_CFG_SECTION 0xE800 +#define mmDCORE2_TPC4_EML_CFG_SPECIAL_BASE 0x2840E80ull +#define DCORE2_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2841000ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC4_EML_TPC_CFG_BASE 0x2841000ull +#define DCORE2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2841050ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x28410A0ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x28410F0ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2841140ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2841190ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x28411E0ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2841230ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2841280ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x28412D0ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2841320ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2841370ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x28413C0ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2841410ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2841460ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x28414B0ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2841500ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_BASE 0x2841508ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x28415DCull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x284162Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x284167Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x28416CCull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x284171Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x284176Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x28417BCull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x284180Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x284185Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x28418ACull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x28418FCull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x284194Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x284199Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x28419ECull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2841A3Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2841A8Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2841ADCull +#define DCORE2_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_BASE 0x2841AE4ull +#define DCORE2_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE2_TPC4_EML_TPC_CFG_AXUSER_BASE 0x2841E00ull +#define DCORE2_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x2841E80ull +#define DCORE2_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC4_EML_QM_DCCM_BASE 0x2842000ull +#define DCORE2_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC4_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_QM_ARCAUX_BASE 0x284A000ull +#define DCORE2_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE2_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x284AE80ull +#define DCORE2_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_TPC4_EML_TPC_QM_BASE 0x284C000ull +#define DCORE2_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x284C900ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x284C908ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x284C910ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x284C918ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x284C920ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x284C928ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x284C930ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x284C938ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x284C940ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x284C948ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x284C950ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x284C958ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x284C960ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x284C968ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x284C970ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x284C978ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x284CB00ull +#define DCORE2_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x284CB80ull +#define DCORE2_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x284CC00ull +#define DCORE2_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x284CC80ull +#define DCORE2_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_TPC4_EML_TPC_QM_CGM_BASE 0x284CD80ull +#define DCORE2_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC4_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE2_TPC4_EML_TPC_QM_SPECIAL_BASE 0x284CE80ull +#define DCORE2_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE2_TPC4_EML_CS_BASE 0x29FF000ull +#define DCORE2_TPC4_EML_CS_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_CS_SECTION 0x1000 +#define mmDCORE2_TPC5_ROM_TABLE_BASE 0x2A00000ull +#define DCORE2_TPC5_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_ROM_TABLE_SECTION 0x1000 +#define mmDCORE2_TPC5_EML_SPMU_BASE 0x2A01000ull +#define DCORE2_TPC5_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_SPMU_SECTION 0x1000 +#define mmDCORE2_TPC5_EML_ETF_BASE 0x2A02000ull +#define DCORE2_TPC5_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_ETF_SECTION 0x1000 +#define mmDCORE2_TPC5_EML_STM_BASE 0x2A03000ull +#define DCORE2_TPC5_EML_STM_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_STM_SECTION 0x2000 +#define mmDCORE2_TPC5_EML_CTI_BASE 0x2A05000ull +#define DCORE2_TPC5_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_CTI_SECTION 0x1000 +#define mmDCORE2_TPC5_EML_FUNNEL_BASE 0x2A06000ull +#define DCORE2_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE2_TPC5_EML_BUSMON_0_BASE 0x2A07000ull +#define DCORE2_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE2_TPC5_EML_BUSMON_1_BASE 0x2A08000ull +#define DCORE2_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE2_TPC5_EML_BUSMON_2_BASE 0x2A09000ull +#define DCORE2_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE2_TPC5_EML_BUSMON_3_BASE 0x2A0A000ull +#define DCORE2_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE2_TPC5_QM_ARC_RTT_BASE 0x2A0B000ull +#define DCORE2_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_TPC5_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE2_TPC5_EML_CFG_BASE 0x2A40000ull +#define DCORE2_TPC5_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_CFG_SECTION 0xE800 +#define mmDCORE2_TPC5_EML_CFG_SPECIAL_BASE 0x2A40E80ull +#define DCORE2_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2A41000ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC5_EML_TPC_CFG_BASE 0x2A41000ull +#define DCORE2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2A41050ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x2A410A0ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x2A410F0ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2A41140ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2A41190ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x2A411E0ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2A41230ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2A41280ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x2A412D0ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2A41320ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2A41370ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x2A413C0ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2A41410ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2A41460ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x2A414B0ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2A41500ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_BASE 0x2A41508ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0x2A415DCull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0x2A4162Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0x2A4167Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0x2A416CCull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0x2A4171Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0x2A4176Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0x2A417BCull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0x2A4180Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0x2A4185Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0x2A418ACull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0x2A418FCull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0x2A4194Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0x2A4199Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0x2A419ECull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2A41A3Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2A41A8Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2A41ADCull +#define DCORE2_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_BASE 0x2A41AE4ull +#define DCORE2_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE2_TPC5_EML_TPC_CFG_AXUSER_BASE 0x2A41E00ull +#define DCORE2_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_CFG_SPECIAL_BASE 0x2A41E80ull +#define DCORE2_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC5_EML_QM_DCCM_BASE 0x2A42000ull +#define DCORE2_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC5_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_QM_ARCAUX_BASE 0x2A4A000ull +#define DCORE2_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE2_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0x2A4AE80ull +#define DCORE2_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_TPC5_EML_TPC_QM_BASE 0x2A4C000ull +#define DCORE2_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x2A4C900ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x2A4C908ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x2A4C910ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x2A4C918ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x2A4C920ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x2A4C928ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x2A4C930ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x2A4C938ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x2A4C940ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x2A4C948ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x2A4C950ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x2A4C958ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x2A4C960ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x2A4C968ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x2A4C970ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x2A4C978ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0x2A4CB00ull +#define DCORE2_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x2A4CB80ull +#define DCORE2_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_DBG_HBW_BASE 0x2A4CC00ull +#define DCORE2_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC5_EML_TPC_QM_DBG_LBW_BASE 0x2A4CC80ull +#define DCORE2_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_TPC5_EML_TPC_QM_CGM_BASE 0x2A4CD80ull +#define DCORE2_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC5_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE2_TPC5_EML_TPC_QM_SPECIAL_BASE 0x2A4CE80ull +#define DCORE2_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE2_TPC5_EML_CS_BASE 0x2BFF000ull +#define DCORE2_TPC5_EML_CS_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_CS_SECTION 0x401000 +#define mmDCORE3_TPC0_ROM_TABLE_BASE 0x3000000ull +#define DCORE3_TPC0_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_ROM_TABLE_SECTION 0x1000 +#define mmDCORE3_TPC0_EML_SPMU_BASE 0x3001000ull +#define DCORE3_TPC0_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_SPMU_SECTION 0x1000 +#define mmDCORE3_TPC0_EML_ETF_BASE 0x3002000ull +#define DCORE3_TPC0_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_ETF_SECTION 0x1000 +#define mmDCORE3_TPC0_EML_STM_BASE 0x3003000ull +#define DCORE3_TPC0_EML_STM_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_STM_SECTION 0x2000 +#define mmDCORE3_TPC0_EML_CTI_BASE 0x3005000ull +#define DCORE3_TPC0_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_CTI_SECTION 0x1000 +#define mmDCORE3_TPC0_EML_FUNNEL_BASE 0x3006000ull +#define DCORE3_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE3_TPC0_EML_BUSMON_0_BASE 0x3007000ull +#define DCORE3_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE3_TPC0_EML_BUSMON_1_BASE 0x3008000ull +#define DCORE3_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE3_TPC0_EML_BUSMON_2_BASE 0x3009000ull +#define DCORE3_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE3_TPC0_EML_BUSMON_3_BASE 0x300A000ull +#define DCORE3_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE3_TPC0_QM_ARC_RTT_BASE 0x300B000ull +#define DCORE3_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_TPC0_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE3_TPC0_EML_CFG_BASE 0x3040000ull +#define DCORE3_TPC0_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_CFG_SECTION 0xE800 +#define mmDCORE3_TPC0_EML_CFG_SPECIAL_BASE 0x3040E80ull +#define DCORE3_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3041000ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC0_EML_TPC_CFG_BASE 0x3041000ull +#define DCORE3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3041050ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x30410A0ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x30410F0ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3041140ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3041190ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x30411E0ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3041230ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3041280ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x30412D0ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3041320ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3041370ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x30413C0ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3041410ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3041460ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x30414B0ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3041500ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_BASE 0x3041508ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x30415DCull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x304162Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x304167Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x30416CCull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x304171Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x304176Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x30417BCull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x304180Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x304185Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x30418ACull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x30418FCull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x304194Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x304199Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x30419ECull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3041A3Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3041A8Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3041ADCull +#define DCORE3_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_BASE 0x3041AE4ull +#define DCORE3_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE3_TPC0_EML_TPC_CFG_AXUSER_BASE 0x3041E00ull +#define DCORE3_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x3041E80ull +#define DCORE3_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC0_EML_QM_DCCM_BASE 0x3042000ull +#define DCORE3_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC0_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_QM_ARCAUX_BASE 0x304A000ull +#define DCORE3_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE3_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x304AE80ull +#define DCORE3_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TPC0_EML_TPC_QM_BASE 0x304C000ull +#define DCORE3_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x304C900ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x304C908ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x304C910ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x304C918ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x304C920ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x304C928ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x304C930ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x304C938ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x304C940ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x304C948ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x304C950ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x304C958ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x304C960ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x304C968ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x304C970ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x304C978ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x304CB00ull +#define DCORE3_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x304CB80ull +#define DCORE3_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x304CC00ull +#define DCORE3_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x304CC80ull +#define DCORE3_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_TPC0_EML_TPC_QM_CGM_BASE 0x304CD80ull +#define DCORE3_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC0_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE3_TPC0_EML_TPC_QM_SPECIAL_BASE 0x304CE80ull +#define DCORE3_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE3_TPC0_EML_CS_BASE 0x31FF000ull +#define DCORE3_TPC0_EML_CS_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_CS_SECTION 0x1000 +#define mmDCORE3_TPC1_ROM_TABLE_BASE 0x3200000ull +#define DCORE3_TPC1_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_ROM_TABLE_SECTION 0x1000 +#define mmDCORE3_TPC1_EML_SPMU_BASE 0x3201000ull +#define DCORE3_TPC1_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_SPMU_SECTION 0x1000 +#define mmDCORE3_TPC1_EML_ETF_BASE 0x3202000ull +#define DCORE3_TPC1_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_ETF_SECTION 0x1000 +#define mmDCORE3_TPC1_EML_STM_BASE 0x3203000ull +#define DCORE3_TPC1_EML_STM_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_STM_SECTION 0x2000 +#define mmDCORE3_TPC1_EML_CTI_BASE 0x3205000ull +#define DCORE3_TPC1_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_CTI_SECTION 0x1000 +#define mmDCORE3_TPC1_EML_FUNNEL_BASE 0x3206000ull +#define DCORE3_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE3_TPC1_EML_BUSMON_0_BASE 0x3207000ull +#define DCORE3_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE3_TPC1_EML_BUSMON_1_BASE 0x3208000ull +#define DCORE3_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE3_TPC1_EML_BUSMON_2_BASE 0x3209000ull +#define DCORE3_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE3_TPC1_EML_BUSMON_3_BASE 0x320A000ull +#define DCORE3_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE3_TPC1_QM_ARC_RTT_BASE 0x320B000ull +#define DCORE3_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_TPC1_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE3_TPC1_EML_CFG_BASE 0x3240000ull +#define DCORE3_TPC1_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_CFG_SECTION 0xE800 +#define mmDCORE3_TPC1_EML_CFG_SPECIAL_BASE 0x3240E80ull +#define DCORE3_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3241000ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC1_EML_TPC_CFG_BASE 0x3241000ull +#define DCORE3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3241050ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x32410A0ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x32410F0ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3241140ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3241190ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x32411E0ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3241230ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3241280ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x32412D0ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3241320ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3241370ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x32413C0ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3241410ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3241460ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x32414B0ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3241500ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_BASE 0x3241508ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x32415DCull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x324162Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x324167Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x32416CCull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x324171Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x324176Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x32417BCull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x324180Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x324185Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x32418ACull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x32418FCull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x324194Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x324199Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x32419ECull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3241A3Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3241A8Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3241ADCull +#define DCORE3_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_BASE 0x3241AE4ull +#define DCORE3_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE3_TPC1_EML_TPC_CFG_AXUSER_BASE 0x3241E00ull +#define DCORE3_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x3241E80ull +#define DCORE3_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC1_EML_QM_DCCM_BASE 0x3242000ull +#define DCORE3_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC1_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_QM_ARCAUX_BASE 0x324A000ull +#define DCORE3_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE3_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x324AE80ull +#define DCORE3_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TPC1_EML_TPC_QM_BASE 0x324C000ull +#define DCORE3_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x324C900ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x324C908ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x324C910ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x324C918ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x324C920ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x324C928ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x324C930ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x324C938ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x324C940ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x324C948ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x324C950ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x324C958ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x324C960ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x324C968ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x324C970ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x324C978ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x324CB00ull +#define DCORE3_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x324CB80ull +#define DCORE3_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x324CC00ull +#define DCORE3_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x324CC80ull +#define DCORE3_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_TPC1_EML_TPC_QM_CGM_BASE 0x324CD80ull +#define DCORE3_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC1_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE3_TPC1_EML_TPC_QM_SPECIAL_BASE 0x324CE80ull +#define DCORE3_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE3_TPC1_EML_CS_BASE 0x33FF000ull +#define DCORE3_TPC1_EML_CS_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_CS_SECTION 0x1000 +#define mmDCORE3_TPC2_ROM_TABLE_BASE 0x3400000ull +#define DCORE3_TPC2_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_ROM_TABLE_SECTION 0x1000 +#define mmDCORE3_TPC2_EML_SPMU_BASE 0x3401000ull +#define DCORE3_TPC2_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_SPMU_SECTION 0x1000 +#define mmDCORE3_TPC2_EML_ETF_BASE 0x3402000ull +#define DCORE3_TPC2_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_ETF_SECTION 0x1000 +#define mmDCORE3_TPC2_EML_STM_BASE 0x3403000ull +#define DCORE3_TPC2_EML_STM_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_STM_SECTION 0x2000 +#define mmDCORE3_TPC2_EML_CTI_BASE 0x3405000ull +#define DCORE3_TPC2_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_CTI_SECTION 0x1000 +#define mmDCORE3_TPC2_EML_FUNNEL_BASE 0x3406000ull +#define DCORE3_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE3_TPC2_EML_BUSMON_0_BASE 0x3407000ull +#define DCORE3_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE3_TPC2_EML_BUSMON_1_BASE 0x3408000ull +#define DCORE3_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE3_TPC2_EML_BUSMON_2_BASE 0x3409000ull +#define DCORE3_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE3_TPC2_EML_BUSMON_3_BASE 0x340A000ull +#define DCORE3_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE3_TPC2_QM_ARC_RTT_BASE 0x340B000ull +#define DCORE3_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_TPC2_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE3_TPC2_EML_CFG_BASE 0x3440000ull +#define DCORE3_TPC2_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_CFG_SECTION 0xE800 +#define mmDCORE3_TPC2_EML_CFG_SPECIAL_BASE 0x3440E80ull +#define DCORE3_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3441000ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC2_EML_TPC_CFG_BASE 0x3441000ull +#define DCORE3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3441050ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x34410A0ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x34410F0ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3441140ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3441190ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x34411E0ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3441230ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3441280ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x34412D0ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3441320ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3441370ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x34413C0ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3441410ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3441460ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x34414B0ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3441500ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_BASE 0x3441508ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x34415DCull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x344162Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x344167Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x34416CCull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x344171Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x344176Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x34417BCull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x344180Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x344185Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x34418ACull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x34418FCull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x344194Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x344199Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x34419ECull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3441A3Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3441A8Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3441ADCull +#define DCORE3_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_BASE 0x3441AE4ull +#define DCORE3_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE3_TPC2_EML_TPC_CFG_AXUSER_BASE 0x3441E00ull +#define DCORE3_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x3441E80ull +#define DCORE3_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC2_EML_QM_DCCM_BASE 0x3442000ull +#define DCORE3_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC2_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_QM_ARCAUX_BASE 0x344A000ull +#define DCORE3_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE3_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x344AE80ull +#define DCORE3_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TPC2_EML_TPC_QM_BASE 0x344C000ull +#define DCORE3_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x344C900ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x344C908ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x344C910ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x344C918ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x344C920ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x344C928ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x344C930ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x344C938ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x344C940ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x344C948ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x344C950ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x344C958ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x344C960ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x344C968ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x344C970ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x344C978ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x344CB00ull +#define DCORE3_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x344CB80ull +#define DCORE3_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x344CC00ull +#define DCORE3_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x344CC80ull +#define DCORE3_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_TPC2_EML_TPC_QM_CGM_BASE 0x344CD80ull +#define DCORE3_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC2_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE3_TPC2_EML_TPC_QM_SPECIAL_BASE 0x344CE80ull +#define DCORE3_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE3_TPC2_EML_CS_BASE 0x35FF000ull +#define DCORE3_TPC2_EML_CS_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_CS_SECTION 0x1000 +#define mmDCORE3_TPC3_ROM_TABLE_BASE 0x3600000ull +#define DCORE3_TPC3_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_ROM_TABLE_SECTION 0x1000 +#define mmDCORE3_TPC3_EML_SPMU_BASE 0x3601000ull +#define DCORE3_TPC3_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_SPMU_SECTION 0x1000 +#define mmDCORE3_TPC3_EML_ETF_BASE 0x3602000ull +#define DCORE3_TPC3_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_ETF_SECTION 0x1000 +#define mmDCORE3_TPC3_EML_STM_BASE 0x3603000ull +#define DCORE3_TPC3_EML_STM_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_STM_SECTION 0x2000 +#define mmDCORE3_TPC3_EML_CTI_BASE 0x3605000ull +#define DCORE3_TPC3_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_CTI_SECTION 0x1000 +#define mmDCORE3_TPC3_EML_FUNNEL_BASE 0x3606000ull +#define DCORE3_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE3_TPC3_EML_BUSMON_0_BASE 0x3607000ull +#define DCORE3_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE3_TPC3_EML_BUSMON_1_BASE 0x3608000ull +#define DCORE3_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE3_TPC3_EML_BUSMON_2_BASE 0x3609000ull +#define DCORE3_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE3_TPC3_EML_BUSMON_3_BASE 0x360A000ull +#define DCORE3_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE3_TPC3_QM_ARC_RTT_BASE 0x360B000ull +#define DCORE3_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_TPC3_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE3_TPC3_EML_CFG_BASE 0x3640000ull +#define DCORE3_TPC3_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_CFG_SECTION 0xE800 +#define mmDCORE3_TPC3_EML_CFG_SPECIAL_BASE 0x3640E80ull +#define DCORE3_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3641000ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC3_EML_TPC_CFG_BASE 0x3641000ull +#define DCORE3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3641050ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x36410A0ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x36410F0ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3641140ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3641190ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x36411E0ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3641230ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3641280ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x36412D0ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3641320ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3641370ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x36413C0ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3641410ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3641460ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x36414B0ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3641500ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_BASE 0x3641508ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x36415DCull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x364162Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x364167Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x36416CCull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x364171Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x364176Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x36417BCull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x364180Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x364185Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x36418ACull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x36418FCull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x364194Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x364199Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x36419ECull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3641A3Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3641A8Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3641ADCull +#define DCORE3_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_BASE 0x3641AE4ull +#define DCORE3_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE3_TPC3_EML_TPC_CFG_AXUSER_BASE 0x3641E00ull +#define DCORE3_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x3641E80ull +#define DCORE3_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC3_EML_QM_DCCM_BASE 0x3642000ull +#define DCORE3_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC3_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_QM_ARCAUX_BASE 0x364A000ull +#define DCORE3_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE3_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x364AE80ull +#define DCORE3_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TPC3_EML_TPC_QM_BASE 0x364C000ull +#define DCORE3_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x364C900ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x364C908ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x364C910ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x364C918ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x364C920ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x364C928ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x364C930ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x364C938ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x364C940ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x364C948ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x364C950ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x364C958ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x364C960ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x364C968ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x364C970ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x364C978ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x364CB00ull +#define DCORE3_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x364CB80ull +#define DCORE3_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x364CC00ull +#define DCORE3_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x364CC80ull +#define DCORE3_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_TPC3_EML_TPC_QM_CGM_BASE 0x364CD80ull +#define DCORE3_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC3_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE3_TPC3_EML_TPC_QM_SPECIAL_BASE 0x364CE80ull +#define DCORE3_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE3_TPC3_EML_CS_BASE 0x37FF000ull +#define DCORE3_TPC3_EML_CS_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_CS_SECTION 0x1000 +#define mmDCORE3_TPC4_ROM_TABLE_BASE 0x3800000ull +#define DCORE3_TPC4_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_ROM_TABLE_SECTION 0x1000 +#define mmDCORE3_TPC4_EML_SPMU_BASE 0x3801000ull +#define DCORE3_TPC4_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_SPMU_SECTION 0x1000 +#define mmDCORE3_TPC4_EML_ETF_BASE 0x3802000ull +#define DCORE3_TPC4_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_ETF_SECTION 0x1000 +#define mmDCORE3_TPC4_EML_STM_BASE 0x3803000ull +#define DCORE3_TPC4_EML_STM_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_STM_SECTION 0x2000 +#define mmDCORE3_TPC4_EML_CTI_BASE 0x3805000ull +#define DCORE3_TPC4_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_CTI_SECTION 0x1000 +#define mmDCORE3_TPC4_EML_FUNNEL_BASE 0x3806000ull +#define DCORE3_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE3_TPC4_EML_BUSMON_0_BASE 0x3807000ull +#define DCORE3_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE3_TPC4_EML_BUSMON_1_BASE 0x3808000ull +#define DCORE3_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE3_TPC4_EML_BUSMON_2_BASE 0x3809000ull +#define DCORE3_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE3_TPC4_EML_BUSMON_3_BASE 0x380A000ull +#define DCORE3_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE3_TPC4_QM_ARC_RTT_BASE 0x380B000ull +#define DCORE3_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_TPC4_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE3_TPC4_EML_CFG_BASE 0x3840000ull +#define DCORE3_TPC4_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_CFG_SECTION 0xE800 +#define mmDCORE3_TPC4_EML_CFG_SPECIAL_BASE 0x3840E80ull +#define DCORE3_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3841000ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC4_EML_TPC_CFG_BASE 0x3841000ull +#define DCORE3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3841050ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x38410A0ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x38410F0ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3841140ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3841190ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x38411E0ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3841230ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3841280ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x38412D0ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3841320ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3841370ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x38413C0ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3841410ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3841460ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x38414B0ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3841500ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_BASE 0x3841508ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x38415DCull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x384162Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x384167Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x38416CCull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x384171Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x384176Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x38417BCull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x384180Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x384185Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x38418ACull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x38418FCull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x384194Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x384199Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x38419ECull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3841A3Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3841A8Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3841ADCull +#define DCORE3_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_BASE 0x3841AE4ull +#define DCORE3_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE3_TPC4_EML_TPC_CFG_AXUSER_BASE 0x3841E00ull +#define DCORE3_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x3841E80ull +#define DCORE3_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC4_EML_QM_DCCM_BASE 0x3842000ull +#define DCORE3_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC4_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_QM_ARCAUX_BASE 0x384A000ull +#define DCORE3_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE3_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x384AE80ull +#define DCORE3_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TPC4_EML_TPC_QM_BASE 0x384C000ull +#define DCORE3_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x384C900ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x384C908ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x384C910ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x384C918ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x384C920ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x384C928ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x384C930ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x384C938ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x384C940ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x384C948ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x384C950ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x384C958ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x384C960ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x384C968ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x384C970ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x384C978ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x384CB00ull +#define DCORE3_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x384CB80ull +#define DCORE3_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x384CC00ull +#define DCORE3_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x384CC80ull +#define DCORE3_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_TPC4_EML_TPC_QM_CGM_BASE 0x384CD80ull +#define DCORE3_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC4_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE3_TPC4_EML_TPC_QM_SPECIAL_BASE 0x384CE80ull +#define DCORE3_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE3_TPC4_EML_CS_BASE 0x39FF000ull +#define DCORE3_TPC4_EML_CS_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_CS_SECTION 0x1000 +#define mmDCORE3_TPC5_ROM_TABLE_BASE 0x3A00000ull +#define DCORE3_TPC5_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_ROM_TABLE_SECTION 0x1000 +#define mmDCORE3_TPC5_EML_SPMU_BASE 0x3A01000ull +#define DCORE3_TPC5_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_SPMU_SECTION 0x1000 +#define mmDCORE3_TPC5_EML_ETF_BASE 0x3A02000ull +#define DCORE3_TPC5_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_ETF_SECTION 0x1000 +#define mmDCORE3_TPC5_EML_STM_BASE 0x3A03000ull +#define DCORE3_TPC5_EML_STM_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_STM_SECTION 0x2000 +#define mmDCORE3_TPC5_EML_CTI_BASE 0x3A05000ull +#define DCORE3_TPC5_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_CTI_SECTION 0x1000 +#define mmDCORE3_TPC5_EML_FUNNEL_BASE 0x3A06000ull +#define DCORE3_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_FUNNEL_SECTION 0x1000 +#define mmDCORE3_TPC5_EML_BUSMON_0_BASE 0x3A07000ull +#define DCORE3_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_BUSMON_0_SECTION 0x1000 +#define mmDCORE3_TPC5_EML_BUSMON_1_BASE 0x3A08000ull +#define DCORE3_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_BUSMON_1_SECTION 0x1000 +#define mmDCORE3_TPC5_EML_BUSMON_2_BASE 0x3A09000ull +#define DCORE3_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_BUSMON_2_SECTION 0x1000 +#define mmDCORE3_TPC5_EML_BUSMON_3_BASE 0x3A0A000ull +#define DCORE3_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_BUSMON_3_SECTION 0x1000 +#define mmDCORE3_TPC5_QM_ARC_RTT_BASE 0x3A0B000ull +#define DCORE3_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_TPC5_QM_ARC_RTT_SECTION 0x35000 +#define mmDCORE3_TPC5_EML_CFG_BASE 0x3A40000ull +#define DCORE3_TPC5_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_CFG_SECTION 0xE800 +#define mmDCORE3_TPC5_EML_CFG_SPECIAL_BASE 0x3A40E80ull +#define DCORE3_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3A41000ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC5_EML_TPC_CFG_BASE 0x3A41000ull +#define DCORE3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_TPC_CFG_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3A41050ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x3A410A0ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x3A410F0ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3A41140ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3A41190ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x3A411E0ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3A41230ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3A41280ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x3A412D0ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3A41320ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3A41370ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x3A413C0ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3A41410ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3A41460ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x3A414B0ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3A41500ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_BASE 0x3A41508ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0x3A415DCull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0x3A4162Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0x3A4167Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0x3A416CCull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0x3A4171Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0x3A4176Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0x3A417BCull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0x3A4180Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0x3A4185Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0x3A418ACull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0x3A418FCull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0x3A4194Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0x3A4199Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0x3A419ECull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3A41A3Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3A41A8Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3A41ADCull +#define DCORE3_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_BASE 0x3A41AE4ull +#define DCORE3_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0 +#define mmDCORE3_TPC5_EML_TPC_CFG_AXUSER_BASE 0x3A41E00ull +#define DCORE3_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_CFG_SPECIAL_BASE 0x3A41E80ull +#define DCORE3_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC5_EML_QM_DCCM_BASE 0x3A42000ull +#define DCORE3_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC5_EML_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_QM_ARCAUX_BASE 0x3A4A000ull +#define DCORE3_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_QM_ARCAUX_SECTION 0xE800 +#define mmDCORE3_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0x3A4AE80ull +#define DCORE3_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TPC5_EML_TPC_QM_BASE 0x3A4C000ull +#define DCORE3_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_TPC_QM_SECTION 0x9000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x3A4C900ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x3A4C908ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x3A4C910ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x3A4C918ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x3A4C920ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x3A4C928ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x3A4C930ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x3A4C938ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x3A4C940ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x3A4C948ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x3A4C950ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x3A4C958ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x3A4C960ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x3A4C968ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x3A4C970ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x3A4C978ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0x3A4CB00ull +#define DCORE3_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x3A4CB80ull +#define DCORE3_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_DBG_HBW_BASE 0x3A4CC00ull +#define DCORE3_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC5_EML_TPC_QM_DBG_LBW_BASE 0x3A4CC80ull +#define DCORE3_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_TPC5_EML_TPC_QM_CGM_BASE 0x3A4CD80ull +#define DCORE3_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC5_EML_TPC_QM_CGM_SECTION 0x1000 +#define mmDCORE3_TPC5_EML_TPC_QM_SPECIAL_BASE 0x3A4CE80ull +#define DCORE3_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 +#define mmDCORE3_TPC5_EML_CS_BASE 0x3BFF000ull +#define DCORE3_TPC5_EML_CS_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_CS_SECTION 0x401000 +#define mmDCORE0_TPC0_QM_DCCM_BASE 0x4000000ull +#define DCORE0_TPC0_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC0_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_ARC_AUX_BASE 0x4008000ull +#define DCORE0_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE0_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x4008E80ull +#define DCORE0_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC0_QM_BASE 0x400A000ull +#define DCORE0_TPC0_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_QM_SECTION 0x9000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x400A900ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x400A908ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x400A910ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x400A918ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x400A920ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x400A928ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x400A930ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x400A938ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x400A940ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x400A948ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x400A950ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x400A958ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x400A960ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x400A968ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x400A970ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x400A978ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC0_QM_AXUSER_SECURED_BASE 0x400AB00ull +#define DCORE0_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_BASE 0x400AB80ull +#define DCORE0_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_DBG_HBW_BASE 0x400AC00ull +#define DCORE0_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC0_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC0_QM_DBG_LBW_BASE 0x400AC80ull +#define DCORE0_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC0_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC0_QM_CGM_BASE 0x400AD80ull +#define DCORE0_TPC0_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC0_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC0_QM_SPECIAL_BASE 0x400AE80ull +#define DCORE0_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC0_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x400B000ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC0_CFG_BASE 0x400B000ull +#define DCORE0_TPC0_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_CFG_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x400B050ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x400B0A0ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x400B0F0ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x400B140ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x400B190ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x400B1E0ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x400B230ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x400B280ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x400B2D0ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x400B320ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x400B370ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x400B3C0ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x400B410ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x400B460ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x400B4B0ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x400B500ull +#define DCORE0_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC0_CFG_KERNEL_BASE 0x400B508ull +#define DCORE0_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC0_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE 0x400B5DCull +#define DCORE0_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_1_BASE 0x400B62Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_2_BASE 0x400B67Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_3_BASE 0x400B6CCull +#define DCORE0_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_4_BASE 0x400B71Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_5_BASE 0x400B76Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_6_BASE 0x400B7BCull +#define DCORE0_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_7_BASE 0x400B80Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_8_BASE 0x400B85Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_9_BASE 0x400B8ACull +#define DCORE0_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_10_BASE 0x400B8FCull +#define DCORE0_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_11_BASE 0x400B94Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_12_BASE 0x400B99Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_13_BASE 0x400B9ECull +#define DCORE0_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_14_BASE 0x400BA3Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_TENSOR_15_BASE 0x400BA8Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x400BADCull +#define DCORE0_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC0_CFG_QM_BASE 0x400BAE4ull +#define DCORE0_TPC0_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC0_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC0_CFG_AXUSER_BASE 0x400BE00ull +#define DCORE0_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC0_CFG_SPECIAL_BASE 0x400BE80ull +#define DCORE0_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC0_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x400C000ull +#define DCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x400C200ull +#define DCORE0_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x400C400ull +#define DCORE0_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x400C600ull +#define DCORE0_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_TPC0_MSTR_IF_E2E_CRDT_BASE 0x400C800ull +#define DCORE0_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_TPC0_MSTR_IF_AXUSER_BASE 0x400CA80ull +#define DCORE0_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC0_MSTR_IF_DBG_HBW_BASE 0x400CB00ull +#define DCORE0_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC0_MSTR_IF_DBG_LBW_BASE 0x400CB80ull +#define DCORE0_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_TPC0_MSTR_IF_CORE_HBW_BASE 0x400CC00ull +#define DCORE0_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_TPC0_MSTR_IF_CORE_LBW_BASE 0x400CD80ull +#define DCORE0_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_TPC0_MSTR_IF_SPECIAL_BASE 0x400CE80ull +#define DCORE0_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE0_TPC1_QM_DCCM_BASE 0x4010000ull +#define DCORE0_TPC1_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC1_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_ARC_AUX_BASE 0x4018000ull +#define DCORE0_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE0_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x4018E80ull +#define DCORE0_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC1_QM_BASE 0x401A000ull +#define DCORE0_TPC1_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_QM_SECTION 0x9000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x401A900ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x401A908ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x401A910ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x401A918ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x401A920ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x401A928ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x401A930ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x401A938ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x401A940ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x401A948ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x401A950ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x401A958ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x401A960ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x401A968ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x401A970ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x401A978ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC1_QM_AXUSER_SECURED_BASE 0x401AB00ull +#define DCORE0_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_AXUSER_NONSECURED_BASE 0x401AB80ull +#define DCORE0_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_DBG_HBW_BASE 0x401AC00ull +#define DCORE0_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC1_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC1_QM_DBG_LBW_BASE 0x401AC80ull +#define DCORE0_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC1_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC1_QM_CGM_BASE 0x401AD80ull +#define DCORE0_TPC1_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC1_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC1_QM_SPECIAL_BASE 0x401AE80ull +#define DCORE0_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC1_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x401B000ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC1_CFG_BASE 0x401B000ull +#define DCORE0_TPC1_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_CFG_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x401B050ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x401B0A0ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x401B0F0ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x401B140ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x401B190ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x401B1E0ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x401B230ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x401B280ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x401B2D0ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x401B320ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x401B370ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x401B3C0ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x401B410ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x401B460ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x401B4B0ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x401B500ull +#define DCORE0_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC1_CFG_KERNEL_BASE 0x401B508ull +#define DCORE0_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC1_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_0_BASE 0x401B5DCull +#define DCORE0_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_1_BASE 0x401B62Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_2_BASE 0x401B67Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_3_BASE 0x401B6CCull +#define DCORE0_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_4_BASE 0x401B71Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_5_BASE 0x401B76Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_6_BASE 0x401B7BCull +#define DCORE0_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_7_BASE 0x401B80Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_8_BASE 0x401B85Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_9_BASE 0x401B8ACull +#define DCORE0_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_10_BASE 0x401B8FCull +#define DCORE0_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_11_BASE 0x401B94Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_12_BASE 0x401B99Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_13_BASE 0x401B9ECull +#define DCORE0_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_14_BASE 0x401BA3Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_TENSOR_15_BASE 0x401BA8Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x401BADCull +#define DCORE0_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC1_CFG_QM_BASE 0x401BAE4ull +#define DCORE0_TPC1_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC1_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC1_CFG_AXUSER_BASE 0x401BE00ull +#define DCORE0_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC1_CFG_SPECIAL_BASE 0x401BE80ull +#define DCORE0_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC1_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x401C000ull +#define DCORE0_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x401C200ull +#define DCORE0_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x401C400ull +#define DCORE0_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x401C600ull +#define DCORE0_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_TPC1_MSTR_IF_E2E_CRDT_BASE 0x401C800ull +#define DCORE0_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_TPC1_MSTR_IF_AXUSER_BASE 0x401CA80ull +#define DCORE0_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC1_MSTR_IF_DBG_HBW_BASE 0x401CB00ull +#define DCORE0_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC1_MSTR_IF_DBG_LBW_BASE 0x401CB80ull +#define DCORE0_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_TPC1_MSTR_IF_CORE_HBW_BASE 0x401CC00ull +#define DCORE0_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_TPC1_MSTR_IF_CORE_LBW_BASE 0x401CD80ull +#define DCORE0_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_TPC1_MSTR_IF_SPECIAL_BASE 0x401CE80ull +#define DCORE0_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE0_TPC2_QM_DCCM_BASE 0x4020000ull +#define DCORE0_TPC2_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC2_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_ARC_AUX_BASE 0x4028000ull +#define DCORE0_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE0_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x4028E80ull +#define DCORE0_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC2_QM_BASE 0x402A000ull +#define DCORE0_TPC2_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_QM_SECTION 0x9000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x402A900ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x402A908ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x402A910ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x402A918ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x402A920ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x402A928ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x402A930ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x402A938ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x402A940ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x402A948ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x402A950ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x402A958ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x402A960ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x402A968ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x402A970ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x402A978ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC2_QM_AXUSER_SECURED_BASE 0x402AB00ull +#define DCORE0_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_AXUSER_NONSECURED_BASE 0x402AB80ull +#define DCORE0_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_DBG_HBW_BASE 0x402AC00ull +#define DCORE0_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC2_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC2_QM_DBG_LBW_BASE 0x402AC80ull +#define DCORE0_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC2_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC2_QM_CGM_BASE 0x402AD80ull +#define DCORE0_TPC2_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC2_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC2_QM_SPECIAL_BASE 0x402AE80ull +#define DCORE0_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC2_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x402B000ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC2_CFG_BASE 0x402B000ull +#define DCORE0_TPC2_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_CFG_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x402B050ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x402B0A0ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x402B0F0ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x402B140ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x402B190ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x402B1E0ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x402B230ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x402B280ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x402B2D0ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x402B320ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x402B370ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x402B3C0ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x402B410ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x402B460ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x402B4B0ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x402B500ull +#define DCORE0_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC2_CFG_KERNEL_BASE 0x402B508ull +#define DCORE0_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC2_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_0_BASE 0x402B5DCull +#define DCORE0_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_1_BASE 0x402B62Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_2_BASE 0x402B67Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_3_BASE 0x402B6CCull +#define DCORE0_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_4_BASE 0x402B71Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_5_BASE 0x402B76Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_6_BASE 0x402B7BCull +#define DCORE0_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_7_BASE 0x402B80Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_8_BASE 0x402B85Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_9_BASE 0x402B8ACull +#define DCORE0_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_10_BASE 0x402B8FCull +#define DCORE0_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_11_BASE 0x402B94Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_12_BASE 0x402B99Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_13_BASE 0x402B9ECull +#define DCORE0_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_14_BASE 0x402BA3Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_TENSOR_15_BASE 0x402BA8Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x402BADCull +#define DCORE0_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC2_CFG_QM_BASE 0x402BAE4ull +#define DCORE0_TPC2_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC2_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC2_CFG_AXUSER_BASE 0x402BE00ull +#define DCORE0_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC2_CFG_SPECIAL_BASE 0x402BE80ull +#define DCORE0_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC2_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x402C000ull +#define DCORE0_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x402C200ull +#define DCORE0_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x402C400ull +#define DCORE0_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x402C600ull +#define DCORE0_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_TPC2_MSTR_IF_E2E_CRDT_BASE 0x402C800ull +#define DCORE0_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_TPC2_MSTR_IF_AXUSER_BASE 0x402CA80ull +#define DCORE0_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC2_MSTR_IF_DBG_HBW_BASE 0x402CB00ull +#define DCORE0_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC2_MSTR_IF_DBG_LBW_BASE 0x402CB80ull +#define DCORE0_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_TPC2_MSTR_IF_CORE_HBW_BASE 0x402CC00ull +#define DCORE0_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_TPC2_MSTR_IF_CORE_LBW_BASE 0x402CD80ull +#define DCORE0_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_TPC2_MSTR_IF_SPECIAL_BASE 0x402CE80ull +#define DCORE0_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE0_TPC3_QM_DCCM_BASE 0x4030000ull +#define DCORE0_TPC3_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC3_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_ARC_AUX_BASE 0x4038000ull +#define DCORE0_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE0_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x4038E80ull +#define DCORE0_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC3_QM_BASE 0x403A000ull +#define DCORE0_TPC3_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_QM_SECTION 0x9000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x403A900ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x403A908ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x403A910ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x403A918ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x403A920ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x403A928ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x403A930ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x403A938ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x403A940ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x403A948ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x403A950ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x403A958ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x403A960ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x403A968ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x403A970ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x403A978ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC3_QM_AXUSER_SECURED_BASE 0x403AB00ull +#define DCORE0_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_AXUSER_NONSECURED_BASE 0x403AB80ull +#define DCORE0_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_DBG_HBW_BASE 0x403AC00ull +#define DCORE0_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC3_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC3_QM_DBG_LBW_BASE 0x403AC80ull +#define DCORE0_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC3_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC3_QM_CGM_BASE 0x403AD80ull +#define DCORE0_TPC3_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC3_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC3_QM_SPECIAL_BASE 0x403AE80ull +#define DCORE0_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC3_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x403B000ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC3_CFG_BASE 0x403B000ull +#define DCORE0_TPC3_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_CFG_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x403B050ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x403B0A0ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x403B0F0ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x403B140ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x403B190ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x403B1E0ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x403B230ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x403B280ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x403B2D0ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x403B320ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x403B370ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x403B3C0ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x403B410ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x403B460ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x403B4B0ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x403B500ull +#define DCORE0_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC3_CFG_KERNEL_BASE 0x403B508ull +#define DCORE0_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC3_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_0_BASE 0x403B5DCull +#define DCORE0_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_1_BASE 0x403B62Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_2_BASE 0x403B67Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_3_BASE 0x403B6CCull +#define DCORE0_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_4_BASE 0x403B71Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_5_BASE 0x403B76Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_6_BASE 0x403B7BCull +#define DCORE0_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_7_BASE 0x403B80Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_8_BASE 0x403B85Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_9_BASE 0x403B8ACull +#define DCORE0_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_10_BASE 0x403B8FCull +#define DCORE0_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_11_BASE 0x403B94Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_12_BASE 0x403B99Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_13_BASE 0x403B9ECull +#define DCORE0_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_14_BASE 0x403BA3Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_TENSOR_15_BASE 0x403BA8Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x403BADCull +#define DCORE0_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC3_CFG_QM_BASE 0x403BAE4ull +#define DCORE0_TPC3_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC3_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC3_CFG_AXUSER_BASE 0x403BE00ull +#define DCORE0_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC3_CFG_SPECIAL_BASE 0x403BE80ull +#define DCORE0_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC3_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x403C000ull +#define DCORE0_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x403C200ull +#define DCORE0_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x403C400ull +#define DCORE0_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x403C600ull +#define DCORE0_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_TPC3_MSTR_IF_E2E_CRDT_BASE 0x403C800ull +#define DCORE0_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_TPC3_MSTR_IF_AXUSER_BASE 0x403CA80ull +#define DCORE0_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC3_MSTR_IF_DBG_HBW_BASE 0x403CB00ull +#define DCORE0_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC3_MSTR_IF_DBG_LBW_BASE 0x403CB80ull +#define DCORE0_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_TPC3_MSTR_IF_CORE_HBW_BASE 0x403CC00ull +#define DCORE0_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_TPC3_MSTR_IF_CORE_LBW_BASE 0x403CD80ull +#define DCORE0_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_TPC3_MSTR_IF_SPECIAL_BASE 0x403CE80ull +#define DCORE0_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE0_TPC4_QM_DCCM_BASE 0x4040000ull +#define DCORE0_TPC4_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC4_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_ARC_AUX_BASE 0x4048000ull +#define DCORE0_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE0_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x4048E80ull +#define DCORE0_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC4_QM_BASE 0x404A000ull +#define DCORE0_TPC4_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_QM_SECTION 0x9000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x404A900ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x404A908ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x404A910ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x404A918ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x404A920ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x404A928ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x404A930ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x404A938ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x404A940ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x404A948ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x404A950ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x404A958ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x404A960ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x404A968ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x404A970ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x404A978ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC4_QM_AXUSER_SECURED_BASE 0x404AB00ull +#define DCORE0_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_AXUSER_NONSECURED_BASE 0x404AB80ull +#define DCORE0_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_DBG_HBW_BASE 0x404AC00ull +#define DCORE0_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC4_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC4_QM_DBG_LBW_BASE 0x404AC80ull +#define DCORE0_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC4_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC4_QM_CGM_BASE 0x404AD80ull +#define DCORE0_TPC4_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC4_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC4_QM_SPECIAL_BASE 0x404AE80ull +#define DCORE0_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC4_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x404B000ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC4_CFG_BASE 0x404B000ull +#define DCORE0_TPC4_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_CFG_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x404B050ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x404B0A0ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x404B0F0ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x404B140ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x404B190ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x404B1E0ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x404B230ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x404B280ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x404B2D0ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x404B320ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x404B370ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x404B3C0ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x404B410ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x404B460ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x404B4B0ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x404B500ull +#define DCORE0_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC4_CFG_KERNEL_BASE 0x404B508ull +#define DCORE0_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC4_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_0_BASE 0x404B5DCull +#define DCORE0_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_1_BASE 0x404B62Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_2_BASE 0x404B67Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_3_BASE 0x404B6CCull +#define DCORE0_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_4_BASE 0x404B71Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_5_BASE 0x404B76Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_6_BASE 0x404B7BCull +#define DCORE0_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_7_BASE 0x404B80Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_8_BASE 0x404B85Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_9_BASE 0x404B8ACull +#define DCORE0_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_10_BASE 0x404B8FCull +#define DCORE0_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_11_BASE 0x404B94Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_12_BASE 0x404B99Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_13_BASE 0x404B9ECull +#define DCORE0_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_14_BASE 0x404BA3Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_TENSOR_15_BASE 0x404BA8Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x404BADCull +#define DCORE0_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC4_CFG_QM_BASE 0x404BAE4ull +#define DCORE0_TPC4_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC4_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC4_CFG_AXUSER_BASE 0x404BE00ull +#define DCORE0_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC4_CFG_SPECIAL_BASE 0x404BE80ull +#define DCORE0_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC4_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x404C000ull +#define DCORE0_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x404C200ull +#define DCORE0_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x404C400ull +#define DCORE0_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x404C600ull +#define DCORE0_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_TPC4_MSTR_IF_E2E_CRDT_BASE 0x404C800ull +#define DCORE0_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_TPC4_MSTR_IF_AXUSER_BASE 0x404CA80ull +#define DCORE0_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC4_MSTR_IF_DBG_HBW_BASE 0x404CB00ull +#define DCORE0_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC4_MSTR_IF_DBG_LBW_BASE 0x404CB80ull +#define DCORE0_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_TPC4_MSTR_IF_CORE_HBW_BASE 0x404CC00ull +#define DCORE0_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_TPC4_MSTR_IF_CORE_LBW_BASE 0x404CD80ull +#define DCORE0_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_TPC4_MSTR_IF_SPECIAL_BASE 0x404CE80ull +#define DCORE0_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE0_TPC5_QM_DCCM_BASE 0x4050000ull +#define DCORE0_TPC5_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC5_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_ARC_AUX_BASE 0x4058000ull +#define DCORE0_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE0_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x4058E80ull +#define DCORE0_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC5_QM_BASE 0x405A000ull +#define DCORE0_TPC5_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_QM_SECTION 0x9000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x405A900ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x405A908ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x405A910ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x405A918ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x405A920ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x405A928ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x405A930ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x405A938ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x405A940ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x405A948ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x405A950ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x405A958ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x405A960ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x405A968ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x405A970ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x405A978ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC5_QM_AXUSER_SECURED_BASE 0x405AB00ull +#define DCORE0_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_AXUSER_NONSECURED_BASE 0x405AB80ull +#define DCORE0_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_DBG_HBW_BASE 0x405AC00ull +#define DCORE0_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC5_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC5_QM_DBG_LBW_BASE 0x405AC80ull +#define DCORE0_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC5_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC5_QM_CGM_BASE 0x405AD80ull +#define DCORE0_TPC5_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC5_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC5_QM_SPECIAL_BASE 0x405AE80ull +#define DCORE0_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC5_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x405B000ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC5_CFG_BASE 0x405B000ull +#define DCORE0_TPC5_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_CFG_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x405B050ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x405B0A0ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x405B0F0ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x405B140ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x405B190ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x405B1E0ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x405B230ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x405B280ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x405B2D0ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x405B320ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x405B370ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x405B3C0ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x405B410ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x405B460ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x405B4B0ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x405B500ull +#define DCORE0_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC5_CFG_KERNEL_BASE 0x405B508ull +#define DCORE0_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC5_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_0_BASE 0x405B5DCull +#define DCORE0_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_1_BASE 0x405B62Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_2_BASE 0x405B67Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_3_BASE 0x405B6CCull +#define DCORE0_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_4_BASE 0x405B71Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_5_BASE 0x405B76Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_6_BASE 0x405B7BCull +#define DCORE0_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_7_BASE 0x405B80Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_8_BASE 0x405B85Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_9_BASE 0x405B8ACull +#define DCORE0_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_10_BASE 0x405B8FCull +#define DCORE0_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_11_BASE 0x405B94Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_12_BASE 0x405B99Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_13_BASE 0x405B9ECull +#define DCORE0_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_14_BASE 0x405BA3Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_TENSOR_15_BASE 0x405BA8Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x405BADCull +#define DCORE0_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC5_CFG_QM_BASE 0x405BAE4ull +#define DCORE0_TPC5_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC5_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC5_CFG_AXUSER_BASE 0x405BE00ull +#define DCORE0_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC5_CFG_SPECIAL_BASE 0x405BE80ull +#define DCORE0_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC5_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x405C000ull +#define DCORE0_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x405C200ull +#define DCORE0_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x405C400ull +#define DCORE0_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x405C600ull +#define DCORE0_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_TPC5_MSTR_IF_E2E_CRDT_BASE 0x405C800ull +#define DCORE0_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_TPC5_MSTR_IF_AXUSER_BASE 0x405CA80ull +#define DCORE0_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC5_MSTR_IF_DBG_HBW_BASE 0x405CB00ull +#define DCORE0_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC5_MSTR_IF_DBG_LBW_BASE 0x405CB80ull +#define DCORE0_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_TPC5_MSTR_IF_CORE_HBW_BASE 0x405CC00ull +#define DCORE0_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_TPC5_MSTR_IF_CORE_LBW_BASE 0x405CD80ull +#define DCORE0_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_TPC5_MSTR_IF_SPECIAL_BASE 0x405CE80ull +#define DCORE0_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC5_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE0_TPC6_QM_DCCM_BASE 0x4060000ull +#define DCORE0_TPC6_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC6_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_ARC_AUX_BASE 0x4068000ull +#define DCORE0_TPC6_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE0_TPC6_QM_ARC_AUX_SPECIAL_BASE 0x4068E80ull +#define DCORE0_TPC6_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC6_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TPC6_QM_BASE 0x406A000ull +#define DCORE0_TPC6_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_QM_SECTION 0x9000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR0_BASE 0x406A900ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR1_BASE 0x406A908ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR2_BASE 0x406A910ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR3_BASE 0x406A918ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR4_BASE 0x406A920ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR5_BASE 0x406A928ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR6_BASE 0x406A930ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR7_BASE 0x406A938ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR8_BASE 0x406A940ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR9_BASE 0x406A948ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR10_BASE 0x406A950ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR11_BASE 0x406A958ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR12_BASE 0x406A960ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR13_BASE 0x406A968ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR14_BASE 0x406A970ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR15_BASE 0x406A978ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_TPC6_QM_AXUSER_SECURED_BASE 0x406AB00ull +#define DCORE0_TPC6_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_AXUSER_NONSECURED_BASE 0x406AB80ull +#define DCORE0_TPC6_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_DBG_HBW_BASE 0x406AC00ull +#define DCORE0_TPC6_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC6_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC6_QM_DBG_LBW_BASE 0x406AC80ull +#define DCORE0_TPC6_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC6_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_TPC6_QM_CGM_BASE 0x406AD80ull +#define DCORE0_TPC6_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC6_QM_CGM_SECTION 0x1000 +#define mmDCORE0_TPC6_QM_SPECIAL_BASE 0x406AE80ull +#define DCORE0_TPC6_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC6_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_0_BASE 0x406B000ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC6_CFG_BASE 0x406B000ull +#define DCORE0_TPC6_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_CFG_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_1_BASE 0x406B050ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_2_BASE 0x406B0A0ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_3_BASE 0x406B0F0ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_4_BASE 0x406B140ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_5_BASE 0x406B190ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_6_BASE 0x406B1E0ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_7_BASE 0x406B230ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_8_BASE 0x406B280ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_9_BASE 0x406B2D0ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_10_BASE 0x406B320ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_11_BASE 0x406B370ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_12_BASE 0x406B3C0ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_13_BASE 0x406B410ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_14_BASE 0x406B460ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_15_BASE 0x406B4B0ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_KERNEL_SYNC_OBJECT_BASE 0x406B500ull +#define DCORE0_TPC6_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC6_CFG_KERNEL_BASE 0x406B508ull +#define DCORE0_TPC6_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC6_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_0_BASE 0x406B5DCull +#define DCORE0_TPC6_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_1_BASE 0x406B62Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_2_BASE 0x406B67Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_3_BASE 0x406B6CCull +#define DCORE0_TPC6_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_4_BASE 0x406B71Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_5_BASE 0x406B76Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_6_BASE 0x406B7BCull +#define DCORE0_TPC6_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_7_BASE 0x406B80Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_8_BASE 0x406B85Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_9_BASE 0x406B8ACull +#define DCORE0_TPC6_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_10_BASE 0x406B8FCull +#define DCORE0_TPC6_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_11_BASE 0x406B94Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_12_BASE 0x406B99Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_13_BASE 0x406B9ECull +#define DCORE0_TPC6_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_14_BASE 0x406BA3Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_TENSOR_15_BASE 0x406BA8Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE0_TPC6_CFG_QM_SYNC_OBJECT_BASE 0x406BADCull +#define DCORE0_TPC6_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE0_TPC6_CFG_QM_BASE 0x406BAE4ull +#define DCORE0_TPC6_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC6_CFG_QM_SECTION 0x31C0 +#define mmDCORE0_TPC6_CFG_AXUSER_BASE 0x406BE00ull +#define DCORE0_TPC6_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC6_CFG_SPECIAL_BASE 0x406BE80ull +#define DCORE0_TPC6_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC6_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC6_MSTR_IF_RR_SHRD_HBW_BASE 0x406C000ull +#define DCORE0_TPC6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_TPC6_MSTR_IF_RR_PRVT_HBW_BASE 0x406C200ull +#define DCORE0_TPC6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_TPC6_MSTR_IF_RR_SHRD_LBW_BASE 0x406C400ull +#define DCORE0_TPC6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_TPC6_MSTR_IF_RR_PRVT_LBW_BASE 0x406C600ull +#define DCORE0_TPC6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_TPC6_MSTR_IF_E2E_CRDT_BASE 0x406C800ull +#define DCORE0_TPC6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_TPC6_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_TPC6_MSTR_IF_AXUSER_BASE 0x406CA80ull +#define DCORE0_TPC6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_TPC6_MSTR_IF_DBG_HBW_BASE 0x406CB00ull +#define DCORE0_TPC6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC6_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_TPC6_MSTR_IF_DBG_LBW_BASE 0x406CB80ull +#define DCORE0_TPC6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC6_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_TPC6_MSTR_IF_CORE_HBW_BASE 0x406CC00ull +#define DCORE0_TPC6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_TPC6_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_TPC6_MSTR_IF_CORE_LBW_BASE 0x406CD80ull +#define DCORE0_TPC6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_TPC6_MSTR_IF_SPECIAL_BASE 0x406CE80ull +#define DCORE0_TPC6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC6_MSTR_IF_SPECIAL_SECTION 0x13180 +#define mmDCORE0_HMMU0_MMU_BASE 0x4080000ull +#define DCORE0_HMMU0_MMU_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_MMU_SECTION 0xE800 +#define mmDCORE0_HMMU0_MMU_SPECIAL_BASE 0x4080E80ull +#define DCORE0_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU0_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE0_HMMU0_STLB_BASE 0x4081000ull +#define DCORE0_HMMU0_STLB_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_STLB_SECTION 0xE800 +#define mmDCORE0_HMMU0_STLB_SPECIAL_BASE 0x4081E80ull +#define DCORE0_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU0_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE0_HMMU0_SCRAMB_OUT_BASE 0x4083000ull +#define DCORE0_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE0_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x4083E80ull +#define DCORE0_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x4084000ull +#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x4084200ull +#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x4084400ull +#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x4084600ull +#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x4084800ull +#define DCORE0_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_HMMU0_MSTR_IF_AXUSER_BASE 0x4084A80ull +#define DCORE0_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_HMMU0_MSTR_IF_DBG_HBW_BASE 0x4084B00ull +#define DCORE0_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_HMMU0_MSTR_IF_DBG_LBW_BASE 0x4084B80ull +#define DCORE0_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_HMMU0_MSTR_IF_CORE_HBW_BASE 0x4084C00ull +#define DCORE0_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_HMMU0_MSTR_IF_CORE_LBW_BASE 0x4084D80ull +#define DCORE0_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_HMMU0_MSTR_IF_SPECIAL_BASE 0x4084E80ull +#define DCORE0_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE0_HMMU1_MMU_BASE 0x4090000ull +#define DCORE0_HMMU1_MMU_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_MMU_SECTION 0xE800 +#define mmDCORE0_HMMU1_MMU_SPECIAL_BASE 0x4090E80ull +#define DCORE0_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU1_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE0_HMMU1_STLB_BASE 0x4091000ull +#define DCORE0_HMMU1_STLB_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_STLB_SECTION 0xE800 +#define mmDCORE0_HMMU1_STLB_SPECIAL_BASE 0x4091E80ull +#define DCORE0_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU1_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE0_HMMU1_SCRAMB_OUT_BASE 0x4093000ull +#define DCORE0_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE0_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x4093E80ull +#define DCORE0_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE0_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x4094000ull +#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x4094200ull +#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x4094400ull +#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x4094600ull +#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x4094800ull +#define DCORE0_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_HMMU1_MSTR_IF_AXUSER_BASE 0x4094A80ull +#define DCORE0_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_HMMU1_MSTR_IF_DBG_HBW_BASE 0x4094B00ull +#define DCORE0_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_HMMU1_MSTR_IF_DBG_LBW_BASE 0x4094B80ull +#define DCORE0_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_HMMU1_MSTR_IF_CORE_HBW_BASE 0x4094C00ull +#define DCORE0_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_HMMU1_MSTR_IF_CORE_LBW_BASE 0x4094D80ull +#define DCORE0_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_HMMU1_MSTR_IF_SPECIAL_BASE 0x4094E80ull +#define DCORE0_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE0_HMMU2_MMU_BASE 0x40A0000ull +#define DCORE0_HMMU2_MMU_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_MMU_SECTION 0xE800 +#define mmDCORE0_HMMU2_MMU_SPECIAL_BASE 0x40A0E80ull +#define DCORE0_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU2_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE0_HMMU2_STLB_BASE 0x40A1000ull +#define DCORE0_HMMU2_STLB_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_STLB_SECTION 0xE800 +#define mmDCORE0_HMMU2_STLB_SPECIAL_BASE 0x40A1E80ull +#define DCORE0_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU2_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE0_HMMU2_SCRAMB_OUT_BASE 0x40A3000ull +#define DCORE0_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE0_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x40A3E80ull +#define DCORE0_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE0_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x40A4000ull +#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x40A4200ull +#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x40A4400ull +#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x40A4600ull +#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x40A4800ull +#define DCORE0_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_HMMU2_MSTR_IF_AXUSER_BASE 0x40A4A80ull +#define DCORE0_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_HMMU2_MSTR_IF_DBG_HBW_BASE 0x40A4B00ull +#define DCORE0_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_HMMU2_MSTR_IF_DBG_LBW_BASE 0x40A4B80ull +#define DCORE0_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_HMMU2_MSTR_IF_CORE_HBW_BASE 0x40A4C00ull +#define DCORE0_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_HMMU2_MSTR_IF_CORE_LBW_BASE 0x40A4D80ull +#define DCORE0_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_HMMU2_MSTR_IF_SPECIAL_BASE 0x40A4E80ull +#define DCORE0_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE0_HMMU3_MMU_BASE 0x40B0000ull +#define DCORE0_HMMU3_MMU_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_MMU_SECTION 0xE800 +#define mmDCORE0_HMMU3_MMU_SPECIAL_BASE 0x40B0E80ull +#define DCORE0_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU3_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE0_HMMU3_STLB_BASE 0x40B1000ull +#define DCORE0_HMMU3_STLB_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_STLB_SECTION 0xE800 +#define mmDCORE0_HMMU3_STLB_SPECIAL_BASE 0x40B1E80ull +#define DCORE0_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU3_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE0_HMMU3_SCRAMB_OUT_BASE 0x40B3000ull +#define DCORE0_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE0_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x40B3E80ull +#define DCORE0_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE0_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x40B4000ull +#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x40B4200ull +#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x40B4400ull +#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x40B4600ull +#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x40B4800ull +#define DCORE0_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_HMMU3_MSTR_IF_AXUSER_BASE 0x40B4A80ull +#define DCORE0_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_HMMU3_MSTR_IF_DBG_HBW_BASE 0x40B4B00ull +#define DCORE0_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_HMMU3_MSTR_IF_DBG_LBW_BASE 0x40B4B80ull +#define DCORE0_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_HMMU3_MSTR_IF_CORE_HBW_BASE 0x40B4C00ull +#define DCORE0_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_HMMU3_MSTR_IF_CORE_LBW_BASE 0x40B4D80ull +#define DCORE0_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_HMMU3_MSTR_IF_SPECIAL_BASE 0x40B4E80ull +#define DCORE0_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE0_MME_QM_ARC_DCCM_BASE 0x40C0000ull +#define DCORE0_MME_QM_ARC_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_MME_QM_ARC_DCCM_SECTION 0x8000 +#define mmDCORE0_MME_QM_ARC_AUX_BASE 0x40C8000ull +#define DCORE0_MME_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_MME_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE0_MME_QM_ARC_AUX_SPECIAL_BASE 0x40C8E80ull +#define DCORE0_MME_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_QM_ARC_AUX_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_QM_ARC_DUP_ENG_BASE 0x40C9000ull +#define DCORE0_MME_QM_ARC_DUP_ENG_MAX_OFFSET 0x1000 +#define DCORE0_MME_QM_ARC_DUP_ENG_SECTION 0x9000 +#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_BASE 0x40C9900ull +#define DCORE0_MME_QM_ARC_DUP_ENG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_MME_QM_ARC_DUP_ENG_AXUSER_SECTION 0x5800 +#define mmDCORE0_MME_QM_ARC_DUP_ENG_SPECIAL_BASE 0x40C9E80ull +#define DCORE0_MME_QM_ARC_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_QM_ARC_DUP_ENG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_QM_BASE 0x40CA000ull +#define DCORE0_MME_QM_MAX_OFFSET 0x1000 +#define DCORE0_MME_QM_SECTION 0x9000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE 0x40CA900ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE 0x40CA908ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE 0x40CA910ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE 0x40CA918ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE 0x40CA920ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE 0x40CA928ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE 0x40CA930ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE 0x40CA938ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE 0x40CA940ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE 0x40CA948ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE 0x40CA950ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE 0x40CA958ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE 0x40CA960ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE 0x40CA968ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE 0x40CA970ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE 0x40CA978ull +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_MME_QM_AXUSER_SECURED_BASE 0x40CAB00ull +#define DCORE0_MME_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_MME_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_MME_QM_AXUSER_NONSECURED_BASE 0x40CAB80ull +#define DCORE0_MME_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_MME_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_MME_QM_DBG_HBW_BASE 0x40CAC00ull +#define DCORE0_MME_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_MME_QM_DBG_LBW_BASE 0x40CAC80ull +#define DCORE0_MME_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_MME_QM_CGM_BASE 0x40CAD80ull +#define DCORE0_MME_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_MME_QM_CGM_SECTION 0x1000 +#define mmDCORE0_MME_QM_SPECIAL_BASE 0x40CAE80ull +#define DCORE0_MME_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_LO_BASE 0x40CB000ull +#define DCORE0_MME_CTRL_LO_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_LO_SECTION 0x8000 +#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_BASE 0x40CB008ull +#define DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_SECTION 0x2000 +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE 0x40CB028ull +#define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_BASE 0x40CB040ull +#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SECTION 0x5800 +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_BASE 0x40CB098ull +#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SECTION 0x5800 +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE 0x40CB0F0ull +#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE 0x40CB15Cull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE 0x40CB170ull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE 0x40CB184ull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE 0x40CB198ull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE 0x40CB1ACull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE 0x40CB1C0ull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE 0x40CB1D4ull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE 0x40CB1E8ull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE 0x40CB1FCull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE 0x40CB210ull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE 0x40CB22Cull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE 0x40CB240ull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE 0x40CB254ull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE 0x40CB268ull +#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE 0x40CB280ull +#define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SECTION 0xB800 +#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_BASE 0x40CBE00ull +#define DCORE0_MME_CTRL_LO_MME_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_MME_CTRL_LO_MME_AXUSER_SECTION 0x8000 +#define mmDCORE0_MME_CTRL_LO_SPECIAL_BASE 0x40CBE80ull +#define DCORE0_MME_CTRL_LO_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_CTRL_LO_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_HI_BASE 0x40CC000ull +#define DCORE0_MME_CTRL_HI_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_HI_SECTION 0x8000 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_BASE_ADDR_BASE 0x40CC008ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE0_MME_CTRL_HI_SHADOW_0_BASE_ADDR_SECTION 0x2000 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_BASE 0x40CC028ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_A_BASE 0x40CC040ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_A_SECTION 0x5800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_B_BASE 0x40CC098ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_B_SECTION 0x5800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_BASE 0x40CC0F0ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_BASE 0x40CC15Cull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_BASE 0x40CC170ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_BASE 0x40CC184ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_BASE 0x40CC198ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_BASE 0x40CC1ACull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_BASE 0x40CC1C0ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_BASE 0x40CC1D4ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_BASE 0x40CC1E8ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_BASE 0x40CC1FCull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_BASE 0x40CC210ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_BASE 0x40CC22Cull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_BASE 0x40CC240ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_BASE 0x40CC254ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_BASE 0x40CC268ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_BASE 0x40CC280ull +#define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_SECTION 0x8800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_BASE_ADDR_BASE 0x40CC308ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE0_MME_CTRL_HI_SHADOW_1_BASE_ADDR_SECTION 0x2000 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_BASE 0x40CC328ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_A_BASE 0x40CC340ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_A_SECTION 0x5800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_B_BASE 0x40CC398ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_B_SECTION 0x5800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_BASE 0x40CC3F0ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_BASE 0x40CC45Cull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_BASE 0x40CC470ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_BASE 0x40CC484ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_BASE 0x40CC498ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_BASE 0x40CC4ACull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_BASE 0x40CC4C0ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_BASE 0x40CC4D4ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_BASE 0x40CC4E8ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_BASE 0x40CC4FCull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_BASE 0x40CC510ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_BASE 0x40CC52Cull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_BASE 0x40CC540ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_BASE 0x40CC554ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_BASE 0x40CC568ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_BASE 0x40CC580ull +#define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_SECTION 0x8800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_BASE_ADDR_BASE 0x40CC608ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE0_MME_CTRL_HI_SHADOW_2_BASE_ADDR_SECTION 0x2000 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_BASE 0x40CC628ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_A_BASE 0x40CC640ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_A_SECTION 0x5800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_B_BASE 0x40CC698ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_B_SECTION 0x5800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_BASE 0x40CC6F0ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_BASE 0x40CC75Cull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_BASE 0x40CC770ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_BASE 0x40CC784ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_BASE 0x40CC798ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_BASE 0x40CC7ACull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_BASE 0x40CC7C0ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_BASE 0x40CC7D4ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_BASE 0x40CC7E8ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_BASE 0x40CC7FCull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_BASE 0x40CC810ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_BASE 0x40CC82Cull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_BASE 0x40CC840ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_BASE 0x40CC854ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_BASE 0x40CC868ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_BASE 0x40CC880ull +#define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_SECTION 0x8800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_BASE_ADDR_BASE 0x40CC908ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE0_MME_CTRL_HI_SHADOW_3_BASE_ADDR_SECTION 0x2000 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_BASE 0x40CC928ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_A_BASE 0x40CC940ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_A_SECTION 0x5800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_B_BASE 0x40CC998ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_B_SECTION 0x5800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_BASE 0x40CC9F0ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_BASE 0x40CCA5Cull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_BASE 0x40CCA70ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_BASE 0x40CCA84ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_BASE 0x40CCA98ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_BASE 0x40CCAACull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_BASE 0x40CCAC0ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_BASE 0x40CCAD4ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_BASE 0x40CCAE8ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_BASE 0x40CCAFCull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_BASE 0x40CCB10ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_BASE 0x40CCB2Cull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_BASE 0x40CCB40ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_BASE 0x40CCB54ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_BASE 0x40CCB68ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_BASE 0x40CCB80ull +#define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_SECTION 0x3000 +#define mmDCORE0_MME_CTRL_HI_SPECIAL_BASE 0x40CCE80ull +#define DCORE0_MME_CTRL_HI_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_CTRL_HI_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_EU_BIST_BASE 0x40CD000ull +#define DCORE0_MME_EU_BIST_MAX_OFFSET 0x1000 +#define DCORE0_MME_EU_BIST_SECTION 0xE800 +#define mmDCORE0_MME_EU_BIST_SPECIAL_BASE 0x40CDE80ull +#define DCORE0_MME_EU_BIST_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_EU_BIST_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE 0x40CE000ull +#define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_MME_CTRL_MSTR_IF_RR_PRVT_HBW_BASE 0x40CE200ull +#define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_MME_CTRL_MSTR_IF_RR_SHRD_LBW_BASE 0x40CE400ull +#define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_MME_CTRL_MSTR_IF_RR_PRVT_LBW_BASE 0x40CE600ull +#define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_MME_CTRL_MSTR_IF_E2E_CRDT_BASE 0x40CE800ull +#define DCORE0_MME_CTRL_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_MME_CTRL_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_MME_CTRL_MSTR_IF_AXUSER_BASE 0x40CEA80ull +#define DCORE0_MME_CTRL_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_MME_CTRL_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_MME_CTRL_MSTR_IF_DBG_HBW_BASE 0x40CEB00ull +#define DCORE0_MME_CTRL_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_MME_CTRL_MSTR_IF_DBG_LBW_BASE 0x40CEB80ull +#define DCORE0_MME_CTRL_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_CTRL_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_MME_CTRL_MSTR_IF_CORE_HBW_BASE 0x40CEC00ull +#define DCORE0_MME_CTRL_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_MME_CTRL_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_MME_CTRL_MSTR_IF_CORE_LBW_BASE 0x40CED80ull +#define DCORE0_MME_CTRL_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_MME_CTRL_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_MME_CTRL_MSTR_IF_SPECIAL_BASE 0x40CEE80ull +#define DCORE0_MME_CTRL_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_CTRL_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_QM_ARC_ACP_ENG_BASE 0x40CF000ull +#define DCORE0_MME_QM_ARC_ACP_ENG_MAX_OFFSET 0x1000 +#define DCORE0_MME_QM_ARC_ACP_ENG_SECTION 0xE800 +#define mmDCORE0_MME_QM_ARC_ACP_ENG_SPECIAL_BASE 0x40CFE80ull +#define DCORE0_MME_QM_ARC_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_QM_ARC_ACP_ENG_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_SBTE0_BASE 0x40D0000ull +#define DCORE0_MME_SBTE0_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE0_SECTION 0xE800 +#define mmDCORE0_MME_SBTE0_SPECIAL_BASE 0x40D0E80ull +#define DCORE0_MME_SBTE0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_SBTE0_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE 0x40D1000ull +#define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_BASE 0x40D1200ull +#define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_BASE 0x40D1400ull +#define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_BASE 0x40D1600ull +#define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE0_MSTR_IF_E2E_CRDT_BASE 0x40D1800ull +#define DCORE0_MME_SBTE0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_MME_SBTE0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_BASE 0x40D1A80ull +#define DCORE0_MME_SBTE0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_MME_SBTE0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_MME_SBTE0_MSTR_IF_DBG_HBW_BASE 0x40D1B00ull +#define DCORE0_MME_SBTE0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_SBTE0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_MME_SBTE0_MSTR_IF_DBG_LBW_BASE 0x40D1B80ull +#define DCORE0_MME_SBTE0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_SBTE0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_MME_SBTE0_MSTR_IF_CORE_HBW_BASE 0x40D1C00ull +#define DCORE0_MME_SBTE0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_MME_SBTE0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_MME_SBTE0_MSTR_IF_CORE_LBW_BASE 0x40D1D80ull +#define DCORE0_MME_SBTE0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_MME_SBTE0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_MME_SBTE0_MSTR_IF_SPECIAL_BASE 0x40D1E80ull +#define DCORE0_MME_SBTE0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_SBTE0_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE0_MME_SBTE1_BASE 0x40D8000ull +#define DCORE0_MME_SBTE1_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE1_SECTION 0xE800 +#define mmDCORE0_MME_SBTE1_SPECIAL_BASE 0x40D8E80ull +#define DCORE0_MME_SBTE1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_SBTE1_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE 0x40D9000ull +#define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_BASE 0x40D9200ull +#define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_BASE 0x40D9400ull +#define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_BASE 0x40D9600ull +#define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE1_MSTR_IF_E2E_CRDT_BASE 0x40D9800ull +#define DCORE0_MME_SBTE1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_MME_SBTE1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_MME_SBTE1_MSTR_IF_AXUSER_BASE 0x40D9A80ull +#define DCORE0_MME_SBTE1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_MME_SBTE1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_MME_SBTE1_MSTR_IF_DBG_HBW_BASE 0x40D9B00ull +#define DCORE0_MME_SBTE1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_SBTE1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_MME_SBTE1_MSTR_IF_DBG_LBW_BASE 0x40D9B80ull +#define DCORE0_MME_SBTE1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_SBTE1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_MME_SBTE1_MSTR_IF_CORE_HBW_BASE 0x40D9C00ull +#define DCORE0_MME_SBTE1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_MME_SBTE1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_MME_SBTE1_MSTR_IF_CORE_LBW_BASE 0x40D9D80ull +#define DCORE0_MME_SBTE1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_MME_SBTE1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_MME_SBTE1_MSTR_IF_SPECIAL_BASE 0x40D9E80ull +#define DCORE0_MME_SBTE1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_SBTE1_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE0_MME_SBTE2_BASE 0x40E0000ull +#define DCORE0_MME_SBTE2_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE2_SECTION 0xE800 +#define mmDCORE0_MME_SBTE2_SPECIAL_BASE 0x40E0E80ull +#define DCORE0_MME_SBTE2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_SBTE2_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_BASE 0x40E1000ull +#define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_BASE 0x40E1200ull +#define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_BASE 0x40E1400ull +#define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_BASE 0x40E1600ull +#define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE2_MSTR_IF_E2E_CRDT_BASE 0x40E1800ull +#define DCORE0_MME_SBTE2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_MME_SBTE2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_MME_SBTE2_MSTR_IF_AXUSER_BASE 0x40E1A80ull +#define DCORE0_MME_SBTE2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_MME_SBTE2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_MME_SBTE2_MSTR_IF_DBG_HBW_BASE 0x40E1B00ull +#define DCORE0_MME_SBTE2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_SBTE2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_MME_SBTE2_MSTR_IF_DBG_LBW_BASE 0x40E1B80ull +#define DCORE0_MME_SBTE2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_SBTE2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_MME_SBTE2_MSTR_IF_CORE_HBW_BASE 0x40E1C00ull +#define DCORE0_MME_SBTE2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_MME_SBTE2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_MME_SBTE2_MSTR_IF_CORE_LBW_BASE 0x40E1D80ull +#define DCORE0_MME_SBTE2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_MME_SBTE2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_MME_SBTE2_MSTR_IF_SPECIAL_BASE 0x40E1E80ull +#define DCORE0_MME_SBTE2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_SBTE2_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE0_MME_SBTE3_BASE 0x40E8000ull +#define DCORE0_MME_SBTE3_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE3_SECTION 0xE800 +#define mmDCORE0_MME_SBTE3_SPECIAL_BASE 0x40E8E80ull +#define DCORE0_MME_SBTE3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_SBTE3_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_BASE 0x40E9000ull +#define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_BASE 0x40E9200ull +#define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_BASE 0x40E9400ull +#define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_BASE 0x40E9600ull +#define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE3_MSTR_IF_E2E_CRDT_BASE 0x40E9800ull +#define DCORE0_MME_SBTE3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_MME_SBTE3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_MME_SBTE3_MSTR_IF_AXUSER_BASE 0x40E9A80ull +#define DCORE0_MME_SBTE3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_MME_SBTE3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_MME_SBTE3_MSTR_IF_DBG_HBW_BASE 0x40E9B00ull +#define DCORE0_MME_SBTE3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_SBTE3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_MME_SBTE3_MSTR_IF_DBG_LBW_BASE 0x40E9B80ull +#define DCORE0_MME_SBTE3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_SBTE3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_MME_SBTE3_MSTR_IF_CORE_HBW_BASE 0x40E9C00ull +#define DCORE0_MME_SBTE3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_MME_SBTE3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_MME_SBTE3_MSTR_IF_CORE_LBW_BASE 0x40E9D80ull +#define DCORE0_MME_SBTE3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_MME_SBTE3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_MME_SBTE3_MSTR_IF_SPECIAL_BASE 0x40E9E80ull +#define DCORE0_MME_SBTE3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_SBTE3_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE0_MME_SBTE4_BASE 0x40F0000ull +#define DCORE0_MME_SBTE4_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE4_SECTION 0xE800 +#define mmDCORE0_MME_SBTE4_SPECIAL_BASE 0x40F0E80ull +#define DCORE0_MME_SBTE4_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_SBTE4_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_BASE 0x40F1000ull +#define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_BASE 0x40F1200ull +#define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_BASE 0x40F1400ull +#define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_BASE 0x40F1600ull +#define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_MME_SBTE4_MSTR_IF_E2E_CRDT_BASE 0x40F1800ull +#define DCORE0_MME_SBTE4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_MME_SBTE4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_MME_SBTE4_MSTR_IF_AXUSER_BASE 0x40F1A80ull +#define DCORE0_MME_SBTE4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_MME_SBTE4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_MME_SBTE4_MSTR_IF_DBG_HBW_BASE 0x40F1B00ull +#define DCORE0_MME_SBTE4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_SBTE4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_MME_SBTE4_MSTR_IF_DBG_LBW_BASE 0x40F1B80ull +#define DCORE0_MME_SBTE4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_SBTE4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_MME_SBTE4_MSTR_IF_CORE_HBW_BASE 0x40F1C00ull +#define DCORE0_MME_SBTE4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_MME_SBTE4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_MME_SBTE4_MSTR_IF_CORE_LBW_BASE 0x40F1D80ull +#define DCORE0_MME_SBTE4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_MME_SBTE4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_MME_SBTE4_MSTR_IF_SPECIAL_BASE 0x40F1E80ull +#define DCORE0_MME_SBTE4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_SBTE4_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE0_MME_ACC_BASE 0x40F8000ull +#define DCORE0_MME_ACC_MAX_OFFSET 0x1000 +#define DCORE0_MME_ACC_SECTION 0xE800 +#define mmDCORE0_MME_ACC_SPECIAL_BASE 0x40F8E80ull +#define DCORE0_MME_ACC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_ACC_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE 0x40F9000ull +#define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_MME_WB0_MSTR_IF_RR_PRVT_HBW_BASE 0x40F9200ull +#define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_LBW_BASE 0x40F9400ull +#define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_MME_WB0_MSTR_IF_RR_PRVT_LBW_BASE 0x40F9600ull +#define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_MME_WB0_MSTR_IF_E2E_CRDT_BASE 0x40F9800ull +#define DCORE0_MME_WB0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_MME_WB0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_BASE 0x40F9A80ull +#define DCORE0_MME_WB0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_MME_WB0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_MME_WB0_MSTR_IF_DBG_HBW_BASE 0x40F9B00ull +#define DCORE0_MME_WB0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_WB0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_MME_WB0_MSTR_IF_DBG_LBW_BASE 0x40F9B80ull +#define DCORE0_MME_WB0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_WB0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_MME_WB0_MSTR_IF_CORE_HBW_BASE 0x40F9C00ull +#define DCORE0_MME_WB0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_MME_WB0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_MME_WB0_MSTR_IF_CORE_LBW_BASE 0x40F9D80ull +#define DCORE0_MME_WB0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_MME_WB0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_MME_WB0_MSTR_IF_SPECIAL_BASE 0x40F9E80ull +#define DCORE0_MME_WB0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_WB0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE 0x40FA000ull +#define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_MME_WB1_MSTR_IF_RR_PRVT_HBW_BASE 0x40FA200ull +#define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_LBW_BASE 0x40FA400ull +#define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_MME_WB1_MSTR_IF_RR_PRVT_LBW_BASE 0x40FA600ull +#define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_MME_WB1_MSTR_IF_E2E_CRDT_BASE 0x40FA800ull +#define DCORE0_MME_WB1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_MME_WB1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_MME_WB1_MSTR_IF_AXUSER_BASE 0x40FAA80ull +#define DCORE0_MME_WB1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_MME_WB1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_MME_WB1_MSTR_IF_DBG_HBW_BASE 0x40FAB00ull +#define DCORE0_MME_WB1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_WB1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_MME_WB1_MSTR_IF_DBG_LBW_BASE 0x40FAB80ull +#define DCORE0_MME_WB1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_MME_WB1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_MME_WB1_MSTR_IF_CORE_HBW_BASE 0x40FAC00ull +#define DCORE0_MME_WB1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_MME_WB1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_MME_WB1_MSTR_IF_CORE_LBW_BASE 0x40FAD80ull +#define DCORE0_MME_WB1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_MME_WB1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_MME_WB1_MSTR_IF_SPECIAL_BASE 0x40FAE80ull +#define DCORE0_MME_WB1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_MME_WB1_MSTR_IF_SPECIAL_SECTION 0x5180 +#define mmDCORE0_SYNC_MNGR_OBJS_BASE 0x4100000ull +#define DCORE0_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00 +#define DCORE0_SYNC_MNGR_OBJS_SECTION 0x1E000 +#define mmDCORE0_SYNC_MNGR_GLBL_BASE 0x411E000ull +#define DCORE0_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000 +#define DCORE0_SYNC_MNGR_GLBL_SECTION 0xE800 +#define mmDCORE0_SYNC_MNGR_GLBL_SPECIAL_BASE 0x411EE80ull +#define DCORE0_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x411F000ull +#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x411F200ull +#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x411F400ull +#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x411F600ull +#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x411F800ull +#define DCORE0_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x411FA80ull +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x411FB00ull +#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x411FB80ull +#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x411FC00ull +#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x411FD80ull +#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x411FE80ull +#define DCORE0_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE0_HIF0_BASE 0x4120000ull +#define DCORE0_HIF0_MAX_OFFSET 0x1000 +#define DCORE0_HIF0_SECTION 0xE800 +#define mmDCORE0_HIF0_SPECIAL_BASE 0x4120E80ull +#define DCORE0_HIF0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HIF0_SPECIAL_SECTION 0x3180 +#define mmDCORE0_HIF1_BASE 0x4124000ull +#define DCORE0_HIF1_MAX_OFFSET 0x1000 +#define DCORE0_HIF1_SECTION 0xE800 +#define mmDCORE0_HIF1_SPECIAL_BASE 0x4124E80ull +#define DCORE0_HIF1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HIF1_SPECIAL_SECTION 0x3180 +#define mmDCORE0_HIF2_BASE 0x4128000ull +#define DCORE0_HIF2_MAX_OFFSET 0x1000 +#define DCORE0_HIF2_SECTION 0xE800 +#define mmDCORE0_HIF2_SPECIAL_BASE 0x4128E80ull +#define DCORE0_HIF2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HIF2_SPECIAL_SECTION 0x3180 +#define mmDCORE0_HIF3_BASE 0x412C000ull +#define DCORE0_HIF3_MAX_OFFSET 0x1000 +#define DCORE0_HIF3_SECTION 0xE800 +#define mmDCORE0_HIF3_SPECIAL_BASE 0x412CE80ull +#define DCORE0_HIF3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HIF3_SPECIAL_SECTION 0x13180 +#define mmDCORE0_RTR0_CTRL_BASE 0x4140000ull +#define DCORE0_RTR0_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_RTR0_CTRL_SECTION 0xE800 +#define mmDCORE0_RTR0_CTRL_SPECIAL_BASE 0x4140E80ull +#define DCORE0_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR0_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR0_H3_BASE 0x4141000ull +#define DCORE0_RTR0_H3_MAX_OFFSET 0x1000 +#define DCORE0_RTR0_H3_SECTION 0xE800 +#define mmDCORE0_RTR0_H3_SPECIAL_BASE 0x4141E80ull +#define DCORE0_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR0_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x4142000ull +#define DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x4142200ull +#define DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x4142400ull +#define DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x4142600ull +#define DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_RTR0_MSTR_IF_E2E_CRDT_BASE 0x4142800ull +#define DCORE0_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_RTR0_MSTR_IF_AXUSER_BASE 0x4142A80ull +#define DCORE0_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_RTR0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_RTR0_MSTR_IF_DBG_HBW_BASE 0x4142B00ull +#define DCORE0_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_RTR0_MSTR_IF_DBG_LBW_BASE 0x4142B80ull +#define DCORE0_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_RTR0_MSTR_IF_CORE_HBW_BASE 0x4142C00ull +#define DCORE0_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_RTR0_MSTR_IF_CORE_LBW_BASE 0x4142D80ull +#define DCORE0_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_RTR0_MSTR_IF_SPECIAL_BASE 0x4142E80ull +#define DCORE0_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR0_ADD_DEC_HBW_BASE 0x4143000ull +#define DCORE0_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE0_RTR0_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE0_RTR0_ADD_DEC_LBW_BASE 0x4143400ull +#define DCORE0_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE0_RTR0_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE0_RTR0_ADD_DEC_SPECIAL_BASE 0x4143E80ull +#define DCORE0_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR0_BASE 0x4144000ull +#define DCORE0_RTR0_MAX_OFFSET 0x1000 +#define DCORE0_RTR0_SECTION 0x3000 +#define mmDCORE0_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x4144300ull +#define DCORE0_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR0_HBW_RD_RS_LL_STAT_BASE 0x4144340ull +#define DCORE0_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x4144380ull +#define DCORE0_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR0_HBW_WR_RS_LL_STAT_BASE 0x41443C0ull +#define DCORE0_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x4144400ull +#define DCORE0_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR0_LBW_RD_RS_LL_STAT_BASE 0x4144440ull +#define DCORE0_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x4144480ull +#define DCORE0_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR0_LBW_WR_RS_LL_STAT_BASE 0x41444C0ull +#define DCORE0_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR0_HBW_MFIFO_BASE 0x4144500ull +#define DCORE0_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE0_RTR0_E2E_RD_LL_STAT_BASE 0x4144540ull +#define DCORE0_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR0_E2E_WR_LL_STAT_BASE 0x4144580ull +#define DCORE0_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE0_RTR0_RTR_HBW_XACT_STAT_BASE 0x4144600ull +#define DCORE0_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR0_RTR_LBW_XACT_STAT_BASE 0x4144680ull +#define DCORE0_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR0_RTR_E2E_XACT_STAT_BASE 0x4144700ull +#define DCORE0_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE0_RTR0_SPECIAL_BASE 0x4144E80ull +#define DCORE0_RTR0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR0_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR0_DBG_ADDR_BASE 0x4145000ull +#define DCORE0_RTR0_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE0_RTR0_DBG_ADDR_SECTION 0xE800 +#define mmDCORE0_RTR0_DBG_ADDR_SPECIAL_BASE 0x4145E80ull +#define DCORE0_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE0_RTR1_CTRL_BASE 0x4148000ull +#define DCORE0_RTR1_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_RTR1_CTRL_SECTION 0xE800 +#define mmDCORE0_RTR1_CTRL_SPECIAL_BASE 0x4148E80ull +#define DCORE0_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR1_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR1_H3_BASE 0x4149000ull +#define DCORE0_RTR1_H3_MAX_OFFSET 0x1000 +#define DCORE0_RTR1_H3_SECTION 0xE800 +#define mmDCORE0_RTR1_H3_SPECIAL_BASE 0x4149E80ull +#define DCORE0_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR1_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x414A000ull +#define DCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x414A200ull +#define DCORE0_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x414A400ull +#define DCORE0_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x414A600ull +#define DCORE0_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_RTR1_MSTR_IF_E2E_CRDT_BASE 0x414A800ull +#define DCORE0_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_RTR1_MSTR_IF_AXUSER_BASE 0x414AA80ull +#define DCORE0_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_RTR1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_RTR1_MSTR_IF_DBG_HBW_BASE 0x414AB00ull +#define DCORE0_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_RTR1_MSTR_IF_DBG_LBW_BASE 0x414AB80ull +#define DCORE0_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_RTR1_MSTR_IF_CORE_HBW_BASE 0x414AC00ull +#define DCORE0_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_RTR1_MSTR_IF_CORE_LBW_BASE 0x414AD80ull +#define DCORE0_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_RTR1_MSTR_IF_SPECIAL_BASE 0x414AE80ull +#define DCORE0_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR1_ADD_DEC_HBW_BASE 0x414B000ull +#define DCORE0_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE0_RTR1_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE0_RTR1_ADD_DEC_LBW_BASE 0x414B400ull +#define DCORE0_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE0_RTR1_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE0_RTR1_ADD_DEC_SPECIAL_BASE 0x414BE80ull +#define DCORE0_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR1_BASE 0x414C000ull +#define DCORE0_RTR1_MAX_OFFSET 0x1000 +#define DCORE0_RTR1_SECTION 0x3000 +#define mmDCORE0_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x414C300ull +#define DCORE0_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR1_HBW_RD_RS_LL_STAT_BASE 0x414C340ull +#define DCORE0_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x414C380ull +#define DCORE0_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR1_HBW_WR_RS_LL_STAT_BASE 0x414C3C0ull +#define DCORE0_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x414C400ull +#define DCORE0_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR1_LBW_RD_RS_LL_STAT_BASE 0x414C440ull +#define DCORE0_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x414C480ull +#define DCORE0_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR1_LBW_WR_RS_LL_STAT_BASE 0x414C4C0ull +#define DCORE0_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR1_HBW_MFIFO_BASE 0x414C500ull +#define DCORE0_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE0_RTR1_E2E_RD_LL_STAT_BASE 0x414C540ull +#define DCORE0_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR1_E2E_WR_LL_STAT_BASE 0x414C580ull +#define DCORE0_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE0_RTR1_RTR_HBW_XACT_STAT_BASE 0x414C600ull +#define DCORE0_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR1_RTR_LBW_XACT_STAT_BASE 0x414C680ull +#define DCORE0_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR1_RTR_E2E_XACT_STAT_BASE 0x414C700ull +#define DCORE0_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE0_RTR1_SPECIAL_BASE 0x414CE80ull +#define DCORE0_RTR1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR1_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR1_DBG_ADDR_BASE 0x414D000ull +#define DCORE0_RTR1_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE0_RTR1_DBG_ADDR_SECTION 0xE800 +#define mmDCORE0_RTR1_DBG_ADDR_SPECIAL_BASE 0x414DE80ull +#define DCORE0_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE0_RTR2_CTRL_BASE 0x4150000ull +#define DCORE0_RTR2_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_RTR2_CTRL_SECTION 0xE800 +#define mmDCORE0_RTR2_CTRL_SPECIAL_BASE 0x4150E80ull +#define DCORE0_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR2_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR2_H3_BASE 0x4151000ull +#define DCORE0_RTR2_H3_MAX_OFFSET 0x1000 +#define DCORE0_RTR2_H3_SECTION 0xE800 +#define mmDCORE0_RTR2_H3_SPECIAL_BASE 0x4151E80ull +#define DCORE0_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR2_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x4152000ull +#define DCORE0_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x4152200ull +#define DCORE0_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x4152400ull +#define DCORE0_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x4152600ull +#define DCORE0_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_RTR2_MSTR_IF_E2E_CRDT_BASE 0x4152800ull +#define DCORE0_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_RTR2_MSTR_IF_AXUSER_BASE 0x4152A80ull +#define DCORE0_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_RTR2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_RTR2_MSTR_IF_DBG_HBW_BASE 0x4152B00ull +#define DCORE0_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_RTR2_MSTR_IF_DBG_LBW_BASE 0x4152B80ull +#define DCORE0_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_RTR2_MSTR_IF_CORE_HBW_BASE 0x4152C00ull +#define DCORE0_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_RTR2_MSTR_IF_CORE_LBW_BASE 0x4152D80ull +#define DCORE0_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_RTR2_MSTR_IF_SPECIAL_BASE 0x4152E80ull +#define DCORE0_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR2_ADD_DEC_HBW_BASE 0x4153000ull +#define DCORE0_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE0_RTR2_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE0_RTR2_ADD_DEC_LBW_BASE 0x4153400ull +#define DCORE0_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE0_RTR2_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE0_RTR2_ADD_DEC_SPECIAL_BASE 0x4153E80ull +#define DCORE0_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR2_BASE 0x4154000ull +#define DCORE0_RTR2_MAX_OFFSET 0x1000 +#define DCORE0_RTR2_SECTION 0x3000 +#define mmDCORE0_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x4154300ull +#define DCORE0_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR2_HBW_RD_RS_LL_STAT_BASE 0x4154340ull +#define DCORE0_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x4154380ull +#define DCORE0_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR2_HBW_WR_RS_LL_STAT_BASE 0x41543C0ull +#define DCORE0_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x4154400ull +#define DCORE0_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR2_LBW_RD_RS_LL_STAT_BASE 0x4154440ull +#define DCORE0_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x4154480ull +#define DCORE0_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR2_LBW_WR_RS_LL_STAT_BASE 0x41544C0ull +#define DCORE0_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR2_HBW_MFIFO_BASE 0x4154500ull +#define DCORE0_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE0_RTR2_E2E_RD_LL_STAT_BASE 0x4154540ull +#define DCORE0_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR2_E2E_WR_LL_STAT_BASE 0x4154580ull +#define DCORE0_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE0_RTR2_RTR_HBW_XACT_STAT_BASE 0x4154600ull +#define DCORE0_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR2_RTR_LBW_XACT_STAT_BASE 0x4154680ull +#define DCORE0_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR2_RTR_E2E_XACT_STAT_BASE 0x4154700ull +#define DCORE0_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE0_RTR2_SPECIAL_BASE 0x4154E80ull +#define DCORE0_RTR2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR2_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR2_DBG_ADDR_BASE 0x4155000ull +#define DCORE0_RTR2_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE0_RTR2_DBG_ADDR_SECTION 0xE800 +#define mmDCORE0_RTR2_DBG_ADDR_SPECIAL_BASE 0x4155E80ull +#define DCORE0_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE0_RTR3_CTRL_BASE 0x4158000ull +#define DCORE0_RTR3_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_RTR3_CTRL_SECTION 0xE800 +#define mmDCORE0_RTR3_CTRL_SPECIAL_BASE 0x4158E80ull +#define DCORE0_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR3_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR3_H3_BASE 0x4159000ull +#define DCORE0_RTR3_H3_MAX_OFFSET 0x1000 +#define DCORE0_RTR3_H3_SECTION 0xE800 +#define mmDCORE0_RTR3_H3_SPECIAL_BASE 0x4159E80ull +#define DCORE0_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR3_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x415A000ull +#define DCORE0_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x415A200ull +#define DCORE0_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x415A400ull +#define DCORE0_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x415A600ull +#define DCORE0_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_RTR3_MSTR_IF_E2E_CRDT_BASE 0x415A800ull +#define DCORE0_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_RTR3_MSTR_IF_AXUSER_BASE 0x415AA80ull +#define DCORE0_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_RTR3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_RTR3_MSTR_IF_DBG_HBW_BASE 0x415AB00ull +#define DCORE0_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_RTR3_MSTR_IF_DBG_LBW_BASE 0x415AB80ull +#define DCORE0_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_RTR3_MSTR_IF_CORE_HBW_BASE 0x415AC00ull +#define DCORE0_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_RTR3_MSTR_IF_CORE_LBW_BASE 0x415AD80ull +#define DCORE0_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_RTR3_MSTR_IF_SPECIAL_BASE 0x415AE80ull +#define DCORE0_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR3_ADD_DEC_HBW_BASE 0x415B000ull +#define DCORE0_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE0_RTR3_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE0_RTR3_ADD_DEC_LBW_BASE 0x415B400ull +#define DCORE0_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE0_RTR3_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE0_RTR3_ADD_DEC_SPECIAL_BASE 0x415BE80ull +#define DCORE0_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR3_BASE 0x415C000ull +#define DCORE0_RTR3_MAX_OFFSET 0x1000 +#define DCORE0_RTR3_SECTION 0x3000 +#define mmDCORE0_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x415C300ull +#define DCORE0_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR3_HBW_RD_RS_LL_STAT_BASE 0x415C340ull +#define DCORE0_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x415C380ull +#define DCORE0_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR3_HBW_WR_RS_LL_STAT_BASE 0x415C3C0ull +#define DCORE0_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x415C400ull +#define DCORE0_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR3_LBW_RD_RS_LL_STAT_BASE 0x415C440ull +#define DCORE0_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x415C480ull +#define DCORE0_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR3_LBW_WR_RS_LL_STAT_BASE 0x415C4C0ull +#define DCORE0_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR3_HBW_MFIFO_BASE 0x415C500ull +#define DCORE0_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE0_RTR3_E2E_RD_LL_STAT_BASE 0x415C540ull +#define DCORE0_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR3_E2E_WR_LL_STAT_BASE 0x415C580ull +#define DCORE0_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE0_RTR3_RTR_HBW_XACT_STAT_BASE 0x415C600ull +#define DCORE0_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR3_RTR_LBW_XACT_STAT_BASE 0x415C680ull +#define DCORE0_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR3_RTR_E2E_XACT_STAT_BASE 0x415C700ull +#define DCORE0_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE0_RTR3_SPECIAL_BASE 0x415CE80ull +#define DCORE0_RTR3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR3_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR3_DBG_ADDR_BASE 0x415D000ull +#define DCORE0_RTR3_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE0_RTR3_DBG_ADDR_SECTION 0xE800 +#define mmDCORE0_RTR3_DBG_ADDR_SPECIAL_BASE 0x415DE80ull +#define DCORE0_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE0_RTR4_CTRL_BASE 0x4160000ull +#define DCORE0_RTR4_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_RTR4_CTRL_SECTION 0xE800 +#define mmDCORE0_RTR4_CTRL_SPECIAL_BASE 0x4160E80ull +#define DCORE0_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR4_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR4_H3_BASE 0x4161000ull +#define DCORE0_RTR4_H3_MAX_OFFSET 0x1000 +#define DCORE0_RTR4_H3_SECTION 0xE800 +#define mmDCORE0_RTR4_H3_SPECIAL_BASE 0x4161E80ull +#define DCORE0_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR4_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x4162000ull +#define DCORE0_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x4162200ull +#define DCORE0_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x4162400ull +#define DCORE0_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x4162600ull +#define DCORE0_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_RTR4_MSTR_IF_E2E_CRDT_BASE 0x4162800ull +#define DCORE0_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_RTR4_MSTR_IF_AXUSER_BASE 0x4162A80ull +#define DCORE0_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_RTR4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_RTR4_MSTR_IF_DBG_HBW_BASE 0x4162B00ull +#define DCORE0_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_RTR4_MSTR_IF_DBG_LBW_BASE 0x4162B80ull +#define DCORE0_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_RTR4_MSTR_IF_CORE_HBW_BASE 0x4162C00ull +#define DCORE0_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_RTR4_MSTR_IF_CORE_LBW_BASE 0x4162D80ull +#define DCORE0_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_RTR4_MSTR_IF_SPECIAL_BASE 0x4162E80ull +#define DCORE0_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR4_ADD_DEC_HBW_BASE 0x4163000ull +#define DCORE0_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE0_RTR4_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE0_RTR4_ADD_DEC_LBW_BASE 0x4163400ull +#define DCORE0_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE0_RTR4_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE0_RTR4_ADD_DEC_SPECIAL_BASE 0x4163E80ull +#define DCORE0_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR4_BASE 0x4164000ull +#define DCORE0_RTR4_MAX_OFFSET 0x1000 +#define DCORE0_RTR4_SECTION 0x3000 +#define mmDCORE0_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x4164300ull +#define DCORE0_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR4_HBW_RD_RS_LL_STAT_BASE 0x4164340ull +#define DCORE0_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x4164380ull +#define DCORE0_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR4_HBW_WR_RS_LL_STAT_BASE 0x41643C0ull +#define DCORE0_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x4164400ull +#define DCORE0_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR4_LBW_RD_RS_LL_STAT_BASE 0x4164440ull +#define DCORE0_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x4164480ull +#define DCORE0_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR4_LBW_WR_RS_LL_STAT_BASE 0x41644C0ull +#define DCORE0_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR4_HBW_MFIFO_BASE 0x4164500ull +#define DCORE0_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE0_RTR4_E2E_RD_LL_STAT_BASE 0x4164540ull +#define DCORE0_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR4_E2E_WR_LL_STAT_BASE 0x4164580ull +#define DCORE0_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE0_RTR4_RTR_HBW_XACT_STAT_BASE 0x4164600ull +#define DCORE0_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR4_RTR_LBW_XACT_STAT_BASE 0x4164680ull +#define DCORE0_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR4_RTR_E2E_XACT_STAT_BASE 0x4164700ull +#define DCORE0_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE0_RTR4_SPECIAL_BASE 0x4164E80ull +#define DCORE0_RTR4_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR4_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR4_DBG_ADDR_BASE 0x4165000ull +#define DCORE0_RTR4_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE0_RTR4_DBG_ADDR_SECTION 0xE800 +#define mmDCORE0_RTR4_DBG_ADDR_SPECIAL_BASE 0x4165E80ull +#define DCORE0_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE0_RTR5_CTRL_BASE 0x4168000ull +#define DCORE0_RTR5_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_RTR5_CTRL_SECTION 0xE800 +#define mmDCORE0_RTR5_CTRL_SPECIAL_BASE 0x4168E80ull +#define DCORE0_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR5_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR5_H3_BASE 0x4169000ull +#define DCORE0_RTR5_H3_MAX_OFFSET 0x1000 +#define DCORE0_RTR5_H3_SECTION 0xE800 +#define mmDCORE0_RTR5_H3_SPECIAL_BASE 0x4169E80ull +#define DCORE0_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR5_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x416A000ull +#define DCORE0_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x416A200ull +#define DCORE0_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x416A400ull +#define DCORE0_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x416A600ull +#define DCORE0_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_RTR5_MSTR_IF_E2E_CRDT_BASE 0x416A800ull +#define DCORE0_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_RTR5_MSTR_IF_AXUSER_BASE 0x416AA80ull +#define DCORE0_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_RTR5_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_RTR5_MSTR_IF_DBG_HBW_BASE 0x416AB00ull +#define DCORE0_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_RTR5_MSTR_IF_DBG_LBW_BASE 0x416AB80ull +#define DCORE0_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_RTR5_MSTR_IF_CORE_HBW_BASE 0x416AC00ull +#define DCORE0_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_RTR5_MSTR_IF_CORE_LBW_BASE 0x416AD80ull +#define DCORE0_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_RTR5_MSTR_IF_SPECIAL_BASE 0x416AE80ull +#define DCORE0_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR5_ADD_DEC_HBW_BASE 0x416B000ull +#define DCORE0_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE0_RTR5_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE0_RTR5_ADD_DEC_LBW_BASE 0x416B400ull +#define DCORE0_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE0_RTR5_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE0_RTR5_ADD_DEC_SPECIAL_BASE 0x416BE80ull +#define DCORE0_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR5_BASE 0x416C000ull +#define DCORE0_RTR5_MAX_OFFSET 0x1000 +#define DCORE0_RTR5_SECTION 0x3000 +#define mmDCORE0_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x416C300ull +#define DCORE0_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR5_HBW_RD_RS_LL_STAT_BASE 0x416C340ull +#define DCORE0_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x416C380ull +#define DCORE0_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR5_HBW_WR_RS_LL_STAT_BASE 0x416C3C0ull +#define DCORE0_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x416C400ull +#define DCORE0_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR5_LBW_RD_RS_LL_STAT_BASE 0x416C440ull +#define DCORE0_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x416C480ull +#define DCORE0_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR5_LBW_WR_RS_LL_STAT_BASE 0x416C4C0ull +#define DCORE0_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR5_HBW_MFIFO_BASE 0x416C500ull +#define DCORE0_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE0_RTR5_E2E_RD_LL_STAT_BASE 0x416C540ull +#define DCORE0_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR5_E2E_WR_LL_STAT_BASE 0x416C580ull +#define DCORE0_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE0_RTR5_RTR_HBW_XACT_STAT_BASE 0x416C600ull +#define DCORE0_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR5_RTR_LBW_XACT_STAT_BASE 0x416C680ull +#define DCORE0_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR5_RTR_E2E_XACT_STAT_BASE 0x416C700ull +#define DCORE0_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE0_RTR5_SPECIAL_BASE 0x416CE80ull +#define DCORE0_RTR5_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR5_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR5_DBG_ADDR_BASE 0x416D000ull +#define DCORE0_RTR5_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE0_RTR5_DBG_ADDR_SECTION 0xE800 +#define mmDCORE0_RTR5_DBG_ADDR_SPECIAL_BASE 0x416DE80ull +#define DCORE0_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE0_RTR6_CTRL_BASE 0x4170000ull +#define DCORE0_RTR6_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_RTR6_CTRL_SECTION 0xE800 +#define mmDCORE0_RTR6_CTRL_SPECIAL_BASE 0x4170E80ull +#define DCORE0_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR6_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR6_H3_BASE 0x4171000ull +#define DCORE0_RTR6_H3_MAX_OFFSET 0x1000 +#define DCORE0_RTR6_H3_SECTION 0xE800 +#define mmDCORE0_RTR6_H3_SPECIAL_BASE 0x4171E80ull +#define DCORE0_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR6_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x4172000ull +#define DCORE0_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x4172200ull +#define DCORE0_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x4172400ull +#define DCORE0_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x4172600ull +#define DCORE0_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_RTR6_MSTR_IF_E2E_CRDT_BASE 0x4172800ull +#define DCORE0_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_RTR6_MSTR_IF_AXUSER_BASE 0x4172A80ull +#define DCORE0_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_RTR6_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_RTR6_MSTR_IF_DBG_HBW_BASE 0x4172B00ull +#define DCORE0_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_RTR6_MSTR_IF_DBG_LBW_BASE 0x4172B80ull +#define DCORE0_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_RTR6_MSTR_IF_CORE_HBW_BASE 0x4172C00ull +#define DCORE0_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_RTR6_MSTR_IF_CORE_LBW_BASE 0x4172D80ull +#define DCORE0_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_RTR6_MSTR_IF_SPECIAL_BASE 0x4172E80ull +#define DCORE0_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR6_ADD_DEC_HBW_BASE 0x4173000ull +#define DCORE0_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE0_RTR6_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE0_RTR6_ADD_DEC_LBW_BASE 0x4173400ull +#define DCORE0_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE0_RTR6_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE0_RTR6_ADD_DEC_SPECIAL_BASE 0x4173E80ull +#define DCORE0_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR6_BASE 0x4174000ull +#define DCORE0_RTR6_MAX_OFFSET 0x1000 +#define DCORE0_RTR6_SECTION 0x3000 +#define mmDCORE0_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x4174300ull +#define DCORE0_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR6_HBW_RD_RS_LL_STAT_BASE 0x4174340ull +#define DCORE0_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x4174380ull +#define DCORE0_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR6_HBW_WR_RS_LL_STAT_BASE 0x41743C0ull +#define DCORE0_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x4174400ull +#define DCORE0_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR6_LBW_RD_RS_LL_STAT_BASE 0x4174440ull +#define DCORE0_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x4174480ull +#define DCORE0_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR6_LBW_WR_RS_LL_STAT_BASE 0x41744C0ull +#define DCORE0_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR6_HBW_MFIFO_BASE 0x4174500ull +#define DCORE0_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE0_RTR6_E2E_RD_LL_STAT_BASE 0x4174540ull +#define DCORE0_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR6_E2E_WR_LL_STAT_BASE 0x4174580ull +#define DCORE0_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE0_RTR6_RTR_HBW_XACT_STAT_BASE 0x4174600ull +#define DCORE0_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR6_RTR_LBW_XACT_STAT_BASE 0x4174680ull +#define DCORE0_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR6_RTR_E2E_XACT_STAT_BASE 0x4174700ull +#define DCORE0_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE0_RTR6_SPECIAL_BASE 0x4174E80ull +#define DCORE0_RTR6_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR6_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR6_DBG_ADDR_BASE 0x4175000ull +#define DCORE0_RTR6_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE0_RTR6_DBG_ADDR_SECTION 0xE800 +#define mmDCORE0_RTR6_DBG_ADDR_SPECIAL_BASE 0x4175E80ull +#define DCORE0_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE0_RTR7_CTRL_BASE 0x4178000ull +#define DCORE0_RTR7_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_RTR7_CTRL_SECTION 0xE800 +#define mmDCORE0_RTR7_CTRL_SPECIAL_BASE 0x4178E80ull +#define DCORE0_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR7_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR7_H3_BASE 0x4179000ull +#define DCORE0_RTR7_H3_MAX_OFFSET 0x1000 +#define DCORE0_RTR7_H3_SECTION 0xE800 +#define mmDCORE0_RTR7_H3_SPECIAL_BASE 0x4179E80ull +#define DCORE0_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR7_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x417A000ull +#define DCORE0_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x417A200ull +#define DCORE0_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x417A400ull +#define DCORE0_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x417A600ull +#define DCORE0_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_RTR7_MSTR_IF_E2E_CRDT_BASE 0x417A800ull +#define DCORE0_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_RTR7_MSTR_IF_AXUSER_BASE 0x417AA80ull +#define DCORE0_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_RTR7_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_RTR7_MSTR_IF_DBG_HBW_BASE 0x417AB00ull +#define DCORE0_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_RTR7_MSTR_IF_DBG_LBW_BASE 0x417AB80ull +#define DCORE0_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_RTR7_MSTR_IF_CORE_HBW_BASE 0x417AC00ull +#define DCORE0_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_RTR7_MSTR_IF_CORE_LBW_BASE 0x417AD80ull +#define DCORE0_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_RTR7_MSTR_IF_SPECIAL_BASE 0x417AE80ull +#define DCORE0_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR7_ADD_DEC_HBW_BASE 0x417B000ull +#define DCORE0_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE0_RTR7_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE0_RTR7_ADD_DEC_LBW_BASE 0x417B400ull +#define DCORE0_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE0_RTR7_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE0_RTR7_ADD_DEC_SPECIAL_BASE 0x417BE80ull +#define DCORE0_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR7_BASE 0x417C000ull +#define DCORE0_RTR7_MAX_OFFSET 0x1000 +#define DCORE0_RTR7_SECTION 0x3000 +#define mmDCORE0_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x417C300ull +#define DCORE0_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR7_HBW_RD_RS_LL_STAT_BASE 0x417C340ull +#define DCORE0_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x417C380ull +#define DCORE0_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR7_HBW_WR_RS_LL_STAT_BASE 0x417C3C0ull +#define DCORE0_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x417C400ull +#define DCORE0_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR7_LBW_RD_RS_LL_STAT_BASE 0x417C440ull +#define DCORE0_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x417C480ull +#define DCORE0_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR7_LBW_WR_RS_LL_STAT_BASE 0x417C4C0ull +#define DCORE0_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR7_HBW_MFIFO_BASE 0x417C500ull +#define DCORE0_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE0_RTR7_E2E_RD_LL_STAT_BASE 0x417C540ull +#define DCORE0_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE0_RTR7_E2E_WR_LL_STAT_BASE 0x417C580ull +#define DCORE0_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE0_RTR7_RTR_HBW_XACT_STAT_BASE 0x417C600ull +#define DCORE0_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR7_RTR_LBW_XACT_STAT_BASE 0x417C680ull +#define DCORE0_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE0_RTR7_RTR_E2E_XACT_STAT_BASE 0x417C700ull +#define DCORE0_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE0_RTR7_SPECIAL_BASE 0x417CE80ull +#define DCORE0_RTR7_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR7_SPECIAL_SECTION 0x1800 +#define mmDCORE0_RTR7_DBG_ADDR_BASE 0x417D000ull +#define DCORE0_RTR7_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE0_RTR7_DBG_ADDR_SECTION 0xE800 +#define mmDCORE0_RTR7_DBG_ADDR_SPECIAL_BASE 0x417DE80ull +#define DCORE0_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE0_SRAM0_BANK_BASE 0x4180000ull +#define DCORE0_SRAM0_BANK_MAX_OFFSET 0x1000 +#define DCORE0_SRAM0_BANK_SECTION 0xE800 +#define mmDCORE0_SRAM0_BANK_SPECIAL_BASE 0x4180E80ull +#define DCORE0_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM0_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM0_RTR_BASE 0x4181000ull +#define DCORE0_SRAM0_RTR_MAX_OFFSET 0x1000 +#define DCORE0_SRAM0_RTR_SECTION 0xE800 +#define mmDCORE0_SRAM0_RTR_SPECIAL_BASE 0x4181E80ull +#define DCORE0_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM0_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4182000ull +#define DCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4182100ull +#define DCORE0_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4182200ull +#define DCORE0_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4182300ull +#define DCORE0_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4182400ull +#define DCORE0_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4182500ull +#define DCORE0_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4182600ull +#define DCORE0_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4182700ull +#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4182780ull +#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4182800ull +#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4182880ull +#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4182900ull +#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4182980ull +#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4182A00ull +#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4182A80ull +#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE0_SRAM0_DBG_CNT_SPECIAL_BASE 0x4182E80ull +#define DCORE0_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE0_SRAM1_BANK_BASE 0x4188000ull +#define DCORE0_SRAM1_BANK_MAX_OFFSET 0x1000 +#define DCORE0_SRAM1_BANK_SECTION 0xE800 +#define mmDCORE0_SRAM1_BANK_SPECIAL_BASE 0x4188E80ull +#define DCORE0_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM1_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM1_RTR_BASE 0x4189000ull +#define DCORE0_SRAM1_RTR_MAX_OFFSET 0x1000 +#define DCORE0_SRAM1_RTR_SECTION 0xE800 +#define mmDCORE0_SRAM1_RTR_SPECIAL_BASE 0x4189E80ull +#define DCORE0_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM1_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x418A000ull +#define DCORE0_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x418A100ull +#define DCORE0_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x418A200ull +#define DCORE0_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x418A300ull +#define DCORE0_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x418A400ull +#define DCORE0_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x418A500ull +#define DCORE0_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x418A600ull +#define DCORE0_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x418A700ull +#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x418A780ull +#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x418A800ull +#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x418A880ull +#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x418A900ull +#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x418A980ull +#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x418AA00ull +#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x418AA80ull +#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE0_SRAM1_DBG_CNT_SPECIAL_BASE 0x418AE80ull +#define DCORE0_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE0_SRAM2_BANK_BASE 0x4190000ull +#define DCORE0_SRAM2_BANK_MAX_OFFSET 0x1000 +#define DCORE0_SRAM2_BANK_SECTION 0xE800 +#define mmDCORE0_SRAM2_BANK_SPECIAL_BASE 0x4190E80ull +#define DCORE0_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM2_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM2_RTR_BASE 0x4191000ull +#define DCORE0_SRAM2_RTR_MAX_OFFSET 0x1000 +#define DCORE0_SRAM2_RTR_SECTION 0xE800 +#define mmDCORE0_SRAM2_RTR_SPECIAL_BASE 0x4191E80ull +#define DCORE0_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM2_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4192000ull +#define DCORE0_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4192100ull +#define DCORE0_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4192200ull +#define DCORE0_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4192300ull +#define DCORE0_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4192400ull +#define DCORE0_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4192500ull +#define DCORE0_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4192600ull +#define DCORE0_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4192700ull +#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4192780ull +#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4192800ull +#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4192880ull +#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4192900ull +#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4192980ull +#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4192A00ull +#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4192A80ull +#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE0_SRAM2_DBG_CNT_SPECIAL_BASE 0x4192E80ull +#define DCORE0_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE0_SRAM3_BANK_BASE 0x4198000ull +#define DCORE0_SRAM3_BANK_MAX_OFFSET 0x1000 +#define DCORE0_SRAM3_BANK_SECTION 0xE800 +#define mmDCORE0_SRAM3_BANK_SPECIAL_BASE 0x4198E80ull +#define DCORE0_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM3_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM3_RTR_BASE 0x4199000ull +#define DCORE0_SRAM3_RTR_MAX_OFFSET 0x1000 +#define DCORE0_SRAM3_RTR_SECTION 0xE800 +#define mmDCORE0_SRAM3_RTR_SPECIAL_BASE 0x4199E80ull +#define DCORE0_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM3_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x419A000ull +#define DCORE0_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x419A100ull +#define DCORE0_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x419A200ull +#define DCORE0_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x419A300ull +#define DCORE0_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x419A400ull +#define DCORE0_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x419A500ull +#define DCORE0_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x419A600ull +#define DCORE0_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x419A700ull +#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x419A780ull +#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x419A800ull +#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x419A880ull +#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x419A900ull +#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x419A980ull +#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x419AA00ull +#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x419AA80ull +#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE0_SRAM3_DBG_CNT_SPECIAL_BASE 0x419AE80ull +#define DCORE0_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE0_SRAM4_BANK_BASE 0x41A0000ull +#define DCORE0_SRAM4_BANK_MAX_OFFSET 0x1000 +#define DCORE0_SRAM4_BANK_SECTION 0xE800 +#define mmDCORE0_SRAM4_BANK_SPECIAL_BASE 0x41A0E80ull +#define DCORE0_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM4_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM4_RTR_BASE 0x41A1000ull +#define DCORE0_SRAM4_RTR_MAX_OFFSET 0x1000 +#define DCORE0_SRAM4_RTR_SECTION 0xE800 +#define mmDCORE0_SRAM4_RTR_SPECIAL_BASE 0x41A1E80ull +#define DCORE0_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM4_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x41A2000ull +#define DCORE0_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x41A2100ull +#define DCORE0_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x41A2200ull +#define DCORE0_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x41A2300ull +#define DCORE0_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x41A2400ull +#define DCORE0_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x41A2500ull +#define DCORE0_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x41A2600ull +#define DCORE0_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x41A2700ull +#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x41A2780ull +#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x41A2800ull +#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x41A2880ull +#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x41A2900ull +#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x41A2980ull +#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x41A2A00ull +#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x41A2A80ull +#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE0_SRAM4_DBG_CNT_SPECIAL_BASE 0x41A2E80ull +#define DCORE0_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE0_SRAM5_BANK_BASE 0x41A8000ull +#define DCORE0_SRAM5_BANK_MAX_OFFSET 0x1000 +#define DCORE0_SRAM5_BANK_SECTION 0xE800 +#define mmDCORE0_SRAM5_BANK_SPECIAL_BASE 0x41A8E80ull +#define DCORE0_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM5_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM5_RTR_BASE 0x41A9000ull +#define DCORE0_SRAM5_RTR_MAX_OFFSET 0x1000 +#define DCORE0_SRAM5_RTR_SECTION 0xE800 +#define mmDCORE0_SRAM5_RTR_SPECIAL_BASE 0x41A9E80ull +#define DCORE0_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM5_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x41AA000ull +#define DCORE0_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x41AA100ull +#define DCORE0_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x41AA200ull +#define DCORE0_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x41AA300ull +#define DCORE0_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x41AA400ull +#define DCORE0_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x41AA500ull +#define DCORE0_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x41AA600ull +#define DCORE0_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x41AA700ull +#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x41AA780ull +#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x41AA800ull +#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x41AA880ull +#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x41AA900ull +#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x41AA980ull +#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x41AAA00ull +#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x41AAA80ull +#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE0_SRAM5_DBG_CNT_SPECIAL_BASE 0x41AAE80ull +#define DCORE0_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE0_SRAM6_BANK_BASE 0x41B0000ull +#define DCORE0_SRAM6_BANK_MAX_OFFSET 0x1000 +#define DCORE0_SRAM6_BANK_SECTION 0xE800 +#define mmDCORE0_SRAM6_BANK_SPECIAL_BASE 0x41B0E80ull +#define DCORE0_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM6_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM6_RTR_BASE 0x41B1000ull +#define DCORE0_SRAM6_RTR_MAX_OFFSET 0x1000 +#define DCORE0_SRAM6_RTR_SECTION 0xE800 +#define mmDCORE0_SRAM6_RTR_SPECIAL_BASE 0x41B1E80ull +#define DCORE0_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM6_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x41B2000ull +#define DCORE0_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x41B2100ull +#define DCORE0_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x41B2200ull +#define DCORE0_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x41B2300ull +#define DCORE0_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x41B2400ull +#define DCORE0_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x41B2500ull +#define DCORE0_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x41B2600ull +#define DCORE0_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x41B2700ull +#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x41B2780ull +#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x41B2800ull +#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x41B2880ull +#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x41B2900ull +#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x41B2980ull +#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x41B2A00ull +#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x41B2A80ull +#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE0_SRAM6_DBG_CNT_SPECIAL_BASE 0x41B2E80ull +#define DCORE0_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE0_SRAM7_BANK_BASE 0x41B8000ull +#define DCORE0_SRAM7_BANK_MAX_OFFSET 0x1000 +#define DCORE0_SRAM7_BANK_SECTION 0xE800 +#define mmDCORE0_SRAM7_BANK_SPECIAL_BASE 0x41B8E80ull +#define DCORE0_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM7_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM7_RTR_BASE 0x41B9000ull +#define DCORE0_SRAM7_RTR_MAX_OFFSET 0x1000 +#define DCORE0_SRAM7_RTR_SECTION 0xE800 +#define mmDCORE0_SRAM7_RTR_SPECIAL_BASE 0x41B9E80ull +#define DCORE0_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM7_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE0_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x41BA000ull +#define DCORE0_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x41BA100ull +#define DCORE0_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x41BA200ull +#define DCORE0_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x41BA300ull +#define DCORE0_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x41BA400ull +#define DCORE0_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x41BA500ull +#define DCORE0_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x41BA600ull +#define DCORE0_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE0_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x41BA700ull +#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x41BA780ull +#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x41BA800ull +#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x41BA880ull +#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x41BA900ull +#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x41BA980ull +#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x41BAA00ull +#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE0_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x41BAA80ull +#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE0_SRAM7_DBG_CNT_SPECIAL_BASE 0x41BAE80ull +#define DCORE0_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE0_EDMA0_QM_DCCM_BASE 0x41C0000ull +#define DCORE0_EDMA0_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_EDMA0_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_ARC_AUX_BASE 0x41C8000ull +#define DCORE0_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE0_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x41C8E80ull +#define DCORE0_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_EDMA0_QM_BASE 0x41CA000ull +#define DCORE0_EDMA0_QM_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_QM_SECTION 0x9000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x41CA900ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x41CA908ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x41CA910ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x41CA918ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x41CA920ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x41CA928ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x41CA930ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x41CA938ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x41CA940ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x41CA948ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x41CA950ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x41CA958ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x41CA960ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x41CA968ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x41CA970ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x41CA978ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_EDMA0_QM_AXUSER_SECURED_BASE 0x41CAB00ull +#define DCORE0_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_BASE 0x41CAB80ull +#define DCORE0_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_DBG_HBW_BASE 0x41CAC00ull +#define DCORE0_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_EDMA0_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_EDMA0_QM_DBG_LBW_BASE 0x41CAC80ull +#define DCORE0_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_EDMA0_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_EDMA0_QM_CGM_BASE 0x41CAD80ull +#define DCORE0_EDMA0_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_EDMA0_QM_CGM_SECTION 0x1000 +#define mmDCORE0_EDMA0_QM_SPECIAL_BASE 0x41CAE80ull +#define DCORE0_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_EDMA0_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_EDMA0_CORE_BASE 0x41CB000ull +#define DCORE0_EDMA0_CORE_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_CORE_SECTION 0x8000 +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_BASE 0x41CB800ull +#define DCORE0_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000 +#define mmDCORE0_EDMA0_CORE_CTX_BASE 0x41CB860ull +#define DCORE0_EDMA0_CORE_CTX_MAX_OFFSET 0x9000 +#define DCORE0_EDMA0_CORE_CTX_SECTION 0x5A00 +#define mmDCORE0_EDMA0_CORE_KDMA_CGM_BASE 0x41CBE00ull +#define DCORE0_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define DCORE0_EDMA0_CORE_KDMA_CGM_SECTION 0x8000 +#define mmDCORE0_EDMA0_CORE_SPECIAL_BASE 0x41CBE80ull +#define DCORE0_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_EDMA0_CORE_SPECIAL_SECTION 0x1800 +#define mmDCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x41CC000ull +#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x41CC200ull +#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x41CC400ull +#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x41CC600ull +#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x41CC800ull +#define DCORE0_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_EDMA0_MSTR_IF_AXUSER_BASE 0x41CCA80ull +#define DCORE0_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_EDMA0_MSTR_IF_DBG_HBW_BASE 0x41CCB00ull +#define DCORE0_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_EDMA0_MSTR_IF_DBG_LBW_BASE 0x41CCB80ull +#define DCORE0_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_EDMA0_MSTR_IF_CORE_HBW_BASE 0x41CCC00ull +#define DCORE0_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_EDMA0_MSTR_IF_CORE_LBW_BASE 0x41CCD80ull +#define DCORE0_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_EDMA0_MSTR_IF_SPECIAL_BASE 0x41CCE80ull +#define DCORE0_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE0_EDMA1_QM_DCCM_BASE 0x41D0000ull +#define DCORE0_EDMA1_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_EDMA1_QM_DCCM_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_ARC_AUX_BASE 0x41D8000ull +#define DCORE0_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE0_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x41D8E80ull +#define DCORE0_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE0_EDMA1_QM_BASE 0x41DA000ull +#define DCORE0_EDMA1_QM_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_QM_SECTION 0x9000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x41DA900ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x41DA908ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x41DA910ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x41DA918ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x41DA920ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x41DA928ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x41DA930ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x41DA938ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x41DA940ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x41DA948ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x41DA950ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x41DA958ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x41DA960ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x41DA968ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x41DA970ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x41DA978ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE0_EDMA1_QM_AXUSER_SECURED_BASE 0x41DAB00ull +#define DCORE0_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_BASE 0x41DAB80ull +#define DCORE0_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_DBG_HBW_BASE 0x41DAC00ull +#define DCORE0_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_EDMA1_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_EDMA1_QM_DBG_LBW_BASE 0x41DAC80ull +#define DCORE0_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_EDMA1_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE0_EDMA1_QM_CGM_BASE 0x41DAD80ull +#define DCORE0_EDMA1_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_EDMA1_QM_CGM_SECTION 0x1000 +#define mmDCORE0_EDMA1_QM_SPECIAL_BASE 0x41DAE80ull +#define DCORE0_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_EDMA1_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE0_EDMA1_CORE_BASE 0x41DB000ull +#define DCORE0_EDMA1_CORE_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_CORE_SECTION 0x8000 +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_BASE 0x41DB800ull +#define DCORE0_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000 +#define mmDCORE0_EDMA1_CORE_CTX_BASE 0x41DB860ull +#define DCORE0_EDMA1_CORE_CTX_MAX_OFFSET 0x9000 +#define DCORE0_EDMA1_CORE_CTX_SECTION 0x5A00 +#define mmDCORE0_EDMA1_CORE_KDMA_CGM_BASE 0x41DBE00ull +#define DCORE0_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define DCORE0_EDMA1_CORE_KDMA_CGM_SECTION 0x8000 +#define mmDCORE0_EDMA1_CORE_SPECIAL_BASE 0x41DBE80ull +#define DCORE0_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_EDMA1_CORE_SPECIAL_SECTION 0x1800 +#define mmDCORE0_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x41DC000ull +#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x41DC200ull +#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x41DC400ull +#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x41DC600ull +#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x41DC800ull +#define DCORE0_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_EDMA1_MSTR_IF_AXUSER_BASE 0x41DCA80ull +#define DCORE0_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_EDMA1_MSTR_IF_DBG_HBW_BASE 0x41DCB00ull +#define DCORE0_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_EDMA1_MSTR_IF_DBG_LBW_BASE 0x41DCB80ull +#define DCORE0_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_EDMA1_MSTR_IF_CORE_HBW_BASE 0x41DCC00ull +#define DCORE0_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_EDMA1_MSTR_IF_CORE_LBW_BASE 0x41DCD80ull +#define DCORE0_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_EDMA1_MSTR_IF_SPECIAL_BASE 0x41DCE80ull +#define DCORE0_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE0_DEC0_CMD_BASE 0x41E0000ull +#define DCORE0_DEC0_CMD_MAX_OFFSET 0x1100 +#define DCORE0_DEC0_CMD_SECTION 0x1000 +#define mmDCORE0_DEC0_VSI_BASE 0x41E1000ull +#define DCORE0_DEC0_VSI_MAX_OFFSET 0x6FC0 +#define DCORE0_DEC0_VSI_SECTION 0x1000 +#define mmDCORE0_DEC0_L2C_BASE 0x41E2000ull +#define DCORE0_DEC0_L2C_MAX_OFFSET 0x39C0 +#define DCORE0_DEC0_L2C_SECTION 0x1000 +#define mmDCORE0_VDEC0_BRDG_CTRL_BASE 0x41E3000ull +#define DCORE0_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_BRDG_CTRL_SECTION 0x8000 +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x41E3800ull +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x41E3900ull +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x41E3A00ull +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x41E3B00ull +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x41E3C00ull +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 +#define mmDCORE0_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x41E3E80ull +#define DCORE0_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_VDEC0_CTRL_BASE 0x41E4000ull +#define DCORE0_VDEC0_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_CTRL_SECTION 0xE800 +#define mmDCORE0_VDEC0_CTRL_SPECIAL_BASE 0x41E4E80ull +#define DCORE0_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_VDEC0_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x41E5000ull +#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x41E5200ull +#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x41E5400ull +#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x41E5600ull +#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x41E5800ull +#define DCORE0_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_VDEC0_MSTR_IF_AXUSER_BASE 0x41E5A80ull +#define DCORE0_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_VDEC0_MSTR_IF_DBG_HBW_BASE 0x41E5B00ull +#define DCORE0_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_VDEC0_MSTR_IF_DBG_LBW_BASE 0x41E5B80ull +#define DCORE0_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_VDEC0_MSTR_IF_CORE_HBW_BASE 0x41E5C00ull +#define DCORE0_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_VDEC0_MSTR_IF_CORE_LBW_BASE 0x41E5D80ull +#define DCORE0_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_VDEC0_MSTR_IF_SPECIAL_BASE 0x41E5E80ull +#define DCORE0_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180 +#define mmDCORE0_DEC1_CMD_BASE 0x41F0000ull +#define DCORE0_DEC1_CMD_MAX_OFFSET 0x1100 +#define DCORE0_DEC1_CMD_SECTION 0x1000 +#define mmDCORE0_DEC1_VSI_BASE 0x41F1000ull +#define DCORE0_DEC1_VSI_MAX_OFFSET 0x6FC0 +#define DCORE0_DEC1_VSI_SECTION 0x1000 +#define mmDCORE0_DEC1_L2C_BASE 0x41F2000ull +#define DCORE0_DEC1_L2C_MAX_OFFSET 0x39C0 +#define DCORE0_DEC1_L2C_SECTION 0x1000 +#define mmDCORE0_VDEC1_BRDG_CTRL_BASE 0x41F3000ull +#define DCORE0_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_BRDG_CTRL_SECTION 0x8000 +#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x41F3800ull +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 +#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x41F3900ull +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 +#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x41F3A00ull +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 +#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x41F3B00ull +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 +#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x41F3C00ull +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 +#define mmDCORE0_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x41F3E80ull +#define DCORE0_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_VDEC1_CTRL_BASE 0x41F4000ull +#define DCORE0_VDEC1_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_CTRL_SECTION 0xE800 +#define mmDCORE0_VDEC1_CTRL_SPECIAL_BASE 0x41F4E80ull +#define DCORE0_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_VDEC1_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x41F5000ull +#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE0_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x41F5200ull +#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE0_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x41F5400ull +#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE0_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x41F5600ull +#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE0_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x41F5800ull +#define DCORE0_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE0_VDEC1_MSTR_IF_AXUSER_BASE 0x41F5A80ull +#define DCORE0_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE0_VDEC1_MSTR_IF_DBG_HBW_BASE 0x41F5B00ull +#define DCORE0_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE0_VDEC1_MSTR_IF_DBG_LBW_BASE 0x41F5B80ull +#define DCORE0_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE0_VDEC1_MSTR_IF_CORE_HBW_BASE 0x41F5C00ull +#define DCORE0_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE0_VDEC1_MSTR_IF_CORE_LBW_BASE 0x41F5D80ull +#define DCORE0_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE0_VDEC1_MSTR_IF_SPECIAL_BASE 0x41F5E80ull +#define DCORE0_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180 +#define mmDCORE1_TPC0_QM_DCCM_BASE 0x4200000ull +#define DCORE1_TPC0_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC0_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_ARC_AUX_BASE 0x4208000ull +#define DCORE1_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE1_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x4208E80ull +#define DCORE1_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TPC0_QM_BASE 0x420A000ull +#define DCORE1_TPC0_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_QM_SECTION 0x9000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x420A900ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x420A908ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x420A910ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x420A918ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x420A920ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x420A928ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x420A930ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x420A938ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x420A940ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x420A948ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x420A950ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x420A958ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x420A960ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x420A968ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x420A970ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x420A978ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_TPC0_QM_AXUSER_SECURED_BASE 0x420AB00ull +#define DCORE1_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_AXUSER_NONSECURED_BASE 0x420AB80ull +#define DCORE1_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_DBG_HBW_BASE 0x420AC00ull +#define DCORE1_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC0_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC0_QM_DBG_LBW_BASE 0x420AC80ull +#define DCORE1_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC0_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_TPC0_QM_CGM_BASE 0x420AD80ull +#define DCORE1_TPC0_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC0_QM_CGM_SECTION 0x1000 +#define mmDCORE1_TPC0_QM_SPECIAL_BASE 0x420AE80ull +#define DCORE1_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC0_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x420B000ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC0_CFG_BASE 0x420B000ull +#define DCORE1_TPC0_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_CFG_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x420B050ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x420B0A0ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x420B0F0ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x420B140ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x420B190ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x420B1E0ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x420B230ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x420B280ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x420B2D0ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x420B320ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x420B370ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x420B3C0ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x420B410ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x420B460ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x420B4B0ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x420B500ull +#define DCORE1_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC0_CFG_KERNEL_BASE 0x420B508ull +#define DCORE1_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC0_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_0_BASE 0x420B5DCull +#define DCORE1_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_1_BASE 0x420B62Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_2_BASE 0x420B67Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_3_BASE 0x420B6CCull +#define DCORE1_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_4_BASE 0x420B71Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_5_BASE 0x420B76Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_6_BASE 0x420B7BCull +#define DCORE1_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_7_BASE 0x420B80Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_8_BASE 0x420B85Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_9_BASE 0x420B8ACull +#define DCORE1_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_10_BASE 0x420B8FCull +#define DCORE1_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_11_BASE 0x420B94Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_12_BASE 0x420B99Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_13_BASE 0x420B9ECull +#define DCORE1_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_14_BASE 0x420BA3Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_TENSOR_15_BASE 0x420BA8Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x420BADCull +#define DCORE1_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC0_CFG_QM_BASE 0x420BAE4ull +#define DCORE1_TPC0_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC0_CFG_QM_SECTION 0x31C0 +#define mmDCORE1_TPC0_CFG_AXUSER_BASE 0x420BE00ull +#define DCORE1_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC0_CFG_SPECIAL_BASE 0x420BE80ull +#define DCORE1_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC0_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x420C000ull +#define DCORE1_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x420C200ull +#define DCORE1_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x420C400ull +#define DCORE1_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x420C600ull +#define DCORE1_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_TPC0_MSTR_IF_E2E_CRDT_BASE 0x420C800ull +#define DCORE1_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_TPC0_MSTR_IF_AXUSER_BASE 0x420CA80ull +#define DCORE1_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC0_MSTR_IF_DBG_HBW_BASE 0x420CB00ull +#define DCORE1_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC0_MSTR_IF_DBG_LBW_BASE 0x420CB80ull +#define DCORE1_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_TPC0_MSTR_IF_CORE_HBW_BASE 0x420CC00ull +#define DCORE1_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_TPC0_MSTR_IF_CORE_LBW_BASE 0x420CD80ull +#define DCORE1_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_TPC0_MSTR_IF_SPECIAL_BASE 0x420CE80ull +#define DCORE1_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE1_TPC1_QM_DCCM_BASE 0x4210000ull +#define DCORE1_TPC1_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC1_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_ARC_AUX_BASE 0x4218000ull +#define DCORE1_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE1_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x4218E80ull +#define DCORE1_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TPC1_QM_BASE 0x421A000ull +#define DCORE1_TPC1_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_QM_SECTION 0x9000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x421A900ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x421A908ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x421A910ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x421A918ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x421A920ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x421A928ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x421A930ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x421A938ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x421A940ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x421A948ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x421A950ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x421A958ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x421A960ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x421A968ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x421A970ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x421A978ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_TPC1_QM_AXUSER_SECURED_BASE 0x421AB00ull +#define DCORE1_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_AXUSER_NONSECURED_BASE 0x421AB80ull +#define DCORE1_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_DBG_HBW_BASE 0x421AC00ull +#define DCORE1_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC1_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC1_QM_DBG_LBW_BASE 0x421AC80ull +#define DCORE1_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC1_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_TPC1_QM_CGM_BASE 0x421AD80ull +#define DCORE1_TPC1_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC1_QM_CGM_SECTION 0x1000 +#define mmDCORE1_TPC1_QM_SPECIAL_BASE 0x421AE80ull +#define DCORE1_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC1_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x421B000ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC1_CFG_BASE 0x421B000ull +#define DCORE1_TPC1_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_CFG_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x421B050ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x421B0A0ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x421B0F0ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x421B140ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x421B190ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x421B1E0ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x421B230ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x421B280ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x421B2D0ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x421B320ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x421B370ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x421B3C0ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x421B410ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x421B460ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x421B4B0ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x421B500ull +#define DCORE1_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC1_CFG_KERNEL_BASE 0x421B508ull +#define DCORE1_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC1_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_0_BASE 0x421B5DCull +#define DCORE1_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_1_BASE 0x421B62Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_2_BASE 0x421B67Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_3_BASE 0x421B6CCull +#define DCORE1_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_4_BASE 0x421B71Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_5_BASE 0x421B76Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_6_BASE 0x421B7BCull +#define DCORE1_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_7_BASE 0x421B80Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_8_BASE 0x421B85Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_9_BASE 0x421B8ACull +#define DCORE1_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_10_BASE 0x421B8FCull +#define DCORE1_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_11_BASE 0x421B94Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_12_BASE 0x421B99Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_13_BASE 0x421B9ECull +#define DCORE1_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_14_BASE 0x421BA3Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_TENSOR_15_BASE 0x421BA8Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x421BADCull +#define DCORE1_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC1_CFG_QM_BASE 0x421BAE4ull +#define DCORE1_TPC1_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC1_CFG_QM_SECTION 0x31C0 +#define mmDCORE1_TPC1_CFG_AXUSER_BASE 0x421BE00ull +#define DCORE1_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC1_CFG_SPECIAL_BASE 0x421BE80ull +#define DCORE1_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC1_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x421C000ull +#define DCORE1_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x421C200ull +#define DCORE1_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x421C400ull +#define DCORE1_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x421C600ull +#define DCORE1_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_TPC1_MSTR_IF_E2E_CRDT_BASE 0x421C800ull +#define DCORE1_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_TPC1_MSTR_IF_AXUSER_BASE 0x421CA80ull +#define DCORE1_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC1_MSTR_IF_DBG_HBW_BASE 0x421CB00ull +#define DCORE1_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC1_MSTR_IF_DBG_LBW_BASE 0x421CB80ull +#define DCORE1_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_TPC1_MSTR_IF_CORE_HBW_BASE 0x421CC00ull +#define DCORE1_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_TPC1_MSTR_IF_CORE_LBW_BASE 0x421CD80ull +#define DCORE1_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_TPC1_MSTR_IF_SPECIAL_BASE 0x421CE80ull +#define DCORE1_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE1_TPC2_QM_DCCM_BASE 0x4220000ull +#define DCORE1_TPC2_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC2_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_ARC_AUX_BASE 0x4228000ull +#define DCORE1_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE1_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x4228E80ull +#define DCORE1_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TPC2_QM_BASE 0x422A000ull +#define DCORE1_TPC2_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_QM_SECTION 0x9000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x422A900ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x422A908ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x422A910ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x422A918ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x422A920ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x422A928ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x422A930ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x422A938ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x422A940ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x422A948ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x422A950ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x422A958ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x422A960ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x422A968ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x422A970ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x422A978ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_TPC2_QM_AXUSER_SECURED_BASE 0x422AB00ull +#define DCORE1_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_AXUSER_NONSECURED_BASE 0x422AB80ull +#define DCORE1_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_DBG_HBW_BASE 0x422AC00ull +#define DCORE1_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC2_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC2_QM_DBG_LBW_BASE 0x422AC80ull +#define DCORE1_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC2_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_TPC2_QM_CGM_BASE 0x422AD80ull +#define DCORE1_TPC2_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC2_QM_CGM_SECTION 0x1000 +#define mmDCORE1_TPC2_QM_SPECIAL_BASE 0x422AE80ull +#define DCORE1_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC2_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x422B000ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC2_CFG_BASE 0x422B000ull +#define DCORE1_TPC2_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_CFG_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x422B050ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x422B0A0ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x422B0F0ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x422B140ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x422B190ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x422B1E0ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x422B230ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x422B280ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x422B2D0ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x422B320ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x422B370ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x422B3C0ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x422B410ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x422B460ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x422B4B0ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x422B500ull +#define DCORE1_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC2_CFG_KERNEL_BASE 0x422B508ull +#define DCORE1_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC2_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_0_BASE 0x422B5DCull +#define DCORE1_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_1_BASE 0x422B62Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_2_BASE 0x422B67Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_3_BASE 0x422B6CCull +#define DCORE1_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_4_BASE 0x422B71Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_5_BASE 0x422B76Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_6_BASE 0x422B7BCull +#define DCORE1_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_7_BASE 0x422B80Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_8_BASE 0x422B85Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_9_BASE 0x422B8ACull +#define DCORE1_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_10_BASE 0x422B8FCull +#define DCORE1_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_11_BASE 0x422B94Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_12_BASE 0x422B99Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_13_BASE 0x422B9ECull +#define DCORE1_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_14_BASE 0x422BA3Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_TENSOR_15_BASE 0x422BA8Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x422BADCull +#define DCORE1_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC2_CFG_QM_BASE 0x422BAE4ull +#define DCORE1_TPC2_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC2_CFG_QM_SECTION 0x31C0 +#define mmDCORE1_TPC2_CFG_AXUSER_BASE 0x422BE00ull +#define DCORE1_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC2_CFG_SPECIAL_BASE 0x422BE80ull +#define DCORE1_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC2_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x422C000ull +#define DCORE1_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x422C200ull +#define DCORE1_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x422C400ull +#define DCORE1_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x422C600ull +#define DCORE1_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_TPC2_MSTR_IF_E2E_CRDT_BASE 0x422C800ull +#define DCORE1_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_TPC2_MSTR_IF_AXUSER_BASE 0x422CA80ull +#define DCORE1_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC2_MSTR_IF_DBG_HBW_BASE 0x422CB00ull +#define DCORE1_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC2_MSTR_IF_DBG_LBW_BASE 0x422CB80ull +#define DCORE1_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_TPC2_MSTR_IF_CORE_HBW_BASE 0x422CC00ull +#define DCORE1_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_TPC2_MSTR_IF_CORE_LBW_BASE 0x422CD80ull +#define DCORE1_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_TPC2_MSTR_IF_SPECIAL_BASE 0x422CE80ull +#define DCORE1_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE1_TPC3_QM_DCCM_BASE 0x4230000ull +#define DCORE1_TPC3_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC3_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_ARC_AUX_BASE 0x4238000ull +#define DCORE1_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE1_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x4238E80ull +#define DCORE1_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TPC3_QM_BASE 0x423A000ull +#define DCORE1_TPC3_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_QM_SECTION 0x9000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x423A900ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x423A908ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x423A910ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x423A918ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x423A920ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x423A928ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x423A930ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x423A938ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x423A940ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x423A948ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x423A950ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x423A958ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x423A960ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x423A968ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x423A970ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x423A978ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_TPC3_QM_AXUSER_SECURED_BASE 0x423AB00ull +#define DCORE1_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_AXUSER_NONSECURED_BASE 0x423AB80ull +#define DCORE1_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_DBG_HBW_BASE 0x423AC00ull +#define DCORE1_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC3_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC3_QM_DBG_LBW_BASE 0x423AC80ull +#define DCORE1_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC3_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_TPC3_QM_CGM_BASE 0x423AD80ull +#define DCORE1_TPC3_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC3_QM_CGM_SECTION 0x1000 +#define mmDCORE1_TPC3_QM_SPECIAL_BASE 0x423AE80ull +#define DCORE1_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC3_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x423B000ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC3_CFG_BASE 0x423B000ull +#define DCORE1_TPC3_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_CFG_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x423B050ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x423B0A0ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x423B0F0ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x423B140ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x423B190ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x423B1E0ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x423B230ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x423B280ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x423B2D0ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x423B320ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x423B370ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x423B3C0ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x423B410ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x423B460ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x423B4B0ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x423B500ull +#define DCORE1_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC3_CFG_KERNEL_BASE 0x423B508ull +#define DCORE1_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC3_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_0_BASE 0x423B5DCull +#define DCORE1_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_1_BASE 0x423B62Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_2_BASE 0x423B67Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_3_BASE 0x423B6CCull +#define DCORE1_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_4_BASE 0x423B71Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_5_BASE 0x423B76Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_6_BASE 0x423B7BCull +#define DCORE1_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_7_BASE 0x423B80Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_8_BASE 0x423B85Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_9_BASE 0x423B8ACull +#define DCORE1_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_10_BASE 0x423B8FCull +#define DCORE1_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_11_BASE 0x423B94Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_12_BASE 0x423B99Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_13_BASE 0x423B9ECull +#define DCORE1_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_14_BASE 0x423BA3Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_TENSOR_15_BASE 0x423BA8Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x423BADCull +#define DCORE1_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC3_CFG_QM_BASE 0x423BAE4ull +#define DCORE1_TPC3_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC3_CFG_QM_SECTION 0x31C0 +#define mmDCORE1_TPC3_CFG_AXUSER_BASE 0x423BE00ull +#define DCORE1_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC3_CFG_SPECIAL_BASE 0x423BE80ull +#define DCORE1_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC3_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x423C000ull +#define DCORE1_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x423C200ull +#define DCORE1_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x423C400ull +#define DCORE1_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x423C600ull +#define DCORE1_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_TPC3_MSTR_IF_E2E_CRDT_BASE 0x423C800ull +#define DCORE1_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_TPC3_MSTR_IF_AXUSER_BASE 0x423CA80ull +#define DCORE1_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC3_MSTR_IF_DBG_HBW_BASE 0x423CB00ull +#define DCORE1_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC3_MSTR_IF_DBG_LBW_BASE 0x423CB80ull +#define DCORE1_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_TPC3_MSTR_IF_CORE_HBW_BASE 0x423CC00ull +#define DCORE1_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_TPC3_MSTR_IF_CORE_LBW_BASE 0x423CD80ull +#define DCORE1_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_TPC3_MSTR_IF_SPECIAL_BASE 0x423CE80ull +#define DCORE1_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE1_TPC4_QM_DCCM_BASE 0x4240000ull +#define DCORE1_TPC4_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC4_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_ARC_AUX_BASE 0x4248000ull +#define DCORE1_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE1_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x4248E80ull +#define DCORE1_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TPC4_QM_BASE 0x424A000ull +#define DCORE1_TPC4_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_QM_SECTION 0x9000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x424A900ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x424A908ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x424A910ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x424A918ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x424A920ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x424A928ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x424A930ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x424A938ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x424A940ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x424A948ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x424A950ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x424A958ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x424A960ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x424A968ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x424A970ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x424A978ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_TPC4_QM_AXUSER_SECURED_BASE 0x424AB00ull +#define DCORE1_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_AXUSER_NONSECURED_BASE 0x424AB80ull +#define DCORE1_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_DBG_HBW_BASE 0x424AC00ull +#define DCORE1_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC4_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC4_QM_DBG_LBW_BASE 0x424AC80ull +#define DCORE1_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC4_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_TPC4_QM_CGM_BASE 0x424AD80ull +#define DCORE1_TPC4_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC4_QM_CGM_SECTION 0x1000 +#define mmDCORE1_TPC4_QM_SPECIAL_BASE 0x424AE80ull +#define DCORE1_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC4_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x424B000ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC4_CFG_BASE 0x424B000ull +#define DCORE1_TPC4_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_CFG_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x424B050ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x424B0A0ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x424B0F0ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x424B140ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x424B190ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x424B1E0ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x424B230ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x424B280ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x424B2D0ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x424B320ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x424B370ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x424B3C0ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x424B410ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x424B460ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x424B4B0ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x424B500ull +#define DCORE1_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC4_CFG_KERNEL_BASE 0x424B508ull +#define DCORE1_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC4_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_0_BASE 0x424B5DCull +#define DCORE1_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_1_BASE 0x424B62Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_2_BASE 0x424B67Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_3_BASE 0x424B6CCull +#define DCORE1_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_4_BASE 0x424B71Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_5_BASE 0x424B76Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_6_BASE 0x424B7BCull +#define DCORE1_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_7_BASE 0x424B80Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_8_BASE 0x424B85Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_9_BASE 0x424B8ACull +#define DCORE1_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_10_BASE 0x424B8FCull +#define DCORE1_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_11_BASE 0x424B94Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_12_BASE 0x424B99Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_13_BASE 0x424B9ECull +#define DCORE1_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_14_BASE 0x424BA3Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_TENSOR_15_BASE 0x424BA8Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x424BADCull +#define DCORE1_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC4_CFG_QM_BASE 0x424BAE4ull +#define DCORE1_TPC4_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC4_CFG_QM_SECTION 0x31C0 +#define mmDCORE1_TPC4_CFG_AXUSER_BASE 0x424BE00ull +#define DCORE1_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC4_CFG_SPECIAL_BASE 0x424BE80ull +#define DCORE1_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC4_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x424C000ull +#define DCORE1_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x424C200ull +#define DCORE1_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x424C400ull +#define DCORE1_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x424C600ull +#define DCORE1_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_TPC4_MSTR_IF_E2E_CRDT_BASE 0x424C800ull +#define DCORE1_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_TPC4_MSTR_IF_AXUSER_BASE 0x424CA80ull +#define DCORE1_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC4_MSTR_IF_DBG_HBW_BASE 0x424CB00ull +#define DCORE1_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC4_MSTR_IF_DBG_LBW_BASE 0x424CB80ull +#define DCORE1_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_TPC4_MSTR_IF_CORE_HBW_BASE 0x424CC00ull +#define DCORE1_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_TPC4_MSTR_IF_CORE_LBW_BASE 0x424CD80ull +#define DCORE1_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_TPC4_MSTR_IF_SPECIAL_BASE 0x424CE80ull +#define DCORE1_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE1_TPC5_QM_DCCM_BASE 0x4250000ull +#define DCORE1_TPC5_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC5_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_ARC_AUX_BASE 0x4258000ull +#define DCORE1_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE1_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x4258E80ull +#define DCORE1_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TPC5_QM_BASE 0x425A000ull +#define DCORE1_TPC5_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_QM_SECTION 0x9000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x425A900ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x425A908ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x425A910ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x425A918ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x425A920ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x425A928ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x425A930ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x425A938ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x425A940ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x425A948ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x425A950ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x425A958ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x425A960ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x425A968ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x425A970ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x425A978ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_TPC5_QM_AXUSER_SECURED_BASE 0x425AB00ull +#define DCORE1_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_AXUSER_NONSECURED_BASE 0x425AB80ull +#define DCORE1_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_DBG_HBW_BASE 0x425AC00ull +#define DCORE1_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC5_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC5_QM_DBG_LBW_BASE 0x425AC80ull +#define DCORE1_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC5_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_TPC5_QM_CGM_BASE 0x425AD80ull +#define DCORE1_TPC5_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC5_QM_CGM_SECTION 0x1000 +#define mmDCORE1_TPC5_QM_SPECIAL_BASE 0x425AE80ull +#define DCORE1_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC5_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x425B000ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC5_CFG_BASE 0x425B000ull +#define DCORE1_TPC5_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_CFG_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x425B050ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x425B0A0ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x425B0F0ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x425B140ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x425B190ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x425B1E0ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x425B230ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x425B280ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x425B2D0ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x425B320ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x425B370ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x425B3C0ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x425B410ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x425B460ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x425B4B0ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x425B500ull +#define DCORE1_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC5_CFG_KERNEL_BASE 0x425B508ull +#define DCORE1_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC5_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_0_BASE 0x425B5DCull +#define DCORE1_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_1_BASE 0x425B62Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_2_BASE 0x425B67Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_3_BASE 0x425B6CCull +#define DCORE1_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_4_BASE 0x425B71Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_5_BASE 0x425B76Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_6_BASE 0x425B7BCull +#define DCORE1_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_7_BASE 0x425B80Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_8_BASE 0x425B85Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_9_BASE 0x425B8ACull +#define DCORE1_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_10_BASE 0x425B8FCull +#define DCORE1_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_11_BASE 0x425B94Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_12_BASE 0x425B99Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_13_BASE 0x425B9ECull +#define DCORE1_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_14_BASE 0x425BA3Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_TENSOR_15_BASE 0x425BA8Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE1_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x425BADCull +#define DCORE1_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE1_TPC5_CFG_QM_BASE 0x425BAE4ull +#define DCORE1_TPC5_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC5_CFG_QM_SECTION 0x31C0 +#define mmDCORE1_TPC5_CFG_AXUSER_BASE 0x425BE00ull +#define DCORE1_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC5_CFG_SPECIAL_BASE 0x425BE80ull +#define DCORE1_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC5_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x425C000ull +#define DCORE1_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x425C200ull +#define DCORE1_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x425C400ull +#define DCORE1_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x425C600ull +#define DCORE1_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_TPC5_MSTR_IF_E2E_CRDT_BASE 0x425C800ull +#define DCORE1_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_TPC5_MSTR_IF_AXUSER_BASE 0x425CA80ull +#define DCORE1_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_TPC5_MSTR_IF_DBG_HBW_BASE 0x425CB00ull +#define DCORE1_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_TPC5_MSTR_IF_DBG_LBW_BASE 0x425CB80ull +#define DCORE1_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_TPC5_MSTR_IF_CORE_HBW_BASE 0x425CC00ull +#define DCORE1_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_TPC5_MSTR_IF_CORE_LBW_BASE 0x425CD80ull +#define DCORE1_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_TPC5_MSTR_IF_SPECIAL_BASE 0x425CE80ull +#define DCORE1_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC5_MSTR_IF_SPECIAL_SECTION 0x23180 +#define mmDCORE1_HMMU0_MMU_BASE 0x4280000ull +#define DCORE1_HMMU0_MMU_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_MMU_SECTION 0xE800 +#define mmDCORE1_HMMU0_MMU_SPECIAL_BASE 0x4280E80ull +#define DCORE1_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU0_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE1_HMMU0_STLB_BASE 0x4281000ull +#define DCORE1_HMMU0_STLB_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_STLB_SECTION 0xE800 +#define mmDCORE1_HMMU0_STLB_SPECIAL_BASE 0x4281E80ull +#define DCORE1_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU0_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE1_HMMU0_SCRAMB_OUT_BASE 0x4283000ull +#define DCORE1_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE1_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x4283E80ull +#define DCORE1_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE1_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x4284000ull +#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x4284200ull +#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x4284400ull +#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x4284600ull +#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x4284800ull +#define DCORE1_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_HMMU0_MSTR_IF_AXUSER_BASE 0x4284A80ull +#define DCORE1_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_HMMU0_MSTR_IF_DBG_HBW_BASE 0x4284B00ull +#define DCORE1_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_HMMU0_MSTR_IF_DBG_LBW_BASE 0x4284B80ull +#define DCORE1_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_HMMU0_MSTR_IF_CORE_HBW_BASE 0x4284C00ull +#define DCORE1_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_HMMU0_MSTR_IF_CORE_LBW_BASE 0x4284D80ull +#define DCORE1_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_HMMU0_MSTR_IF_SPECIAL_BASE 0x4284E80ull +#define DCORE1_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE1_HMMU1_MMU_BASE 0x4290000ull +#define DCORE1_HMMU1_MMU_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_MMU_SECTION 0xE800 +#define mmDCORE1_HMMU1_MMU_SPECIAL_BASE 0x4290E80ull +#define DCORE1_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU1_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE1_HMMU1_STLB_BASE 0x4291000ull +#define DCORE1_HMMU1_STLB_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_STLB_SECTION 0xE800 +#define mmDCORE1_HMMU1_STLB_SPECIAL_BASE 0x4291E80ull +#define DCORE1_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU1_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE1_HMMU1_SCRAMB_OUT_BASE 0x4293000ull +#define DCORE1_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE1_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x4293E80ull +#define DCORE1_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE1_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x4294000ull +#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x4294200ull +#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x4294400ull +#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x4294600ull +#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x4294800ull +#define DCORE1_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_HMMU1_MSTR_IF_AXUSER_BASE 0x4294A80ull +#define DCORE1_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_HMMU1_MSTR_IF_DBG_HBW_BASE 0x4294B00ull +#define DCORE1_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_HMMU1_MSTR_IF_DBG_LBW_BASE 0x4294B80ull +#define DCORE1_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_HMMU1_MSTR_IF_CORE_HBW_BASE 0x4294C00ull +#define DCORE1_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_HMMU1_MSTR_IF_CORE_LBW_BASE 0x4294D80ull +#define DCORE1_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_HMMU1_MSTR_IF_SPECIAL_BASE 0x4294E80ull +#define DCORE1_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE1_HMMU2_MMU_BASE 0x42A0000ull +#define DCORE1_HMMU2_MMU_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_MMU_SECTION 0xE800 +#define mmDCORE1_HMMU2_MMU_SPECIAL_BASE 0x42A0E80ull +#define DCORE1_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU2_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE1_HMMU2_STLB_BASE 0x42A1000ull +#define DCORE1_HMMU2_STLB_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_STLB_SECTION 0xE800 +#define mmDCORE1_HMMU2_STLB_SPECIAL_BASE 0x42A1E80ull +#define DCORE1_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU2_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE1_HMMU2_SCRAMB_OUT_BASE 0x42A3000ull +#define DCORE1_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE1_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x42A3E80ull +#define DCORE1_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE1_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x42A4000ull +#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x42A4200ull +#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x42A4400ull +#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x42A4600ull +#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x42A4800ull +#define DCORE1_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_HMMU2_MSTR_IF_AXUSER_BASE 0x42A4A80ull +#define DCORE1_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_HMMU2_MSTR_IF_DBG_HBW_BASE 0x42A4B00ull +#define DCORE1_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_HMMU2_MSTR_IF_DBG_LBW_BASE 0x42A4B80ull +#define DCORE1_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_HMMU2_MSTR_IF_CORE_HBW_BASE 0x42A4C00ull +#define DCORE1_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_HMMU2_MSTR_IF_CORE_LBW_BASE 0x42A4D80ull +#define DCORE1_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_HMMU2_MSTR_IF_SPECIAL_BASE 0x42A4E80ull +#define DCORE1_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE1_HMMU3_MMU_BASE 0x42B0000ull +#define DCORE1_HMMU3_MMU_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_MMU_SECTION 0xE800 +#define mmDCORE1_HMMU3_MMU_SPECIAL_BASE 0x42B0E80ull +#define DCORE1_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU3_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE1_HMMU3_STLB_BASE 0x42B1000ull +#define DCORE1_HMMU3_STLB_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_STLB_SECTION 0xE800 +#define mmDCORE1_HMMU3_STLB_SPECIAL_BASE 0x42B1E80ull +#define DCORE1_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU3_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE1_HMMU3_SCRAMB_OUT_BASE 0x42B3000ull +#define DCORE1_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE1_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x42B3E80ull +#define DCORE1_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE1_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x42B4000ull +#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x42B4200ull +#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x42B4400ull +#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x42B4600ull +#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x42B4800ull +#define DCORE1_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_HMMU3_MSTR_IF_AXUSER_BASE 0x42B4A80ull +#define DCORE1_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_HMMU3_MSTR_IF_DBG_HBW_BASE 0x42B4B00ull +#define DCORE1_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_HMMU3_MSTR_IF_DBG_LBW_BASE 0x42B4B80ull +#define DCORE1_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_HMMU3_MSTR_IF_CORE_HBW_BASE 0x42B4C00ull +#define DCORE1_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_HMMU3_MSTR_IF_CORE_LBW_BASE 0x42B4D80ull +#define DCORE1_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_HMMU3_MSTR_IF_SPECIAL_BASE 0x42B4E80ull +#define DCORE1_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE1_MME_QM_ARC_DCCM_BASE 0x42C0000ull +#define DCORE1_MME_QM_ARC_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_MME_QM_ARC_DCCM_SECTION 0x8000 +#define mmDCORE1_MME_QM_ARC_AUX_BASE 0x42C8000ull +#define DCORE1_MME_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_MME_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE1_MME_QM_ARC_AUX_SPECIAL_BASE 0x42C8E80ull +#define DCORE1_MME_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_QM_ARC_AUX_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_QM_ARC_DUP_ENG_BASE 0x42C9000ull +#define DCORE1_MME_QM_ARC_DUP_ENG_MAX_OFFSET 0x1000 +#define DCORE1_MME_QM_ARC_DUP_ENG_SECTION 0x9000 +#define mmDCORE1_MME_QM_ARC_DUP_ENG_AXUSER_BASE 0x42C9900ull +#define DCORE1_MME_QM_ARC_DUP_ENG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_MME_QM_ARC_DUP_ENG_AXUSER_SECTION 0x5800 +#define mmDCORE1_MME_QM_ARC_DUP_ENG_SPECIAL_BASE 0x42C9E80ull +#define DCORE1_MME_QM_ARC_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_QM_ARC_DUP_ENG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_QM_BASE 0x42CA000ull +#define DCORE1_MME_QM_MAX_OFFSET 0x1000 +#define DCORE1_MME_QM_SECTION 0x9000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR0_BASE 0x42CA900ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR1_BASE 0x42CA908ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR2_BASE 0x42CA910ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR3_BASE 0x42CA918ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR4_BASE 0x42CA920ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR5_BASE 0x42CA928ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR6_BASE 0x42CA930ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR7_BASE 0x42CA938ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR8_BASE 0x42CA940ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR9_BASE 0x42CA948ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR10_BASE 0x42CA950ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR11_BASE 0x42CA958ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR12_BASE 0x42CA960ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR13_BASE 0x42CA968ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR14_BASE 0x42CA970ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR15_BASE 0x42CA978ull +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_MME_QM_AXUSER_SECURED_BASE 0x42CAB00ull +#define DCORE1_MME_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_MME_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_MME_QM_AXUSER_NONSECURED_BASE 0x42CAB80ull +#define DCORE1_MME_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_MME_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_MME_QM_DBG_HBW_BASE 0x42CAC00ull +#define DCORE1_MME_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_MME_QM_DBG_LBW_BASE 0x42CAC80ull +#define DCORE1_MME_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_MME_QM_CGM_BASE 0x42CAD80ull +#define DCORE1_MME_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_MME_QM_CGM_SECTION 0x1000 +#define mmDCORE1_MME_QM_SPECIAL_BASE 0x42CAE80ull +#define DCORE1_MME_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_LO_BASE 0x42CB000ull +#define DCORE1_MME_CTRL_LO_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_LO_SECTION 0x8000 +#define mmDCORE1_MME_CTRL_LO_ARCH_BASE_ADDR_BASE 0x42CB008ull +#define DCORE1_MME_CTRL_LO_ARCH_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE1_MME_CTRL_LO_ARCH_BASE_ADDR_SECTION 0x2000 +#define mmDCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE 0x42CB028ull +#define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_LO_ARCH_TENSOR_A_BASE 0x42CB040ull +#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_A_SECTION 0x5800 +#define mmDCORE1_MME_CTRL_LO_ARCH_TENSOR_B_BASE 0x42CB098ull +#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_B_SECTION 0x5800 +#define mmDCORE1_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE 0x42CB0F0ull +#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE 0x42CB15Cull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE 0x42CB170ull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE 0x42CB184ull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE 0x42CB198ull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE 0x42CB1ACull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE 0x42CB1C0ull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE 0x42CB1D4ull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE 0x42CB1E8ull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE 0x42CB1FCull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE 0x42CB210ull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE 0x42CB22Cull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE 0x42CB240ull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE 0x42CB254ull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE 0x42CB268ull +#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE 0x42CB280ull +#define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_END_SECTION 0xB800 +#define mmDCORE1_MME_CTRL_LO_MME_AXUSER_BASE 0x42CBE00ull +#define DCORE1_MME_CTRL_LO_MME_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_MME_CTRL_LO_MME_AXUSER_SECTION 0x8000 +#define mmDCORE1_MME_CTRL_LO_SPECIAL_BASE 0x42CBE80ull +#define DCORE1_MME_CTRL_LO_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_CTRL_LO_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_HI_BASE 0x42CC000ull +#define DCORE1_MME_CTRL_HI_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_HI_SECTION 0x8000 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_BASE_ADDR_BASE 0x42CC008ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE1_MME_CTRL_HI_SHADOW_0_BASE_ADDR_SECTION 0x2000 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_BASE 0x42CC028ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_A_BASE 0x42CC040ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_A_SECTION 0x5800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_B_BASE 0x42CC098ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_B_SECTION 0x5800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_BASE 0x42CC0F0ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_BASE 0x42CC15Cull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_BASE 0x42CC170ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_BASE 0x42CC184ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_BASE 0x42CC198ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_BASE 0x42CC1ACull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_BASE 0x42CC1C0ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_BASE 0x42CC1D4ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_BASE 0x42CC1E8ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_BASE 0x42CC1FCull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_BASE 0x42CC210ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_BASE 0x42CC22Cull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_BASE 0x42CC240ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_BASE 0x42CC254ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_BASE 0x42CC268ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_BASE 0x42CC280ull +#define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_SECTION 0x8800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_BASE_ADDR_BASE 0x42CC308ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE1_MME_CTRL_HI_SHADOW_1_BASE_ADDR_SECTION 0x2000 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_BASE 0x42CC328ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_A_BASE 0x42CC340ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_A_SECTION 0x5800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_B_BASE 0x42CC398ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_B_SECTION 0x5800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_BASE 0x42CC3F0ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_BASE 0x42CC45Cull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_BASE 0x42CC470ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_BASE 0x42CC484ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_BASE 0x42CC498ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_BASE 0x42CC4ACull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_BASE 0x42CC4C0ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_BASE 0x42CC4D4ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_BASE 0x42CC4E8ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_BASE 0x42CC4FCull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_BASE 0x42CC510ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_BASE 0x42CC52Cull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_BASE 0x42CC540ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_BASE 0x42CC554ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_BASE 0x42CC568ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_BASE 0x42CC580ull +#define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_SECTION 0x8800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_BASE_ADDR_BASE 0x42CC608ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE1_MME_CTRL_HI_SHADOW_2_BASE_ADDR_SECTION 0x2000 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_BASE 0x42CC628ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_A_BASE 0x42CC640ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_A_SECTION 0x5800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_B_BASE 0x42CC698ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_B_SECTION 0x5800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_BASE 0x42CC6F0ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_BASE 0x42CC75Cull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_BASE 0x42CC770ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_BASE 0x42CC784ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_BASE 0x42CC798ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_BASE 0x42CC7ACull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_BASE 0x42CC7C0ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_BASE 0x42CC7D4ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_BASE 0x42CC7E8ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_BASE 0x42CC7FCull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_BASE 0x42CC810ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_BASE 0x42CC82Cull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_BASE 0x42CC840ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_BASE 0x42CC854ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_BASE 0x42CC868ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_BASE 0x42CC880ull +#define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_SECTION 0x8800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_BASE_ADDR_BASE 0x42CC908ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE1_MME_CTRL_HI_SHADOW_3_BASE_ADDR_SECTION 0x2000 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_BASE 0x42CC928ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_A_BASE 0x42CC940ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_A_SECTION 0x5800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_B_BASE 0x42CC998ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_B_SECTION 0x5800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_BASE 0x42CC9F0ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_BASE 0x42CCA5Cull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_BASE 0x42CCA70ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_BASE 0x42CCA84ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_BASE 0x42CCA98ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_BASE 0x42CCAACull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_BASE 0x42CCAC0ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_BASE 0x42CCAD4ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_BASE 0x42CCAE8ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_BASE 0x42CCAFCull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_BASE 0x42CCB10ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_BASE 0x42CCB2Cull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_BASE 0x42CCB40ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_BASE 0x42CCB54ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_BASE 0x42CCB68ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_BASE 0x42CCB80ull +#define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_SECTION 0x3000 +#define mmDCORE1_MME_CTRL_HI_SPECIAL_BASE 0x42CCE80ull +#define DCORE1_MME_CTRL_HI_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_CTRL_HI_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_EU_BIST_BASE 0x42CD000ull +#define DCORE1_MME_EU_BIST_MAX_OFFSET 0x1000 +#define DCORE1_MME_EU_BIST_SECTION 0xE800 +#define mmDCORE1_MME_EU_BIST_SPECIAL_BASE 0x42CDE80ull +#define DCORE1_MME_EU_BIST_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_EU_BIST_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE 0x42CE000ull +#define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_MME_CTRL_MSTR_IF_RR_PRVT_HBW_BASE 0x42CE200ull +#define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_MME_CTRL_MSTR_IF_RR_SHRD_LBW_BASE 0x42CE400ull +#define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_MME_CTRL_MSTR_IF_RR_PRVT_LBW_BASE 0x42CE600ull +#define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_MME_CTRL_MSTR_IF_E2E_CRDT_BASE 0x42CE800ull +#define DCORE1_MME_CTRL_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_MME_CTRL_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_MME_CTRL_MSTR_IF_AXUSER_BASE 0x42CEA80ull +#define DCORE1_MME_CTRL_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_MME_CTRL_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_MME_CTRL_MSTR_IF_DBG_HBW_BASE 0x42CEB00ull +#define DCORE1_MME_CTRL_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_MME_CTRL_MSTR_IF_DBG_LBW_BASE 0x42CEB80ull +#define DCORE1_MME_CTRL_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_CTRL_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_MME_CTRL_MSTR_IF_CORE_HBW_BASE 0x42CEC00ull +#define DCORE1_MME_CTRL_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_MME_CTRL_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_MME_CTRL_MSTR_IF_CORE_LBW_BASE 0x42CED80ull +#define DCORE1_MME_CTRL_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_MME_CTRL_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_MME_CTRL_MSTR_IF_SPECIAL_BASE 0x42CEE80ull +#define DCORE1_MME_CTRL_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_CTRL_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_QM_ARC_ACP_ENG_BASE 0x42CF000ull +#define DCORE1_MME_QM_ARC_ACP_ENG_MAX_OFFSET 0x1000 +#define DCORE1_MME_QM_ARC_ACP_ENG_SECTION 0xE800 +#define mmDCORE1_MME_QM_ARC_ACP_ENG_SPECIAL_BASE 0x42CFE80ull +#define DCORE1_MME_QM_ARC_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_QM_ARC_ACP_ENG_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_SBTE0_BASE 0x42D0000ull +#define DCORE1_MME_SBTE0_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE0_SECTION 0xE800 +#define mmDCORE1_MME_SBTE0_SPECIAL_BASE 0x42D0E80ull +#define DCORE1_MME_SBTE0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_SBTE0_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE 0x42D1000ull +#define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_BASE 0x42D1200ull +#define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_BASE 0x42D1400ull +#define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_BASE 0x42D1600ull +#define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE0_MSTR_IF_E2E_CRDT_BASE 0x42D1800ull +#define DCORE1_MME_SBTE0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_MME_SBTE0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_MME_SBTE0_MSTR_IF_AXUSER_BASE 0x42D1A80ull +#define DCORE1_MME_SBTE0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_MME_SBTE0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_MME_SBTE0_MSTR_IF_DBG_HBW_BASE 0x42D1B00ull +#define DCORE1_MME_SBTE0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_SBTE0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_MME_SBTE0_MSTR_IF_DBG_LBW_BASE 0x42D1B80ull +#define DCORE1_MME_SBTE0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_SBTE0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_MME_SBTE0_MSTR_IF_CORE_HBW_BASE 0x42D1C00ull +#define DCORE1_MME_SBTE0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_MME_SBTE0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_MME_SBTE0_MSTR_IF_CORE_LBW_BASE 0x42D1D80ull +#define DCORE1_MME_SBTE0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_MME_SBTE0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_MME_SBTE0_MSTR_IF_SPECIAL_BASE 0x42D1E80ull +#define DCORE1_MME_SBTE0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_SBTE0_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE1_MME_SBTE1_BASE 0x42D8000ull +#define DCORE1_MME_SBTE1_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE1_SECTION 0xE800 +#define mmDCORE1_MME_SBTE1_SPECIAL_BASE 0x42D8E80ull +#define DCORE1_MME_SBTE1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_SBTE1_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE 0x42D9000ull +#define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_BASE 0x42D9200ull +#define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_BASE 0x42D9400ull +#define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_BASE 0x42D9600ull +#define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE1_MSTR_IF_E2E_CRDT_BASE 0x42D9800ull +#define DCORE1_MME_SBTE1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_MME_SBTE1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_MME_SBTE1_MSTR_IF_AXUSER_BASE 0x42D9A80ull +#define DCORE1_MME_SBTE1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_MME_SBTE1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_MME_SBTE1_MSTR_IF_DBG_HBW_BASE 0x42D9B00ull +#define DCORE1_MME_SBTE1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_SBTE1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_MME_SBTE1_MSTR_IF_DBG_LBW_BASE 0x42D9B80ull +#define DCORE1_MME_SBTE1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_SBTE1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_MME_SBTE1_MSTR_IF_CORE_HBW_BASE 0x42D9C00ull +#define DCORE1_MME_SBTE1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_MME_SBTE1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_MME_SBTE1_MSTR_IF_CORE_LBW_BASE 0x42D9D80ull +#define DCORE1_MME_SBTE1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_MME_SBTE1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_MME_SBTE1_MSTR_IF_SPECIAL_BASE 0x42D9E80ull +#define DCORE1_MME_SBTE1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_SBTE1_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE1_MME_SBTE2_BASE 0x42E0000ull +#define DCORE1_MME_SBTE2_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE2_SECTION 0xE800 +#define mmDCORE1_MME_SBTE2_SPECIAL_BASE 0x42E0E80ull +#define DCORE1_MME_SBTE2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_SBTE2_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_BASE 0x42E1000ull +#define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_BASE 0x42E1200ull +#define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_BASE 0x42E1400ull +#define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_BASE 0x42E1600ull +#define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE2_MSTR_IF_E2E_CRDT_BASE 0x42E1800ull +#define DCORE1_MME_SBTE2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_MME_SBTE2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_MME_SBTE2_MSTR_IF_AXUSER_BASE 0x42E1A80ull +#define DCORE1_MME_SBTE2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_MME_SBTE2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_MME_SBTE2_MSTR_IF_DBG_HBW_BASE 0x42E1B00ull +#define DCORE1_MME_SBTE2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_SBTE2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_MME_SBTE2_MSTR_IF_DBG_LBW_BASE 0x42E1B80ull +#define DCORE1_MME_SBTE2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_SBTE2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_MME_SBTE2_MSTR_IF_CORE_HBW_BASE 0x42E1C00ull +#define DCORE1_MME_SBTE2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_MME_SBTE2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_MME_SBTE2_MSTR_IF_CORE_LBW_BASE 0x42E1D80ull +#define DCORE1_MME_SBTE2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_MME_SBTE2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_MME_SBTE2_MSTR_IF_SPECIAL_BASE 0x42E1E80ull +#define DCORE1_MME_SBTE2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_SBTE2_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE1_MME_SBTE3_BASE 0x42E8000ull +#define DCORE1_MME_SBTE3_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE3_SECTION 0xE800 +#define mmDCORE1_MME_SBTE3_SPECIAL_BASE 0x42E8E80ull +#define DCORE1_MME_SBTE3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_SBTE3_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_BASE 0x42E9000ull +#define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_BASE 0x42E9200ull +#define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_BASE 0x42E9400ull +#define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_BASE 0x42E9600ull +#define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE3_MSTR_IF_E2E_CRDT_BASE 0x42E9800ull +#define DCORE1_MME_SBTE3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_MME_SBTE3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_MME_SBTE3_MSTR_IF_AXUSER_BASE 0x42E9A80ull +#define DCORE1_MME_SBTE3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_MME_SBTE3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_MME_SBTE3_MSTR_IF_DBG_HBW_BASE 0x42E9B00ull +#define DCORE1_MME_SBTE3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_SBTE3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_MME_SBTE3_MSTR_IF_DBG_LBW_BASE 0x42E9B80ull +#define DCORE1_MME_SBTE3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_SBTE3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_MME_SBTE3_MSTR_IF_CORE_HBW_BASE 0x42E9C00ull +#define DCORE1_MME_SBTE3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_MME_SBTE3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_MME_SBTE3_MSTR_IF_CORE_LBW_BASE 0x42E9D80ull +#define DCORE1_MME_SBTE3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_MME_SBTE3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_MME_SBTE3_MSTR_IF_SPECIAL_BASE 0x42E9E80ull +#define DCORE1_MME_SBTE3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_SBTE3_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE1_MME_SBTE4_BASE 0x42F0000ull +#define DCORE1_MME_SBTE4_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE4_SECTION 0xE800 +#define mmDCORE1_MME_SBTE4_SPECIAL_BASE 0x42F0E80ull +#define DCORE1_MME_SBTE4_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_SBTE4_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_BASE 0x42F1000ull +#define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_BASE 0x42F1200ull +#define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_BASE 0x42F1400ull +#define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_BASE 0x42F1600ull +#define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_MME_SBTE4_MSTR_IF_E2E_CRDT_BASE 0x42F1800ull +#define DCORE1_MME_SBTE4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_MME_SBTE4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_MME_SBTE4_MSTR_IF_AXUSER_BASE 0x42F1A80ull +#define DCORE1_MME_SBTE4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_MME_SBTE4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_MME_SBTE4_MSTR_IF_DBG_HBW_BASE 0x42F1B00ull +#define DCORE1_MME_SBTE4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_SBTE4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_MME_SBTE4_MSTR_IF_DBG_LBW_BASE 0x42F1B80ull +#define DCORE1_MME_SBTE4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_SBTE4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_MME_SBTE4_MSTR_IF_CORE_HBW_BASE 0x42F1C00ull +#define DCORE1_MME_SBTE4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_MME_SBTE4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_MME_SBTE4_MSTR_IF_CORE_LBW_BASE 0x42F1D80ull +#define DCORE1_MME_SBTE4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_MME_SBTE4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_MME_SBTE4_MSTR_IF_SPECIAL_BASE 0x42F1E80ull +#define DCORE1_MME_SBTE4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_SBTE4_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE1_MME_ACC_BASE 0x42F8000ull +#define DCORE1_MME_ACC_MAX_OFFSET 0x1000 +#define DCORE1_MME_ACC_SECTION 0xE800 +#define mmDCORE1_MME_ACC_SPECIAL_BASE 0x42F8E80ull +#define DCORE1_MME_ACC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_ACC_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE 0x42F9000ull +#define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_MME_WB0_MSTR_IF_RR_PRVT_HBW_BASE 0x42F9200ull +#define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_MME_WB0_MSTR_IF_RR_SHRD_LBW_BASE 0x42F9400ull +#define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_MME_WB0_MSTR_IF_RR_PRVT_LBW_BASE 0x42F9600ull +#define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_MME_WB0_MSTR_IF_E2E_CRDT_BASE 0x42F9800ull +#define DCORE1_MME_WB0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_MME_WB0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_MME_WB0_MSTR_IF_AXUSER_BASE 0x42F9A80ull +#define DCORE1_MME_WB0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_MME_WB0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_MME_WB0_MSTR_IF_DBG_HBW_BASE 0x42F9B00ull +#define DCORE1_MME_WB0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_WB0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_MME_WB0_MSTR_IF_DBG_LBW_BASE 0x42F9B80ull +#define DCORE1_MME_WB0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_WB0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_MME_WB0_MSTR_IF_CORE_HBW_BASE 0x42F9C00ull +#define DCORE1_MME_WB0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_MME_WB0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_MME_WB0_MSTR_IF_CORE_LBW_BASE 0x42F9D80ull +#define DCORE1_MME_WB0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_MME_WB0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_MME_WB0_MSTR_IF_SPECIAL_BASE 0x42F9E80ull +#define DCORE1_MME_WB0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_WB0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE1_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE 0x42FA000ull +#define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_MME_WB1_MSTR_IF_RR_PRVT_HBW_BASE 0x42FA200ull +#define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_MME_WB1_MSTR_IF_RR_SHRD_LBW_BASE 0x42FA400ull +#define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_MME_WB1_MSTR_IF_RR_PRVT_LBW_BASE 0x42FA600ull +#define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_MME_WB1_MSTR_IF_E2E_CRDT_BASE 0x42FA800ull +#define DCORE1_MME_WB1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_MME_WB1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_MME_WB1_MSTR_IF_AXUSER_BASE 0x42FAA80ull +#define DCORE1_MME_WB1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_MME_WB1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_MME_WB1_MSTR_IF_DBG_HBW_BASE 0x42FAB00ull +#define DCORE1_MME_WB1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_WB1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_MME_WB1_MSTR_IF_DBG_LBW_BASE 0x42FAB80ull +#define DCORE1_MME_WB1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_MME_WB1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_MME_WB1_MSTR_IF_CORE_HBW_BASE 0x42FAC00ull +#define DCORE1_MME_WB1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_MME_WB1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_MME_WB1_MSTR_IF_CORE_LBW_BASE 0x42FAD80ull +#define DCORE1_MME_WB1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_MME_WB1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_MME_WB1_MSTR_IF_SPECIAL_BASE 0x42FAE80ull +#define DCORE1_MME_WB1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_MME_WB1_MSTR_IF_SPECIAL_SECTION 0x5180 +#define mmDCORE1_SYNC_MNGR_OBJS_BASE 0x4300000ull +#define DCORE1_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00 +#define DCORE1_SYNC_MNGR_OBJS_SECTION 0x1E000 +#define mmDCORE1_SYNC_MNGR_GLBL_BASE 0x431E000ull +#define DCORE1_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000 +#define DCORE1_SYNC_MNGR_GLBL_SECTION 0xE800 +#define mmDCORE1_SYNC_MNGR_GLBL_SPECIAL_BASE 0x431EE80ull +#define DCORE1_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x431F000ull +#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x431F200ull +#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x431F400ull +#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x431F600ull +#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x431F800ull +#define DCORE1_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x431FA80ull +#define DCORE1_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x431FB00ull +#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x431FB80ull +#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x431FC00ull +#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x431FD80ull +#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x431FE80ull +#define DCORE1_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE1_HIF0_BASE 0x4320000ull +#define DCORE1_HIF0_MAX_OFFSET 0x1000 +#define DCORE1_HIF0_SECTION 0xE800 +#define mmDCORE1_HIF0_SPECIAL_BASE 0x4320E80ull +#define DCORE1_HIF0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HIF0_SPECIAL_SECTION 0x3180 +#define mmDCORE1_HIF1_BASE 0x4324000ull +#define DCORE1_HIF1_MAX_OFFSET 0x1000 +#define DCORE1_HIF1_SECTION 0xE800 +#define mmDCORE1_HIF1_SPECIAL_BASE 0x4324E80ull +#define DCORE1_HIF1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HIF1_SPECIAL_SECTION 0x3180 +#define mmDCORE1_HIF2_BASE 0x4328000ull +#define DCORE1_HIF2_MAX_OFFSET 0x1000 +#define DCORE1_HIF2_SECTION 0xE800 +#define mmDCORE1_HIF2_SPECIAL_BASE 0x4328E80ull +#define DCORE1_HIF2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HIF2_SPECIAL_SECTION 0x3180 +#define mmDCORE1_HIF3_BASE 0x432C000ull +#define DCORE1_HIF3_MAX_OFFSET 0x1000 +#define DCORE1_HIF3_SECTION 0xE800 +#define mmDCORE1_HIF3_SPECIAL_BASE 0x432CE80ull +#define DCORE1_HIF3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HIF3_SPECIAL_SECTION 0x13180 +#define mmDCORE1_RTR0_CTRL_BASE 0x4340000ull +#define DCORE1_RTR0_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_RTR0_CTRL_SECTION 0xE800 +#define mmDCORE1_RTR0_CTRL_SPECIAL_BASE 0x4340E80ull +#define DCORE1_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR0_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR0_H3_BASE 0x4341000ull +#define DCORE1_RTR0_H3_MAX_OFFSET 0x1000 +#define DCORE1_RTR0_H3_SECTION 0xE800 +#define mmDCORE1_RTR0_H3_SPECIAL_BASE 0x4341E80ull +#define DCORE1_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR0_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x4342000ull +#define DCORE1_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x4342200ull +#define DCORE1_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x4342400ull +#define DCORE1_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x4342600ull +#define DCORE1_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_RTR0_MSTR_IF_E2E_CRDT_BASE 0x4342800ull +#define DCORE1_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_RTR0_MSTR_IF_AXUSER_BASE 0x4342A80ull +#define DCORE1_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_RTR0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_RTR0_MSTR_IF_DBG_HBW_BASE 0x4342B00ull +#define DCORE1_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_RTR0_MSTR_IF_DBG_LBW_BASE 0x4342B80ull +#define DCORE1_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_RTR0_MSTR_IF_CORE_HBW_BASE 0x4342C00ull +#define DCORE1_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_RTR0_MSTR_IF_CORE_LBW_BASE 0x4342D80ull +#define DCORE1_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_RTR0_MSTR_IF_SPECIAL_BASE 0x4342E80ull +#define DCORE1_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR0_ADD_DEC_HBW_BASE 0x4343000ull +#define DCORE1_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE1_RTR0_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE1_RTR0_ADD_DEC_LBW_BASE 0x4343400ull +#define DCORE1_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE1_RTR0_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE1_RTR0_ADD_DEC_SPECIAL_BASE 0x4343E80ull +#define DCORE1_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR0_BASE 0x4344000ull +#define DCORE1_RTR0_MAX_OFFSET 0x1000 +#define DCORE1_RTR0_SECTION 0x3000 +#define mmDCORE1_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x4344300ull +#define DCORE1_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR0_HBW_RD_RS_LL_STAT_BASE 0x4344340ull +#define DCORE1_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x4344380ull +#define DCORE1_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR0_HBW_WR_RS_LL_STAT_BASE 0x43443C0ull +#define DCORE1_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x4344400ull +#define DCORE1_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR0_LBW_RD_RS_LL_STAT_BASE 0x4344440ull +#define DCORE1_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x4344480ull +#define DCORE1_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR0_LBW_WR_RS_LL_STAT_BASE 0x43444C0ull +#define DCORE1_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR0_HBW_MFIFO_BASE 0x4344500ull +#define DCORE1_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE1_RTR0_E2E_RD_LL_STAT_BASE 0x4344540ull +#define DCORE1_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR0_E2E_WR_LL_STAT_BASE 0x4344580ull +#define DCORE1_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE1_RTR0_RTR_HBW_XACT_STAT_BASE 0x4344600ull +#define DCORE1_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR0_RTR_LBW_XACT_STAT_BASE 0x4344680ull +#define DCORE1_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR0_RTR_E2E_XACT_STAT_BASE 0x4344700ull +#define DCORE1_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE1_RTR0_SPECIAL_BASE 0x4344E80ull +#define DCORE1_RTR0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR0_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR0_DBG_ADDR_BASE 0x4345000ull +#define DCORE1_RTR0_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE1_RTR0_DBG_ADDR_SECTION 0xE800 +#define mmDCORE1_RTR0_DBG_ADDR_SPECIAL_BASE 0x4345E80ull +#define DCORE1_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE1_RTR1_CTRL_BASE 0x4348000ull +#define DCORE1_RTR1_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_RTR1_CTRL_SECTION 0xE800 +#define mmDCORE1_RTR1_CTRL_SPECIAL_BASE 0x4348E80ull +#define DCORE1_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR1_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR1_H3_BASE 0x4349000ull +#define DCORE1_RTR1_H3_MAX_OFFSET 0x1000 +#define DCORE1_RTR1_H3_SECTION 0xE800 +#define mmDCORE1_RTR1_H3_SPECIAL_BASE 0x4349E80ull +#define DCORE1_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR1_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x434A000ull +#define DCORE1_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x434A200ull +#define DCORE1_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x434A400ull +#define DCORE1_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x434A600ull +#define DCORE1_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_RTR1_MSTR_IF_E2E_CRDT_BASE 0x434A800ull +#define DCORE1_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_RTR1_MSTR_IF_AXUSER_BASE 0x434AA80ull +#define DCORE1_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_RTR1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_RTR1_MSTR_IF_DBG_HBW_BASE 0x434AB00ull +#define DCORE1_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_RTR1_MSTR_IF_DBG_LBW_BASE 0x434AB80ull +#define DCORE1_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_RTR1_MSTR_IF_CORE_HBW_BASE 0x434AC00ull +#define DCORE1_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_RTR1_MSTR_IF_CORE_LBW_BASE 0x434AD80ull +#define DCORE1_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_RTR1_MSTR_IF_SPECIAL_BASE 0x434AE80ull +#define DCORE1_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR1_ADD_DEC_HBW_BASE 0x434B000ull +#define DCORE1_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE1_RTR1_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE1_RTR1_ADD_DEC_LBW_BASE 0x434B400ull +#define DCORE1_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE1_RTR1_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE1_RTR1_ADD_DEC_SPECIAL_BASE 0x434BE80ull +#define DCORE1_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR1_BASE 0x434C000ull +#define DCORE1_RTR1_MAX_OFFSET 0x1000 +#define DCORE1_RTR1_SECTION 0x3000 +#define mmDCORE1_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x434C300ull +#define DCORE1_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR1_HBW_RD_RS_LL_STAT_BASE 0x434C340ull +#define DCORE1_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x434C380ull +#define DCORE1_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR1_HBW_WR_RS_LL_STAT_BASE 0x434C3C0ull +#define DCORE1_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x434C400ull +#define DCORE1_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR1_LBW_RD_RS_LL_STAT_BASE 0x434C440ull +#define DCORE1_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x434C480ull +#define DCORE1_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR1_LBW_WR_RS_LL_STAT_BASE 0x434C4C0ull +#define DCORE1_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR1_HBW_MFIFO_BASE 0x434C500ull +#define DCORE1_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE1_RTR1_E2E_RD_LL_STAT_BASE 0x434C540ull +#define DCORE1_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR1_E2E_WR_LL_STAT_BASE 0x434C580ull +#define DCORE1_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE1_RTR1_RTR_HBW_XACT_STAT_BASE 0x434C600ull +#define DCORE1_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR1_RTR_LBW_XACT_STAT_BASE 0x434C680ull +#define DCORE1_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR1_RTR_E2E_XACT_STAT_BASE 0x434C700ull +#define DCORE1_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE1_RTR1_SPECIAL_BASE 0x434CE80ull +#define DCORE1_RTR1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR1_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR1_DBG_ADDR_BASE 0x434D000ull +#define DCORE1_RTR1_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE1_RTR1_DBG_ADDR_SECTION 0xE800 +#define mmDCORE1_RTR1_DBG_ADDR_SPECIAL_BASE 0x434DE80ull +#define DCORE1_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE1_RTR2_CTRL_BASE 0x4350000ull +#define DCORE1_RTR2_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_RTR2_CTRL_SECTION 0xE800 +#define mmDCORE1_RTR2_CTRL_SPECIAL_BASE 0x4350E80ull +#define DCORE1_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR2_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR2_H3_BASE 0x4351000ull +#define DCORE1_RTR2_H3_MAX_OFFSET 0x1000 +#define DCORE1_RTR2_H3_SECTION 0xE800 +#define mmDCORE1_RTR2_H3_SPECIAL_BASE 0x4351E80ull +#define DCORE1_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR2_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x4352000ull +#define DCORE1_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x4352200ull +#define DCORE1_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x4352400ull +#define DCORE1_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x4352600ull +#define DCORE1_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_RTR2_MSTR_IF_E2E_CRDT_BASE 0x4352800ull +#define DCORE1_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_RTR2_MSTR_IF_AXUSER_BASE 0x4352A80ull +#define DCORE1_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_RTR2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_RTR2_MSTR_IF_DBG_HBW_BASE 0x4352B00ull +#define DCORE1_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_RTR2_MSTR_IF_DBG_LBW_BASE 0x4352B80ull +#define DCORE1_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_RTR2_MSTR_IF_CORE_HBW_BASE 0x4352C00ull +#define DCORE1_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_RTR2_MSTR_IF_CORE_LBW_BASE 0x4352D80ull +#define DCORE1_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_RTR2_MSTR_IF_SPECIAL_BASE 0x4352E80ull +#define DCORE1_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR2_ADD_DEC_HBW_BASE 0x4353000ull +#define DCORE1_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE1_RTR2_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE1_RTR2_ADD_DEC_LBW_BASE 0x4353400ull +#define DCORE1_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE1_RTR2_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE1_RTR2_ADD_DEC_SPECIAL_BASE 0x4353E80ull +#define DCORE1_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR2_BASE 0x4354000ull +#define DCORE1_RTR2_MAX_OFFSET 0x1000 +#define DCORE1_RTR2_SECTION 0x3000 +#define mmDCORE1_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x4354300ull +#define DCORE1_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR2_HBW_RD_RS_LL_STAT_BASE 0x4354340ull +#define DCORE1_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x4354380ull +#define DCORE1_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR2_HBW_WR_RS_LL_STAT_BASE 0x43543C0ull +#define DCORE1_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x4354400ull +#define DCORE1_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR2_LBW_RD_RS_LL_STAT_BASE 0x4354440ull +#define DCORE1_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x4354480ull +#define DCORE1_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR2_LBW_WR_RS_LL_STAT_BASE 0x43544C0ull +#define DCORE1_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR2_HBW_MFIFO_BASE 0x4354500ull +#define DCORE1_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE1_RTR2_E2E_RD_LL_STAT_BASE 0x4354540ull +#define DCORE1_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR2_E2E_WR_LL_STAT_BASE 0x4354580ull +#define DCORE1_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE1_RTR2_RTR_HBW_XACT_STAT_BASE 0x4354600ull +#define DCORE1_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR2_RTR_LBW_XACT_STAT_BASE 0x4354680ull +#define DCORE1_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR2_RTR_E2E_XACT_STAT_BASE 0x4354700ull +#define DCORE1_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE1_RTR2_SPECIAL_BASE 0x4354E80ull +#define DCORE1_RTR2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR2_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR2_DBG_ADDR_BASE 0x4355000ull +#define DCORE1_RTR2_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE1_RTR2_DBG_ADDR_SECTION 0xE800 +#define mmDCORE1_RTR2_DBG_ADDR_SPECIAL_BASE 0x4355E80ull +#define DCORE1_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE1_RTR3_CTRL_BASE 0x4358000ull +#define DCORE1_RTR3_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_RTR3_CTRL_SECTION 0xE800 +#define mmDCORE1_RTR3_CTRL_SPECIAL_BASE 0x4358E80ull +#define DCORE1_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR3_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR3_H3_BASE 0x4359000ull +#define DCORE1_RTR3_H3_MAX_OFFSET 0x1000 +#define DCORE1_RTR3_H3_SECTION 0xE800 +#define mmDCORE1_RTR3_H3_SPECIAL_BASE 0x4359E80ull +#define DCORE1_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR3_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x435A000ull +#define DCORE1_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x435A200ull +#define DCORE1_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x435A400ull +#define DCORE1_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x435A600ull +#define DCORE1_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_RTR3_MSTR_IF_E2E_CRDT_BASE 0x435A800ull +#define DCORE1_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_RTR3_MSTR_IF_AXUSER_BASE 0x435AA80ull +#define DCORE1_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_RTR3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_RTR3_MSTR_IF_DBG_HBW_BASE 0x435AB00ull +#define DCORE1_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_RTR3_MSTR_IF_DBG_LBW_BASE 0x435AB80ull +#define DCORE1_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_RTR3_MSTR_IF_CORE_HBW_BASE 0x435AC00ull +#define DCORE1_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_RTR3_MSTR_IF_CORE_LBW_BASE 0x435AD80ull +#define DCORE1_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_RTR3_MSTR_IF_SPECIAL_BASE 0x435AE80ull +#define DCORE1_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR3_ADD_DEC_HBW_BASE 0x435B000ull +#define DCORE1_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE1_RTR3_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE1_RTR3_ADD_DEC_LBW_BASE 0x435B400ull +#define DCORE1_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE1_RTR3_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE1_RTR3_ADD_DEC_SPECIAL_BASE 0x435BE80ull +#define DCORE1_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR3_BASE 0x435C000ull +#define DCORE1_RTR3_MAX_OFFSET 0x1000 +#define DCORE1_RTR3_SECTION 0x3000 +#define mmDCORE1_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x435C300ull +#define DCORE1_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR3_HBW_RD_RS_LL_STAT_BASE 0x435C340ull +#define DCORE1_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x435C380ull +#define DCORE1_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR3_HBW_WR_RS_LL_STAT_BASE 0x435C3C0ull +#define DCORE1_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x435C400ull +#define DCORE1_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR3_LBW_RD_RS_LL_STAT_BASE 0x435C440ull +#define DCORE1_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x435C480ull +#define DCORE1_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR3_LBW_WR_RS_LL_STAT_BASE 0x435C4C0ull +#define DCORE1_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR3_HBW_MFIFO_BASE 0x435C500ull +#define DCORE1_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE1_RTR3_E2E_RD_LL_STAT_BASE 0x435C540ull +#define DCORE1_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR3_E2E_WR_LL_STAT_BASE 0x435C580ull +#define DCORE1_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE1_RTR3_RTR_HBW_XACT_STAT_BASE 0x435C600ull +#define DCORE1_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR3_RTR_LBW_XACT_STAT_BASE 0x435C680ull +#define DCORE1_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR3_RTR_E2E_XACT_STAT_BASE 0x435C700ull +#define DCORE1_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE1_RTR3_SPECIAL_BASE 0x435CE80ull +#define DCORE1_RTR3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR3_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR3_DBG_ADDR_BASE 0x435D000ull +#define DCORE1_RTR3_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE1_RTR3_DBG_ADDR_SECTION 0xE800 +#define mmDCORE1_RTR3_DBG_ADDR_SPECIAL_BASE 0x435DE80ull +#define DCORE1_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE1_RTR4_CTRL_BASE 0x4360000ull +#define DCORE1_RTR4_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_RTR4_CTRL_SECTION 0xE800 +#define mmDCORE1_RTR4_CTRL_SPECIAL_BASE 0x4360E80ull +#define DCORE1_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR4_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR4_H3_BASE 0x4361000ull +#define DCORE1_RTR4_H3_MAX_OFFSET 0x1000 +#define DCORE1_RTR4_H3_SECTION 0xE800 +#define mmDCORE1_RTR4_H3_SPECIAL_BASE 0x4361E80ull +#define DCORE1_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR4_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x4362000ull +#define DCORE1_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x4362200ull +#define DCORE1_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x4362400ull +#define DCORE1_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x4362600ull +#define DCORE1_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_RTR4_MSTR_IF_E2E_CRDT_BASE 0x4362800ull +#define DCORE1_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_RTR4_MSTR_IF_AXUSER_BASE 0x4362A80ull +#define DCORE1_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_RTR4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_RTR4_MSTR_IF_DBG_HBW_BASE 0x4362B00ull +#define DCORE1_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_RTR4_MSTR_IF_DBG_LBW_BASE 0x4362B80ull +#define DCORE1_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_RTR4_MSTR_IF_CORE_HBW_BASE 0x4362C00ull +#define DCORE1_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_RTR4_MSTR_IF_CORE_LBW_BASE 0x4362D80ull +#define DCORE1_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_RTR4_MSTR_IF_SPECIAL_BASE 0x4362E80ull +#define DCORE1_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR4_ADD_DEC_HBW_BASE 0x4363000ull +#define DCORE1_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE1_RTR4_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE1_RTR4_ADD_DEC_LBW_BASE 0x4363400ull +#define DCORE1_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE1_RTR4_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE1_RTR4_ADD_DEC_SPECIAL_BASE 0x4363E80ull +#define DCORE1_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR4_BASE 0x4364000ull +#define DCORE1_RTR4_MAX_OFFSET 0x1000 +#define DCORE1_RTR4_SECTION 0x3000 +#define mmDCORE1_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x4364300ull +#define DCORE1_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR4_HBW_RD_RS_LL_STAT_BASE 0x4364340ull +#define DCORE1_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x4364380ull +#define DCORE1_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR4_HBW_WR_RS_LL_STAT_BASE 0x43643C0ull +#define DCORE1_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x4364400ull +#define DCORE1_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR4_LBW_RD_RS_LL_STAT_BASE 0x4364440ull +#define DCORE1_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x4364480ull +#define DCORE1_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR4_LBW_WR_RS_LL_STAT_BASE 0x43644C0ull +#define DCORE1_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR4_HBW_MFIFO_BASE 0x4364500ull +#define DCORE1_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE1_RTR4_E2E_RD_LL_STAT_BASE 0x4364540ull +#define DCORE1_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR4_E2E_WR_LL_STAT_BASE 0x4364580ull +#define DCORE1_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE1_RTR4_RTR_HBW_XACT_STAT_BASE 0x4364600ull +#define DCORE1_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR4_RTR_LBW_XACT_STAT_BASE 0x4364680ull +#define DCORE1_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR4_RTR_E2E_XACT_STAT_BASE 0x4364700ull +#define DCORE1_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE1_RTR4_SPECIAL_BASE 0x4364E80ull +#define DCORE1_RTR4_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR4_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR4_DBG_ADDR_BASE 0x4365000ull +#define DCORE1_RTR4_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE1_RTR4_DBG_ADDR_SECTION 0xE800 +#define mmDCORE1_RTR4_DBG_ADDR_SPECIAL_BASE 0x4365E80ull +#define DCORE1_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE1_RTR5_CTRL_BASE 0x4368000ull +#define DCORE1_RTR5_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_RTR5_CTRL_SECTION 0xE800 +#define mmDCORE1_RTR5_CTRL_SPECIAL_BASE 0x4368E80ull +#define DCORE1_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR5_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR5_H3_BASE 0x4369000ull +#define DCORE1_RTR5_H3_MAX_OFFSET 0x1000 +#define DCORE1_RTR5_H3_SECTION 0xE800 +#define mmDCORE1_RTR5_H3_SPECIAL_BASE 0x4369E80ull +#define DCORE1_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR5_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x436A000ull +#define DCORE1_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x436A200ull +#define DCORE1_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x436A400ull +#define DCORE1_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x436A600ull +#define DCORE1_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_RTR5_MSTR_IF_E2E_CRDT_BASE 0x436A800ull +#define DCORE1_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_RTR5_MSTR_IF_AXUSER_BASE 0x436AA80ull +#define DCORE1_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_RTR5_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_RTR5_MSTR_IF_DBG_HBW_BASE 0x436AB00ull +#define DCORE1_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_RTR5_MSTR_IF_DBG_LBW_BASE 0x436AB80ull +#define DCORE1_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_RTR5_MSTR_IF_CORE_HBW_BASE 0x436AC00ull +#define DCORE1_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_RTR5_MSTR_IF_CORE_LBW_BASE 0x436AD80ull +#define DCORE1_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_RTR5_MSTR_IF_SPECIAL_BASE 0x436AE80ull +#define DCORE1_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR5_ADD_DEC_HBW_BASE 0x436B000ull +#define DCORE1_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE1_RTR5_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE1_RTR5_ADD_DEC_LBW_BASE 0x436B400ull +#define DCORE1_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE1_RTR5_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE1_RTR5_ADD_DEC_SPECIAL_BASE 0x436BE80ull +#define DCORE1_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR5_BASE 0x436C000ull +#define DCORE1_RTR5_MAX_OFFSET 0x1000 +#define DCORE1_RTR5_SECTION 0x3000 +#define mmDCORE1_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x436C300ull +#define DCORE1_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR5_HBW_RD_RS_LL_STAT_BASE 0x436C340ull +#define DCORE1_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x436C380ull +#define DCORE1_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR5_HBW_WR_RS_LL_STAT_BASE 0x436C3C0ull +#define DCORE1_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x436C400ull +#define DCORE1_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR5_LBW_RD_RS_LL_STAT_BASE 0x436C440ull +#define DCORE1_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x436C480ull +#define DCORE1_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR5_LBW_WR_RS_LL_STAT_BASE 0x436C4C0ull +#define DCORE1_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR5_HBW_MFIFO_BASE 0x436C500ull +#define DCORE1_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE1_RTR5_E2E_RD_LL_STAT_BASE 0x436C540ull +#define DCORE1_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR5_E2E_WR_LL_STAT_BASE 0x436C580ull +#define DCORE1_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE1_RTR5_RTR_HBW_XACT_STAT_BASE 0x436C600ull +#define DCORE1_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR5_RTR_LBW_XACT_STAT_BASE 0x436C680ull +#define DCORE1_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR5_RTR_E2E_XACT_STAT_BASE 0x436C700ull +#define DCORE1_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE1_RTR5_SPECIAL_BASE 0x436CE80ull +#define DCORE1_RTR5_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR5_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR5_DBG_ADDR_BASE 0x436D000ull +#define DCORE1_RTR5_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE1_RTR5_DBG_ADDR_SECTION 0xE800 +#define mmDCORE1_RTR5_DBG_ADDR_SPECIAL_BASE 0x436DE80ull +#define DCORE1_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE1_RTR6_CTRL_BASE 0x4370000ull +#define DCORE1_RTR6_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_RTR6_CTRL_SECTION 0xE800 +#define mmDCORE1_RTR6_CTRL_SPECIAL_BASE 0x4370E80ull +#define DCORE1_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR6_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR6_H3_BASE 0x4371000ull +#define DCORE1_RTR6_H3_MAX_OFFSET 0x1000 +#define DCORE1_RTR6_H3_SECTION 0xE800 +#define mmDCORE1_RTR6_H3_SPECIAL_BASE 0x4371E80ull +#define DCORE1_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR6_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x4372000ull +#define DCORE1_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x4372200ull +#define DCORE1_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x4372400ull +#define DCORE1_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x4372600ull +#define DCORE1_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_RTR6_MSTR_IF_E2E_CRDT_BASE 0x4372800ull +#define DCORE1_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_RTR6_MSTR_IF_AXUSER_BASE 0x4372A80ull +#define DCORE1_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_RTR6_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_RTR6_MSTR_IF_DBG_HBW_BASE 0x4372B00ull +#define DCORE1_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_RTR6_MSTR_IF_DBG_LBW_BASE 0x4372B80ull +#define DCORE1_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_RTR6_MSTR_IF_CORE_HBW_BASE 0x4372C00ull +#define DCORE1_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_RTR6_MSTR_IF_CORE_LBW_BASE 0x4372D80ull +#define DCORE1_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_RTR6_MSTR_IF_SPECIAL_BASE 0x4372E80ull +#define DCORE1_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR6_ADD_DEC_HBW_BASE 0x4373000ull +#define DCORE1_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE1_RTR6_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE1_RTR6_ADD_DEC_LBW_BASE 0x4373400ull +#define DCORE1_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE1_RTR6_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE1_RTR6_ADD_DEC_SPECIAL_BASE 0x4373E80ull +#define DCORE1_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR6_BASE 0x4374000ull +#define DCORE1_RTR6_MAX_OFFSET 0x1000 +#define DCORE1_RTR6_SECTION 0x3000 +#define mmDCORE1_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x4374300ull +#define DCORE1_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR6_HBW_RD_RS_LL_STAT_BASE 0x4374340ull +#define DCORE1_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x4374380ull +#define DCORE1_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR6_HBW_WR_RS_LL_STAT_BASE 0x43743C0ull +#define DCORE1_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x4374400ull +#define DCORE1_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR6_LBW_RD_RS_LL_STAT_BASE 0x4374440ull +#define DCORE1_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x4374480ull +#define DCORE1_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR6_LBW_WR_RS_LL_STAT_BASE 0x43744C0ull +#define DCORE1_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR6_HBW_MFIFO_BASE 0x4374500ull +#define DCORE1_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE1_RTR6_E2E_RD_LL_STAT_BASE 0x4374540ull +#define DCORE1_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR6_E2E_WR_LL_STAT_BASE 0x4374580ull +#define DCORE1_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE1_RTR6_RTR_HBW_XACT_STAT_BASE 0x4374600ull +#define DCORE1_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR6_RTR_LBW_XACT_STAT_BASE 0x4374680ull +#define DCORE1_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR6_RTR_E2E_XACT_STAT_BASE 0x4374700ull +#define DCORE1_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE1_RTR6_SPECIAL_BASE 0x4374E80ull +#define DCORE1_RTR6_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR6_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR6_DBG_ADDR_BASE 0x4375000ull +#define DCORE1_RTR6_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE1_RTR6_DBG_ADDR_SECTION 0xE800 +#define mmDCORE1_RTR6_DBG_ADDR_SPECIAL_BASE 0x4375E80ull +#define DCORE1_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE1_RTR7_CTRL_BASE 0x4378000ull +#define DCORE1_RTR7_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_RTR7_CTRL_SECTION 0xE800 +#define mmDCORE1_RTR7_CTRL_SPECIAL_BASE 0x4378E80ull +#define DCORE1_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR7_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR7_H3_BASE 0x4379000ull +#define DCORE1_RTR7_H3_MAX_OFFSET 0x1000 +#define DCORE1_RTR7_H3_SECTION 0xE800 +#define mmDCORE1_RTR7_H3_SPECIAL_BASE 0x4379E80ull +#define DCORE1_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR7_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x437A000ull +#define DCORE1_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x437A200ull +#define DCORE1_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x437A400ull +#define DCORE1_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x437A600ull +#define DCORE1_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_RTR7_MSTR_IF_E2E_CRDT_BASE 0x437A800ull +#define DCORE1_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_RTR7_MSTR_IF_AXUSER_BASE 0x437AA80ull +#define DCORE1_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_RTR7_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_RTR7_MSTR_IF_DBG_HBW_BASE 0x437AB00ull +#define DCORE1_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_RTR7_MSTR_IF_DBG_LBW_BASE 0x437AB80ull +#define DCORE1_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_RTR7_MSTR_IF_CORE_HBW_BASE 0x437AC00ull +#define DCORE1_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_RTR7_MSTR_IF_CORE_LBW_BASE 0x437AD80ull +#define DCORE1_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_RTR7_MSTR_IF_SPECIAL_BASE 0x437AE80ull +#define DCORE1_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR7_ADD_DEC_HBW_BASE 0x437B000ull +#define DCORE1_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE1_RTR7_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE1_RTR7_ADD_DEC_LBW_BASE 0x437B400ull +#define DCORE1_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE1_RTR7_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE1_RTR7_ADD_DEC_SPECIAL_BASE 0x437BE80ull +#define DCORE1_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR7_BASE 0x437C000ull +#define DCORE1_RTR7_MAX_OFFSET 0x1000 +#define DCORE1_RTR7_SECTION 0x3000 +#define mmDCORE1_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x437C300ull +#define DCORE1_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR7_HBW_RD_RS_LL_STAT_BASE 0x437C340ull +#define DCORE1_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x437C380ull +#define DCORE1_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR7_HBW_WR_RS_LL_STAT_BASE 0x437C3C0ull +#define DCORE1_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x437C400ull +#define DCORE1_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR7_LBW_RD_RS_LL_STAT_BASE 0x437C440ull +#define DCORE1_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x437C480ull +#define DCORE1_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR7_LBW_WR_RS_LL_STAT_BASE 0x437C4C0ull +#define DCORE1_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR7_HBW_MFIFO_BASE 0x437C500ull +#define DCORE1_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE1_RTR7_E2E_RD_LL_STAT_BASE 0x437C540ull +#define DCORE1_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE1_RTR7_E2E_WR_LL_STAT_BASE 0x437C580ull +#define DCORE1_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE1_RTR7_RTR_HBW_XACT_STAT_BASE 0x437C600ull +#define DCORE1_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR7_RTR_LBW_XACT_STAT_BASE 0x437C680ull +#define DCORE1_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE1_RTR7_RTR_E2E_XACT_STAT_BASE 0x437C700ull +#define DCORE1_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE1_RTR7_SPECIAL_BASE 0x437CE80ull +#define DCORE1_RTR7_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR7_SPECIAL_SECTION 0x1800 +#define mmDCORE1_RTR7_DBG_ADDR_BASE 0x437D000ull +#define DCORE1_RTR7_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE1_RTR7_DBG_ADDR_SECTION 0xE800 +#define mmDCORE1_RTR7_DBG_ADDR_SPECIAL_BASE 0x437DE80ull +#define DCORE1_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE1_SRAM0_BANK_BASE 0x4380000ull +#define DCORE1_SRAM0_BANK_MAX_OFFSET 0x1000 +#define DCORE1_SRAM0_BANK_SECTION 0xE800 +#define mmDCORE1_SRAM0_BANK_SPECIAL_BASE 0x4380E80ull +#define DCORE1_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM0_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM0_RTR_BASE 0x4381000ull +#define DCORE1_SRAM0_RTR_MAX_OFFSET 0x1000 +#define DCORE1_SRAM0_RTR_SECTION 0xE800 +#define mmDCORE1_SRAM0_RTR_SPECIAL_BASE 0x4381E80ull +#define DCORE1_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM0_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4382000ull +#define DCORE1_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4382100ull +#define DCORE1_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4382200ull +#define DCORE1_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4382300ull +#define DCORE1_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4382400ull +#define DCORE1_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4382500ull +#define DCORE1_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4382600ull +#define DCORE1_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4382700ull +#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4382780ull +#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4382800ull +#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4382880ull +#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4382900ull +#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4382980ull +#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4382A00ull +#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4382A80ull +#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE1_SRAM0_DBG_CNT_SPECIAL_BASE 0x4382E80ull +#define DCORE1_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE1_SRAM1_BANK_BASE 0x4388000ull +#define DCORE1_SRAM1_BANK_MAX_OFFSET 0x1000 +#define DCORE1_SRAM1_BANK_SECTION 0xE800 +#define mmDCORE1_SRAM1_BANK_SPECIAL_BASE 0x4388E80ull +#define DCORE1_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM1_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM1_RTR_BASE 0x4389000ull +#define DCORE1_SRAM1_RTR_MAX_OFFSET 0x1000 +#define DCORE1_SRAM1_RTR_SECTION 0xE800 +#define mmDCORE1_SRAM1_RTR_SPECIAL_BASE 0x4389E80ull +#define DCORE1_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM1_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x438A000ull +#define DCORE1_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x438A100ull +#define DCORE1_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x438A200ull +#define DCORE1_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x438A300ull +#define DCORE1_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x438A400ull +#define DCORE1_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x438A500ull +#define DCORE1_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x438A600ull +#define DCORE1_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x438A700ull +#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x438A780ull +#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x438A800ull +#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x438A880ull +#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x438A900ull +#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x438A980ull +#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x438AA00ull +#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x438AA80ull +#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE1_SRAM1_DBG_CNT_SPECIAL_BASE 0x438AE80ull +#define DCORE1_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE1_SRAM2_BANK_BASE 0x4390000ull +#define DCORE1_SRAM2_BANK_MAX_OFFSET 0x1000 +#define DCORE1_SRAM2_BANK_SECTION 0xE800 +#define mmDCORE1_SRAM2_BANK_SPECIAL_BASE 0x4390E80ull +#define DCORE1_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM2_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM2_RTR_BASE 0x4391000ull +#define DCORE1_SRAM2_RTR_MAX_OFFSET 0x1000 +#define DCORE1_SRAM2_RTR_SECTION 0xE800 +#define mmDCORE1_SRAM2_RTR_SPECIAL_BASE 0x4391E80ull +#define DCORE1_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM2_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4392000ull +#define DCORE1_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4392100ull +#define DCORE1_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4392200ull +#define DCORE1_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4392300ull +#define DCORE1_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4392400ull +#define DCORE1_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4392500ull +#define DCORE1_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4392600ull +#define DCORE1_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4392700ull +#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4392780ull +#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4392800ull +#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4392880ull +#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4392900ull +#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4392980ull +#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4392A00ull +#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4392A80ull +#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE1_SRAM2_DBG_CNT_SPECIAL_BASE 0x4392E80ull +#define DCORE1_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE1_SRAM3_BANK_BASE 0x4398000ull +#define DCORE1_SRAM3_BANK_MAX_OFFSET 0x1000 +#define DCORE1_SRAM3_BANK_SECTION 0xE800 +#define mmDCORE1_SRAM3_BANK_SPECIAL_BASE 0x4398E80ull +#define DCORE1_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM3_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM3_RTR_BASE 0x4399000ull +#define DCORE1_SRAM3_RTR_MAX_OFFSET 0x1000 +#define DCORE1_SRAM3_RTR_SECTION 0xE800 +#define mmDCORE1_SRAM3_RTR_SPECIAL_BASE 0x4399E80ull +#define DCORE1_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM3_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x439A000ull +#define DCORE1_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x439A100ull +#define DCORE1_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x439A200ull +#define DCORE1_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x439A300ull +#define DCORE1_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x439A400ull +#define DCORE1_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x439A500ull +#define DCORE1_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x439A600ull +#define DCORE1_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x439A700ull +#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x439A780ull +#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x439A800ull +#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x439A880ull +#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x439A900ull +#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x439A980ull +#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x439AA00ull +#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x439AA80ull +#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE1_SRAM3_DBG_CNT_SPECIAL_BASE 0x439AE80ull +#define DCORE1_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE1_SRAM4_BANK_BASE 0x43A0000ull +#define DCORE1_SRAM4_BANK_MAX_OFFSET 0x1000 +#define DCORE1_SRAM4_BANK_SECTION 0xE800 +#define mmDCORE1_SRAM4_BANK_SPECIAL_BASE 0x43A0E80ull +#define DCORE1_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM4_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM4_RTR_BASE 0x43A1000ull +#define DCORE1_SRAM4_RTR_MAX_OFFSET 0x1000 +#define DCORE1_SRAM4_RTR_SECTION 0xE800 +#define mmDCORE1_SRAM4_RTR_SPECIAL_BASE 0x43A1E80ull +#define DCORE1_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM4_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x43A2000ull +#define DCORE1_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x43A2100ull +#define DCORE1_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x43A2200ull +#define DCORE1_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x43A2300ull +#define DCORE1_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x43A2400ull +#define DCORE1_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x43A2500ull +#define DCORE1_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x43A2600ull +#define DCORE1_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x43A2700ull +#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x43A2780ull +#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x43A2800ull +#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x43A2880ull +#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x43A2900ull +#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x43A2980ull +#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x43A2A00ull +#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x43A2A80ull +#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE1_SRAM4_DBG_CNT_SPECIAL_BASE 0x43A2E80ull +#define DCORE1_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE1_SRAM5_BANK_BASE 0x43A8000ull +#define DCORE1_SRAM5_BANK_MAX_OFFSET 0x1000 +#define DCORE1_SRAM5_BANK_SECTION 0xE800 +#define mmDCORE1_SRAM5_BANK_SPECIAL_BASE 0x43A8E80ull +#define DCORE1_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM5_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM5_RTR_BASE 0x43A9000ull +#define DCORE1_SRAM5_RTR_MAX_OFFSET 0x1000 +#define DCORE1_SRAM5_RTR_SECTION 0xE800 +#define mmDCORE1_SRAM5_RTR_SPECIAL_BASE 0x43A9E80ull +#define DCORE1_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM5_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x43AA000ull +#define DCORE1_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x43AA100ull +#define DCORE1_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x43AA200ull +#define DCORE1_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x43AA300ull +#define DCORE1_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x43AA400ull +#define DCORE1_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x43AA500ull +#define DCORE1_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x43AA600ull +#define DCORE1_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x43AA700ull +#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x43AA780ull +#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x43AA800ull +#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x43AA880ull +#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x43AA900ull +#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x43AA980ull +#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x43AAA00ull +#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x43AAA80ull +#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE1_SRAM5_DBG_CNT_SPECIAL_BASE 0x43AAE80ull +#define DCORE1_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE1_SRAM6_BANK_BASE 0x43B0000ull +#define DCORE1_SRAM6_BANK_MAX_OFFSET 0x1000 +#define DCORE1_SRAM6_BANK_SECTION 0xE800 +#define mmDCORE1_SRAM6_BANK_SPECIAL_BASE 0x43B0E80ull +#define DCORE1_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM6_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM6_RTR_BASE 0x43B1000ull +#define DCORE1_SRAM6_RTR_MAX_OFFSET 0x1000 +#define DCORE1_SRAM6_RTR_SECTION 0xE800 +#define mmDCORE1_SRAM6_RTR_SPECIAL_BASE 0x43B1E80ull +#define DCORE1_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM6_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x43B2000ull +#define DCORE1_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x43B2100ull +#define DCORE1_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x43B2200ull +#define DCORE1_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x43B2300ull +#define DCORE1_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x43B2400ull +#define DCORE1_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x43B2500ull +#define DCORE1_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x43B2600ull +#define DCORE1_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x43B2700ull +#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x43B2780ull +#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x43B2800ull +#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x43B2880ull +#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x43B2900ull +#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x43B2980ull +#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x43B2A00ull +#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x43B2A80ull +#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE1_SRAM6_DBG_CNT_SPECIAL_BASE 0x43B2E80ull +#define DCORE1_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE1_SRAM7_BANK_BASE 0x43B8000ull +#define DCORE1_SRAM7_BANK_MAX_OFFSET 0x1000 +#define DCORE1_SRAM7_BANK_SECTION 0xE800 +#define mmDCORE1_SRAM7_BANK_SPECIAL_BASE 0x43B8E80ull +#define DCORE1_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM7_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM7_RTR_BASE 0x43B9000ull +#define DCORE1_SRAM7_RTR_MAX_OFFSET 0x1000 +#define DCORE1_SRAM7_RTR_SECTION 0xE800 +#define mmDCORE1_SRAM7_RTR_SPECIAL_BASE 0x43B9E80ull +#define DCORE1_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM7_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE1_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x43BA000ull +#define DCORE1_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x43BA100ull +#define DCORE1_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x43BA200ull +#define DCORE1_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x43BA300ull +#define DCORE1_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x43BA400ull +#define DCORE1_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x43BA500ull +#define DCORE1_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x43BA600ull +#define DCORE1_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE1_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x43BA700ull +#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x43BA780ull +#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x43BA800ull +#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x43BA880ull +#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x43BA900ull +#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x43BA980ull +#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x43BAA00ull +#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE1_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x43BAA80ull +#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE1_SRAM7_DBG_CNT_SPECIAL_BASE 0x43BAE80ull +#define DCORE1_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE1_EDMA0_QM_DCCM_BASE 0x43C0000ull +#define DCORE1_EDMA0_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_EDMA0_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_ARC_AUX_BASE 0x43C8000ull +#define DCORE1_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE1_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x43C8E80ull +#define DCORE1_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_EDMA0_QM_BASE 0x43CA000ull +#define DCORE1_EDMA0_QM_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_QM_SECTION 0x9000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x43CA900ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x43CA908ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x43CA910ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x43CA918ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x43CA920ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x43CA928ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x43CA930ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x43CA938ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x43CA940ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x43CA948ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x43CA950ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x43CA958ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x43CA960ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x43CA968ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x43CA970ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x43CA978ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_EDMA0_QM_AXUSER_SECURED_BASE 0x43CAB00ull +#define DCORE1_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_AXUSER_NONSECURED_BASE 0x43CAB80ull +#define DCORE1_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_DBG_HBW_BASE 0x43CAC00ull +#define DCORE1_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_EDMA0_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_EDMA0_QM_DBG_LBW_BASE 0x43CAC80ull +#define DCORE1_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_EDMA0_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_EDMA0_QM_CGM_BASE 0x43CAD80ull +#define DCORE1_EDMA0_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_EDMA0_QM_CGM_SECTION 0x1000 +#define mmDCORE1_EDMA0_QM_SPECIAL_BASE 0x43CAE80ull +#define DCORE1_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_EDMA0_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_EDMA0_CORE_BASE 0x43CB000ull +#define DCORE1_EDMA0_CORE_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_CORE_SECTION 0x8000 +#define mmDCORE1_EDMA0_CORE_CTX_AXUSER_BASE 0x43CB800ull +#define DCORE1_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000 +#define mmDCORE1_EDMA0_CORE_CTX_BASE 0x43CB860ull +#define DCORE1_EDMA0_CORE_CTX_MAX_OFFSET 0x9000 +#define DCORE1_EDMA0_CORE_CTX_SECTION 0x5A00 +#define mmDCORE1_EDMA0_CORE_KDMA_CGM_BASE 0x43CBE00ull +#define DCORE1_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define DCORE1_EDMA0_CORE_KDMA_CGM_SECTION 0x8000 +#define mmDCORE1_EDMA0_CORE_SPECIAL_BASE 0x43CBE80ull +#define DCORE1_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_EDMA0_CORE_SPECIAL_SECTION 0x1800 +#define mmDCORE1_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x43CC000ull +#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x43CC200ull +#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x43CC400ull +#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x43CC600ull +#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x43CC800ull +#define DCORE1_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_EDMA0_MSTR_IF_AXUSER_BASE 0x43CCA80ull +#define DCORE1_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_EDMA0_MSTR_IF_DBG_HBW_BASE 0x43CCB00ull +#define DCORE1_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_EDMA0_MSTR_IF_DBG_LBW_BASE 0x43CCB80ull +#define DCORE1_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_EDMA0_MSTR_IF_CORE_HBW_BASE 0x43CCC00ull +#define DCORE1_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_EDMA0_MSTR_IF_CORE_LBW_BASE 0x43CCD80ull +#define DCORE1_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_EDMA0_MSTR_IF_SPECIAL_BASE 0x43CCE80ull +#define DCORE1_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE1_EDMA1_QM_DCCM_BASE 0x43D0000ull +#define DCORE1_EDMA1_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_EDMA1_QM_DCCM_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_ARC_AUX_BASE 0x43D8000ull +#define DCORE1_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE1_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x43D8E80ull +#define DCORE1_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE1_EDMA1_QM_BASE 0x43DA000ull +#define DCORE1_EDMA1_QM_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_QM_SECTION 0x9000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x43DA900ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x43DA908ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x43DA910ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x43DA918ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x43DA920ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x43DA928ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x43DA930ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x43DA938ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x43DA940ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x43DA948ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x43DA950ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x43DA958ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x43DA960ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x43DA968ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x43DA970ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x43DA978ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE1_EDMA1_QM_AXUSER_SECURED_BASE 0x43DAB00ull +#define DCORE1_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_AXUSER_NONSECURED_BASE 0x43DAB80ull +#define DCORE1_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_DBG_HBW_BASE 0x43DAC00ull +#define DCORE1_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_EDMA1_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_EDMA1_QM_DBG_LBW_BASE 0x43DAC80ull +#define DCORE1_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_EDMA1_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE1_EDMA1_QM_CGM_BASE 0x43DAD80ull +#define DCORE1_EDMA1_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_EDMA1_QM_CGM_SECTION 0x1000 +#define mmDCORE1_EDMA1_QM_SPECIAL_BASE 0x43DAE80ull +#define DCORE1_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_EDMA1_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE1_EDMA1_CORE_BASE 0x43DB000ull +#define DCORE1_EDMA1_CORE_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_CORE_SECTION 0x8000 +#define mmDCORE1_EDMA1_CORE_CTX_AXUSER_BASE 0x43DB800ull +#define DCORE1_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000 +#define mmDCORE1_EDMA1_CORE_CTX_BASE 0x43DB860ull +#define DCORE1_EDMA1_CORE_CTX_MAX_OFFSET 0x9000 +#define DCORE1_EDMA1_CORE_CTX_SECTION 0x5A00 +#define mmDCORE1_EDMA1_CORE_KDMA_CGM_BASE 0x43DBE00ull +#define DCORE1_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define DCORE1_EDMA1_CORE_KDMA_CGM_SECTION 0x8000 +#define mmDCORE1_EDMA1_CORE_SPECIAL_BASE 0x43DBE80ull +#define DCORE1_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_EDMA1_CORE_SPECIAL_SECTION 0x1800 +#define mmDCORE1_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x43DC000ull +#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x43DC200ull +#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x43DC400ull +#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x43DC600ull +#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x43DC800ull +#define DCORE1_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_EDMA1_MSTR_IF_AXUSER_BASE 0x43DCA80ull +#define DCORE1_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_EDMA1_MSTR_IF_DBG_HBW_BASE 0x43DCB00ull +#define DCORE1_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_EDMA1_MSTR_IF_DBG_LBW_BASE 0x43DCB80ull +#define DCORE1_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_EDMA1_MSTR_IF_CORE_HBW_BASE 0x43DCC00ull +#define DCORE1_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_EDMA1_MSTR_IF_CORE_LBW_BASE 0x43DCD80ull +#define DCORE1_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_EDMA1_MSTR_IF_SPECIAL_BASE 0x43DCE80ull +#define DCORE1_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE1_DEC0_CMD_BASE 0x43E0000ull +#define DCORE1_DEC0_CMD_MAX_OFFSET 0x1100 +#define DCORE1_DEC0_CMD_SECTION 0x1000 +#define mmDCORE1_DEC0_VSI_BASE 0x43E1000ull +#define DCORE1_DEC0_VSI_MAX_OFFSET 0x6FC0 +#define DCORE1_DEC0_VSI_SECTION 0x1000 +#define mmDCORE1_DEC0_L2C_BASE 0x43E2000ull +#define DCORE1_DEC0_L2C_MAX_OFFSET 0x39C0 +#define DCORE1_DEC0_L2C_SECTION 0x1000 +#define mmDCORE1_VDEC0_BRDG_CTRL_BASE 0x43E3000ull +#define DCORE1_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_BRDG_CTRL_SECTION 0x8000 +#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x43E3800ull +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 +#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x43E3900ull +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 +#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x43E3A00ull +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 +#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x43E3B00ull +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 +#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x43E3C00ull +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 +#define mmDCORE1_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x43E3E80ull +#define DCORE1_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_VDEC0_CTRL_BASE 0x43E4000ull +#define DCORE1_VDEC0_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_CTRL_SECTION 0xE800 +#define mmDCORE1_VDEC0_CTRL_SPECIAL_BASE 0x43E4E80ull +#define DCORE1_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_VDEC0_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x43E5000ull +#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x43E5200ull +#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x43E5400ull +#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x43E5600ull +#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x43E5800ull +#define DCORE1_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_VDEC0_MSTR_IF_AXUSER_BASE 0x43E5A80ull +#define DCORE1_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_VDEC0_MSTR_IF_DBG_HBW_BASE 0x43E5B00ull +#define DCORE1_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_VDEC0_MSTR_IF_DBG_LBW_BASE 0x43E5B80ull +#define DCORE1_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_VDEC0_MSTR_IF_CORE_HBW_BASE 0x43E5C00ull +#define DCORE1_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_VDEC0_MSTR_IF_CORE_LBW_BASE 0x43E5D80ull +#define DCORE1_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_VDEC0_MSTR_IF_SPECIAL_BASE 0x43E5E80ull +#define DCORE1_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180 +#define mmDCORE1_DEC1_CMD_BASE 0x43F0000ull +#define DCORE1_DEC1_CMD_MAX_OFFSET 0x1100 +#define DCORE1_DEC1_CMD_SECTION 0x1000 +#define mmDCORE1_DEC1_VSI_BASE 0x43F1000ull +#define DCORE1_DEC1_VSI_MAX_OFFSET 0x6FC0 +#define DCORE1_DEC1_VSI_SECTION 0x1000 +#define mmDCORE1_DEC1_L2C_BASE 0x43F2000ull +#define DCORE1_DEC1_L2C_MAX_OFFSET 0x39C0 +#define DCORE1_DEC1_L2C_SECTION 0x1000 +#define mmDCORE1_VDEC1_BRDG_CTRL_BASE 0x43F3000ull +#define DCORE1_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_BRDG_CTRL_SECTION 0x8000 +#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x43F3800ull +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 +#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x43F3900ull +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 +#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x43F3A00ull +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 +#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x43F3B00ull +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 +#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x43F3C00ull +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 +#define mmDCORE1_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x43F3E80ull +#define DCORE1_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_VDEC1_CTRL_BASE 0x43F4000ull +#define DCORE1_VDEC1_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_CTRL_SECTION 0xE800 +#define mmDCORE1_VDEC1_CTRL_SPECIAL_BASE 0x43F4E80ull +#define DCORE1_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_VDEC1_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x43F5000ull +#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE1_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x43F5200ull +#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE1_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x43F5400ull +#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE1_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x43F5600ull +#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE1_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x43F5800ull +#define DCORE1_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE1_VDEC1_MSTR_IF_AXUSER_BASE 0x43F5A80ull +#define DCORE1_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE1_VDEC1_MSTR_IF_DBG_HBW_BASE 0x43F5B00ull +#define DCORE1_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE1_VDEC1_MSTR_IF_DBG_LBW_BASE 0x43F5B80ull +#define DCORE1_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE1_VDEC1_MSTR_IF_CORE_HBW_BASE 0x43F5C00ull +#define DCORE1_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE1_VDEC1_MSTR_IF_CORE_LBW_BASE 0x43F5D80ull +#define DCORE1_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE1_VDEC1_MSTR_IF_SPECIAL_BASE 0x43F5E80ull +#define DCORE1_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180 +#define mmDCORE2_TPC0_QM_DCCM_BASE 0x4400000ull +#define DCORE2_TPC0_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC0_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_ARC_AUX_BASE 0x4408000ull +#define DCORE2_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE2_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x4408E80ull +#define DCORE2_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_TPC0_QM_BASE 0x440A000ull +#define DCORE2_TPC0_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_QM_SECTION 0x9000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x440A900ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x440A908ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x440A910ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x440A918ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x440A920ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x440A928ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x440A930ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x440A938ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x440A940ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x440A948ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x440A950ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x440A958ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x440A960ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x440A968ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x440A970ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x440A978ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_TPC0_QM_AXUSER_SECURED_BASE 0x440AB00ull +#define DCORE2_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_AXUSER_NONSECURED_BASE 0x440AB80ull +#define DCORE2_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_DBG_HBW_BASE 0x440AC00ull +#define DCORE2_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC0_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC0_QM_DBG_LBW_BASE 0x440AC80ull +#define DCORE2_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC0_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_TPC0_QM_CGM_BASE 0x440AD80ull +#define DCORE2_TPC0_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC0_QM_CGM_SECTION 0x1000 +#define mmDCORE2_TPC0_QM_SPECIAL_BASE 0x440AE80ull +#define DCORE2_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC0_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x440B000ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC0_CFG_BASE 0x440B000ull +#define DCORE2_TPC0_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_CFG_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x440B050ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x440B0A0ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x440B0F0ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x440B140ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x440B190ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x440B1E0ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x440B230ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x440B280ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x440B2D0ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x440B320ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x440B370ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x440B3C0ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x440B410ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x440B460ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x440B4B0ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x440B500ull +#define DCORE2_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC0_CFG_KERNEL_BASE 0x440B508ull +#define DCORE2_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC0_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_0_BASE 0x440B5DCull +#define DCORE2_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_1_BASE 0x440B62Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_2_BASE 0x440B67Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_3_BASE 0x440B6CCull +#define DCORE2_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_4_BASE 0x440B71Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_5_BASE 0x440B76Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_6_BASE 0x440B7BCull +#define DCORE2_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_7_BASE 0x440B80Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_8_BASE 0x440B85Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_9_BASE 0x440B8ACull +#define DCORE2_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_10_BASE 0x440B8FCull +#define DCORE2_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_11_BASE 0x440B94Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_12_BASE 0x440B99Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_13_BASE 0x440B9ECull +#define DCORE2_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_14_BASE 0x440BA3Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_TENSOR_15_BASE 0x440BA8Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x440BADCull +#define DCORE2_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC0_CFG_QM_BASE 0x440BAE4ull +#define DCORE2_TPC0_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC0_CFG_QM_SECTION 0x31C0 +#define mmDCORE2_TPC0_CFG_AXUSER_BASE 0x440BE00ull +#define DCORE2_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC0_CFG_SPECIAL_BASE 0x440BE80ull +#define DCORE2_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC0_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x440C000ull +#define DCORE2_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x440C200ull +#define DCORE2_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x440C400ull +#define DCORE2_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x440C600ull +#define DCORE2_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_TPC0_MSTR_IF_E2E_CRDT_BASE 0x440C800ull +#define DCORE2_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_TPC0_MSTR_IF_AXUSER_BASE 0x440CA80ull +#define DCORE2_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC0_MSTR_IF_DBG_HBW_BASE 0x440CB00ull +#define DCORE2_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC0_MSTR_IF_DBG_LBW_BASE 0x440CB80ull +#define DCORE2_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_TPC0_MSTR_IF_CORE_HBW_BASE 0x440CC00ull +#define DCORE2_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_TPC0_MSTR_IF_CORE_LBW_BASE 0x440CD80ull +#define DCORE2_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_TPC0_MSTR_IF_SPECIAL_BASE 0x440CE80ull +#define DCORE2_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE2_TPC1_QM_DCCM_BASE 0x4410000ull +#define DCORE2_TPC1_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC1_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_ARC_AUX_BASE 0x4418000ull +#define DCORE2_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE2_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x4418E80ull +#define DCORE2_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_TPC1_QM_BASE 0x441A000ull +#define DCORE2_TPC1_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_QM_SECTION 0x9000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x441A900ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x441A908ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x441A910ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x441A918ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x441A920ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x441A928ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x441A930ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x441A938ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x441A940ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x441A948ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x441A950ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x441A958ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x441A960ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x441A968ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x441A970ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x441A978ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_TPC1_QM_AXUSER_SECURED_BASE 0x441AB00ull +#define DCORE2_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_AXUSER_NONSECURED_BASE 0x441AB80ull +#define DCORE2_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_DBG_HBW_BASE 0x441AC00ull +#define DCORE2_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC1_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC1_QM_DBG_LBW_BASE 0x441AC80ull +#define DCORE2_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC1_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_TPC1_QM_CGM_BASE 0x441AD80ull +#define DCORE2_TPC1_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC1_QM_CGM_SECTION 0x1000 +#define mmDCORE2_TPC1_QM_SPECIAL_BASE 0x441AE80ull +#define DCORE2_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC1_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x441B000ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC1_CFG_BASE 0x441B000ull +#define DCORE2_TPC1_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_CFG_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x441B050ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x441B0A0ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x441B0F0ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x441B140ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x441B190ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x441B1E0ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x441B230ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x441B280ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x441B2D0ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x441B320ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x441B370ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x441B3C0ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x441B410ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x441B460ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x441B4B0ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x441B500ull +#define DCORE2_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC1_CFG_KERNEL_BASE 0x441B508ull +#define DCORE2_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC1_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_0_BASE 0x441B5DCull +#define DCORE2_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_1_BASE 0x441B62Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_2_BASE 0x441B67Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_3_BASE 0x441B6CCull +#define DCORE2_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_4_BASE 0x441B71Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_5_BASE 0x441B76Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_6_BASE 0x441B7BCull +#define DCORE2_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_7_BASE 0x441B80Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_8_BASE 0x441B85Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_9_BASE 0x441B8ACull +#define DCORE2_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_10_BASE 0x441B8FCull +#define DCORE2_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_11_BASE 0x441B94Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_12_BASE 0x441B99Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_13_BASE 0x441B9ECull +#define DCORE2_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_14_BASE 0x441BA3Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_TENSOR_15_BASE 0x441BA8Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x441BADCull +#define DCORE2_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC1_CFG_QM_BASE 0x441BAE4ull +#define DCORE2_TPC1_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC1_CFG_QM_SECTION 0x31C0 +#define mmDCORE2_TPC1_CFG_AXUSER_BASE 0x441BE00ull +#define DCORE2_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC1_CFG_SPECIAL_BASE 0x441BE80ull +#define DCORE2_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC1_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x441C000ull +#define DCORE2_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x441C200ull +#define DCORE2_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x441C400ull +#define DCORE2_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x441C600ull +#define DCORE2_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_TPC1_MSTR_IF_E2E_CRDT_BASE 0x441C800ull +#define DCORE2_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_TPC1_MSTR_IF_AXUSER_BASE 0x441CA80ull +#define DCORE2_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC1_MSTR_IF_DBG_HBW_BASE 0x441CB00ull +#define DCORE2_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC1_MSTR_IF_DBG_LBW_BASE 0x441CB80ull +#define DCORE2_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_TPC1_MSTR_IF_CORE_HBW_BASE 0x441CC00ull +#define DCORE2_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_TPC1_MSTR_IF_CORE_LBW_BASE 0x441CD80ull +#define DCORE2_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_TPC1_MSTR_IF_SPECIAL_BASE 0x441CE80ull +#define DCORE2_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE2_TPC2_QM_DCCM_BASE 0x4420000ull +#define DCORE2_TPC2_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC2_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_ARC_AUX_BASE 0x4428000ull +#define DCORE2_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE2_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x4428E80ull +#define DCORE2_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_TPC2_QM_BASE 0x442A000ull +#define DCORE2_TPC2_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_QM_SECTION 0x9000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x442A900ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x442A908ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x442A910ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x442A918ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x442A920ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x442A928ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x442A930ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x442A938ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x442A940ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x442A948ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x442A950ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x442A958ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x442A960ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x442A968ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x442A970ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x442A978ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_TPC2_QM_AXUSER_SECURED_BASE 0x442AB00ull +#define DCORE2_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_AXUSER_NONSECURED_BASE 0x442AB80ull +#define DCORE2_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_DBG_HBW_BASE 0x442AC00ull +#define DCORE2_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC2_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC2_QM_DBG_LBW_BASE 0x442AC80ull +#define DCORE2_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC2_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_TPC2_QM_CGM_BASE 0x442AD80ull +#define DCORE2_TPC2_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC2_QM_CGM_SECTION 0x1000 +#define mmDCORE2_TPC2_QM_SPECIAL_BASE 0x442AE80ull +#define DCORE2_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC2_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x442B000ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC2_CFG_BASE 0x442B000ull +#define DCORE2_TPC2_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_CFG_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x442B050ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x442B0A0ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x442B0F0ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x442B140ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x442B190ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x442B1E0ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x442B230ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x442B280ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x442B2D0ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x442B320ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x442B370ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x442B3C0ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x442B410ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x442B460ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x442B4B0ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x442B500ull +#define DCORE2_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC2_CFG_KERNEL_BASE 0x442B508ull +#define DCORE2_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC2_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_0_BASE 0x442B5DCull +#define DCORE2_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_1_BASE 0x442B62Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_2_BASE 0x442B67Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_3_BASE 0x442B6CCull +#define DCORE2_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_4_BASE 0x442B71Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_5_BASE 0x442B76Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_6_BASE 0x442B7BCull +#define DCORE2_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_7_BASE 0x442B80Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_8_BASE 0x442B85Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_9_BASE 0x442B8ACull +#define DCORE2_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_10_BASE 0x442B8FCull +#define DCORE2_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_11_BASE 0x442B94Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_12_BASE 0x442B99Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_13_BASE 0x442B9ECull +#define DCORE2_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_14_BASE 0x442BA3Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_TENSOR_15_BASE 0x442BA8Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x442BADCull +#define DCORE2_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC2_CFG_QM_BASE 0x442BAE4ull +#define DCORE2_TPC2_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC2_CFG_QM_SECTION 0x31C0 +#define mmDCORE2_TPC2_CFG_AXUSER_BASE 0x442BE00ull +#define DCORE2_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC2_CFG_SPECIAL_BASE 0x442BE80ull +#define DCORE2_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC2_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x442C000ull +#define DCORE2_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x442C200ull +#define DCORE2_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x442C400ull +#define DCORE2_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x442C600ull +#define DCORE2_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_TPC2_MSTR_IF_E2E_CRDT_BASE 0x442C800ull +#define DCORE2_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_TPC2_MSTR_IF_AXUSER_BASE 0x442CA80ull +#define DCORE2_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC2_MSTR_IF_DBG_HBW_BASE 0x442CB00ull +#define DCORE2_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC2_MSTR_IF_DBG_LBW_BASE 0x442CB80ull +#define DCORE2_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_TPC2_MSTR_IF_CORE_HBW_BASE 0x442CC00ull +#define DCORE2_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_TPC2_MSTR_IF_CORE_LBW_BASE 0x442CD80ull +#define DCORE2_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_TPC2_MSTR_IF_SPECIAL_BASE 0x442CE80ull +#define DCORE2_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE2_TPC3_QM_DCCM_BASE 0x4430000ull +#define DCORE2_TPC3_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC3_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_ARC_AUX_BASE 0x4438000ull +#define DCORE2_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE2_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x4438E80ull +#define DCORE2_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_TPC3_QM_BASE 0x443A000ull +#define DCORE2_TPC3_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_QM_SECTION 0x9000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x443A900ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x443A908ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x443A910ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x443A918ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x443A920ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x443A928ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x443A930ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x443A938ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x443A940ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x443A948ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x443A950ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x443A958ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x443A960ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x443A968ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x443A970ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x443A978ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_TPC3_QM_AXUSER_SECURED_BASE 0x443AB00ull +#define DCORE2_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_AXUSER_NONSECURED_BASE 0x443AB80ull +#define DCORE2_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_DBG_HBW_BASE 0x443AC00ull +#define DCORE2_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC3_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC3_QM_DBG_LBW_BASE 0x443AC80ull +#define DCORE2_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC3_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_TPC3_QM_CGM_BASE 0x443AD80ull +#define DCORE2_TPC3_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC3_QM_CGM_SECTION 0x1000 +#define mmDCORE2_TPC3_QM_SPECIAL_BASE 0x443AE80ull +#define DCORE2_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC3_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x443B000ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC3_CFG_BASE 0x443B000ull +#define DCORE2_TPC3_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_CFG_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x443B050ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x443B0A0ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x443B0F0ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x443B140ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x443B190ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x443B1E0ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x443B230ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x443B280ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x443B2D0ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x443B320ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x443B370ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x443B3C0ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x443B410ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x443B460ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x443B4B0ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x443B500ull +#define DCORE2_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC3_CFG_KERNEL_BASE 0x443B508ull +#define DCORE2_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC3_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_0_BASE 0x443B5DCull +#define DCORE2_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_1_BASE 0x443B62Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_2_BASE 0x443B67Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_3_BASE 0x443B6CCull +#define DCORE2_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_4_BASE 0x443B71Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_5_BASE 0x443B76Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_6_BASE 0x443B7BCull +#define DCORE2_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_7_BASE 0x443B80Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_8_BASE 0x443B85Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_9_BASE 0x443B8ACull +#define DCORE2_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_10_BASE 0x443B8FCull +#define DCORE2_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_11_BASE 0x443B94Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_12_BASE 0x443B99Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_13_BASE 0x443B9ECull +#define DCORE2_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_14_BASE 0x443BA3Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_TENSOR_15_BASE 0x443BA8Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x443BADCull +#define DCORE2_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC3_CFG_QM_BASE 0x443BAE4ull +#define DCORE2_TPC3_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC3_CFG_QM_SECTION 0x31C0 +#define mmDCORE2_TPC3_CFG_AXUSER_BASE 0x443BE00ull +#define DCORE2_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC3_CFG_SPECIAL_BASE 0x443BE80ull +#define DCORE2_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC3_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x443C000ull +#define DCORE2_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x443C200ull +#define DCORE2_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x443C400ull +#define DCORE2_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x443C600ull +#define DCORE2_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_TPC3_MSTR_IF_E2E_CRDT_BASE 0x443C800ull +#define DCORE2_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_TPC3_MSTR_IF_AXUSER_BASE 0x443CA80ull +#define DCORE2_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC3_MSTR_IF_DBG_HBW_BASE 0x443CB00ull +#define DCORE2_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC3_MSTR_IF_DBG_LBW_BASE 0x443CB80ull +#define DCORE2_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_TPC3_MSTR_IF_CORE_HBW_BASE 0x443CC00ull +#define DCORE2_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_TPC3_MSTR_IF_CORE_LBW_BASE 0x443CD80ull +#define DCORE2_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_TPC3_MSTR_IF_SPECIAL_BASE 0x443CE80ull +#define DCORE2_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE2_TPC4_QM_DCCM_BASE 0x4440000ull +#define DCORE2_TPC4_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC4_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_ARC_AUX_BASE 0x4448000ull +#define DCORE2_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE2_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x4448E80ull +#define DCORE2_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_TPC4_QM_BASE 0x444A000ull +#define DCORE2_TPC4_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_QM_SECTION 0x9000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x444A900ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x444A908ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x444A910ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x444A918ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x444A920ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x444A928ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x444A930ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x444A938ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x444A940ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x444A948ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x444A950ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x444A958ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x444A960ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x444A968ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x444A970ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x444A978ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_TPC4_QM_AXUSER_SECURED_BASE 0x444AB00ull +#define DCORE2_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_AXUSER_NONSECURED_BASE 0x444AB80ull +#define DCORE2_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_DBG_HBW_BASE 0x444AC00ull +#define DCORE2_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC4_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC4_QM_DBG_LBW_BASE 0x444AC80ull +#define DCORE2_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC4_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_TPC4_QM_CGM_BASE 0x444AD80ull +#define DCORE2_TPC4_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC4_QM_CGM_SECTION 0x1000 +#define mmDCORE2_TPC4_QM_SPECIAL_BASE 0x444AE80ull +#define DCORE2_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC4_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x444B000ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC4_CFG_BASE 0x444B000ull +#define DCORE2_TPC4_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_CFG_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x444B050ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x444B0A0ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x444B0F0ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x444B140ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x444B190ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x444B1E0ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x444B230ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x444B280ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x444B2D0ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x444B320ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x444B370ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x444B3C0ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x444B410ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x444B460ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x444B4B0ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x444B500ull +#define DCORE2_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC4_CFG_KERNEL_BASE 0x444B508ull +#define DCORE2_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC4_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_0_BASE 0x444B5DCull +#define DCORE2_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_1_BASE 0x444B62Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_2_BASE 0x444B67Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_3_BASE 0x444B6CCull +#define DCORE2_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_4_BASE 0x444B71Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_5_BASE 0x444B76Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_6_BASE 0x444B7BCull +#define DCORE2_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_7_BASE 0x444B80Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_8_BASE 0x444B85Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_9_BASE 0x444B8ACull +#define DCORE2_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_10_BASE 0x444B8FCull +#define DCORE2_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_11_BASE 0x444B94Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_12_BASE 0x444B99Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_13_BASE 0x444B9ECull +#define DCORE2_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_14_BASE 0x444BA3Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_TENSOR_15_BASE 0x444BA8Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x444BADCull +#define DCORE2_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC4_CFG_QM_BASE 0x444BAE4ull +#define DCORE2_TPC4_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC4_CFG_QM_SECTION 0x31C0 +#define mmDCORE2_TPC4_CFG_AXUSER_BASE 0x444BE00ull +#define DCORE2_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC4_CFG_SPECIAL_BASE 0x444BE80ull +#define DCORE2_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC4_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x444C000ull +#define DCORE2_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x444C200ull +#define DCORE2_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x444C400ull +#define DCORE2_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x444C600ull +#define DCORE2_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_TPC4_MSTR_IF_E2E_CRDT_BASE 0x444C800ull +#define DCORE2_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_TPC4_MSTR_IF_AXUSER_BASE 0x444CA80ull +#define DCORE2_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC4_MSTR_IF_DBG_HBW_BASE 0x444CB00ull +#define DCORE2_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC4_MSTR_IF_DBG_LBW_BASE 0x444CB80ull +#define DCORE2_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_TPC4_MSTR_IF_CORE_HBW_BASE 0x444CC00ull +#define DCORE2_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_TPC4_MSTR_IF_CORE_LBW_BASE 0x444CD80ull +#define DCORE2_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_TPC4_MSTR_IF_SPECIAL_BASE 0x444CE80ull +#define DCORE2_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE2_TPC5_QM_DCCM_BASE 0x4450000ull +#define DCORE2_TPC5_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC5_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_ARC_AUX_BASE 0x4458000ull +#define DCORE2_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE2_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x4458E80ull +#define DCORE2_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_TPC5_QM_BASE 0x445A000ull +#define DCORE2_TPC5_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_QM_SECTION 0x9000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x445A900ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x445A908ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x445A910ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x445A918ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x445A920ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x445A928ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x445A930ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x445A938ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x445A940ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x445A948ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x445A950ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x445A958ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x445A960ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x445A968ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x445A970ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x445A978ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_TPC5_QM_AXUSER_SECURED_BASE 0x445AB00ull +#define DCORE2_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_AXUSER_NONSECURED_BASE 0x445AB80ull +#define DCORE2_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_DBG_HBW_BASE 0x445AC00ull +#define DCORE2_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC5_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC5_QM_DBG_LBW_BASE 0x445AC80ull +#define DCORE2_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC5_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_TPC5_QM_CGM_BASE 0x445AD80ull +#define DCORE2_TPC5_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC5_QM_CGM_SECTION 0x1000 +#define mmDCORE2_TPC5_QM_SPECIAL_BASE 0x445AE80ull +#define DCORE2_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC5_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x445B000ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC5_CFG_BASE 0x445B000ull +#define DCORE2_TPC5_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_CFG_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x445B050ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x445B0A0ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x445B0F0ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x445B140ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x445B190ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x445B1E0ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x445B230ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x445B280ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x445B2D0ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x445B320ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x445B370ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x445B3C0ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x445B410ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x445B460ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x445B4B0ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x445B500ull +#define DCORE2_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC5_CFG_KERNEL_BASE 0x445B508ull +#define DCORE2_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC5_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_0_BASE 0x445B5DCull +#define DCORE2_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_1_BASE 0x445B62Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_2_BASE 0x445B67Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_3_BASE 0x445B6CCull +#define DCORE2_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_4_BASE 0x445B71Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_5_BASE 0x445B76Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_6_BASE 0x445B7BCull +#define DCORE2_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_7_BASE 0x445B80Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_8_BASE 0x445B85Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_9_BASE 0x445B8ACull +#define DCORE2_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_10_BASE 0x445B8FCull +#define DCORE2_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_11_BASE 0x445B94Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_12_BASE 0x445B99Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_13_BASE 0x445B9ECull +#define DCORE2_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_14_BASE 0x445BA3Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_TENSOR_15_BASE 0x445BA8Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE2_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x445BADCull +#define DCORE2_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE2_TPC5_CFG_QM_BASE 0x445BAE4ull +#define DCORE2_TPC5_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC5_CFG_QM_SECTION 0x31C0 +#define mmDCORE2_TPC5_CFG_AXUSER_BASE 0x445BE00ull +#define DCORE2_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC5_CFG_SPECIAL_BASE 0x445BE80ull +#define DCORE2_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC5_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x445C000ull +#define DCORE2_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x445C200ull +#define DCORE2_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x445C400ull +#define DCORE2_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x445C600ull +#define DCORE2_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_TPC5_MSTR_IF_E2E_CRDT_BASE 0x445C800ull +#define DCORE2_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_TPC5_MSTR_IF_AXUSER_BASE 0x445CA80ull +#define DCORE2_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_TPC5_MSTR_IF_DBG_HBW_BASE 0x445CB00ull +#define DCORE2_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_TPC5_MSTR_IF_DBG_LBW_BASE 0x445CB80ull +#define DCORE2_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_TPC5_MSTR_IF_CORE_HBW_BASE 0x445CC00ull +#define DCORE2_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_TPC5_MSTR_IF_CORE_LBW_BASE 0x445CD80ull +#define DCORE2_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_TPC5_MSTR_IF_SPECIAL_BASE 0x445CE80ull +#define DCORE2_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC5_MSTR_IF_SPECIAL_SECTION 0x23180 +#define mmDCORE2_HMMU0_MMU_BASE 0x4480000ull +#define DCORE2_HMMU0_MMU_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_MMU_SECTION 0xE800 +#define mmDCORE2_HMMU0_MMU_SPECIAL_BASE 0x4480E80ull +#define DCORE2_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU0_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE2_HMMU0_STLB_BASE 0x4481000ull +#define DCORE2_HMMU0_STLB_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_STLB_SECTION 0xE800 +#define mmDCORE2_HMMU0_STLB_SPECIAL_BASE 0x4481E80ull +#define DCORE2_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU0_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE2_HMMU0_SCRAMB_OUT_BASE 0x4483000ull +#define DCORE2_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE2_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x4483E80ull +#define DCORE2_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE2_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x4484000ull +#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x4484200ull +#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x4484400ull +#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x4484600ull +#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x4484800ull +#define DCORE2_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_HMMU0_MSTR_IF_AXUSER_BASE 0x4484A80ull +#define DCORE2_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_HMMU0_MSTR_IF_DBG_HBW_BASE 0x4484B00ull +#define DCORE2_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_HMMU0_MSTR_IF_DBG_LBW_BASE 0x4484B80ull +#define DCORE2_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_HMMU0_MSTR_IF_CORE_HBW_BASE 0x4484C00ull +#define DCORE2_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_HMMU0_MSTR_IF_CORE_LBW_BASE 0x4484D80ull +#define DCORE2_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_HMMU0_MSTR_IF_SPECIAL_BASE 0x4484E80ull +#define DCORE2_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE2_HMMU1_MMU_BASE 0x4490000ull +#define DCORE2_HMMU1_MMU_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_MMU_SECTION 0xE800 +#define mmDCORE2_HMMU1_MMU_SPECIAL_BASE 0x4490E80ull +#define DCORE2_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU1_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE2_HMMU1_STLB_BASE 0x4491000ull +#define DCORE2_HMMU1_STLB_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_STLB_SECTION 0xE800 +#define mmDCORE2_HMMU1_STLB_SPECIAL_BASE 0x4491E80ull +#define DCORE2_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU1_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE2_HMMU1_SCRAMB_OUT_BASE 0x4493000ull +#define DCORE2_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE2_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x4493E80ull +#define DCORE2_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE2_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x4494000ull +#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x4494200ull +#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x4494400ull +#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x4494600ull +#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x4494800ull +#define DCORE2_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_HMMU1_MSTR_IF_AXUSER_BASE 0x4494A80ull +#define DCORE2_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_HMMU1_MSTR_IF_DBG_HBW_BASE 0x4494B00ull +#define DCORE2_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_HMMU1_MSTR_IF_DBG_LBW_BASE 0x4494B80ull +#define DCORE2_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_HMMU1_MSTR_IF_CORE_HBW_BASE 0x4494C00ull +#define DCORE2_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_HMMU1_MSTR_IF_CORE_LBW_BASE 0x4494D80ull +#define DCORE2_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_HMMU1_MSTR_IF_SPECIAL_BASE 0x4494E80ull +#define DCORE2_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE2_HMMU2_MMU_BASE 0x44A0000ull +#define DCORE2_HMMU2_MMU_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_MMU_SECTION 0xE800 +#define mmDCORE2_HMMU2_MMU_SPECIAL_BASE 0x44A0E80ull +#define DCORE2_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU2_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE2_HMMU2_STLB_BASE 0x44A1000ull +#define DCORE2_HMMU2_STLB_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_STLB_SECTION 0xE800 +#define mmDCORE2_HMMU2_STLB_SPECIAL_BASE 0x44A1E80ull +#define DCORE2_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU2_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE2_HMMU2_SCRAMB_OUT_BASE 0x44A3000ull +#define DCORE2_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE2_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x44A3E80ull +#define DCORE2_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE2_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x44A4000ull +#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x44A4200ull +#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x44A4400ull +#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x44A4600ull +#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x44A4800ull +#define DCORE2_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_HMMU2_MSTR_IF_AXUSER_BASE 0x44A4A80ull +#define DCORE2_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_HMMU2_MSTR_IF_DBG_HBW_BASE 0x44A4B00ull +#define DCORE2_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_HMMU2_MSTR_IF_DBG_LBW_BASE 0x44A4B80ull +#define DCORE2_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_HMMU2_MSTR_IF_CORE_HBW_BASE 0x44A4C00ull +#define DCORE2_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_HMMU2_MSTR_IF_CORE_LBW_BASE 0x44A4D80ull +#define DCORE2_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_HMMU2_MSTR_IF_SPECIAL_BASE 0x44A4E80ull +#define DCORE2_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE2_HMMU3_MMU_BASE 0x44B0000ull +#define DCORE2_HMMU3_MMU_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_MMU_SECTION 0xE800 +#define mmDCORE2_HMMU3_MMU_SPECIAL_BASE 0x44B0E80ull +#define DCORE2_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU3_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE2_HMMU3_STLB_BASE 0x44B1000ull +#define DCORE2_HMMU3_STLB_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_STLB_SECTION 0xE800 +#define mmDCORE2_HMMU3_STLB_SPECIAL_BASE 0x44B1E80ull +#define DCORE2_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU3_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE2_HMMU3_SCRAMB_OUT_BASE 0x44B3000ull +#define DCORE2_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE2_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x44B3E80ull +#define DCORE2_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE2_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x44B4000ull +#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x44B4200ull +#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x44B4400ull +#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x44B4600ull +#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x44B4800ull +#define DCORE2_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_HMMU3_MSTR_IF_AXUSER_BASE 0x44B4A80ull +#define DCORE2_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_HMMU3_MSTR_IF_DBG_HBW_BASE 0x44B4B00ull +#define DCORE2_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_HMMU3_MSTR_IF_DBG_LBW_BASE 0x44B4B80ull +#define DCORE2_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_HMMU3_MSTR_IF_CORE_HBW_BASE 0x44B4C00ull +#define DCORE2_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_HMMU3_MSTR_IF_CORE_LBW_BASE 0x44B4D80ull +#define DCORE2_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_HMMU3_MSTR_IF_SPECIAL_BASE 0x44B4E80ull +#define DCORE2_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE2_MME_QM_ARC_DCCM_BASE 0x44C0000ull +#define DCORE2_MME_QM_ARC_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_MME_QM_ARC_DCCM_SECTION 0x8000 +#define mmDCORE2_MME_QM_ARC_AUX_BASE 0x44C8000ull +#define DCORE2_MME_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_MME_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE2_MME_QM_ARC_AUX_SPECIAL_BASE 0x44C8E80ull +#define DCORE2_MME_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_QM_ARC_AUX_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_QM_ARC_DUP_ENG_BASE 0x44C9000ull +#define DCORE2_MME_QM_ARC_DUP_ENG_MAX_OFFSET 0x1000 +#define DCORE2_MME_QM_ARC_DUP_ENG_SECTION 0x9000 +#define mmDCORE2_MME_QM_ARC_DUP_ENG_AXUSER_BASE 0x44C9900ull +#define DCORE2_MME_QM_ARC_DUP_ENG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_MME_QM_ARC_DUP_ENG_AXUSER_SECTION 0x5800 +#define mmDCORE2_MME_QM_ARC_DUP_ENG_SPECIAL_BASE 0x44C9E80ull +#define DCORE2_MME_QM_ARC_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_QM_ARC_DUP_ENG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_QM_BASE 0x44CA000ull +#define DCORE2_MME_QM_MAX_OFFSET 0x1000 +#define DCORE2_MME_QM_SECTION 0x9000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR0_BASE 0x44CA900ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR1_BASE 0x44CA908ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR2_BASE 0x44CA910ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR3_BASE 0x44CA918ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR4_BASE 0x44CA920ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR5_BASE 0x44CA928ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR6_BASE 0x44CA930ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR7_BASE 0x44CA938ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR8_BASE 0x44CA940ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR9_BASE 0x44CA948ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR10_BASE 0x44CA950ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR11_BASE 0x44CA958ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR12_BASE 0x44CA960ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR13_BASE 0x44CA968ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR14_BASE 0x44CA970ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR15_BASE 0x44CA978ull +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_MME_QM_AXUSER_SECURED_BASE 0x44CAB00ull +#define DCORE2_MME_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_MME_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_MME_QM_AXUSER_NONSECURED_BASE 0x44CAB80ull +#define DCORE2_MME_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_MME_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_MME_QM_DBG_HBW_BASE 0x44CAC00ull +#define DCORE2_MME_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_MME_QM_DBG_LBW_BASE 0x44CAC80ull +#define DCORE2_MME_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_MME_QM_CGM_BASE 0x44CAD80ull +#define DCORE2_MME_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_MME_QM_CGM_SECTION 0x1000 +#define mmDCORE2_MME_QM_SPECIAL_BASE 0x44CAE80ull +#define DCORE2_MME_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_LO_BASE 0x44CB000ull +#define DCORE2_MME_CTRL_LO_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_LO_SECTION 0x8000 +#define mmDCORE2_MME_CTRL_LO_ARCH_BASE_ADDR_BASE 0x44CB008ull +#define DCORE2_MME_CTRL_LO_ARCH_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE2_MME_CTRL_LO_ARCH_BASE_ADDR_SECTION 0x2000 +#define mmDCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE 0x44CB028ull +#define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_LO_ARCH_TENSOR_A_BASE 0x44CB040ull +#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_A_SECTION 0x5800 +#define mmDCORE2_MME_CTRL_LO_ARCH_TENSOR_B_BASE 0x44CB098ull +#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_B_SECTION 0x5800 +#define mmDCORE2_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE 0x44CB0F0ull +#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE 0x44CB15Cull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE 0x44CB170ull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE 0x44CB184ull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE 0x44CB198ull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE 0x44CB1ACull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE 0x44CB1C0ull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE 0x44CB1D4ull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE 0x44CB1E8ull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE 0x44CB1FCull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE 0x44CB210ull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE 0x44CB22Cull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE 0x44CB240ull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE 0x44CB254ull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE 0x44CB268ull +#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE 0x44CB280ull +#define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_END_SECTION 0xB800 +#define mmDCORE2_MME_CTRL_LO_MME_AXUSER_BASE 0x44CBE00ull +#define DCORE2_MME_CTRL_LO_MME_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_MME_CTRL_LO_MME_AXUSER_SECTION 0x8000 +#define mmDCORE2_MME_CTRL_LO_SPECIAL_BASE 0x44CBE80ull +#define DCORE2_MME_CTRL_LO_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_CTRL_LO_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_HI_BASE 0x44CC000ull +#define DCORE2_MME_CTRL_HI_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_HI_SECTION 0x8000 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_BASE_ADDR_BASE 0x44CC008ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE2_MME_CTRL_HI_SHADOW_0_BASE_ADDR_SECTION 0x2000 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_BASE 0x44CC028ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_A_BASE 0x44CC040ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_A_SECTION 0x5800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_B_BASE 0x44CC098ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_B_SECTION 0x5800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_BASE 0x44CC0F0ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_BASE 0x44CC15Cull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_BASE 0x44CC170ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_BASE 0x44CC184ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_BASE 0x44CC198ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_BASE 0x44CC1ACull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_BASE 0x44CC1C0ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_BASE 0x44CC1D4ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_BASE 0x44CC1E8ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_BASE 0x44CC1FCull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_BASE 0x44CC210ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_BASE 0x44CC22Cull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_BASE 0x44CC240ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_BASE 0x44CC254ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_BASE 0x44CC268ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_BASE 0x44CC280ull +#define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_SECTION 0x8800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_BASE_ADDR_BASE 0x44CC308ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE2_MME_CTRL_HI_SHADOW_1_BASE_ADDR_SECTION 0x2000 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_BASE 0x44CC328ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_A_BASE 0x44CC340ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_A_SECTION 0x5800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_B_BASE 0x44CC398ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_B_SECTION 0x5800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_BASE 0x44CC3F0ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_BASE 0x44CC45Cull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_BASE 0x44CC470ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_BASE 0x44CC484ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_BASE 0x44CC498ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_BASE 0x44CC4ACull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_BASE 0x44CC4C0ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_BASE 0x44CC4D4ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_BASE 0x44CC4E8ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_BASE 0x44CC4FCull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_BASE 0x44CC510ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_BASE 0x44CC52Cull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_BASE 0x44CC540ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_BASE 0x44CC554ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_BASE 0x44CC568ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_BASE 0x44CC580ull +#define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_SECTION 0x8800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_BASE_ADDR_BASE 0x44CC608ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE2_MME_CTRL_HI_SHADOW_2_BASE_ADDR_SECTION 0x2000 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_BASE 0x44CC628ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_A_BASE 0x44CC640ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_A_SECTION 0x5800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_B_BASE 0x44CC698ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_B_SECTION 0x5800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_BASE 0x44CC6F0ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_BASE 0x44CC75Cull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_BASE 0x44CC770ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_BASE 0x44CC784ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_BASE 0x44CC798ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_BASE 0x44CC7ACull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_BASE 0x44CC7C0ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_BASE 0x44CC7D4ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_BASE 0x44CC7E8ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_BASE 0x44CC7FCull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_BASE 0x44CC810ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_BASE 0x44CC82Cull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_BASE 0x44CC840ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_BASE 0x44CC854ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_BASE 0x44CC868ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_BASE 0x44CC880ull +#define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_SECTION 0x8800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_BASE_ADDR_BASE 0x44CC908ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE2_MME_CTRL_HI_SHADOW_3_BASE_ADDR_SECTION 0x2000 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_BASE 0x44CC928ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_A_BASE 0x44CC940ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_A_SECTION 0x5800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_B_BASE 0x44CC998ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_B_SECTION 0x5800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_BASE 0x44CC9F0ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_BASE 0x44CCA5Cull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_BASE 0x44CCA70ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_BASE 0x44CCA84ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_BASE 0x44CCA98ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_BASE 0x44CCAACull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_BASE 0x44CCAC0ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_BASE 0x44CCAD4ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_BASE 0x44CCAE8ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_BASE 0x44CCAFCull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_BASE 0x44CCB10ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_BASE 0x44CCB2Cull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_BASE 0x44CCB40ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_BASE 0x44CCB54ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_BASE 0x44CCB68ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_BASE 0x44CCB80ull +#define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_SECTION 0x3000 +#define mmDCORE2_MME_CTRL_HI_SPECIAL_BASE 0x44CCE80ull +#define DCORE2_MME_CTRL_HI_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_CTRL_HI_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_EU_BIST_BASE 0x44CD000ull +#define DCORE2_MME_EU_BIST_MAX_OFFSET 0x1000 +#define DCORE2_MME_EU_BIST_SECTION 0xE800 +#define mmDCORE2_MME_EU_BIST_SPECIAL_BASE 0x44CDE80ull +#define DCORE2_MME_EU_BIST_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_EU_BIST_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE 0x44CE000ull +#define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_MME_CTRL_MSTR_IF_RR_PRVT_HBW_BASE 0x44CE200ull +#define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_MME_CTRL_MSTR_IF_RR_SHRD_LBW_BASE 0x44CE400ull +#define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_MME_CTRL_MSTR_IF_RR_PRVT_LBW_BASE 0x44CE600ull +#define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_MME_CTRL_MSTR_IF_E2E_CRDT_BASE 0x44CE800ull +#define DCORE2_MME_CTRL_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_MME_CTRL_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_MME_CTRL_MSTR_IF_AXUSER_BASE 0x44CEA80ull +#define DCORE2_MME_CTRL_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_MME_CTRL_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_MME_CTRL_MSTR_IF_DBG_HBW_BASE 0x44CEB00ull +#define DCORE2_MME_CTRL_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_MME_CTRL_MSTR_IF_DBG_LBW_BASE 0x44CEB80ull +#define DCORE2_MME_CTRL_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_CTRL_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_MME_CTRL_MSTR_IF_CORE_HBW_BASE 0x44CEC00ull +#define DCORE2_MME_CTRL_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_MME_CTRL_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_MME_CTRL_MSTR_IF_CORE_LBW_BASE 0x44CED80ull +#define DCORE2_MME_CTRL_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_MME_CTRL_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_MME_CTRL_MSTR_IF_SPECIAL_BASE 0x44CEE80ull +#define DCORE2_MME_CTRL_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_CTRL_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_QM_ARC_ACP_ENG_BASE 0x44CF000ull +#define DCORE2_MME_QM_ARC_ACP_ENG_MAX_OFFSET 0x1000 +#define DCORE2_MME_QM_ARC_ACP_ENG_SECTION 0xE800 +#define mmDCORE2_MME_QM_ARC_ACP_ENG_SPECIAL_BASE 0x44CFE80ull +#define DCORE2_MME_QM_ARC_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_QM_ARC_ACP_ENG_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_SBTE0_BASE 0x44D0000ull +#define DCORE2_MME_SBTE0_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE0_SECTION 0xE800 +#define mmDCORE2_MME_SBTE0_SPECIAL_BASE 0x44D0E80ull +#define DCORE2_MME_SBTE0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_SBTE0_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE 0x44D1000ull +#define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_BASE 0x44D1200ull +#define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_BASE 0x44D1400ull +#define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_BASE 0x44D1600ull +#define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE0_MSTR_IF_E2E_CRDT_BASE 0x44D1800ull +#define DCORE2_MME_SBTE0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_MME_SBTE0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_MME_SBTE0_MSTR_IF_AXUSER_BASE 0x44D1A80ull +#define DCORE2_MME_SBTE0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_MME_SBTE0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_MME_SBTE0_MSTR_IF_DBG_HBW_BASE 0x44D1B00ull +#define DCORE2_MME_SBTE0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_SBTE0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_MME_SBTE0_MSTR_IF_DBG_LBW_BASE 0x44D1B80ull +#define DCORE2_MME_SBTE0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_SBTE0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_MME_SBTE0_MSTR_IF_CORE_HBW_BASE 0x44D1C00ull +#define DCORE2_MME_SBTE0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_MME_SBTE0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_MME_SBTE0_MSTR_IF_CORE_LBW_BASE 0x44D1D80ull +#define DCORE2_MME_SBTE0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_MME_SBTE0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_MME_SBTE0_MSTR_IF_SPECIAL_BASE 0x44D1E80ull +#define DCORE2_MME_SBTE0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_SBTE0_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE2_MME_SBTE1_BASE 0x44D8000ull +#define DCORE2_MME_SBTE1_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE1_SECTION 0xE800 +#define mmDCORE2_MME_SBTE1_SPECIAL_BASE 0x44D8E80ull +#define DCORE2_MME_SBTE1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_SBTE1_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE 0x44D9000ull +#define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_BASE 0x44D9200ull +#define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_BASE 0x44D9400ull +#define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_BASE 0x44D9600ull +#define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE1_MSTR_IF_E2E_CRDT_BASE 0x44D9800ull +#define DCORE2_MME_SBTE1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_MME_SBTE1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_MME_SBTE1_MSTR_IF_AXUSER_BASE 0x44D9A80ull +#define DCORE2_MME_SBTE1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_MME_SBTE1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_MME_SBTE1_MSTR_IF_DBG_HBW_BASE 0x44D9B00ull +#define DCORE2_MME_SBTE1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_SBTE1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_MME_SBTE1_MSTR_IF_DBG_LBW_BASE 0x44D9B80ull +#define DCORE2_MME_SBTE1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_SBTE1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_MME_SBTE1_MSTR_IF_CORE_HBW_BASE 0x44D9C00ull +#define DCORE2_MME_SBTE1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_MME_SBTE1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_MME_SBTE1_MSTR_IF_CORE_LBW_BASE 0x44D9D80ull +#define DCORE2_MME_SBTE1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_MME_SBTE1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_MME_SBTE1_MSTR_IF_SPECIAL_BASE 0x44D9E80ull +#define DCORE2_MME_SBTE1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_SBTE1_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE2_MME_SBTE2_BASE 0x44E0000ull +#define DCORE2_MME_SBTE2_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE2_SECTION 0xE800 +#define mmDCORE2_MME_SBTE2_SPECIAL_BASE 0x44E0E80ull +#define DCORE2_MME_SBTE2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_SBTE2_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_BASE 0x44E1000ull +#define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_BASE 0x44E1200ull +#define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_BASE 0x44E1400ull +#define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_BASE 0x44E1600ull +#define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE2_MSTR_IF_E2E_CRDT_BASE 0x44E1800ull +#define DCORE2_MME_SBTE2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_MME_SBTE2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_MME_SBTE2_MSTR_IF_AXUSER_BASE 0x44E1A80ull +#define DCORE2_MME_SBTE2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_MME_SBTE2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_MME_SBTE2_MSTR_IF_DBG_HBW_BASE 0x44E1B00ull +#define DCORE2_MME_SBTE2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_SBTE2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_MME_SBTE2_MSTR_IF_DBG_LBW_BASE 0x44E1B80ull +#define DCORE2_MME_SBTE2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_SBTE2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_MME_SBTE2_MSTR_IF_CORE_HBW_BASE 0x44E1C00ull +#define DCORE2_MME_SBTE2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_MME_SBTE2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_MME_SBTE2_MSTR_IF_CORE_LBW_BASE 0x44E1D80ull +#define DCORE2_MME_SBTE2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_MME_SBTE2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_MME_SBTE2_MSTR_IF_SPECIAL_BASE 0x44E1E80ull +#define DCORE2_MME_SBTE2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_SBTE2_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE2_MME_SBTE3_BASE 0x44E8000ull +#define DCORE2_MME_SBTE3_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE3_SECTION 0xE800 +#define mmDCORE2_MME_SBTE3_SPECIAL_BASE 0x44E8E80ull +#define DCORE2_MME_SBTE3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_SBTE3_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_BASE 0x44E9000ull +#define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_BASE 0x44E9200ull +#define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_BASE 0x44E9400ull +#define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_BASE 0x44E9600ull +#define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE3_MSTR_IF_E2E_CRDT_BASE 0x44E9800ull +#define DCORE2_MME_SBTE3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_MME_SBTE3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_MME_SBTE3_MSTR_IF_AXUSER_BASE 0x44E9A80ull +#define DCORE2_MME_SBTE3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_MME_SBTE3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_MME_SBTE3_MSTR_IF_DBG_HBW_BASE 0x44E9B00ull +#define DCORE2_MME_SBTE3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_SBTE3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_MME_SBTE3_MSTR_IF_DBG_LBW_BASE 0x44E9B80ull +#define DCORE2_MME_SBTE3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_SBTE3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_MME_SBTE3_MSTR_IF_CORE_HBW_BASE 0x44E9C00ull +#define DCORE2_MME_SBTE3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_MME_SBTE3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_MME_SBTE3_MSTR_IF_CORE_LBW_BASE 0x44E9D80ull +#define DCORE2_MME_SBTE3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_MME_SBTE3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_MME_SBTE3_MSTR_IF_SPECIAL_BASE 0x44E9E80ull +#define DCORE2_MME_SBTE3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_SBTE3_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE2_MME_SBTE4_BASE 0x44F0000ull +#define DCORE2_MME_SBTE4_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE4_SECTION 0xE800 +#define mmDCORE2_MME_SBTE4_SPECIAL_BASE 0x44F0E80ull +#define DCORE2_MME_SBTE4_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_SBTE4_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_BASE 0x44F1000ull +#define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_BASE 0x44F1200ull +#define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_BASE 0x44F1400ull +#define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_BASE 0x44F1600ull +#define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_MME_SBTE4_MSTR_IF_E2E_CRDT_BASE 0x44F1800ull +#define DCORE2_MME_SBTE4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_MME_SBTE4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_MME_SBTE4_MSTR_IF_AXUSER_BASE 0x44F1A80ull +#define DCORE2_MME_SBTE4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_MME_SBTE4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_MME_SBTE4_MSTR_IF_DBG_HBW_BASE 0x44F1B00ull +#define DCORE2_MME_SBTE4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_SBTE4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_MME_SBTE4_MSTR_IF_DBG_LBW_BASE 0x44F1B80ull +#define DCORE2_MME_SBTE4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_SBTE4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_MME_SBTE4_MSTR_IF_CORE_HBW_BASE 0x44F1C00ull +#define DCORE2_MME_SBTE4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_MME_SBTE4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_MME_SBTE4_MSTR_IF_CORE_LBW_BASE 0x44F1D80ull +#define DCORE2_MME_SBTE4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_MME_SBTE4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_MME_SBTE4_MSTR_IF_SPECIAL_BASE 0x44F1E80ull +#define DCORE2_MME_SBTE4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_SBTE4_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE2_MME_ACC_BASE 0x44F8000ull +#define DCORE2_MME_ACC_MAX_OFFSET 0x1000 +#define DCORE2_MME_ACC_SECTION 0xE800 +#define mmDCORE2_MME_ACC_SPECIAL_BASE 0x44F8E80ull +#define DCORE2_MME_ACC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_ACC_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE 0x44F9000ull +#define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_MME_WB0_MSTR_IF_RR_PRVT_HBW_BASE 0x44F9200ull +#define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_MME_WB0_MSTR_IF_RR_SHRD_LBW_BASE 0x44F9400ull +#define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_MME_WB0_MSTR_IF_RR_PRVT_LBW_BASE 0x44F9600ull +#define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_MME_WB0_MSTR_IF_E2E_CRDT_BASE 0x44F9800ull +#define DCORE2_MME_WB0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_MME_WB0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_MME_WB0_MSTR_IF_AXUSER_BASE 0x44F9A80ull +#define DCORE2_MME_WB0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_MME_WB0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_MME_WB0_MSTR_IF_DBG_HBW_BASE 0x44F9B00ull +#define DCORE2_MME_WB0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_WB0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_MME_WB0_MSTR_IF_DBG_LBW_BASE 0x44F9B80ull +#define DCORE2_MME_WB0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_WB0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_MME_WB0_MSTR_IF_CORE_HBW_BASE 0x44F9C00ull +#define DCORE2_MME_WB0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_MME_WB0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_MME_WB0_MSTR_IF_CORE_LBW_BASE 0x44F9D80ull +#define DCORE2_MME_WB0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_MME_WB0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_MME_WB0_MSTR_IF_SPECIAL_BASE 0x44F9E80ull +#define DCORE2_MME_WB0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_WB0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE2_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE 0x44FA000ull +#define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_MME_WB1_MSTR_IF_RR_PRVT_HBW_BASE 0x44FA200ull +#define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_MME_WB1_MSTR_IF_RR_SHRD_LBW_BASE 0x44FA400ull +#define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_MME_WB1_MSTR_IF_RR_PRVT_LBW_BASE 0x44FA600ull +#define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_MME_WB1_MSTR_IF_E2E_CRDT_BASE 0x44FA800ull +#define DCORE2_MME_WB1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_MME_WB1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_MME_WB1_MSTR_IF_AXUSER_BASE 0x44FAA80ull +#define DCORE2_MME_WB1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_MME_WB1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_MME_WB1_MSTR_IF_DBG_HBW_BASE 0x44FAB00ull +#define DCORE2_MME_WB1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_WB1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_MME_WB1_MSTR_IF_DBG_LBW_BASE 0x44FAB80ull +#define DCORE2_MME_WB1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_MME_WB1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_MME_WB1_MSTR_IF_CORE_HBW_BASE 0x44FAC00ull +#define DCORE2_MME_WB1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_MME_WB1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_MME_WB1_MSTR_IF_CORE_LBW_BASE 0x44FAD80ull +#define DCORE2_MME_WB1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_MME_WB1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_MME_WB1_MSTR_IF_SPECIAL_BASE 0x44FAE80ull +#define DCORE2_MME_WB1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_MME_WB1_MSTR_IF_SPECIAL_SECTION 0x5180 +#define mmDCORE2_SYNC_MNGR_OBJS_BASE 0x4500000ull +#define DCORE2_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00 +#define DCORE2_SYNC_MNGR_OBJS_SECTION 0x1E000 +#define mmDCORE2_SYNC_MNGR_GLBL_BASE 0x451E000ull +#define DCORE2_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000 +#define DCORE2_SYNC_MNGR_GLBL_SECTION 0xE800 +#define mmDCORE2_SYNC_MNGR_GLBL_SPECIAL_BASE 0x451EE80ull +#define DCORE2_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x451F000ull +#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x451F200ull +#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x451F400ull +#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x451F600ull +#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x451F800ull +#define DCORE2_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x451FA80ull +#define DCORE2_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x451FB00ull +#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x451FB80ull +#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x451FC00ull +#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x451FD80ull +#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x451FE80ull +#define DCORE2_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE2_HIF0_BASE 0x4520000ull +#define DCORE2_HIF0_MAX_OFFSET 0x1000 +#define DCORE2_HIF0_SECTION 0xE800 +#define mmDCORE2_HIF0_SPECIAL_BASE 0x4520E80ull +#define DCORE2_HIF0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HIF0_SPECIAL_SECTION 0x3180 +#define mmDCORE2_HIF1_BASE 0x4524000ull +#define DCORE2_HIF1_MAX_OFFSET 0x1000 +#define DCORE2_HIF1_SECTION 0xE800 +#define mmDCORE2_HIF1_SPECIAL_BASE 0x4524E80ull +#define DCORE2_HIF1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HIF1_SPECIAL_SECTION 0x3180 +#define mmDCORE2_HIF2_BASE 0x4528000ull +#define DCORE2_HIF2_MAX_OFFSET 0x1000 +#define DCORE2_HIF2_SECTION 0xE800 +#define mmDCORE2_HIF2_SPECIAL_BASE 0x4528E80ull +#define DCORE2_HIF2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HIF2_SPECIAL_SECTION 0x3180 +#define mmDCORE2_HIF3_BASE 0x452C000ull +#define DCORE2_HIF3_MAX_OFFSET 0x1000 +#define DCORE2_HIF3_SECTION 0xE800 +#define mmDCORE2_HIF3_SPECIAL_BASE 0x452CE80ull +#define DCORE2_HIF3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HIF3_SPECIAL_SECTION 0x13180 +#define mmDCORE2_RTR0_CTRL_BASE 0x4540000ull +#define DCORE2_RTR0_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_RTR0_CTRL_SECTION 0xE800 +#define mmDCORE2_RTR0_CTRL_SPECIAL_BASE 0x4540E80ull +#define DCORE2_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR0_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR0_H3_BASE 0x4541000ull +#define DCORE2_RTR0_H3_MAX_OFFSET 0x1000 +#define DCORE2_RTR0_H3_SECTION 0xE800 +#define mmDCORE2_RTR0_H3_SPECIAL_BASE 0x4541E80ull +#define DCORE2_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR0_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x4542000ull +#define DCORE2_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x4542200ull +#define DCORE2_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x4542400ull +#define DCORE2_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x4542600ull +#define DCORE2_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_RTR0_MSTR_IF_E2E_CRDT_BASE 0x4542800ull +#define DCORE2_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_RTR0_MSTR_IF_AXUSER_BASE 0x4542A80ull +#define DCORE2_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_RTR0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_RTR0_MSTR_IF_DBG_HBW_BASE 0x4542B00ull +#define DCORE2_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_RTR0_MSTR_IF_DBG_LBW_BASE 0x4542B80ull +#define DCORE2_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_RTR0_MSTR_IF_CORE_HBW_BASE 0x4542C00ull +#define DCORE2_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_RTR0_MSTR_IF_CORE_LBW_BASE 0x4542D80ull +#define DCORE2_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_RTR0_MSTR_IF_SPECIAL_BASE 0x4542E80ull +#define DCORE2_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR0_ADD_DEC_HBW_BASE 0x4543000ull +#define DCORE2_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE2_RTR0_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE2_RTR0_ADD_DEC_LBW_BASE 0x4543400ull +#define DCORE2_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE2_RTR0_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE2_RTR0_ADD_DEC_SPECIAL_BASE 0x4543E80ull +#define DCORE2_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR0_BASE 0x4544000ull +#define DCORE2_RTR0_MAX_OFFSET 0x1000 +#define DCORE2_RTR0_SECTION 0x3000 +#define mmDCORE2_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x4544300ull +#define DCORE2_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR0_HBW_RD_RS_LL_STAT_BASE 0x4544340ull +#define DCORE2_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x4544380ull +#define DCORE2_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR0_HBW_WR_RS_LL_STAT_BASE 0x45443C0ull +#define DCORE2_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x4544400ull +#define DCORE2_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR0_LBW_RD_RS_LL_STAT_BASE 0x4544440ull +#define DCORE2_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x4544480ull +#define DCORE2_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR0_LBW_WR_RS_LL_STAT_BASE 0x45444C0ull +#define DCORE2_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR0_HBW_MFIFO_BASE 0x4544500ull +#define DCORE2_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE2_RTR0_E2E_RD_LL_STAT_BASE 0x4544540ull +#define DCORE2_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR0_E2E_WR_LL_STAT_BASE 0x4544580ull +#define DCORE2_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE2_RTR0_RTR_HBW_XACT_STAT_BASE 0x4544600ull +#define DCORE2_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR0_RTR_LBW_XACT_STAT_BASE 0x4544680ull +#define DCORE2_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR0_RTR_E2E_XACT_STAT_BASE 0x4544700ull +#define DCORE2_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE2_RTR0_SPECIAL_BASE 0x4544E80ull +#define DCORE2_RTR0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR0_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR0_DBG_ADDR_BASE 0x4545000ull +#define DCORE2_RTR0_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE2_RTR0_DBG_ADDR_SECTION 0xE800 +#define mmDCORE2_RTR0_DBG_ADDR_SPECIAL_BASE 0x4545E80ull +#define DCORE2_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE2_RTR1_CTRL_BASE 0x4548000ull +#define DCORE2_RTR1_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_RTR1_CTRL_SECTION 0xE800 +#define mmDCORE2_RTR1_CTRL_SPECIAL_BASE 0x4548E80ull +#define DCORE2_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR1_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR1_H3_BASE 0x4549000ull +#define DCORE2_RTR1_H3_MAX_OFFSET 0x1000 +#define DCORE2_RTR1_H3_SECTION 0xE800 +#define mmDCORE2_RTR1_H3_SPECIAL_BASE 0x4549E80ull +#define DCORE2_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR1_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x454A000ull +#define DCORE2_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x454A200ull +#define DCORE2_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x454A400ull +#define DCORE2_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x454A600ull +#define DCORE2_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_RTR1_MSTR_IF_E2E_CRDT_BASE 0x454A800ull +#define DCORE2_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_RTR1_MSTR_IF_AXUSER_BASE 0x454AA80ull +#define DCORE2_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_RTR1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_RTR1_MSTR_IF_DBG_HBW_BASE 0x454AB00ull +#define DCORE2_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_RTR1_MSTR_IF_DBG_LBW_BASE 0x454AB80ull +#define DCORE2_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_RTR1_MSTR_IF_CORE_HBW_BASE 0x454AC00ull +#define DCORE2_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_RTR1_MSTR_IF_CORE_LBW_BASE 0x454AD80ull +#define DCORE2_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_RTR1_MSTR_IF_SPECIAL_BASE 0x454AE80ull +#define DCORE2_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR1_ADD_DEC_HBW_BASE 0x454B000ull +#define DCORE2_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE2_RTR1_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE2_RTR1_ADD_DEC_LBW_BASE 0x454B400ull +#define DCORE2_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE2_RTR1_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE2_RTR1_ADD_DEC_SPECIAL_BASE 0x454BE80ull +#define DCORE2_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR1_BASE 0x454C000ull +#define DCORE2_RTR1_MAX_OFFSET 0x1000 +#define DCORE2_RTR1_SECTION 0x3000 +#define mmDCORE2_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x454C300ull +#define DCORE2_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR1_HBW_RD_RS_LL_STAT_BASE 0x454C340ull +#define DCORE2_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x454C380ull +#define DCORE2_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR1_HBW_WR_RS_LL_STAT_BASE 0x454C3C0ull +#define DCORE2_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x454C400ull +#define DCORE2_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR1_LBW_RD_RS_LL_STAT_BASE 0x454C440ull +#define DCORE2_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x454C480ull +#define DCORE2_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR1_LBW_WR_RS_LL_STAT_BASE 0x454C4C0ull +#define DCORE2_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR1_HBW_MFIFO_BASE 0x454C500ull +#define DCORE2_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE2_RTR1_E2E_RD_LL_STAT_BASE 0x454C540ull +#define DCORE2_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR1_E2E_WR_LL_STAT_BASE 0x454C580ull +#define DCORE2_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE2_RTR1_RTR_HBW_XACT_STAT_BASE 0x454C600ull +#define DCORE2_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR1_RTR_LBW_XACT_STAT_BASE 0x454C680ull +#define DCORE2_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR1_RTR_E2E_XACT_STAT_BASE 0x454C700ull +#define DCORE2_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE2_RTR1_SPECIAL_BASE 0x454CE80ull +#define DCORE2_RTR1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR1_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR1_DBG_ADDR_BASE 0x454D000ull +#define DCORE2_RTR1_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE2_RTR1_DBG_ADDR_SECTION 0xE800 +#define mmDCORE2_RTR1_DBG_ADDR_SPECIAL_BASE 0x454DE80ull +#define DCORE2_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE2_RTR2_CTRL_BASE 0x4550000ull +#define DCORE2_RTR2_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_RTR2_CTRL_SECTION 0xE800 +#define mmDCORE2_RTR2_CTRL_SPECIAL_BASE 0x4550E80ull +#define DCORE2_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR2_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR2_H3_BASE 0x4551000ull +#define DCORE2_RTR2_H3_MAX_OFFSET 0x1000 +#define DCORE2_RTR2_H3_SECTION 0xE800 +#define mmDCORE2_RTR2_H3_SPECIAL_BASE 0x4551E80ull +#define DCORE2_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR2_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x4552000ull +#define DCORE2_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x4552200ull +#define DCORE2_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x4552400ull +#define DCORE2_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x4552600ull +#define DCORE2_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_RTR2_MSTR_IF_E2E_CRDT_BASE 0x4552800ull +#define DCORE2_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_RTR2_MSTR_IF_AXUSER_BASE 0x4552A80ull +#define DCORE2_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_RTR2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_RTR2_MSTR_IF_DBG_HBW_BASE 0x4552B00ull +#define DCORE2_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_RTR2_MSTR_IF_DBG_LBW_BASE 0x4552B80ull +#define DCORE2_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_RTR2_MSTR_IF_CORE_HBW_BASE 0x4552C00ull +#define DCORE2_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_RTR2_MSTR_IF_CORE_LBW_BASE 0x4552D80ull +#define DCORE2_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_RTR2_MSTR_IF_SPECIAL_BASE 0x4552E80ull +#define DCORE2_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR2_ADD_DEC_HBW_BASE 0x4553000ull +#define DCORE2_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE2_RTR2_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE2_RTR2_ADD_DEC_LBW_BASE 0x4553400ull +#define DCORE2_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE2_RTR2_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE2_RTR2_ADD_DEC_SPECIAL_BASE 0x4553E80ull +#define DCORE2_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR2_BASE 0x4554000ull +#define DCORE2_RTR2_MAX_OFFSET 0x1000 +#define DCORE2_RTR2_SECTION 0x3000 +#define mmDCORE2_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x4554300ull +#define DCORE2_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR2_HBW_RD_RS_LL_STAT_BASE 0x4554340ull +#define DCORE2_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x4554380ull +#define DCORE2_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR2_HBW_WR_RS_LL_STAT_BASE 0x45543C0ull +#define DCORE2_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x4554400ull +#define DCORE2_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR2_LBW_RD_RS_LL_STAT_BASE 0x4554440ull +#define DCORE2_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x4554480ull +#define DCORE2_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR2_LBW_WR_RS_LL_STAT_BASE 0x45544C0ull +#define DCORE2_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR2_HBW_MFIFO_BASE 0x4554500ull +#define DCORE2_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE2_RTR2_E2E_RD_LL_STAT_BASE 0x4554540ull +#define DCORE2_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR2_E2E_WR_LL_STAT_BASE 0x4554580ull +#define DCORE2_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE2_RTR2_RTR_HBW_XACT_STAT_BASE 0x4554600ull +#define DCORE2_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR2_RTR_LBW_XACT_STAT_BASE 0x4554680ull +#define DCORE2_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR2_RTR_E2E_XACT_STAT_BASE 0x4554700ull +#define DCORE2_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE2_RTR2_SPECIAL_BASE 0x4554E80ull +#define DCORE2_RTR2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR2_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR2_DBG_ADDR_BASE 0x4555000ull +#define DCORE2_RTR2_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE2_RTR2_DBG_ADDR_SECTION 0xE800 +#define mmDCORE2_RTR2_DBG_ADDR_SPECIAL_BASE 0x4555E80ull +#define DCORE2_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE2_RTR3_CTRL_BASE 0x4558000ull +#define DCORE2_RTR3_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_RTR3_CTRL_SECTION 0xE800 +#define mmDCORE2_RTR3_CTRL_SPECIAL_BASE 0x4558E80ull +#define DCORE2_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR3_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR3_H3_BASE 0x4559000ull +#define DCORE2_RTR3_H3_MAX_OFFSET 0x1000 +#define DCORE2_RTR3_H3_SECTION 0xE800 +#define mmDCORE2_RTR3_H3_SPECIAL_BASE 0x4559E80ull +#define DCORE2_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR3_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x455A000ull +#define DCORE2_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x455A200ull +#define DCORE2_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x455A400ull +#define DCORE2_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x455A600ull +#define DCORE2_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_RTR3_MSTR_IF_E2E_CRDT_BASE 0x455A800ull +#define DCORE2_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_RTR3_MSTR_IF_AXUSER_BASE 0x455AA80ull +#define DCORE2_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_RTR3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_RTR3_MSTR_IF_DBG_HBW_BASE 0x455AB00ull +#define DCORE2_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_RTR3_MSTR_IF_DBG_LBW_BASE 0x455AB80ull +#define DCORE2_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_RTR3_MSTR_IF_CORE_HBW_BASE 0x455AC00ull +#define DCORE2_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_RTR3_MSTR_IF_CORE_LBW_BASE 0x455AD80ull +#define DCORE2_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_RTR3_MSTR_IF_SPECIAL_BASE 0x455AE80ull +#define DCORE2_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR3_ADD_DEC_HBW_BASE 0x455B000ull +#define DCORE2_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE2_RTR3_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE2_RTR3_ADD_DEC_LBW_BASE 0x455B400ull +#define DCORE2_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE2_RTR3_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE2_RTR3_ADD_DEC_SPECIAL_BASE 0x455BE80ull +#define DCORE2_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR3_BASE 0x455C000ull +#define DCORE2_RTR3_MAX_OFFSET 0x1000 +#define DCORE2_RTR3_SECTION 0x3000 +#define mmDCORE2_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x455C300ull +#define DCORE2_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR3_HBW_RD_RS_LL_STAT_BASE 0x455C340ull +#define DCORE2_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x455C380ull +#define DCORE2_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR3_HBW_WR_RS_LL_STAT_BASE 0x455C3C0ull +#define DCORE2_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x455C400ull +#define DCORE2_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR3_LBW_RD_RS_LL_STAT_BASE 0x455C440ull +#define DCORE2_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x455C480ull +#define DCORE2_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR3_LBW_WR_RS_LL_STAT_BASE 0x455C4C0ull +#define DCORE2_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR3_HBW_MFIFO_BASE 0x455C500ull +#define DCORE2_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE2_RTR3_E2E_RD_LL_STAT_BASE 0x455C540ull +#define DCORE2_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR3_E2E_WR_LL_STAT_BASE 0x455C580ull +#define DCORE2_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE2_RTR3_RTR_HBW_XACT_STAT_BASE 0x455C600ull +#define DCORE2_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR3_RTR_LBW_XACT_STAT_BASE 0x455C680ull +#define DCORE2_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR3_RTR_E2E_XACT_STAT_BASE 0x455C700ull +#define DCORE2_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE2_RTR3_SPECIAL_BASE 0x455CE80ull +#define DCORE2_RTR3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR3_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR3_DBG_ADDR_BASE 0x455D000ull +#define DCORE2_RTR3_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE2_RTR3_DBG_ADDR_SECTION 0xE800 +#define mmDCORE2_RTR3_DBG_ADDR_SPECIAL_BASE 0x455DE80ull +#define DCORE2_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE2_RTR4_CTRL_BASE 0x4560000ull +#define DCORE2_RTR4_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_RTR4_CTRL_SECTION 0xE800 +#define mmDCORE2_RTR4_CTRL_SPECIAL_BASE 0x4560E80ull +#define DCORE2_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR4_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR4_H3_BASE 0x4561000ull +#define DCORE2_RTR4_H3_MAX_OFFSET 0x1000 +#define DCORE2_RTR4_H3_SECTION 0xE800 +#define mmDCORE2_RTR4_H3_SPECIAL_BASE 0x4561E80ull +#define DCORE2_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR4_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x4562000ull +#define DCORE2_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x4562200ull +#define DCORE2_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x4562400ull +#define DCORE2_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x4562600ull +#define DCORE2_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_RTR4_MSTR_IF_E2E_CRDT_BASE 0x4562800ull +#define DCORE2_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_RTR4_MSTR_IF_AXUSER_BASE 0x4562A80ull +#define DCORE2_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_RTR4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_RTR4_MSTR_IF_DBG_HBW_BASE 0x4562B00ull +#define DCORE2_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_RTR4_MSTR_IF_DBG_LBW_BASE 0x4562B80ull +#define DCORE2_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_RTR4_MSTR_IF_CORE_HBW_BASE 0x4562C00ull +#define DCORE2_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_RTR4_MSTR_IF_CORE_LBW_BASE 0x4562D80ull +#define DCORE2_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_RTR4_MSTR_IF_SPECIAL_BASE 0x4562E80ull +#define DCORE2_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR4_ADD_DEC_HBW_BASE 0x4563000ull +#define DCORE2_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE2_RTR4_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE2_RTR4_ADD_DEC_LBW_BASE 0x4563400ull +#define DCORE2_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE2_RTR4_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE2_RTR4_ADD_DEC_SPECIAL_BASE 0x4563E80ull +#define DCORE2_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR4_BASE 0x4564000ull +#define DCORE2_RTR4_MAX_OFFSET 0x1000 +#define DCORE2_RTR4_SECTION 0x3000 +#define mmDCORE2_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x4564300ull +#define DCORE2_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR4_HBW_RD_RS_LL_STAT_BASE 0x4564340ull +#define DCORE2_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x4564380ull +#define DCORE2_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR4_HBW_WR_RS_LL_STAT_BASE 0x45643C0ull +#define DCORE2_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x4564400ull +#define DCORE2_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR4_LBW_RD_RS_LL_STAT_BASE 0x4564440ull +#define DCORE2_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x4564480ull +#define DCORE2_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR4_LBW_WR_RS_LL_STAT_BASE 0x45644C0ull +#define DCORE2_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR4_HBW_MFIFO_BASE 0x4564500ull +#define DCORE2_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE2_RTR4_E2E_RD_LL_STAT_BASE 0x4564540ull +#define DCORE2_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR4_E2E_WR_LL_STAT_BASE 0x4564580ull +#define DCORE2_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE2_RTR4_RTR_HBW_XACT_STAT_BASE 0x4564600ull +#define DCORE2_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR4_RTR_LBW_XACT_STAT_BASE 0x4564680ull +#define DCORE2_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR4_RTR_E2E_XACT_STAT_BASE 0x4564700ull +#define DCORE2_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE2_RTR4_SPECIAL_BASE 0x4564E80ull +#define DCORE2_RTR4_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR4_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR4_DBG_ADDR_BASE 0x4565000ull +#define DCORE2_RTR4_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE2_RTR4_DBG_ADDR_SECTION 0xE800 +#define mmDCORE2_RTR4_DBG_ADDR_SPECIAL_BASE 0x4565E80ull +#define DCORE2_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE2_RTR5_CTRL_BASE 0x4568000ull +#define DCORE2_RTR5_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_RTR5_CTRL_SECTION 0xE800 +#define mmDCORE2_RTR5_CTRL_SPECIAL_BASE 0x4568E80ull +#define DCORE2_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR5_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR5_H3_BASE 0x4569000ull +#define DCORE2_RTR5_H3_MAX_OFFSET 0x1000 +#define DCORE2_RTR5_H3_SECTION 0xE800 +#define mmDCORE2_RTR5_H3_SPECIAL_BASE 0x4569E80ull +#define DCORE2_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR5_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x456A000ull +#define DCORE2_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x456A200ull +#define DCORE2_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x456A400ull +#define DCORE2_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x456A600ull +#define DCORE2_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_RTR5_MSTR_IF_E2E_CRDT_BASE 0x456A800ull +#define DCORE2_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_RTR5_MSTR_IF_AXUSER_BASE 0x456AA80ull +#define DCORE2_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_RTR5_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_RTR5_MSTR_IF_DBG_HBW_BASE 0x456AB00ull +#define DCORE2_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_RTR5_MSTR_IF_DBG_LBW_BASE 0x456AB80ull +#define DCORE2_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_RTR5_MSTR_IF_CORE_HBW_BASE 0x456AC00ull +#define DCORE2_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_RTR5_MSTR_IF_CORE_LBW_BASE 0x456AD80ull +#define DCORE2_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_RTR5_MSTR_IF_SPECIAL_BASE 0x456AE80ull +#define DCORE2_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR5_ADD_DEC_HBW_BASE 0x456B000ull +#define DCORE2_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE2_RTR5_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE2_RTR5_ADD_DEC_LBW_BASE 0x456B400ull +#define DCORE2_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE2_RTR5_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE2_RTR5_ADD_DEC_SPECIAL_BASE 0x456BE80ull +#define DCORE2_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR5_BASE 0x456C000ull +#define DCORE2_RTR5_MAX_OFFSET 0x1000 +#define DCORE2_RTR5_SECTION 0x3000 +#define mmDCORE2_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x456C300ull +#define DCORE2_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR5_HBW_RD_RS_LL_STAT_BASE 0x456C340ull +#define DCORE2_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x456C380ull +#define DCORE2_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR5_HBW_WR_RS_LL_STAT_BASE 0x456C3C0ull +#define DCORE2_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x456C400ull +#define DCORE2_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR5_LBW_RD_RS_LL_STAT_BASE 0x456C440ull +#define DCORE2_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x456C480ull +#define DCORE2_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR5_LBW_WR_RS_LL_STAT_BASE 0x456C4C0ull +#define DCORE2_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR5_HBW_MFIFO_BASE 0x456C500ull +#define DCORE2_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE2_RTR5_E2E_RD_LL_STAT_BASE 0x456C540ull +#define DCORE2_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR5_E2E_WR_LL_STAT_BASE 0x456C580ull +#define DCORE2_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE2_RTR5_RTR_HBW_XACT_STAT_BASE 0x456C600ull +#define DCORE2_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR5_RTR_LBW_XACT_STAT_BASE 0x456C680ull +#define DCORE2_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR5_RTR_E2E_XACT_STAT_BASE 0x456C700ull +#define DCORE2_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE2_RTR5_SPECIAL_BASE 0x456CE80ull +#define DCORE2_RTR5_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR5_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR5_DBG_ADDR_BASE 0x456D000ull +#define DCORE2_RTR5_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE2_RTR5_DBG_ADDR_SECTION 0xE800 +#define mmDCORE2_RTR5_DBG_ADDR_SPECIAL_BASE 0x456DE80ull +#define DCORE2_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE2_RTR6_CTRL_BASE 0x4570000ull +#define DCORE2_RTR6_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_RTR6_CTRL_SECTION 0xE800 +#define mmDCORE2_RTR6_CTRL_SPECIAL_BASE 0x4570E80ull +#define DCORE2_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR6_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR6_H3_BASE 0x4571000ull +#define DCORE2_RTR6_H3_MAX_OFFSET 0x1000 +#define DCORE2_RTR6_H3_SECTION 0xE800 +#define mmDCORE2_RTR6_H3_SPECIAL_BASE 0x4571E80ull +#define DCORE2_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR6_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x4572000ull +#define DCORE2_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x4572200ull +#define DCORE2_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x4572400ull +#define DCORE2_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x4572600ull +#define DCORE2_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_RTR6_MSTR_IF_E2E_CRDT_BASE 0x4572800ull +#define DCORE2_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_RTR6_MSTR_IF_AXUSER_BASE 0x4572A80ull +#define DCORE2_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_RTR6_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_RTR6_MSTR_IF_DBG_HBW_BASE 0x4572B00ull +#define DCORE2_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_RTR6_MSTR_IF_DBG_LBW_BASE 0x4572B80ull +#define DCORE2_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_RTR6_MSTR_IF_CORE_HBW_BASE 0x4572C00ull +#define DCORE2_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_RTR6_MSTR_IF_CORE_LBW_BASE 0x4572D80ull +#define DCORE2_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_RTR6_MSTR_IF_SPECIAL_BASE 0x4572E80ull +#define DCORE2_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR6_ADD_DEC_HBW_BASE 0x4573000ull +#define DCORE2_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE2_RTR6_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE2_RTR6_ADD_DEC_LBW_BASE 0x4573400ull +#define DCORE2_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE2_RTR6_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE2_RTR6_ADD_DEC_SPECIAL_BASE 0x4573E80ull +#define DCORE2_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR6_BASE 0x4574000ull +#define DCORE2_RTR6_MAX_OFFSET 0x1000 +#define DCORE2_RTR6_SECTION 0x3000 +#define mmDCORE2_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x4574300ull +#define DCORE2_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR6_HBW_RD_RS_LL_STAT_BASE 0x4574340ull +#define DCORE2_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x4574380ull +#define DCORE2_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR6_HBW_WR_RS_LL_STAT_BASE 0x45743C0ull +#define DCORE2_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x4574400ull +#define DCORE2_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR6_LBW_RD_RS_LL_STAT_BASE 0x4574440ull +#define DCORE2_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x4574480ull +#define DCORE2_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR6_LBW_WR_RS_LL_STAT_BASE 0x45744C0ull +#define DCORE2_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR6_HBW_MFIFO_BASE 0x4574500ull +#define DCORE2_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE2_RTR6_E2E_RD_LL_STAT_BASE 0x4574540ull +#define DCORE2_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR6_E2E_WR_LL_STAT_BASE 0x4574580ull +#define DCORE2_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE2_RTR6_RTR_HBW_XACT_STAT_BASE 0x4574600ull +#define DCORE2_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR6_RTR_LBW_XACT_STAT_BASE 0x4574680ull +#define DCORE2_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR6_RTR_E2E_XACT_STAT_BASE 0x4574700ull +#define DCORE2_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE2_RTR6_SPECIAL_BASE 0x4574E80ull +#define DCORE2_RTR6_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR6_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR6_DBG_ADDR_BASE 0x4575000ull +#define DCORE2_RTR6_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE2_RTR6_DBG_ADDR_SECTION 0xE800 +#define mmDCORE2_RTR6_DBG_ADDR_SPECIAL_BASE 0x4575E80ull +#define DCORE2_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE2_RTR7_CTRL_BASE 0x4578000ull +#define DCORE2_RTR7_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_RTR7_CTRL_SECTION 0xE800 +#define mmDCORE2_RTR7_CTRL_SPECIAL_BASE 0x4578E80ull +#define DCORE2_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR7_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR7_H3_BASE 0x4579000ull +#define DCORE2_RTR7_H3_MAX_OFFSET 0x1000 +#define DCORE2_RTR7_H3_SECTION 0xE800 +#define mmDCORE2_RTR7_H3_SPECIAL_BASE 0x4579E80ull +#define DCORE2_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR7_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x457A000ull +#define DCORE2_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x457A200ull +#define DCORE2_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x457A400ull +#define DCORE2_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x457A600ull +#define DCORE2_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_RTR7_MSTR_IF_E2E_CRDT_BASE 0x457A800ull +#define DCORE2_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_RTR7_MSTR_IF_AXUSER_BASE 0x457AA80ull +#define DCORE2_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_RTR7_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_RTR7_MSTR_IF_DBG_HBW_BASE 0x457AB00ull +#define DCORE2_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_RTR7_MSTR_IF_DBG_LBW_BASE 0x457AB80ull +#define DCORE2_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_RTR7_MSTR_IF_CORE_HBW_BASE 0x457AC00ull +#define DCORE2_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_RTR7_MSTR_IF_CORE_LBW_BASE 0x457AD80ull +#define DCORE2_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_RTR7_MSTR_IF_SPECIAL_BASE 0x457AE80ull +#define DCORE2_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR7_ADD_DEC_HBW_BASE 0x457B000ull +#define DCORE2_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE2_RTR7_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE2_RTR7_ADD_DEC_LBW_BASE 0x457B400ull +#define DCORE2_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE2_RTR7_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE2_RTR7_ADD_DEC_SPECIAL_BASE 0x457BE80ull +#define DCORE2_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR7_BASE 0x457C000ull +#define DCORE2_RTR7_MAX_OFFSET 0x1000 +#define DCORE2_RTR7_SECTION 0x3000 +#define mmDCORE2_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x457C300ull +#define DCORE2_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR7_HBW_RD_RS_LL_STAT_BASE 0x457C340ull +#define DCORE2_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x457C380ull +#define DCORE2_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR7_HBW_WR_RS_LL_STAT_BASE 0x457C3C0ull +#define DCORE2_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x457C400ull +#define DCORE2_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR7_LBW_RD_RS_LL_STAT_BASE 0x457C440ull +#define DCORE2_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x457C480ull +#define DCORE2_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR7_LBW_WR_RS_LL_STAT_BASE 0x457C4C0ull +#define DCORE2_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR7_HBW_MFIFO_BASE 0x457C500ull +#define DCORE2_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE2_RTR7_E2E_RD_LL_STAT_BASE 0x457C540ull +#define DCORE2_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE2_RTR7_E2E_WR_LL_STAT_BASE 0x457C580ull +#define DCORE2_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE2_RTR7_RTR_HBW_XACT_STAT_BASE 0x457C600ull +#define DCORE2_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR7_RTR_LBW_XACT_STAT_BASE 0x457C680ull +#define DCORE2_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE2_RTR7_RTR_E2E_XACT_STAT_BASE 0x457C700ull +#define DCORE2_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE2_RTR7_SPECIAL_BASE 0x457CE80ull +#define DCORE2_RTR7_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR7_SPECIAL_SECTION 0x1800 +#define mmDCORE2_RTR7_DBG_ADDR_BASE 0x457D000ull +#define DCORE2_RTR7_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE2_RTR7_DBG_ADDR_SECTION 0xE800 +#define mmDCORE2_RTR7_DBG_ADDR_SPECIAL_BASE 0x457DE80ull +#define DCORE2_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE2_SRAM0_BANK_BASE 0x4580000ull +#define DCORE2_SRAM0_BANK_MAX_OFFSET 0x1000 +#define DCORE2_SRAM0_BANK_SECTION 0xE800 +#define mmDCORE2_SRAM0_BANK_SPECIAL_BASE 0x4580E80ull +#define DCORE2_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM0_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM0_RTR_BASE 0x4581000ull +#define DCORE2_SRAM0_RTR_MAX_OFFSET 0x1000 +#define DCORE2_SRAM0_RTR_SECTION 0xE800 +#define mmDCORE2_SRAM0_RTR_SPECIAL_BASE 0x4581E80ull +#define DCORE2_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM0_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4582000ull +#define DCORE2_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4582100ull +#define DCORE2_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4582200ull +#define DCORE2_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4582300ull +#define DCORE2_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4582400ull +#define DCORE2_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4582500ull +#define DCORE2_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4582600ull +#define DCORE2_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4582700ull +#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4582780ull +#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4582800ull +#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4582880ull +#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4582900ull +#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4582980ull +#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4582A00ull +#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4582A80ull +#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE2_SRAM0_DBG_CNT_SPECIAL_BASE 0x4582E80ull +#define DCORE2_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE2_SRAM1_BANK_BASE 0x4588000ull +#define DCORE2_SRAM1_BANK_MAX_OFFSET 0x1000 +#define DCORE2_SRAM1_BANK_SECTION 0xE800 +#define mmDCORE2_SRAM1_BANK_SPECIAL_BASE 0x4588E80ull +#define DCORE2_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM1_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM1_RTR_BASE 0x4589000ull +#define DCORE2_SRAM1_RTR_MAX_OFFSET 0x1000 +#define DCORE2_SRAM1_RTR_SECTION 0xE800 +#define mmDCORE2_SRAM1_RTR_SPECIAL_BASE 0x4589E80ull +#define DCORE2_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM1_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x458A000ull +#define DCORE2_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x458A100ull +#define DCORE2_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x458A200ull +#define DCORE2_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x458A300ull +#define DCORE2_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x458A400ull +#define DCORE2_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x458A500ull +#define DCORE2_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x458A600ull +#define DCORE2_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x458A700ull +#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x458A780ull +#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x458A800ull +#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x458A880ull +#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x458A900ull +#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x458A980ull +#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x458AA00ull +#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x458AA80ull +#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE2_SRAM1_DBG_CNT_SPECIAL_BASE 0x458AE80ull +#define DCORE2_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE2_SRAM2_BANK_BASE 0x4590000ull +#define DCORE2_SRAM2_BANK_MAX_OFFSET 0x1000 +#define DCORE2_SRAM2_BANK_SECTION 0xE800 +#define mmDCORE2_SRAM2_BANK_SPECIAL_BASE 0x4590E80ull +#define DCORE2_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM2_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM2_RTR_BASE 0x4591000ull +#define DCORE2_SRAM2_RTR_MAX_OFFSET 0x1000 +#define DCORE2_SRAM2_RTR_SECTION 0xE800 +#define mmDCORE2_SRAM2_RTR_SPECIAL_BASE 0x4591E80ull +#define DCORE2_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM2_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4592000ull +#define DCORE2_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4592100ull +#define DCORE2_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4592200ull +#define DCORE2_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4592300ull +#define DCORE2_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4592400ull +#define DCORE2_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4592500ull +#define DCORE2_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4592600ull +#define DCORE2_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4592700ull +#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4592780ull +#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4592800ull +#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4592880ull +#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4592900ull +#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4592980ull +#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4592A00ull +#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4592A80ull +#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE2_SRAM2_DBG_CNT_SPECIAL_BASE 0x4592E80ull +#define DCORE2_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE2_SRAM3_BANK_BASE 0x4598000ull +#define DCORE2_SRAM3_BANK_MAX_OFFSET 0x1000 +#define DCORE2_SRAM3_BANK_SECTION 0xE800 +#define mmDCORE2_SRAM3_BANK_SPECIAL_BASE 0x4598E80ull +#define DCORE2_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM3_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM3_RTR_BASE 0x4599000ull +#define DCORE2_SRAM3_RTR_MAX_OFFSET 0x1000 +#define DCORE2_SRAM3_RTR_SECTION 0xE800 +#define mmDCORE2_SRAM3_RTR_SPECIAL_BASE 0x4599E80ull +#define DCORE2_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM3_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x459A000ull +#define DCORE2_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x459A100ull +#define DCORE2_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x459A200ull +#define DCORE2_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x459A300ull +#define DCORE2_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x459A400ull +#define DCORE2_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x459A500ull +#define DCORE2_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x459A600ull +#define DCORE2_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x459A700ull +#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x459A780ull +#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x459A800ull +#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x459A880ull +#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x459A900ull +#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x459A980ull +#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x459AA00ull +#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x459AA80ull +#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE2_SRAM3_DBG_CNT_SPECIAL_BASE 0x459AE80ull +#define DCORE2_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE2_SRAM4_BANK_BASE 0x45A0000ull +#define DCORE2_SRAM4_BANK_MAX_OFFSET 0x1000 +#define DCORE2_SRAM4_BANK_SECTION 0xE800 +#define mmDCORE2_SRAM4_BANK_SPECIAL_BASE 0x45A0E80ull +#define DCORE2_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM4_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM4_RTR_BASE 0x45A1000ull +#define DCORE2_SRAM4_RTR_MAX_OFFSET 0x1000 +#define DCORE2_SRAM4_RTR_SECTION 0xE800 +#define mmDCORE2_SRAM4_RTR_SPECIAL_BASE 0x45A1E80ull +#define DCORE2_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM4_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x45A2000ull +#define DCORE2_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x45A2100ull +#define DCORE2_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x45A2200ull +#define DCORE2_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x45A2300ull +#define DCORE2_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x45A2400ull +#define DCORE2_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x45A2500ull +#define DCORE2_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x45A2600ull +#define DCORE2_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x45A2700ull +#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x45A2780ull +#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x45A2800ull +#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x45A2880ull +#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x45A2900ull +#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x45A2980ull +#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x45A2A00ull +#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x45A2A80ull +#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE2_SRAM4_DBG_CNT_SPECIAL_BASE 0x45A2E80ull +#define DCORE2_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE2_SRAM5_BANK_BASE 0x45A8000ull +#define DCORE2_SRAM5_BANK_MAX_OFFSET 0x1000 +#define DCORE2_SRAM5_BANK_SECTION 0xE800 +#define mmDCORE2_SRAM5_BANK_SPECIAL_BASE 0x45A8E80ull +#define DCORE2_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM5_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM5_RTR_BASE 0x45A9000ull +#define DCORE2_SRAM5_RTR_MAX_OFFSET 0x1000 +#define DCORE2_SRAM5_RTR_SECTION 0xE800 +#define mmDCORE2_SRAM5_RTR_SPECIAL_BASE 0x45A9E80ull +#define DCORE2_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM5_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x45AA000ull +#define DCORE2_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x45AA100ull +#define DCORE2_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x45AA200ull +#define DCORE2_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x45AA300ull +#define DCORE2_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x45AA400ull +#define DCORE2_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x45AA500ull +#define DCORE2_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x45AA600ull +#define DCORE2_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x45AA700ull +#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x45AA780ull +#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x45AA800ull +#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x45AA880ull +#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x45AA900ull +#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x45AA980ull +#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x45AAA00ull +#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x45AAA80ull +#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE2_SRAM5_DBG_CNT_SPECIAL_BASE 0x45AAE80ull +#define DCORE2_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE2_SRAM6_BANK_BASE 0x45B0000ull +#define DCORE2_SRAM6_BANK_MAX_OFFSET 0x1000 +#define DCORE2_SRAM6_BANK_SECTION 0xE800 +#define mmDCORE2_SRAM6_BANK_SPECIAL_BASE 0x45B0E80ull +#define DCORE2_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM6_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM6_RTR_BASE 0x45B1000ull +#define DCORE2_SRAM6_RTR_MAX_OFFSET 0x1000 +#define DCORE2_SRAM6_RTR_SECTION 0xE800 +#define mmDCORE2_SRAM6_RTR_SPECIAL_BASE 0x45B1E80ull +#define DCORE2_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM6_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x45B2000ull +#define DCORE2_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x45B2100ull +#define DCORE2_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x45B2200ull +#define DCORE2_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x45B2300ull +#define DCORE2_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x45B2400ull +#define DCORE2_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x45B2500ull +#define DCORE2_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x45B2600ull +#define DCORE2_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x45B2700ull +#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x45B2780ull +#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x45B2800ull +#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x45B2880ull +#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x45B2900ull +#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x45B2980ull +#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x45B2A00ull +#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x45B2A80ull +#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE2_SRAM6_DBG_CNT_SPECIAL_BASE 0x45B2E80ull +#define DCORE2_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE2_SRAM7_BANK_BASE 0x45B8000ull +#define DCORE2_SRAM7_BANK_MAX_OFFSET 0x1000 +#define DCORE2_SRAM7_BANK_SECTION 0xE800 +#define mmDCORE2_SRAM7_BANK_SPECIAL_BASE 0x45B8E80ull +#define DCORE2_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM7_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM7_RTR_BASE 0x45B9000ull +#define DCORE2_SRAM7_RTR_MAX_OFFSET 0x1000 +#define DCORE2_SRAM7_RTR_SECTION 0xE800 +#define mmDCORE2_SRAM7_RTR_SPECIAL_BASE 0x45B9E80ull +#define DCORE2_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM7_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE2_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x45BA000ull +#define DCORE2_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x45BA100ull +#define DCORE2_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x45BA200ull +#define DCORE2_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x45BA300ull +#define DCORE2_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x45BA400ull +#define DCORE2_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x45BA500ull +#define DCORE2_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x45BA600ull +#define DCORE2_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE2_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x45BA700ull +#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x45BA780ull +#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x45BA800ull +#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x45BA880ull +#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x45BA900ull +#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x45BA980ull +#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x45BAA00ull +#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE2_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x45BAA80ull +#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE2_SRAM7_DBG_CNT_SPECIAL_BASE 0x45BAE80ull +#define DCORE2_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE2_EDMA0_QM_DCCM_BASE 0x45C0000ull +#define DCORE2_EDMA0_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_EDMA0_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_ARC_AUX_BASE 0x45C8000ull +#define DCORE2_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE2_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x45C8E80ull +#define DCORE2_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_EDMA0_QM_BASE 0x45CA000ull +#define DCORE2_EDMA0_QM_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_QM_SECTION 0x9000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x45CA900ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x45CA908ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x45CA910ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x45CA918ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x45CA920ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x45CA928ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x45CA930ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x45CA938ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x45CA940ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x45CA948ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x45CA950ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x45CA958ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x45CA960ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x45CA968ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x45CA970ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x45CA978ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_EDMA0_QM_AXUSER_SECURED_BASE 0x45CAB00ull +#define DCORE2_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_AXUSER_NONSECURED_BASE 0x45CAB80ull +#define DCORE2_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_DBG_HBW_BASE 0x45CAC00ull +#define DCORE2_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_EDMA0_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_EDMA0_QM_DBG_LBW_BASE 0x45CAC80ull +#define DCORE2_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_EDMA0_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_EDMA0_QM_CGM_BASE 0x45CAD80ull +#define DCORE2_EDMA0_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_EDMA0_QM_CGM_SECTION 0x1000 +#define mmDCORE2_EDMA0_QM_SPECIAL_BASE 0x45CAE80ull +#define DCORE2_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_EDMA0_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_EDMA0_CORE_BASE 0x45CB000ull +#define DCORE2_EDMA0_CORE_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_CORE_SECTION 0x8000 +#define mmDCORE2_EDMA0_CORE_CTX_AXUSER_BASE 0x45CB800ull +#define DCORE2_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000 +#define mmDCORE2_EDMA0_CORE_CTX_BASE 0x45CB860ull +#define DCORE2_EDMA0_CORE_CTX_MAX_OFFSET 0x9000 +#define DCORE2_EDMA0_CORE_CTX_SECTION 0x5A00 +#define mmDCORE2_EDMA0_CORE_KDMA_CGM_BASE 0x45CBE00ull +#define DCORE2_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define DCORE2_EDMA0_CORE_KDMA_CGM_SECTION 0x8000 +#define mmDCORE2_EDMA0_CORE_SPECIAL_BASE 0x45CBE80ull +#define DCORE2_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_EDMA0_CORE_SPECIAL_SECTION 0x1800 +#define mmDCORE2_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x45CC000ull +#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x45CC200ull +#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x45CC400ull +#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x45CC600ull +#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x45CC800ull +#define DCORE2_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_EDMA0_MSTR_IF_AXUSER_BASE 0x45CCA80ull +#define DCORE2_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_EDMA0_MSTR_IF_DBG_HBW_BASE 0x45CCB00ull +#define DCORE2_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_EDMA0_MSTR_IF_DBG_LBW_BASE 0x45CCB80ull +#define DCORE2_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_EDMA0_MSTR_IF_CORE_HBW_BASE 0x45CCC00ull +#define DCORE2_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_EDMA0_MSTR_IF_CORE_LBW_BASE 0x45CCD80ull +#define DCORE2_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_EDMA0_MSTR_IF_SPECIAL_BASE 0x45CCE80ull +#define DCORE2_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE2_EDMA1_QM_DCCM_BASE 0x45D0000ull +#define DCORE2_EDMA1_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_EDMA1_QM_DCCM_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_ARC_AUX_BASE 0x45D8000ull +#define DCORE2_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE2_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x45D8E80ull +#define DCORE2_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE2_EDMA1_QM_BASE 0x45DA000ull +#define DCORE2_EDMA1_QM_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_QM_SECTION 0x9000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x45DA900ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x45DA908ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x45DA910ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x45DA918ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x45DA920ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x45DA928ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x45DA930ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x45DA938ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x45DA940ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x45DA948ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x45DA950ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x45DA958ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x45DA960ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x45DA968ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x45DA970ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x45DA978ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE2_EDMA1_QM_AXUSER_SECURED_BASE 0x45DAB00ull +#define DCORE2_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_AXUSER_NONSECURED_BASE 0x45DAB80ull +#define DCORE2_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_DBG_HBW_BASE 0x45DAC00ull +#define DCORE2_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_EDMA1_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_EDMA1_QM_DBG_LBW_BASE 0x45DAC80ull +#define DCORE2_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_EDMA1_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE2_EDMA1_QM_CGM_BASE 0x45DAD80ull +#define DCORE2_EDMA1_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_EDMA1_QM_CGM_SECTION 0x1000 +#define mmDCORE2_EDMA1_QM_SPECIAL_BASE 0x45DAE80ull +#define DCORE2_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_EDMA1_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE2_EDMA1_CORE_BASE 0x45DB000ull +#define DCORE2_EDMA1_CORE_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_CORE_SECTION 0x8000 +#define mmDCORE2_EDMA1_CORE_CTX_AXUSER_BASE 0x45DB800ull +#define DCORE2_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000 +#define mmDCORE2_EDMA1_CORE_CTX_BASE 0x45DB860ull +#define DCORE2_EDMA1_CORE_CTX_MAX_OFFSET 0x9000 +#define DCORE2_EDMA1_CORE_CTX_SECTION 0x5A00 +#define mmDCORE2_EDMA1_CORE_KDMA_CGM_BASE 0x45DBE00ull +#define DCORE2_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define DCORE2_EDMA1_CORE_KDMA_CGM_SECTION 0x8000 +#define mmDCORE2_EDMA1_CORE_SPECIAL_BASE 0x45DBE80ull +#define DCORE2_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_EDMA1_CORE_SPECIAL_SECTION 0x1800 +#define mmDCORE2_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x45DC000ull +#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x45DC200ull +#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x45DC400ull +#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x45DC600ull +#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x45DC800ull +#define DCORE2_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_EDMA1_MSTR_IF_AXUSER_BASE 0x45DCA80ull +#define DCORE2_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_EDMA1_MSTR_IF_DBG_HBW_BASE 0x45DCB00ull +#define DCORE2_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_EDMA1_MSTR_IF_DBG_LBW_BASE 0x45DCB80ull +#define DCORE2_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_EDMA1_MSTR_IF_CORE_HBW_BASE 0x45DCC00ull +#define DCORE2_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_EDMA1_MSTR_IF_CORE_LBW_BASE 0x45DCD80ull +#define DCORE2_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_EDMA1_MSTR_IF_SPECIAL_BASE 0x45DCE80ull +#define DCORE2_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE2_DEC0_CMD_BASE 0x45E0000ull +#define DCORE2_DEC0_CMD_MAX_OFFSET 0x1100 +#define DCORE2_DEC0_CMD_SECTION 0x1000 +#define mmDCORE2_DEC0_VSI_BASE 0x45E1000ull +#define DCORE2_DEC0_VSI_MAX_OFFSET 0x6FC0 +#define DCORE2_DEC0_VSI_SECTION 0x1000 +#define mmDCORE2_DEC0_L2C_BASE 0x45E2000ull +#define DCORE2_DEC0_L2C_MAX_OFFSET 0x39C0 +#define DCORE2_DEC0_L2C_SECTION 0x1000 +#define mmDCORE2_VDEC0_BRDG_CTRL_BASE 0x45E3000ull +#define DCORE2_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_BRDG_CTRL_SECTION 0x8000 +#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x45E3800ull +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 +#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x45E3900ull +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 +#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x45E3A00ull +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 +#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x45E3B00ull +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 +#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x45E3C00ull +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 +#define mmDCORE2_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x45E3E80ull +#define DCORE2_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_VDEC0_CTRL_BASE 0x45E4000ull +#define DCORE2_VDEC0_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_CTRL_SECTION 0xE800 +#define mmDCORE2_VDEC0_CTRL_SPECIAL_BASE 0x45E4E80ull +#define DCORE2_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_VDEC0_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x45E5000ull +#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x45E5200ull +#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x45E5400ull +#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x45E5600ull +#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x45E5800ull +#define DCORE2_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_VDEC0_MSTR_IF_AXUSER_BASE 0x45E5A80ull +#define DCORE2_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_VDEC0_MSTR_IF_DBG_HBW_BASE 0x45E5B00ull +#define DCORE2_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_VDEC0_MSTR_IF_DBG_LBW_BASE 0x45E5B80ull +#define DCORE2_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_VDEC0_MSTR_IF_CORE_HBW_BASE 0x45E5C00ull +#define DCORE2_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_VDEC0_MSTR_IF_CORE_LBW_BASE 0x45E5D80ull +#define DCORE2_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_VDEC0_MSTR_IF_SPECIAL_BASE 0x45E5E80ull +#define DCORE2_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180 +#define mmDCORE2_DEC1_CMD_BASE 0x45F0000ull +#define DCORE2_DEC1_CMD_MAX_OFFSET 0x1100 +#define DCORE2_DEC1_CMD_SECTION 0x1000 +#define mmDCORE2_DEC1_VSI_BASE 0x45F1000ull +#define DCORE2_DEC1_VSI_MAX_OFFSET 0x6FC0 +#define DCORE2_DEC1_VSI_SECTION 0x1000 +#define mmDCORE2_DEC1_L2C_BASE 0x45F2000ull +#define DCORE2_DEC1_L2C_MAX_OFFSET 0x39C0 +#define DCORE2_DEC1_L2C_SECTION 0x1000 +#define mmDCORE2_VDEC1_BRDG_CTRL_BASE 0x45F3000ull +#define DCORE2_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_BRDG_CTRL_SECTION 0x8000 +#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x45F3800ull +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 +#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x45F3900ull +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 +#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x45F3A00ull +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 +#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x45F3B00ull +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 +#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x45F3C00ull +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 +#define mmDCORE2_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x45F3E80ull +#define DCORE2_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_VDEC1_CTRL_BASE 0x45F4000ull +#define DCORE2_VDEC1_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_CTRL_SECTION 0xE800 +#define mmDCORE2_VDEC1_CTRL_SPECIAL_BASE 0x45F4E80ull +#define DCORE2_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_VDEC1_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x45F5000ull +#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE2_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x45F5200ull +#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE2_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x45F5400ull +#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE2_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x45F5600ull +#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE2_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x45F5800ull +#define DCORE2_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE2_VDEC1_MSTR_IF_AXUSER_BASE 0x45F5A80ull +#define DCORE2_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE2_VDEC1_MSTR_IF_DBG_HBW_BASE 0x45F5B00ull +#define DCORE2_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE2_VDEC1_MSTR_IF_DBG_LBW_BASE 0x45F5B80ull +#define DCORE2_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE2_VDEC1_MSTR_IF_CORE_HBW_BASE 0x45F5C00ull +#define DCORE2_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE2_VDEC1_MSTR_IF_CORE_LBW_BASE 0x45F5D80ull +#define DCORE2_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE2_VDEC1_MSTR_IF_SPECIAL_BASE 0x45F5E80ull +#define DCORE2_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180 +#define mmDCORE3_TPC0_QM_DCCM_BASE 0x4600000ull +#define DCORE3_TPC0_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC0_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_ARC_AUX_BASE 0x4608000ull +#define DCORE3_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE3_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x4608E80ull +#define DCORE3_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TPC0_QM_BASE 0x460A000ull +#define DCORE3_TPC0_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_QM_SECTION 0x9000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x460A900ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x460A908ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x460A910ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x460A918ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x460A920ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x460A928ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x460A930ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x460A938ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x460A940ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x460A948ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x460A950ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x460A958ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x460A960ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x460A968ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x460A970ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x460A978ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_TPC0_QM_AXUSER_SECURED_BASE 0x460AB00ull +#define DCORE3_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_AXUSER_NONSECURED_BASE 0x460AB80ull +#define DCORE3_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_DBG_HBW_BASE 0x460AC00ull +#define DCORE3_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC0_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC0_QM_DBG_LBW_BASE 0x460AC80ull +#define DCORE3_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC0_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_TPC0_QM_CGM_BASE 0x460AD80ull +#define DCORE3_TPC0_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC0_QM_CGM_SECTION 0x1000 +#define mmDCORE3_TPC0_QM_SPECIAL_BASE 0x460AE80ull +#define DCORE3_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC0_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x460B000ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC0_CFG_BASE 0x460B000ull +#define DCORE3_TPC0_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_CFG_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x460B050ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x460B0A0ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x460B0F0ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x460B140ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x460B190ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x460B1E0ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x460B230ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x460B280ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x460B2D0ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x460B320ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x460B370ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x460B3C0ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x460B410ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x460B460ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x460B4B0ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x460B500ull +#define DCORE3_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC0_CFG_KERNEL_BASE 0x460B508ull +#define DCORE3_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC0_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_0_BASE 0x460B5DCull +#define DCORE3_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_1_BASE 0x460B62Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_2_BASE 0x460B67Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_3_BASE 0x460B6CCull +#define DCORE3_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_4_BASE 0x460B71Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_5_BASE 0x460B76Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_6_BASE 0x460B7BCull +#define DCORE3_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_7_BASE 0x460B80Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_8_BASE 0x460B85Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_9_BASE 0x460B8ACull +#define DCORE3_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_10_BASE 0x460B8FCull +#define DCORE3_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_11_BASE 0x460B94Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_12_BASE 0x460B99Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_13_BASE 0x460B9ECull +#define DCORE3_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_14_BASE 0x460BA3Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_TENSOR_15_BASE 0x460BA8Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x460BADCull +#define DCORE3_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC0_CFG_QM_BASE 0x460BAE4ull +#define DCORE3_TPC0_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC0_CFG_QM_SECTION 0x31C0 +#define mmDCORE3_TPC0_CFG_AXUSER_BASE 0x460BE00ull +#define DCORE3_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC0_CFG_SPECIAL_BASE 0x460BE80ull +#define DCORE3_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC0_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x460C000ull +#define DCORE3_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x460C200ull +#define DCORE3_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x460C400ull +#define DCORE3_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x460C600ull +#define DCORE3_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_TPC0_MSTR_IF_E2E_CRDT_BASE 0x460C800ull +#define DCORE3_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_TPC0_MSTR_IF_AXUSER_BASE 0x460CA80ull +#define DCORE3_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC0_MSTR_IF_DBG_HBW_BASE 0x460CB00ull +#define DCORE3_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC0_MSTR_IF_DBG_LBW_BASE 0x460CB80ull +#define DCORE3_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_TPC0_MSTR_IF_CORE_HBW_BASE 0x460CC00ull +#define DCORE3_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_TPC0_MSTR_IF_CORE_LBW_BASE 0x460CD80ull +#define DCORE3_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_TPC0_MSTR_IF_SPECIAL_BASE 0x460CE80ull +#define DCORE3_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE3_TPC1_QM_DCCM_BASE 0x4610000ull +#define DCORE3_TPC1_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC1_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_ARC_AUX_BASE 0x4618000ull +#define DCORE3_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE3_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x4618E80ull +#define DCORE3_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TPC1_QM_BASE 0x461A000ull +#define DCORE3_TPC1_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_QM_SECTION 0x9000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x461A900ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x461A908ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x461A910ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x461A918ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x461A920ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x461A928ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x461A930ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x461A938ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x461A940ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x461A948ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x461A950ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x461A958ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x461A960ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x461A968ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x461A970ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x461A978ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_TPC1_QM_AXUSER_SECURED_BASE 0x461AB00ull +#define DCORE3_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_AXUSER_NONSECURED_BASE 0x461AB80ull +#define DCORE3_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_DBG_HBW_BASE 0x461AC00ull +#define DCORE3_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC1_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC1_QM_DBG_LBW_BASE 0x461AC80ull +#define DCORE3_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC1_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_TPC1_QM_CGM_BASE 0x461AD80ull +#define DCORE3_TPC1_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC1_QM_CGM_SECTION 0x1000 +#define mmDCORE3_TPC1_QM_SPECIAL_BASE 0x461AE80ull +#define DCORE3_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC1_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x461B000ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC1_CFG_BASE 0x461B000ull +#define DCORE3_TPC1_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_CFG_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x461B050ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x461B0A0ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x461B0F0ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x461B140ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x461B190ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x461B1E0ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x461B230ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x461B280ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x461B2D0ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x461B320ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x461B370ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x461B3C0ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x461B410ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x461B460ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x461B4B0ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x461B500ull +#define DCORE3_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC1_CFG_KERNEL_BASE 0x461B508ull +#define DCORE3_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC1_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_0_BASE 0x461B5DCull +#define DCORE3_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_1_BASE 0x461B62Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_2_BASE 0x461B67Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_3_BASE 0x461B6CCull +#define DCORE3_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_4_BASE 0x461B71Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_5_BASE 0x461B76Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_6_BASE 0x461B7BCull +#define DCORE3_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_7_BASE 0x461B80Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_8_BASE 0x461B85Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_9_BASE 0x461B8ACull +#define DCORE3_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_10_BASE 0x461B8FCull +#define DCORE3_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_11_BASE 0x461B94Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_12_BASE 0x461B99Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_13_BASE 0x461B9ECull +#define DCORE3_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_14_BASE 0x461BA3Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_TENSOR_15_BASE 0x461BA8Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x461BADCull +#define DCORE3_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC1_CFG_QM_BASE 0x461BAE4ull +#define DCORE3_TPC1_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC1_CFG_QM_SECTION 0x31C0 +#define mmDCORE3_TPC1_CFG_AXUSER_BASE 0x461BE00ull +#define DCORE3_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC1_CFG_SPECIAL_BASE 0x461BE80ull +#define DCORE3_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC1_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x461C000ull +#define DCORE3_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x461C200ull +#define DCORE3_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x461C400ull +#define DCORE3_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x461C600ull +#define DCORE3_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_TPC1_MSTR_IF_E2E_CRDT_BASE 0x461C800ull +#define DCORE3_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_TPC1_MSTR_IF_AXUSER_BASE 0x461CA80ull +#define DCORE3_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC1_MSTR_IF_DBG_HBW_BASE 0x461CB00ull +#define DCORE3_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC1_MSTR_IF_DBG_LBW_BASE 0x461CB80ull +#define DCORE3_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_TPC1_MSTR_IF_CORE_HBW_BASE 0x461CC00ull +#define DCORE3_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_TPC1_MSTR_IF_CORE_LBW_BASE 0x461CD80ull +#define DCORE3_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_TPC1_MSTR_IF_SPECIAL_BASE 0x461CE80ull +#define DCORE3_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE3_TPC2_QM_DCCM_BASE 0x4620000ull +#define DCORE3_TPC2_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC2_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_ARC_AUX_BASE 0x4628000ull +#define DCORE3_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE3_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x4628E80ull +#define DCORE3_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TPC2_QM_BASE 0x462A000ull +#define DCORE3_TPC2_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_QM_SECTION 0x9000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x462A900ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x462A908ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x462A910ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x462A918ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x462A920ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x462A928ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x462A930ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x462A938ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x462A940ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x462A948ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x462A950ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x462A958ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x462A960ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x462A968ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x462A970ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x462A978ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_TPC2_QM_AXUSER_SECURED_BASE 0x462AB00ull +#define DCORE3_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_AXUSER_NONSECURED_BASE 0x462AB80ull +#define DCORE3_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_DBG_HBW_BASE 0x462AC00ull +#define DCORE3_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC2_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC2_QM_DBG_LBW_BASE 0x462AC80ull +#define DCORE3_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC2_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_TPC2_QM_CGM_BASE 0x462AD80ull +#define DCORE3_TPC2_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC2_QM_CGM_SECTION 0x1000 +#define mmDCORE3_TPC2_QM_SPECIAL_BASE 0x462AE80ull +#define DCORE3_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC2_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x462B000ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC2_CFG_BASE 0x462B000ull +#define DCORE3_TPC2_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_CFG_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x462B050ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x462B0A0ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x462B0F0ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x462B140ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x462B190ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x462B1E0ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x462B230ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x462B280ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x462B2D0ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x462B320ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x462B370ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x462B3C0ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x462B410ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x462B460ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x462B4B0ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x462B500ull +#define DCORE3_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC2_CFG_KERNEL_BASE 0x462B508ull +#define DCORE3_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC2_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_0_BASE 0x462B5DCull +#define DCORE3_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_1_BASE 0x462B62Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_2_BASE 0x462B67Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_3_BASE 0x462B6CCull +#define DCORE3_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_4_BASE 0x462B71Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_5_BASE 0x462B76Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_6_BASE 0x462B7BCull +#define DCORE3_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_7_BASE 0x462B80Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_8_BASE 0x462B85Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_9_BASE 0x462B8ACull +#define DCORE3_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_10_BASE 0x462B8FCull +#define DCORE3_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_11_BASE 0x462B94Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_12_BASE 0x462B99Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_13_BASE 0x462B9ECull +#define DCORE3_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_14_BASE 0x462BA3Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_TENSOR_15_BASE 0x462BA8Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x462BADCull +#define DCORE3_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC2_CFG_QM_BASE 0x462BAE4ull +#define DCORE3_TPC2_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC2_CFG_QM_SECTION 0x31C0 +#define mmDCORE3_TPC2_CFG_AXUSER_BASE 0x462BE00ull +#define DCORE3_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC2_CFG_SPECIAL_BASE 0x462BE80ull +#define DCORE3_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC2_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x462C000ull +#define DCORE3_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x462C200ull +#define DCORE3_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x462C400ull +#define DCORE3_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x462C600ull +#define DCORE3_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_TPC2_MSTR_IF_E2E_CRDT_BASE 0x462C800ull +#define DCORE3_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_TPC2_MSTR_IF_AXUSER_BASE 0x462CA80ull +#define DCORE3_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC2_MSTR_IF_DBG_HBW_BASE 0x462CB00ull +#define DCORE3_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC2_MSTR_IF_DBG_LBW_BASE 0x462CB80ull +#define DCORE3_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_TPC2_MSTR_IF_CORE_HBW_BASE 0x462CC00ull +#define DCORE3_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_TPC2_MSTR_IF_CORE_LBW_BASE 0x462CD80ull +#define DCORE3_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_TPC2_MSTR_IF_SPECIAL_BASE 0x462CE80ull +#define DCORE3_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE3_TPC3_QM_DCCM_BASE 0x4630000ull +#define DCORE3_TPC3_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC3_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_ARC_AUX_BASE 0x4638000ull +#define DCORE3_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE3_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x4638E80ull +#define DCORE3_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TPC3_QM_BASE 0x463A000ull +#define DCORE3_TPC3_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_QM_SECTION 0x9000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x463A900ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x463A908ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x463A910ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x463A918ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x463A920ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x463A928ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x463A930ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x463A938ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x463A940ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x463A948ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x463A950ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x463A958ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x463A960ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x463A968ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x463A970ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x463A978ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_TPC3_QM_AXUSER_SECURED_BASE 0x463AB00ull +#define DCORE3_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_AXUSER_NONSECURED_BASE 0x463AB80ull +#define DCORE3_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_DBG_HBW_BASE 0x463AC00ull +#define DCORE3_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC3_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC3_QM_DBG_LBW_BASE 0x463AC80ull +#define DCORE3_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC3_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_TPC3_QM_CGM_BASE 0x463AD80ull +#define DCORE3_TPC3_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC3_QM_CGM_SECTION 0x1000 +#define mmDCORE3_TPC3_QM_SPECIAL_BASE 0x463AE80ull +#define DCORE3_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC3_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x463B000ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC3_CFG_BASE 0x463B000ull +#define DCORE3_TPC3_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_CFG_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x463B050ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x463B0A0ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x463B0F0ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x463B140ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x463B190ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x463B1E0ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x463B230ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x463B280ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x463B2D0ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x463B320ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x463B370ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x463B3C0ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x463B410ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x463B460ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x463B4B0ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x463B500ull +#define DCORE3_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC3_CFG_KERNEL_BASE 0x463B508ull +#define DCORE3_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC3_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_0_BASE 0x463B5DCull +#define DCORE3_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_1_BASE 0x463B62Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_2_BASE 0x463B67Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_3_BASE 0x463B6CCull +#define DCORE3_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_4_BASE 0x463B71Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_5_BASE 0x463B76Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_6_BASE 0x463B7BCull +#define DCORE3_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_7_BASE 0x463B80Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_8_BASE 0x463B85Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_9_BASE 0x463B8ACull +#define DCORE3_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_10_BASE 0x463B8FCull +#define DCORE3_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_11_BASE 0x463B94Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_12_BASE 0x463B99Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_13_BASE 0x463B9ECull +#define DCORE3_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_14_BASE 0x463BA3Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_TENSOR_15_BASE 0x463BA8Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x463BADCull +#define DCORE3_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC3_CFG_QM_BASE 0x463BAE4ull +#define DCORE3_TPC3_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC3_CFG_QM_SECTION 0x31C0 +#define mmDCORE3_TPC3_CFG_AXUSER_BASE 0x463BE00ull +#define DCORE3_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC3_CFG_SPECIAL_BASE 0x463BE80ull +#define DCORE3_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC3_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x463C000ull +#define DCORE3_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x463C200ull +#define DCORE3_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x463C400ull +#define DCORE3_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x463C600ull +#define DCORE3_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_TPC3_MSTR_IF_E2E_CRDT_BASE 0x463C800ull +#define DCORE3_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_TPC3_MSTR_IF_AXUSER_BASE 0x463CA80ull +#define DCORE3_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC3_MSTR_IF_DBG_HBW_BASE 0x463CB00ull +#define DCORE3_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC3_MSTR_IF_DBG_LBW_BASE 0x463CB80ull +#define DCORE3_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_TPC3_MSTR_IF_CORE_HBW_BASE 0x463CC00ull +#define DCORE3_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_TPC3_MSTR_IF_CORE_LBW_BASE 0x463CD80ull +#define DCORE3_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_TPC3_MSTR_IF_SPECIAL_BASE 0x463CE80ull +#define DCORE3_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE3_TPC4_QM_DCCM_BASE 0x4640000ull +#define DCORE3_TPC4_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC4_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_ARC_AUX_BASE 0x4648000ull +#define DCORE3_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE3_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x4648E80ull +#define DCORE3_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TPC4_QM_BASE 0x464A000ull +#define DCORE3_TPC4_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_QM_SECTION 0x9000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x464A900ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x464A908ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x464A910ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x464A918ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x464A920ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x464A928ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x464A930ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x464A938ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x464A940ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x464A948ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x464A950ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x464A958ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x464A960ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x464A968ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x464A970ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x464A978ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_TPC4_QM_AXUSER_SECURED_BASE 0x464AB00ull +#define DCORE3_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_AXUSER_NONSECURED_BASE 0x464AB80ull +#define DCORE3_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_DBG_HBW_BASE 0x464AC00ull +#define DCORE3_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC4_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC4_QM_DBG_LBW_BASE 0x464AC80ull +#define DCORE3_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC4_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_TPC4_QM_CGM_BASE 0x464AD80ull +#define DCORE3_TPC4_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC4_QM_CGM_SECTION 0x1000 +#define mmDCORE3_TPC4_QM_SPECIAL_BASE 0x464AE80ull +#define DCORE3_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC4_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x464B000ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC4_CFG_BASE 0x464B000ull +#define DCORE3_TPC4_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_CFG_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x464B050ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x464B0A0ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x464B0F0ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x464B140ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x464B190ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x464B1E0ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x464B230ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x464B280ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x464B2D0ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x464B320ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x464B370ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x464B3C0ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x464B410ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x464B460ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x464B4B0ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x464B500ull +#define DCORE3_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC4_CFG_KERNEL_BASE 0x464B508ull +#define DCORE3_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC4_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_0_BASE 0x464B5DCull +#define DCORE3_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_1_BASE 0x464B62Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_2_BASE 0x464B67Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_3_BASE 0x464B6CCull +#define DCORE3_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_4_BASE 0x464B71Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_5_BASE 0x464B76Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_6_BASE 0x464B7BCull +#define DCORE3_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_7_BASE 0x464B80Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_8_BASE 0x464B85Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_9_BASE 0x464B8ACull +#define DCORE3_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_10_BASE 0x464B8FCull +#define DCORE3_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_11_BASE 0x464B94Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_12_BASE 0x464B99Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_13_BASE 0x464B9ECull +#define DCORE3_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_14_BASE 0x464BA3Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_TENSOR_15_BASE 0x464BA8Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x464BADCull +#define DCORE3_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC4_CFG_QM_BASE 0x464BAE4ull +#define DCORE3_TPC4_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC4_CFG_QM_SECTION 0x31C0 +#define mmDCORE3_TPC4_CFG_AXUSER_BASE 0x464BE00ull +#define DCORE3_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC4_CFG_SPECIAL_BASE 0x464BE80ull +#define DCORE3_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC4_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x464C000ull +#define DCORE3_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x464C200ull +#define DCORE3_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x464C400ull +#define DCORE3_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x464C600ull +#define DCORE3_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_TPC4_MSTR_IF_E2E_CRDT_BASE 0x464C800ull +#define DCORE3_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_TPC4_MSTR_IF_AXUSER_BASE 0x464CA80ull +#define DCORE3_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC4_MSTR_IF_DBG_HBW_BASE 0x464CB00ull +#define DCORE3_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC4_MSTR_IF_DBG_LBW_BASE 0x464CB80ull +#define DCORE3_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_TPC4_MSTR_IF_CORE_HBW_BASE 0x464CC00ull +#define DCORE3_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_TPC4_MSTR_IF_CORE_LBW_BASE 0x464CD80ull +#define DCORE3_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_TPC4_MSTR_IF_SPECIAL_BASE 0x464CE80ull +#define DCORE3_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE3_TPC5_QM_DCCM_BASE 0x4650000ull +#define DCORE3_TPC5_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC5_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_ARC_AUX_BASE 0x4658000ull +#define DCORE3_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE3_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x4658E80ull +#define DCORE3_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TPC5_QM_BASE 0x465A000ull +#define DCORE3_TPC5_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_QM_SECTION 0x9000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x465A900ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x465A908ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x465A910ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x465A918ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x465A920ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x465A928ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x465A930ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x465A938ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x465A940ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x465A948ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x465A950ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x465A958ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x465A960ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x465A968ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x465A970ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x465A978ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_TPC5_QM_AXUSER_SECURED_BASE 0x465AB00ull +#define DCORE3_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_AXUSER_NONSECURED_BASE 0x465AB80ull +#define DCORE3_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_DBG_HBW_BASE 0x465AC00ull +#define DCORE3_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC5_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC5_QM_DBG_LBW_BASE 0x465AC80ull +#define DCORE3_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC5_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_TPC5_QM_CGM_BASE 0x465AD80ull +#define DCORE3_TPC5_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC5_QM_CGM_SECTION 0x1000 +#define mmDCORE3_TPC5_QM_SPECIAL_BASE 0x465AE80ull +#define DCORE3_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC5_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x465B000ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC5_CFG_BASE 0x465B000ull +#define DCORE3_TPC5_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_CFG_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x465B050ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x465B0A0ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x465B0F0ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x465B140ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x465B190ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x465B1E0ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x465B230ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x465B280ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x465B2D0ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x465B320ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x465B370ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x465B3C0ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x465B410ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x465B460ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x465B4B0ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x465B500ull +#define DCORE3_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC5_CFG_KERNEL_BASE 0x465B508ull +#define DCORE3_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC5_CFG_KERNEL_SECTION 0xD400 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_0_BASE 0x465B5DCull +#define DCORE3_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_1_BASE 0x465B62Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_2_BASE 0x465B67Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_3_BASE 0x465B6CCull +#define DCORE3_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_4_BASE 0x465B71Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_5_BASE 0x465B76Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_6_BASE 0x465B7BCull +#define DCORE3_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_7_BASE 0x465B80Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_8_BASE 0x465B85Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_9_BASE 0x465B8ACull +#define DCORE3_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_10_BASE 0x465B8FCull +#define DCORE3_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_11_BASE 0x465B94Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_12_BASE 0x465B99Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_13_BASE 0x465B9ECull +#define DCORE3_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_14_BASE 0x465BA3Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_TENSOR_15_BASE 0x465BA8Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000 +#define mmDCORE3_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x465BADCull +#define DCORE3_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000 +#define mmDCORE3_TPC5_CFG_QM_BASE 0x465BAE4ull +#define DCORE3_TPC5_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC5_CFG_QM_SECTION 0x31C0 +#define mmDCORE3_TPC5_CFG_AXUSER_BASE 0x465BE00ull +#define DCORE3_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC5_CFG_SPECIAL_BASE 0x465BE80ull +#define DCORE3_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC5_CFG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x465C000ull +#define DCORE3_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x465C200ull +#define DCORE3_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x465C400ull +#define DCORE3_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x465C600ull +#define DCORE3_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_TPC5_MSTR_IF_E2E_CRDT_BASE 0x465C800ull +#define DCORE3_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_TPC5_MSTR_IF_AXUSER_BASE 0x465CA80ull +#define DCORE3_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_TPC5_MSTR_IF_DBG_HBW_BASE 0x465CB00ull +#define DCORE3_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_TPC5_MSTR_IF_DBG_LBW_BASE 0x465CB80ull +#define DCORE3_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_TPC5_MSTR_IF_CORE_HBW_BASE 0x465CC00ull +#define DCORE3_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_TPC5_MSTR_IF_CORE_LBW_BASE 0x465CD80ull +#define DCORE3_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_TPC5_MSTR_IF_SPECIAL_BASE 0x465CE80ull +#define DCORE3_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC5_MSTR_IF_SPECIAL_SECTION 0x23180 +#define mmDCORE3_HMMU0_MMU_BASE 0x4680000ull +#define DCORE3_HMMU0_MMU_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_MMU_SECTION 0xE800 +#define mmDCORE3_HMMU0_MMU_SPECIAL_BASE 0x4680E80ull +#define DCORE3_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU0_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE3_HMMU0_STLB_BASE 0x4681000ull +#define DCORE3_HMMU0_STLB_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_STLB_SECTION 0xE800 +#define mmDCORE3_HMMU0_STLB_SPECIAL_BASE 0x4681E80ull +#define DCORE3_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU0_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE3_HMMU0_SCRAMB_OUT_BASE 0x4683000ull +#define DCORE3_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE3_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x4683E80ull +#define DCORE3_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE3_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x4684000ull +#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x4684200ull +#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x4684400ull +#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x4684600ull +#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x4684800ull +#define DCORE3_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_HMMU0_MSTR_IF_AXUSER_BASE 0x4684A80ull +#define DCORE3_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_HMMU0_MSTR_IF_DBG_HBW_BASE 0x4684B00ull +#define DCORE3_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_HMMU0_MSTR_IF_DBG_LBW_BASE 0x4684B80ull +#define DCORE3_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_HMMU0_MSTR_IF_CORE_HBW_BASE 0x4684C00ull +#define DCORE3_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_HMMU0_MSTR_IF_CORE_LBW_BASE 0x4684D80ull +#define DCORE3_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_HMMU0_MSTR_IF_SPECIAL_BASE 0x4684E80ull +#define DCORE3_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE3_HMMU1_MMU_BASE 0x4690000ull +#define DCORE3_HMMU1_MMU_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_MMU_SECTION 0xE800 +#define mmDCORE3_HMMU1_MMU_SPECIAL_BASE 0x4690E80ull +#define DCORE3_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU1_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE3_HMMU1_STLB_BASE 0x4691000ull +#define DCORE3_HMMU1_STLB_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_STLB_SECTION 0xE800 +#define mmDCORE3_HMMU1_STLB_SPECIAL_BASE 0x4691E80ull +#define DCORE3_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU1_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE3_HMMU1_SCRAMB_OUT_BASE 0x4693000ull +#define DCORE3_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE3_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x4693E80ull +#define DCORE3_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE3_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x4694000ull +#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x4694200ull +#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x4694400ull +#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x4694600ull +#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x4694800ull +#define DCORE3_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_HMMU1_MSTR_IF_AXUSER_BASE 0x4694A80ull +#define DCORE3_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_HMMU1_MSTR_IF_DBG_HBW_BASE 0x4694B00ull +#define DCORE3_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_HMMU1_MSTR_IF_DBG_LBW_BASE 0x4694B80ull +#define DCORE3_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_HMMU1_MSTR_IF_CORE_HBW_BASE 0x4694C00ull +#define DCORE3_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_HMMU1_MSTR_IF_CORE_LBW_BASE 0x4694D80ull +#define DCORE3_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_HMMU1_MSTR_IF_SPECIAL_BASE 0x4694E80ull +#define DCORE3_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE3_HMMU2_MMU_BASE 0x46A0000ull +#define DCORE3_HMMU2_MMU_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_MMU_SECTION 0xE800 +#define mmDCORE3_HMMU2_MMU_SPECIAL_BASE 0x46A0E80ull +#define DCORE3_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU2_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE3_HMMU2_STLB_BASE 0x46A1000ull +#define DCORE3_HMMU2_STLB_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_STLB_SECTION 0xE800 +#define mmDCORE3_HMMU2_STLB_SPECIAL_BASE 0x46A1E80ull +#define DCORE3_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU2_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE3_HMMU2_SCRAMB_OUT_BASE 0x46A3000ull +#define DCORE3_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE3_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x46A3E80ull +#define DCORE3_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE3_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x46A4000ull +#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x46A4200ull +#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x46A4400ull +#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x46A4600ull +#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x46A4800ull +#define DCORE3_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_HMMU2_MSTR_IF_AXUSER_BASE 0x46A4A80ull +#define DCORE3_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_HMMU2_MSTR_IF_DBG_HBW_BASE 0x46A4B00ull +#define DCORE3_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_HMMU2_MSTR_IF_DBG_LBW_BASE 0x46A4B80ull +#define DCORE3_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_HMMU2_MSTR_IF_CORE_HBW_BASE 0x46A4C00ull +#define DCORE3_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_HMMU2_MSTR_IF_CORE_LBW_BASE 0x46A4D80ull +#define DCORE3_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_HMMU2_MSTR_IF_SPECIAL_BASE 0x46A4E80ull +#define DCORE3_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE3_HMMU3_MMU_BASE 0x46B0000ull +#define DCORE3_HMMU3_MMU_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_MMU_SECTION 0xE800 +#define mmDCORE3_HMMU3_MMU_SPECIAL_BASE 0x46B0E80ull +#define DCORE3_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU3_MMU_SPECIAL_SECTION 0x1800 +#define mmDCORE3_HMMU3_STLB_BASE 0x46B1000ull +#define DCORE3_HMMU3_STLB_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_STLB_SECTION 0xE800 +#define mmDCORE3_HMMU3_STLB_SPECIAL_BASE 0x46B1E80ull +#define DCORE3_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU3_STLB_SPECIAL_SECTION 0x1180 +#define mmDCORE3_HMMU3_SCRAMB_OUT_BASE 0x46B3000ull +#define DCORE3_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_SCRAMB_OUT_SECTION 0xE800 +#define mmDCORE3_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x46B3E80ull +#define DCORE3_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800 +#define mmDCORE3_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x46B4000ull +#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x46B4200ull +#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x46B4400ull +#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x46B4600ull +#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x46B4800ull +#define DCORE3_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_HMMU3_MSTR_IF_AXUSER_BASE 0x46B4A80ull +#define DCORE3_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_HMMU3_MSTR_IF_DBG_HBW_BASE 0x46B4B00ull +#define DCORE3_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_HMMU3_MSTR_IF_DBG_LBW_BASE 0x46B4B80ull +#define DCORE3_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_HMMU3_MSTR_IF_CORE_HBW_BASE 0x46B4C00ull +#define DCORE3_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_HMMU3_MSTR_IF_CORE_LBW_BASE 0x46B4D80ull +#define DCORE3_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_HMMU3_MSTR_IF_SPECIAL_BASE 0x46B4E80ull +#define DCORE3_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180 +#define mmDCORE3_MME_QM_ARC_DCCM_BASE 0x46C0000ull +#define DCORE3_MME_QM_ARC_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_MME_QM_ARC_DCCM_SECTION 0x8000 +#define mmDCORE3_MME_QM_ARC_AUX_BASE 0x46C8000ull +#define DCORE3_MME_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_MME_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE3_MME_QM_ARC_AUX_SPECIAL_BASE 0x46C8E80ull +#define DCORE3_MME_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_QM_ARC_AUX_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_QM_ARC_DUP_ENG_BASE 0x46C9000ull +#define DCORE3_MME_QM_ARC_DUP_ENG_MAX_OFFSET 0x1000 +#define DCORE3_MME_QM_ARC_DUP_ENG_SECTION 0x9000 +#define mmDCORE3_MME_QM_ARC_DUP_ENG_AXUSER_BASE 0x46C9900ull +#define DCORE3_MME_QM_ARC_DUP_ENG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_MME_QM_ARC_DUP_ENG_AXUSER_SECTION 0x5800 +#define mmDCORE3_MME_QM_ARC_DUP_ENG_SPECIAL_BASE 0x46C9E80ull +#define DCORE3_MME_QM_ARC_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_QM_ARC_DUP_ENG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_QM_BASE 0x46CA000ull +#define DCORE3_MME_QM_MAX_OFFSET 0x1000 +#define DCORE3_MME_QM_SECTION 0x9000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR0_BASE 0x46CA900ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR1_BASE 0x46CA908ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR2_BASE 0x46CA910ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR3_BASE 0x46CA918ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR4_BASE 0x46CA920ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR5_BASE 0x46CA928ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR6_BASE 0x46CA930ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR7_BASE 0x46CA938ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR8_BASE 0x46CA940ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR9_BASE 0x46CA948ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR10_BASE 0x46CA950ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR11_BASE 0x46CA958ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR12_BASE 0x46CA960ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR13_BASE 0x46CA968ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR14_BASE 0x46CA970ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR15_BASE 0x46CA978ull +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_MME_QM_AXUSER_SECURED_BASE 0x46CAB00ull +#define DCORE3_MME_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_MME_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_MME_QM_AXUSER_NONSECURED_BASE 0x46CAB80ull +#define DCORE3_MME_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_MME_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_MME_QM_DBG_HBW_BASE 0x46CAC00ull +#define DCORE3_MME_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_MME_QM_DBG_LBW_BASE 0x46CAC80ull +#define DCORE3_MME_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_MME_QM_CGM_BASE 0x46CAD80ull +#define DCORE3_MME_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_MME_QM_CGM_SECTION 0x1000 +#define mmDCORE3_MME_QM_SPECIAL_BASE 0x46CAE80ull +#define DCORE3_MME_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_LO_BASE 0x46CB000ull +#define DCORE3_MME_CTRL_LO_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_LO_SECTION 0x8000 +#define mmDCORE3_MME_CTRL_LO_ARCH_BASE_ADDR_BASE 0x46CB008ull +#define DCORE3_MME_CTRL_LO_ARCH_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE3_MME_CTRL_LO_ARCH_BASE_ADDR_SECTION 0x2000 +#define mmDCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE 0x46CB028ull +#define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_LO_ARCH_TENSOR_A_BASE 0x46CB040ull +#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_A_SECTION 0x5800 +#define mmDCORE3_MME_CTRL_LO_ARCH_TENSOR_B_BASE 0x46CB098ull +#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_B_SECTION 0x5800 +#define mmDCORE3_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE 0x46CB0F0ull +#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE 0x46CB15Cull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE 0x46CB170ull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE 0x46CB184ull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE 0x46CB198ull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE 0x46CB1ACull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE 0x46CB1C0ull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE 0x46CB1D4ull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE 0x46CB1E8ull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE 0x46CB1FCull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE 0x46CB210ull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE 0x46CB22Cull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE 0x46CB240ull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE 0x46CB254ull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE 0x46CB268ull +#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE 0x46CB280ull +#define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_END_SECTION 0xB800 +#define mmDCORE3_MME_CTRL_LO_MME_AXUSER_BASE 0x46CBE00ull +#define DCORE3_MME_CTRL_LO_MME_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_MME_CTRL_LO_MME_AXUSER_SECTION 0x8000 +#define mmDCORE3_MME_CTRL_LO_SPECIAL_BASE 0x46CBE80ull +#define DCORE3_MME_CTRL_LO_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_CTRL_LO_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_HI_BASE 0x46CC000ull +#define DCORE3_MME_CTRL_HI_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_HI_SECTION 0x8000 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_BASE_ADDR_BASE 0x46CC008ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE3_MME_CTRL_HI_SHADOW_0_BASE_ADDR_SECTION 0x2000 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_BASE 0x46CC028ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_A_BASE 0x46CC040ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_A_SECTION 0x5800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_B_BASE 0x46CC098ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_B_SECTION 0x5800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_BASE 0x46CC0F0ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_BASE 0x46CC15Cull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_BASE 0x46CC170ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_BASE 0x46CC184ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_BASE 0x46CC198ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_BASE 0x46CC1ACull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_BASE 0x46CC1C0ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_BASE 0x46CC1D4ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_BASE 0x46CC1E8ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_BASE 0x46CC1FCull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_BASE 0x46CC210ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_BASE 0x46CC22Cull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_BASE 0x46CC240ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_BASE 0x46CC254ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_BASE 0x46CC268ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_BASE 0x46CC280ull +#define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_SECTION 0x8800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_BASE_ADDR_BASE 0x46CC308ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE3_MME_CTRL_HI_SHADOW_1_BASE_ADDR_SECTION 0x2000 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_BASE 0x46CC328ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_A_BASE 0x46CC340ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_A_SECTION 0x5800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_B_BASE 0x46CC398ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_B_SECTION 0x5800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_BASE 0x46CC3F0ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_BASE 0x46CC45Cull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_BASE 0x46CC470ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_BASE 0x46CC484ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_BASE 0x46CC498ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_BASE 0x46CC4ACull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_BASE 0x46CC4C0ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_BASE 0x46CC4D4ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_BASE 0x46CC4E8ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_BASE 0x46CC4FCull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_BASE 0x46CC510ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_BASE 0x46CC52Cull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_BASE 0x46CC540ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_BASE 0x46CC554ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_BASE 0x46CC568ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_BASE 0x46CC580ull +#define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_SECTION 0x8800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_BASE_ADDR_BASE 0x46CC608ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE3_MME_CTRL_HI_SHADOW_2_BASE_ADDR_SECTION 0x2000 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_BASE 0x46CC628ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_A_BASE 0x46CC640ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_A_SECTION 0x5800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_B_BASE 0x46CC698ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_B_SECTION 0x5800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_BASE 0x46CC6F0ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_BASE 0x46CC75Cull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_BASE 0x46CC770ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_BASE 0x46CC784ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_BASE 0x46CC798ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_BASE 0x46CC7ACull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_BASE 0x46CC7C0ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_BASE 0x46CC7D4ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_BASE 0x46CC7E8ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_BASE 0x46CC7FCull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_BASE 0x46CC810ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_BASE 0x46CC82Cull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_BASE 0x46CC840ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_BASE 0x46CC854ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_BASE 0x46CC868ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_BASE 0x46CC880ull +#define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_SECTION 0x8800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_BASE_ADDR_BASE 0x46CC908ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_BASE_ADDR_MAX_OFFSET 0x2000 +#define DCORE3_MME_CTRL_HI_SHADOW_3_BASE_ADDR_SECTION 0x2000 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_BASE 0x46CC928ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_MAX_OFFSET 0x1800 +#define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_A_BASE 0x46CC940ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_A_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_A_SECTION 0x5800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_B_BASE 0x46CC998ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_B_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_B_SECTION 0x5800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_BASE 0x46CC9F0ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_SECTION 0x6C00 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_BASE 0x46CCA5Cull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_BASE 0x46CCA70ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_BASE 0x46CCA84ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_BASE 0x46CCA98ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_BASE 0x46CCAACull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_BASE 0x46CCAC0ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_BASE 0x46CCAD4ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_BASE 0x46CCAE8ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_BASE 0x46CCAFCull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_BASE 0x46CCB10ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_SECTION 0x1C00 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_BASE 0x46CCB2Cull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_BASE 0x46CCB40ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_BASE 0x46CCB54ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_SECTION 0x1400 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_BASE 0x46CCB68ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_BASE 0x46CCB80ull +#define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_MAX_OFFSET 0x6000 +#define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_SECTION 0x3000 +#define mmDCORE3_MME_CTRL_HI_SPECIAL_BASE 0x46CCE80ull +#define DCORE3_MME_CTRL_HI_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_CTRL_HI_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_EU_BIST_BASE 0x46CD000ull +#define DCORE3_MME_EU_BIST_MAX_OFFSET 0x1000 +#define DCORE3_MME_EU_BIST_SECTION 0xE800 +#define mmDCORE3_MME_EU_BIST_SPECIAL_BASE 0x46CDE80ull +#define DCORE3_MME_EU_BIST_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_EU_BIST_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE 0x46CE000ull +#define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_MME_CTRL_MSTR_IF_RR_PRVT_HBW_BASE 0x46CE200ull +#define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_MME_CTRL_MSTR_IF_RR_SHRD_LBW_BASE 0x46CE400ull +#define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_MME_CTRL_MSTR_IF_RR_PRVT_LBW_BASE 0x46CE600ull +#define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_MME_CTRL_MSTR_IF_E2E_CRDT_BASE 0x46CE800ull +#define DCORE3_MME_CTRL_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_MME_CTRL_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_MME_CTRL_MSTR_IF_AXUSER_BASE 0x46CEA80ull +#define DCORE3_MME_CTRL_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_MME_CTRL_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_MME_CTRL_MSTR_IF_DBG_HBW_BASE 0x46CEB00ull +#define DCORE3_MME_CTRL_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_MME_CTRL_MSTR_IF_DBG_LBW_BASE 0x46CEB80ull +#define DCORE3_MME_CTRL_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_CTRL_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_MME_CTRL_MSTR_IF_CORE_HBW_BASE 0x46CEC00ull +#define DCORE3_MME_CTRL_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_MME_CTRL_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_MME_CTRL_MSTR_IF_CORE_LBW_BASE 0x46CED80ull +#define DCORE3_MME_CTRL_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_MME_CTRL_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_MME_CTRL_MSTR_IF_SPECIAL_BASE 0x46CEE80ull +#define DCORE3_MME_CTRL_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_CTRL_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_QM_ARC_ACP_ENG_BASE 0x46CF000ull +#define DCORE3_MME_QM_ARC_ACP_ENG_MAX_OFFSET 0x1000 +#define DCORE3_MME_QM_ARC_ACP_ENG_SECTION 0xE800 +#define mmDCORE3_MME_QM_ARC_ACP_ENG_SPECIAL_BASE 0x46CFE80ull +#define DCORE3_MME_QM_ARC_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_QM_ARC_ACP_ENG_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_SBTE0_BASE 0x46D0000ull +#define DCORE3_MME_SBTE0_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE0_SECTION 0xE800 +#define mmDCORE3_MME_SBTE0_SPECIAL_BASE 0x46D0E80ull +#define DCORE3_MME_SBTE0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_SBTE0_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE 0x46D1000ull +#define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_BASE 0x46D1200ull +#define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_BASE 0x46D1400ull +#define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_BASE 0x46D1600ull +#define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE0_MSTR_IF_E2E_CRDT_BASE 0x46D1800ull +#define DCORE3_MME_SBTE0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_MME_SBTE0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_MME_SBTE0_MSTR_IF_AXUSER_BASE 0x46D1A80ull +#define DCORE3_MME_SBTE0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_MME_SBTE0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_MME_SBTE0_MSTR_IF_DBG_HBW_BASE 0x46D1B00ull +#define DCORE3_MME_SBTE0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_SBTE0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_MME_SBTE0_MSTR_IF_DBG_LBW_BASE 0x46D1B80ull +#define DCORE3_MME_SBTE0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_SBTE0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_MME_SBTE0_MSTR_IF_CORE_HBW_BASE 0x46D1C00ull +#define DCORE3_MME_SBTE0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_MME_SBTE0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_MME_SBTE0_MSTR_IF_CORE_LBW_BASE 0x46D1D80ull +#define DCORE3_MME_SBTE0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_MME_SBTE0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_MME_SBTE0_MSTR_IF_SPECIAL_BASE 0x46D1E80ull +#define DCORE3_MME_SBTE0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_SBTE0_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE3_MME_SBTE1_BASE 0x46D8000ull +#define DCORE3_MME_SBTE1_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE1_SECTION 0xE800 +#define mmDCORE3_MME_SBTE1_SPECIAL_BASE 0x46D8E80ull +#define DCORE3_MME_SBTE1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_SBTE1_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE 0x46D9000ull +#define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_BASE 0x46D9200ull +#define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_BASE 0x46D9400ull +#define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_BASE 0x46D9600ull +#define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE1_MSTR_IF_E2E_CRDT_BASE 0x46D9800ull +#define DCORE3_MME_SBTE1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_MME_SBTE1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_MME_SBTE1_MSTR_IF_AXUSER_BASE 0x46D9A80ull +#define DCORE3_MME_SBTE1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_MME_SBTE1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_MME_SBTE1_MSTR_IF_DBG_HBW_BASE 0x46D9B00ull +#define DCORE3_MME_SBTE1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_SBTE1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_MME_SBTE1_MSTR_IF_DBG_LBW_BASE 0x46D9B80ull +#define DCORE3_MME_SBTE1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_SBTE1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_MME_SBTE1_MSTR_IF_CORE_HBW_BASE 0x46D9C00ull +#define DCORE3_MME_SBTE1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_MME_SBTE1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_MME_SBTE1_MSTR_IF_CORE_LBW_BASE 0x46D9D80ull +#define DCORE3_MME_SBTE1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_MME_SBTE1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_MME_SBTE1_MSTR_IF_SPECIAL_BASE 0x46D9E80ull +#define DCORE3_MME_SBTE1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_SBTE1_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE3_MME_SBTE2_BASE 0x46E0000ull +#define DCORE3_MME_SBTE2_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE2_SECTION 0xE800 +#define mmDCORE3_MME_SBTE2_SPECIAL_BASE 0x46E0E80ull +#define DCORE3_MME_SBTE2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_SBTE2_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_BASE 0x46E1000ull +#define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_BASE 0x46E1200ull +#define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_BASE 0x46E1400ull +#define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_BASE 0x46E1600ull +#define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE2_MSTR_IF_E2E_CRDT_BASE 0x46E1800ull +#define DCORE3_MME_SBTE2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_MME_SBTE2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_MME_SBTE2_MSTR_IF_AXUSER_BASE 0x46E1A80ull +#define DCORE3_MME_SBTE2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_MME_SBTE2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_MME_SBTE2_MSTR_IF_DBG_HBW_BASE 0x46E1B00ull +#define DCORE3_MME_SBTE2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_SBTE2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_MME_SBTE2_MSTR_IF_DBG_LBW_BASE 0x46E1B80ull +#define DCORE3_MME_SBTE2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_SBTE2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_MME_SBTE2_MSTR_IF_CORE_HBW_BASE 0x46E1C00ull +#define DCORE3_MME_SBTE2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_MME_SBTE2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_MME_SBTE2_MSTR_IF_CORE_LBW_BASE 0x46E1D80ull +#define DCORE3_MME_SBTE2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_MME_SBTE2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_MME_SBTE2_MSTR_IF_SPECIAL_BASE 0x46E1E80ull +#define DCORE3_MME_SBTE2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_SBTE2_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE3_MME_SBTE3_BASE 0x46E8000ull +#define DCORE3_MME_SBTE3_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE3_SECTION 0xE800 +#define mmDCORE3_MME_SBTE3_SPECIAL_BASE 0x46E8E80ull +#define DCORE3_MME_SBTE3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_SBTE3_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_BASE 0x46E9000ull +#define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_BASE 0x46E9200ull +#define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_BASE 0x46E9400ull +#define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_BASE 0x46E9600ull +#define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE3_MSTR_IF_E2E_CRDT_BASE 0x46E9800ull +#define DCORE3_MME_SBTE3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_MME_SBTE3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_MME_SBTE3_MSTR_IF_AXUSER_BASE 0x46E9A80ull +#define DCORE3_MME_SBTE3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_MME_SBTE3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_MME_SBTE3_MSTR_IF_DBG_HBW_BASE 0x46E9B00ull +#define DCORE3_MME_SBTE3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_SBTE3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_MME_SBTE3_MSTR_IF_DBG_LBW_BASE 0x46E9B80ull +#define DCORE3_MME_SBTE3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_SBTE3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_MME_SBTE3_MSTR_IF_CORE_HBW_BASE 0x46E9C00ull +#define DCORE3_MME_SBTE3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_MME_SBTE3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_MME_SBTE3_MSTR_IF_CORE_LBW_BASE 0x46E9D80ull +#define DCORE3_MME_SBTE3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_MME_SBTE3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_MME_SBTE3_MSTR_IF_SPECIAL_BASE 0x46E9E80ull +#define DCORE3_MME_SBTE3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_SBTE3_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE3_MME_SBTE4_BASE 0x46F0000ull +#define DCORE3_MME_SBTE4_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE4_SECTION 0xE800 +#define mmDCORE3_MME_SBTE4_SPECIAL_BASE 0x46F0E80ull +#define DCORE3_MME_SBTE4_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_SBTE4_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_BASE 0x46F1000ull +#define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_BASE 0x46F1200ull +#define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_BASE 0x46F1400ull +#define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_BASE 0x46F1600ull +#define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_MME_SBTE4_MSTR_IF_E2E_CRDT_BASE 0x46F1800ull +#define DCORE3_MME_SBTE4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_MME_SBTE4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_MME_SBTE4_MSTR_IF_AXUSER_BASE 0x46F1A80ull +#define DCORE3_MME_SBTE4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_MME_SBTE4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_MME_SBTE4_MSTR_IF_DBG_HBW_BASE 0x46F1B00ull +#define DCORE3_MME_SBTE4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_SBTE4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_MME_SBTE4_MSTR_IF_DBG_LBW_BASE 0x46F1B80ull +#define DCORE3_MME_SBTE4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_SBTE4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_MME_SBTE4_MSTR_IF_CORE_HBW_BASE 0x46F1C00ull +#define DCORE3_MME_SBTE4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_MME_SBTE4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_MME_SBTE4_MSTR_IF_CORE_LBW_BASE 0x46F1D80ull +#define DCORE3_MME_SBTE4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_MME_SBTE4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_MME_SBTE4_MSTR_IF_SPECIAL_BASE 0x46F1E80ull +#define DCORE3_MME_SBTE4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_SBTE4_MSTR_IF_SPECIAL_SECTION 0x6180 +#define mmDCORE3_MME_ACC_BASE 0x46F8000ull +#define DCORE3_MME_ACC_MAX_OFFSET 0x1000 +#define DCORE3_MME_ACC_SECTION 0xE800 +#define mmDCORE3_MME_ACC_SPECIAL_BASE 0x46F8E80ull +#define DCORE3_MME_ACC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_ACC_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE 0x46F9000ull +#define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_MME_WB0_MSTR_IF_RR_PRVT_HBW_BASE 0x46F9200ull +#define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_MME_WB0_MSTR_IF_RR_SHRD_LBW_BASE 0x46F9400ull +#define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_MME_WB0_MSTR_IF_RR_PRVT_LBW_BASE 0x46F9600ull +#define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_MME_WB0_MSTR_IF_E2E_CRDT_BASE 0x46F9800ull +#define DCORE3_MME_WB0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_MME_WB0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_MME_WB0_MSTR_IF_AXUSER_BASE 0x46F9A80ull +#define DCORE3_MME_WB0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_MME_WB0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_MME_WB0_MSTR_IF_DBG_HBW_BASE 0x46F9B00ull +#define DCORE3_MME_WB0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_WB0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_MME_WB0_MSTR_IF_DBG_LBW_BASE 0x46F9B80ull +#define DCORE3_MME_WB0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_WB0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_MME_WB0_MSTR_IF_CORE_HBW_BASE 0x46F9C00ull +#define DCORE3_MME_WB0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_MME_WB0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_MME_WB0_MSTR_IF_CORE_LBW_BASE 0x46F9D80ull +#define DCORE3_MME_WB0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_MME_WB0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_MME_WB0_MSTR_IF_SPECIAL_BASE 0x46F9E80ull +#define DCORE3_MME_WB0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_WB0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE3_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE 0x46FA000ull +#define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_MME_WB1_MSTR_IF_RR_PRVT_HBW_BASE 0x46FA200ull +#define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_MME_WB1_MSTR_IF_RR_SHRD_LBW_BASE 0x46FA400ull +#define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_MME_WB1_MSTR_IF_RR_PRVT_LBW_BASE 0x46FA600ull +#define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_MME_WB1_MSTR_IF_E2E_CRDT_BASE 0x46FA800ull +#define DCORE3_MME_WB1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_MME_WB1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_MME_WB1_MSTR_IF_AXUSER_BASE 0x46FAA80ull +#define DCORE3_MME_WB1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_MME_WB1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_MME_WB1_MSTR_IF_DBG_HBW_BASE 0x46FAB00ull +#define DCORE3_MME_WB1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_WB1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_MME_WB1_MSTR_IF_DBG_LBW_BASE 0x46FAB80ull +#define DCORE3_MME_WB1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_MME_WB1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_MME_WB1_MSTR_IF_CORE_HBW_BASE 0x46FAC00ull +#define DCORE3_MME_WB1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_MME_WB1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_MME_WB1_MSTR_IF_CORE_LBW_BASE 0x46FAD80ull +#define DCORE3_MME_WB1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_MME_WB1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_MME_WB1_MSTR_IF_SPECIAL_BASE 0x46FAE80ull +#define DCORE3_MME_WB1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_MME_WB1_MSTR_IF_SPECIAL_SECTION 0x5180 +#define mmDCORE3_SYNC_MNGR_OBJS_BASE 0x4700000ull +#define DCORE3_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00 +#define DCORE3_SYNC_MNGR_OBJS_SECTION 0x1E000 +#define mmDCORE3_SYNC_MNGR_GLBL_BASE 0x471E000ull +#define DCORE3_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000 +#define DCORE3_SYNC_MNGR_GLBL_SECTION 0xE800 +#define mmDCORE3_SYNC_MNGR_GLBL_SPECIAL_BASE 0x471EE80ull +#define DCORE3_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x471F000ull +#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x471F200ull +#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x471F400ull +#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x471F600ull +#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x471F800ull +#define DCORE3_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x471FA80ull +#define DCORE3_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x471FB00ull +#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x471FB80ull +#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x471FC00ull +#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x471FD80ull +#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x471FE80ull +#define DCORE3_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE3_HIF0_BASE 0x4720000ull +#define DCORE3_HIF0_MAX_OFFSET 0x1000 +#define DCORE3_HIF0_SECTION 0xE800 +#define mmDCORE3_HIF0_SPECIAL_BASE 0x4720E80ull +#define DCORE3_HIF0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HIF0_SPECIAL_SECTION 0x3180 +#define mmDCORE3_HIF1_BASE 0x4724000ull +#define DCORE3_HIF1_MAX_OFFSET 0x1000 +#define DCORE3_HIF1_SECTION 0xE800 +#define mmDCORE3_HIF1_SPECIAL_BASE 0x4724E80ull +#define DCORE3_HIF1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HIF1_SPECIAL_SECTION 0x3180 +#define mmDCORE3_HIF2_BASE 0x4728000ull +#define DCORE3_HIF2_MAX_OFFSET 0x1000 +#define DCORE3_HIF2_SECTION 0xE800 +#define mmDCORE3_HIF2_SPECIAL_BASE 0x4728E80ull +#define DCORE3_HIF2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HIF2_SPECIAL_SECTION 0x3180 +#define mmDCORE3_HIF3_BASE 0x472C000ull +#define DCORE3_HIF3_MAX_OFFSET 0x1000 +#define DCORE3_HIF3_SECTION 0xE800 +#define mmDCORE3_HIF3_SPECIAL_BASE 0x472CE80ull +#define DCORE3_HIF3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HIF3_SPECIAL_SECTION 0x13180 +#define mmDCORE3_RTR0_CTRL_BASE 0x4740000ull +#define DCORE3_RTR0_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_RTR0_CTRL_SECTION 0xE800 +#define mmDCORE3_RTR0_CTRL_SPECIAL_BASE 0x4740E80ull +#define DCORE3_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR0_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR0_H3_BASE 0x4741000ull +#define DCORE3_RTR0_H3_MAX_OFFSET 0x1000 +#define DCORE3_RTR0_H3_SECTION 0xE800 +#define mmDCORE3_RTR0_H3_SPECIAL_BASE 0x4741E80ull +#define DCORE3_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR0_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x4742000ull +#define DCORE3_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x4742200ull +#define DCORE3_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x4742400ull +#define DCORE3_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x4742600ull +#define DCORE3_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_RTR0_MSTR_IF_E2E_CRDT_BASE 0x4742800ull +#define DCORE3_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_RTR0_MSTR_IF_AXUSER_BASE 0x4742A80ull +#define DCORE3_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_RTR0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_RTR0_MSTR_IF_DBG_HBW_BASE 0x4742B00ull +#define DCORE3_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_RTR0_MSTR_IF_DBG_LBW_BASE 0x4742B80ull +#define DCORE3_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_RTR0_MSTR_IF_CORE_HBW_BASE 0x4742C00ull +#define DCORE3_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_RTR0_MSTR_IF_CORE_LBW_BASE 0x4742D80ull +#define DCORE3_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_RTR0_MSTR_IF_SPECIAL_BASE 0x4742E80ull +#define DCORE3_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR0_ADD_DEC_HBW_BASE 0x4743000ull +#define DCORE3_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE3_RTR0_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE3_RTR0_ADD_DEC_LBW_BASE 0x4743400ull +#define DCORE3_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE3_RTR0_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE3_RTR0_ADD_DEC_SPECIAL_BASE 0x4743E80ull +#define DCORE3_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR0_BASE 0x4744000ull +#define DCORE3_RTR0_MAX_OFFSET 0x1000 +#define DCORE3_RTR0_SECTION 0x3000 +#define mmDCORE3_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x4744300ull +#define DCORE3_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR0_HBW_RD_RS_LL_STAT_BASE 0x4744340ull +#define DCORE3_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x4744380ull +#define DCORE3_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR0_HBW_WR_RS_LL_STAT_BASE 0x47443C0ull +#define DCORE3_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x4744400ull +#define DCORE3_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR0_LBW_RD_RS_LL_STAT_BASE 0x4744440ull +#define DCORE3_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x4744480ull +#define DCORE3_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR0_LBW_WR_RS_LL_STAT_BASE 0x47444C0ull +#define DCORE3_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR0_HBW_MFIFO_BASE 0x4744500ull +#define DCORE3_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE3_RTR0_E2E_RD_LL_STAT_BASE 0x4744540ull +#define DCORE3_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR0_E2E_WR_LL_STAT_BASE 0x4744580ull +#define DCORE3_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE3_RTR0_RTR_HBW_XACT_STAT_BASE 0x4744600ull +#define DCORE3_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR0_RTR_LBW_XACT_STAT_BASE 0x4744680ull +#define DCORE3_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR0_RTR_E2E_XACT_STAT_BASE 0x4744700ull +#define DCORE3_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE3_RTR0_SPECIAL_BASE 0x4744E80ull +#define DCORE3_RTR0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR0_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR0_DBG_ADDR_BASE 0x4745000ull +#define DCORE3_RTR0_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE3_RTR0_DBG_ADDR_SECTION 0xE800 +#define mmDCORE3_RTR0_DBG_ADDR_SPECIAL_BASE 0x4745E80ull +#define DCORE3_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE3_RTR1_CTRL_BASE 0x4748000ull +#define DCORE3_RTR1_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_RTR1_CTRL_SECTION 0xE800 +#define mmDCORE3_RTR1_CTRL_SPECIAL_BASE 0x4748E80ull +#define DCORE3_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR1_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR1_H3_BASE 0x4749000ull +#define DCORE3_RTR1_H3_MAX_OFFSET 0x1000 +#define DCORE3_RTR1_H3_SECTION 0xE800 +#define mmDCORE3_RTR1_H3_SPECIAL_BASE 0x4749E80ull +#define DCORE3_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR1_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x474A000ull +#define DCORE3_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x474A200ull +#define DCORE3_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x474A400ull +#define DCORE3_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x474A600ull +#define DCORE3_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_RTR1_MSTR_IF_E2E_CRDT_BASE 0x474A800ull +#define DCORE3_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_RTR1_MSTR_IF_AXUSER_BASE 0x474AA80ull +#define DCORE3_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_RTR1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_RTR1_MSTR_IF_DBG_HBW_BASE 0x474AB00ull +#define DCORE3_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_RTR1_MSTR_IF_DBG_LBW_BASE 0x474AB80ull +#define DCORE3_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_RTR1_MSTR_IF_CORE_HBW_BASE 0x474AC00ull +#define DCORE3_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_RTR1_MSTR_IF_CORE_LBW_BASE 0x474AD80ull +#define DCORE3_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_RTR1_MSTR_IF_SPECIAL_BASE 0x474AE80ull +#define DCORE3_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR1_ADD_DEC_HBW_BASE 0x474B000ull +#define DCORE3_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE3_RTR1_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE3_RTR1_ADD_DEC_LBW_BASE 0x474B400ull +#define DCORE3_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE3_RTR1_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE3_RTR1_ADD_DEC_SPECIAL_BASE 0x474BE80ull +#define DCORE3_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR1_BASE 0x474C000ull +#define DCORE3_RTR1_MAX_OFFSET 0x1000 +#define DCORE3_RTR1_SECTION 0x3000 +#define mmDCORE3_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x474C300ull +#define DCORE3_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR1_HBW_RD_RS_LL_STAT_BASE 0x474C340ull +#define DCORE3_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x474C380ull +#define DCORE3_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR1_HBW_WR_RS_LL_STAT_BASE 0x474C3C0ull +#define DCORE3_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x474C400ull +#define DCORE3_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR1_LBW_RD_RS_LL_STAT_BASE 0x474C440ull +#define DCORE3_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x474C480ull +#define DCORE3_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR1_LBW_WR_RS_LL_STAT_BASE 0x474C4C0ull +#define DCORE3_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR1_HBW_MFIFO_BASE 0x474C500ull +#define DCORE3_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE3_RTR1_E2E_RD_LL_STAT_BASE 0x474C540ull +#define DCORE3_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR1_E2E_WR_LL_STAT_BASE 0x474C580ull +#define DCORE3_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE3_RTR1_RTR_HBW_XACT_STAT_BASE 0x474C600ull +#define DCORE3_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR1_RTR_LBW_XACT_STAT_BASE 0x474C680ull +#define DCORE3_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR1_RTR_E2E_XACT_STAT_BASE 0x474C700ull +#define DCORE3_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE3_RTR1_SPECIAL_BASE 0x474CE80ull +#define DCORE3_RTR1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR1_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR1_DBG_ADDR_BASE 0x474D000ull +#define DCORE3_RTR1_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE3_RTR1_DBG_ADDR_SECTION 0xE800 +#define mmDCORE3_RTR1_DBG_ADDR_SPECIAL_BASE 0x474DE80ull +#define DCORE3_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE3_RTR2_CTRL_BASE 0x4750000ull +#define DCORE3_RTR2_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_RTR2_CTRL_SECTION 0xE800 +#define mmDCORE3_RTR2_CTRL_SPECIAL_BASE 0x4750E80ull +#define DCORE3_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR2_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR2_H3_BASE 0x4751000ull +#define DCORE3_RTR2_H3_MAX_OFFSET 0x1000 +#define DCORE3_RTR2_H3_SECTION 0xE800 +#define mmDCORE3_RTR2_H3_SPECIAL_BASE 0x4751E80ull +#define DCORE3_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR2_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x4752000ull +#define DCORE3_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x4752200ull +#define DCORE3_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x4752400ull +#define DCORE3_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x4752600ull +#define DCORE3_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_RTR2_MSTR_IF_E2E_CRDT_BASE 0x4752800ull +#define DCORE3_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_RTR2_MSTR_IF_AXUSER_BASE 0x4752A80ull +#define DCORE3_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_RTR2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_RTR2_MSTR_IF_DBG_HBW_BASE 0x4752B00ull +#define DCORE3_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_RTR2_MSTR_IF_DBG_LBW_BASE 0x4752B80ull +#define DCORE3_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_RTR2_MSTR_IF_CORE_HBW_BASE 0x4752C00ull +#define DCORE3_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_RTR2_MSTR_IF_CORE_LBW_BASE 0x4752D80ull +#define DCORE3_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_RTR2_MSTR_IF_SPECIAL_BASE 0x4752E80ull +#define DCORE3_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR2_ADD_DEC_HBW_BASE 0x4753000ull +#define DCORE3_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE3_RTR2_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE3_RTR2_ADD_DEC_LBW_BASE 0x4753400ull +#define DCORE3_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE3_RTR2_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE3_RTR2_ADD_DEC_SPECIAL_BASE 0x4753E80ull +#define DCORE3_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR2_BASE 0x4754000ull +#define DCORE3_RTR2_MAX_OFFSET 0x1000 +#define DCORE3_RTR2_SECTION 0x3000 +#define mmDCORE3_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x4754300ull +#define DCORE3_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR2_HBW_RD_RS_LL_STAT_BASE 0x4754340ull +#define DCORE3_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x4754380ull +#define DCORE3_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR2_HBW_WR_RS_LL_STAT_BASE 0x47543C0ull +#define DCORE3_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x4754400ull +#define DCORE3_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR2_LBW_RD_RS_LL_STAT_BASE 0x4754440ull +#define DCORE3_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x4754480ull +#define DCORE3_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR2_LBW_WR_RS_LL_STAT_BASE 0x47544C0ull +#define DCORE3_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR2_HBW_MFIFO_BASE 0x4754500ull +#define DCORE3_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE3_RTR2_E2E_RD_LL_STAT_BASE 0x4754540ull +#define DCORE3_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR2_E2E_WR_LL_STAT_BASE 0x4754580ull +#define DCORE3_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE3_RTR2_RTR_HBW_XACT_STAT_BASE 0x4754600ull +#define DCORE3_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR2_RTR_LBW_XACT_STAT_BASE 0x4754680ull +#define DCORE3_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR2_RTR_E2E_XACT_STAT_BASE 0x4754700ull +#define DCORE3_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE3_RTR2_SPECIAL_BASE 0x4754E80ull +#define DCORE3_RTR2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR2_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR2_DBG_ADDR_BASE 0x4755000ull +#define DCORE3_RTR2_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE3_RTR2_DBG_ADDR_SECTION 0xE800 +#define mmDCORE3_RTR2_DBG_ADDR_SPECIAL_BASE 0x4755E80ull +#define DCORE3_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE3_RTR3_CTRL_BASE 0x4758000ull +#define DCORE3_RTR3_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_RTR3_CTRL_SECTION 0xE800 +#define mmDCORE3_RTR3_CTRL_SPECIAL_BASE 0x4758E80ull +#define DCORE3_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR3_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR3_H3_BASE 0x4759000ull +#define DCORE3_RTR3_H3_MAX_OFFSET 0x1000 +#define DCORE3_RTR3_H3_SECTION 0xE800 +#define mmDCORE3_RTR3_H3_SPECIAL_BASE 0x4759E80ull +#define DCORE3_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR3_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x475A000ull +#define DCORE3_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x475A200ull +#define DCORE3_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x475A400ull +#define DCORE3_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x475A600ull +#define DCORE3_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_RTR3_MSTR_IF_E2E_CRDT_BASE 0x475A800ull +#define DCORE3_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_RTR3_MSTR_IF_AXUSER_BASE 0x475AA80ull +#define DCORE3_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_RTR3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_RTR3_MSTR_IF_DBG_HBW_BASE 0x475AB00ull +#define DCORE3_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_RTR3_MSTR_IF_DBG_LBW_BASE 0x475AB80ull +#define DCORE3_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_RTR3_MSTR_IF_CORE_HBW_BASE 0x475AC00ull +#define DCORE3_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_RTR3_MSTR_IF_CORE_LBW_BASE 0x475AD80ull +#define DCORE3_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_RTR3_MSTR_IF_SPECIAL_BASE 0x475AE80ull +#define DCORE3_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR3_ADD_DEC_HBW_BASE 0x475B000ull +#define DCORE3_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE3_RTR3_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE3_RTR3_ADD_DEC_LBW_BASE 0x475B400ull +#define DCORE3_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE3_RTR3_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE3_RTR3_ADD_DEC_SPECIAL_BASE 0x475BE80ull +#define DCORE3_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR3_BASE 0x475C000ull +#define DCORE3_RTR3_MAX_OFFSET 0x1000 +#define DCORE3_RTR3_SECTION 0x3000 +#define mmDCORE3_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x475C300ull +#define DCORE3_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR3_HBW_RD_RS_LL_STAT_BASE 0x475C340ull +#define DCORE3_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x475C380ull +#define DCORE3_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR3_HBW_WR_RS_LL_STAT_BASE 0x475C3C0ull +#define DCORE3_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x475C400ull +#define DCORE3_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR3_LBW_RD_RS_LL_STAT_BASE 0x475C440ull +#define DCORE3_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x475C480ull +#define DCORE3_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR3_LBW_WR_RS_LL_STAT_BASE 0x475C4C0ull +#define DCORE3_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR3_HBW_MFIFO_BASE 0x475C500ull +#define DCORE3_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE3_RTR3_E2E_RD_LL_STAT_BASE 0x475C540ull +#define DCORE3_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR3_E2E_WR_LL_STAT_BASE 0x475C580ull +#define DCORE3_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE3_RTR3_RTR_HBW_XACT_STAT_BASE 0x475C600ull +#define DCORE3_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR3_RTR_LBW_XACT_STAT_BASE 0x475C680ull +#define DCORE3_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR3_RTR_E2E_XACT_STAT_BASE 0x475C700ull +#define DCORE3_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE3_RTR3_SPECIAL_BASE 0x475CE80ull +#define DCORE3_RTR3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR3_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR3_DBG_ADDR_BASE 0x475D000ull +#define DCORE3_RTR3_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE3_RTR3_DBG_ADDR_SECTION 0xE800 +#define mmDCORE3_RTR3_DBG_ADDR_SPECIAL_BASE 0x475DE80ull +#define DCORE3_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE3_RTR4_CTRL_BASE 0x4760000ull +#define DCORE3_RTR4_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_RTR4_CTRL_SECTION 0xE800 +#define mmDCORE3_RTR4_CTRL_SPECIAL_BASE 0x4760E80ull +#define DCORE3_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR4_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR4_H3_BASE 0x4761000ull +#define DCORE3_RTR4_H3_MAX_OFFSET 0x1000 +#define DCORE3_RTR4_H3_SECTION 0xE800 +#define mmDCORE3_RTR4_H3_SPECIAL_BASE 0x4761E80ull +#define DCORE3_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR4_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x4762000ull +#define DCORE3_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x4762200ull +#define DCORE3_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x4762400ull +#define DCORE3_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x4762600ull +#define DCORE3_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_RTR4_MSTR_IF_E2E_CRDT_BASE 0x4762800ull +#define DCORE3_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_RTR4_MSTR_IF_AXUSER_BASE 0x4762A80ull +#define DCORE3_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_RTR4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_RTR4_MSTR_IF_DBG_HBW_BASE 0x4762B00ull +#define DCORE3_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_RTR4_MSTR_IF_DBG_LBW_BASE 0x4762B80ull +#define DCORE3_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_RTR4_MSTR_IF_CORE_HBW_BASE 0x4762C00ull +#define DCORE3_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_RTR4_MSTR_IF_CORE_LBW_BASE 0x4762D80ull +#define DCORE3_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_RTR4_MSTR_IF_SPECIAL_BASE 0x4762E80ull +#define DCORE3_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR4_ADD_DEC_HBW_BASE 0x4763000ull +#define DCORE3_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE3_RTR4_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE3_RTR4_ADD_DEC_LBW_BASE 0x4763400ull +#define DCORE3_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE3_RTR4_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE3_RTR4_ADD_DEC_SPECIAL_BASE 0x4763E80ull +#define DCORE3_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR4_BASE 0x4764000ull +#define DCORE3_RTR4_MAX_OFFSET 0x1000 +#define DCORE3_RTR4_SECTION 0x3000 +#define mmDCORE3_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x4764300ull +#define DCORE3_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR4_HBW_RD_RS_LL_STAT_BASE 0x4764340ull +#define DCORE3_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x4764380ull +#define DCORE3_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR4_HBW_WR_RS_LL_STAT_BASE 0x47643C0ull +#define DCORE3_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x4764400ull +#define DCORE3_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR4_LBW_RD_RS_LL_STAT_BASE 0x4764440ull +#define DCORE3_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x4764480ull +#define DCORE3_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR4_LBW_WR_RS_LL_STAT_BASE 0x47644C0ull +#define DCORE3_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR4_HBW_MFIFO_BASE 0x4764500ull +#define DCORE3_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE3_RTR4_E2E_RD_LL_STAT_BASE 0x4764540ull +#define DCORE3_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR4_E2E_WR_LL_STAT_BASE 0x4764580ull +#define DCORE3_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE3_RTR4_RTR_HBW_XACT_STAT_BASE 0x4764600ull +#define DCORE3_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR4_RTR_LBW_XACT_STAT_BASE 0x4764680ull +#define DCORE3_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR4_RTR_E2E_XACT_STAT_BASE 0x4764700ull +#define DCORE3_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE3_RTR4_SPECIAL_BASE 0x4764E80ull +#define DCORE3_RTR4_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR4_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR4_DBG_ADDR_BASE 0x4765000ull +#define DCORE3_RTR4_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE3_RTR4_DBG_ADDR_SECTION 0xE800 +#define mmDCORE3_RTR4_DBG_ADDR_SPECIAL_BASE 0x4765E80ull +#define DCORE3_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE3_RTR5_CTRL_BASE 0x4768000ull +#define DCORE3_RTR5_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_RTR5_CTRL_SECTION 0xE800 +#define mmDCORE3_RTR5_CTRL_SPECIAL_BASE 0x4768E80ull +#define DCORE3_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR5_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR5_H3_BASE 0x4769000ull +#define DCORE3_RTR5_H3_MAX_OFFSET 0x1000 +#define DCORE3_RTR5_H3_SECTION 0xE800 +#define mmDCORE3_RTR5_H3_SPECIAL_BASE 0x4769E80ull +#define DCORE3_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR5_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x476A000ull +#define DCORE3_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x476A200ull +#define DCORE3_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x476A400ull +#define DCORE3_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x476A600ull +#define DCORE3_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_RTR5_MSTR_IF_E2E_CRDT_BASE 0x476A800ull +#define DCORE3_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_RTR5_MSTR_IF_AXUSER_BASE 0x476AA80ull +#define DCORE3_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_RTR5_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_RTR5_MSTR_IF_DBG_HBW_BASE 0x476AB00ull +#define DCORE3_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_RTR5_MSTR_IF_DBG_LBW_BASE 0x476AB80ull +#define DCORE3_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_RTR5_MSTR_IF_CORE_HBW_BASE 0x476AC00ull +#define DCORE3_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_RTR5_MSTR_IF_CORE_LBW_BASE 0x476AD80ull +#define DCORE3_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_RTR5_MSTR_IF_SPECIAL_BASE 0x476AE80ull +#define DCORE3_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR5_ADD_DEC_HBW_BASE 0x476B000ull +#define DCORE3_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE3_RTR5_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE3_RTR5_ADD_DEC_LBW_BASE 0x476B400ull +#define DCORE3_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE3_RTR5_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE3_RTR5_ADD_DEC_SPECIAL_BASE 0x476BE80ull +#define DCORE3_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR5_BASE 0x476C000ull +#define DCORE3_RTR5_MAX_OFFSET 0x1000 +#define DCORE3_RTR5_SECTION 0x3000 +#define mmDCORE3_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x476C300ull +#define DCORE3_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR5_HBW_RD_RS_LL_STAT_BASE 0x476C340ull +#define DCORE3_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x476C380ull +#define DCORE3_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR5_HBW_WR_RS_LL_STAT_BASE 0x476C3C0ull +#define DCORE3_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x476C400ull +#define DCORE3_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR5_LBW_RD_RS_LL_STAT_BASE 0x476C440ull +#define DCORE3_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x476C480ull +#define DCORE3_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR5_LBW_WR_RS_LL_STAT_BASE 0x476C4C0ull +#define DCORE3_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR5_HBW_MFIFO_BASE 0x476C500ull +#define DCORE3_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE3_RTR5_E2E_RD_LL_STAT_BASE 0x476C540ull +#define DCORE3_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR5_E2E_WR_LL_STAT_BASE 0x476C580ull +#define DCORE3_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE3_RTR5_RTR_HBW_XACT_STAT_BASE 0x476C600ull +#define DCORE3_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR5_RTR_LBW_XACT_STAT_BASE 0x476C680ull +#define DCORE3_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR5_RTR_E2E_XACT_STAT_BASE 0x476C700ull +#define DCORE3_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE3_RTR5_SPECIAL_BASE 0x476CE80ull +#define DCORE3_RTR5_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR5_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR5_DBG_ADDR_BASE 0x476D000ull +#define DCORE3_RTR5_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE3_RTR5_DBG_ADDR_SECTION 0xE800 +#define mmDCORE3_RTR5_DBG_ADDR_SPECIAL_BASE 0x476DE80ull +#define DCORE3_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE3_RTR6_CTRL_BASE 0x4770000ull +#define DCORE3_RTR6_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_RTR6_CTRL_SECTION 0xE800 +#define mmDCORE3_RTR6_CTRL_SPECIAL_BASE 0x4770E80ull +#define DCORE3_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR6_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR6_H3_BASE 0x4771000ull +#define DCORE3_RTR6_H3_MAX_OFFSET 0x1000 +#define DCORE3_RTR6_H3_SECTION 0xE800 +#define mmDCORE3_RTR6_H3_SPECIAL_BASE 0x4771E80ull +#define DCORE3_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR6_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x4772000ull +#define DCORE3_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x4772200ull +#define DCORE3_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x4772400ull +#define DCORE3_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x4772600ull +#define DCORE3_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_RTR6_MSTR_IF_E2E_CRDT_BASE 0x4772800ull +#define DCORE3_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_RTR6_MSTR_IF_AXUSER_BASE 0x4772A80ull +#define DCORE3_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_RTR6_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_RTR6_MSTR_IF_DBG_HBW_BASE 0x4772B00ull +#define DCORE3_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_RTR6_MSTR_IF_DBG_LBW_BASE 0x4772B80ull +#define DCORE3_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_RTR6_MSTR_IF_CORE_HBW_BASE 0x4772C00ull +#define DCORE3_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_RTR6_MSTR_IF_CORE_LBW_BASE 0x4772D80ull +#define DCORE3_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_RTR6_MSTR_IF_SPECIAL_BASE 0x4772E80ull +#define DCORE3_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR6_ADD_DEC_HBW_BASE 0x4773000ull +#define DCORE3_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE3_RTR6_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE3_RTR6_ADD_DEC_LBW_BASE 0x4773400ull +#define DCORE3_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE3_RTR6_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE3_RTR6_ADD_DEC_SPECIAL_BASE 0x4773E80ull +#define DCORE3_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR6_BASE 0x4774000ull +#define DCORE3_RTR6_MAX_OFFSET 0x1000 +#define DCORE3_RTR6_SECTION 0x3000 +#define mmDCORE3_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x4774300ull +#define DCORE3_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR6_HBW_RD_RS_LL_STAT_BASE 0x4774340ull +#define DCORE3_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x4774380ull +#define DCORE3_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR6_HBW_WR_RS_LL_STAT_BASE 0x47743C0ull +#define DCORE3_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x4774400ull +#define DCORE3_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR6_LBW_RD_RS_LL_STAT_BASE 0x4774440ull +#define DCORE3_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x4774480ull +#define DCORE3_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR6_LBW_WR_RS_LL_STAT_BASE 0x47744C0ull +#define DCORE3_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR6_HBW_MFIFO_BASE 0x4774500ull +#define DCORE3_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE3_RTR6_E2E_RD_LL_STAT_BASE 0x4774540ull +#define DCORE3_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR6_E2E_WR_LL_STAT_BASE 0x4774580ull +#define DCORE3_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE3_RTR6_RTR_HBW_XACT_STAT_BASE 0x4774600ull +#define DCORE3_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR6_RTR_LBW_XACT_STAT_BASE 0x4774680ull +#define DCORE3_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR6_RTR_E2E_XACT_STAT_BASE 0x4774700ull +#define DCORE3_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE3_RTR6_SPECIAL_BASE 0x4774E80ull +#define DCORE3_RTR6_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR6_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR6_DBG_ADDR_BASE 0x4775000ull +#define DCORE3_RTR6_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE3_RTR6_DBG_ADDR_SECTION 0xE800 +#define mmDCORE3_RTR6_DBG_ADDR_SPECIAL_BASE 0x4775E80ull +#define DCORE3_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE3_RTR7_CTRL_BASE 0x4778000ull +#define DCORE3_RTR7_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_RTR7_CTRL_SECTION 0xE800 +#define mmDCORE3_RTR7_CTRL_SPECIAL_BASE 0x4778E80ull +#define DCORE3_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR7_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR7_H3_BASE 0x4779000ull +#define DCORE3_RTR7_H3_MAX_OFFSET 0x1000 +#define DCORE3_RTR7_H3_SECTION 0xE800 +#define mmDCORE3_RTR7_H3_SPECIAL_BASE 0x4779E80ull +#define DCORE3_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR7_H3_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x477A000ull +#define DCORE3_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x477A200ull +#define DCORE3_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x477A400ull +#define DCORE3_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x477A600ull +#define DCORE3_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_RTR7_MSTR_IF_E2E_CRDT_BASE 0x477A800ull +#define DCORE3_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_RTR7_MSTR_IF_AXUSER_BASE 0x477AA80ull +#define DCORE3_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_RTR7_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_RTR7_MSTR_IF_DBG_HBW_BASE 0x477AB00ull +#define DCORE3_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_RTR7_MSTR_IF_DBG_LBW_BASE 0x477AB80ull +#define DCORE3_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_RTR7_MSTR_IF_CORE_HBW_BASE 0x477AC00ull +#define DCORE3_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_RTR7_MSTR_IF_CORE_LBW_BASE 0x477AD80ull +#define DCORE3_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_RTR7_MSTR_IF_SPECIAL_BASE 0x477AE80ull +#define DCORE3_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR7_ADD_DEC_HBW_BASE 0x477B000ull +#define DCORE3_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE3_RTR7_ADD_DEC_HBW_SECTION 0x4000 +#define mmDCORE3_RTR7_ADD_DEC_LBW_BASE 0x477B400ull +#define DCORE3_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE3_RTR7_ADD_DEC_LBW_SECTION 0xA800 +#define mmDCORE3_RTR7_ADD_DEC_SPECIAL_BASE 0x477BE80ull +#define DCORE3_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR7_BASE 0x477C000ull +#define DCORE3_RTR7_MAX_OFFSET 0x1000 +#define DCORE3_RTR7_SECTION 0x3000 +#define mmDCORE3_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x477C300ull +#define DCORE3_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR7_HBW_RD_RS_LL_STAT_BASE 0x477C340ull +#define DCORE3_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x477C380ull +#define DCORE3_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR7_HBW_WR_RS_LL_STAT_BASE 0x477C3C0ull +#define DCORE3_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x477C400ull +#define DCORE3_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR7_LBW_RD_RS_LL_STAT_BASE 0x477C440ull +#define DCORE3_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x477C480ull +#define DCORE3_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR7_LBW_WR_RS_LL_STAT_BASE 0x477C4C0ull +#define DCORE3_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR7_HBW_MFIFO_BASE 0x477C500ull +#define DCORE3_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_HBW_MFIFO_SECTION 0x4000 +#define mmDCORE3_RTR7_E2E_RD_LL_STAT_BASE 0x477C540ull +#define DCORE3_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_E2E_RD_LL_STAT_SECTION 0x4000 +#define mmDCORE3_RTR7_E2E_WR_LL_STAT_BASE 0x477C580ull +#define DCORE3_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_E2E_WR_LL_STAT_SECTION 0x8000 +#define mmDCORE3_RTR7_RTR_HBW_XACT_STAT_BASE 0x477C600ull +#define DCORE3_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR7_RTR_LBW_XACT_STAT_BASE 0x477C680ull +#define DCORE3_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000 +#define mmDCORE3_RTR7_RTR_E2E_XACT_STAT_BASE 0x477C700ull +#define DCORE3_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800 +#define mmDCORE3_RTR7_SPECIAL_BASE 0x477CE80ull +#define DCORE3_RTR7_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR7_SPECIAL_SECTION 0x1800 +#define mmDCORE3_RTR7_DBG_ADDR_BASE 0x477D000ull +#define DCORE3_RTR7_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE3_RTR7_DBG_ADDR_SECTION 0xE800 +#define mmDCORE3_RTR7_DBG_ADDR_SPECIAL_BASE 0x477DE80ull +#define DCORE3_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180 +#define mmDCORE3_SRAM0_BANK_BASE 0x4780000ull +#define DCORE3_SRAM0_BANK_MAX_OFFSET 0x1000 +#define DCORE3_SRAM0_BANK_SECTION 0xE800 +#define mmDCORE3_SRAM0_BANK_SPECIAL_BASE 0x4780E80ull +#define DCORE3_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM0_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM0_RTR_BASE 0x4781000ull +#define DCORE3_SRAM0_RTR_MAX_OFFSET 0x1000 +#define DCORE3_SRAM0_RTR_SECTION 0xE800 +#define mmDCORE3_SRAM0_RTR_SPECIAL_BASE 0x4781E80ull +#define DCORE3_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM0_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4782000ull +#define DCORE3_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4782100ull +#define DCORE3_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4782200ull +#define DCORE3_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4782300ull +#define DCORE3_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4782400ull +#define DCORE3_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4782500ull +#define DCORE3_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4782600ull +#define DCORE3_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4782700ull +#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4782780ull +#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4782800ull +#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4782880ull +#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4782900ull +#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4782980ull +#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4782A00ull +#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4782A80ull +#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE3_SRAM0_DBG_CNT_SPECIAL_BASE 0x4782E80ull +#define DCORE3_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE3_SRAM1_BANK_BASE 0x4788000ull +#define DCORE3_SRAM1_BANK_MAX_OFFSET 0x1000 +#define DCORE3_SRAM1_BANK_SECTION 0xE800 +#define mmDCORE3_SRAM1_BANK_SPECIAL_BASE 0x4788E80ull +#define DCORE3_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM1_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM1_RTR_BASE 0x4789000ull +#define DCORE3_SRAM1_RTR_MAX_OFFSET 0x1000 +#define DCORE3_SRAM1_RTR_SECTION 0xE800 +#define mmDCORE3_SRAM1_RTR_SPECIAL_BASE 0x4789E80ull +#define DCORE3_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM1_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x478A000ull +#define DCORE3_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x478A100ull +#define DCORE3_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x478A200ull +#define DCORE3_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x478A300ull +#define DCORE3_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x478A400ull +#define DCORE3_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x478A500ull +#define DCORE3_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x478A600ull +#define DCORE3_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x478A700ull +#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x478A780ull +#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x478A800ull +#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x478A880ull +#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x478A900ull +#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x478A980ull +#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x478AA00ull +#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x478AA80ull +#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE3_SRAM1_DBG_CNT_SPECIAL_BASE 0x478AE80ull +#define DCORE3_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE3_SRAM2_BANK_BASE 0x4790000ull +#define DCORE3_SRAM2_BANK_MAX_OFFSET 0x1000 +#define DCORE3_SRAM2_BANK_SECTION 0xE800 +#define mmDCORE3_SRAM2_BANK_SPECIAL_BASE 0x4790E80ull +#define DCORE3_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM2_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM2_RTR_BASE 0x4791000ull +#define DCORE3_SRAM2_RTR_MAX_OFFSET 0x1000 +#define DCORE3_SRAM2_RTR_SECTION 0xE800 +#define mmDCORE3_SRAM2_RTR_SPECIAL_BASE 0x4791E80ull +#define DCORE3_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM2_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4792000ull +#define DCORE3_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4792100ull +#define DCORE3_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4792200ull +#define DCORE3_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4792300ull +#define DCORE3_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4792400ull +#define DCORE3_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4792500ull +#define DCORE3_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4792600ull +#define DCORE3_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4792700ull +#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4792780ull +#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4792800ull +#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4792880ull +#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4792900ull +#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4792980ull +#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4792A00ull +#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4792A80ull +#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE3_SRAM2_DBG_CNT_SPECIAL_BASE 0x4792E80ull +#define DCORE3_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE3_SRAM3_BANK_BASE 0x4798000ull +#define DCORE3_SRAM3_BANK_MAX_OFFSET 0x1000 +#define DCORE3_SRAM3_BANK_SECTION 0xE800 +#define mmDCORE3_SRAM3_BANK_SPECIAL_BASE 0x4798E80ull +#define DCORE3_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM3_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM3_RTR_BASE 0x4799000ull +#define DCORE3_SRAM3_RTR_MAX_OFFSET 0x1000 +#define DCORE3_SRAM3_RTR_SECTION 0xE800 +#define mmDCORE3_SRAM3_RTR_SPECIAL_BASE 0x4799E80ull +#define DCORE3_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM3_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x479A000ull +#define DCORE3_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x479A100ull +#define DCORE3_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x479A200ull +#define DCORE3_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x479A300ull +#define DCORE3_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x479A400ull +#define DCORE3_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x479A500ull +#define DCORE3_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x479A600ull +#define DCORE3_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x479A700ull +#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x479A780ull +#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x479A800ull +#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x479A880ull +#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x479A900ull +#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x479A980ull +#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x479AA00ull +#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x479AA80ull +#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE3_SRAM3_DBG_CNT_SPECIAL_BASE 0x479AE80ull +#define DCORE3_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE3_SRAM4_BANK_BASE 0x47A0000ull +#define DCORE3_SRAM4_BANK_MAX_OFFSET 0x1000 +#define DCORE3_SRAM4_BANK_SECTION 0xE800 +#define mmDCORE3_SRAM4_BANK_SPECIAL_BASE 0x47A0E80ull +#define DCORE3_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM4_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM4_RTR_BASE 0x47A1000ull +#define DCORE3_SRAM4_RTR_MAX_OFFSET 0x1000 +#define DCORE3_SRAM4_RTR_SECTION 0xE800 +#define mmDCORE3_SRAM4_RTR_SPECIAL_BASE 0x47A1E80ull +#define DCORE3_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM4_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x47A2000ull +#define DCORE3_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x47A2100ull +#define DCORE3_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x47A2200ull +#define DCORE3_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x47A2300ull +#define DCORE3_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x47A2400ull +#define DCORE3_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x47A2500ull +#define DCORE3_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x47A2600ull +#define DCORE3_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x47A2700ull +#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x47A2780ull +#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x47A2800ull +#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x47A2880ull +#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x47A2900ull +#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x47A2980ull +#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x47A2A00ull +#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x47A2A80ull +#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE3_SRAM4_DBG_CNT_SPECIAL_BASE 0x47A2E80ull +#define DCORE3_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE3_SRAM5_BANK_BASE 0x47A8000ull +#define DCORE3_SRAM5_BANK_MAX_OFFSET 0x1000 +#define DCORE3_SRAM5_BANK_SECTION 0xE800 +#define mmDCORE3_SRAM5_BANK_SPECIAL_BASE 0x47A8E80ull +#define DCORE3_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM5_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM5_RTR_BASE 0x47A9000ull +#define DCORE3_SRAM5_RTR_MAX_OFFSET 0x1000 +#define DCORE3_SRAM5_RTR_SECTION 0xE800 +#define mmDCORE3_SRAM5_RTR_SPECIAL_BASE 0x47A9E80ull +#define DCORE3_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM5_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x47AA000ull +#define DCORE3_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x47AA100ull +#define DCORE3_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x47AA200ull +#define DCORE3_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x47AA300ull +#define DCORE3_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x47AA400ull +#define DCORE3_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x47AA500ull +#define DCORE3_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x47AA600ull +#define DCORE3_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x47AA700ull +#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x47AA780ull +#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x47AA800ull +#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x47AA880ull +#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x47AA900ull +#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x47AA980ull +#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x47AAA00ull +#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x47AAA80ull +#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE3_SRAM5_DBG_CNT_SPECIAL_BASE 0x47AAE80ull +#define DCORE3_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE3_SRAM6_BANK_BASE 0x47B0000ull +#define DCORE3_SRAM6_BANK_MAX_OFFSET 0x1000 +#define DCORE3_SRAM6_BANK_SECTION 0xE800 +#define mmDCORE3_SRAM6_BANK_SPECIAL_BASE 0x47B0E80ull +#define DCORE3_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM6_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM6_RTR_BASE 0x47B1000ull +#define DCORE3_SRAM6_RTR_MAX_OFFSET 0x1000 +#define DCORE3_SRAM6_RTR_SECTION 0xE800 +#define mmDCORE3_SRAM6_RTR_SPECIAL_BASE 0x47B1E80ull +#define DCORE3_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM6_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x47B2000ull +#define DCORE3_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x47B2100ull +#define DCORE3_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x47B2200ull +#define DCORE3_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x47B2300ull +#define DCORE3_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x47B2400ull +#define DCORE3_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x47B2500ull +#define DCORE3_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x47B2600ull +#define DCORE3_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x47B2700ull +#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x47B2780ull +#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x47B2800ull +#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x47B2880ull +#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x47B2900ull +#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x47B2980ull +#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x47B2A00ull +#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x47B2A80ull +#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE3_SRAM6_DBG_CNT_SPECIAL_BASE 0x47B2E80ull +#define DCORE3_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE3_SRAM7_BANK_BASE 0x47B8000ull +#define DCORE3_SRAM7_BANK_MAX_OFFSET 0x1000 +#define DCORE3_SRAM7_BANK_SECTION 0xE800 +#define mmDCORE3_SRAM7_BANK_SPECIAL_BASE 0x47B8E80ull +#define DCORE3_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM7_BANK_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM7_RTR_BASE 0x47B9000ull +#define DCORE3_SRAM7_RTR_MAX_OFFSET 0x1000 +#define DCORE3_SRAM7_RTR_SECTION 0xE800 +#define mmDCORE3_SRAM7_RTR_SPECIAL_BASE 0x47B9E80ull +#define DCORE3_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM7_RTR_SPECIAL_SECTION 0x1800 +#define mmDCORE3_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x47BA000ull +#define DCORE3_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x47BA100ull +#define DCORE3_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x47BA200ull +#define DCORE3_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x47BA300ull +#define DCORE3_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x47BA400ull +#define DCORE3_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x47BA500ull +#define DCORE3_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x47BA600ull +#define DCORE3_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 +#define mmDCORE3_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x47BA700ull +#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x47BA780ull +#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x47BA800ull +#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x47BA880ull +#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x47BA900ull +#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x47BA980ull +#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x47BAA00ull +#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 +#define mmDCORE3_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x47BAA80ull +#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 +#define mmDCORE3_SRAM7_DBG_CNT_SPECIAL_BASE 0x47BAE80ull +#define DCORE3_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180 +#define mmDCORE3_EDMA0_QM_DCCM_BASE 0x47C0000ull +#define DCORE3_EDMA0_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_EDMA0_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_ARC_AUX_BASE 0x47C8000ull +#define DCORE3_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE3_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x47C8E80ull +#define DCORE3_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_EDMA0_QM_BASE 0x47CA000ull +#define DCORE3_EDMA0_QM_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_QM_SECTION 0x9000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x47CA900ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x47CA908ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x47CA910ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x47CA918ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x47CA920ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x47CA928ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x47CA930ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x47CA938ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x47CA940ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x47CA948ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x47CA950ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x47CA958ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x47CA960ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x47CA968ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x47CA970ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x47CA978ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_EDMA0_QM_AXUSER_SECURED_BASE 0x47CAB00ull +#define DCORE3_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_AXUSER_NONSECURED_BASE 0x47CAB80ull +#define DCORE3_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_DBG_HBW_BASE 0x47CAC00ull +#define DCORE3_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_EDMA0_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_EDMA0_QM_DBG_LBW_BASE 0x47CAC80ull +#define DCORE3_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_EDMA0_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_EDMA0_QM_CGM_BASE 0x47CAD80ull +#define DCORE3_EDMA0_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_EDMA0_QM_CGM_SECTION 0x1000 +#define mmDCORE3_EDMA0_QM_SPECIAL_BASE 0x47CAE80ull +#define DCORE3_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_EDMA0_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_EDMA0_CORE_BASE 0x47CB000ull +#define DCORE3_EDMA0_CORE_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_CORE_SECTION 0x8000 +#define mmDCORE3_EDMA0_CORE_CTX_AXUSER_BASE 0x47CB800ull +#define DCORE3_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000 +#define mmDCORE3_EDMA0_CORE_CTX_BASE 0x47CB860ull +#define DCORE3_EDMA0_CORE_CTX_MAX_OFFSET 0x9000 +#define DCORE3_EDMA0_CORE_CTX_SECTION 0x5A00 +#define mmDCORE3_EDMA0_CORE_KDMA_CGM_BASE 0x47CBE00ull +#define DCORE3_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define DCORE3_EDMA0_CORE_KDMA_CGM_SECTION 0x8000 +#define mmDCORE3_EDMA0_CORE_SPECIAL_BASE 0x47CBE80ull +#define DCORE3_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_EDMA0_CORE_SPECIAL_SECTION 0x1800 +#define mmDCORE3_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x47CC000ull +#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x47CC200ull +#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x47CC400ull +#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x47CC600ull +#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x47CC800ull +#define DCORE3_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_EDMA0_MSTR_IF_AXUSER_BASE 0x47CCA80ull +#define DCORE3_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_EDMA0_MSTR_IF_DBG_HBW_BASE 0x47CCB00ull +#define DCORE3_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_EDMA0_MSTR_IF_DBG_LBW_BASE 0x47CCB80ull +#define DCORE3_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_EDMA0_MSTR_IF_CORE_HBW_BASE 0x47CCC00ull +#define DCORE3_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_EDMA0_MSTR_IF_CORE_LBW_BASE 0x47CCD80ull +#define DCORE3_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_EDMA0_MSTR_IF_SPECIAL_BASE 0x47CCE80ull +#define DCORE3_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE3_EDMA1_QM_DCCM_BASE 0x47D0000ull +#define DCORE3_EDMA1_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_EDMA1_QM_DCCM_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_ARC_AUX_BASE 0x47D8000ull +#define DCORE3_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_QM_ARC_AUX_SECTION 0xE800 +#define mmDCORE3_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x47D8E80ull +#define DCORE3_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmDCORE3_EDMA1_QM_BASE 0x47DA000ull +#define DCORE3_EDMA1_QM_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_QM_SECTION 0x9000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x47DA900ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x47DA908ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x47DA910ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x47DA918ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x47DA920ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x47DA928ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x47DA930ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x47DA938ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x47DA940ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x47DA948ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x47DA950ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x47DA958ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x47DA960ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x47DA968ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x47DA970ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x47DA978ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmDCORE3_EDMA1_QM_AXUSER_SECURED_BASE 0x47DAB00ull +#define DCORE3_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_AXUSER_NONSECURED_BASE 0x47DAB80ull +#define DCORE3_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_DBG_HBW_BASE 0x47DAC00ull +#define DCORE3_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_EDMA1_QM_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_EDMA1_QM_DBG_LBW_BASE 0x47DAC80ull +#define DCORE3_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_EDMA1_QM_DBG_LBW_SECTION 0x1000 +#define mmDCORE3_EDMA1_QM_CGM_BASE 0x47DAD80ull +#define DCORE3_EDMA1_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_EDMA1_QM_CGM_SECTION 0x1000 +#define mmDCORE3_EDMA1_QM_SPECIAL_BASE 0x47DAE80ull +#define DCORE3_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_EDMA1_QM_SPECIAL_SECTION 0x1800 +#define mmDCORE3_EDMA1_CORE_BASE 0x47DB000ull +#define DCORE3_EDMA1_CORE_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_CORE_SECTION 0x8000 +#define mmDCORE3_EDMA1_CORE_CTX_AXUSER_BASE 0x47DB800ull +#define DCORE3_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000 +#define mmDCORE3_EDMA1_CORE_CTX_BASE 0x47DB860ull +#define DCORE3_EDMA1_CORE_CTX_MAX_OFFSET 0x9000 +#define DCORE3_EDMA1_CORE_CTX_SECTION 0x5A00 +#define mmDCORE3_EDMA1_CORE_KDMA_CGM_BASE 0x47DBE00ull +#define DCORE3_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define DCORE3_EDMA1_CORE_KDMA_CGM_SECTION 0x8000 +#define mmDCORE3_EDMA1_CORE_SPECIAL_BASE 0x47DBE80ull +#define DCORE3_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_EDMA1_CORE_SPECIAL_SECTION 0x1800 +#define mmDCORE3_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x47DC000ull +#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x47DC200ull +#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x47DC400ull +#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x47DC600ull +#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x47DC800ull +#define DCORE3_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_EDMA1_MSTR_IF_AXUSER_BASE 0x47DCA80ull +#define DCORE3_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_EDMA1_MSTR_IF_DBG_HBW_BASE 0x47DCB00ull +#define DCORE3_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_EDMA1_MSTR_IF_DBG_LBW_BASE 0x47DCB80ull +#define DCORE3_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_EDMA1_MSTR_IF_CORE_HBW_BASE 0x47DCC00ull +#define DCORE3_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_EDMA1_MSTR_IF_CORE_LBW_BASE 0x47DCD80ull +#define DCORE3_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_EDMA1_MSTR_IF_SPECIAL_BASE 0x47DCE80ull +#define DCORE3_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmDCORE3_DEC0_CMD_BASE 0x47E0000ull +#define DCORE3_DEC0_CMD_MAX_OFFSET 0x1100 +#define DCORE3_DEC0_CMD_SECTION 0x1000 +#define mmDCORE3_DEC0_VSI_BASE 0x47E1000ull +#define DCORE3_DEC0_VSI_MAX_OFFSET 0x6FC0 +#define DCORE3_DEC0_VSI_SECTION 0x1000 +#define mmDCORE3_DEC0_L2C_BASE 0x47E2000ull +#define DCORE3_DEC0_L2C_MAX_OFFSET 0x39C0 +#define DCORE3_DEC0_L2C_SECTION 0x1000 +#define mmDCORE3_VDEC0_BRDG_CTRL_BASE 0x47E3000ull +#define DCORE3_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_BRDG_CTRL_SECTION 0x8000 +#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x47E3800ull +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 +#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x47E3900ull +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 +#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x47E3A00ull +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 +#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x47E3B00ull +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 +#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x47E3C00ull +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 +#define mmDCORE3_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x47E3E80ull +#define DCORE3_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_VDEC0_CTRL_BASE 0x47E4000ull +#define DCORE3_VDEC0_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_CTRL_SECTION 0xE800 +#define mmDCORE3_VDEC0_CTRL_SPECIAL_BASE 0x47E4E80ull +#define DCORE3_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_VDEC0_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x47E5000ull +#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x47E5200ull +#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x47E5400ull +#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x47E5600ull +#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x47E5800ull +#define DCORE3_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_VDEC0_MSTR_IF_AXUSER_BASE 0x47E5A80ull +#define DCORE3_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_VDEC0_MSTR_IF_DBG_HBW_BASE 0x47E5B00ull +#define DCORE3_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_VDEC0_MSTR_IF_DBG_LBW_BASE 0x47E5B80ull +#define DCORE3_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_VDEC0_MSTR_IF_CORE_HBW_BASE 0x47E5C00ull +#define DCORE3_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_VDEC0_MSTR_IF_CORE_LBW_BASE 0x47E5D80ull +#define DCORE3_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_VDEC0_MSTR_IF_SPECIAL_BASE 0x47E5E80ull +#define DCORE3_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180 +#define mmDCORE3_DEC1_CMD_BASE 0x47F0000ull +#define DCORE3_DEC1_CMD_MAX_OFFSET 0x1100 +#define DCORE3_DEC1_CMD_SECTION 0x1000 +#define mmDCORE3_DEC1_VSI_BASE 0x47F1000ull +#define DCORE3_DEC1_VSI_MAX_OFFSET 0x6FC0 +#define DCORE3_DEC1_VSI_SECTION 0x1000 +#define mmDCORE3_DEC1_L2C_BASE 0x47F2000ull +#define DCORE3_DEC1_L2C_MAX_OFFSET 0x39C0 +#define DCORE3_DEC1_L2C_SECTION 0x1000 +#define mmDCORE3_VDEC1_BRDG_CTRL_BASE 0x47F3000ull +#define DCORE3_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_BRDG_CTRL_SECTION 0x8000 +#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x47F3800ull +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 +#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x47F3900ull +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 +#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x47F3A00ull +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 +#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x47F3B00ull +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 +#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x47F3C00ull +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 +#define mmDCORE3_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x47F3E80ull +#define DCORE3_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_VDEC1_CTRL_BASE 0x47F4000ull +#define DCORE3_VDEC1_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_CTRL_SECTION 0xE800 +#define mmDCORE3_VDEC1_CTRL_SPECIAL_BASE 0x47F4E80ull +#define DCORE3_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_VDEC1_CTRL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x47F5000ull +#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmDCORE3_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x47F5200ull +#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmDCORE3_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x47F5400ull +#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmDCORE3_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x47F5600ull +#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmDCORE3_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x47F5800ull +#define DCORE3_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmDCORE3_VDEC1_MSTR_IF_AXUSER_BASE 0x47F5A80ull +#define DCORE3_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmDCORE3_VDEC1_MSTR_IF_DBG_HBW_BASE 0x47F5B00ull +#define DCORE3_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmDCORE3_VDEC1_MSTR_IF_DBG_LBW_BASE 0x47F5B80ull +#define DCORE3_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmDCORE3_VDEC1_MSTR_IF_CORE_HBW_BASE 0x47F5C00ull +#define DCORE3_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmDCORE3_VDEC1_MSTR_IF_CORE_LBW_BASE 0x47F5D80ull +#define DCORE3_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmDCORE3_VDEC1_MSTR_IF_SPECIAL_BASE 0x47F5E80ull +#define DCORE3_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180 +#define mmGIC_BASE 0x4800000ull +#define GIC_MAX_OFFSET 0x10000 +#define GIC_SECTION 0x401000 +#define mmPCIE_WRAP_BASE 0x4C01000ull +#define PCIE_WRAP_MAX_OFFSET 0x1000 +#define PCIE_WRAP_SECTION 0xE800 +#define mmPCIE_WRAP_SPECIAL_BASE 0x4C01E80ull +#define PCIE_WRAP_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_WRAP_SPECIAL_SECTION 0x1800 +#define mmPCIE_DBI_BASE 0x4C02000ull +#define PCIE_DBI_MAX_OFFSET 0xC040 +#define PCIE_DBI_SECTION 0x2000 +#define mmPCIE_CORE_BASE 0x4C04000ull +#define PCIE_CORE_MAX_OFFSET 0x1000 +#define PCIE_CORE_SECTION 0xE800 +#define mmPCIE_CORE_SPECIAL_BASE 0x4C04E80ull +#define PCIE_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_CORE_SPECIAL_SECTION 0x2180 +#define mmPCIE_AUX_BASE 0x4C07000ull +#define PCIE_AUX_MAX_OFFSET 0x1000 +#define PCIE_AUX_SECTION 0xE800 +#define mmPCIE_AUX_SPECIAL_BASE 0x4C07E80ull +#define PCIE_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_AUX_SPECIAL_SECTION 0x8180 +#define mmPCIE_PHY_BASE 0x4C10000ull +#define PCIE_PHY_MAX_OFFSET 0x1000 +#define PCIE_PHY_SECTION 0xE800 +#define mmPCIE_PHY_SPECIAL_BASE 0x4C10E80ull +#define PCIE_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_PHY_SPECIAL_SECTION 0x2180 +#define mmPCIE_MSI_BASE 0x4C13000ull +#define PCIE_MSI_MAX_OFFSET 0x8000 +#define PCIE_MSI_SECTION 0x1000 +#define mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_BASE 0x4C14000ull +#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmPCIE_ELBI_RR_MSTR_IF_RR_PRVT_HBW_BASE 0x4C14200ull +#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_BASE 0x4C14400ull +#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmPCIE_ELBI_RR_MSTR_IF_RR_PRVT_LBW_BASE 0x4C14600ull +#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmPCIE_ELBI_RR_MSTR_IF_E2E_CRDT_BASE 0x4C14800ull +#define PCIE_ELBI_RR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PCIE_ELBI_RR_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmPCIE_ELBI_RR_MSTR_IF_AXUSER_BASE 0x4C14A80ull +#define PCIE_ELBI_RR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PCIE_ELBI_RR_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmPCIE_ELBI_RR_MSTR_IF_DBG_HBW_BASE 0x4C14B00ull +#define PCIE_ELBI_RR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PCIE_ELBI_RR_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmPCIE_ELBI_RR_MSTR_IF_DBG_LBW_BASE 0x4C14B80ull +#define PCIE_ELBI_RR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PCIE_ELBI_RR_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmPCIE_ELBI_RR_MSTR_IF_CORE_HBW_BASE 0x4C14C00ull +#define PCIE_ELBI_RR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PCIE_ELBI_RR_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmPCIE_ELBI_RR_MSTR_IF_CORE_LBW_BASE 0x4C14D80ull +#define PCIE_ELBI_RR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PCIE_ELBI_RR_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmPCIE_ELBI_RR_MSTR_IF_SPECIAL_BASE 0x4C14E80ull +#define PCIE_ELBI_RR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_ELBI_RR_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE 0x4C15000ull +#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmPCIE_MSTR_RR_MSTR_IF_RR_PRVT_HBW_BASE 0x4C15200ull +#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_BASE 0x4C15400ull +#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmPCIE_MSTR_RR_MSTR_IF_RR_PRVT_LBW_BASE 0x4C15600ull +#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmPCIE_MSTR_RR_MSTR_IF_E2E_CRDT_BASE 0x4C15800ull +#define PCIE_MSTR_RR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PCIE_MSTR_RR_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmPCIE_MSTR_RR_MSTR_IF_AXUSER_BASE 0x4C15A80ull +#define PCIE_MSTR_RR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PCIE_MSTR_RR_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmPCIE_MSTR_RR_MSTR_IF_DBG_HBW_BASE 0x4C15B00ull +#define PCIE_MSTR_RR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PCIE_MSTR_RR_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmPCIE_MSTR_RR_MSTR_IF_DBG_LBW_BASE 0x4C15B80ull +#define PCIE_MSTR_RR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PCIE_MSTR_RR_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmPCIE_MSTR_RR_MSTR_IF_CORE_HBW_BASE 0x4C15C00ull +#define PCIE_MSTR_RR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PCIE_MSTR_RR_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmPCIE_MSTR_RR_MSTR_IF_CORE_LBW_BASE 0x4C15D80ull +#define PCIE_MSTR_RR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PCIE_MSTR_RR_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmPCIE_MSTR_RR_MSTR_IF_SPECIAL_BASE 0x4C15E80ull +#define PCIE_MSTR_RR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_MSTR_RR_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_BASE 0x4C16000ull +#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmPCIE_LBW_RR_MSTR_IF_RR_PRVT_HBW_BASE 0x4C16200ull +#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_BASE 0x4C16400ull +#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmPCIE_LBW_RR_MSTR_IF_RR_PRVT_LBW_BASE 0x4C16600ull +#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmPCIE_LBW_RR_MSTR_IF_E2E_CRDT_BASE 0x4C16800ull +#define PCIE_LBW_RR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PCIE_LBW_RR_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmPCIE_LBW_RR_MSTR_IF_AXUSER_BASE 0x4C16A80ull +#define PCIE_LBW_RR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PCIE_LBW_RR_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmPCIE_LBW_RR_MSTR_IF_DBG_HBW_BASE 0x4C16B00ull +#define PCIE_LBW_RR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PCIE_LBW_RR_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmPCIE_LBW_RR_MSTR_IF_DBG_LBW_BASE 0x4C16B80ull +#define PCIE_LBW_RR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PCIE_LBW_RR_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmPCIE_LBW_RR_MSTR_IF_CORE_HBW_BASE 0x4C16C00ull +#define PCIE_LBW_RR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PCIE_LBW_RR_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmPCIE_LBW_RR_MSTR_IF_CORE_LBW_BASE 0x4C16D80ull +#define PCIE_LBW_RR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PCIE_LBW_RR_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmPCIE_LBW_RR_MSTR_IF_SPECIAL_BASE 0x4C16E80ull +#define PCIE_LBW_RR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_LBW_RR_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmPCIE_MSIX_BASE 0x4C17000ull +#define PCIE_MSIX_MAX_OFFSET 0x4000 +#define PCIE_MSIX_SECTION 0x29000 +#define mmPSOC_I2C_M0_BASE 0x4C40000ull +#define PSOC_I2C_M0_MAX_OFFSET 0x1000 +#define PSOC_I2C_M0_SECTION 0x1000 +#define mmPSOC_I2C_M1_BASE 0x4C41000ull +#define PSOC_I2C_M1_MAX_OFFSET 0x1000 +#define PSOC_I2C_M1_SECTION 0x1000 +#define mmPSOC_I2C_S_BASE 0x4C42000ull +#define PSOC_I2C_S_MAX_OFFSET 0x1000 +#define PSOC_I2C_S_SECTION 0x1000 +#define mmPSOC_SPI_BASE 0x4C43000ull +#define PSOC_SPI_MAX_OFFSET 0x1000 +#define PSOC_SPI_SECTION 0x1000 +#define mmPSOC_QSPI_BASE 0x4C44000ull +#define PSOC_QSPI_MAX_OFFSET 0x1000 +#define PSOC_QSPI_SECTION 0x1000 +#define mmPSOC_UART_0_BASE 0x4C45000ull +#define PSOC_UART_0_MAX_OFFSET 0x1000 +#define PSOC_UART_0_SECTION 0x1000 +#define mmPSOC_UART_1_BASE 0x4C46000ull +#define PSOC_UART_1_MAX_OFFSET 0x1000 +#define PSOC_UART_1_SECTION 0x1000 +#define mmPSOC_TIMER_BASE 0x4C47000ull +#define PSOC_TIMER_MAX_OFFSET 0x1000 +#define PSOC_TIMER_SECTION 0x1000 +#define mmPSOC_WDOG_BASE 0x4C48000ull +#define PSOC_WDOG_MAX_OFFSET 0x1000 +#define PSOC_WDOG_SECTION 0x1000 +#define mmPSOC_TIMESTAMP_BASE 0x4C49000ull +#define PSOC_TIMESTAMP_MAX_OFFSET 0x1000 +#define PSOC_TIMESTAMP_SECTION 0x1000 +#define mmPSOC_EFUSE_BASE 0x4C4A000ull +#define PSOC_EFUSE_MAX_OFFSET 0x1000 +#define PSOC_EFUSE_SECTION 0xE800 +#define mmPSOC_EFUSE_SPECIAL_BASE 0x4C4AE80ull +#define PSOC_EFUSE_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_EFUSE_SPECIAL_SECTION 0x1800 +#define mmPSOC_GLOBAL_CONF_BASE 0x4C4B000ull +#define PSOC_GLOBAL_CONF_MAX_OFFSET 0x1000 +#define PSOC_GLOBAL_CONF_SECTION 0xE800 +#define mmPSOC_GLOBAL_CONF_SPECIAL_BASE 0x4C4BE80ull +#define PSOC_GLOBAL_CONF_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_GLOBAL_CONF_SPECIAL_SECTION 0x1800 +#define mmPSOC_GPIO0_BASE 0x4C4C000ull +#define PSOC_GPIO0_MAX_OFFSET 0x1000 +#define PSOC_GPIO0_SECTION 0x1000 +#define mmPSOC_GPIO1_BASE 0x4C4D000ull +#define PSOC_GPIO1_MAX_OFFSET 0x1000 +#define PSOC_GPIO1_SECTION 0x1000 +#define mmPSOC_BTL_BASE 0x4C4E000ull +#define PSOC_BTL_MAX_OFFSET 0x1000 +#define PSOC_BTL_SECTION 0xE800 +#define mmPSOC_BTL_SPECIAL_BASE 0x4C4EE80ull +#define PSOC_BTL_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_BTL_SPECIAL_SECTION 0x1800 +#define mmPSOC_CS_TRACE_BASE 0x4C4F000ull +#define PSOC_CS_TRACE_MAX_OFFSET 0x1000 +#define PSOC_CS_TRACE_SECTION 0xE800 +#define mmPSOC_CS_TRACE_SPECIAL_BASE 0x4C4FE80ull +#define PSOC_CS_TRACE_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_CS_TRACE_SPECIAL_SECTION 0x1800 +#define mmPSOC_GPIO2_BASE 0x4C50000ull +#define PSOC_GPIO2_MAX_OFFSET 0x1000 +#define PSOC_GPIO2_SECTION 0x1000 +#define mmPSOC_GPIO3_BASE 0x4C51000ull +#define PSOC_GPIO3_MAX_OFFSET 0x1000 +#define PSOC_GPIO3_SECTION 0x2000 +#define mmPSOC_DFT_EFUSE_BASE 0x4C53000ull +#define PSOC_DFT_EFUSE_MAX_OFFSET 0x1000 +#define PSOC_DFT_EFUSE_SECTION 0xE800 +#define mmPSOC_DFT_EFUSE_SPECIAL_BASE 0x4C53E80ull +#define PSOC_DFT_EFUSE_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_DFT_EFUSE_SPECIAL_SECTION 0x1800 +#define mmPSOC_RPM_0_BASE 0x4C54000ull +#define PSOC_RPM_0_MAX_OFFSET 0x1000 +#define PSOC_RPM_0_SECTION 0xE800 +#define mmPSOC_RPM_0_SPECIAL_BASE 0x4C54E80ull +#define PSOC_RPM_0_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_RPM_0_SPECIAL_SECTION 0x1800 +#define mmPSOC_RPM_1_BASE 0x4C55000ull +#define PSOC_RPM_1_MAX_OFFSET 0x1000 +#define PSOC_RPM_1_SECTION 0xE800 +#define mmPSOC_RPM_1_SPECIAL_BASE 0x4C55E80ull +#define PSOC_RPM_1_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_RPM_1_SPECIAL_SECTION 0x1800 +#define mmPSOC_GPIO4_BASE 0x4C56000ull +#define PSOC_GPIO4_MAX_OFFSET 0x1000 +#define PSOC_GPIO4_SECTION 0x1000 +#define mmPSOC_GPIO5_BASE 0x4C57000ull +#define PSOC_GPIO5_MAX_OFFSET 0x1000 +#define PSOC_GPIO5_SECTION 0x1000 +#define mmPSOC_PID_BASE 0x4C58000ull +#define PSOC_PID_MAX_OFFSET 0x1000 +#define PSOC_PID_SECTION 0xE800 +#define mmPSOC_PID_SPECIAL_BASE 0x4C58E80ull +#define PSOC_PID_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_PID_SPECIAL_SECTION 0x1800 +#define mmPSOC_ARC0_CFG_BASE 0x4C59000ull +#define PSOC_ARC0_CFG_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CFG_SECTION 0xE800 +#define mmPSOC_ARC0_CFG_SPECIAL_BASE 0x4C59E80ull +#define PSOC_ARC0_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_ARC0_CFG_SPECIAL_SECTION 0x1800 +#define mmPSOC_ARC0_MSTR_IF_RR_SHRD_HBW_BASE 0x4C5A000ull +#define PSOC_ARC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PSOC_ARC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmPSOC_ARC0_MSTR_IF_RR_PRVT_HBW_BASE 0x4C5A200ull +#define PSOC_ARC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PSOC_ARC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmPSOC_ARC0_MSTR_IF_RR_SHRD_LBW_BASE 0x4C5A400ull +#define PSOC_ARC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PSOC_ARC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmPSOC_ARC0_MSTR_IF_RR_PRVT_LBW_BASE 0x4C5A600ull +#define PSOC_ARC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PSOC_ARC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmPSOC_ARC0_MSTR_IF_E2E_CRDT_BASE 0x4C5A800ull +#define PSOC_ARC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PSOC_ARC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmPSOC_ARC0_MSTR_IF_AXUSER_BASE 0x4C5AA80ull +#define PSOC_ARC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PSOC_ARC0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmPSOC_ARC0_MSTR_IF_DBG_HBW_BASE 0x4C5AB00ull +#define PSOC_ARC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PSOC_ARC0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmPSOC_ARC0_MSTR_IF_DBG_LBW_BASE 0x4C5AB80ull +#define PSOC_ARC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PSOC_ARC0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmPSOC_ARC0_MSTR_IF_CORE_HBW_BASE 0x4C5AC00ull +#define PSOC_ARC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PSOC_ARC0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmPSOC_ARC0_MSTR_IF_CORE_LBW_BASE 0x4C5AD80ull +#define PSOC_ARC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PSOC_ARC0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmPSOC_ARC0_MSTR_IF_SPECIAL_BASE 0x4C5AE80ull +#define PSOC_ARC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_ARC0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmPSOC_ARC0_AUX_BASE 0x4C5B000ull +#define PSOC_ARC0_AUX_MAX_OFFSET 0x1000 +#define PSOC_ARC0_AUX_SECTION 0xE800 +#define mmPSOC_ARC0_AUX_SPECIAL_BASE 0x4C5BE80ull +#define PSOC_ARC0_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_ARC0_AUX_SPECIAL_SECTION 0x1800 +#define mmPSOC_ARC1_CFG_BASE 0x4C5C000ull +#define PSOC_ARC1_CFG_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CFG_SECTION 0xE800 +#define mmPSOC_ARC1_CFG_SPECIAL_BASE 0x4C5CE80ull +#define PSOC_ARC1_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_ARC1_CFG_SPECIAL_SECTION 0x1800 +#define mmPSOC_ARC1_MSTR_IF_RR_SHRD_HBW_BASE 0x4C5D000ull +#define PSOC_ARC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PSOC_ARC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmPSOC_ARC1_MSTR_IF_RR_PRVT_HBW_BASE 0x4C5D200ull +#define PSOC_ARC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PSOC_ARC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmPSOC_ARC1_MSTR_IF_RR_SHRD_LBW_BASE 0x4C5D400ull +#define PSOC_ARC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PSOC_ARC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmPSOC_ARC1_MSTR_IF_RR_PRVT_LBW_BASE 0x4C5D600ull +#define PSOC_ARC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PSOC_ARC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmPSOC_ARC1_MSTR_IF_E2E_CRDT_BASE 0x4C5D800ull +#define PSOC_ARC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PSOC_ARC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmPSOC_ARC1_MSTR_IF_AXUSER_BASE 0x4C5DA80ull +#define PSOC_ARC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PSOC_ARC1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmPSOC_ARC1_MSTR_IF_DBG_HBW_BASE 0x4C5DB00ull +#define PSOC_ARC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PSOC_ARC1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmPSOC_ARC1_MSTR_IF_DBG_LBW_BASE 0x4C5DB80ull +#define PSOC_ARC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PSOC_ARC1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmPSOC_ARC1_MSTR_IF_CORE_HBW_BASE 0x4C5DC00ull +#define PSOC_ARC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PSOC_ARC1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmPSOC_ARC1_MSTR_IF_CORE_LBW_BASE 0x4C5DD80ull +#define PSOC_ARC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PSOC_ARC1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmPSOC_ARC1_MSTR_IF_SPECIAL_BASE 0x4C5DE80ull +#define PSOC_ARC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_ARC1_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmPSOC_ARC1_AUX_BASE 0x4C5E000ull +#define PSOC_ARC1_AUX_MAX_OFFSET 0x1000 +#define PSOC_ARC1_AUX_SECTION 0xE800 +#define mmPSOC_ARC1_AUX_SPECIAL_BASE 0x4C5EE80ull +#define PSOC_ARC1_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_ARC1_AUX_SPECIAL_SECTION 0x1180 +#define mmPSOC_SECURITY_BASE 0x4C60000ull +#define PSOC_SECURITY_MAX_OFFSET 0x1000 +#define PSOC_SECURITY_SECTION 0xE800 +#define mmPSOC_SECURITY_SPECIAL_BASE 0x4C60E80ull +#define PSOC_SECURITY_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_SECURITY_SPECIAL_SECTION 0x1800 +#define mmJT_MSTR_IF_RR_SHRD_HBW_BASE 0x4C61000ull +#define JT_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define JT_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmJT_MSTR_IF_RR_PRVT_HBW_BASE 0x4C61200ull +#define JT_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define JT_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmJT_MSTR_IF_RR_SHRD_LBW_BASE 0x4C61400ull +#define JT_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define JT_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmJT_MSTR_IF_RR_PRVT_LBW_BASE 0x4C61600ull +#define JT_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define JT_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmJT_MSTR_IF_E2E_CRDT_BASE 0x4C61800ull +#define JT_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define JT_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmJT_MSTR_IF_AXUSER_BASE 0x4C61A80ull +#define JT_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define JT_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmJT_MSTR_IF_DBG_HBW_BASE 0x4C61B00ull +#define JT_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define JT_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmJT_MSTR_IF_DBG_LBW_BASE 0x4C61B80ull +#define JT_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define JT_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmJT_MSTR_IF_CORE_HBW_BASE 0x4C61C00ull +#define JT_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define JT_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmJT_MSTR_IF_CORE_LBW_BASE 0x4C61D80ull +#define JT_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define JT_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmJT_MSTR_IF_SPECIAL_BASE 0x4C61E80ull +#define JT_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define JT_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSMI_MSTR_IF_RR_SHRD_HBW_BASE 0x4C62000ull +#define SMI_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SMI_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSMI_MSTR_IF_RR_PRVT_HBW_BASE 0x4C62200ull +#define SMI_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SMI_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSMI_MSTR_IF_RR_SHRD_LBW_BASE 0x4C62400ull +#define SMI_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SMI_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSMI_MSTR_IF_RR_PRVT_LBW_BASE 0x4C62600ull +#define SMI_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SMI_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSMI_MSTR_IF_E2E_CRDT_BASE 0x4C62800ull +#define SMI_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SMI_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSMI_MSTR_IF_AXUSER_BASE 0x4C62A80ull +#define SMI_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SMI_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSMI_MSTR_IF_DBG_HBW_BASE 0x4C62B00ull +#define SMI_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SMI_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSMI_MSTR_IF_DBG_LBW_BASE 0x4C62B80ull +#define SMI_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SMI_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSMI_MSTR_IF_CORE_HBW_BASE 0x4C62C00ull +#define SMI_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SMI_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSMI_MSTR_IF_CORE_LBW_BASE 0x4C62D80ull +#define SMI_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SMI_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSMI_MSTR_IF_SPECIAL_BASE 0x4C62E80ull +#define SMI_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SMI_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmI2C_S_MSTR_IF_RR_SHRD_HBW_BASE 0x4C63000ull +#define I2C_S_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define I2C_S_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmI2C_S_MSTR_IF_RR_PRVT_HBW_BASE 0x4C63200ull +#define I2C_S_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define I2C_S_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmI2C_S_MSTR_IF_RR_SHRD_LBW_BASE 0x4C63400ull +#define I2C_S_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define I2C_S_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmI2C_S_MSTR_IF_RR_PRVT_LBW_BASE 0x4C63600ull +#define I2C_S_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define I2C_S_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmI2C_S_MSTR_IF_E2E_CRDT_BASE 0x4C63800ull +#define I2C_S_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define I2C_S_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmI2C_S_MSTR_IF_AXUSER_BASE 0x4C63A80ull +#define I2C_S_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define I2C_S_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmI2C_S_MSTR_IF_DBG_HBW_BASE 0x4C63B00ull +#define I2C_S_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define I2C_S_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmI2C_S_MSTR_IF_DBG_LBW_BASE 0x4C63B80ull +#define I2C_S_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define I2C_S_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmI2C_S_MSTR_IF_CORE_HBW_BASE 0x4C63C00ull +#define I2C_S_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define I2C_S_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmI2C_S_MSTR_IF_CORE_LBW_BASE 0x4C63D80ull +#define I2C_S_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define I2C_S_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmI2C_S_MSTR_IF_SPECIAL_BASE 0x4C63E80ull +#define I2C_S_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define I2C_S_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmPSOC_SVID0_BASE 0x4C64000ull +#define PSOC_SVID0_MAX_OFFSET 0x1000 +#define PSOC_SVID0_SECTION 0xE800 +#define mmPSOC_SVID0_SPECIAL_BASE 0x4C64E80ull +#define PSOC_SVID0_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_SVID0_SPECIAL_SECTION 0x1800 +#define mmPSOC_SVID1_BASE 0x4C65000ull +#define PSOC_SVID1_MAX_OFFSET 0x1000 +#define PSOC_SVID1_SECTION 0xE800 +#define mmPSOC_SVID1_SPECIAL_BASE 0x4C65E80ull +#define PSOC_SVID1_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_SVID1_SPECIAL_SECTION 0x1800 +#define mmPSOC_SVID2_BASE 0x4C66000ull +#define PSOC_SVID2_MAX_OFFSET 0x1000 +#define PSOC_SVID2_SECTION 0xE800 +#define mmPSOC_SVID2_SPECIAL_BASE 0x4C66E80ull +#define PSOC_SVID2_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_SVID2_SPECIAL_SECTION 0x5180 +#define mmPSOC_MME_PLL_CTRL_BASE 0x4C6C000ull +#define PSOC_MME_PLL_CTRL_MAX_OFFSET 0x3540 +#define PSOC_MME_PLL_CTRL_SECTION 0x3600 +#define mmPSOC_MME_PLL_ASIF_SLV_BASE 0x4C6C360ull +#define PSOC_MME_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define PSOC_MME_PLL_ASIF_SLV_SECTION 0xA000 +#define mmPSOC_MME_PLL_DIV_0_RLX_BASE 0x4C6C400ull +#define PSOC_MME_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define PSOC_MME_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmPSOC_MME_PLL_DIV_1_RLX_BASE 0x4C6C800ull +#define PSOC_MME_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define PSOC_MME_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmPSOC_MME_PLL_DIV_2_RLX_BASE 0x4C6CA00ull +#define PSOC_MME_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define PSOC_MME_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmPSOC_MME_PLL_DIV_3_RLX_BASE 0x4C6CC00ull +#define PSOC_MME_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define PSOC_MME_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmPSOC_MME_PLL_SPECIAL_BASE 0x4C6CE80ull +#define PSOC_MME_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_MME_PLL_SPECIAL_SECTION 0x1800 +#define mmPSOC_CPU_PLL_CTRL_BASE 0x4C6D000ull +#define PSOC_CPU_PLL_CTRL_MAX_OFFSET 0x3540 +#define PSOC_CPU_PLL_CTRL_SECTION 0x3600 +#define mmPSOC_CPU_PLL_ASIF_SLV_BASE 0x4C6D360ull +#define PSOC_CPU_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define PSOC_CPU_PLL_ASIF_SLV_SECTION 0xA000 +#define mmPSOC_CPU_PLL_DIV_0_RLX_BASE 0x4C6D400ull +#define PSOC_CPU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define PSOC_CPU_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmPSOC_CPU_PLL_DIV_1_RLX_BASE 0x4C6D800ull +#define PSOC_CPU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define PSOC_CPU_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmPSOC_CPU_PLL_DIV_2_RLX_BASE 0x4C6DA00ull +#define PSOC_CPU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define PSOC_CPU_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmPSOC_CPU_PLL_DIV_3_RLX_BASE 0x4C6DC00ull +#define PSOC_CPU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define PSOC_CPU_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmPSOC_CPU_PLL_SPECIAL_BASE 0x4C6DE80ull +#define PSOC_CPU_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_CPU_PLL_SPECIAL_SECTION 0x1800 +#define mmPSOC_VID_PLL_CTRL_BASE 0x4C6E000ull +#define PSOC_VID_PLL_CTRL_MAX_OFFSET 0x3540 +#define PSOC_VID_PLL_CTRL_SECTION 0x3600 +#define mmPSOC_VID_PLL_ASIF_SLV_BASE 0x4C6E360ull +#define PSOC_VID_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define PSOC_VID_PLL_ASIF_SLV_SECTION 0xA000 +#define mmPSOC_VID_PLL_DIV_0_RLX_BASE 0x4C6E400ull +#define PSOC_VID_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define PSOC_VID_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmPSOC_VID_PLL_DIV_1_RLX_BASE 0x4C6E800ull +#define PSOC_VID_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define PSOC_VID_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmPSOC_VID_PLL_DIV_2_RLX_BASE 0x4C6EA00ull +#define PSOC_VID_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define PSOC_VID_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmPSOC_VID_PLL_DIV_3_RLX_BASE 0x4C6EC00ull +#define PSOC_VID_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define PSOC_VID_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmPSOC_VID_PLL_SPECIAL_BASE 0x4C6EE80ull +#define PSOC_VID_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_VID_PLL_SPECIAL_SECTION 0x5180 +#define mmPSOC_RESET_CONF_BASE 0x4C74000ull +#define PSOC_RESET_CONF_MAX_OFFSET 0x1000 +#define PSOC_RESET_CONF_SECTION 0xE800 +#define mmPSOC_RESET_CONF_SPECIAL_BASE 0x4C74E80ull +#define PSOC_RESET_CONF_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_RESET_CONF_SPECIAL_SECTION 0x1800 +#define mmPSOC_DFT_APB_BASE 0x4C75000ull +#define PSOC_DFT_APB_MAX_OFFSET 0x8000 +#define PSOC_DFT_APB_SECTION 0x1000 +#define mmPSOC_AVS0_BASE 0x4C76000ull +#define PSOC_AVS0_MAX_OFFSET 0x1000 +#define PSOC_AVS0_SECTION 0xE800 +#define mmPSOC_AVS0_SPECIAL_BASE 0x4C76E80ull +#define PSOC_AVS0_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_AVS0_SPECIAL_SECTION 0x1800 +#define mmPSOC_AVS1_BASE 0x4C77000ull +#define PSOC_AVS1_MAX_OFFSET 0x1000 +#define PSOC_AVS1_SECTION 0xE800 +#define mmPSOC_AVS1_SPECIAL_BASE 0x4C77E80ull +#define PSOC_AVS1_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_AVS1_SPECIAL_SECTION 0x1800 +#define mmPSOC_AVS2_BASE 0x4C78000ull +#define PSOC_AVS2_MAX_OFFSET 0x1000 +#define PSOC_AVS2_SECTION 0xE800 +#define mmPSOC_AVS2_SPECIAL_BASE 0x4C78E80ull +#define PSOC_AVS2_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_AVS2_SPECIAL_SECTION 0x1800 +#define mmPSOC_PWM0_BASE 0x4C79000ull +#define PSOC_PWM0_MAX_OFFSET 0x1000 +#define PSOC_PWM0_SECTION 0xE800 +#define mmPSOC_PWM0_SPECIAL_BASE 0x4C79E80ull +#define PSOC_PWM0_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_PWM0_SPECIAL_SECTION 0x1800 +#define mmPSOC_PWM1_BASE 0x4C7A000ull +#define PSOC_PWM1_MAX_OFFSET 0x1000 +#define PSOC_PWM1_SECTION 0xE800 +#define mmPSOC_PWM1_SPECIAL_BASE 0x4C7AE80ull +#define PSOC_PWM1_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_PWM1_SPECIAL_SECTION 0x1800 +#define mmSVID0_AC_BASE 0x4C7B000ull +#define SVID0_AC_MAX_OFFSET 0x1000 +#define SVID0_AC_SECTION 0xE800 +#define mmSVID0_AC_SPECIAL_BASE 0x4C7BE80ull +#define SVID0_AC_SPECIAL_MAX_OFFSET 0x1800 +#define SVID0_AC_SPECIAL_SECTION 0x1800 +#define mmSVID1_AC_BASE 0x4C7C000ull +#define SVID1_AC_MAX_OFFSET 0x1000 +#define SVID1_AC_SECTION 0xE800 +#define mmSVID1_AC_SPECIAL_BASE 0x4C7CE80ull +#define SVID1_AC_SPECIAL_MAX_OFFSET 0x1800 +#define SVID1_AC_SPECIAL_SECTION 0x1800 +#define mmSVID2_AC_BASE 0x4C7D000ull +#define SVID2_AC_MAX_OFFSET 0x1000 +#define SVID2_AC_SECTION 0xE800 +#define mmSVID2_AC_SPECIAL_BASE 0x4C7DE80ull +#define SVID2_AC_SPECIAL_MAX_OFFSET 0x1800 +#define SVID2_AC_SPECIAL_SECTION 0x1180 +#define mmPSOC_MSTR_IF_RR_SHRD_HBW_BASE 0x4C7F000ull +#define PSOC_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PSOC_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmPSOC_MSTR_IF_RR_PRVT_HBW_BASE 0x4C7F200ull +#define PSOC_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PSOC_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmPSOC_MSTR_IF_RR_SHRD_LBW_BASE 0x4C7F400ull +#define PSOC_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PSOC_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmPSOC_MSTR_IF_RR_PRVT_LBW_BASE 0x4C7F600ull +#define PSOC_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PSOC_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmPSOC_MSTR_IF_E2E_CRDT_BASE 0x4C7F800ull +#define PSOC_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PSOC_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmPSOC_MSTR_IF_AXUSER_BASE 0x4C7FA80ull +#define PSOC_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PSOC_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmPSOC_MSTR_IF_DBG_HBW_BASE 0x4C7FB00ull +#define PSOC_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PSOC_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmPSOC_MSTR_IF_DBG_LBW_BASE 0x4C7FB80ull +#define PSOC_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PSOC_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmPSOC_MSTR_IF_CORE_HBW_BASE 0x4C7FC00ull +#define PSOC_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PSOC_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmPSOC_MSTR_IF_CORE_LBW_BASE 0x4C7FD80ull +#define PSOC_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PSOC_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmPSOC_MSTR_IF_SPECIAL_BASE 0x4C7FE80ull +#define PSOC_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmPDMA0_QM_ARC_DCCM_BASE 0x4C80000ull +#define PDMA0_QM_ARC_DCCM_MAX_OFFSET 0x4000 +#define PDMA0_QM_ARC_DCCM_SECTION 0x8000 +#define mmPDMA0_QM_ARC_AUX_BASE 0x4C88000ull +#define PDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define PDMA0_QM_ARC_AUX_SECTION 0xE800 +#define mmPDMA0_QM_ARC_AUX_SPECIAL_BASE 0x4C88E80ull +#define PDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmPDMA0_QM_BASE 0x4C8A000ull +#define PDMA0_QM_MAX_OFFSET 0x1000 +#define PDMA0_QM_SECTION 0x9000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4C8A900ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4C8A908ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4C8A910ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4C8A918ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4C8A920ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4C8A928ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4C8A930ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4C8A938ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4C8A940ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4C8A948ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4C8A950ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4C8A958ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4C8A960ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4C8A968ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4C8A970ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4C8A978ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmPDMA0_QM_AXUSER_SECURED_BASE 0x4C8AB00ull +#define PDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define PDMA0_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmPDMA0_QM_AXUSER_NONSECURED_BASE 0x4C8AB80ull +#define PDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define PDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmPDMA0_QM_DBG_HBW_BASE 0x4C8AC00ull +#define PDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define PDMA0_QM_DBG_HBW_SECTION 0x8000 +#define mmPDMA0_QM_DBG_LBW_BASE 0x4C8AC80ull +#define PDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define PDMA0_QM_DBG_LBW_SECTION 0x1000 +#define mmPDMA0_QM_CGM_BASE 0x4C8AD80ull +#define PDMA0_QM_CGM_MAX_OFFSET 0xC000 +#define PDMA0_QM_CGM_SECTION 0x1000 +#define mmPDMA0_QM_SPECIAL_BASE 0x4C8AE80ull +#define PDMA0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define PDMA0_QM_SPECIAL_SECTION 0x1800 +#define mmPDMA0_CORE_BASE 0x4C8B000ull +#define PDMA0_CORE_MAX_OFFSET 0x1000 +#define PDMA0_CORE_SECTION 0x8000 +#define mmPDMA0_CORE_CTX_AXUSER_BASE 0x4C8B800ull +#define PDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define PDMA0_CORE_CTX_AXUSER_SECTION 0x6000 +#define mmPDMA0_CORE_CTX_BASE 0x4C8B860ull +#define PDMA0_CORE_CTX_MAX_OFFSET 0x9000 +#define PDMA0_CORE_CTX_SECTION 0x5A00 +#define mmPDMA0_CORE_KDMA_CGM_BASE 0x4C8BE00ull +#define PDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define PDMA0_CORE_KDMA_CGM_SECTION 0x8000 +#define mmPDMA0_CORE_SPECIAL_BASE 0x4C8BE80ull +#define PDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PDMA0_CORE_SPECIAL_SECTION 0x1800 +#define mmPDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x4C8C000ull +#define PDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmPDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x4C8C200ull +#define PDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmPDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x4C8C400ull +#define PDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmPDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x4C8C600ull +#define PDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmPDMA0_MSTR_IF_E2E_CRDT_BASE 0x4C8C800ull +#define PDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmPDMA0_MSTR_IF_AXUSER_BASE 0x4C8CA80ull +#define PDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PDMA0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmPDMA0_MSTR_IF_DBG_HBW_BASE 0x4C8CB00ull +#define PDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmPDMA0_MSTR_IF_DBG_LBW_BASE 0x4C8CB80ull +#define PDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmPDMA0_MSTR_IF_CORE_HBW_BASE 0x4C8CC00ull +#define PDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmPDMA0_MSTR_IF_CORE_LBW_BASE 0x4C8CD80ull +#define PDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmPDMA0_MSTR_IF_SPECIAL_BASE 0x4C8CE80ull +#define PDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PDMA0_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmPDMA1_QM_ARC_DCCM_BASE 0x4C90000ull +#define PDMA1_QM_ARC_DCCM_MAX_OFFSET 0x4000 +#define PDMA1_QM_ARC_DCCM_SECTION 0x8000 +#define mmPDMA1_QM_ARC_AUX_BASE 0x4C98000ull +#define PDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define PDMA1_QM_ARC_AUX_SECTION 0xE800 +#define mmPDMA1_QM_ARC_AUX_SPECIAL_BASE 0x4C98E80ull +#define PDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmPDMA1_QM_BASE 0x4C9A000ull +#define PDMA1_QM_MAX_OFFSET 0x1000 +#define PDMA1_QM_SECTION 0x9000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4C9A900ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4C9A908ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4C9A910ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4C9A918ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4C9A920ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4C9A928ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4C9A930ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4C9A938ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4C9A940ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4C9A948ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4C9A950ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4C9A958ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4C9A960ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4C9A968ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4C9A970ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4C9A978ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmPDMA1_QM_AXUSER_SECURED_BASE 0x4C9AB00ull +#define PDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define PDMA1_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmPDMA1_QM_AXUSER_NONSECURED_BASE 0x4C9AB80ull +#define PDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define PDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmPDMA1_QM_DBG_HBW_BASE 0x4C9AC00ull +#define PDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define PDMA1_QM_DBG_HBW_SECTION 0x8000 +#define mmPDMA1_QM_DBG_LBW_BASE 0x4C9AC80ull +#define PDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define PDMA1_QM_DBG_LBW_SECTION 0x1000 +#define mmPDMA1_QM_CGM_BASE 0x4C9AD80ull +#define PDMA1_QM_CGM_MAX_OFFSET 0xC000 +#define PDMA1_QM_CGM_SECTION 0x1000 +#define mmPDMA1_QM_SPECIAL_BASE 0x4C9AE80ull +#define PDMA1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define PDMA1_QM_SPECIAL_SECTION 0x1800 +#define mmPDMA1_CORE_BASE 0x4C9B000ull +#define PDMA1_CORE_MAX_OFFSET 0x1000 +#define PDMA1_CORE_SECTION 0x8000 +#define mmPDMA1_CORE_CTX_AXUSER_BASE 0x4C9B800ull +#define PDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define PDMA1_CORE_CTX_AXUSER_SECTION 0x6000 +#define mmPDMA1_CORE_CTX_BASE 0x4C9B860ull +#define PDMA1_CORE_CTX_MAX_OFFSET 0x9000 +#define PDMA1_CORE_CTX_SECTION 0x5A00 +#define mmPDMA1_CORE_KDMA_CGM_BASE 0x4C9BE00ull +#define PDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define PDMA1_CORE_KDMA_CGM_SECTION 0x8000 +#define mmPDMA1_CORE_SPECIAL_BASE 0x4C9BE80ull +#define PDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PDMA1_CORE_SPECIAL_SECTION 0x1800 +#define mmPDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x4C9C000ull +#define PDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmPDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x4C9C200ull +#define PDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmPDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x4C9C400ull +#define PDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmPDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x4C9C600ull +#define PDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmPDMA1_MSTR_IF_E2E_CRDT_BASE 0x4C9C800ull +#define PDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmPDMA1_MSTR_IF_AXUSER_BASE 0x4C9CA80ull +#define PDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PDMA1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmPDMA1_MSTR_IF_DBG_HBW_BASE 0x4C9CB00ull +#define PDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmPDMA1_MSTR_IF_DBG_LBW_BASE 0x4C9CB80ull +#define PDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmPDMA1_MSTR_IF_CORE_HBW_BASE 0x4C9CC00ull +#define PDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmPDMA1_MSTR_IF_CORE_LBW_BASE 0x4C9CD80ull +#define PDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmPDMA1_MSTR_IF_SPECIAL_BASE 0x4C9CE80ull +#define PDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PDMA1_MSTR_IF_SPECIAL_SECTION 0x23180 +#define mmCPU_CA53_CFG_BASE 0x4CC0000ull +#define CPU_CA53_CFG_MAX_OFFSET 0x1000 +#define CPU_CA53_CFG_SECTION 0xE800 +#define mmCPU_CA53_CFG_SPECIAL_BASE 0x4CC0E80ull +#define CPU_CA53_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define CPU_CA53_CFG_SPECIAL_SECTION 0x1800 +#define mmCPU_IF_BASE 0x4CC1000ull +#define CPU_IF_MAX_OFFSET 0x1000 +#define CPU_IF_SECTION 0xE800 +#define mmCPU_IF_SPECIAL_BASE 0x4CC1E80ull +#define CPU_IF_SPECIAL_MAX_OFFSET 0x1800 +#define CPU_IF_SPECIAL_SECTION 0x1800 +#define mmCPU_TIMESTAMP_BASE 0x4CC2000ull +#define CPU_TIMESTAMP_MAX_OFFSET 0x1000 +#define CPU_TIMESTAMP_SECTION 0x1000 +#define mmCPU_MSTR_IF_RR_SHRD_HBW_BASE 0x4CC3000ull +#define CPU_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define CPU_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmCPU_MSTR_IF_RR_PRVT_HBW_BASE 0x4CC3200ull +#define CPU_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define CPU_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmCPU_MSTR_IF_RR_SHRD_LBW_BASE 0x4CC3400ull +#define CPU_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define CPU_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmCPU_MSTR_IF_RR_PRVT_LBW_BASE 0x4CC3600ull +#define CPU_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define CPU_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmCPU_MSTR_IF_E2E_CRDT_BASE 0x4CC3800ull +#define CPU_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define CPU_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmCPU_MSTR_IF_AXUSER_BASE 0x4CC3A80ull +#define CPU_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define CPU_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmCPU_MSTR_IF_DBG_HBW_BASE 0x4CC3B00ull +#define CPU_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define CPU_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmCPU_MSTR_IF_DBG_LBW_BASE 0x4CC3B80ull +#define CPU_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define CPU_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmCPU_MSTR_IF_CORE_HBW_BASE 0x4CC3C00ull +#define CPU_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define CPU_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmCPU_MSTR_IF_CORE_LBW_BASE 0x4CC3D80ull +#define CPU_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define CPU_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmCPU_MSTR_IF_SPECIAL_BASE 0x4CC3E80ull +#define CPU_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define CPU_MSTR_IF_SPECIAL_SECTION 0x3C180 +#define mmPMMU_HBW_MMU_BASE 0x4D00000ull +#define PMMU_HBW_MMU_MAX_OFFSET 0x1000 +#define PMMU_HBW_MMU_SECTION 0xE800 +#define mmPMMU_HBW_MMU_SPECIAL_BASE 0x4D00E80ull +#define PMMU_HBW_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define PMMU_HBW_MMU_SPECIAL_SECTION 0x1800 +#define mmPMMU_HBW_STLB_BASE 0x4D01000ull +#define PMMU_HBW_STLB_MAX_OFFSET 0x1000 +#define PMMU_HBW_STLB_SECTION 0xE800 +#define mmPMMU_HBW_STLB_SPECIAL_BASE 0x4D01E80ull +#define PMMU_HBW_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define PMMU_HBW_STLB_SPECIAL_SECTION 0x1800 +#define mmPMMU_HBW_MSTR_IF_RR_SHRD_HBW_BASE 0x4D02000ull +#define PMMU_HBW_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PMMU_HBW_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmPMMU_HBW_MSTR_IF_RR_PRVT_HBW_BASE 0x4D02200ull +#define PMMU_HBW_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PMMU_HBW_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmPMMU_HBW_MSTR_IF_RR_SHRD_LBW_BASE 0x4D02400ull +#define PMMU_HBW_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PMMU_HBW_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmPMMU_HBW_MSTR_IF_RR_PRVT_LBW_BASE 0x4D02600ull +#define PMMU_HBW_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PMMU_HBW_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmPMMU_HBW_MSTR_IF_E2E_CRDT_BASE 0x4D02800ull +#define PMMU_HBW_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PMMU_HBW_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmPMMU_HBW_MSTR_IF_AXUSER_BASE 0x4D02A80ull +#define PMMU_HBW_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PMMU_HBW_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmPMMU_HBW_MSTR_IF_DBG_HBW_BASE 0x4D02B00ull +#define PMMU_HBW_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PMMU_HBW_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmPMMU_HBW_MSTR_IF_DBG_LBW_BASE 0x4D02B80ull +#define PMMU_HBW_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PMMU_HBW_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmPMMU_HBW_MSTR_IF_CORE_HBW_BASE 0x4D02C00ull +#define PMMU_HBW_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PMMU_HBW_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmPMMU_HBW_MSTR_IF_CORE_LBW_BASE 0x4D02D80ull +#define PMMU_HBW_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PMMU_HBW_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmPMMU_HBW_MSTR_IF_SPECIAL_BASE 0x4D02E80ull +#define PMMU_HBW_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PMMU_HBW_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmPMMU_PIF_BASE 0x4D03000ull +#define PMMU_PIF_MAX_OFFSET 0x1000 +#define PMMU_PIF_SECTION 0xE800 +#define mmPMMU_PIF_SPECIAL_BASE 0x4D03E80ull +#define PMMU_PIF_SPECIAL_MAX_OFFSET 0x1800 +#define PMMU_PIF_SPECIAL_SECTION 0x1800 +#define mmPMMU_MME_PLL_CTRL_BASE 0x4D04000ull +#define PMMU_MME_PLL_CTRL_MAX_OFFSET 0x3540 +#define PMMU_MME_PLL_CTRL_SECTION 0x3600 +#define mmPMMU_MME_PLL_ASIF_SLV_BASE 0x4D04360ull +#define PMMU_MME_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define PMMU_MME_PLL_ASIF_SLV_SECTION 0xA000 +#define mmPMMU_MME_PLL_DIV_0_RLX_BASE 0x4D04400ull +#define PMMU_MME_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define PMMU_MME_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmPMMU_MME_PLL_DIV_1_RLX_BASE 0x4D04800ull +#define PMMU_MME_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define PMMU_MME_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmPMMU_MME_PLL_DIV_2_RLX_BASE 0x4D04A00ull +#define PMMU_MME_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define PMMU_MME_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmPMMU_MME_PLL_DIV_3_RLX_BASE 0x4D04C00ull +#define PMMU_MME_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define PMMU_MME_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmPMMU_MME_PLL_SPECIAL_BASE 0x4D04E80ull +#define PMMU_MME_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define PMMU_MME_PLL_SPECIAL_SECTION 0x1800 +#define mmPMMU_VID_PLL_CTRL_BASE 0x4D05000ull +#define PMMU_VID_PLL_CTRL_MAX_OFFSET 0x3540 +#define PMMU_VID_PLL_CTRL_SECTION 0x3600 +#define mmPMMU_VID_PLL_ASIF_SLV_BASE 0x4D05360ull +#define PMMU_VID_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define PMMU_VID_PLL_ASIF_SLV_SECTION 0xA000 +#define mmPMMU_VID_PLL_DIV_0_RLX_BASE 0x4D05400ull +#define PMMU_VID_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define PMMU_VID_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmPMMU_VID_PLL_DIV_1_RLX_BASE 0x4D05800ull +#define PMMU_VID_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define PMMU_VID_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmPMMU_VID_PLL_DIV_2_RLX_BASE 0x4D05A00ull +#define PMMU_VID_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define PMMU_VID_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmPMMU_VID_PLL_DIV_3_RLX_BASE 0x4D05C00ull +#define PMMU_VID_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define PMMU_VID_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmPMMU_VID_PLL_SPECIAL_BASE 0x4D05E80ull +#define PMMU_VID_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define PMMU_VID_PLL_SPECIAL_SECTION 0x3A180 +#define mmXBAR_MID_0_BASE 0x4D40000ull +#define XBAR_MID_0_MAX_OFFSET 0x1000 +#define XBAR_MID_0_SECTION 0xE800 +#define mmXBAR_MID_0_SPECIAL_BASE 0x4D40E80ull +#define XBAR_MID_0_SPECIAL_MAX_OFFSET 0x1800 +#define XBAR_MID_0_SPECIAL_SECTION 0x1800 +#define mmDCORE0_XBAR_DMA_PLL_CTRL_BASE 0x4D41000ull +#define DCORE0_XBAR_DMA_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE0_XBAR_DMA_PLL_CTRL_SECTION 0x3600 +#define mmDCORE0_XBAR_DMA_PLL_ASIF_SLV_BASE 0x4D41360ull +#define DCORE0_XBAR_DMA_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE0_XBAR_DMA_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE0_XBAR_DMA_PLL_DIV_0_RLX_BASE 0x4D41400ull +#define DCORE0_XBAR_DMA_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE0_XBAR_DMA_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE0_XBAR_DMA_PLL_DIV_1_RLX_BASE 0x4D41800ull +#define DCORE0_XBAR_DMA_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_DMA_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE0_XBAR_DMA_PLL_DIV_2_RLX_BASE 0x4D41A00ull +#define DCORE0_XBAR_DMA_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_DMA_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE0_XBAR_DMA_PLL_DIV_3_RLX_BASE 0x4D41C00ull +#define DCORE0_XBAR_DMA_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_DMA_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE0_XBAR_DMA_PLL_SPECIAL_BASE 0x4D41E80ull +#define DCORE0_XBAR_DMA_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_XBAR_DMA_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_XBAR_MMU_PLL_CTRL_BASE 0x4D42000ull +#define DCORE0_XBAR_MMU_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE0_XBAR_MMU_PLL_CTRL_SECTION 0x3600 +#define mmDCORE0_XBAR_MMU_PLL_ASIF_SLV_BASE 0x4D42360ull +#define DCORE0_XBAR_MMU_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE0_XBAR_MMU_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE0_XBAR_MMU_PLL_DIV_0_RLX_BASE 0x4D42400ull +#define DCORE0_XBAR_MMU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE0_XBAR_MMU_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE0_XBAR_MMU_PLL_DIV_1_RLX_BASE 0x4D42800ull +#define DCORE0_XBAR_MMU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_MMU_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE0_XBAR_MMU_PLL_DIV_2_RLX_BASE 0x4D42A00ull +#define DCORE0_XBAR_MMU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_MMU_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE0_XBAR_MMU_PLL_DIV_3_RLX_BASE 0x4D42C00ull +#define DCORE0_XBAR_MMU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_MMU_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE0_XBAR_MMU_PLL_SPECIAL_BASE 0x4D42E80ull +#define DCORE0_XBAR_MMU_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_XBAR_MMU_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_XBAR_IF_PLL_CTRL_BASE 0x4D43000ull +#define DCORE0_XBAR_IF_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE0_XBAR_IF_PLL_CTRL_SECTION 0x3600 +#define mmDCORE0_XBAR_IF_PLL_ASIF_SLV_BASE 0x4D43360ull +#define DCORE0_XBAR_IF_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE0_XBAR_IF_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE0_XBAR_IF_PLL_DIV_0_RLX_BASE 0x4D43400ull +#define DCORE0_XBAR_IF_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE0_XBAR_IF_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE0_XBAR_IF_PLL_DIV_1_RLX_BASE 0x4D43800ull +#define DCORE0_XBAR_IF_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_IF_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE0_XBAR_IF_PLL_DIV_2_RLX_BASE 0x4D43A00ull +#define DCORE0_XBAR_IF_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_IF_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE0_XBAR_IF_PLL_DIV_3_RLX_BASE 0x4D43C00ull +#define DCORE0_XBAR_IF_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_IF_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE0_XBAR_IF_PLL_SPECIAL_BASE 0x4D43E80ull +#define DCORE0_XBAR_IF_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_XBAR_IF_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_XBAR_MESH_PLL_CTRL_BASE 0x4D44000ull +#define DCORE0_XBAR_MESH_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE0_XBAR_MESH_PLL_CTRL_SECTION 0x3600 +#define mmDCORE0_XBAR_MESH_PLL_ASIF_SLV_BASE 0x4D44360ull +#define DCORE0_XBAR_MESH_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE0_XBAR_MESH_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE0_XBAR_MESH_PLL_DIV_0_RLX_BASE 0x4D44400ull +#define DCORE0_XBAR_MESH_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE0_XBAR_MESH_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE0_XBAR_MESH_PLL_DIV_1_RLX_BASE 0x4D44800ull +#define DCORE0_XBAR_MESH_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_MESH_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE0_XBAR_MESH_PLL_DIV_2_RLX_BASE 0x4D44A00ull +#define DCORE0_XBAR_MESH_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_MESH_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE0_XBAR_MESH_PLL_DIV_3_RLX_BASE 0x4D44C00ull +#define DCORE0_XBAR_MESH_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_MESH_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE0_XBAR_MESH_PLL_SPECIAL_BASE 0x4D44E80ull +#define DCORE0_XBAR_MESH_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_XBAR_MESH_PLL_SPECIAL_SECTION 0x3180 +#define mmXBAR_EDGE_0_BASE 0x4D48000ull +#define XBAR_EDGE_0_MAX_OFFSET 0x1000 +#define XBAR_EDGE_0_SECTION 0xE800 +#define mmXBAR_EDGE_0_SPECIAL_BASE 0x4D48E80ull +#define XBAR_EDGE_0_SPECIAL_MAX_OFFSET 0x1800 +#define XBAR_EDGE_0_SPECIAL_SECTION 0x7180 +#define mmXBAR_MID_1_BASE 0x4D50000ull +#define XBAR_MID_1_MAX_OFFSET 0x1000 +#define XBAR_MID_1_SECTION 0xE800 +#define mmXBAR_MID_1_SPECIAL_BASE 0x4D50E80ull +#define XBAR_MID_1_SPECIAL_MAX_OFFSET 0x1800 +#define XBAR_MID_1_SPECIAL_SECTION 0x1800 +#define mmDCORE1_XBAR_DMA_PLL_CTRL_BASE 0x4D51000ull +#define DCORE1_XBAR_DMA_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE1_XBAR_DMA_PLL_CTRL_SECTION 0x3600 +#define mmDCORE1_XBAR_DMA_PLL_ASIF_SLV_BASE 0x4D51360ull +#define DCORE1_XBAR_DMA_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_XBAR_DMA_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE1_XBAR_DMA_PLL_DIV_0_RLX_BASE 0x4D51400ull +#define DCORE1_XBAR_DMA_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_DMA_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE1_XBAR_DMA_PLL_DIV_1_RLX_BASE 0x4D51800ull +#define DCORE1_XBAR_DMA_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_DMA_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE1_XBAR_DMA_PLL_DIV_2_RLX_BASE 0x4D51A00ull +#define DCORE1_XBAR_DMA_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_DMA_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE1_XBAR_DMA_PLL_DIV_3_RLX_BASE 0x4D51C00ull +#define DCORE1_XBAR_DMA_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_DMA_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE1_XBAR_DMA_PLL_SPECIAL_BASE 0x4D51E80ull +#define DCORE1_XBAR_DMA_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_DMA_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_XBAR_MMU_PLL_CTRL_BASE 0x4D52000ull +#define DCORE1_XBAR_MMU_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE1_XBAR_MMU_PLL_CTRL_SECTION 0x3600 +#define mmDCORE1_XBAR_MMU_PLL_ASIF_SLV_BASE 0x4D52360ull +#define DCORE1_XBAR_MMU_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_XBAR_MMU_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE1_XBAR_MMU_PLL_DIV_0_RLX_BASE 0x4D52400ull +#define DCORE1_XBAR_MMU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_MMU_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE1_XBAR_MMU_PLL_DIV_1_RLX_BASE 0x4D52800ull +#define DCORE1_XBAR_MMU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_MMU_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE1_XBAR_MMU_PLL_DIV_2_RLX_BASE 0x4D52A00ull +#define DCORE1_XBAR_MMU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_MMU_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE1_XBAR_MMU_PLL_DIV_3_RLX_BASE 0x4D52C00ull +#define DCORE1_XBAR_MMU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_MMU_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE1_XBAR_MMU_PLL_SPECIAL_BASE 0x4D52E80ull +#define DCORE1_XBAR_MMU_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_MMU_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_XBAR_IF_PLL_CTRL_BASE 0x4D53000ull +#define DCORE1_XBAR_IF_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE1_XBAR_IF_PLL_CTRL_SECTION 0x3600 +#define mmDCORE1_XBAR_IF_PLL_ASIF_SLV_BASE 0x4D53360ull +#define DCORE1_XBAR_IF_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_XBAR_IF_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE1_XBAR_IF_PLL_DIV_0_RLX_BASE 0x4D53400ull +#define DCORE1_XBAR_IF_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_IF_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE1_XBAR_IF_PLL_DIV_1_RLX_BASE 0x4D53800ull +#define DCORE1_XBAR_IF_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_IF_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE1_XBAR_IF_PLL_DIV_2_RLX_BASE 0x4D53A00ull +#define DCORE1_XBAR_IF_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_IF_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE1_XBAR_IF_PLL_DIV_3_RLX_BASE 0x4D53C00ull +#define DCORE1_XBAR_IF_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_IF_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE1_XBAR_IF_PLL_SPECIAL_BASE 0x4D53E80ull +#define DCORE1_XBAR_IF_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_IF_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_XBAR_MESH_PLL_CTRL_BASE 0x4D54000ull +#define DCORE1_XBAR_MESH_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE1_XBAR_MESH_PLL_CTRL_SECTION 0x3600 +#define mmDCORE1_XBAR_MESH_PLL_ASIF_SLV_BASE 0x4D54360ull +#define DCORE1_XBAR_MESH_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_XBAR_MESH_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE1_XBAR_MESH_PLL_DIV_0_RLX_BASE 0x4D54400ull +#define DCORE1_XBAR_MESH_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_MESH_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE1_XBAR_MESH_PLL_DIV_1_RLX_BASE 0x4D54800ull +#define DCORE1_XBAR_MESH_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_MESH_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE1_XBAR_MESH_PLL_DIV_2_RLX_BASE 0x4D54A00ull +#define DCORE1_XBAR_MESH_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_MESH_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE1_XBAR_MESH_PLL_DIV_3_RLX_BASE 0x4D54C00ull +#define DCORE1_XBAR_MESH_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_MESH_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE1_XBAR_MESH_PLL_SPECIAL_BASE 0x4D54E80ull +#define DCORE1_XBAR_MESH_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_MESH_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_XBAR_HBM_PLL_CTRL_BASE 0x4D55000ull +#define DCORE1_XBAR_HBM_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE1_XBAR_HBM_PLL_CTRL_SECTION 0x3600 +#define mmDCORE1_XBAR_HBM_PLL_ASIF_SLV_BASE 0x4D55360ull +#define DCORE1_XBAR_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_XBAR_HBM_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE1_XBAR_HBM_PLL_DIV_0_RLX_BASE 0x4D55400ull +#define DCORE1_XBAR_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_HBM_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE1_XBAR_HBM_PLL_DIV_1_RLX_BASE 0x4D55800ull +#define DCORE1_XBAR_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_HBM_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE1_XBAR_HBM_PLL_DIV_2_RLX_BASE 0x4D55A00ull +#define DCORE1_XBAR_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_HBM_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE1_XBAR_HBM_PLL_DIV_3_RLX_BASE 0x4D55C00ull +#define DCORE1_XBAR_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_HBM_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE1_XBAR_HBM_PLL_SPECIAL_BASE 0x4D55E80ull +#define DCORE1_XBAR_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_HBM_PLL_SPECIAL_SECTION 0x2180 +#define mmXBAR_EDGE_1_BASE 0x4D58000ull +#define XBAR_EDGE_1_MAX_OFFSET 0x1000 +#define XBAR_EDGE_1_SECTION 0xE800 +#define mmXBAR_EDGE_1_SPECIAL_BASE 0x4D58E80ull +#define XBAR_EDGE_1_SPECIAL_MAX_OFFSET 0x1800 +#define XBAR_EDGE_1_SPECIAL_SECTION 0x7180 +#define mmXBAR_MID_2_BASE 0x4D60000ull +#define XBAR_MID_2_MAX_OFFSET 0x1000 +#define XBAR_MID_2_SECTION 0xE800 +#define mmXBAR_MID_2_SPECIAL_BASE 0x4D60E80ull +#define XBAR_MID_2_SPECIAL_MAX_OFFSET 0x1800 +#define XBAR_MID_2_SPECIAL_SECTION 0x1800 +#define mmDCORE2_XBAR_DMA_PLL_CTRL_BASE 0x4D61000ull +#define DCORE2_XBAR_DMA_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE2_XBAR_DMA_PLL_CTRL_SECTION 0x3600 +#define mmDCORE2_XBAR_DMA_PLL_ASIF_SLV_BASE 0x4D61360ull +#define DCORE2_XBAR_DMA_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE2_XBAR_DMA_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE2_XBAR_DMA_PLL_DIV_0_RLX_BASE 0x4D61400ull +#define DCORE2_XBAR_DMA_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_DMA_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE2_XBAR_DMA_PLL_DIV_1_RLX_BASE 0x4D61800ull +#define DCORE2_XBAR_DMA_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_DMA_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE2_XBAR_DMA_PLL_DIV_2_RLX_BASE 0x4D61A00ull +#define DCORE2_XBAR_DMA_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_DMA_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE2_XBAR_DMA_PLL_DIV_3_RLX_BASE 0x4D61C00ull +#define DCORE2_XBAR_DMA_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_DMA_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE2_XBAR_DMA_PLL_SPECIAL_BASE 0x4D61E80ull +#define DCORE2_XBAR_DMA_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_DMA_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_XBAR_MMU_PLL_CTRL_BASE 0x4D62000ull +#define DCORE2_XBAR_MMU_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE2_XBAR_MMU_PLL_CTRL_SECTION 0x3600 +#define mmDCORE2_XBAR_MMU_PLL_ASIF_SLV_BASE 0x4D62360ull +#define DCORE2_XBAR_MMU_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE2_XBAR_MMU_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE2_XBAR_MMU_PLL_DIV_0_RLX_BASE 0x4D62400ull +#define DCORE2_XBAR_MMU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_MMU_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE2_XBAR_MMU_PLL_DIV_1_RLX_BASE 0x4D62800ull +#define DCORE2_XBAR_MMU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_MMU_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE2_XBAR_MMU_PLL_DIV_2_RLX_BASE 0x4D62A00ull +#define DCORE2_XBAR_MMU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_MMU_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE2_XBAR_MMU_PLL_DIV_3_RLX_BASE 0x4D62C00ull +#define DCORE2_XBAR_MMU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_MMU_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE2_XBAR_MMU_PLL_SPECIAL_BASE 0x4D62E80ull +#define DCORE2_XBAR_MMU_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_MMU_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_XBAR_IF_PLL_CTRL_BASE 0x4D63000ull +#define DCORE2_XBAR_IF_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE2_XBAR_IF_PLL_CTRL_SECTION 0x3600 +#define mmDCORE2_XBAR_IF_PLL_ASIF_SLV_BASE 0x4D63360ull +#define DCORE2_XBAR_IF_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE2_XBAR_IF_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE2_XBAR_IF_PLL_DIV_0_RLX_BASE 0x4D63400ull +#define DCORE2_XBAR_IF_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_IF_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE2_XBAR_IF_PLL_DIV_1_RLX_BASE 0x4D63800ull +#define DCORE2_XBAR_IF_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_IF_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE2_XBAR_IF_PLL_DIV_2_RLX_BASE 0x4D63A00ull +#define DCORE2_XBAR_IF_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_IF_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE2_XBAR_IF_PLL_DIV_3_RLX_BASE 0x4D63C00ull +#define DCORE2_XBAR_IF_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_IF_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE2_XBAR_IF_PLL_SPECIAL_BASE 0x4D63E80ull +#define DCORE2_XBAR_IF_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_IF_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_XBAR_BANK_PLL_CTRL_BASE 0x4D64000ull +#define DCORE2_XBAR_BANK_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE2_XBAR_BANK_PLL_CTRL_SECTION 0x3600 +#define mmDCORE2_XBAR_BANK_PLL_ASIF_SLV_BASE 0x4D64360ull +#define DCORE2_XBAR_BANK_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE2_XBAR_BANK_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE2_XBAR_BANK_PLL_DIV_0_RLX_BASE 0x4D64400ull +#define DCORE2_XBAR_BANK_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_BANK_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE2_XBAR_BANK_PLL_DIV_1_RLX_BASE 0x4D64800ull +#define DCORE2_XBAR_BANK_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_BANK_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE2_XBAR_BANK_PLL_DIV_2_RLX_BASE 0x4D64A00ull +#define DCORE2_XBAR_BANK_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_BANK_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE2_XBAR_BANK_PLL_DIV_3_RLX_BASE 0x4D64C00ull +#define DCORE2_XBAR_BANK_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_BANK_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE2_XBAR_BANK_PLL_SPECIAL_BASE 0x4D64E80ull +#define DCORE2_XBAR_BANK_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_BANK_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_XBAR_HBM_PLL_CTRL_BASE 0x4D65000ull +#define DCORE2_XBAR_HBM_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE2_XBAR_HBM_PLL_CTRL_SECTION 0x3600 +#define mmDCORE2_XBAR_HBM_PLL_ASIF_SLV_BASE 0x4D65360ull +#define DCORE2_XBAR_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE2_XBAR_HBM_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE2_XBAR_HBM_PLL_DIV_0_RLX_BASE 0x4D65400ull +#define DCORE2_XBAR_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_HBM_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE2_XBAR_HBM_PLL_DIV_1_RLX_BASE 0x4D65800ull +#define DCORE2_XBAR_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_HBM_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE2_XBAR_HBM_PLL_DIV_2_RLX_BASE 0x4D65A00ull +#define DCORE2_XBAR_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_HBM_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE2_XBAR_HBM_PLL_DIV_3_RLX_BASE 0x4D65C00ull +#define DCORE2_XBAR_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_HBM_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE2_XBAR_HBM_PLL_SPECIAL_BASE 0x4D65E80ull +#define DCORE2_XBAR_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_HBM_PLL_SPECIAL_SECTION 0x2180 +#define mmXBAR_EDGE_2_BASE 0x4D68000ull +#define XBAR_EDGE_2_MAX_OFFSET 0x1000 +#define XBAR_EDGE_2_SECTION 0xE800 +#define mmXBAR_EDGE_2_SPECIAL_BASE 0x4D68E80ull +#define XBAR_EDGE_2_SPECIAL_MAX_OFFSET 0x1800 +#define XBAR_EDGE_2_SPECIAL_SECTION 0x7180 +#define mmXBAR_MID_3_BASE 0x4D70000ull +#define XBAR_MID_3_MAX_OFFSET 0x1000 +#define XBAR_MID_3_SECTION 0xE800 +#define mmXBAR_MID_3_SPECIAL_BASE 0x4D70E80ull +#define XBAR_MID_3_SPECIAL_MAX_OFFSET 0x1800 +#define XBAR_MID_3_SPECIAL_SECTION 0x1800 +#define mmDCORE3_XBAR_DMA_PLL_CTRL_BASE 0x4D71000ull +#define DCORE3_XBAR_DMA_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE3_XBAR_DMA_PLL_CTRL_SECTION 0x3600 +#define mmDCORE3_XBAR_DMA_PLL_ASIF_SLV_BASE 0x4D71360ull +#define DCORE3_XBAR_DMA_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE3_XBAR_DMA_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE3_XBAR_DMA_PLL_DIV_0_RLX_BASE 0x4D71400ull +#define DCORE3_XBAR_DMA_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE3_XBAR_DMA_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE3_XBAR_DMA_PLL_DIV_1_RLX_BASE 0x4D71800ull +#define DCORE3_XBAR_DMA_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_DMA_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE3_XBAR_DMA_PLL_DIV_2_RLX_BASE 0x4D71A00ull +#define DCORE3_XBAR_DMA_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_DMA_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE3_XBAR_DMA_PLL_DIV_3_RLX_BASE 0x4D71C00ull +#define DCORE3_XBAR_DMA_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_DMA_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE3_XBAR_DMA_PLL_SPECIAL_BASE 0x4D71E80ull +#define DCORE3_XBAR_DMA_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_XBAR_DMA_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_XBAR_MMU_PLL_CTRL_BASE 0x4D72000ull +#define DCORE3_XBAR_MMU_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE3_XBAR_MMU_PLL_CTRL_SECTION 0x3600 +#define mmDCORE3_XBAR_MMU_PLL_ASIF_SLV_BASE 0x4D72360ull +#define DCORE3_XBAR_MMU_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE3_XBAR_MMU_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE3_XBAR_MMU_PLL_DIV_0_RLX_BASE 0x4D72400ull +#define DCORE3_XBAR_MMU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE3_XBAR_MMU_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE3_XBAR_MMU_PLL_DIV_1_RLX_BASE 0x4D72800ull +#define DCORE3_XBAR_MMU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_MMU_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE3_XBAR_MMU_PLL_DIV_2_RLX_BASE 0x4D72A00ull +#define DCORE3_XBAR_MMU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_MMU_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE3_XBAR_MMU_PLL_DIV_3_RLX_BASE 0x4D72C00ull +#define DCORE3_XBAR_MMU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_MMU_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE3_XBAR_MMU_PLL_SPECIAL_BASE 0x4D72E80ull +#define DCORE3_XBAR_MMU_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_XBAR_MMU_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_XBAR_IF_PLL_CTRL_BASE 0x4D73000ull +#define DCORE3_XBAR_IF_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE3_XBAR_IF_PLL_CTRL_SECTION 0x3600 +#define mmDCORE3_XBAR_IF_PLL_ASIF_SLV_BASE 0x4D73360ull +#define DCORE3_XBAR_IF_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE3_XBAR_IF_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE3_XBAR_IF_PLL_DIV_0_RLX_BASE 0x4D73400ull +#define DCORE3_XBAR_IF_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE3_XBAR_IF_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE3_XBAR_IF_PLL_DIV_1_RLX_BASE 0x4D73800ull +#define DCORE3_XBAR_IF_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_IF_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE3_XBAR_IF_PLL_DIV_2_RLX_BASE 0x4D73A00ull +#define DCORE3_XBAR_IF_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_IF_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE3_XBAR_IF_PLL_DIV_3_RLX_BASE 0x4D73C00ull +#define DCORE3_XBAR_IF_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_IF_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE3_XBAR_IF_PLL_SPECIAL_BASE 0x4D73E80ull +#define DCORE3_XBAR_IF_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_XBAR_IF_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_XBAR_BANK_PLL_CTRL_BASE 0x4D74000ull +#define DCORE3_XBAR_BANK_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE3_XBAR_BANK_PLL_CTRL_SECTION 0x3600 +#define mmDCORE3_XBAR_BANK_PLL_ASIF_SLV_BASE 0x4D74360ull +#define DCORE3_XBAR_BANK_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE3_XBAR_BANK_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE3_XBAR_BANK_PLL_DIV_0_RLX_BASE 0x4D74400ull +#define DCORE3_XBAR_BANK_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE3_XBAR_BANK_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE3_XBAR_BANK_PLL_DIV_1_RLX_BASE 0x4D74800ull +#define DCORE3_XBAR_BANK_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_BANK_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE3_XBAR_BANK_PLL_DIV_2_RLX_BASE 0x4D74A00ull +#define DCORE3_XBAR_BANK_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_BANK_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE3_XBAR_BANK_PLL_DIV_3_RLX_BASE 0x4D74C00ull +#define DCORE3_XBAR_BANK_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_BANK_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE3_XBAR_BANK_PLL_SPECIAL_BASE 0x4D74E80ull +#define DCORE3_XBAR_BANK_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_XBAR_BANK_PLL_SPECIAL_SECTION 0x3180 +#define mmXBAR_EDGE_3_BASE 0x4D78000ull +#define XBAR_EDGE_3_MAX_OFFSET 0x1000 +#define XBAR_EDGE_3_SECTION 0xE800 +#define mmXBAR_EDGE_3_SPECIAL_BASE 0x4D78E80ull +#define XBAR_EDGE_3_SPECIAL_MAX_OFFSET 0x1800 +#define XBAR_EDGE_3_SPECIAL_SECTION 0x7180 +#define mmPCIE_PMA_0_BASE 0x4D80000ull +#define PCIE_PMA_0_MAX_OFFSET 0x40000 +#define PCIE_PMA_0_SECTION 0x40000 +#define mmPCIE_PMA_1_BASE 0x4DC0000ull +#define PCIE_PMA_1_MAX_OFFSET 0x40000 +#define PCIE_PMA_1_SECTION 0x40000 +#define mmROT0_QM_ARC_DCCM_BASE 0x4E00000ull +#define ROT0_QM_ARC_DCCM_MAX_OFFSET 0x4000 +#define ROT0_QM_ARC_DCCM_SECTION 0x8000 +#define mmROT0_QM_ARC_AUX_BASE 0x4E08000ull +#define ROT0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define ROT0_QM_ARC_AUX_SECTION 0xE800 +#define mmROT0_QM_ARC_AUX_SPECIAL_BASE 0x4E08E80ull +#define ROT0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define ROT0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmROT0_QM_BASE 0x4E0A000ull +#define ROT0_QM_MAX_OFFSET 0x1000 +#define ROT0_QM_SECTION 0x9000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4E0A900ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4E0A908ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4E0A910ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4E0A918ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4E0A920ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4E0A928ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4E0A930ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4E0A938ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4E0A940ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4E0A948ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4E0A950ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4E0A958ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4E0A960ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4E0A968ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4E0A970ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmROT0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4E0A978ull +#define ROT0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define ROT0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmROT0_QM_AXUSER_SECURED_BASE 0x4E0AB00ull +#define ROT0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define ROT0_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmROT0_QM_AXUSER_NONSECURED_BASE 0x4E0AB80ull +#define ROT0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define ROT0_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmROT0_QM_DBG_HBW_BASE 0x4E0AC00ull +#define ROT0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define ROT0_QM_DBG_HBW_SECTION 0x8000 +#define mmROT0_QM_DBG_LBW_BASE 0x4E0AC80ull +#define ROT0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define ROT0_QM_DBG_LBW_SECTION 0x1000 +#define mmROT0_QM_CGM_BASE 0x4E0AD80ull +#define ROT0_QM_CGM_MAX_OFFSET 0xC000 +#define ROT0_QM_CGM_SECTION 0x1000 +#define mmROT0_QM_SPECIAL_BASE 0x4E0AE80ull +#define ROT0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define ROT0_QM_SPECIAL_SECTION 0x1800 +#define mmROT0_BASE 0x4E0B000ull +#define ROT0_MAX_OFFSET 0x1000 +#define ROT0_SECTION 0x1000 +#define mmROT0_DESC_BASE 0x4E0B100ull +#define ROT0_DESC_MAX_OFFSET 0x1080 +#define ROT0_DESC_SECTION 0xD800 +#define mmROT0_SPECIAL_BASE 0x4E0BE80ull +#define ROT0_SPECIAL_MAX_OFFSET 0x1800 +#define ROT0_SPECIAL_SECTION 0x1800 +#define mmROT0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E0C000ull +#define ROT0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define ROT0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmROT0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E0C200ull +#define ROT0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define ROT0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmROT0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E0C400ull +#define ROT0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define ROT0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmROT0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E0C600ull +#define ROT0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define ROT0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmROT0_MSTR_IF_E2E_CRDT_BASE 0x4E0C800ull +#define ROT0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define ROT0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmROT0_MSTR_IF_AXUSER_BASE 0x4E0CA80ull +#define ROT0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define ROT0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmROT0_MSTR_IF_DBG_HBW_BASE 0x4E0CB00ull +#define ROT0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define ROT0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmROT0_MSTR_IF_DBG_LBW_BASE 0x4E0CB80ull +#define ROT0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define ROT0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmROT0_MSTR_IF_CORE_HBW_BASE 0x4E0CC00ull +#define ROT0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define ROT0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmROT0_MSTR_IF_CORE_LBW_BASE 0x4E0CD80ull +#define ROT0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define ROT0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmROT0_MSTR_IF_SPECIAL_BASE 0x4E0CE80ull +#define ROT0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define ROT0_MSTR_IF_SPECIAL_SECTION 0x3180 +#define mmROT1_QM_ARC_DCCM_BASE 0x4E10000ull +#define ROT1_QM_ARC_DCCM_MAX_OFFSET 0x4000 +#define ROT1_QM_ARC_DCCM_SECTION 0x8000 +#define mmROT1_QM_ARC_AUX_BASE 0x4E18000ull +#define ROT1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define ROT1_QM_ARC_AUX_SECTION 0xE800 +#define mmROT1_QM_ARC_AUX_SPECIAL_BASE 0x4E18E80ull +#define ROT1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define ROT1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 +#define mmROT1_QM_BASE 0x4E1A000ull +#define ROT1_QM_MAX_OFFSET 0x1000 +#define ROT1_QM_SECTION 0x9000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4E1A900ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4E1A908ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4E1A910ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4E1A918ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4E1A920ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4E1A928ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4E1A930ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4E1A938ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4E1A940ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4E1A948ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4E1A950ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4E1A958ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4E1A960ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4E1A968ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4E1A970ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmROT1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4E1A978ull +#define ROT1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define ROT1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmROT1_QM_AXUSER_SECURED_BASE 0x4E1AB00ull +#define ROT1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define ROT1_QM_AXUSER_SECURED_SECTION 0x8000 +#define mmROT1_QM_AXUSER_NONSECURED_BASE 0x4E1AB80ull +#define ROT1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define ROT1_QM_AXUSER_NONSECURED_SECTION 0x8000 +#define mmROT1_QM_DBG_HBW_BASE 0x4E1AC00ull +#define ROT1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define ROT1_QM_DBG_HBW_SECTION 0x8000 +#define mmROT1_QM_DBG_LBW_BASE 0x4E1AC80ull +#define ROT1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define ROT1_QM_DBG_LBW_SECTION 0x1000 +#define mmROT1_QM_CGM_BASE 0x4E1AD80ull +#define ROT1_QM_CGM_MAX_OFFSET 0xC000 +#define ROT1_QM_CGM_SECTION 0x1000 +#define mmROT1_QM_SPECIAL_BASE 0x4E1AE80ull +#define ROT1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define ROT1_QM_SPECIAL_SECTION 0x1800 +#define mmROT1_BASE 0x4E1B000ull +#define ROT1_MAX_OFFSET 0x1000 +#define ROT1_SECTION 0x1000 +#define mmROT1_DESC_BASE 0x4E1B100ull +#define ROT1_DESC_MAX_OFFSET 0x1080 +#define ROT1_DESC_SECTION 0xD800 +#define mmROT1_SPECIAL_BASE 0x4E1BE80ull +#define ROT1_SPECIAL_MAX_OFFSET 0x1800 +#define ROT1_SPECIAL_SECTION 0x1800 +#define mmROT1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E1C000ull +#define ROT1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define ROT1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmROT1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E1C200ull +#define ROT1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define ROT1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmROT1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E1C400ull +#define ROT1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define ROT1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmROT1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E1C600ull +#define ROT1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define ROT1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmROT1_MSTR_IF_E2E_CRDT_BASE 0x4E1C800ull +#define ROT1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define ROT1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmROT1_MSTR_IF_AXUSER_BASE 0x4E1CA80ull +#define ROT1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define ROT1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmROT1_MSTR_IF_DBG_HBW_BASE 0x4E1CB00ull +#define ROT1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define ROT1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmROT1_MSTR_IF_DBG_LBW_BASE 0x4E1CB80ull +#define ROT1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define ROT1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmROT1_MSTR_IF_CORE_HBW_BASE 0x4E1CC00ull +#define ROT1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define ROT1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmROT1_MSTR_IF_CORE_LBW_BASE 0x4E1CD80ull +#define ROT1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define ROT1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmROT1_MSTR_IF_SPECIAL_BASE 0x4E1CE80ull +#define ROT1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define ROT1_MSTR_IF_SPECIAL_SECTION 0x23180 +#define mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE 0x4E40000ull +#define SFT0_HBW_RTR_IF0_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT0_HBW_RTR_IF0_RTR_CTRL_SECTION 0xE800 +#define mmSFT0_HBW_RTR_IF0_RTR_CTRL_SPECIAL_BASE 0x4E40E80ull +#define SFT0_HBW_RTR_IF0_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_HBW_RTR_IF0_RTR_CTRL_SPECIAL_SECTION 0x1800 +#define mmSFT0_HBW_RTR_IF0_RTR_H3_BASE 0x4E41000ull +#define SFT0_HBW_RTR_IF0_RTR_H3_MAX_OFFSET 0x1000 +#define SFT0_HBW_RTR_IF0_RTR_H3_SECTION 0xE800 +#define mmSFT0_HBW_RTR_IF0_RTR_H3_SPECIAL_BASE 0x4E41E80ull +#define SFT0_HBW_RTR_IF0_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_HBW_RTR_IF0_RTR_H3_SPECIAL_SECTION 0x1800 +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E42000ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E42200ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E42400ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E42600ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_BASE 0x4E42800ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT0_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_AXUSER_BASE 0x4E42A80ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT0_HBW_RTR_IF0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_DBG_HBW_BASE 0x4E42B00ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_DBG_LBW_BASE 0x4E42B80ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_CORE_HBW_BASE 0x4E42C00ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_CORE_LBW_BASE 0x4E42D80ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_SPECIAL_BASE 0x4E42E80ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_HBW_RTR_IF0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSFT0_HBW_RTR_IF0_ADDR_DEC_HBW_BASE 0x4E43000ull +#define SFT0_HBW_RTR_IF0_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT0_HBW_RTR_IF0_ADDR_DEC_HBW_SECTION 0x4000 +#define mmSFT0_HBW_RTR_IF0_ADDR_DEC_LBW_BASE 0x4E43400ull +#define SFT0_HBW_RTR_IF0_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT0_HBW_RTR_IF0_ADDR_DEC_LBW_SECTION 0xA800 +#define mmSFT0_HBW_RTR_IF0_ADDR_DEC_SPECIAL_BASE 0x4E43E80ull +#define SFT0_HBW_RTR_IF0_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_HBW_RTR_IF0_ADDR_DEC_SPECIAL_SECTION 0x1800 +#define mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE 0x4E44000ull +#define SFT0_HBW_RTR_IF1_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT0_HBW_RTR_IF1_RTR_CTRL_SECTION 0xE800 +#define mmSFT0_HBW_RTR_IF1_RTR_CTRL_SPECIAL_BASE 0x4E44E80ull +#define SFT0_HBW_RTR_IF1_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_HBW_RTR_IF1_RTR_CTRL_SPECIAL_SECTION 0x1800 +#define mmSFT0_HBW_RTR_IF1_RTR_H3_BASE 0x4E45000ull +#define SFT0_HBW_RTR_IF1_RTR_H3_MAX_OFFSET 0x1000 +#define SFT0_HBW_RTR_IF1_RTR_H3_SECTION 0xE800 +#define mmSFT0_HBW_RTR_IF1_RTR_H3_SPECIAL_BASE 0x4E45E80ull +#define SFT0_HBW_RTR_IF1_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_HBW_RTR_IF1_RTR_H3_SPECIAL_SECTION 0x1800 +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E46000ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E46200ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E46400ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E46600ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_BASE 0x4E46800ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT0_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_AXUSER_BASE 0x4E46A80ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT0_HBW_RTR_IF1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_DBG_HBW_BASE 0x4E46B00ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_DBG_LBW_BASE 0x4E46B80ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_CORE_HBW_BASE 0x4E46C00ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_CORE_LBW_BASE 0x4E46D80ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_SPECIAL_BASE 0x4E46E80ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_HBW_RTR_IF1_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSFT0_HBW_RTR_IF1_ADDR_DEC_HBW_BASE 0x4E47000ull +#define SFT0_HBW_RTR_IF1_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT0_HBW_RTR_IF1_ADDR_DEC_HBW_SECTION 0x4000 +#define mmSFT0_HBW_RTR_IF1_ADDR_DEC_LBW_BASE 0x4E47400ull +#define SFT0_HBW_RTR_IF1_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT0_HBW_RTR_IF1_ADDR_DEC_LBW_SECTION 0xA800 +#define mmSFT0_HBW_RTR_IF1_ADDR_DEC_SPECIAL_BASE 0x4E47E80ull +#define SFT0_HBW_RTR_IF1_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_HBW_RTR_IF1_ADDR_DEC_SPECIAL_SECTION 0x1800 +#define mmSFT0_LBW_RTR_IF_RTR_CTRL_BASE 0x4E48000ull +#define SFT0_LBW_RTR_IF_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT0_LBW_RTR_IF_RTR_CTRL_SECTION 0xE800 +#define mmSFT0_LBW_RTR_IF_RTR_CTRL_SPECIAL_BASE 0x4E48E80ull +#define SFT0_LBW_RTR_IF_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_LBW_RTR_IF_RTR_CTRL_SPECIAL_SECTION 0x1800 +#define mmSFT0_LBW_RTR_IF_RTR_H3_BASE 0x4E49000ull +#define SFT0_LBW_RTR_IF_RTR_H3_MAX_OFFSET 0x1000 +#define SFT0_LBW_RTR_IF_RTR_H3_SECTION 0xE800 +#define mmSFT0_LBW_RTR_IF_RTR_H3_SPECIAL_BASE 0x4E49E80ull +#define SFT0_LBW_RTR_IF_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_LBW_RTR_IF_RTR_H3_SPECIAL_SECTION 0x1800 +#define mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE 0x4E4A000ull +#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_BASE 0x4E4A200ull +#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE 0x4E4A400ull +#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_BASE 0x4E4A600ull +#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSFT0_LBW_RTR_IF_MSTR_IF_E2E_CRDT_BASE 0x4E4A800ull +#define SFT0_LBW_RTR_IF_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT0_LBW_RTR_IF_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSFT0_LBW_RTR_IF_MSTR_IF_AXUSER_BASE 0x4E4AA80ull +#define SFT0_LBW_RTR_IF_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT0_LBW_RTR_IF_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSFT0_LBW_RTR_IF_MSTR_IF_DBG_HBW_BASE 0x4E4AB00ull +#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSFT0_LBW_RTR_IF_MSTR_IF_DBG_LBW_BASE 0x4E4AB80ull +#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSFT0_LBW_RTR_IF_MSTR_IF_CORE_HBW_BASE 0x4E4AC00ull +#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSFT0_LBW_RTR_IF_MSTR_IF_CORE_LBW_BASE 0x4E4AD80ull +#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSFT0_LBW_RTR_IF_MSTR_IF_SPECIAL_BASE 0x4E4AE80ull +#define SFT0_LBW_RTR_IF_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_LBW_RTR_IF_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSFT0_LBW_RTR_IF_ADDR_DEC_HBW_BASE 0x4E4B000ull +#define SFT0_LBW_RTR_IF_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT0_LBW_RTR_IF_ADDR_DEC_HBW_SECTION 0x4000 +#define mmSFT0_LBW_RTR_IF_ADDR_DEC_LBW_BASE 0x4E4B400ull +#define SFT0_LBW_RTR_IF_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT0_LBW_RTR_IF_ADDR_DEC_LBW_SECTION 0xA800 +#define mmSFT0_LBW_RTR_IF_ADDR_DEC_SPECIAL_BASE 0x4E4BE80ull +#define SFT0_LBW_RTR_IF_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_LBW_RTR_IF_ADDR_DEC_SPECIAL_SECTION 0x1800 +#define mmSFT0_BASE 0x4E4C000ull +#define SFT0_MAX_OFFSET 0x1000 +#define SFT0_SECTION 0xE800 +#define mmSFT0_SPECIAL_BASE 0x4E4CE80ull +#define SFT0_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_SPECIAL_SECTION 0x3180 +#define mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE 0x4E50000ull +#define SFT1_HBW_RTR_IF0_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT1_HBW_RTR_IF0_RTR_CTRL_SECTION 0xE800 +#define mmSFT1_HBW_RTR_IF0_RTR_CTRL_SPECIAL_BASE 0x4E50E80ull +#define SFT1_HBW_RTR_IF0_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_HBW_RTR_IF0_RTR_CTRL_SPECIAL_SECTION 0x1800 +#define mmSFT1_HBW_RTR_IF0_RTR_H3_BASE 0x4E51000ull +#define SFT1_HBW_RTR_IF0_RTR_H3_MAX_OFFSET 0x1000 +#define SFT1_HBW_RTR_IF0_RTR_H3_SECTION 0xE800 +#define mmSFT1_HBW_RTR_IF0_RTR_H3_SPECIAL_BASE 0x4E51E80ull +#define SFT1_HBW_RTR_IF0_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_HBW_RTR_IF0_RTR_H3_SPECIAL_SECTION 0x1800 +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E52000ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E52200ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E52400ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E52600ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_BASE 0x4E52800ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT1_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_AXUSER_BASE 0x4E52A80ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT1_HBW_RTR_IF0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_DBG_HBW_BASE 0x4E52B00ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_DBG_LBW_BASE 0x4E52B80ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_CORE_HBW_BASE 0x4E52C00ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_CORE_LBW_BASE 0x4E52D80ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_SPECIAL_BASE 0x4E52E80ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_HBW_RTR_IF0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSFT1_HBW_RTR_IF0_ADDR_DEC_HBW_BASE 0x4E53000ull +#define SFT1_HBW_RTR_IF0_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT1_HBW_RTR_IF0_ADDR_DEC_HBW_SECTION 0x4000 +#define mmSFT1_HBW_RTR_IF0_ADDR_DEC_LBW_BASE 0x4E53400ull +#define SFT1_HBW_RTR_IF0_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT1_HBW_RTR_IF0_ADDR_DEC_LBW_SECTION 0xA800 +#define mmSFT1_HBW_RTR_IF0_ADDR_DEC_SPECIAL_BASE 0x4E53E80ull +#define SFT1_HBW_RTR_IF0_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_HBW_RTR_IF0_ADDR_DEC_SPECIAL_SECTION 0x1800 +#define mmSFT1_HBW_RTR_IF1_RTR_CTRL_BASE 0x4E54000ull +#define SFT1_HBW_RTR_IF1_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT1_HBW_RTR_IF1_RTR_CTRL_SECTION 0xE800 +#define mmSFT1_HBW_RTR_IF1_RTR_CTRL_SPECIAL_BASE 0x4E54E80ull +#define SFT1_HBW_RTR_IF1_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_HBW_RTR_IF1_RTR_CTRL_SPECIAL_SECTION 0x1800 +#define mmSFT1_HBW_RTR_IF1_RTR_H3_BASE 0x4E55000ull +#define SFT1_HBW_RTR_IF1_RTR_H3_MAX_OFFSET 0x1000 +#define SFT1_HBW_RTR_IF1_RTR_H3_SECTION 0xE800 +#define mmSFT1_HBW_RTR_IF1_RTR_H3_SPECIAL_BASE 0x4E55E80ull +#define SFT1_HBW_RTR_IF1_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_HBW_RTR_IF1_RTR_H3_SPECIAL_SECTION 0x1800 +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E56000ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E56200ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E56400ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E56600ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_BASE 0x4E56800ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT1_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_AXUSER_BASE 0x4E56A80ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT1_HBW_RTR_IF1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_DBG_HBW_BASE 0x4E56B00ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_DBG_LBW_BASE 0x4E56B80ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_CORE_HBW_BASE 0x4E56C00ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_CORE_LBW_BASE 0x4E56D80ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_SPECIAL_BASE 0x4E56E80ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_HBW_RTR_IF1_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSFT1_HBW_RTR_IF1_ADDR_DEC_HBW_BASE 0x4E57000ull +#define SFT1_HBW_RTR_IF1_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT1_HBW_RTR_IF1_ADDR_DEC_HBW_SECTION 0x4000 +#define mmSFT1_HBW_RTR_IF1_ADDR_DEC_LBW_BASE 0x4E57400ull +#define SFT1_HBW_RTR_IF1_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT1_HBW_RTR_IF1_ADDR_DEC_LBW_SECTION 0xA800 +#define mmSFT1_HBW_RTR_IF1_ADDR_DEC_SPECIAL_BASE 0x4E57E80ull +#define SFT1_HBW_RTR_IF1_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_HBW_RTR_IF1_ADDR_DEC_SPECIAL_SECTION 0x1800 +#define mmSFT1_LBW_RTR_IF_RTR_CTRL_BASE 0x4E58000ull +#define SFT1_LBW_RTR_IF_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT1_LBW_RTR_IF_RTR_CTRL_SECTION 0xE800 +#define mmSFT1_LBW_RTR_IF_RTR_CTRL_SPECIAL_BASE 0x4E58E80ull +#define SFT1_LBW_RTR_IF_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_LBW_RTR_IF_RTR_CTRL_SPECIAL_SECTION 0x1800 +#define mmSFT1_LBW_RTR_IF_RTR_H3_BASE 0x4E59000ull +#define SFT1_LBW_RTR_IF_RTR_H3_MAX_OFFSET 0x1000 +#define SFT1_LBW_RTR_IF_RTR_H3_SECTION 0xE800 +#define mmSFT1_LBW_RTR_IF_RTR_H3_SPECIAL_BASE 0x4E59E80ull +#define SFT1_LBW_RTR_IF_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_LBW_RTR_IF_RTR_H3_SPECIAL_SECTION 0x1800 +#define mmSFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE 0x4E5A000ull +#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_BASE 0x4E5A200ull +#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE 0x4E5A400ull +#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_BASE 0x4E5A600ull +#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSFT1_LBW_RTR_IF_MSTR_IF_E2E_CRDT_BASE 0x4E5A800ull +#define SFT1_LBW_RTR_IF_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT1_LBW_RTR_IF_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSFT1_LBW_RTR_IF_MSTR_IF_AXUSER_BASE 0x4E5AA80ull +#define SFT1_LBW_RTR_IF_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT1_LBW_RTR_IF_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSFT1_LBW_RTR_IF_MSTR_IF_DBG_HBW_BASE 0x4E5AB00ull +#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSFT1_LBW_RTR_IF_MSTR_IF_DBG_LBW_BASE 0x4E5AB80ull +#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSFT1_LBW_RTR_IF_MSTR_IF_CORE_HBW_BASE 0x4E5AC00ull +#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSFT1_LBW_RTR_IF_MSTR_IF_CORE_LBW_BASE 0x4E5AD80ull +#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSFT1_LBW_RTR_IF_MSTR_IF_SPECIAL_BASE 0x4E5AE80ull +#define SFT1_LBW_RTR_IF_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_LBW_RTR_IF_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSFT1_LBW_RTR_IF_ADDR_DEC_HBW_BASE 0x4E5B000ull +#define SFT1_LBW_RTR_IF_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT1_LBW_RTR_IF_ADDR_DEC_HBW_SECTION 0x4000 +#define mmSFT1_LBW_RTR_IF_ADDR_DEC_LBW_BASE 0x4E5B400ull +#define SFT1_LBW_RTR_IF_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT1_LBW_RTR_IF_ADDR_DEC_LBW_SECTION 0xA800 +#define mmSFT1_LBW_RTR_IF_ADDR_DEC_SPECIAL_BASE 0x4E5BE80ull +#define SFT1_LBW_RTR_IF_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_LBW_RTR_IF_ADDR_DEC_SPECIAL_SECTION 0x1800 +#define mmSFT1_BASE 0x4E5C000ull +#define SFT1_MAX_OFFSET 0x1000 +#define SFT1_SECTION 0xE800 +#define mmSFT1_SPECIAL_BASE 0x4E5CE80ull +#define SFT1_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_SPECIAL_SECTION 0x3180 +#define mmSFT2_HBW_RTR_IF0_RTR_CTRL_BASE 0x4E60000ull +#define SFT2_HBW_RTR_IF0_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT2_HBW_RTR_IF0_RTR_CTRL_SECTION 0xE800 +#define mmSFT2_HBW_RTR_IF0_RTR_CTRL_SPECIAL_BASE 0x4E60E80ull +#define SFT2_HBW_RTR_IF0_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_HBW_RTR_IF0_RTR_CTRL_SPECIAL_SECTION 0x1800 +#define mmSFT2_HBW_RTR_IF0_RTR_H3_BASE 0x4E61000ull +#define SFT2_HBW_RTR_IF0_RTR_H3_MAX_OFFSET 0x1000 +#define SFT2_HBW_RTR_IF0_RTR_H3_SECTION 0xE800 +#define mmSFT2_HBW_RTR_IF0_RTR_H3_SPECIAL_BASE 0x4E61E80ull +#define SFT2_HBW_RTR_IF0_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_HBW_RTR_IF0_RTR_H3_SPECIAL_SECTION 0x1800 +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E62000ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E62200ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E62400ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E62600ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_BASE 0x4E62800ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT2_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_AXUSER_BASE 0x4E62A80ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT2_HBW_RTR_IF0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_DBG_HBW_BASE 0x4E62B00ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_DBG_LBW_BASE 0x4E62B80ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_CORE_HBW_BASE 0x4E62C00ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_CORE_LBW_BASE 0x4E62D80ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_SPECIAL_BASE 0x4E62E80ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_HBW_RTR_IF0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSFT2_HBW_RTR_IF0_ADDR_DEC_HBW_BASE 0x4E63000ull +#define SFT2_HBW_RTR_IF0_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT2_HBW_RTR_IF0_ADDR_DEC_HBW_SECTION 0x4000 +#define mmSFT2_HBW_RTR_IF0_ADDR_DEC_LBW_BASE 0x4E63400ull +#define SFT2_HBW_RTR_IF0_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT2_HBW_RTR_IF0_ADDR_DEC_LBW_SECTION 0xA800 +#define mmSFT2_HBW_RTR_IF0_ADDR_DEC_SPECIAL_BASE 0x4E63E80ull +#define SFT2_HBW_RTR_IF0_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_HBW_RTR_IF0_ADDR_DEC_SPECIAL_SECTION 0x1800 +#define mmSFT2_HBW_RTR_IF1_RTR_CTRL_BASE 0x4E64000ull +#define SFT2_HBW_RTR_IF1_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT2_HBW_RTR_IF1_RTR_CTRL_SECTION 0xE800 +#define mmSFT2_HBW_RTR_IF1_RTR_CTRL_SPECIAL_BASE 0x4E64E80ull +#define SFT2_HBW_RTR_IF1_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_HBW_RTR_IF1_RTR_CTRL_SPECIAL_SECTION 0x1800 +#define mmSFT2_HBW_RTR_IF1_RTR_H3_BASE 0x4E65000ull +#define SFT2_HBW_RTR_IF1_RTR_H3_MAX_OFFSET 0x1000 +#define SFT2_HBW_RTR_IF1_RTR_H3_SECTION 0xE800 +#define mmSFT2_HBW_RTR_IF1_RTR_H3_SPECIAL_BASE 0x4E65E80ull +#define SFT2_HBW_RTR_IF1_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_HBW_RTR_IF1_RTR_H3_SPECIAL_SECTION 0x1800 +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E66000ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E66200ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E66400ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E66600ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_BASE 0x4E66800ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT2_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_AXUSER_BASE 0x4E66A80ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT2_HBW_RTR_IF1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_DBG_HBW_BASE 0x4E66B00ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_DBG_LBW_BASE 0x4E66B80ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_CORE_HBW_BASE 0x4E66C00ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_CORE_LBW_BASE 0x4E66D80ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_SPECIAL_BASE 0x4E66E80ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_HBW_RTR_IF1_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSFT2_HBW_RTR_IF1_ADDR_DEC_HBW_BASE 0x4E67000ull +#define SFT2_HBW_RTR_IF1_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT2_HBW_RTR_IF1_ADDR_DEC_HBW_SECTION 0x4000 +#define mmSFT2_HBW_RTR_IF1_ADDR_DEC_LBW_BASE 0x4E67400ull +#define SFT2_HBW_RTR_IF1_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT2_HBW_RTR_IF1_ADDR_DEC_LBW_SECTION 0xA800 +#define mmSFT2_HBW_RTR_IF1_ADDR_DEC_SPECIAL_BASE 0x4E67E80ull +#define SFT2_HBW_RTR_IF1_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_HBW_RTR_IF1_ADDR_DEC_SPECIAL_SECTION 0x1800 +#define mmSFT2_LBW_RTR_IF_RTR_CTRL_BASE 0x4E68000ull +#define SFT2_LBW_RTR_IF_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT2_LBW_RTR_IF_RTR_CTRL_SECTION 0xE800 +#define mmSFT2_LBW_RTR_IF_RTR_CTRL_SPECIAL_BASE 0x4E68E80ull +#define SFT2_LBW_RTR_IF_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_LBW_RTR_IF_RTR_CTRL_SPECIAL_SECTION 0x1800 +#define mmSFT2_LBW_RTR_IF_RTR_H3_BASE 0x4E69000ull +#define SFT2_LBW_RTR_IF_RTR_H3_MAX_OFFSET 0x1000 +#define SFT2_LBW_RTR_IF_RTR_H3_SECTION 0xE800 +#define mmSFT2_LBW_RTR_IF_RTR_H3_SPECIAL_BASE 0x4E69E80ull +#define SFT2_LBW_RTR_IF_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_LBW_RTR_IF_RTR_H3_SPECIAL_SECTION 0x1800 +#define mmSFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE 0x4E6A000ull +#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_BASE 0x4E6A200ull +#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE 0x4E6A400ull +#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_BASE 0x4E6A600ull +#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSFT2_LBW_RTR_IF_MSTR_IF_E2E_CRDT_BASE 0x4E6A800ull +#define SFT2_LBW_RTR_IF_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT2_LBW_RTR_IF_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSFT2_LBW_RTR_IF_MSTR_IF_AXUSER_BASE 0x4E6AA80ull +#define SFT2_LBW_RTR_IF_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT2_LBW_RTR_IF_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSFT2_LBW_RTR_IF_MSTR_IF_DBG_HBW_BASE 0x4E6AB00ull +#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSFT2_LBW_RTR_IF_MSTR_IF_DBG_LBW_BASE 0x4E6AB80ull +#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSFT2_LBW_RTR_IF_MSTR_IF_CORE_HBW_BASE 0x4E6AC00ull +#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSFT2_LBW_RTR_IF_MSTR_IF_CORE_LBW_BASE 0x4E6AD80ull +#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSFT2_LBW_RTR_IF_MSTR_IF_SPECIAL_BASE 0x4E6AE80ull +#define SFT2_LBW_RTR_IF_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_LBW_RTR_IF_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSFT2_LBW_RTR_IF_ADDR_DEC_HBW_BASE 0x4E6B000ull +#define SFT2_LBW_RTR_IF_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT2_LBW_RTR_IF_ADDR_DEC_HBW_SECTION 0x4000 +#define mmSFT2_LBW_RTR_IF_ADDR_DEC_LBW_BASE 0x4E6B400ull +#define SFT2_LBW_RTR_IF_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT2_LBW_RTR_IF_ADDR_DEC_LBW_SECTION 0xA800 +#define mmSFT2_LBW_RTR_IF_ADDR_DEC_SPECIAL_BASE 0x4E6BE80ull +#define SFT2_LBW_RTR_IF_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_LBW_RTR_IF_ADDR_DEC_SPECIAL_SECTION 0x1800 +#define mmSFT2_BASE 0x4E6C000ull +#define SFT2_MAX_OFFSET 0x1000 +#define SFT2_SECTION 0xE800 +#define mmSFT2_SPECIAL_BASE 0x4E6CE80ull +#define SFT2_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_SPECIAL_SECTION 0x3180 +#define mmSFT3_HBW_RTR_IF0_RTR_CTRL_BASE 0x4E70000ull +#define SFT3_HBW_RTR_IF0_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT3_HBW_RTR_IF0_RTR_CTRL_SECTION 0xE800 +#define mmSFT3_HBW_RTR_IF0_RTR_CTRL_SPECIAL_BASE 0x4E70E80ull +#define SFT3_HBW_RTR_IF0_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_HBW_RTR_IF0_RTR_CTRL_SPECIAL_SECTION 0x1800 +#define mmSFT3_HBW_RTR_IF0_RTR_H3_BASE 0x4E71000ull +#define SFT3_HBW_RTR_IF0_RTR_H3_MAX_OFFSET 0x1000 +#define SFT3_HBW_RTR_IF0_RTR_H3_SECTION 0xE800 +#define mmSFT3_HBW_RTR_IF0_RTR_H3_SPECIAL_BASE 0x4E71E80ull +#define SFT3_HBW_RTR_IF0_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_HBW_RTR_IF0_RTR_H3_SPECIAL_SECTION 0x1800 +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E72000ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E72200ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E72400ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E72600ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_BASE 0x4E72800ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT3_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_AXUSER_BASE 0x4E72A80ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT3_HBW_RTR_IF0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_DBG_HBW_BASE 0x4E72B00ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_DBG_LBW_BASE 0x4E72B80ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_CORE_HBW_BASE 0x4E72C00ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_CORE_LBW_BASE 0x4E72D80ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_SPECIAL_BASE 0x4E72E80ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_HBW_RTR_IF0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSFT3_HBW_RTR_IF0_ADDR_DEC_HBW_BASE 0x4E73000ull +#define SFT3_HBW_RTR_IF0_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT3_HBW_RTR_IF0_ADDR_DEC_HBW_SECTION 0x4000 +#define mmSFT3_HBW_RTR_IF0_ADDR_DEC_LBW_BASE 0x4E73400ull +#define SFT3_HBW_RTR_IF0_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT3_HBW_RTR_IF0_ADDR_DEC_LBW_SECTION 0xA800 +#define mmSFT3_HBW_RTR_IF0_ADDR_DEC_SPECIAL_BASE 0x4E73E80ull +#define SFT3_HBW_RTR_IF0_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_HBW_RTR_IF0_ADDR_DEC_SPECIAL_SECTION 0x1800 +#define mmSFT3_HBW_RTR_IF1_RTR_CTRL_BASE 0x4E74000ull +#define SFT3_HBW_RTR_IF1_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT3_HBW_RTR_IF1_RTR_CTRL_SECTION 0xE800 +#define mmSFT3_HBW_RTR_IF1_RTR_CTRL_SPECIAL_BASE 0x4E74E80ull +#define SFT3_HBW_RTR_IF1_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_HBW_RTR_IF1_RTR_CTRL_SPECIAL_SECTION 0x1800 +#define mmSFT3_HBW_RTR_IF1_RTR_H3_BASE 0x4E75000ull +#define SFT3_HBW_RTR_IF1_RTR_H3_MAX_OFFSET 0x1000 +#define SFT3_HBW_RTR_IF1_RTR_H3_SECTION 0xE800 +#define mmSFT3_HBW_RTR_IF1_RTR_H3_SPECIAL_BASE 0x4E75E80ull +#define SFT3_HBW_RTR_IF1_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_HBW_RTR_IF1_RTR_H3_SPECIAL_SECTION 0x1800 +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E76000ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E76200ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E76400ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E76600ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_BASE 0x4E76800ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT3_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_AXUSER_BASE 0x4E76A80ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT3_HBW_RTR_IF1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_DBG_HBW_BASE 0x4E76B00ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_DBG_LBW_BASE 0x4E76B80ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_CORE_HBW_BASE 0x4E76C00ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_CORE_LBW_BASE 0x4E76D80ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_SPECIAL_BASE 0x4E76E80ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_HBW_RTR_IF1_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSFT3_HBW_RTR_IF1_ADDR_DEC_HBW_BASE 0x4E77000ull +#define SFT3_HBW_RTR_IF1_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT3_HBW_RTR_IF1_ADDR_DEC_HBW_SECTION 0x4000 +#define mmSFT3_HBW_RTR_IF1_ADDR_DEC_LBW_BASE 0x4E77400ull +#define SFT3_HBW_RTR_IF1_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT3_HBW_RTR_IF1_ADDR_DEC_LBW_SECTION 0xA800 +#define mmSFT3_HBW_RTR_IF1_ADDR_DEC_SPECIAL_BASE 0x4E77E80ull +#define SFT3_HBW_RTR_IF1_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_HBW_RTR_IF1_ADDR_DEC_SPECIAL_SECTION 0x1800 +#define mmSFT3_LBW_RTR_IF_RTR_CTRL_BASE 0x4E78000ull +#define SFT3_LBW_RTR_IF_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT3_LBW_RTR_IF_RTR_CTRL_SECTION 0xE800 +#define mmSFT3_LBW_RTR_IF_RTR_CTRL_SPECIAL_BASE 0x4E78E80ull +#define SFT3_LBW_RTR_IF_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_LBW_RTR_IF_RTR_CTRL_SPECIAL_SECTION 0x1800 +#define mmSFT3_LBW_RTR_IF_RTR_H3_BASE 0x4E79000ull +#define SFT3_LBW_RTR_IF_RTR_H3_MAX_OFFSET 0x1000 +#define SFT3_LBW_RTR_IF_RTR_H3_SECTION 0xE800 +#define mmSFT3_LBW_RTR_IF_RTR_H3_SPECIAL_BASE 0x4E79E80ull +#define SFT3_LBW_RTR_IF_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_LBW_RTR_IF_RTR_H3_SPECIAL_SECTION 0x1800 +#define mmSFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE 0x4E7A000ull +#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmSFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_BASE 0x4E7A200ull +#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmSFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE 0x4E7A400ull +#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmSFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_BASE 0x4E7A600ull +#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmSFT3_LBW_RTR_IF_MSTR_IF_E2E_CRDT_BASE 0x4E7A800ull +#define SFT3_LBW_RTR_IF_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT3_LBW_RTR_IF_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmSFT3_LBW_RTR_IF_MSTR_IF_AXUSER_BASE 0x4E7AA80ull +#define SFT3_LBW_RTR_IF_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT3_LBW_RTR_IF_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmSFT3_LBW_RTR_IF_MSTR_IF_DBG_HBW_BASE 0x4E7AB00ull +#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmSFT3_LBW_RTR_IF_MSTR_IF_DBG_LBW_BASE 0x4E7AB80ull +#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmSFT3_LBW_RTR_IF_MSTR_IF_CORE_HBW_BASE 0x4E7AC00ull +#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmSFT3_LBW_RTR_IF_MSTR_IF_CORE_LBW_BASE 0x4E7AD80ull +#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmSFT3_LBW_RTR_IF_MSTR_IF_SPECIAL_BASE 0x4E7AE80ull +#define SFT3_LBW_RTR_IF_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_LBW_RTR_IF_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmSFT3_LBW_RTR_IF_ADDR_DEC_HBW_BASE 0x4E7B000ull +#define SFT3_LBW_RTR_IF_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT3_LBW_RTR_IF_ADDR_DEC_HBW_SECTION 0x4000 +#define mmSFT3_LBW_RTR_IF_ADDR_DEC_LBW_BASE 0x4E7B400ull +#define SFT3_LBW_RTR_IF_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT3_LBW_RTR_IF_ADDR_DEC_LBW_SECTION 0xA800 +#define mmSFT3_LBW_RTR_IF_ADDR_DEC_SPECIAL_BASE 0x4E7BE80ull +#define SFT3_LBW_RTR_IF_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_LBW_RTR_IF_ADDR_DEC_SPECIAL_SECTION 0x1800 +#define mmSFT3_BASE 0x4E7C000ull +#define SFT3_MAX_OFFSET 0x1000 +#define SFT3_SECTION 0xE800 +#define mmSFT3_SPECIAL_BASE 0x4E7CE80ull +#define SFT3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_SPECIAL_SECTION 0x4180 +#define mmARC_FARM_FARM_BASE 0x4E81000ull +#define ARC_FARM_FARM_MAX_OFFSET 0x1000 +#define ARC_FARM_FARM_SECTION 0xE800 +#define mmARC_FARM_FARM_SPECIAL_BASE 0x4E81E80ull +#define ARC_FARM_FARM_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_FARM_SPECIAL_SECTION 0x1800 +#define mmARC_FARM_FARM_MSTR_IF_RR_SHRD_HBW_BASE 0x4E82000ull +#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmARC_FARM_FARM_MSTR_IF_RR_PRVT_HBW_BASE 0x4E82200ull +#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmARC_FARM_FARM_MSTR_IF_RR_SHRD_LBW_BASE 0x4E82400ull +#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmARC_FARM_FARM_MSTR_IF_RR_PRVT_LBW_BASE 0x4E82600ull +#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmARC_FARM_FARM_MSTR_IF_E2E_CRDT_BASE 0x4E82800ull +#define ARC_FARM_FARM_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define ARC_FARM_FARM_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmARC_FARM_FARM_MSTR_IF_AXUSER_BASE 0x4E82A80ull +#define ARC_FARM_FARM_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define ARC_FARM_FARM_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmARC_FARM_FARM_MSTR_IF_DBG_HBW_BASE 0x4E82B00ull +#define ARC_FARM_FARM_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define ARC_FARM_FARM_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmARC_FARM_FARM_MSTR_IF_DBG_LBW_BASE 0x4E82B80ull +#define ARC_FARM_FARM_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define ARC_FARM_FARM_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmARC_FARM_FARM_MSTR_IF_CORE_HBW_BASE 0x4E82C00ull +#define ARC_FARM_FARM_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define ARC_FARM_FARM_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmARC_FARM_FARM_MSTR_IF_CORE_LBW_BASE 0x4E82D80ull +#define ARC_FARM_FARM_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define ARC_FARM_FARM_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmARC_FARM_FARM_MSTR_IF_SPECIAL_BASE 0x4E82E80ull +#define ARC_FARM_FARM_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_FARM_MSTR_IF_SPECIAL_SECTION 0x5180 +#define mmARC_FARM_ARC0_AUX_BASE 0x4E88000ull +#define ARC_FARM_ARC0_AUX_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC0_AUX_SECTION 0xE800 +#define mmARC_FARM_ARC0_AUX_SPECIAL_BASE 0x4E88E80ull +#define ARC_FARM_ARC0_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC0_AUX_SPECIAL_SECTION 0x1800 +#define mmARC_FARM_ARC0_DUP_ENG_BASE 0x4E89000ull +#define ARC_FARM_ARC0_DUP_ENG_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC0_DUP_ENG_SECTION 0x9000 +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_BASE 0x4E89900ull +#define ARC_FARM_ARC0_DUP_ENG_AXUSER_MAX_OFFSET 0x5000 +#define ARC_FARM_ARC0_DUP_ENG_AXUSER_SECTION 0x5800 +#define mmARC_FARM_ARC0_DUP_ENG_SPECIAL_BASE 0x4E89E80ull +#define ARC_FARM_ARC0_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC0_DUP_ENG_SPECIAL_SECTION 0x1180 +#define mmARC_FARM_KDMA_BASE 0x4E8B000ull +#define ARC_FARM_KDMA_MAX_OFFSET 0x1000 +#define ARC_FARM_KDMA_SECTION 0x8000 +#define mmARC_FARM_KDMA_CTX_AXUSER_BASE 0x4E8B800ull +#define ARC_FARM_KDMA_CTX_AXUSER_MAX_OFFSET 0x5000 +#define ARC_FARM_KDMA_CTX_AXUSER_SECTION 0x6000 +#define mmARC_FARM_KDMA_CTX_BASE 0x4E8B860ull +#define ARC_FARM_KDMA_CTX_MAX_OFFSET 0x9000 +#define ARC_FARM_KDMA_CTX_SECTION 0x5A00 +#define mmARC_FARM_KDMA_KDMA_CGM_BASE 0x4E8BE00ull +#define ARC_FARM_KDMA_KDMA_CGM_MAX_OFFSET 0xC000 +#define ARC_FARM_KDMA_KDMA_CGM_SECTION 0x8000 +#define mmARC_FARM_KDMA_SPECIAL_BASE 0x4E8BE80ull +#define ARC_FARM_KDMA_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_KDMA_SPECIAL_SECTION 0x1800 +#define mmARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_BASE 0x4E8C000ull +#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmARC_FARM_KDMA_MSTR_IF_RR_PRVT_HBW_BASE 0x4E8C200ull +#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmARC_FARM_KDMA_MSTR_IF_RR_SHRD_LBW_BASE 0x4E8C400ull +#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmARC_FARM_KDMA_MSTR_IF_RR_PRVT_LBW_BASE 0x4E8C600ull +#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmARC_FARM_KDMA_MSTR_IF_E2E_CRDT_BASE 0x4E8C800ull +#define ARC_FARM_KDMA_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define ARC_FARM_KDMA_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmARC_FARM_KDMA_MSTR_IF_AXUSER_BASE 0x4E8CA80ull +#define ARC_FARM_KDMA_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define ARC_FARM_KDMA_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmARC_FARM_KDMA_MSTR_IF_DBG_HBW_BASE 0x4E8CB00ull +#define ARC_FARM_KDMA_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define ARC_FARM_KDMA_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmARC_FARM_KDMA_MSTR_IF_DBG_LBW_BASE 0x4E8CB80ull +#define ARC_FARM_KDMA_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define ARC_FARM_KDMA_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmARC_FARM_KDMA_MSTR_IF_CORE_HBW_BASE 0x4E8CC00ull +#define ARC_FARM_KDMA_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define ARC_FARM_KDMA_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmARC_FARM_KDMA_MSTR_IF_CORE_LBW_BASE 0x4E8CD80ull +#define ARC_FARM_KDMA_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define ARC_FARM_KDMA_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmARC_FARM_KDMA_MSTR_IF_SPECIAL_BASE 0x4E8CE80ull +#define ARC_FARM_KDMA_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_KDMA_MSTR_IF_SPECIAL_SECTION 0x2180 +#define mmARC_FARM_ARC0_ACP_ENG_BASE 0x4E8F000ull +#define ARC_FARM_ARC0_ACP_ENG_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC0_ACP_ENG_SECTION 0xE800 +#define mmARC_FARM_ARC0_ACP_ENG_SPECIAL_BASE 0x4E8FE80ull +#define ARC_FARM_ARC0_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC0_ACP_ENG_SPECIAL_SECTION 0x1800 +#define mmARC_FARM_ARC0_DCCM0_BASE 0x4E90000ull +#define ARC_FARM_ARC0_DCCM0_MAX_OFFSET 0x4000 +#define ARC_FARM_ARC0_DCCM0_SECTION 0x8000 +#define mmARC_FARM_ARC0_DCCM1_BASE 0x4E98000ull +#define ARC_FARM_ARC0_DCCM1_MAX_OFFSET 0x4000 +#define ARC_FARM_ARC0_DCCM1_SECTION 0x10000 +#define mmARC_FARM_ARC1_AUX_BASE 0x4EA8000ull +#define ARC_FARM_ARC1_AUX_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC1_AUX_SECTION 0xE800 +#define mmARC_FARM_ARC1_AUX_SPECIAL_BASE 0x4EA8E80ull +#define ARC_FARM_ARC1_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC1_AUX_SPECIAL_SECTION 0x1800 +#define mmARC_FARM_ARC1_DUP_ENG_BASE 0x4EA9000ull +#define ARC_FARM_ARC1_DUP_ENG_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC1_DUP_ENG_SECTION 0x9000 +#define mmARC_FARM_ARC1_DUP_ENG_AXUSER_BASE 0x4EA9900ull +#define ARC_FARM_ARC1_DUP_ENG_AXUSER_MAX_OFFSET 0x5000 +#define ARC_FARM_ARC1_DUP_ENG_AXUSER_SECTION 0x5800 +#define mmARC_FARM_ARC1_DUP_ENG_SPECIAL_BASE 0x4EA9E80ull +#define ARC_FARM_ARC1_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC1_DUP_ENG_SPECIAL_SECTION 0x5180 +#define mmARC_FARM_ARC1_ACP_ENG_BASE 0x4EAF000ull +#define ARC_FARM_ARC1_ACP_ENG_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC1_ACP_ENG_SECTION 0xE800 +#define mmARC_FARM_ARC1_ACP_ENG_SPECIAL_BASE 0x4EAFE80ull +#define ARC_FARM_ARC1_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC1_ACP_ENG_SPECIAL_SECTION 0x1800 +#define mmARC_FARM_ARC1_DCCM0_BASE 0x4EB0000ull +#define ARC_FARM_ARC1_DCCM0_MAX_OFFSET 0x4000 +#define ARC_FARM_ARC1_DCCM0_SECTION 0x8000 +#define mmARC_FARM_ARC1_DCCM1_BASE 0x4EB8000ull +#define ARC_FARM_ARC1_DCCM1_MAX_OFFSET 0x4000 +#define ARC_FARM_ARC1_DCCM1_SECTION 0x10000 +#define mmARC_FARM_ARC2_AUX_BASE 0x4EC8000ull +#define ARC_FARM_ARC2_AUX_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC2_AUX_SECTION 0xE800 +#define mmARC_FARM_ARC2_AUX_SPECIAL_BASE 0x4EC8E80ull +#define ARC_FARM_ARC2_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC2_AUX_SPECIAL_SECTION 0x1800 +#define mmARC_FARM_ARC2_DUP_ENG_BASE 0x4EC9000ull +#define ARC_FARM_ARC2_DUP_ENG_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC2_DUP_ENG_SECTION 0x9000 +#define mmARC_FARM_ARC2_DUP_ENG_AXUSER_BASE 0x4EC9900ull +#define ARC_FARM_ARC2_DUP_ENG_AXUSER_MAX_OFFSET 0x5000 +#define ARC_FARM_ARC2_DUP_ENG_AXUSER_SECTION 0x5800 +#define mmARC_FARM_ARC2_DUP_ENG_SPECIAL_BASE 0x4EC9E80ull +#define ARC_FARM_ARC2_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC2_DUP_ENG_SPECIAL_SECTION 0x5180 +#define mmARC_FARM_ARC2_ACP_ENG_BASE 0x4ECF000ull +#define ARC_FARM_ARC2_ACP_ENG_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC2_ACP_ENG_SECTION 0xE800 +#define mmARC_FARM_ARC2_ACP_ENG_SPECIAL_BASE 0x4ECFE80ull +#define ARC_FARM_ARC2_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC2_ACP_ENG_SPECIAL_SECTION 0x1800 +#define mmARC_FARM_ARC2_DCCM0_BASE 0x4ED0000ull +#define ARC_FARM_ARC2_DCCM0_MAX_OFFSET 0x4000 +#define ARC_FARM_ARC2_DCCM0_SECTION 0x8000 +#define mmARC_FARM_ARC2_DCCM1_BASE 0x4ED8000ull +#define ARC_FARM_ARC2_DCCM1_MAX_OFFSET 0x4000 +#define ARC_FARM_ARC2_DCCM1_SECTION 0x10000 +#define mmARC_FARM_ARC3_AUX_BASE 0x4EE8000ull +#define ARC_FARM_ARC3_AUX_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC3_AUX_SECTION 0xE800 +#define mmARC_FARM_ARC3_AUX_SPECIAL_BASE 0x4EE8E80ull +#define ARC_FARM_ARC3_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC3_AUX_SPECIAL_SECTION 0x1800 +#define mmARC_FARM_ARC3_DUP_ENG_BASE 0x4EE9000ull +#define ARC_FARM_ARC3_DUP_ENG_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC3_DUP_ENG_SECTION 0x9000 +#define mmARC_FARM_ARC3_DUP_ENG_AXUSER_BASE 0x4EE9900ull +#define ARC_FARM_ARC3_DUP_ENG_AXUSER_MAX_OFFSET 0x5000 +#define ARC_FARM_ARC3_DUP_ENG_AXUSER_SECTION 0x5800 +#define mmARC_FARM_ARC3_DUP_ENG_SPECIAL_BASE 0x4EE9E80ull +#define ARC_FARM_ARC3_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC3_DUP_ENG_SPECIAL_SECTION 0x5180 +#define mmARC_FARM_ARC3_ACP_ENG_BASE 0x4EEF000ull +#define ARC_FARM_ARC3_ACP_ENG_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC3_ACP_ENG_SECTION 0xE800 +#define mmARC_FARM_ARC3_ACP_ENG_SPECIAL_BASE 0x4EEFE80ull +#define ARC_FARM_ARC3_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC3_ACP_ENG_SPECIAL_SECTION 0x1800 +#define mmARC_FARM_ARC3_DCCM0_BASE 0x4EF0000ull +#define ARC_FARM_ARC3_DCCM0_MAX_OFFSET 0x4000 +#define ARC_FARM_ARC3_DCCM0_SECTION 0x8000 +#define mmARC_FARM_ARC3_DCCM1_BASE 0x4EF8000ull +#define ARC_FARM_ARC3_DCCM1_MAX_OFFSET 0x4000 +#define ARC_FARM_ARC3_DCCM1_SECTION 0x8000 +#define mmPCIE_DEC0_CMD_BASE 0x4F00000ull +#define PCIE_DEC0_CMD_MAX_OFFSET 0x1100 +#define PCIE_DEC0_CMD_SECTION 0x1000 +#define mmPCIE_DEC0_VSI_BASE 0x4F01000ull +#define PCIE_DEC0_VSI_MAX_OFFSET 0x6FC0 +#define PCIE_DEC0_VSI_SECTION 0x1000 +#define mmPCIE_DEC0_L2C_BASE 0x4F02000ull +#define PCIE_DEC0_L2C_MAX_OFFSET 0x39C0 +#define PCIE_DEC0_L2C_SECTION 0x1000 +#define mmPCIE_VDEC0_BRDG_CTRL_BASE 0x4F03000ull +#define PCIE_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_BRDG_CTRL_SECTION 0x8000 +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x4F03800ull +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x4F03900ull +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x4F03A00ull +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x4F03B00ull +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x4F03C00ull +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 +#define mmPCIE_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x4F03E80ull +#define PCIE_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800 +#define mmPCIE_VDEC0_CTRL_BASE 0x4F04000ull +#define PCIE_VDEC0_CTRL_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_CTRL_SECTION 0xE800 +#define mmPCIE_VDEC0_CTRL_SPECIAL_BASE 0x4F04E80ull +#define PCIE_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_VDEC0_CTRL_SPECIAL_SECTION 0x1800 +#define mmPCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x4F05000ull +#define PCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmPCIE_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x4F05200ull +#define PCIE_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PCIE_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmPCIE_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x4F05400ull +#define PCIE_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PCIE_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmPCIE_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x4F05600ull +#define PCIE_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PCIE_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmPCIE_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x4F05800ull +#define PCIE_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PCIE_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmPCIE_VDEC0_MSTR_IF_AXUSER_BASE 0x4F05A80ull +#define PCIE_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PCIE_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmPCIE_VDEC0_MSTR_IF_DBG_HBW_BASE 0x4F05B00ull +#define PCIE_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PCIE_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmPCIE_VDEC0_MSTR_IF_DBG_LBW_BASE 0x4F05B80ull +#define PCIE_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PCIE_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmPCIE_VDEC0_MSTR_IF_CORE_HBW_BASE 0x4F05C00ull +#define PCIE_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PCIE_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmPCIE_VDEC0_MSTR_IF_CORE_LBW_BASE 0x4F05D80ull +#define PCIE_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PCIE_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmPCIE_VDEC0_MSTR_IF_SPECIAL_BASE 0x4F05E80ull +#define PCIE_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180 +#define mmPCIE_DEC1_CMD_BASE 0x4F10000ull +#define PCIE_DEC1_CMD_MAX_OFFSET 0x1100 +#define PCIE_DEC1_CMD_SECTION 0x1000 +#define mmPCIE_DEC1_VSI_BASE 0x4F11000ull +#define PCIE_DEC1_VSI_MAX_OFFSET 0x6FC0 +#define PCIE_DEC1_VSI_SECTION 0x1000 +#define mmPCIE_DEC1_L2C_BASE 0x4F12000ull +#define PCIE_DEC1_L2C_MAX_OFFSET 0x39C0 +#define PCIE_DEC1_L2C_SECTION 0x1000 +#define mmPCIE_VDEC1_BRDG_CTRL_BASE 0x4F13000ull +#define PCIE_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_BRDG_CTRL_SECTION 0x8000 +#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x4F13800ull +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 +#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x4F13900ull +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 +#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x4F13A00ull +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 +#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x4F13B00ull +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 +#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x4F13C00ull +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 +#define mmPCIE_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x4F13E80ull +#define PCIE_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800 +#define mmPCIE_VDEC1_CTRL_BASE 0x4F14000ull +#define PCIE_VDEC1_CTRL_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_CTRL_SECTION 0xE800 +#define mmPCIE_VDEC1_CTRL_SPECIAL_BASE 0x4F14E80ull +#define PCIE_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_VDEC1_CTRL_SPECIAL_SECTION 0x1800 +#define mmPCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x4F15000ull +#define PCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmPCIE_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x4F15200ull +#define PCIE_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PCIE_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmPCIE_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x4F15400ull +#define PCIE_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PCIE_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmPCIE_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x4F15600ull +#define PCIE_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PCIE_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmPCIE_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x4F15800ull +#define PCIE_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PCIE_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmPCIE_VDEC1_MSTR_IF_AXUSER_BASE 0x4F15A80ull +#define PCIE_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PCIE_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmPCIE_VDEC1_MSTR_IF_DBG_HBW_BASE 0x4F15B00ull +#define PCIE_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PCIE_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmPCIE_VDEC1_MSTR_IF_DBG_LBW_BASE 0x4F15B80ull +#define PCIE_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PCIE_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmPCIE_VDEC1_MSTR_IF_CORE_HBW_BASE 0x4F15C00ull +#define PCIE_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PCIE_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmPCIE_VDEC1_MSTR_IF_CORE_LBW_BASE 0x4F15D80ull +#define PCIE_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PCIE_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmPCIE_VDEC1_MSTR_IF_SPECIAL_BASE 0x4F15E80ull +#define PCIE_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_VDEC1_MSTR_IF_SPECIAL_SECTION 0x2A180 +#define mmDCORE0_XFT_BASE 0x4F40000ull +#define DCORE0_XFT_MAX_OFFSET 0x1000 +#define DCORE0_XFT_SECTION 0xE800 +#define mmDCORE0_XFT_SPECIAL_BASE 0x4F40E80ull +#define DCORE0_XFT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_XFT_SPECIAL_SECTION 0x1800 +#define mmDCORE0_HBM_PLL_CTRL_BASE 0x4F41000ull +#define DCORE0_HBM_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE0_HBM_PLL_CTRL_SECTION 0x3600 +#define mmDCORE0_HBM_PLL_ASIF_SLV_BASE 0x4F41360ull +#define DCORE0_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE0_HBM_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE0_HBM_PLL_DIV_0_RLX_BASE 0x4F41400ull +#define DCORE0_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE0_HBM_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE0_HBM_PLL_DIV_1_RLX_BASE 0x4F41800ull +#define DCORE0_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE0_HBM_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE0_HBM_PLL_DIV_2_RLX_BASE 0x4F41A00ull +#define DCORE0_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE0_HBM_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE0_HBM_PLL_DIV_3_RLX_BASE 0x4F41C00ull +#define DCORE0_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE0_HBM_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE0_HBM_PLL_SPECIAL_BASE 0x4F41E80ull +#define DCORE0_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HBM_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_TPC_PLL_CTRL_BASE 0x4F42000ull +#define DCORE0_TPC_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE0_TPC_PLL_CTRL_SECTION 0x3600 +#define mmDCORE0_TPC_PLL_ASIF_SLV_BASE 0x4F42360ull +#define DCORE0_TPC_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE0_TPC_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE0_TPC_PLL_DIV_0_RLX_BASE 0x4F42400ull +#define DCORE0_TPC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE0_TPC_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE0_TPC_PLL_DIV_1_RLX_BASE 0x4F42800ull +#define DCORE0_TPC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE0_TPC_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE0_TPC_PLL_DIV_2_RLX_BASE 0x4F42A00ull +#define DCORE0_TPC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE0_TPC_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE0_TPC_PLL_DIV_3_RLX_BASE 0x4F42C00ull +#define DCORE0_TPC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE0_TPC_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE0_TPC_PLL_SPECIAL_BASE 0x4F42E80ull +#define DCORE0_TPC_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE0_PCI_PLL_CTRL_BASE 0x4F43000ull +#define DCORE0_PCI_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE0_PCI_PLL_CTRL_SECTION 0x3600 +#define mmDCORE0_PCI_PLL_ASIF_SLV_BASE 0x4F43360ull +#define DCORE0_PCI_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE0_PCI_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE0_PCI_PLL_DIV_0_RLX_BASE 0x4F43400ull +#define DCORE0_PCI_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE0_PCI_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE0_PCI_PLL_DIV_1_RLX_BASE 0x4F43800ull +#define DCORE0_PCI_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE0_PCI_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE0_PCI_PLL_DIV_2_RLX_BASE 0x4F43A00ull +#define DCORE0_PCI_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE0_PCI_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE0_PCI_PLL_DIV_3_RLX_BASE 0x4F43C00ull +#define DCORE0_PCI_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE0_PCI_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE0_PCI_PLL_SPECIAL_BASE 0x4F43E80ull +#define DCORE0_PCI_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_PCI_PLL_SPECIAL_SECTION 0x1180 +#define mmDCORE0_TSTDVS_BASE 0x4F45000ull +#define DCORE0_TSTDVS_MAX_OFFSET 0x7800 +#define DCORE0_TSTDVS_SECTION 0x1000 +#define mmDCORE0_TS_WRAP_BASE 0x4F46000ull +#define DCORE0_TS_WRAP_MAX_OFFSET 0x2380 +#define DCORE0_TS_WRAP_SECTION 0x2000 +#define mmDCORE0_TS_WRAP_ASIF_SLV_BASE 0x4F46200ull +#define DCORE0_TS_WRAP_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE0_TS_WRAP_ASIF_SLV_SECTION 0x9E00 +#define mmDCORE1_XFT_BASE 0x4F50000ull +#define DCORE1_XFT_MAX_OFFSET 0x1000 +#define DCORE1_XFT_SECTION 0xE800 +#define mmDCORE1_XFT_SPECIAL_BASE 0x4F50E80ull +#define DCORE1_XFT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_XFT_SPECIAL_SECTION 0x1800 +#define mmDCORE1_HBM_PLL_CTRL_BASE 0x4F51000ull +#define DCORE1_HBM_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE1_HBM_PLL_CTRL_SECTION 0x3600 +#define mmDCORE1_HBM_PLL_ASIF_SLV_BASE 0x4F51360ull +#define DCORE1_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_HBM_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE1_HBM_PLL_DIV_0_RLX_BASE 0x4F51400ull +#define DCORE1_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE1_HBM_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE1_HBM_PLL_DIV_1_RLX_BASE 0x4F51800ull +#define DCORE1_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE1_HBM_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE1_HBM_PLL_DIV_2_RLX_BASE 0x4F51A00ull +#define DCORE1_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE1_HBM_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE1_HBM_PLL_DIV_3_RLX_BASE 0x4F51C00ull +#define DCORE1_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE1_HBM_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE1_HBM_PLL_SPECIAL_BASE 0x4F51E80ull +#define DCORE1_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HBM_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_TPC_PLL_CTRL_BASE 0x4F52000ull +#define DCORE1_TPC_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE1_TPC_PLL_CTRL_SECTION 0x3600 +#define mmDCORE1_TPC_PLL_ASIF_SLV_BASE 0x4F52360ull +#define DCORE1_TPC_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_TPC_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE1_TPC_PLL_DIV_0_RLX_BASE 0x4F52400ull +#define DCORE1_TPC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE1_TPC_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE1_TPC_PLL_DIV_1_RLX_BASE 0x4F52800ull +#define DCORE1_TPC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE1_TPC_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE1_TPC_PLL_DIV_2_RLX_BASE 0x4F52A00ull +#define DCORE1_TPC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE1_TPC_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE1_TPC_PLL_DIV_3_RLX_BASE 0x4F52C00ull +#define DCORE1_TPC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE1_TPC_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE1_TPC_PLL_SPECIAL_BASE 0x4F52E80ull +#define DCORE1_TPC_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE1_NIC_PLL_CTRL_BASE 0x4F53000ull +#define DCORE1_NIC_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE1_NIC_PLL_CTRL_SECTION 0x3600 +#define mmDCORE1_NIC_PLL_ASIF_SLV_BASE 0x4F53360ull +#define DCORE1_NIC_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_NIC_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE1_NIC_PLL_DIV_0_RLX_BASE 0x4F53400ull +#define DCORE1_NIC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE1_NIC_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE1_NIC_PLL_DIV_1_RLX_BASE 0x4F53800ull +#define DCORE1_NIC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE1_NIC_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE1_NIC_PLL_DIV_2_RLX_BASE 0x4F53A00ull +#define DCORE1_NIC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE1_NIC_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE1_NIC_PLL_DIV_3_RLX_BASE 0x4F53C00ull +#define DCORE1_NIC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE1_NIC_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE1_NIC_PLL_SPECIAL_BASE 0x4F53E80ull +#define DCORE1_NIC_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_NIC_PLL_SPECIAL_SECTION 0x1180 +#define mmDCORE1_TSTDVS_BASE 0x4F55000ull +#define DCORE1_TSTDVS_MAX_OFFSET 0x7800 +#define DCORE1_TSTDVS_SECTION 0x1000 +#define mmDCORE1_TS_WRAP_BASE 0x4F56000ull +#define DCORE1_TS_WRAP_MAX_OFFSET 0x2380 +#define DCORE1_TS_WRAP_SECTION 0x2000 +#define mmDCORE1_TS_WRAP_ASIF_SLV_BASE 0x4F56200ull +#define DCORE1_TS_WRAP_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_TS_WRAP_ASIF_SLV_SECTION 0x9E00 +#define mmDCORE2_XFT_BASE 0x4F60000ull +#define DCORE2_XFT_MAX_OFFSET 0x1000 +#define DCORE2_XFT_SECTION 0xE800 +#define mmDCORE2_XFT_SPECIAL_BASE 0x4F60E80ull +#define DCORE2_XFT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_XFT_SPECIAL_SECTION 0x1800 +#define mmDCORE2_HBM_PLL_CTRL_BASE 0x4F61000ull +#define DCORE2_HBM_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE2_HBM_PLL_CTRL_SECTION 0x3600 +#define mmDCORE2_HBM_PLL_ASIF_SLV_BASE 0x4F61360ull +#define DCORE2_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE2_HBM_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE2_HBM_PLL_DIV_0_RLX_BASE 0x4F61400ull +#define DCORE2_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE2_HBM_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE2_HBM_PLL_DIV_1_RLX_BASE 0x4F61800ull +#define DCORE2_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE2_HBM_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE2_HBM_PLL_DIV_2_RLX_BASE 0x4F61A00ull +#define DCORE2_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE2_HBM_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE2_HBM_PLL_DIV_3_RLX_BASE 0x4F61C00ull +#define DCORE2_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE2_HBM_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE2_HBM_PLL_SPECIAL_BASE 0x4F61E80ull +#define DCORE2_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HBM_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE2_TPC_PLL_CTRL_BASE 0x4F62000ull +#define DCORE2_TPC_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE2_TPC_PLL_CTRL_SECTION 0x3600 +#define mmDCORE2_TPC_PLL_ASIF_SLV_BASE 0x4F62360ull +#define DCORE2_TPC_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE2_TPC_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE2_TPC_PLL_DIV_0_RLX_BASE 0x4F62400ull +#define DCORE2_TPC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE2_TPC_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE2_TPC_PLL_DIV_1_RLX_BASE 0x4F62800ull +#define DCORE2_TPC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE2_TPC_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE2_TPC_PLL_DIV_2_RLX_BASE 0x4F62A00ull +#define DCORE2_TPC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE2_TPC_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE2_TPC_PLL_DIV_3_RLX_BASE 0x4F62C00ull +#define DCORE2_TPC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE2_TPC_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE2_TPC_PLL_SPECIAL_BASE 0x4F62E80ull +#define DCORE2_TPC_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC_PLL_SPECIAL_SECTION 0x2180 +#define mmDCORE2_TSTDVS_BASE 0x4F65000ull +#define DCORE2_TSTDVS_MAX_OFFSET 0x7800 +#define DCORE2_TSTDVS_SECTION 0x1000 +#define mmDCORE2_TS_WRAP_BASE 0x4F66000ull +#define DCORE2_TS_WRAP_MAX_OFFSET 0x2380 +#define DCORE2_TS_WRAP_SECTION 0x2000 +#define mmDCORE2_TS_WRAP_ASIF_SLV_BASE 0x4F66200ull +#define DCORE2_TS_WRAP_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE2_TS_WRAP_ASIF_SLV_SECTION 0x9E00 +#define mmDCORE3_XFT_BASE 0x4F70000ull +#define DCORE3_XFT_MAX_OFFSET 0x1000 +#define DCORE3_XFT_SECTION 0xE800 +#define mmDCORE3_XFT_SPECIAL_BASE 0x4F70E80ull +#define DCORE3_XFT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_XFT_SPECIAL_SECTION 0x1800 +#define mmDCORE3_HBM_PLL_CTRL_BASE 0x4F71000ull +#define DCORE3_HBM_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE3_HBM_PLL_CTRL_SECTION 0x3600 +#define mmDCORE3_HBM_PLL_ASIF_SLV_BASE 0x4F71360ull +#define DCORE3_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE3_HBM_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE3_HBM_PLL_DIV_0_RLX_BASE 0x4F71400ull +#define DCORE3_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE3_HBM_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE3_HBM_PLL_DIV_1_RLX_BASE 0x4F71800ull +#define DCORE3_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE3_HBM_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE3_HBM_PLL_DIV_2_RLX_BASE 0x4F71A00ull +#define DCORE3_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE3_HBM_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE3_HBM_PLL_DIV_3_RLX_BASE 0x4F71C00ull +#define DCORE3_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE3_HBM_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE3_HBM_PLL_SPECIAL_BASE 0x4F71E80ull +#define DCORE3_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HBM_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_TPC_PLL_CTRL_BASE 0x4F72000ull +#define DCORE3_TPC_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE3_TPC_PLL_CTRL_SECTION 0x3600 +#define mmDCORE3_TPC_PLL_ASIF_SLV_BASE 0x4F72360ull +#define DCORE3_TPC_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE3_TPC_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE3_TPC_PLL_DIV_0_RLX_BASE 0x4F72400ull +#define DCORE3_TPC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE3_TPC_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE3_TPC_PLL_DIV_1_RLX_BASE 0x4F72800ull +#define DCORE3_TPC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE3_TPC_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE3_TPC_PLL_DIV_2_RLX_BASE 0x4F72A00ull +#define DCORE3_TPC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE3_TPC_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE3_TPC_PLL_DIV_3_RLX_BASE 0x4F72C00ull +#define DCORE3_TPC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE3_TPC_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE3_TPC_PLL_SPECIAL_BASE 0x4F72E80ull +#define DCORE3_TPC_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC_PLL_SPECIAL_SECTION 0x1800 +#define mmDCORE3_NIC_PLL_CTRL_BASE 0x4F73000ull +#define DCORE3_NIC_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE3_NIC_PLL_CTRL_SECTION 0x3600 +#define mmDCORE3_NIC_PLL_ASIF_SLV_BASE 0x4F73360ull +#define DCORE3_NIC_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE3_NIC_PLL_ASIF_SLV_SECTION 0xA000 +#define mmDCORE3_NIC_PLL_DIV_0_RLX_BASE 0x4F73400ull +#define DCORE3_NIC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE3_NIC_PLL_DIV_0_RLX_SECTION 0x4000 +#define mmDCORE3_NIC_PLL_DIV_1_RLX_BASE 0x4F73800ull +#define DCORE3_NIC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE3_NIC_PLL_DIV_1_RLX_SECTION 0x2000 +#define mmDCORE3_NIC_PLL_DIV_2_RLX_BASE 0x4F73A00ull +#define DCORE3_NIC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE3_NIC_PLL_DIV_2_RLX_SECTION 0x2000 +#define mmDCORE3_NIC_PLL_DIV_3_RLX_BASE 0x4F73C00ull +#define DCORE3_NIC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE3_NIC_PLL_DIV_3_RLX_SECTION 0x2800 +#define mmDCORE3_NIC_PLL_SPECIAL_BASE 0x4F73E80ull +#define DCORE3_NIC_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_NIC_PLL_SPECIAL_SECTION 0x1180 +#define mmDCORE3_TSTDVS_BASE 0x4F75000ull +#define DCORE3_TSTDVS_MAX_OFFSET 0x7800 +#define DCORE3_TSTDVS_SECTION 0x1000 +#define mmDCORE3_TS_WRAP_BASE 0x4F76000ull +#define DCORE3_TS_WRAP_MAX_OFFSET 0x2380 +#define DCORE3_TS_WRAP_SECTION 0x2000 +#define mmDCORE3_TS_WRAP_ASIF_SLV_BASE 0x4F76200ull +#define DCORE3_TS_WRAP_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE3_TS_WRAP_ASIF_SLV_SECTION 0x9E00 +#define mmPCIE_PMA_2_BASE 0x4F80000ull +#define PCIE_PMA_2_MAX_OFFSET 0x40000 +#define PCIE_PMA_2_SECTION 0x40000 +#define mmPCIE_PMA_3_BASE 0x4FC0000ull +#define PCIE_PMA_3_MAX_OFFSET 0x40000 +#define PCIE_PMA_3_SECTION 0x40000 +#define mmHBM0_MC0_BASE 0x5000000ull +#define HBM0_MC0_MAX_OFFSET 0x1000 +#define HBM0_MC0_SECTION 0xE800 +#define mmHBM0_MC0_SPECIAL_BASE 0x5000E80ull +#define HBM0_MC0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC0BIST0_BASE 0x5001000ull +#define HBM0_MC0BIST0_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST0_SECTION 0xE800 +#define mmHBM0_MC0BIST0_SPECIAL_BASE 0x5001E80ull +#define HBM0_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST0_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC0BIST1_BASE 0x5002000ull +#define HBM0_MC0BIST1_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST1_SECTION 0xE800 +#define mmHBM0_MC0BIST1_SPECIAL_BASE 0x5002E80ull +#define HBM0_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST1_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC0BIST2_BASE 0x5003000ull +#define HBM0_MC0BIST2_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST2_SECTION 0xE800 +#define mmHBM0_MC0BIST2_SPECIAL_BASE 0x5003E80ull +#define HBM0_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST2_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC0BIST3_BASE 0x5004000ull +#define HBM0_MC0BIST3_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST3_SECTION 0xE800 +#define mmHBM0_MC0BIST3_SPECIAL_BASE 0x5004E80ull +#define HBM0_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST3_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC0BIST4_BASE 0x5005000ull +#define HBM0_MC0BIST4_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST4_SECTION 0xE800 +#define mmHBM0_MC0BIST4_SPECIAL_BASE 0x5005E80ull +#define HBM0_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST4_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC0BIST5_BASE 0x5006000ull +#define HBM0_MC0BIST5_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST5_SECTION 0xE800 +#define mmHBM0_MC0BIST5_SPECIAL_BASE 0x5006E80ull +#define HBM0_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST5_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC0BIST6_BASE 0x5007000ull +#define HBM0_MC0BIST6_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST6_SECTION 0xE800 +#define mmHBM0_MC0BIST6_SPECIAL_BASE 0x5007E80ull +#define HBM0_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST6_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC0BIST7_BASE 0x5008000ull +#define HBM0_MC0BIST7_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST7_SECTION 0xE800 +#define mmHBM0_MC0BIST7_SPECIAL_BASE 0x5008E80ull +#define HBM0_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST7_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC0BIST8_MEM_BASE 0x5009000ull +#define HBM0_MC0BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST8_MEM_SECTION 0xE800 +#define mmHBM0_MC0BIST8_MEM_SPECIAL_BASE 0x5009E80ull +#define HBM0_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST8_MEM_SPECIAL_SECTION 0x16180 +#define mmHBM0_MC1_BASE 0x5020000ull +#define HBM0_MC1_MAX_OFFSET 0x1000 +#define HBM0_MC1_SECTION 0xE800 +#define mmHBM0_MC1_SPECIAL_BASE 0x5020E80ull +#define HBM0_MC1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC1BIST0_BASE 0x5021000ull +#define HBM0_MC1BIST0_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST0_SECTION 0xE800 +#define mmHBM0_MC1BIST0_SPECIAL_BASE 0x5021E80ull +#define HBM0_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST0_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC1BIST1_BASE 0x5022000ull +#define HBM0_MC1BIST1_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST1_SECTION 0xE800 +#define mmHBM0_MC1BIST1_SPECIAL_BASE 0x5022E80ull +#define HBM0_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST1_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC1BIST2_BASE 0x5023000ull +#define HBM0_MC1BIST2_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST2_SECTION 0xE800 +#define mmHBM0_MC1BIST2_SPECIAL_BASE 0x5023E80ull +#define HBM0_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST2_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC1BIST3_BASE 0x5024000ull +#define HBM0_MC1BIST3_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST3_SECTION 0xE800 +#define mmHBM0_MC1BIST3_SPECIAL_BASE 0x5024E80ull +#define HBM0_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST3_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC1BIST4_BASE 0x5025000ull +#define HBM0_MC1BIST4_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST4_SECTION 0xE800 +#define mmHBM0_MC1BIST4_SPECIAL_BASE 0x5025E80ull +#define HBM0_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST4_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC1BIST5_BASE 0x5026000ull +#define HBM0_MC1BIST5_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST5_SECTION 0xE800 +#define mmHBM0_MC1BIST5_SPECIAL_BASE 0x5026E80ull +#define HBM0_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST5_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC1BIST6_BASE 0x5027000ull +#define HBM0_MC1BIST6_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST6_SECTION 0xE800 +#define mmHBM0_MC1BIST6_SPECIAL_BASE 0x5027E80ull +#define HBM0_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST6_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC1BIST7_BASE 0x5028000ull +#define HBM0_MC1BIST7_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST7_SECTION 0xE800 +#define mmHBM0_MC1BIST7_SPECIAL_BASE 0x5028E80ull +#define HBM0_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST7_SPECIAL_SECTION 0x1800 +#define mmHBM0_MC1BIST8_MEM_BASE 0x5029000ull +#define HBM0_MC1BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST8_MEM_SECTION 0xE800 +#define mmHBM0_MC1BIST8_MEM_SPECIAL_BASE 0x5029E80ull +#define HBM0_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST8_MEM_SPECIAL_SECTION 0x16180 +#define mmHBM0_PHY_BASE 0x5040000ull +#define HBM0_PHY_MAX_OFFSET 0x4000 +#define HBM0_PHY_SECTION 0x40000 +#define mmHBM1_MC0_BASE 0x5080000ull +#define HBM1_MC0_MAX_OFFSET 0x1000 +#define HBM1_MC0_SECTION 0xE800 +#define mmHBM1_MC0_SPECIAL_BASE 0x5080E80ull +#define HBM1_MC0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC0BIST0_BASE 0x5081000ull +#define HBM1_MC0BIST0_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST0_SECTION 0xE800 +#define mmHBM1_MC0BIST0_SPECIAL_BASE 0x5081E80ull +#define HBM1_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST0_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC0BIST1_BASE 0x5082000ull +#define HBM1_MC0BIST1_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST1_SECTION 0xE800 +#define mmHBM1_MC0BIST1_SPECIAL_BASE 0x5082E80ull +#define HBM1_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST1_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC0BIST2_BASE 0x5083000ull +#define HBM1_MC0BIST2_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST2_SECTION 0xE800 +#define mmHBM1_MC0BIST2_SPECIAL_BASE 0x5083E80ull +#define HBM1_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST2_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC0BIST3_BASE 0x5084000ull +#define HBM1_MC0BIST3_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST3_SECTION 0xE800 +#define mmHBM1_MC0BIST3_SPECIAL_BASE 0x5084E80ull +#define HBM1_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST3_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC0BIST4_BASE 0x5085000ull +#define HBM1_MC0BIST4_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST4_SECTION 0xE800 +#define mmHBM1_MC0BIST4_SPECIAL_BASE 0x5085E80ull +#define HBM1_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST4_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC0BIST5_BASE 0x5086000ull +#define HBM1_MC0BIST5_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST5_SECTION 0xE800 +#define mmHBM1_MC0BIST5_SPECIAL_BASE 0x5086E80ull +#define HBM1_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST5_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC0BIST6_BASE 0x5087000ull +#define HBM1_MC0BIST6_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST6_SECTION 0xE800 +#define mmHBM1_MC0BIST6_SPECIAL_BASE 0x5087E80ull +#define HBM1_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST6_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC0BIST7_BASE 0x5088000ull +#define HBM1_MC0BIST7_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST7_SECTION 0xE800 +#define mmHBM1_MC0BIST7_SPECIAL_BASE 0x5088E80ull +#define HBM1_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST7_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC0BIST8_MEM_BASE 0x5089000ull +#define HBM1_MC0BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST8_MEM_SECTION 0xE800 +#define mmHBM1_MC0BIST8_MEM_SPECIAL_BASE 0x5089E80ull +#define HBM1_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST8_MEM_SPECIAL_SECTION 0x16180 +#define mmHBM1_MC1_BASE 0x50A0000ull +#define HBM1_MC1_MAX_OFFSET 0x1000 +#define HBM1_MC1_SECTION 0xE800 +#define mmHBM1_MC1_SPECIAL_BASE 0x50A0E80ull +#define HBM1_MC1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC1BIST0_BASE 0x50A1000ull +#define HBM1_MC1BIST0_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST0_SECTION 0xE800 +#define mmHBM1_MC1BIST0_SPECIAL_BASE 0x50A1E80ull +#define HBM1_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST0_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC1BIST1_BASE 0x50A2000ull +#define HBM1_MC1BIST1_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST1_SECTION 0xE800 +#define mmHBM1_MC1BIST1_SPECIAL_BASE 0x50A2E80ull +#define HBM1_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST1_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC1BIST2_BASE 0x50A3000ull +#define HBM1_MC1BIST2_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST2_SECTION 0xE800 +#define mmHBM1_MC1BIST2_SPECIAL_BASE 0x50A3E80ull +#define HBM1_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST2_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC1BIST3_BASE 0x50A4000ull +#define HBM1_MC1BIST3_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST3_SECTION 0xE800 +#define mmHBM1_MC1BIST3_SPECIAL_BASE 0x50A4E80ull +#define HBM1_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST3_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC1BIST4_BASE 0x50A5000ull +#define HBM1_MC1BIST4_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST4_SECTION 0xE800 +#define mmHBM1_MC1BIST4_SPECIAL_BASE 0x50A5E80ull +#define HBM1_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST4_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC1BIST5_BASE 0x50A6000ull +#define HBM1_MC1BIST5_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST5_SECTION 0xE800 +#define mmHBM1_MC1BIST5_SPECIAL_BASE 0x50A6E80ull +#define HBM1_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST5_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC1BIST6_BASE 0x50A7000ull +#define HBM1_MC1BIST6_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST6_SECTION 0xE800 +#define mmHBM1_MC1BIST6_SPECIAL_BASE 0x50A7E80ull +#define HBM1_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST6_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC1BIST7_BASE 0x50A8000ull +#define HBM1_MC1BIST7_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST7_SECTION 0xE800 +#define mmHBM1_MC1BIST7_SPECIAL_BASE 0x50A8E80ull +#define HBM1_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST7_SPECIAL_SECTION 0x1800 +#define mmHBM1_MC1BIST8_MEM_BASE 0x50A9000ull +#define HBM1_MC1BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST8_MEM_SECTION 0xE800 +#define mmHBM1_MC1BIST8_MEM_SPECIAL_BASE 0x50A9E80ull +#define HBM1_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST8_MEM_SPECIAL_SECTION 0x16180 +#define mmHBM1_PHY_BASE 0x50C0000ull +#define HBM1_PHY_MAX_OFFSET 0x4000 +#define HBM1_PHY_SECTION 0x40000 +#define mmHBM2_MC0_BASE 0x5100000ull +#define HBM2_MC0_MAX_OFFSET 0x1000 +#define HBM2_MC0_SECTION 0xE800 +#define mmHBM2_MC0_SPECIAL_BASE 0x5100E80ull +#define HBM2_MC0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC0BIST0_BASE 0x5101000ull +#define HBM2_MC0BIST0_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST0_SECTION 0xE800 +#define mmHBM2_MC0BIST0_SPECIAL_BASE 0x5101E80ull +#define HBM2_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST0_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC0BIST1_BASE 0x5102000ull +#define HBM2_MC0BIST1_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST1_SECTION 0xE800 +#define mmHBM2_MC0BIST1_SPECIAL_BASE 0x5102E80ull +#define HBM2_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST1_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC0BIST2_BASE 0x5103000ull +#define HBM2_MC0BIST2_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST2_SECTION 0xE800 +#define mmHBM2_MC0BIST2_SPECIAL_BASE 0x5103E80ull +#define HBM2_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST2_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC0BIST3_BASE 0x5104000ull +#define HBM2_MC0BIST3_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST3_SECTION 0xE800 +#define mmHBM2_MC0BIST3_SPECIAL_BASE 0x5104E80ull +#define HBM2_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST3_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC0BIST4_BASE 0x5105000ull +#define HBM2_MC0BIST4_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST4_SECTION 0xE800 +#define mmHBM2_MC0BIST4_SPECIAL_BASE 0x5105E80ull +#define HBM2_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST4_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC0BIST5_BASE 0x5106000ull +#define HBM2_MC0BIST5_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST5_SECTION 0xE800 +#define mmHBM2_MC0BIST5_SPECIAL_BASE 0x5106E80ull +#define HBM2_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST5_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC0BIST6_BASE 0x5107000ull +#define HBM2_MC0BIST6_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST6_SECTION 0xE800 +#define mmHBM2_MC0BIST6_SPECIAL_BASE 0x5107E80ull +#define HBM2_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST6_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC0BIST7_BASE 0x5108000ull +#define HBM2_MC0BIST7_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST7_SECTION 0xE800 +#define mmHBM2_MC0BIST7_SPECIAL_BASE 0x5108E80ull +#define HBM2_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST7_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC0BIST8_MEM_BASE 0x5109000ull +#define HBM2_MC0BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST8_MEM_SECTION 0xE800 +#define mmHBM2_MC0BIST8_MEM_SPECIAL_BASE 0x5109E80ull +#define HBM2_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST8_MEM_SPECIAL_SECTION 0x16180 +#define mmHBM2_MC1_BASE 0x5120000ull +#define HBM2_MC1_MAX_OFFSET 0x1000 +#define HBM2_MC1_SECTION 0xE800 +#define mmHBM2_MC1_SPECIAL_BASE 0x5120E80ull +#define HBM2_MC1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC1BIST0_BASE 0x5121000ull +#define HBM2_MC1BIST0_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST0_SECTION 0xE800 +#define mmHBM2_MC1BIST0_SPECIAL_BASE 0x5121E80ull +#define HBM2_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST0_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC1BIST1_BASE 0x5122000ull +#define HBM2_MC1BIST1_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST1_SECTION 0xE800 +#define mmHBM2_MC1BIST1_SPECIAL_BASE 0x5122E80ull +#define HBM2_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST1_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC1BIST2_BASE 0x5123000ull +#define HBM2_MC1BIST2_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST2_SECTION 0xE800 +#define mmHBM2_MC1BIST2_SPECIAL_BASE 0x5123E80ull +#define HBM2_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST2_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC1BIST3_BASE 0x5124000ull +#define HBM2_MC1BIST3_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST3_SECTION 0xE800 +#define mmHBM2_MC1BIST3_SPECIAL_BASE 0x5124E80ull +#define HBM2_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST3_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC1BIST4_BASE 0x5125000ull +#define HBM2_MC1BIST4_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST4_SECTION 0xE800 +#define mmHBM2_MC1BIST4_SPECIAL_BASE 0x5125E80ull +#define HBM2_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST4_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC1BIST5_BASE 0x5126000ull +#define HBM2_MC1BIST5_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST5_SECTION 0xE800 +#define mmHBM2_MC1BIST5_SPECIAL_BASE 0x5126E80ull +#define HBM2_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST5_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC1BIST6_BASE 0x5127000ull +#define HBM2_MC1BIST6_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST6_SECTION 0xE800 +#define mmHBM2_MC1BIST6_SPECIAL_BASE 0x5127E80ull +#define HBM2_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST6_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC1BIST7_BASE 0x5128000ull +#define HBM2_MC1BIST7_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST7_SECTION 0xE800 +#define mmHBM2_MC1BIST7_SPECIAL_BASE 0x5128E80ull +#define HBM2_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST7_SPECIAL_SECTION 0x1800 +#define mmHBM2_MC1BIST8_MEM_BASE 0x5129000ull +#define HBM2_MC1BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST8_MEM_SECTION 0xE800 +#define mmHBM2_MC1BIST8_MEM_SPECIAL_BASE 0x5129E80ull +#define HBM2_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST8_MEM_SPECIAL_SECTION 0x16180 +#define mmHBM2_PHY_BASE 0x5140000ull +#define HBM2_PHY_MAX_OFFSET 0x4000 +#define HBM2_PHY_SECTION 0x40000 +#define mmHBM3_MC0_BASE 0x5180000ull +#define HBM3_MC0_MAX_OFFSET 0x1000 +#define HBM3_MC0_SECTION 0xE800 +#define mmHBM3_MC0_SPECIAL_BASE 0x5180E80ull +#define HBM3_MC0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC0BIST0_BASE 0x5181000ull +#define HBM3_MC0BIST0_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST0_SECTION 0xE800 +#define mmHBM3_MC0BIST0_SPECIAL_BASE 0x5181E80ull +#define HBM3_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST0_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC0BIST1_BASE 0x5182000ull +#define HBM3_MC0BIST1_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST1_SECTION 0xE800 +#define mmHBM3_MC0BIST1_SPECIAL_BASE 0x5182E80ull +#define HBM3_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST1_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC0BIST2_BASE 0x5183000ull +#define HBM3_MC0BIST2_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST2_SECTION 0xE800 +#define mmHBM3_MC0BIST2_SPECIAL_BASE 0x5183E80ull +#define HBM3_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST2_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC0BIST3_BASE 0x5184000ull +#define HBM3_MC0BIST3_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST3_SECTION 0xE800 +#define mmHBM3_MC0BIST3_SPECIAL_BASE 0x5184E80ull +#define HBM3_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST3_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC0BIST4_BASE 0x5185000ull +#define HBM3_MC0BIST4_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST4_SECTION 0xE800 +#define mmHBM3_MC0BIST4_SPECIAL_BASE 0x5185E80ull +#define HBM3_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST4_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC0BIST5_BASE 0x5186000ull +#define HBM3_MC0BIST5_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST5_SECTION 0xE800 +#define mmHBM3_MC0BIST5_SPECIAL_BASE 0x5186E80ull +#define HBM3_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST5_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC0BIST6_BASE 0x5187000ull +#define HBM3_MC0BIST6_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST6_SECTION 0xE800 +#define mmHBM3_MC0BIST6_SPECIAL_BASE 0x5187E80ull +#define HBM3_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST6_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC0BIST7_BASE 0x5188000ull +#define HBM3_MC0BIST7_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST7_SECTION 0xE800 +#define mmHBM3_MC0BIST7_SPECIAL_BASE 0x5188E80ull +#define HBM3_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST7_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC0BIST8_MEM_BASE 0x5189000ull +#define HBM3_MC0BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST8_MEM_SECTION 0xE800 +#define mmHBM3_MC0BIST8_MEM_SPECIAL_BASE 0x5189E80ull +#define HBM3_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST8_MEM_SPECIAL_SECTION 0x16180 +#define mmHBM3_MC1_BASE 0x51A0000ull +#define HBM3_MC1_MAX_OFFSET 0x1000 +#define HBM3_MC1_SECTION 0xE800 +#define mmHBM3_MC1_SPECIAL_BASE 0x51A0E80ull +#define HBM3_MC1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC1BIST0_BASE 0x51A1000ull +#define HBM3_MC1BIST0_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST0_SECTION 0xE800 +#define mmHBM3_MC1BIST0_SPECIAL_BASE 0x51A1E80ull +#define HBM3_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST0_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC1BIST1_BASE 0x51A2000ull +#define HBM3_MC1BIST1_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST1_SECTION 0xE800 +#define mmHBM3_MC1BIST1_SPECIAL_BASE 0x51A2E80ull +#define HBM3_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST1_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC1BIST2_BASE 0x51A3000ull +#define HBM3_MC1BIST2_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST2_SECTION 0xE800 +#define mmHBM3_MC1BIST2_SPECIAL_BASE 0x51A3E80ull +#define HBM3_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST2_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC1BIST3_BASE 0x51A4000ull +#define HBM3_MC1BIST3_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST3_SECTION 0xE800 +#define mmHBM3_MC1BIST3_SPECIAL_BASE 0x51A4E80ull +#define HBM3_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST3_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC1BIST4_BASE 0x51A5000ull +#define HBM3_MC1BIST4_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST4_SECTION 0xE800 +#define mmHBM3_MC1BIST4_SPECIAL_BASE 0x51A5E80ull +#define HBM3_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST4_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC1BIST5_BASE 0x51A6000ull +#define HBM3_MC1BIST5_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST5_SECTION 0xE800 +#define mmHBM3_MC1BIST5_SPECIAL_BASE 0x51A6E80ull +#define HBM3_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST5_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC1BIST6_BASE 0x51A7000ull +#define HBM3_MC1BIST6_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST6_SECTION 0xE800 +#define mmHBM3_MC1BIST6_SPECIAL_BASE 0x51A7E80ull +#define HBM3_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST6_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC1BIST7_BASE 0x51A8000ull +#define HBM3_MC1BIST7_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST7_SECTION 0xE800 +#define mmHBM3_MC1BIST7_SPECIAL_BASE 0x51A8E80ull +#define HBM3_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST7_SPECIAL_SECTION 0x1800 +#define mmHBM3_MC1BIST8_MEM_BASE 0x51A9000ull +#define HBM3_MC1BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST8_MEM_SECTION 0xE800 +#define mmHBM3_MC1BIST8_MEM_SPECIAL_BASE 0x51A9E80ull +#define HBM3_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST8_MEM_SPECIAL_SECTION 0x16180 +#define mmHBM3_PHY_BASE 0x51C0000ull +#define HBM3_PHY_MAX_OFFSET 0x4000 +#define HBM3_PHY_SECTION 0x40000 +#define mmHBM4_MC0_BASE 0x5200000ull +#define HBM4_MC0_MAX_OFFSET 0x1000 +#define HBM4_MC0_SECTION 0xE800 +#define mmHBM4_MC0_SPECIAL_BASE 0x5200E80ull +#define HBM4_MC0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC0BIST0_BASE 0x5201000ull +#define HBM4_MC0BIST0_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST0_SECTION 0xE800 +#define mmHBM4_MC0BIST0_SPECIAL_BASE 0x5201E80ull +#define HBM4_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST0_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC0BIST1_BASE 0x5202000ull +#define HBM4_MC0BIST1_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST1_SECTION 0xE800 +#define mmHBM4_MC0BIST1_SPECIAL_BASE 0x5202E80ull +#define HBM4_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST1_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC0BIST2_BASE 0x5203000ull +#define HBM4_MC0BIST2_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST2_SECTION 0xE800 +#define mmHBM4_MC0BIST2_SPECIAL_BASE 0x5203E80ull +#define HBM4_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST2_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC0BIST3_BASE 0x5204000ull +#define HBM4_MC0BIST3_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST3_SECTION 0xE800 +#define mmHBM4_MC0BIST3_SPECIAL_BASE 0x5204E80ull +#define HBM4_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST3_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC0BIST4_BASE 0x5205000ull +#define HBM4_MC0BIST4_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST4_SECTION 0xE800 +#define mmHBM4_MC0BIST4_SPECIAL_BASE 0x5205E80ull +#define HBM4_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST4_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC0BIST5_BASE 0x5206000ull +#define HBM4_MC0BIST5_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST5_SECTION 0xE800 +#define mmHBM4_MC0BIST5_SPECIAL_BASE 0x5206E80ull +#define HBM4_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST5_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC0BIST6_BASE 0x5207000ull +#define HBM4_MC0BIST6_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST6_SECTION 0xE800 +#define mmHBM4_MC0BIST6_SPECIAL_BASE 0x5207E80ull +#define HBM4_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST6_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC0BIST7_BASE 0x5208000ull +#define HBM4_MC0BIST7_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST7_SECTION 0xE800 +#define mmHBM4_MC0BIST7_SPECIAL_BASE 0x5208E80ull +#define HBM4_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST7_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC0BIST8_MEM_BASE 0x5209000ull +#define HBM4_MC0BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST8_MEM_SECTION 0xE800 +#define mmHBM4_MC0BIST8_MEM_SPECIAL_BASE 0x5209E80ull +#define HBM4_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST8_MEM_SPECIAL_SECTION 0x16180 +#define mmHBM4_MC1_BASE 0x5220000ull +#define HBM4_MC1_MAX_OFFSET 0x1000 +#define HBM4_MC1_SECTION 0xE800 +#define mmHBM4_MC1_SPECIAL_BASE 0x5220E80ull +#define HBM4_MC1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC1BIST0_BASE 0x5221000ull +#define HBM4_MC1BIST0_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST0_SECTION 0xE800 +#define mmHBM4_MC1BIST0_SPECIAL_BASE 0x5221E80ull +#define HBM4_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST0_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC1BIST1_BASE 0x5222000ull +#define HBM4_MC1BIST1_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST1_SECTION 0xE800 +#define mmHBM4_MC1BIST1_SPECIAL_BASE 0x5222E80ull +#define HBM4_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST1_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC1BIST2_BASE 0x5223000ull +#define HBM4_MC1BIST2_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST2_SECTION 0xE800 +#define mmHBM4_MC1BIST2_SPECIAL_BASE 0x5223E80ull +#define HBM4_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST2_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC1BIST3_BASE 0x5224000ull +#define HBM4_MC1BIST3_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST3_SECTION 0xE800 +#define mmHBM4_MC1BIST3_SPECIAL_BASE 0x5224E80ull +#define HBM4_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST3_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC1BIST4_BASE 0x5225000ull +#define HBM4_MC1BIST4_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST4_SECTION 0xE800 +#define mmHBM4_MC1BIST4_SPECIAL_BASE 0x5225E80ull +#define HBM4_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST4_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC1BIST5_BASE 0x5226000ull +#define HBM4_MC1BIST5_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST5_SECTION 0xE800 +#define mmHBM4_MC1BIST5_SPECIAL_BASE 0x5226E80ull +#define HBM4_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST5_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC1BIST6_BASE 0x5227000ull +#define HBM4_MC1BIST6_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST6_SECTION 0xE800 +#define mmHBM4_MC1BIST6_SPECIAL_BASE 0x5227E80ull +#define HBM4_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST6_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC1BIST7_BASE 0x5228000ull +#define HBM4_MC1BIST7_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST7_SECTION 0xE800 +#define mmHBM4_MC1BIST7_SPECIAL_BASE 0x5228E80ull +#define HBM4_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST7_SPECIAL_SECTION 0x1800 +#define mmHBM4_MC1BIST8_MEM_BASE 0x5229000ull +#define HBM4_MC1BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST8_MEM_SECTION 0xE800 +#define mmHBM4_MC1BIST8_MEM_SPECIAL_BASE 0x5229E80ull +#define HBM4_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST8_MEM_SPECIAL_SECTION 0x16180 +#define mmHBM4_PHY_BASE 0x5240000ull +#define HBM4_PHY_MAX_OFFSET 0x4000 +#define HBM4_PHY_SECTION 0x40000 +#define mmHBM5_MC0_BASE 0x5280000ull +#define HBM5_MC0_MAX_OFFSET 0x1000 +#define HBM5_MC0_SECTION 0xE800 +#define mmHBM5_MC0_SPECIAL_BASE 0x5280E80ull +#define HBM5_MC0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC0BIST0_BASE 0x5281000ull +#define HBM5_MC0BIST0_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST0_SECTION 0xE800 +#define mmHBM5_MC0BIST0_SPECIAL_BASE 0x5281E80ull +#define HBM5_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST0_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC0BIST1_BASE 0x5282000ull +#define HBM5_MC0BIST1_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST1_SECTION 0xE800 +#define mmHBM5_MC0BIST1_SPECIAL_BASE 0x5282E80ull +#define HBM5_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST1_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC0BIST2_BASE 0x5283000ull +#define HBM5_MC0BIST2_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST2_SECTION 0xE800 +#define mmHBM5_MC0BIST2_SPECIAL_BASE 0x5283E80ull +#define HBM5_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST2_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC0BIST3_BASE 0x5284000ull +#define HBM5_MC0BIST3_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST3_SECTION 0xE800 +#define mmHBM5_MC0BIST3_SPECIAL_BASE 0x5284E80ull +#define HBM5_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST3_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC0BIST4_BASE 0x5285000ull +#define HBM5_MC0BIST4_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST4_SECTION 0xE800 +#define mmHBM5_MC0BIST4_SPECIAL_BASE 0x5285E80ull +#define HBM5_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST4_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC0BIST5_BASE 0x5286000ull +#define HBM5_MC0BIST5_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST5_SECTION 0xE800 +#define mmHBM5_MC0BIST5_SPECIAL_BASE 0x5286E80ull +#define HBM5_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST5_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC0BIST6_BASE 0x5287000ull +#define HBM5_MC0BIST6_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST6_SECTION 0xE800 +#define mmHBM5_MC0BIST6_SPECIAL_BASE 0x5287E80ull +#define HBM5_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST6_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC0BIST7_BASE 0x5288000ull +#define HBM5_MC0BIST7_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST7_SECTION 0xE800 +#define mmHBM5_MC0BIST7_SPECIAL_BASE 0x5288E80ull +#define HBM5_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST7_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC0BIST8_MEM_BASE 0x5289000ull +#define HBM5_MC0BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST8_MEM_SECTION 0xE800 +#define mmHBM5_MC0BIST8_MEM_SPECIAL_BASE 0x5289E80ull +#define HBM5_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST8_MEM_SPECIAL_SECTION 0x16180 +#define mmHBM5_MC1_BASE 0x52A0000ull +#define HBM5_MC1_MAX_OFFSET 0x1000 +#define HBM5_MC1_SECTION 0xE800 +#define mmHBM5_MC1_SPECIAL_BASE 0x52A0E80ull +#define HBM5_MC1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC1BIST0_BASE 0x52A1000ull +#define HBM5_MC1BIST0_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST0_SECTION 0xE800 +#define mmHBM5_MC1BIST0_SPECIAL_BASE 0x52A1E80ull +#define HBM5_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST0_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC1BIST1_BASE 0x52A2000ull +#define HBM5_MC1BIST1_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST1_SECTION 0xE800 +#define mmHBM5_MC1BIST1_SPECIAL_BASE 0x52A2E80ull +#define HBM5_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST1_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC1BIST2_BASE 0x52A3000ull +#define HBM5_MC1BIST2_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST2_SECTION 0xE800 +#define mmHBM5_MC1BIST2_SPECIAL_BASE 0x52A3E80ull +#define HBM5_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST2_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC1BIST3_BASE 0x52A4000ull +#define HBM5_MC1BIST3_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST3_SECTION 0xE800 +#define mmHBM5_MC1BIST3_SPECIAL_BASE 0x52A4E80ull +#define HBM5_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST3_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC1BIST4_BASE 0x52A5000ull +#define HBM5_MC1BIST4_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST4_SECTION 0xE800 +#define mmHBM5_MC1BIST4_SPECIAL_BASE 0x52A5E80ull +#define HBM5_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST4_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC1BIST5_BASE 0x52A6000ull +#define HBM5_MC1BIST5_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST5_SECTION 0xE800 +#define mmHBM5_MC1BIST5_SPECIAL_BASE 0x52A6E80ull +#define HBM5_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST5_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC1BIST6_BASE 0x52A7000ull +#define HBM5_MC1BIST6_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST6_SECTION 0xE800 +#define mmHBM5_MC1BIST6_SPECIAL_BASE 0x52A7E80ull +#define HBM5_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST6_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC1BIST7_BASE 0x52A8000ull +#define HBM5_MC1BIST7_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST7_SECTION 0xE800 +#define mmHBM5_MC1BIST7_SPECIAL_BASE 0x52A8E80ull +#define HBM5_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST7_SPECIAL_SECTION 0x1800 +#define mmHBM5_MC1BIST8_MEM_BASE 0x52A9000ull +#define HBM5_MC1BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST8_MEM_SECTION 0xE800 +#define mmHBM5_MC1BIST8_MEM_SPECIAL_BASE 0x52A9E80ull +#define HBM5_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST8_MEM_SPECIAL_SECTION 0x16180 +#define mmHBM5_PHY_BASE 0x52C0000ull +#define HBM5_PHY_MAX_OFFSET 0x4000 +#define HBM5_PHY_SECTION 0x140000 +#define mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5400000ull +#define NIC0_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5400080ull +#define NIC0_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5400100ull +#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5400180ull +#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_0_SPECIAL_BASE 0x5400E80ull +#define NIC0_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_0_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5401000ull +#define NIC0_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5401080ull +#define NIC0_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5401100ull +#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5401180ull +#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_1_SPECIAL_BASE 0x5401E80ull +#define NIC0_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_1_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5402000ull +#define NIC0_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5402080ull +#define NIC0_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5402100ull +#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5402180ull +#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_2_SPECIAL_BASE 0x5402E80ull +#define NIC0_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_2_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5403000ull +#define NIC0_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5403080ull +#define NIC0_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5403100ull +#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5403180ull +#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_3_SPECIAL_BASE 0x5403E80ull +#define NIC0_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_3_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5404000ull +#define NIC0_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5404080ull +#define NIC0_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5404100ull +#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5404180ull +#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_4_SPECIAL_BASE 0x5404E80ull +#define NIC0_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_4_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5405000ull +#define NIC0_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5405080ull +#define NIC0_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5405100ull +#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5405180ull +#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_5_SPECIAL_BASE 0x5405E80ull +#define NIC0_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_5_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5406000ull +#define NIC0_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5406080ull +#define NIC0_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5406100ull +#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5406180ull +#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_6_SPECIAL_BASE 0x5406E80ull +#define NIC0_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_6_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5407000ull +#define NIC0_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5407080ull +#define NIC0_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5407100ull +#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5407180ull +#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_7_SPECIAL_BASE 0x5407E80ull +#define NIC0_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_7_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5408000ull +#define NIC0_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5408080ull +#define NIC0_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5408100ull +#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5408180ull +#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_8_SPECIAL_BASE 0x5408E80ull +#define NIC0_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_8_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5409000ull +#define NIC0_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5409080ull +#define NIC0_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5409100ull +#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5409180ull +#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_9_SPECIAL_BASE 0x5409E80ull +#define NIC0_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_9_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_10_UNSECURE_DOORBELL0_BASE 0x540A000ull +#define NIC0_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_10_UNSECURE_DOORBELL1_BASE 0x540A080ull +#define NIC0_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x540A100ull +#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x540A180ull +#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_10_SPECIAL_BASE 0x540AE80ull +#define NIC0_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_10_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_11_UNSECURE_DOORBELL0_BASE 0x540B000ull +#define NIC0_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_11_UNSECURE_DOORBELL1_BASE 0x540B080ull +#define NIC0_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x540B100ull +#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x540B180ull +#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_11_SPECIAL_BASE 0x540BE80ull +#define NIC0_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_11_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_12_UNSECURE_DOORBELL0_BASE 0x540C000ull +#define NIC0_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_12_UNSECURE_DOORBELL1_BASE 0x540C080ull +#define NIC0_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x540C100ull +#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x540C180ull +#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_12_SPECIAL_BASE 0x540CE80ull +#define NIC0_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_12_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_13_UNSECURE_DOORBELL0_BASE 0x540D000ull +#define NIC0_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_13_UNSECURE_DOORBELL1_BASE 0x540D080ull +#define NIC0_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x540D100ull +#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x540D180ull +#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_13_SPECIAL_BASE 0x540DE80ull +#define NIC0_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_13_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR0_14_UNSECURE_DOORBELL0_BASE 0x540E000ull +#define NIC0_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR0_14_UNSECURE_DOORBELL1_BASE 0x540E080ull +#define NIC0_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x540E100ull +#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x540E180ull +#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR0_14_SPECIAL_BASE 0x540EE80ull +#define NIC0_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_14_SPECIAL_SECTION 0x1180 +#define mmNIC0_QM_DCCM0_BASE 0x5410000ull +#define NIC0_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC0_QM_DCCM0_SECTION 0x8000 +#define mmNIC0_QM_ARC_AUX0_BASE 0x5418000ull +#define NIC0_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC0_QM_ARC_AUX0_SECTION 0xE800 +#define mmNIC0_QM_ARC_AUX0_SPECIAL_BASE 0x5418E80ull +#define NIC0_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 +#define mmNIC0_QM0_BASE 0x541A000ull +#define NIC0_QM0_MAX_OFFSET 0x1000 +#define NIC0_QM0_SECTION 0x9000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x541A900ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x541A908ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x541A910ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x541A918ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x541A920ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x541A928ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x541A930ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x541A938ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x541A940ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x541A948ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x541A950ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x541A958ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x541A960ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x541A968ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x541A970ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x541A978ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC0_QM0_AXUSER_SECURED_BASE 0x541AB00ull +#define NIC0_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC0_QM0_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC0_QM0_AXUSER_NONSECURED_BASE 0x541AB80ull +#define NIC0_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC0_QM0_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC0_QM0_DBG_HBW_BASE 0x541AC00ull +#define NIC0_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC0_QM0_DBG_HBW_SECTION 0x8000 +#define mmNIC0_QM0_DBG_LBW_BASE 0x541AC80ull +#define NIC0_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC0_QM0_DBG_LBW_SECTION 0x1000 +#define mmNIC0_QM0_CGM_BASE 0x541AD80ull +#define NIC0_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC0_QM0_CGM_SECTION 0x1000 +#define mmNIC0_QM0_SPECIAL_BASE 0x541AE80ull +#define NIC0_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_QM0_SPECIAL_SECTION 0x4180 +#define mmNIC0_QPC0_BASE 0x541F000ull +#define NIC0_QPC0_MAX_OFFSET 0x1000 +#define NIC0_QPC0_SECTION 0x7200 +#define mmNIC0_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x541F720ull +#define NIC0_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x541F728ull +#define NIC0_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x541F730ull +#define NIC0_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x541F738ull +#define NIC0_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x541F740ull +#define NIC0_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x541F748ull +#define NIC0_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x541F750ull +#define NIC0_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x541F758ull +#define NIC0_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x541F760ull +#define NIC0_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x541F768ull +#define NIC0_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x541F770ull +#define NIC0_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x541F778ull +#define NIC0_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x541F780ull +#define NIC0_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x541F788ull +#define NIC0_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x541F790ull +#define NIC0_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x541F798ull +#define NIC0_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x541F7A0ull +#define NIC0_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x541F7A8ull +#define NIC0_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x541F7B0ull +#define NIC0_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x541F7B8ull +#define NIC0_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x541F7C0ull +#define NIC0_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x541F7C8ull +#define NIC0_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x541F7D0ull +#define NIC0_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x541F7D8ull +#define NIC0_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x541F7E0ull +#define NIC0_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x541F7E8ull +#define NIC0_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x541F7F0ull +#define NIC0_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x541F7F8ull +#define NIC0_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x541F800ull +#define NIC0_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x541F808ull +#define NIC0_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x541F810ull +#define NIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x541F818ull +#define NIC0_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC0_QPC0_AXUSER_CONG_QUE_BASE 0x541FB80ull +#define NIC0_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC0_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC0_QPC0_AXUSER_RXWQE_BASE 0x541FBE0ull +#define NIC0_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC0_QPC0_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x541FC40ull +#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC0_QPC0_AXUSER_DB_FIFO_BASE 0x541FCA0ull +#define NIC0_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC0_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x541FD00ull +#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC0_QPC0_AXUSER_ERR_FIFO_BASE 0x541FD60ull +#define NIC0_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC0_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC0_QPC0_AXUSER_QPC_RESP_BASE 0x541FDC0ull +#define NIC0_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC0_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC0_QPC0_AXUSER_QPC_REQ_BASE 0x541FE20ull +#define NIC0_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC0_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC0_QPC0_SPECIAL_BASE 0x541FE80ull +#define NIC0_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_QPC0_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5420000ull +#define NIC0_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5420080ull +#define NIC0_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5420100ull +#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5420180ull +#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_0_SPECIAL_BASE 0x5420E80ull +#define NIC0_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_0_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5421000ull +#define NIC0_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5421080ull +#define NIC0_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5421100ull +#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5421180ull +#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_1_SPECIAL_BASE 0x5421E80ull +#define NIC0_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_1_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5422000ull +#define NIC0_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5422080ull +#define NIC0_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5422100ull +#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5422180ull +#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_2_SPECIAL_BASE 0x5422E80ull +#define NIC0_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_2_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5423000ull +#define NIC0_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5423080ull +#define NIC0_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5423100ull +#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5423180ull +#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_3_SPECIAL_BASE 0x5423E80ull +#define NIC0_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_3_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5424000ull +#define NIC0_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5424080ull +#define NIC0_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5424100ull +#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5424180ull +#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_4_SPECIAL_BASE 0x5424E80ull +#define NIC0_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_4_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5425000ull +#define NIC0_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5425080ull +#define NIC0_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5425100ull +#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5425180ull +#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_5_SPECIAL_BASE 0x5425E80ull +#define NIC0_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_5_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5426000ull +#define NIC0_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5426080ull +#define NIC0_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5426100ull +#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5426180ull +#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_6_SPECIAL_BASE 0x5426E80ull +#define NIC0_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_6_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5427000ull +#define NIC0_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5427080ull +#define NIC0_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5427100ull +#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5427180ull +#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_7_SPECIAL_BASE 0x5427E80ull +#define NIC0_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_7_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5428000ull +#define NIC0_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5428080ull +#define NIC0_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5428100ull +#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5428180ull +#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_8_SPECIAL_BASE 0x5428E80ull +#define NIC0_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_8_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5429000ull +#define NIC0_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5429080ull +#define NIC0_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5429100ull +#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5429180ull +#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_9_SPECIAL_BASE 0x5429E80ull +#define NIC0_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_9_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_10_UNSECURE_DOORBELL0_BASE 0x542A000ull +#define NIC0_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_10_UNSECURE_DOORBELL1_BASE 0x542A080ull +#define NIC0_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x542A100ull +#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x542A180ull +#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_10_SPECIAL_BASE 0x542AE80ull +#define NIC0_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_10_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_11_UNSECURE_DOORBELL0_BASE 0x542B000ull +#define NIC0_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_11_UNSECURE_DOORBELL1_BASE 0x542B080ull +#define NIC0_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x542B100ull +#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x542B180ull +#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_11_SPECIAL_BASE 0x542BE80ull +#define NIC0_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_11_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_12_UNSECURE_DOORBELL0_BASE 0x542C000ull +#define NIC0_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_12_UNSECURE_DOORBELL1_BASE 0x542C080ull +#define NIC0_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x542C100ull +#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x542C180ull +#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_12_SPECIAL_BASE 0x542CE80ull +#define NIC0_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_12_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_13_UNSECURE_DOORBELL0_BASE 0x542D000ull +#define NIC0_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_13_UNSECURE_DOORBELL1_BASE 0x542D080ull +#define NIC0_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x542D100ull +#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x542D180ull +#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_13_SPECIAL_BASE 0x542DE80ull +#define NIC0_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_13_SPECIAL_SECTION 0x1800 +#define mmNIC0_UMR1_14_UNSECURE_DOORBELL0_BASE 0x542E000ull +#define NIC0_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC0_UMR1_14_UNSECURE_DOORBELL1_BASE 0x542E080ull +#define NIC0_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC0_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x542E100ull +#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC0_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x542E180ull +#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC0_UMR1_14_SPECIAL_BASE 0x542EE80ull +#define NIC0_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_14_SPECIAL_SECTION 0x1180 +#define mmNIC0_QM_DCCM1_BASE 0x5430000ull +#define NIC0_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC0_QM_DCCM1_SECTION 0x8000 +#define mmNIC0_QM_ARC_AUX1_BASE 0x5438000ull +#define NIC0_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC0_QM_ARC_AUX1_SECTION 0xE800 +#define mmNIC0_QM_ARC_AUX1_SPECIAL_BASE 0x5438E80ull +#define NIC0_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 +#define mmNIC0_QM1_BASE 0x543A000ull +#define NIC0_QM1_MAX_OFFSET 0x1000 +#define NIC0_QM1_SECTION 0x9000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x543A900ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x543A908ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x543A910ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x543A918ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x543A920ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x543A928ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x543A930ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x543A938ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x543A940ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x543A948ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x543A950ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x543A958ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x543A960ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x543A968ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x543A970ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x543A978ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC0_QM1_AXUSER_SECURED_BASE 0x543AB00ull +#define NIC0_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC0_QM1_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC0_QM1_AXUSER_NONSECURED_BASE 0x543AB80ull +#define NIC0_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC0_QM1_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC0_QM1_DBG_HBW_BASE 0x543AC00ull +#define NIC0_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC0_QM1_DBG_HBW_SECTION 0x8000 +#define mmNIC0_QM1_DBG_LBW_BASE 0x543AC80ull +#define NIC0_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC0_QM1_DBG_LBW_SECTION 0x1000 +#define mmNIC0_QM1_CGM_BASE 0x543AD80ull +#define NIC0_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC0_QM1_CGM_SECTION 0x1000 +#define mmNIC0_QM1_SPECIAL_BASE 0x543AE80ull +#define NIC0_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_QM1_SPECIAL_SECTION 0x4180 +#define mmNIC0_QPC1_BASE 0x543F000ull +#define NIC0_QPC1_MAX_OFFSET 0x1000 +#define NIC0_QPC1_SECTION 0x7200 +#define mmNIC0_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x543F720ull +#define NIC0_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x543F728ull +#define NIC0_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x543F730ull +#define NIC0_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x543F738ull +#define NIC0_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x543F740ull +#define NIC0_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x543F748ull +#define NIC0_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x543F750ull +#define NIC0_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x543F758ull +#define NIC0_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x543F760ull +#define NIC0_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x543F768ull +#define NIC0_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x543F770ull +#define NIC0_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x543F778ull +#define NIC0_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x543F780ull +#define NIC0_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x543F788ull +#define NIC0_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x543F790ull +#define NIC0_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x543F798ull +#define NIC0_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x543F7A0ull +#define NIC0_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x543F7A8ull +#define NIC0_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x543F7B0ull +#define NIC0_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x543F7B8ull +#define NIC0_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x543F7C0ull +#define NIC0_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x543F7C8ull +#define NIC0_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x543F7D0ull +#define NIC0_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x543F7D8ull +#define NIC0_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x543F7E0ull +#define NIC0_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x543F7E8ull +#define NIC0_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x543F7F0ull +#define NIC0_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x543F7F8ull +#define NIC0_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x543F800ull +#define NIC0_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x543F808ull +#define NIC0_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x543F810ull +#define NIC0_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC0_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x543F818ull +#define NIC0_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC0_QPC1_AXUSER_CONG_QUE_BASE 0x543FB80ull +#define NIC0_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC0_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC0_QPC1_AXUSER_RXWQE_BASE 0x543FBE0ull +#define NIC0_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC0_QPC1_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC0_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x543FC40ull +#define NIC0_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC0_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC0_QPC1_AXUSER_DB_FIFO_BASE 0x543FCA0ull +#define NIC0_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC0_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC0_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x543FD00ull +#define NIC0_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC0_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC0_QPC1_AXUSER_ERR_FIFO_BASE 0x543FD60ull +#define NIC0_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC0_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC0_QPC1_AXUSER_QPC_RESP_BASE 0x543FDC0ull +#define NIC0_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC0_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC0_QPC1_AXUSER_QPC_REQ_BASE 0x543FE20ull +#define NIC0_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC0_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC0_QPC1_SPECIAL_BASE 0x543FE80ull +#define NIC0_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_QPC1_SPECIAL_SECTION 0x8180 +#define mmNIC0_TMR_BASE 0x5448000ull +#define NIC0_TMR_MAX_OFFSET 0x1000 +#define NIC0_TMR_SECTION 0xD600 +#define mmNIC0_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5448D60ull +#define NIC0_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC0_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 +#define mmNIC0_TMR_AXUSER_TMR_FIFO_BASE 0x5448DC0ull +#define NIC0_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC0_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 +#define mmNIC0_TMR_AXUSER_TMR_FSM_BASE 0x5448E20ull +#define NIC0_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC0_TMR_AXUSER_TMR_FSM_SECTION 0x6000 +#define mmNIC0_TMR_SPECIAL_BASE 0x5448E80ull +#define NIC0_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_TMR_SPECIAL_SECTION 0x1800 +#define mmNIC0_RXB_CORE_BASE 0x5449000ull +#define NIC0_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC0_RXB_CORE_SECTION 0x6100 +#define mmNIC0_RXB_CORE_SCT_AWUSER_BASE 0x5449610ull +#define NIC0_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC0_RXB_CORE_SCT_AWUSER_SECTION 0x8700 +#define mmNIC0_RXB_CORE_SPECIAL_BASE 0x5449E80ull +#define NIC0_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_RXB_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC0_RXE0_BASE 0x544A000ull +#define NIC0_RXE0_MAX_OFFSET 0x1000 +#define NIC0_RXE0_SECTION 0x9000 +#define mmNIC0_RXE0_WQE_ARUSER_BASE 0x544A900ull +#define NIC0_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC0_RXE0_WQE_ARUSER_SECTION 0x5800 +#define mmNIC0_RXE0_SPECIAL_BASE 0x544AE80ull +#define NIC0_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_RXE0_SPECIAL_SECTION 0x1800 +#define mmNIC0_RXE1_BASE 0x544B000ull +#define NIC0_RXE1_MAX_OFFSET 0x1000 +#define NIC0_RXE1_SECTION 0x9000 +#define mmNIC0_RXE1_WQE_ARUSER_BASE 0x544B900ull +#define NIC0_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC0_RXE1_WQE_ARUSER_SECTION 0x5800 +#define mmNIC0_RXE1_SPECIAL_BASE 0x544BE80ull +#define NIC0_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_RXE1_SPECIAL_SECTION 0x1800 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ0_BASE 0x544C000ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ1_BASE 0x544C050ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ2_BASE 0x544C0A0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ3_BASE 0x544C0F0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ4_BASE 0x544C140ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ5_BASE 0x544C190ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ6_BASE 0x544C1E0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ7_BASE 0x544C230ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ8_BASE 0x544C280ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ9_BASE 0x544C2D0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ10_BASE 0x544C320ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ11_BASE 0x544C370ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ12_BASE 0x544C3C0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ13_BASE 0x544C410ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ14_BASE 0x544C460ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ15_BASE 0x544C4B0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ16_BASE 0x544C500ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ17_BASE 0x544C550ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ18_BASE 0x544C5A0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ19_BASE 0x544C5F0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ20_BASE 0x544C640ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ21_BASE 0x544C690ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ22_BASE 0x544C6E0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ23_BASE 0x544C730ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ24_BASE 0x544C780ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ25_BASE 0x544C7D0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ26_BASE 0x544C820ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ27_BASE 0x544C870ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ28_BASE 0x544C8C0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ29_BASE 0x544C910ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ30_BASE 0x544C960ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ31_BASE 0x544C9B0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC0_RXE0_AXUSER_SPECIAL_BASE 0x544CE80ull +#define NIC0_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_RXE0_AXUSER_SPECIAL_SECTION 0x1800 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ0_BASE 0x544D000ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ1_BASE 0x544D050ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ2_BASE 0x544D0A0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ3_BASE 0x544D0F0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ4_BASE 0x544D140ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ5_BASE 0x544D190ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ6_BASE 0x544D1E0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ7_BASE 0x544D230ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ8_BASE 0x544D280ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ9_BASE 0x544D2D0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ10_BASE 0x544D320ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ11_BASE 0x544D370ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ12_BASE 0x544D3C0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ13_BASE 0x544D410ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ14_BASE 0x544D460ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ15_BASE 0x544D4B0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ16_BASE 0x544D500ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ17_BASE 0x544D550ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ18_BASE 0x544D5A0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ19_BASE 0x544D5F0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ20_BASE 0x544D640ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ21_BASE 0x544D690ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ22_BASE 0x544D6E0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ23_BASE 0x544D730ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ24_BASE 0x544D780ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ25_BASE 0x544D7D0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ26_BASE 0x544D820ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ27_BASE 0x544D870ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ28_BASE 0x544D8C0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ29_BASE 0x544D910ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ30_BASE 0x544D960ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ31_BASE 0x544D9B0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC0_RXE1_AXUSER_SPECIAL_BASE 0x544DE80ull +#define NIC0_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_RXE1_AXUSER_SPECIAL_SECTION 0x2180 +#define mmNIC0_TXS0_BASE 0x5450000ull +#define NIC0_TXS0_MAX_OFFSET 0x1000 +#define NIC0_TXS0_SECTION 0xE800 +#define mmNIC0_TXS0_SPECIAL_BASE 0x5450E80ull +#define NIC0_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_TXS0_SPECIAL_SECTION 0x1800 +#define mmNIC0_TXS1_BASE 0x5451000ull +#define NIC0_TXS1_MAX_OFFSET 0x1000 +#define NIC0_TXS1_SECTION 0xE800 +#define mmNIC0_TXS1_SPECIAL_BASE 0x5451E80ull +#define NIC0_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_TXS1_SPECIAL_SECTION 0x1800 +#define mmNIC0_TXE0_BASE 0x5452000ull +#define NIC0_TXE0_MAX_OFFSET 0x1000 +#define NIC0_TXE0_SECTION 0xE800 +#define mmNIC0_TXE0_SPECIAL_BASE 0x5452E80ull +#define NIC0_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_TXE0_SPECIAL_SECTION 0x1800 +#define mmNIC0_TXE1_BASE 0x5453000ull +#define NIC0_TXE1_MAX_OFFSET 0x1000 +#define NIC0_TXE1_SECTION 0xE800 +#define mmNIC0_TXE1_SPECIAL_BASE 0x5453E80ull +#define NIC0_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_TXE1_SPECIAL_SECTION 0x1800 +#define mmNIC0_TXB_BASE 0x5454000ull +#define NIC0_TXB_MAX_OFFSET 0x1000 +#define NIC0_TXB_SECTION 0xE800 +#define mmNIC0_TXB_SPECIAL_BASE 0x5454E80ull +#define NIC0_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_TXB_SPECIAL_SECTION 0x1800 +#define mmNIC0_MSTR_IF_RR_SHRD_HBW_BASE 0x5455000ull +#define NIC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmNIC0_MSTR_IF_RR_PRVT_HBW_BASE 0x5455200ull +#define NIC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmNIC0_MSTR_IF_RR_SHRD_LBW_BASE 0x5455400ull +#define NIC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmNIC0_MSTR_IF_RR_PRVT_LBW_BASE 0x5455600ull +#define NIC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmNIC0_MSTR_IF_E2E_CRDT_BASE 0x5455800ull +#define NIC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmNIC0_MSTR_IF_AXUSER_BASE 0x5455A80ull +#define NIC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC0_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmNIC0_MSTR_IF_DBG_HBW_BASE 0x5455B00ull +#define NIC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC0_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmNIC0_MSTR_IF_DBG_LBW_BASE 0x5455B80ull +#define NIC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC0_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmNIC0_MSTR_IF_CORE_HBW_BASE 0x5455C00ull +#define NIC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC0_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmNIC0_MSTR_IF_CORE_LBW_BASE 0x5455D80ull +#define NIC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC0_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmNIC0_MSTR_IF_SPECIAL_BASE 0x5455E80ull +#define NIC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmNIC0_TX_AXUSER_BASE 0x5456000ull +#define NIC0_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC0_TX_AXUSER_SECTION 0x2000 +#define mmNIC0_SERDES0_BASE 0x5458000ull +#define NIC0_SERDES0_MAX_OFFSET 0x3E40 +#define NIC0_SERDES0_SECTION 0x4000 +#define mmNIC0_SERDES1_BASE 0x545C000ull +#define NIC0_SERDES1_MAX_OFFSET 0x3E40 +#define NIC0_SERDES1_SECTION 0x4000 +#define mmNIC0_PHY_BASE 0x5460000ull +#define NIC0_PHY_MAX_OFFSET 0x1000 +#define NIC0_PHY_SECTION 0xE800 +#define mmNIC0_PHY_SPECIAL_BASE 0x5460E80ull +#define NIC0_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_PHY_SPECIAL_SECTION 0x7180 +#define mmPRT0_MAC_AUX_BASE 0x5468000ull +#define PRT0_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT0_MAC_AUX_SECTION 0xE800 +#define mmPRT0_MAC_AUX_SPECIAL_BASE 0x5468E80ull +#define PRT0_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT0_MAC_AUX_SPECIAL_SECTION 0x1800 +#define mmPRT0_MAC_CORE_BASE 0x5469000ull +#define PRT0_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT0_MAC_CORE_SECTION 0xE800 +#define mmPRT0_MAC_CORE_SPECIAL_BASE 0x5469E80ull +#define PRT0_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT0_MAC_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC0_MAC_RS_FEC_BASE 0x546A000ull +#define NIC0_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC0_MAC_RS_FEC_SECTION 0x1000 +#define mmNIC0_MAC_GLOB_STAT_CONTROL_REG_BASE 0x546B000ull +#define NIC0_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000 +#define NIC0_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000 +#define mmNIC0_MAC_GLOB_STAT_RX0_BASE 0x546B100ull +#define NIC0_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00 +#define NIC0_MAC_GLOB_STAT_RX0_SECTION 0x8C00 +#define mmNIC0_MAC_GLOB_STAT_RX1_BASE 0x546B18Cull +#define NIC0_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00 +#define NIC0_MAC_GLOB_STAT_RX1_SECTION 0x8C00 +#define mmNIC0_MAC_GLOB_STAT_RX2_BASE 0x546B218ull +#define NIC0_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00 +#define NIC0_MAC_GLOB_STAT_RX2_SECTION 0x8C00 +#define mmNIC0_MAC_GLOB_STAT_RX3_BASE 0x546B2A4ull +#define NIC0_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00 +#define NIC0_MAC_GLOB_STAT_RX3_SECTION 0x8C00 +#define mmNIC0_MAC_GLOB_STAT_TX0_BASE 0x546B330ull +#define NIC0_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800 +#define NIC0_MAC_GLOB_STAT_TX0_SECTION 0x6800 +#define mmNIC0_MAC_GLOB_STAT_TX1_BASE 0x546B398ull +#define NIC0_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800 +#define NIC0_MAC_GLOB_STAT_TX1_SECTION 0x6800 +#define mmNIC0_MAC_GLOB_STAT_TX2_BASE 0x546B400ull +#define NIC0_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800 +#define NIC0_MAC_GLOB_STAT_TX2_SECTION 0x6800 +#define mmNIC0_MAC_GLOB_STAT_TX3_BASE 0x546B468ull +#define NIC0_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800 +#define NIC0_MAC_GLOB_STAT_TX3_SECTION 0x3980 +#define mmNIC0_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x546B800ull +#define NIC0_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC0_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000 +#define mmNIC0_MAC_CH0_MAC_PCS_BASE 0x546C000ull +#define NIC0_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC0_MAC_CH0_MAC_PCS_SECTION 0x4000 +#define mmNIC0_MAC_CH0_MAC_128_BASE 0x546C400ull +#define NIC0_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC0_MAC_CH0_MAC_128_SECTION 0x4000 +#define mmNIC0_MAC_CH0_MAC_AN_BASE 0x546C800ull +#define NIC0_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC0_MAC_CH0_MAC_AN_SECTION 0x8000 +#define mmNIC0_MAC_CH1_MAC_PCS_BASE 0x546D000ull +#define NIC0_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC0_MAC_CH1_MAC_PCS_SECTION 0x4000 +#define mmNIC0_MAC_CH1_MAC_128_BASE 0x546D400ull +#define NIC0_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC0_MAC_CH1_MAC_128_SECTION 0x4000 +#define mmNIC0_MAC_CH1_MAC_AN_BASE 0x546D800ull +#define NIC0_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC0_MAC_CH1_MAC_AN_SECTION 0x8000 +#define mmNIC0_MAC_CH2_MAC_PCS_BASE 0x546E000ull +#define NIC0_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC0_MAC_CH2_MAC_PCS_SECTION 0x4000 +#define mmNIC0_MAC_CH2_MAC_128_BASE 0x546E400ull +#define NIC0_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC0_MAC_CH2_MAC_128_SECTION 0x4000 +#define mmNIC0_MAC_CH2_MAC_AN_BASE 0x546E800ull +#define NIC0_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC0_MAC_CH2_MAC_AN_SECTION 0x8000 +#define mmNIC0_MAC_CH3_MAC_PCS_BASE 0x546F000ull +#define NIC0_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC0_MAC_CH3_MAC_PCS_SECTION 0x4000 +#define mmNIC0_MAC_CH3_MAC_128_BASE 0x546F400ull +#define NIC0_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC0_MAC_CH3_MAC_128_SECTION 0x4000 +#define mmNIC0_MAC_CH3_MAC_AN_BASE 0x546F800ull +#define NIC0_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC0_MAC_CH3_MAC_AN_SECTION 0x10800 +#define mmNIC1_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5480000ull +#define NIC1_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5480080ull +#define NIC1_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5480100ull +#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5480180ull +#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_0_SPECIAL_BASE 0x5480E80ull +#define NIC1_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_0_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5481000ull +#define NIC1_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5481080ull +#define NIC1_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5481100ull +#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5481180ull +#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_1_SPECIAL_BASE 0x5481E80ull +#define NIC1_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_1_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5482000ull +#define NIC1_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5482080ull +#define NIC1_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5482100ull +#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5482180ull +#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_2_SPECIAL_BASE 0x5482E80ull +#define NIC1_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_2_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5483000ull +#define NIC1_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5483080ull +#define NIC1_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5483100ull +#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5483180ull +#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_3_SPECIAL_BASE 0x5483E80ull +#define NIC1_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_3_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5484000ull +#define NIC1_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5484080ull +#define NIC1_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5484100ull +#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5484180ull +#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_4_SPECIAL_BASE 0x5484E80ull +#define NIC1_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_4_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5485000ull +#define NIC1_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5485080ull +#define NIC1_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5485100ull +#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5485180ull +#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_5_SPECIAL_BASE 0x5485E80ull +#define NIC1_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_5_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5486000ull +#define NIC1_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5486080ull +#define NIC1_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5486100ull +#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5486180ull +#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_6_SPECIAL_BASE 0x5486E80ull +#define NIC1_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_6_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5487000ull +#define NIC1_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5487080ull +#define NIC1_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5487100ull +#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5487180ull +#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_7_SPECIAL_BASE 0x5487E80ull +#define NIC1_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_7_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5488000ull +#define NIC1_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5488080ull +#define NIC1_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5488100ull +#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5488180ull +#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_8_SPECIAL_BASE 0x5488E80ull +#define NIC1_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_8_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5489000ull +#define NIC1_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5489080ull +#define NIC1_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5489100ull +#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5489180ull +#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_9_SPECIAL_BASE 0x5489E80ull +#define NIC1_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_9_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_10_UNSECURE_DOORBELL0_BASE 0x548A000ull +#define NIC1_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_10_UNSECURE_DOORBELL1_BASE 0x548A080ull +#define NIC1_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x548A100ull +#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x548A180ull +#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_10_SPECIAL_BASE 0x548AE80ull +#define NIC1_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_10_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_11_UNSECURE_DOORBELL0_BASE 0x548B000ull +#define NIC1_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_11_UNSECURE_DOORBELL1_BASE 0x548B080ull +#define NIC1_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x548B100ull +#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x548B180ull +#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_11_SPECIAL_BASE 0x548BE80ull +#define NIC1_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_11_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_12_UNSECURE_DOORBELL0_BASE 0x548C000ull +#define NIC1_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_12_UNSECURE_DOORBELL1_BASE 0x548C080ull +#define NIC1_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x548C100ull +#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x548C180ull +#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_12_SPECIAL_BASE 0x548CE80ull +#define NIC1_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_12_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_13_UNSECURE_DOORBELL0_BASE 0x548D000ull +#define NIC1_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_13_UNSECURE_DOORBELL1_BASE 0x548D080ull +#define NIC1_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x548D100ull +#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x548D180ull +#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_13_SPECIAL_BASE 0x548DE80ull +#define NIC1_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_13_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR0_14_UNSECURE_DOORBELL0_BASE 0x548E000ull +#define NIC1_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR0_14_UNSECURE_DOORBELL1_BASE 0x548E080ull +#define NIC1_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x548E100ull +#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x548E180ull +#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR0_14_SPECIAL_BASE 0x548EE80ull +#define NIC1_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_14_SPECIAL_SECTION 0x1180 +#define mmNIC1_QM_DCCM0_BASE 0x5490000ull +#define NIC1_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC1_QM_DCCM0_SECTION 0x8000 +#define mmNIC1_QM_ARC_AUX0_BASE 0x5498000ull +#define NIC1_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC1_QM_ARC_AUX0_SECTION 0xE800 +#define mmNIC1_QM_ARC_AUX0_SPECIAL_BASE 0x5498E80ull +#define NIC1_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 +#define mmNIC1_QM0_BASE 0x549A000ull +#define NIC1_QM0_MAX_OFFSET 0x1000 +#define NIC1_QM0_SECTION 0x9000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x549A900ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x549A908ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x549A910ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x549A918ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x549A920ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x549A928ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x549A930ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x549A938ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x549A940ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x549A948ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x549A950ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x549A958ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x549A960ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x549A968ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x549A970ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x549A978ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC1_QM0_AXUSER_SECURED_BASE 0x549AB00ull +#define NIC1_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC1_QM0_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC1_QM0_AXUSER_NONSECURED_BASE 0x549AB80ull +#define NIC1_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC1_QM0_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC1_QM0_DBG_HBW_BASE 0x549AC00ull +#define NIC1_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC1_QM0_DBG_HBW_SECTION 0x8000 +#define mmNIC1_QM0_DBG_LBW_BASE 0x549AC80ull +#define NIC1_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC1_QM0_DBG_LBW_SECTION 0x1000 +#define mmNIC1_QM0_CGM_BASE 0x549AD80ull +#define NIC1_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC1_QM0_CGM_SECTION 0x1000 +#define mmNIC1_QM0_SPECIAL_BASE 0x549AE80ull +#define NIC1_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_QM0_SPECIAL_SECTION 0x4180 +#define mmNIC1_QPC0_BASE 0x549F000ull +#define NIC1_QPC0_MAX_OFFSET 0x1000 +#define NIC1_QPC0_SECTION 0x7200 +#define mmNIC1_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x549F720ull +#define NIC1_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x549F728ull +#define NIC1_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x549F730ull +#define NIC1_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x549F738ull +#define NIC1_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x549F740ull +#define NIC1_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x549F748ull +#define NIC1_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x549F750ull +#define NIC1_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x549F758ull +#define NIC1_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x549F760ull +#define NIC1_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x549F768ull +#define NIC1_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x549F770ull +#define NIC1_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x549F778ull +#define NIC1_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x549F780ull +#define NIC1_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x549F788ull +#define NIC1_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x549F790ull +#define NIC1_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x549F798ull +#define NIC1_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x549F7A0ull +#define NIC1_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x549F7A8ull +#define NIC1_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x549F7B0ull +#define NIC1_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x549F7B8ull +#define NIC1_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x549F7C0ull +#define NIC1_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x549F7C8ull +#define NIC1_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x549F7D0ull +#define NIC1_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x549F7D8ull +#define NIC1_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x549F7E0ull +#define NIC1_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x549F7E8ull +#define NIC1_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x549F7F0ull +#define NIC1_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x549F7F8ull +#define NIC1_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x549F800ull +#define NIC1_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x549F808ull +#define NIC1_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x549F810ull +#define NIC1_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x549F818ull +#define NIC1_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC1_QPC0_AXUSER_CONG_QUE_BASE 0x549FB80ull +#define NIC1_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC1_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC1_QPC0_AXUSER_RXWQE_BASE 0x549FBE0ull +#define NIC1_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC1_QPC0_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC1_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x549FC40ull +#define NIC1_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC1_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC1_QPC0_AXUSER_DB_FIFO_BASE 0x549FCA0ull +#define NIC1_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC1_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC1_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x549FD00ull +#define NIC1_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC1_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC1_QPC0_AXUSER_ERR_FIFO_BASE 0x549FD60ull +#define NIC1_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC1_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC1_QPC0_AXUSER_QPC_RESP_BASE 0x549FDC0ull +#define NIC1_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC1_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC1_QPC0_AXUSER_QPC_REQ_BASE 0x549FE20ull +#define NIC1_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC1_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC1_QPC0_SPECIAL_BASE 0x549FE80ull +#define NIC1_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_QPC0_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_0_UNSECURE_DOORBELL0_BASE 0x54A0000ull +#define NIC1_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_0_UNSECURE_DOORBELL1_BASE 0x54A0080ull +#define NIC1_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x54A0100ull +#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x54A0180ull +#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_0_SPECIAL_BASE 0x54A0E80ull +#define NIC1_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_0_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_1_UNSECURE_DOORBELL0_BASE 0x54A1000ull +#define NIC1_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_1_UNSECURE_DOORBELL1_BASE 0x54A1080ull +#define NIC1_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x54A1100ull +#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x54A1180ull +#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_1_SPECIAL_BASE 0x54A1E80ull +#define NIC1_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_1_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_2_UNSECURE_DOORBELL0_BASE 0x54A2000ull +#define NIC1_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_2_UNSECURE_DOORBELL1_BASE 0x54A2080ull +#define NIC1_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x54A2100ull +#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x54A2180ull +#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_2_SPECIAL_BASE 0x54A2E80ull +#define NIC1_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_2_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_3_UNSECURE_DOORBELL0_BASE 0x54A3000ull +#define NIC1_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_3_UNSECURE_DOORBELL1_BASE 0x54A3080ull +#define NIC1_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x54A3100ull +#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x54A3180ull +#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_3_SPECIAL_BASE 0x54A3E80ull +#define NIC1_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_3_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_4_UNSECURE_DOORBELL0_BASE 0x54A4000ull +#define NIC1_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_4_UNSECURE_DOORBELL1_BASE 0x54A4080ull +#define NIC1_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x54A4100ull +#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x54A4180ull +#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_4_SPECIAL_BASE 0x54A4E80ull +#define NIC1_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_4_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_5_UNSECURE_DOORBELL0_BASE 0x54A5000ull +#define NIC1_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_5_UNSECURE_DOORBELL1_BASE 0x54A5080ull +#define NIC1_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x54A5100ull +#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x54A5180ull +#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_5_SPECIAL_BASE 0x54A5E80ull +#define NIC1_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_5_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_6_UNSECURE_DOORBELL0_BASE 0x54A6000ull +#define NIC1_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_6_UNSECURE_DOORBELL1_BASE 0x54A6080ull +#define NIC1_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x54A6100ull +#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x54A6180ull +#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_6_SPECIAL_BASE 0x54A6E80ull +#define NIC1_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_6_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_7_UNSECURE_DOORBELL0_BASE 0x54A7000ull +#define NIC1_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_7_UNSECURE_DOORBELL1_BASE 0x54A7080ull +#define NIC1_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x54A7100ull +#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x54A7180ull +#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_7_SPECIAL_BASE 0x54A7E80ull +#define NIC1_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_7_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_8_UNSECURE_DOORBELL0_BASE 0x54A8000ull +#define NIC1_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_8_UNSECURE_DOORBELL1_BASE 0x54A8080ull +#define NIC1_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x54A8100ull +#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x54A8180ull +#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_8_SPECIAL_BASE 0x54A8E80ull +#define NIC1_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_8_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_9_UNSECURE_DOORBELL0_BASE 0x54A9000ull +#define NIC1_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_9_UNSECURE_DOORBELL1_BASE 0x54A9080ull +#define NIC1_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x54A9100ull +#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x54A9180ull +#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_9_SPECIAL_BASE 0x54A9E80ull +#define NIC1_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_9_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_10_UNSECURE_DOORBELL0_BASE 0x54AA000ull +#define NIC1_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_10_UNSECURE_DOORBELL1_BASE 0x54AA080ull +#define NIC1_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x54AA100ull +#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x54AA180ull +#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_10_SPECIAL_BASE 0x54AAE80ull +#define NIC1_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_10_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_11_UNSECURE_DOORBELL0_BASE 0x54AB000ull +#define NIC1_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_11_UNSECURE_DOORBELL1_BASE 0x54AB080ull +#define NIC1_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x54AB100ull +#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x54AB180ull +#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_11_SPECIAL_BASE 0x54ABE80ull +#define NIC1_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_11_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_12_UNSECURE_DOORBELL0_BASE 0x54AC000ull +#define NIC1_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_12_UNSECURE_DOORBELL1_BASE 0x54AC080ull +#define NIC1_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x54AC100ull +#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x54AC180ull +#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_12_SPECIAL_BASE 0x54ACE80ull +#define NIC1_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_12_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_13_UNSECURE_DOORBELL0_BASE 0x54AD000ull +#define NIC1_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_13_UNSECURE_DOORBELL1_BASE 0x54AD080ull +#define NIC1_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x54AD100ull +#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x54AD180ull +#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_13_SPECIAL_BASE 0x54ADE80ull +#define NIC1_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_13_SPECIAL_SECTION 0x1800 +#define mmNIC1_UMR1_14_UNSECURE_DOORBELL0_BASE 0x54AE000ull +#define NIC1_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC1_UMR1_14_UNSECURE_DOORBELL1_BASE 0x54AE080ull +#define NIC1_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC1_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x54AE100ull +#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC1_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x54AE180ull +#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC1_UMR1_14_SPECIAL_BASE 0x54AEE80ull +#define NIC1_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_14_SPECIAL_SECTION 0x1180 +#define mmNIC1_QM_DCCM1_BASE 0x54B0000ull +#define NIC1_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC1_QM_DCCM1_SECTION 0x8000 +#define mmNIC1_QM_ARC_AUX1_BASE 0x54B8000ull +#define NIC1_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC1_QM_ARC_AUX1_SECTION 0xE800 +#define mmNIC1_QM_ARC_AUX1_SPECIAL_BASE 0x54B8E80ull +#define NIC1_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 +#define mmNIC1_QM1_BASE 0x54BA000ull +#define NIC1_QM1_MAX_OFFSET 0x1000 +#define NIC1_QM1_SECTION 0x9000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x54BA900ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x54BA908ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x54BA910ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x54BA918ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x54BA920ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x54BA928ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x54BA930ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x54BA938ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x54BA940ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x54BA948ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x54BA950ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x54BA958ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x54BA960ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x54BA968ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x54BA970ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x54BA978ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC1_QM1_AXUSER_SECURED_BASE 0x54BAB00ull +#define NIC1_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC1_QM1_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC1_QM1_AXUSER_NONSECURED_BASE 0x54BAB80ull +#define NIC1_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC1_QM1_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC1_QM1_DBG_HBW_BASE 0x54BAC00ull +#define NIC1_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC1_QM1_DBG_HBW_SECTION 0x8000 +#define mmNIC1_QM1_DBG_LBW_BASE 0x54BAC80ull +#define NIC1_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC1_QM1_DBG_LBW_SECTION 0x1000 +#define mmNIC1_QM1_CGM_BASE 0x54BAD80ull +#define NIC1_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC1_QM1_CGM_SECTION 0x1000 +#define mmNIC1_QM1_SPECIAL_BASE 0x54BAE80ull +#define NIC1_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_QM1_SPECIAL_SECTION 0x4180 +#define mmNIC1_QPC1_BASE 0x54BF000ull +#define NIC1_QPC1_MAX_OFFSET 0x1000 +#define NIC1_QPC1_SECTION 0x7200 +#define mmNIC1_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x54BF720ull +#define NIC1_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x54BF728ull +#define NIC1_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x54BF730ull +#define NIC1_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x54BF738ull +#define NIC1_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x54BF740ull +#define NIC1_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x54BF748ull +#define NIC1_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x54BF750ull +#define NIC1_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x54BF758ull +#define NIC1_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x54BF760ull +#define NIC1_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x54BF768ull +#define NIC1_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x54BF770ull +#define NIC1_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x54BF778ull +#define NIC1_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x54BF780ull +#define NIC1_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x54BF788ull +#define NIC1_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x54BF790ull +#define NIC1_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x54BF798ull +#define NIC1_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x54BF7A0ull +#define NIC1_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x54BF7A8ull +#define NIC1_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x54BF7B0ull +#define NIC1_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x54BF7B8ull +#define NIC1_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x54BF7C0ull +#define NIC1_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x54BF7C8ull +#define NIC1_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x54BF7D0ull +#define NIC1_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x54BF7D8ull +#define NIC1_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x54BF7E0ull +#define NIC1_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x54BF7E8ull +#define NIC1_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x54BF7F0ull +#define NIC1_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x54BF7F8ull +#define NIC1_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x54BF800ull +#define NIC1_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x54BF808ull +#define NIC1_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x54BF810ull +#define NIC1_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC1_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x54BF818ull +#define NIC1_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC1_QPC1_AXUSER_CONG_QUE_BASE 0x54BFB80ull +#define NIC1_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC1_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC1_QPC1_AXUSER_RXWQE_BASE 0x54BFBE0ull +#define NIC1_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC1_QPC1_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC1_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x54BFC40ull +#define NIC1_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC1_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC1_QPC1_AXUSER_DB_FIFO_BASE 0x54BFCA0ull +#define NIC1_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC1_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC1_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x54BFD00ull +#define NIC1_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC1_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC1_QPC1_AXUSER_ERR_FIFO_BASE 0x54BFD60ull +#define NIC1_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC1_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC1_QPC1_AXUSER_QPC_RESP_BASE 0x54BFDC0ull +#define NIC1_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC1_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC1_QPC1_AXUSER_QPC_REQ_BASE 0x54BFE20ull +#define NIC1_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC1_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC1_QPC1_SPECIAL_BASE 0x54BFE80ull +#define NIC1_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_QPC1_SPECIAL_SECTION 0x8180 +#define mmNIC1_TMR_BASE 0x54C8000ull +#define NIC1_TMR_MAX_OFFSET 0x1000 +#define NIC1_TMR_SECTION 0xD600 +#define mmNIC1_TMR_AXUSER_TMR_FREE_LIST_BASE 0x54C8D60ull +#define NIC1_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC1_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 +#define mmNIC1_TMR_AXUSER_TMR_FIFO_BASE 0x54C8DC0ull +#define NIC1_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC1_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 +#define mmNIC1_TMR_AXUSER_TMR_FSM_BASE 0x54C8E20ull +#define NIC1_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC1_TMR_AXUSER_TMR_FSM_SECTION 0x6000 +#define mmNIC1_TMR_SPECIAL_BASE 0x54C8E80ull +#define NIC1_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_TMR_SPECIAL_SECTION 0x1800 +#define mmNIC1_RXB_CORE_BASE 0x54C9000ull +#define NIC1_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC1_RXB_CORE_SECTION 0x6100 +#define mmNIC1_RXB_CORE_SCT_AWUSER_BASE 0x54C9610ull +#define NIC1_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC1_RXB_CORE_SCT_AWUSER_SECTION 0x8700 +#define mmNIC1_RXB_CORE_SPECIAL_BASE 0x54C9E80ull +#define NIC1_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_RXB_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC1_RXE0_BASE 0x54CA000ull +#define NIC1_RXE0_MAX_OFFSET 0x1000 +#define NIC1_RXE0_SECTION 0x9000 +#define mmNIC1_RXE0_WQE_ARUSER_BASE 0x54CA900ull +#define NIC1_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC1_RXE0_WQE_ARUSER_SECTION 0x5800 +#define mmNIC1_RXE0_SPECIAL_BASE 0x54CAE80ull +#define NIC1_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_RXE0_SPECIAL_SECTION 0x1800 +#define mmNIC1_RXE1_BASE 0x54CB000ull +#define NIC1_RXE1_MAX_OFFSET 0x1000 +#define NIC1_RXE1_SECTION 0x9000 +#define mmNIC1_RXE1_WQE_ARUSER_BASE 0x54CB900ull +#define NIC1_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC1_RXE1_WQE_ARUSER_SECTION 0x5800 +#define mmNIC1_RXE1_SPECIAL_BASE 0x54CBE80ull +#define NIC1_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_RXE1_SPECIAL_SECTION 0x1800 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ0_BASE 0x54CC000ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ1_BASE 0x54CC050ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ2_BASE 0x54CC0A0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ3_BASE 0x54CC0F0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ4_BASE 0x54CC140ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ5_BASE 0x54CC190ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ6_BASE 0x54CC1E0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ7_BASE 0x54CC230ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ8_BASE 0x54CC280ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ9_BASE 0x54CC2D0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ10_BASE 0x54CC320ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ11_BASE 0x54CC370ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ12_BASE 0x54CC3C0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ13_BASE 0x54CC410ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ14_BASE 0x54CC460ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ15_BASE 0x54CC4B0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ16_BASE 0x54CC500ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ17_BASE 0x54CC550ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ18_BASE 0x54CC5A0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ19_BASE 0x54CC5F0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ20_BASE 0x54CC640ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ21_BASE 0x54CC690ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ22_BASE 0x54CC6E0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ23_BASE 0x54CC730ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ24_BASE 0x54CC780ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ25_BASE 0x54CC7D0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ26_BASE 0x54CC820ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ27_BASE 0x54CC870ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ28_BASE 0x54CC8C0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ29_BASE 0x54CC910ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ30_BASE 0x54CC960ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ31_BASE 0x54CC9B0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC1_RXE0_AXUSER_SPECIAL_BASE 0x54CCE80ull +#define NIC1_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_RXE0_AXUSER_SPECIAL_SECTION 0x1800 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ0_BASE 0x54CD000ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ1_BASE 0x54CD050ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ2_BASE 0x54CD0A0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ3_BASE 0x54CD0F0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ4_BASE 0x54CD140ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ5_BASE 0x54CD190ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ6_BASE 0x54CD1E0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ7_BASE 0x54CD230ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ8_BASE 0x54CD280ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ9_BASE 0x54CD2D0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ10_BASE 0x54CD320ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ11_BASE 0x54CD370ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ12_BASE 0x54CD3C0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ13_BASE 0x54CD410ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ14_BASE 0x54CD460ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ15_BASE 0x54CD4B0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ16_BASE 0x54CD500ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ17_BASE 0x54CD550ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ18_BASE 0x54CD5A0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ19_BASE 0x54CD5F0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ20_BASE 0x54CD640ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ21_BASE 0x54CD690ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ22_BASE 0x54CD6E0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ23_BASE 0x54CD730ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ24_BASE 0x54CD780ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ25_BASE 0x54CD7D0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ26_BASE 0x54CD820ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ27_BASE 0x54CD870ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ28_BASE 0x54CD8C0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ29_BASE 0x54CD910ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ30_BASE 0x54CD960ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ31_BASE 0x54CD9B0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC1_RXE1_AXUSER_SPECIAL_BASE 0x54CDE80ull +#define NIC1_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_RXE1_AXUSER_SPECIAL_SECTION 0x2180 +#define mmNIC1_TXS0_BASE 0x54D0000ull +#define NIC1_TXS0_MAX_OFFSET 0x1000 +#define NIC1_TXS0_SECTION 0xE800 +#define mmNIC1_TXS0_SPECIAL_BASE 0x54D0E80ull +#define NIC1_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_TXS0_SPECIAL_SECTION 0x1800 +#define mmNIC1_TXS1_BASE 0x54D1000ull +#define NIC1_TXS1_MAX_OFFSET 0x1000 +#define NIC1_TXS1_SECTION 0xE800 +#define mmNIC1_TXS1_SPECIAL_BASE 0x54D1E80ull +#define NIC1_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_TXS1_SPECIAL_SECTION 0x1800 +#define mmNIC1_TXE0_BASE 0x54D2000ull +#define NIC1_TXE0_MAX_OFFSET 0x1000 +#define NIC1_TXE0_SECTION 0xE800 +#define mmNIC1_TXE0_SPECIAL_BASE 0x54D2E80ull +#define NIC1_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_TXE0_SPECIAL_SECTION 0x1800 +#define mmNIC1_TXE1_BASE 0x54D3000ull +#define NIC1_TXE1_MAX_OFFSET 0x1000 +#define NIC1_TXE1_SECTION 0xE800 +#define mmNIC1_TXE1_SPECIAL_BASE 0x54D3E80ull +#define NIC1_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_TXE1_SPECIAL_SECTION 0x1800 +#define mmNIC1_TXB_BASE 0x54D4000ull +#define NIC1_TXB_MAX_OFFSET 0x1000 +#define NIC1_TXB_SECTION 0xE800 +#define mmNIC1_TXB_SPECIAL_BASE 0x54D4E80ull +#define NIC1_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_TXB_SPECIAL_SECTION 0x1800 +#define mmNIC1_MSTR_IF_RR_SHRD_HBW_BASE 0x54D5000ull +#define NIC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmNIC1_MSTR_IF_RR_PRVT_HBW_BASE 0x54D5200ull +#define NIC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmNIC1_MSTR_IF_RR_SHRD_LBW_BASE 0x54D5400ull +#define NIC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmNIC1_MSTR_IF_RR_PRVT_LBW_BASE 0x54D5600ull +#define NIC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmNIC1_MSTR_IF_E2E_CRDT_BASE 0x54D5800ull +#define NIC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmNIC1_MSTR_IF_AXUSER_BASE 0x54D5A80ull +#define NIC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC1_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmNIC1_MSTR_IF_DBG_HBW_BASE 0x54D5B00ull +#define NIC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC1_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmNIC1_MSTR_IF_DBG_LBW_BASE 0x54D5B80ull +#define NIC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC1_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmNIC1_MSTR_IF_CORE_HBW_BASE 0x54D5C00ull +#define NIC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC1_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmNIC1_MSTR_IF_CORE_LBW_BASE 0x54D5D80ull +#define NIC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC1_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmNIC1_MSTR_IF_SPECIAL_BASE 0x54D5E80ull +#define NIC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmNIC1_TX_AXUSER_BASE 0x54D6000ull +#define NIC1_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC1_TX_AXUSER_SECTION 0x2000 +#define mmNIC1_SERDES0_BASE 0x54D8000ull +#define NIC1_SERDES0_MAX_OFFSET 0x3E40 +#define NIC1_SERDES0_SECTION 0x4000 +#define mmNIC1_SERDES1_BASE 0x54DC000ull +#define NIC1_SERDES1_MAX_OFFSET 0x3E40 +#define NIC1_SERDES1_SECTION 0x4000 +#define mmNIC1_PHY_BASE 0x54E0000ull +#define NIC1_PHY_MAX_OFFSET 0x1000 +#define NIC1_PHY_SECTION 0xE800 +#define mmNIC1_PHY_SPECIAL_BASE 0x54E0E80ull +#define NIC1_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_PHY_SPECIAL_SECTION 0x7180 +#define mmPRT1_MAC_AUX_BASE 0x54E8000ull +#define PRT1_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT1_MAC_AUX_SECTION 0xE800 +#define mmPRT1_MAC_AUX_SPECIAL_BASE 0x54E8E80ull +#define PRT1_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT1_MAC_AUX_SPECIAL_SECTION 0x1800 +#define mmPRT1_MAC_CORE_BASE 0x54E9000ull +#define PRT1_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT1_MAC_CORE_SECTION 0xE800 +#define mmPRT1_MAC_CORE_SPECIAL_BASE 0x54E9E80ull +#define PRT1_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT1_MAC_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC1_MAC_RS_FEC_BASE 0x54EA000ull +#define NIC1_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC1_MAC_RS_FEC_SECTION 0x1000 +#define mmNIC1_MAC_GLOB_STAT_CONTROL_REG_BASE 0x54EB000ull +#define NIC1_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000 +#define NIC1_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000 +#define mmNIC1_MAC_GLOB_STAT_RX0_BASE 0x54EB100ull +#define NIC1_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00 +#define NIC1_MAC_GLOB_STAT_RX0_SECTION 0x8C00 +#define mmNIC1_MAC_GLOB_STAT_RX1_BASE 0x54EB18Cull +#define NIC1_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00 +#define NIC1_MAC_GLOB_STAT_RX1_SECTION 0x8C00 +#define mmNIC1_MAC_GLOB_STAT_RX2_BASE 0x54EB218ull +#define NIC1_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00 +#define NIC1_MAC_GLOB_STAT_RX2_SECTION 0x8C00 +#define mmNIC1_MAC_GLOB_STAT_RX3_BASE 0x54EB2A4ull +#define NIC1_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00 +#define NIC1_MAC_GLOB_STAT_RX3_SECTION 0x8C00 +#define mmNIC1_MAC_GLOB_STAT_TX0_BASE 0x54EB330ull +#define NIC1_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800 +#define NIC1_MAC_GLOB_STAT_TX0_SECTION 0x6800 +#define mmNIC1_MAC_GLOB_STAT_TX1_BASE 0x54EB398ull +#define NIC1_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800 +#define NIC1_MAC_GLOB_STAT_TX1_SECTION 0x6800 +#define mmNIC1_MAC_GLOB_STAT_TX2_BASE 0x54EB400ull +#define NIC1_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800 +#define NIC1_MAC_GLOB_STAT_TX2_SECTION 0x6800 +#define mmNIC1_MAC_GLOB_STAT_TX3_BASE 0x54EB468ull +#define NIC1_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800 +#define NIC1_MAC_GLOB_STAT_TX3_SECTION 0x3980 +#define mmNIC1_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x54EB800ull +#define NIC1_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC1_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000 +#define mmNIC1_MAC_CH0_MAC_PCS_BASE 0x54EC000ull +#define NIC1_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC1_MAC_CH0_MAC_PCS_SECTION 0x4000 +#define mmNIC1_MAC_CH0_MAC_128_BASE 0x54EC400ull +#define NIC1_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC1_MAC_CH0_MAC_128_SECTION 0x4000 +#define mmNIC1_MAC_CH0_MAC_AN_BASE 0x54EC800ull +#define NIC1_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC1_MAC_CH0_MAC_AN_SECTION 0x8000 +#define mmNIC1_MAC_CH1_MAC_PCS_BASE 0x54ED000ull +#define NIC1_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC1_MAC_CH1_MAC_PCS_SECTION 0x4000 +#define mmNIC1_MAC_CH1_MAC_128_BASE 0x54ED400ull +#define NIC1_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC1_MAC_CH1_MAC_128_SECTION 0x4000 +#define mmNIC1_MAC_CH1_MAC_AN_BASE 0x54ED800ull +#define NIC1_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC1_MAC_CH1_MAC_AN_SECTION 0x8000 +#define mmNIC1_MAC_CH2_MAC_PCS_BASE 0x54EE000ull +#define NIC1_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC1_MAC_CH2_MAC_PCS_SECTION 0x4000 +#define mmNIC1_MAC_CH2_MAC_128_BASE 0x54EE400ull +#define NIC1_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC1_MAC_CH2_MAC_128_SECTION 0x4000 +#define mmNIC1_MAC_CH2_MAC_AN_BASE 0x54EE800ull +#define NIC1_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC1_MAC_CH2_MAC_AN_SECTION 0x8000 +#define mmNIC1_MAC_CH3_MAC_PCS_BASE 0x54EF000ull +#define NIC1_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC1_MAC_CH3_MAC_PCS_SECTION 0x4000 +#define mmNIC1_MAC_CH3_MAC_128_BASE 0x54EF400ull +#define NIC1_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC1_MAC_CH3_MAC_128_SECTION 0x4000 +#define mmNIC1_MAC_CH3_MAC_AN_BASE 0x54EF800ull +#define NIC1_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC1_MAC_CH3_MAC_AN_SECTION 0x10800 +#define mmNIC2_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5500000ull +#define NIC2_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5500080ull +#define NIC2_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5500100ull +#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5500180ull +#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_0_SPECIAL_BASE 0x5500E80ull +#define NIC2_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_0_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5501000ull +#define NIC2_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5501080ull +#define NIC2_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5501100ull +#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5501180ull +#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_1_SPECIAL_BASE 0x5501E80ull +#define NIC2_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_1_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5502000ull +#define NIC2_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5502080ull +#define NIC2_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5502100ull +#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5502180ull +#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_2_SPECIAL_BASE 0x5502E80ull +#define NIC2_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_2_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5503000ull +#define NIC2_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5503080ull +#define NIC2_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5503100ull +#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5503180ull +#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_3_SPECIAL_BASE 0x5503E80ull +#define NIC2_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_3_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5504000ull +#define NIC2_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5504080ull +#define NIC2_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5504100ull +#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5504180ull +#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_4_SPECIAL_BASE 0x5504E80ull +#define NIC2_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_4_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5505000ull +#define NIC2_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5505080ull +#define NIC2_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5505100ull +#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5505180ull +#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_5_SPECIAL_BASE 0x5505E80ull +#define NIC2_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_5_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5506000ull +#define NIC2_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5506080ull +#define NIC2_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5506100ull +#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5506180ull +#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_6_SPECIAL_BASE 0x5506E80ull +#define NIC2_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_6_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5507000ull +#define NIC2_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5507080ull +#define NIC2_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5507100ull +#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5507180ull +#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_7_SPECIAL_BASE 0x5507E80ull +#define NIC2_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_7_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5508000ull +#define NIC2_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5508080ull +#define NIC2_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5508100ull +#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5508180ull +#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_8_SPECIAL_BASE 0x5508E80ull +#define NIC2_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_8_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5509000ull +#define NIC2_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5509080ull +#define NIC2_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5509100ull +#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5509180ull +#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_9_SPECIAL_BASE 0x5509E80ull +#define NIC2_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_9_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_10_UNSECURE_DOORBELL0_BASE 0x550A000ull +#define NIC2_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_10_UNSECURE_DOORBELL1_BASE 0x550A080ull +#define NIC2_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x550A100ull +#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x550A180ull +#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_10_SPECIAL_BASE 0x550AE80ull +#define NIC2_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_10_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_11_UNSECURE_DOORBELL0_BASE 0x550B000ull +#define NIC2_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_11_UNSECURE_DOORBELL1_BASE 0x550B080ull +#define NIC2_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x550B100ull +#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x550B180ull +#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_11_SPECIAL_BASE 0x550BE80ull +#define NIC2_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_11_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_12_UNSECURE_DOORBELL0_BASE 0x550C000ull +#define NIC2_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_12_UNSECURE_DOORBELL1_BASE 0x550C080ull +#define NIC2_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x550C100ull +#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x550C180ull +#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_12_SPECIAL_BASE 0x550CE80ull +#define NIC2_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_12_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_13_UNSECURE_DOORBELL0_BASE 0x550D000ull +#define NIC2_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_13_UNSECURE_DOORBELL1_BASE 0x550D080ull +#define NIC2_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x550D100ull +#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x550D180ull +#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_13_SPECIAL_BASE 0x550DE80ull +#define NIC2_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_13_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR0_14_UNSECURE_DOORBELL0_BASE 0x550E000ull +#define NIC2_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR0_14_UNSECURE_DOORBELL1_BASE 0x550E080ull +#define NIC2_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x550E100ull +#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x550E180ull +#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR0_14_SPECIAL_BASE 0x550EE80ull +#define NIC2_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_14_SPECIAL_SECTION 0x1180 +#define mmNIC2_QM_DCCM0_BASE 0x5510000ull +#define NIC2_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC2_QM_DCCM0_SECTION 0x8000 +#define mmNIC2_QM_ARC_AUX0_BASE 0x5518000ull +#define NIC2_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC2_QM_ARC_AUX0_SECTION 0xE800 +#define mmNIC2_QM_ARC_AUX0_SPECIAL_BASE 0x5518E80ull +#define NIC2_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 +#define mmNIC2_QM0_BASE 0x551A000ull +#define NIC2_QM0_MAX_OFFSET 0x1000 +#define NIC2_QM0_SECTION 0x9000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x551A900ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x551A908ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x551A910ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x551A918ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x551A920ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x551A928ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x551A930ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x551A938ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x551A940ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x551A948ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x551A950ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x551A958ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x551A960ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x551A968ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x551A970ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x551A978ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC2_QM0_AXUSER_SECURED_BASE 0x551AB00ull +#define NIC2_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC2_QM0_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC2_QM0_AXUSER_NONSECURED_BASE 0x551AB80ull +#define NIC2_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC2_QM0_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC2_QM0_DBG_HBW_BASE 0x551AC00ull +#define NIC2_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC2_QM0_DBG_HBW_SECTION 0x8000 +#define mmNIC2_QM0_DBG_LBW_BASE 0x551AC80ull +#define NIC2_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC2_QM0_DBG_LBW_SECTION 0x1000 +#define mmNIC2_QM0_CGM_BASE 0x551AD80ull +#define NIC2_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC2_QM0_CGM_SECTION 0x1000 +#define mmNIC2_QM0_SPECIAL_BASE 0x551AE80ull +#define NIC2_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_QM0_SPECIAL_SECTION 0x4180 +#define mmNIC2_QPC0_BASE 0x551F000ull +#define NIC2_QPC0_MAX_OFFSET 0x1000 +#define NIC2_QPC0_SECTION 0x7200 +#define mmNIC2_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x551F720ull +#define NIC2_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x551F728ull +#define NIC2_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x551F730ull +#define NIC2_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x551F738ull +#define NIC2_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x551F740ull +#define NIC2_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x551F748ull +#define NIC2_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x551F750ull +#define NIC2_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x551F758ull +#define NIC2_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x551F760ull +#define NIC2_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x551F768ull +#define NIC2_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x551F770ull +#define NIC2_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x551F778ull +#define NIC2_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x551F780ull +#define NIC2_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x551F788ull +#define NIC2_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x551F790ull +#define NIC2_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x551F798ull +#define NIC2_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x551F7A0ull +#define NIC2_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x551F7A8ull +#define NIC2_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x551F7B0ull +#define NIC2_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x551F7B8ull +#define NIC2_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x551F7C0ull +#define NIC2_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x551F7C8ull +#define NIC2_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x551F7D0ull +#define NIC2_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x551F7D8ull +#define NIC2_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x551F7E0ull +#define NIC2_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x551F7E8ull +#define NIC2_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x551F7F0ull +#define NIC2_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x551F7F8ull +#define NIC2_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x551F800ull +#define NIC2_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x551F808ull +#define NIC2_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x551F810ull +#define NIC2_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x551F818ull +#define NIC2_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC2_QPC0_AXUSER_CONG_QUE_BASE 0x551FB80ull +#define NIC2_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC2_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC2_QPC0_AXUSER_RXWQE_BASE 0x551FBE0ull +#define NIC2_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC2_QPC0_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC2_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x551FC40ull +#define NIC2_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC2_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC2_QPC0_AXUSER_DB_FIFO_BASE 0x551FCA0ull +#define NIC2_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC2_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC2_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x551FD00ull +#define NIC2_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC2_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC2_QPC0_AXUSER_ERR_FIFO_BASE 0x551FD60ull +#define NIC2_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC2_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC2_QPC0_AXUSER_QPC_RESP_BASE 0x551FDC0ull +#define NIC2_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC2_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC2_QPC0_AXUSER_QPC_REQ_BASE 0x551FE20ull +#define NIC2_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC2_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC2_QPC0_SPECIAL_BASE 0x551FE80ull +#define NIC2_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_QPC0_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5520000ull +#define NIC2_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5520080ull +#define NIC2_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5520100ull +#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5520180ull +#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_0_SPECIAL_BASE 0x5520E80ull +#define NIC2_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_0_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5521000ull +#define NIC2_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5521080ull +#define NIC2_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5521100ull +#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5521180ull +#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_1_SPECIAL_BASE 0x5521E80ull +#define NIC2_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_1_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5522000ull +#define NIC2_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5522080ull +#define NIC2_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5522100ull +#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5522180ull +#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_2_SPECIAL_BASE 0x5522E80ull +#define NIC2_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_2_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5523000ull +#define NIC2_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5523080ull +#define NIC2_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5523100ull +#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5523180ull +#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_3_SPECIAL_BASE 0x5523E80ull +#define NIC2_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_3_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5524000ull +#define NIC2_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5524080ull +#define NIC2_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5524100ull +#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5524180ull +#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_4_SPECIAL_BASE 0x5524E80ull +#define NIC2_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_4_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5525000ull +#define NIC2_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5525080ull +#define NIC2_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5525100ull +#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5525180ull +#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_5_SPECIAL_BASE 0x5525E80ull +#define NIC2_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_5_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5526000ull +#define NIC2_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5526080ull +#define NIC2_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5526100ull +#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5526180ull +#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_6_SPECIAL_BASE 0x5526E80ull +#define NIC2_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_6_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5527000ull +#define NIC2_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5527080ull +#define NIC2_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5527100ull +#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5527180ull +#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_7_SPECIAL_BASE 0x5527E80ull +#define NIC2_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_7_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5528000ull +#define NIC2_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5528080ull +#define NIC2_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5528100ull +#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5528180ull +#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_8_SPECIAL_BASE 0x5528E80ull +#define NIC2_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_8_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5529000ull +#define NIC2_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5529080ull +#define NIC2_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5529100ull +#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5529180ull +#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_9_SPECIAL_BASE 0x5529E80ull +#define NIC2_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_9_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_10_UNSECURE_DOORBELL0_BASE 0x552A000ull +#define NIC2_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_10_UNSECURE_DOORBELL1_BASE 0x552A080ull +#define NIC2_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x552A100ull +#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x552A180ull +#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_10_SPECIAL_BASE 0x552AE80ull +#define NIC2_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_10_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_11_UNSECURE_DOORBELL0_BASE 0x552B000ull +#define NIC2_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_11_UNSECURE_DOORBELL1_BASE 0x552B080ull +#define NIC2_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x552B100ull +#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x552B180ull +#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_11_SPECIAL_BASE 0x552BE80ull +#define NIC2_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_11_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_12_UNSECURE_DOORBELL0_BASE 0x552C000ull +#define NIC2_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_12_UNSECURE_DOORBELL1_BASE 0x552C080ull +#define NIC2_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x552C100ull +#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x552C180ull +#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_12_SPECIAL_BASE 0x552CE80ull +#define NIC2_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_12_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_13_UNSECURE_DOORBELL0_BASE 0x552D000ull +#define NIC2_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_13_UNSECURE_DOORBELL1_BASE 0x552D080ull +#define NIC2_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x552D100ull +#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x552D180ull +#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_13_SPECIAL_BASE 0x552DE80ull +#define NIC2_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_13_SPECIAL_SECTION 0x1800 +#define mmNIC2_UMR1_14_UNSECURE_DOORBELL0_BASE 0x552E000ull +#define NIC2_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC2_UMR1_14_UNSECURE_DOORBELL1_BASE 0x552E080ull +#define NIC2_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC2_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x552E100ull +#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC2_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x552E180ull +#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC2_UMR1_14_SPECIAL_BASE 0x552EE80ull +#define NIC2_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_14_SPECIAL_SECTION 0x1180 +#define mmNIC2_QM_DCCM1_BASE 0x5530000ull +#define NIC2_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC2_QM_DCCM1_SECTION 0x8000 +#define mmNIC2_QM_ARC_AUX1_BASE 0x5538000ull +#define NIC2_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC2_QM_ARC_AUX1_SECTION 0xE800 +#define mmNIC2_QM_ARC_AUX1_SPECIAL_BASE 0x5538E80ull +#define NIC2_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 +#define mmNIC2_QM1_BASE 0x553A000ull +#define NIC2_QM1_MAX_OFFSET 0x1000 +#define NIC2_QM1_SECTION 0x9000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x553A900ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x553A908ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x553A910ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x553A918ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x553A920ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x553A928ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x553A930ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x553A938ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x553A940ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x553A948ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x553A950ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x553A958ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x553A960ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x553A968ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x553A970ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x553A978ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC2_QM1_AXUSER_SECURED_BASE 0x553AB00ull +#define NIC2_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC2_QM1_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC2_QM1_AXUSER_NONSECURED_BASE 0x553AB80ull +#define NIC2_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC2_QM1_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC2_QM1_DBG_HBW_BASE 0x553AC00ull +#define NIC2_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC2_QM1_DBG_HBW_SECTION 0x8000 +#define mmNIC2_QM1_DBG_LBW_BASE 0x553AC80ull +#define NIC2_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC2_QM1_DBG_LBW_SECTION 0x1000 +#define mmNIC2_QM1_CGM_BASE 0x553AD80ull +#define NIC2_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC2_QM1_CGM_SECTION 0x1000 +#define mmNIC2_QM1_SPECIAL_BASE 0x553AE80ull +#define NIC2_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_QM1_SPECIAL_SECTION 0x4180 +#define mmNIC2_QPC1_BASE 0x553F000ull +#define NIC2_QPC1_MAX_OFFSET 0x1000 +#define NIC2_QPC1_SECTION 0x7200 +#define mmNIC2_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x553F720ull +#define NIC2_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x553F728ull +#define NIC2_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x553F730ull +#define NIC2_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x553F738ull +#define NIC2_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x553F740ull +#define NIC2_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x553F748ull +#define NIC2_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x553F750ull +#define NIC2_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x553F758ull +#define NIC2_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x553F760ull +#define NIC2_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x553F768ull +#define NIC2_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x553F770ull +#define NIC2_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x553F778ull +#define NIC2_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x553F780ull +#define NIC2_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x553F788ull +#define NIC2_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x553F790ull +#define NIC2_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x553F798ull +#define NIC2_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x553F7A0ull +#define NIC2_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x553F7A8ull +#define NIC2_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x553F7B0ull +#define NIC2_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x553F7B8ull +#define NIC2_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x553F7C0ull +#define NIC2_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x553F7C8ull +#define NIC2_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x553F7D0ull +#define NIC2_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x553F7D8ull +#define NIC2_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x553F7E0ull +#define NIC2_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x553F7E8ull +#define NIC2_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x553F7F0ull +#define NIC2_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x553F7F8ull +#define NIC2_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x553F800ull +#define NIC2_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x553F808ull +#define NIC2_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x553F810ull +#define NIC2_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC2_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x553F818ull +#define NIC2_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC2_QPC1_AXUSER_CONG_QUE_BASE 0x553FB80ull +#define NIC2_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC2_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC2_QPC1_AXUSER_RXWQE_BASE 0x553FBE0ull +#define NIC2_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC2_QPC1_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC2_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x553FC40ull +#define NIC2_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC2_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC2_QPC1_AXUSER_DB_FIFO_BASE 0x553FCA0ull +#define NIC2_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC2_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC2_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x553FD00ull +#define NIC2_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC2_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC2_QPC1_AXUSER_ERR_FIFO_BASE 0x553FD60ull +#define NIC2_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC2_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC2_QPC1_AXUSER_QPC_RESP_BASE 0x553FDC0ull +#define NIC2_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC2_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC2_QPC1_AXUSER_QPC_REQ_BASE 0x553FE20ull +#define NIC2_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC2_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC2_QPC1_SPECIAL_BASE 0x553FE80ull +#define NIC2_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_QPC1_SPECIAL_SECTION 0x8180 +#define mmNIC2_TMR_BASE 0x5548000ull +#define NIC2_TMR_MAX_OFFSET 0x1000 +#define NIC2_TMR_SECTION 0xD600 +#define mmNIC2_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5548D60ull +#define NIC2_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC2_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 +#define mmNIC2_TMR_AXUSER_TMR_FIFO_BASE 0x5548DC0ull +#define NIC2_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC2_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 +#define mmNIC2_TMR_AXUSER_TMR_FSM_BASE 0x5548E20ull +#define NIC2_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC2_TMR_AXUSER_TMR_FSM_SECTION 0x6000 +#define mmNIC2_TMR_SPECIAL_BASE 0x5548E80ull +#define NIC2_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_TMR_SPECIAL_SECTION 0x1800 +#define mmNIC2_RXB_CORE_BASE 0x5549000ull +#define NIC2_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC2_RXB_CORE_SECTION 0x6100 +#define mmNIC2_RXB_CORE_SCT_AWUSER_BASE 0x5549610ull +#define NIC2_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC2_RXB_CORE_SCT_AWUSER_SECTION 0x8700 +#define mmNIC2_RXB_CORE_SPECIAL_BASE 0x5549E80ull +#define NIC2_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_RXB_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC2_RXE0_BASE 0x554A000ull +#define NIC2_RXE0_MAX_OFFSET 0x1000 +#define NIC2_RXE0_SECTION 0x9000 +#define mmNIC2_RXE0_WQE_ARUSER_BASE 0x554A900ull +#define NIC2_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC2_RXE0_WQE_ARUSER_SECTION 0x5800 +#define mmNIC2_RXE0_SPECIAL_BASE 0x554AE80ull +#define NIC2_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_RXE0_SPECIAL_SECTION 0x1800 +#define mmNIC2_RXE1_BASE 0x554B000ull +#define NIC2_RXE1_MAX_OFFSET 0x1000 +#define NIC2_RXE1_SECTION 0x9000 +#define mmNIC2_RXE1_WQE_ARUSER_BASE 0x554B900ull +#define NIC2_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC2_RXE1_WQE_ARUSER_SECTION 0x5800 +#define mmNIC2_RXE1_SPECIAL_BASE 0x554BE80ull +#define NIC2_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_RXE1_SPECIAL_SECTION 0x1800 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ0_BASE 0x554C000ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ1_BASE 0x554C050ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ2_BASE 0x554C0A0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ3_BASE 0x554C0F0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ4_BASE 0x554C140ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ5_BASE 0x554C190ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ6_BASE 0x554C1E0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ7_BASE 0x554C230ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ8_BASE 0x554C280ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ9_BASE 0x554C2D0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ10_BASE 0x554C320ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ11_BASE 0x554C370ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ12_BASE 0x554C3C0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ13_BASE 0x554C410ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ14_BASE 0x554C460ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ15_BASE 0x554C4B0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ16_BASE 0x554C500ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ17_BASE 0x554C550ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ18_BASE 0x554C5A0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ19_BASE 0x554C5F0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ20_BASE 0x554C640ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ21_BASE 0x554C690ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ22_BASE 0x554C6E0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ23_BASE 0x554C730ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ24_BASE 0x554C780ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ25_BASE 0x554C7D0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ26_BASE 0x554C820ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ27_BASE 0x554C870ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ28_BASE 0x554C8C0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ29_BASE 0x554C910ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ30_BASE 0x554C960ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ31_BASE 0x554C9B0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC2_RXE0_AXUSER_SPECIAL_BASE 0x554CE80ull +#define NIC2_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_RXE0_AXUSER_SPECIAL_SECTION 0x1800 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ0_BASE 0x554D000ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ1_BASE 0x554D050ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ2_BASE 0x554D0A0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ3_BASE 0x554D0F0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ4_BASE 0x554D140ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ5_BASE 0x554D190ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ6_BASE 0x554D1E0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ7_BASE 0x554D230ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ8_BASE 0x554D280ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ9_BASE 0x554D2D0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ10_BASE 0x554D320ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ11_BASE 0x554D370ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ12_BASE 0x554D3C0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ13_BASE 0x554D410ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ14_BASE 0x554D460ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ15_BASE 0x554D4B0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ16_BASE 0x554D500ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ17_BASE 0x554D550ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ18_BASE 0x554D5A0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ19_BASE 0x554D5F0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ20_BASE 0x554D640ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ21_BASE 0x554D690ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ22_BASE 0x554D6E0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ23_BASE 0x554D730ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ24_BASE 0x554D780ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ25_BASE 0x554D7D0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ26_BASE 0x554D820ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ27_BASE 0x554D870ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ28_BASE 0x554D8C0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ29_BASE 0x554D910ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ30_BASE 0x554D960ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ31_BASE 0x554D9B0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC2_RXE1_AXUSER_SPECIAL_BASE 0x554DE80ull +#define NIC2_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_RXE1_AXUSER_SPECIAL_SECTION 0x2180 +#define mmNIC2_TXS0_BASE 0x5550000ull +#define NIC2_TXS0_MAX_OFFSET 0x1000 +#define NIC2_TXS0_SECTION 0xE800 +#define mmNIC2_TXS0_SPECIAL_BASE 0x5550E80ull +#define NIC2_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_TXS0_SPECIAL_SECTION 0x1800 +#define mmNIC2_TXS1_BASE 0x5551000ull +#define NIC2_TXS1_MAX_OFFSET 0x1000 +#define NIC2_TXS1_SECTION 0xE800 +#define mmNIC2_TXS1_SPECIAL_BASE 0x5551E80ull +#define NIC2_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_TXS1_SPECIAL_SECTION 0x1800 +#define mmNIC2_TXE0_BASE 0x5552000ull +#define NIC2_TXE0_MAX_OFFSET 0x1000 +#define NIC2_TXE0_SECTION 0xE800 +#define mmNIC2_TXE0_SPECIAL_BASE 0x5552E80ull +#define NIC2_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_TXE0_SPECIAL_SECTION 0x1800 +#define mmNIC2_TXE1_BASE 0x5553000ull +#define NIC2_TXE1_MAX_OFFSET 0x1000 +#define NIC2_TXE1_SECTION 0xE800 +#define mmNIC2_TXE1_SPECIAL_BASE 0x5553E80ull +#define NIC2_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_TXE1_SPECIAL_SECTION 0x1800 +#define mmNIC2_TXB_BASE 0x5554000ull +#define NIC2_TXB_MAX_OFFSET 0x1000 +#define NIC2_TXB_SECTION 0xE800 +#define mmNIC2_TXB_SPECIAL_BASE 0x5554E80ull +#define NIC2_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_TXB_SPECIAL_SECTION 0x1800 +#define mmNIC2_MSTR_IF_RR_SHRD_HBW_BASE 0x5555000ull +#define NIC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmNIC2_MSTR_IF_RR_PRVT_HBW_BASE 0x5555200ull +#define NIC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmNIC2_MSTR_IF_RR_SHRD_LBW_BASE 0x5555400ull +#define NIC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmNIC2_MSTR_IF_RR_PRVT_LBW_BASE 0x5555600ull +#define NIC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmNIC2_MSTR_IF_E2E_CRDT_BASE 0x5555800ull +#define NIC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC2_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmNIC2_MSTR_IF_AXUSER_BASE 0x5555A80ull +#define NIC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC2_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmNIC2_MSTR_IF_DBG_HBW_BASE 0x5555B00ull +#define NIC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC2_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmNIC2_MSTR_IF_DBG_LBW_BASE 0x5555B80ull +#define NIC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC2_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmNIC2_MSTR_IF_CORE_HBW_BASE 0x5555C00ull +#define NIC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC2_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmNIC2_MSTR_IF_CORE_LBW_BASE 0x5555D80ull +#define NIC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC2_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmNIC2_MSTR_IF_SPECIAL_BASE 0x5555E80ull +#define NIC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmNIC2_TX_AXUSER_BASE 0x5556000ull +#define NIC2_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC2_TX_AXUSER_SECTION 0x2000 +#define mmNIC2_SERDES0_BASE 0x5558000ull +#define NIC2_SERDES0_MAX_OFFSET 0x3E40 +#define NIC2_SERDES0_SECTION 0x4000 +#define mmNIC2_SERDES1_BASE 0x555C000ull +#define NIC2_SERDES1_MAX_OFFSET 0x3E40 +#define NIC2_SERDES1_SECTION 0x4000 +#define mmNIC2_PHY_BASE 0x5560000ull +#define NIC2_PHY_MAX_OFFSET 0x1000 +#define NIC2_PHY_SECTION 0xE800 +#define mmNIC2_PHY_SPECIAL_BASE 0x5560E80ull +#define NIC2_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_PHY_SPECIAL_SECTION 0x7180 +#define mmPRT2_MAC_AUX_BASE 0x5568000ull +#define PRT2_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT2_MAC_AUX_SECTION 0xE800 +#define mmPRT2_MAC_AUX_SPECIAL_BASE 0x5568E80ull +#define PRT2_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT2_MAC_AUX_SPECIAL_SECTION 0x1800 +#define mmPRT2_MAC_CORE_BASE 0x5569000ull +#define PRT2_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT2_MAC_CORE_SECTION 0xE800 +#define mmPRT2_MAC_CORE_SPECIAL_BASE 0x5569E80ull +#define PRT2_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT2_MAC_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC2_MAC_RS_FEC_BASE 0x556A000ull +#define NIC2_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC2_MAC_RS_FEC_SECTION 0x1000 +#define mmNIC2_MAC_GLOB_STAT_CONTROL_REG_BASE 0x556B000ull +#define NIC2_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000 +#define NIC2_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000 +#define mmNIC2_MAC_GLOB_STAT_RX0_BASE 0x556B100ull +#define NIC2_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00 +#define NIC2_MAC_GLOB_STAT_RX0_SECTION 0x8C00 +#define mmNIC2_MAC_GLOB_STAT_RX1_BASE 0x556B18Cull +#define NIC2_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00 +#define NIC2_MAC_GLOB_STAT_RX1_SECTION 0x8C00 +#define mmNIC2_MAC_GLOB_STAT_RX2_BASE 0x556B218ull +#define NIC2_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00 +#define NIC2_MAC_GLOB_STAT_RX2_SECTION 0x8C00 +#define mmNIC2_MAC_GLOB_STAT_RX3_BASE 0x556B2A4ull +#define NIC2_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00 +#define NIC2_MAC_GLOB_STAT_RX3_SECTION 0x8C00 +#define mmNIC2_MAC_GLOB_STAT_TX0_BASE 0x556B330ull +#define NIC2_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800 +#define NIC2_MAC_GLOB_STAT_TX0_SECTION 0x6800 +#define mmNIC2_MAC_GLOB_STAT_TX1_BASE 0x556B398ull +#define NIC2_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800 +#define NIC2_MAC_GLOB_STAT_TX1_SECTION 0x6800 +#define mmNIC2_MAC_GLOB_STAT_TX2_BASE 0x556B400ull +#define NIC2_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800 +#define NIC2_MAC_GLOB_STAT_TX2_SECTION 0x6800 +#define mmNIC2_MAC_GLOB_STAT_TX3_BASE 0x556B468ull +#define NIC2_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800 +#define NIC2_MAC_GLOB_STAT_TX3_SECTION 0x3980 +#define mmNIC2_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x556B800ull +#define NIC2_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC2_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000 +#define mmNIC2_MAC_CH0_MAC_PCS_BASE 0x556C000ull +#define NIC2_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC2_MAC_CH0_MAC_PCS_SECTION 0x4000 +#define mmNIC2_MAC_CH0_MAC_128_BASE 0x556C400ull +#define NIC2_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC2_MAC_CH0_MAC_128_SECTION 0x4000 +#define mmNIC2_MAC_CH0_MAC_AN_BASE 0x556C800ull +#define NIC2_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC2_MAC_CH0_MAC_AN_SECTION 0x8000 +#define mmNIC2_MAC_CH1_MAC_PCS_BASE 0x556D000ull +#define NIC2_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC2_MAC_CH1_MAC_PCS_SECTION 0x4000 +#define mmNIC2_MAC_CH1_MAC_128_BASE 0x556D400ull +#define NIC2_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC2_MAC_CH1_MAC_128_SECTION 0x4000 +#define mmNIC2_MAC_CH1_MAC_AN_BASE 0x556D800ull +#define NIC2_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC2_MAC_CH1_MAC_AN_SECTION 0x8000 +#define mmNIC2_MAC_CH2_MAC_PCS_BASE 0x556E000ull +#define NIC2_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC2_MAC_CH2_MAC_PCS_SECTION 0x4000 +#define mmNIC2_MAC_CH2_MAC_128_BASE 0x556E400ull +#define NIC2_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC2_MAC_CH2_MAC_128_SECTION 0x4000 +#define mmNIC2_MAC_CH2_MAC_AN_BASE 0x556E800ull +#define NIC2_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC2_MAC_CH2_MAC_AN_SECTION 0x8000 +#define mmNIC2_MAC_CH3_MAC_PCS_BASE 0x556F000ull +#define NIC2_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC2_MAC_CH3_MAC_PCS_SECTION 0x4000 +#define mmNIC2_MAC_CH3_MAC_128_BASE 0x556F400ull +#define NIC2_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC2_MAC_CH3_MAC_128_SECTION 0x4000 +#define mmNIC2_MAC_CH3_MAC_AN_BASE 0x556F800ull +#define NIC2_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC2_MAC_CH3_MAC_AN_SECTION 0x10800 +#define mmNIC3_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5580000ull +#define NIC3_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5580080ull +#define NIC3_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5580100ull +#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5580180ull +#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_0_SPECIAL_BASE 0x5580E80ull +#define NIC3_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_0_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5581000ull +#define NIC3_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5581080ull +#define NIC3_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5581100ull +#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5581180ull +#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_1_SPECIAL_BASE 0x5581E80ull +#define NIC3_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_1_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5582000ull +#define NIC3_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5582080ull +#define NIC3_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5582100ull +#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5582180ull +#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_2_SPECIAL_BASE 0x5582E80ull +#define NIC3_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_2_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5583000ull +#define NIC3_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5583080ull +#define NIC3_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5583100ull +#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5583180ull +#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_3_SPECIAL_BASE 0x5583E80ull +#define NIC3_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_3_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5584000ull +#define NIC3_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5584080ull +#define NIC3_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5584100ull +#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5584180ull +#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_4_SPECIAL_BASE 0x5584E80ull +#define NIC3_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_4_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5585000ull +#define NIC3_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5585080ull +#define NIC3_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5585100ull +#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5585180ull +#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_5_SPECIAL_BASE 0x5585E80ull +#define NIC3_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_5_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5586000ull +#define NIC3_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5586080ull +#define NIC3_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5586100ull +#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5586180ull +#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_6_SPECIAL_BASE 0x5586E80ull +#define NIC3_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_6_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5587000ull +#define NIC3_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5587080ull +#define NIC3_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5587100ull +#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5587180ull +#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_7_SPECIAL_BASE 0x5587E80ull +#define NIC3_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_7_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5588000ull +#define NIC3_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5588080ull +#define NIC3_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5588100ull +#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5588180ull +#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_8_SPECIAL_BASE 0x5588E80ull +#define NIC3_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_8_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5589000ull +#define NIC3_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5589080ull +#define NIC3_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5589100ull +#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5589180ull +#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_9_SPECIAL_BASE 0x5589E80ull +#define NIC3_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_9_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_10_UNSECURE_DOORBELL0_BASE 0x558A000ull +#define NIC3_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_10_UNSECURE_DOORBELL1_BASE 0x558A080ull +#define NIC3_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x558A100ull +#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x558A180ull +#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_10_SPECIAL_BASE 0x558AE80ull +#define NIC3_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_10_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_11_UNSECURE_DOORBELL0_BASE 0x558B000ull +#define NIC3_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_11_UNSECURE_DOORBELL1_BASE 0x558B080ull +#define NIC3_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x558B100ull +#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x558B180ull +#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_11_SPECIAL_BASE 0x558BE80ull +#define NIC3_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_11_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_12_UNSECURE_DOORBELL0_BASE 0x558C000ull +#define NIC3_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_12_UNSECURE_DOORBELL1_BASE 0x558C080ull +#define NIC3_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x558C100ull +#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x558C180ull +#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_12_SPECIAL_BASE 0x558CE80ull +#define NIC3_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_12_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_13_UNSECURE_DOORBELL0_BASE 0x558D000ull +#define NIC3_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_13_UNSECURE_DOORBELL1_BASE 0x558D080ull +#define NIC3_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x558D100ull +#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x558D180ull +#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_13_SPECIAL_BASE 0x558DE80ull +#define NIC3_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_13_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR0_14_UNSECURE_DOORBELL0_BASE 0x558E000ull +#define NIC3_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR0_14_UNSECURE_DOORBELL1_BASE 0x558E080ull +#define NIC3_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x558E100ull +#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x558E180ull +#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR0_14_SPECIAL_BASE 0x558EE80ull +#define NIC3_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_14_SPECIAL_SECTION 0x1180 +#define mmNIC3_QM_DCCM0_BASE 0x5590000ull +#define NIC3_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC3_QM_DCCM0_SECTION 0x8000 +#define mmNIC3_QM_ARC_AUX0_BASE 0x5598000ull +#define NIC3_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC3_QM_ARC_AUX0_SECTION 0xE800 +#define mmNIC3_QM_ARC_AUX0_SPECIAL_BASE 0x5598E80ull +#define NIC3_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 +#define mmNIC3_QM0_BASE 0x559A000ull +#define NIC3_QM0_MAX_OFFSET 0x1000 +#define NIC3_QM0_SECTION 0x9000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x559A900ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x559A908ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x559A910ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x559A918ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x559A920ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x559A928ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x559A930ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x559A938ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x559A940ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x559A948ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x559A950ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x559A958ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x559A960ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x559A968ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x559A970ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x559A978ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC3_QM0_AXUSER_SECURED_BASE 0x559AB00ull +#define NIC3_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC3_QM0_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC3_QM0_AXUSER_NONSECURED_BASE 0x559AB80ull +#define NIC3_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC3_QM0_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC3_QM0_DBG_HBW_BASE 0x559AC00ull +#define NIC3_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC3_QM0_DBG_HBW_SECTION 0x8000 +#define mmNIC3_QM0_DBG_LBW_BASE 0x559AC80ull +#define NIC3_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC3_QM0_DBG_LBW_SECTION 0x1000 +#define mmNIC3_QM0_CGM_BASE 0x559AD80ull +#define NIC3_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC3_QM0_CGM_SECTION 0x1000 +#define mmNIC3_QM0_SPECIAL_BASE 0x559AE80ull +#define NIC3_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_QM0_SPECIAL_SECTION 0x4180 +#define mmNIC3_QPC0_BASE 0x559F000ull +#define NIC3_QPC0_MAX_OFFSET 0x1000 +#define NIC3_QPC0_SECTION 0x7200 +#define mmNIC3_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x559F720ull +#define NIC3_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x559F728ull +#define NIC3_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x559F730ull +#define NIC3_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x559F738ull +#define NIC3_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x559F740ull +#define NIC3_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x559F748ull +#define NIC3_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x559F750ull +#define NIC3_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x559F758ull +#define NIC3_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x559F760ull +#define NIC3_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x559F768ull +#define NIC3_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x559F770ull +#define NIC3_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x559F778ull +#define NIC3_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x559F780ull +#define NIC3_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x559F788ull +#define NIC3_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x559F790ull +#define NIC3_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x559F798ull +#define NIC3_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x559F7A0ull +#define NIC3_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x559F7A8ull +#define NIC3_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x559F7B0ull +#define NIC3_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x559F7B8ull +#define NIC3_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x559F7C0ull +#define NIC3_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x559F7C8ull +#define NIC3_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x559F7D0ull +#define NIC3_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x559F7D8ull +#define NIC3_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x559F7E0ull +#define NIC3_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x559F7E8ull +#define NIC3_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x559F7F0ull +#define NIC3_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x559F7F8ull +#define NIC3_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x559F800ull +#define NIC3_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x559F808ull +#define NIC3_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x559F810ull +#define NIC3_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x559F818ull +#define NIC3_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC3_QPC0_AXUSER_CONG_QUE_BASE 0x559FB80ull +#define NIC3_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC3_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC3_QPC0_AXUSER_RXWQE_BASE 0x559FBE0ull +#define NIC3_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC3_QPC0_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC3_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x559FC40ull +#define NIC3_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC3_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC3_QPC0_AXUSER_DB_FIFO_BASE 0x559FCA0ull +#define NIC3_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC3_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC3_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x559FD00ull +#define NIC3_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC3_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC3_QPC0_AXUSER_ERR_FIFO_BASE 0x559FD60ull +#define NIC3_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC3_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC3_QPC0_AXUSER_QPC_RESP_BASE 0x559FDC0ull +#define NIC3_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC3_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC3_QPC0_AXUSER_QPC_REQ_BASE 0x559FE20ull +#define NIC3_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC3_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC3_QPC0_SPECIAL_BASE 0x559FE80ull +#define NIC3_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_QPC0_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_0_UNSECURE_DOORBELL0_BASE 0x55A0000ull +#define NIC3_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_0_UNSECURE_DOORBELL1_BASE 0x55A0080ull +#define NIC3_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x55A0100ull +#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x55A0180ull +#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_0_SPECIAL_BASE 0x55A0E80ull +#define NIC3_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_0_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_1_UNSECURE_DOORBELL0_BASE 0x55A1000ull +#define NIC3_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_1_UNSECURE_DOORBELL1_BASE 0x55A1080ull +#define NIC3_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x55A1100ull +#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x55A1180ull +#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_1_SPECIAL_BASE 0x55A1E80ull +#define NIC3_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_1_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_2_UNSECURE_DOORBELL0_BASE 0x55A2000ull +#define NIC3_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_2_UNSECURE_DOORBELL1_BASE 0x55A2080ull +#define NIC3_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x55A2100ull +#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x55A2180ull +#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_2_SPECIAL_BASE 0x55A2E80ull +#define NIC3_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_2_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_3_UNSECURE_DOORBELL0_BASE 0x55A3000ull +#define NIC3_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_3_UNSECURE_DOORBELL1_BASE 0x55A3080ull +#define NIC3_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x55A3100ull +#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x55A3180ull +#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_3_SPECIAL_BASE 0x55A3E80ull +#define NIC3_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_3_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_4_UNSECURE_DOORBELL0_BASE 0x55A4000ull +#define NIC3_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_4_UNSECURE_DOORBELL1_BASE 0x55A4080ull +#define NIC3_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x55A4100ull +#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x55A4180ull +#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_4_SPECIAL_BASE 0x55A4E80ull +#define NIC3_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_4_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_5_UNSECURE_DOORBELL0_BASE 0x55A5000ull +#define NIC3_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_5_UNSECURE_DOORBELL1_BASE 0x55A5080ull +#define NIC3_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x55A5100ull +#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x55A5180ull +#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_5_SPECIAL_BASE 0x55A5E80ull +#define NIC3_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_5_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_6_UNSECURE_DOORBELL0_BASE 0x55A6000ull +#define NIC3_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_6_UNSECURE_DOORBELL1_BASE 0x55A6080ull +#define NIC3_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x55A6100ull +#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x55A6180ull +#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_6_SPECIAL_BASE 0x55A6E80ull +#define NIC3_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_6_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_7_UNSECURE_DOORBELL0_BASE 0x55A7000ull +#define NIC3_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_7_UNSECURE_DOORBELL1_BASE 0x55A7080ull +#define NIC3_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x55A7100ull +#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x55A7180ull +#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_7_SPECIAL_BASE 0x55A7E80ull +#define NIC3_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_7_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_8_UNSECURE_DOORBELL0_BASE 0x55A8000ull +#define NIC3_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_8_UNSECURE_DOORBELL1_BASE 0x55A8080ull +#define NIC3_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x55A8100ull +#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x55A8180ull +#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_8_SPECIAL_BASE 0x55A8E80ull +#define NIC3_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_8_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_9_UNSECURE_DOORBELL0_BASE 0x55A9000ull +#define NIC3_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_9_UNSECURE_DOORBELL1_BASE 0x55A9080ull +#define NIC3_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x55A9100ull +#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x55A9180ull +#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_9_SPECIAL_BASE 0x55A9E80ull +#define NIC3_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_9_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_10_UNSECURE_DOORBELL0_BASE 0x55AA000ull +#define NIC3_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_10_UNSECURE_DOORBELL1_BASE 0x55AA080ull +#define NIC3_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x55AA100ull +#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x55AA180ull +#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_10_SPECIAL_BASE 0x55AAE80ull +#define NIC3_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_10_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_11_UNSECURE_DOORBELL0_BASE 0x55AB000ull +#define NIC3_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_11_UNSECURE_DOORBELL1_BASE 0x55AB080ull +#define NIC3_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x55AB100ull +#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x55AB180ull +#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_11_SPECIAL_BASE 0x55ABE80ull +#define NIC3_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_11_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_12_UNSECURE_DOORBELL0_BASE 0x55AC000ull +#define NIC3_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_12_UNSECURE_DOORBELL1_BASE 0x55AC080ull +#define NIC3_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x55AC100ull +#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x55AC180ull +#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_12_SPECIAL_BASE 0x55ACE80ull +#define NIC3_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_12_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_13_UNSECURE_DOORBELL0_BASE 0x55AD000ull +#define NIC3_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_13_UNSECURE_DOORBELL1_BASE 0x55AD080ull +#define NIC3_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x55AD100ull +#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x55AD180ull +#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_13_SPECIAL_BASE 0x55ADE80ull +#define NIC3_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_13_SPECIAL_SECTION 0x1800 +#define mmNIC3_UMR1_14_UNSECURE_DOORBELL0_BASE 0x55AE000ull +#define NIC3_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC3_UMR1_14_UNSECURE_DOORBELL1_BASE 0x55AE080ull +#define NIC3_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC3_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x55AE100ull +#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC3_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x55AE180ull +#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC3_UMR1_14_SPECIAL_BASE 0x55AEE80ull +#define NIC3_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_14_SPECIAL_SECTION 0x1180 +#define mmNIC3_QM_DCCM1_BASE 0x55B0000ull +#define NIC3_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC3_QM_DCCM1_SECTION 0x8000 +#define mmNIC3_QM_ARC_AUX1_BASE 0x55B8000ull +#define NIC3_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC3_QM_ARC_AUX1_SECTION 0xE800 +#define mmNIC3_QM_ARC_AUX1_SPECIAL_BASE 0x55B8E80ull +#define NIC3_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 +#define mmNIC3_QM1_BASE 0x55BA000ull +#define NIC3_QM1_MAX_OFFSET 0x1000 +#define NIC3_QM1_SECTION 0x9000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x55BA900ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x55BA908ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x55BA910ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x55BA918ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x55BA920ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x55BA928ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x55BA930ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x55BA938ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x55BA940ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x55BA948ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x55BA950ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x55BA958ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x55BA960ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x55BA968ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x55BA970ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x55BA978ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC3_QM1_AXUSER_SECURED_BASE 0x55BAB00ull +#define NIC3_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC3_QM1_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC3_QM1_AXUSER_NONSECURED_BASE 0x55BAB80ull +#define NIC3_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC3_QM1_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC3_QM1_DBG_HBW_BASE 0x55BAC00ull +#define NIC3_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC3_QM1_DBG_HBW_SECTION 0x8000 +#define mmNIC3_QM1_DBG_LBW_BASE 0x55BAC80ull +#define NIC3_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC3_QM1_DBG_LBW_SECTION 0x1000 +#define mmNIC3_QM1_CGM_BASE 0x55BAD80ull +#define NIC3_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC3_QM1_CGM_SECTION 0x1000 +#define mmNIC3_QM1_SPECIAL_BASE 0x55BAE80ull +#define NIC3_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_QM1_SPECIAL_SECTION 0x4180 +#define mmNIC3_QPC1_BASE 0x55BF000ull +#define NIC3_QPC1_MAX_OFFSET 0x1000 +#define NIC3_QPC1_SECTION 0x7200 +#define mmNIC3_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x55BF720ull +#define NIC3_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x55BF728ull +#define NIC3_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x55BF730ull +#define NIC3_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x55BF738ull +#define NIC3_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x55BF740ull +#define NIC3_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x55BF748ull +#define NIC3_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x55BF750ull +#define NIC3_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x55BF758ull +#define NIC3_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x55BF760ull +#define NIC3_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x55BF768ull +#define NIC3_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x55BF770ull +#define NIC3_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x55BF778ull +#define NIC3_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x55BF780ull +#define NIC3_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x55BF788ull +#define NIC3_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x55BF790ull +#define NIC3_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x55BF798ull +#define NIC3_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x55BF7A0ull +#define NIC3_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x55BF7A8ull +#define NIC3_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x55BF7B0ull +#define NIC3_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x55BF7B8ull +#define NIC3_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x55BF7C0ull +#define NIC3_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x55BF7C8ull +#define NIC3_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x55BF7D0ull +#define NIC3_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x55BF7D8ull +#define NIC3_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x55BF7E0ull +#define NIC3_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x55BF7E8ull +#define NIC3_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x55BF7F0ull +#define NIC3_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x55BF7F8ull +#define NIC3_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x55BF800ull +#define NIC3_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x55BF808ull +#define NIC3_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x55BF810ull +#define NIC3_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC3_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x55BF818ull +#define NIC3_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC3_QPC1_AXUSER_CONG_QUE_BASE 0x55BFB80ull +#define NIC3_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC3_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC3_QPC1_AXUSER_RXWQE_BASE 0x55BFBE0ull +#define NIC3_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC3_QPC1_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC3_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x55BFC40ull +#define NIC3_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC3_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC3_QPC1_AXUSER_DB_FIFO_BASE 0x55BFCA0ull +#define NIC3_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC3_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC3_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x55BFD00ull +#define NIC3_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC3_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC3_QPC1_AXUSER_ERR_FIFO_BASE 0x55BFD60ull +#define NIC3_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC3_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC3_QPC1_AXUSER_QPC_RESP_BASE 0x55BFDC0ull +#define NIC3_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC3_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC3_QPC1_AXUSER_QPC_REQ_BASE 0x55BFE20ull +#define NIC3_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC3_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC3_QPC1_SPECIAL_BASE 0x55BFE80ull +#define NIC3_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_QPC1_SPECIAL_SECTION 0x8180 +#define mmNIC3_TMR_BASE 0x55C8000ull +#define NIC3_TMR_MAX_OFFSET 0x1000 +#define NIC3_TMR_SECTION 0xD600 +#define mmNIC3_TMR_AXUSER_TMR_FREE_LIST_BASE 0x55C8D60ull +#define NIC3_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC3_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 +#define mmNIC3_TMR_AXUSER_TMR_FIFO_BASE 0x55C8DC0ull +#define NIC3_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC3_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 +#define mmNIC3_TMR_AXUSER_TMR_FSM_BASE 0x55C8E20ull +#define NIC3_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC3_TMR_AXUSER_TMR_FSM_SECTION 0x6000 +#define mmNIC3_TMR_SPECIAL_BASE 0x55C8E80ull +#define NIC3_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_TMR_SPECIAL_SECTION 0x1800 +#define mmNIC3_RXB_CORE_BASE 0x55C9000ull +#define NIC3_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC3_RXB_CORE_SECTION 0x6100 +#define mmNIC3_RXB_CORE_SCT_AWUSER_BASE 0x55C9610ull +#define NIC3_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC3_RXB_CORE_SCT_AWUSER_SECTION 0x8700 +#define mmNIC3_RXB_CORE_SPECIAL_BASE 0x55C9E80ull +#define NIC3_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_RXB_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC3_RXE0_BASE 0x55CA000ull +#define NIC3_RXE0_MAX_OFFSET 0x1000 +#define NIC3_RXE0_SECTION 0x9000 +#define mmNIC3_RXE0_WQE_ARUSER_BASE 0x55CA900ull +#define NIC3_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC3_RXE0_WQE_ARUSER_SECTION 0x5800 +#define mmNIC3_RXE0_SPECIAL_BASE 0x55CAE80ull +#define NIC3_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_RXE0_SPECIAL_SECTION 0x1800 +#define mmNIC3_RXE1_BASE 0x55CB000ull +#define NIC3_RXE1_MAX_OFFSET 0x1000 +#define NIC3_RXE1_SECTION 0x9000 +#define mmNIC3_RXE1_WQE_ARUSER_BASE 0x55CB900ull +#define NIC3_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC3_RXE1_WQE_ARUSER_SECTION 0x5800 +#define mmNIC3_RXE1_SPECIAL_BASE 0x55CBE80ull +#define NIC3_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_RXE1_SPECIAL_SECTION 0x1800 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ0_BASE 0x55CC000ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ1_BASE 0x55CC050ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ2_BASE 0x55CC0A0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ3_BASE 0x55CC0F0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ4_BASE 0x55CC140ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ5_BASE 0x55CC190ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ6_BASE 0x55CC1E0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ7_BASE 0x55CC230ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ8_BASE 0x55CC280ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ9_BASE 0x55CC2D0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ10_BASE 0x55CC320ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ11_BASE 0x55CC370ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ12_BASE 0x55CC3C0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ13_BASE 0x55CC410ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ14_BASE 0x55CC460ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ15_BASE 0x55CC4B0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ16_BASE 0x55CC500ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ17_BASE 0x55CC550ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ18_BASE 0x55CC5A0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ19_BASE 0x55CC5F0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ20_BASE 0x55CC640ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ21_BASE 0x55CC690ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ22_BASE 0x55CC6E0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ23_BASE 0x55CC730ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ24_BASE 0x55CC780ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ25_BASE 0x55CC7D0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ26_BASE 0x55CC820ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ27_BASE 0x55CC870ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ28_BASE 0x55CC8C0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ29_BASE 0x55CC910ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ30_BASE 0x55CC960ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ31_BASE 0x55CC9B0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC3_RXE0_AXUSER_SPECIAL_BASE 0x55CCE80ull +#define NIC3_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_RXE0_AXUSER_SPECIAL_SECTION 0x1800 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ0_BASE 0x55CD000ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ1_BASE 0x55CD050ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ2_BASE 0x55CD0A0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ3_BASE 0x55CD0F0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ4_BASE 0x55CD140ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ5_BASE 0x55CD190ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ6_BASE 0x55CD1E0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ7_BASE 0x55CD230ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ8_BASE 0x55CD280ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ9_BASE 0x55CD2D0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ10_BASE 0x55CD320ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ11_BASE 0x55CD370ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ12_BASE 0x55CD3C0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ13_BASE 0x55CD410ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ14_BASE 0x55CD460ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ15_BASE 0x55CD4B0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ16_BASE 0x55CD500ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ17_BASE 0x55CD550ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ18_BASE 0x55CD5A0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ19_BASE 0x55CD5F0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ20_BASE 0x55CD640ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ21_BASE 0x55CD690ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ22_BASE 0x55CD6E0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ23_BASE 0x55CD730ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ24_BASE 0x55CD780ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ25_BASE 0x55CD7D0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ26_BASE 0x55CD820ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ27_BASE 0x55CD870ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ28_BASE 0x55CD8C0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ29_BASE 0x55CD910ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ30_BASE 0x55CD960ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ31_BASE 0x55CD9B0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC3_RXE1_AXUSER_SPECIAL_BASE 0x55CDE80ull +#define NIC3_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_RXE1_AXUSER_SPECIAL_SECTION 0x2180 +#define mmNIC3_TXS0_BASE 0x55D0000ull +#define NIC3_TXS0_MAX_OFFSET 0x1000 +#define NIC3_TXS0_SECTION 0xE800 +#define mmNIC3_TXS0_SPECIAL_BASE 0x55D0E80ull +#define NIC3_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_TXS0_SPECIAL_SECTION 0x1800 +#define mmNIC3_TXS1_BASE 0x55D1000ull +#define NIC3_TXS1_MAX_OFFSET 0x1000 +#define NIC3_TXS1_SECTION 0xE800 +#define mmNIC3_TXS1_SPECIAL_BASE 0x55D1E80ull +#define NIC3_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_TXS1_SPECIAL_SECTION 0x1800 +#define mmNIC3_TXE0_BASE 0x55D2000ull +#define NIC3_TXE0_MAX_OFFSET 0x1000 +#define NIC3_TXE0_SECTION 0xE800 +#define mmNIC3_TXE0_SPECIAL_BASE 0x55D2E80ull +#define NIC3_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_TXE0_SPECIAL_SECTION 0x1800 +#define mmNIC3_TXE1_BASE 0x55D3000ull +#define NIC3_TXE1_MAX_OFFSET 0x1000 +#define NIC3_TXE1_SECTION 0xE800 +#define mmNIC3_TXE1_SPECIAL_BASE 0x55D3E80ull +#define NIC3_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_TXE1_SPECIAL_SECTION 0x1800 +#define mmNIC3_TXB_BASE 0x55D4000ull +#define NIC3_TXB_MAX_OFFSET 0x1000 +#define NIC3_TXB_SECTION 0xE800 +#define mmNIC3_TXB_SPECIAL_BASE 0x55D4E80ull +#define NIC3_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_TXB_SPECIAL_SECTION 0x1800 +#define mmNIC3_MSTR_IF_RR_SHRD_HBW_BASE 0x55D5000ull +#define NIC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmNIC3_MSTR_IF_RR_PRVT_HBW_BASE 0x55D5200ull +#define NIC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmNIC3_MSTR_IF_RR_SHRD_LBW_BASE 0x55D5400ull +#define NIC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmNIC3_MSTR_IF_RR_PRVT_LBW_BASE 0x55D5600ull +#define NIC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmNIC3_MSTR_IF_E2E_CRDT_BASE 0x55D5800ull +#define NIC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC3_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmNIC3_MSTR_IF_AXUSER_BASE 0x55D5A80ull +#define NIC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC3_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmNIC3_MSTR_IF_DBG_HBW_BASE 0x55D5B00ull +#define NIC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC3_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmNIC3_MSTR_IF_DBG_LBW_BASE 0x55D5B80ull +#define NIC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC3_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmNIC3_MSTR_IF_CORE_HBW_BASE 0x55D5C00ull +#define NIC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC3_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmNIC3_MSTR_IF_CORE_LBW_BASE 0x55D5D80ull +#define NIC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC3_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmNIC3_MSTR_IF_SPECIAL_BASE 0x55D5E80ull +#define NIC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmNIC3_TX_AXUSER_BASE 0x55D6000ull +#define NIC3_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC3_TX_AXUSER_SECTION 0x2000 +#define mmNIC3_SERDES0_BASE 0x55D8000ull +#define NIC3_SERDES0_MAX_OFFSET 0x3E40 +#define NIC3_SERDES0_SECTION 0x4000 +#define mmNIC3_SERDES1_BASE 0x55DC000ull +#define NIC3_SERDES1_MAX_OFFSET 0x3E40 +#define NIC3_SERDES1_SECTION 0x4000 +#define mmNIC3_PHY_BASE 0x55E0000ull +#define NIC3_PHY_MAX_OFFSET 0x1000 +#define NIC3_PHY_SECTION 0xE800 +#define mmNIC3_PHY_SPECIAL_BASE 0x55E0E80ull +#define NIC3_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_PHY_SPECIAL_SECTION 0x7180 +#define mmPRT3_MAC_AUX_BASE 0x55E8000ull +#define PRT3_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT3_MAC_AUX_SECTION 0xE800 +#define mmPRT3_MAC_AUX_SPECIAL_BASE 0x55E8E80ull +#define PRT3_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT3_MAC_AUX_SPECIAL_SECTION 0x1800 +#define mmPRT3_MAC_CORE_BASE 0x55E9000ull +#define PRT3_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT3_MAC_CORE_SECTION 0xE800 +#define mmPRT3_MAC_CORE_SPECIAL_BASE 0x55E9E80ull +#define PRT3_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT3_MAC_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC3_MAC_RS_FEC_BASE 0x55EA000ull +#define NIC3_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC3_MAC_RS_FEC_SECTION 0x1000 +#define mmNIC3_MAC_GLOB_STAT_CONTROL_REG_BASE 0x55EB000ull +#define NIC3_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000 +#define NIC3_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000 +#define mmNIC3_MAC_GLOB_STAT_RX0_BASE 0x55EB100ull +#define NIC3_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00 +#define NIC3_MAC_GLOB_STAT_RX0_SECTION 0x8C00 +#define mmNIC3_MAC_GLOB_STAT_RX1_BASE 0x55EB18Cull +#define NIC3_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00 +#define NIC3_MAC_GLOB_STAT_RX1_SECTION 0x8C00 +#define mmNIC3_MAC_GLOB_STAT_RX2_BASE 0x55EB218ull +#define NIC3_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00 +#define NIC3_MAC_GLOB_STAT_RX2_SECTION 0x8C00 +#define mmNIC3_MAC_GLOB_STAT_RX3_BASE 0x55EB2A4ull +#define NIC3_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00 +#define NIC3_MAC_GLOB_STAT_RX3_SECTION 0x8C00 +#define mmNIC3_MAC_GLOB_STAT_TX0_BASE 0x55EB330ull +#define NIC3_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800 +#define NIC3_MAC_GLOB_STAT_TX0_SECTION 0x6800 +#define mmNIC3_MAC_GLOB_STAT_TX1_BASE 0x55EB398ull +#define NIC3_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800 +#define NIC3_MAC_GLOB_STAT_TX1_SECTION 0x6800 +#define mmNIC3_MAC_GLOB_STAT_TX2_BASE 0x55EB400ull +#define NIC3_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800 +#define NIC3_MAC_GLOB_STAT_TX2_SECTION 0x6800 +#define mmNIC3_MAC_GLOB_STAT_TX3_BASE 0x55EB468ull +#define NIC3_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800 +#define NIC3_MAC_GLOB_STAT_TX3_SECTION 0x3980 +#define mmNIC3_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x55EB800ull +#define NIC3_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC3_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000 +#define mmNIC3_MAC_CH0_MAC_PCS_BASE 0x55EC000ull +#define NIC3_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC3_MAC_CH0_MAC_PCS_SECTION 0x4000 +#define mmNIC3_MAC_CH0_MAC_128_BASE 0x55EC400ull +#define NIC3_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC3_MAC_CH0_MAC_128_SECTION 0x4000 +#define mmNIC3_MAC_CH0_MAC_AN_BASE 0x55EC800ull +#define NIC3_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC3_MAC_CH0_MAC_AN_SECTION 0x8000 +#define mmNIC3_MAC_CH1_MAC_PCS_BASE 0x55ED000ull +#define NIC3_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC3_MAC_CH1_MAC_PCS_SECTION 0x4000 +#define mmNIC3_MAC_CH1_MAC_128_BASE 0x55ED400ull +#define NIC3_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC3_MAC_CH1_MAC_128_SECTION 0x4000 +#define mmNIC3_MAC_CH1_MAC_AN_BASE 0x55ED800ull +#define NIC3_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC3_MAC_CH1_MAC_AN_SECTION 0x8000 +#define mmNIC3_MAC_CH2_MAC_PCS_BASE 0x55EE000ull +#define NIC3_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC3_MAC_CH2_MAC_PCS_SECTION 0x4000 +#define mmNIC3_MAC_CH2_MAC_128_BASE 0x55EE400ull +#define NIC3_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC3_MAC_CH2_MAC_128_SECTION 0x4000 +#define mmNIC3_MAC_CH2_MAC_AN_BASE 0x55EE800ull +#define NIC3_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC3_MAC_CH2_MAC_AN_SECTION 0x8000 +#define mmNIC3_MAC_CH3_MAC_PCS_BASE 0x55EF000ull +#define NIC3_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC3_MAC_CH3_MAC_PCS_SECTION 0x4000 +#define mmNIC3_MAC_CH3_MAC_128_BASE 0x55EF400ull +#define NIC3_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC3_MAC_CH3_MAC_128_SECTION 0x4000 +#define mmNIC3_MAC_CH3_MAC_AN_BASE 0x55EF800ull +#define NIC3_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC3_MAC_CH3_MAC_AN_SECTION 0x10800 +#define mmNIC4_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5600000ull +#define NIC4_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5600080ull +#define NIC4_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5600100ull +#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5600180ull +#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_0_SPECIAL_BASE 0x5600E80ull +#define NIC4_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_0_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5601000ull +#define NIC4_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5601080ull +#define NIC4_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5601100ull +#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5601180ull +#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_1_SPECIAL_BASE 0x5601E80ull +#define NIC4_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_1_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5602000ull +#define NIC4_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5602080ull +#define NIC4_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5602100ull +#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5602180ull +#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_2_SPECIAL_BASE 0x5602E80ull +#define NIC4_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_2_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5603000ull +#define NIC4_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5603080ull +#define NIC4_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5603100ull +#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5603180ull +#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_3_SPECIAL_BASE 0x5603E80ull +#define NIC4_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_3_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5604000ull +#define NIC4_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5604080ull +#define NIC4_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5604100ull +#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5604180ull +#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_4_SPECIAL_BASE 0x5604E80ull +#define NIC4_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_4_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5605000ull +#define NIC4_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5605080ull +#define NIC4_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5605100ull +#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5605180ull +#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_5_SPECIAL_BASE 0x5605E80ull +#define NIC4_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_5_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5606000ull +#define NIC4_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5606080ull +#define NIC4_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5606100ull +#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5606180ull +#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_6_SPECIAL_BASE 0x5606E80ull +#define NIC4_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_6_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5607000ull +#define NIC4_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5607080ull +#define NIC4_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5607100ull +#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5607180ull +#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_7_SPECIAL_BASE 0x5607E80ull +#define NIC4_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_7_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5608000ull +#define NIC4_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5608080ull +#define NIC4_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5608100ull +#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5608180ull +#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_8_SPECIAL_BASE 0x5608E80ull +#define NIC4_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_8_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5609000ull +#define NIC4_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5609080ull +#define NIC4_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5609100ull +#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5609180ull +#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_9_SPECIAL_BASE 0x5609E80ull +#define NIC4_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_9_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_10_UNSECURE_DOORBELL0_BASE 0x560A000ull +#define NIC4_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_10_UNSECURE_DOORBELL1_BASE 0x560A080ull +#define NIC4_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x560A100ull +#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x560A180ull +#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_10_SPECIAL_BASE 0x560AE80ull +#define NIC4_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_10_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_11_UNSECURE_DOORBELL0_BASE 0x560B000ull +#define NIC4_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_11_UNSECURE_DOORBELL1_BASE 0x560B080ull +#define NIC4_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x560B100ull +#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x560B180ull +#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_11_SPECIAL_BASE 0x560BE80ull +#define NIC4_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_11_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_12_UNSECURE_DOORBELL0_BASE 0x560C000ull +#define NIC4_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_12_UNSECURE_DOORBELL1_BASE 0x560C080ull +#define NIC4_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x560C100ull +#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x560C180ull +#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_12_SPECIAL_BASE 0x560CE80ull +#define NIC4_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_12_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_13_UNSECURE_DOORBELL0_BASE 0x560D000ull +#define NIC4_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_13_UNSECURE_DOORBELL1_BASE 0x560D080ull +#define NIC4_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x560D100ull +#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x560D180ull +#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_13_SPECIAL_BASE 0x560DE80ull +#define NIC4_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_13_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR0_14_UNSECURE_DOORBELL0_BASE 0x560E000ull +#define NIC4_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR0_14_UNSECURE_DOORBELL1_BASE 0x560E080ull +#define NIC4_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x560E100ull +#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x560E180ull +#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR0_14_SPECIAL_BASE 0x560EE80ull +#define NIC4_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_14_SPECIAL_SECTION 0x1180 +#define mmNIC4_QM_DCCM0_BASE 0x5610000ull +#define NIC4_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC4_QM_DCCM0_SECTION 0x8000 +#define mmNIC4_QM_ARC_AUX0_BASE 0x5618000ull +#define NIC4_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC4_QM_ARC_AUX0_SECTION 0xE800 +#define mmNIC4_QM_ARC_AUX0_SPECIAL_BASE 0x5618E80ull +#define NIC4_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 +#define mmNIC4_QM0_BASE 0x561A000ull +#define NIC4_QM0_MAX_OFFSET 0x1000 +#define NIC4_QM0_SECTION 0x9000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x561A900ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x561A908ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x561A910ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x561A918ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x561A920ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x561A928ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x561A930ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x561A938ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x561A940ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x561A948ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x561A950ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x561A958ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x561A960ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x561A968ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x561A970ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x561A978ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC4_QM0_AXUSER_SECURED_BASE 0x561AB00ull +#define NIC4_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC4_QM0_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC4_QM0_AXUSER_NONSECURED_BASE 0x561AB80ull +#define NIC4_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC4_QM0_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC4_QM0_DBG_HBW_BASE 0x561AC00ull +#define NIC4_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC4_QM0_DBG_HBW_SECTION 0x8000 +#define mmNIC4_QM0_DBG_LBW_BASE 0x561AC80ull +#define NIC4_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC4_QM0_DBG_LBW_SECTION 0x1000 +#define mmNIC4_QM0_CGM_BASE 0x561AD80ull +#define NIC4_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC4_QM0_CGM_SECTION 0x1000 +#define mmNIC4_QM0_SPECIAL_BASE 0x561AE80ull +#define NIC4_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_QM0_SPECIAL_SECTION 0x4180 +#define mmNIC4_QPC0_BASE 0x561F000ull +#define NIC4_QPC0_MAX_OFFSET 0x1000 +#define NIC4_QPC0_SECTION 0x7200 +#define mmNIC4_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x561F720ull +#define NIC4_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x561F728ull +#define NIC4_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x561F730ull +#define NIC4_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x561F738ull +#define NIC4_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x561F740ull +#define NIC4_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x561F748ull +#define NIC4_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x561F750ull +#define NIC4_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x561F758ull +#define NIC4_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x561F760ull +#define NIC4_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x561F768ull +#define NIC4_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x561F770ull +#define NIC4_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x561F778ull +#define NIC4_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x561F780ull +#define NIC4_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x561F788ull +#define NIC4_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x561F790ull +#define NIC4_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x561F798ull +#define NIC4_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x561F7A0ull +#define NIC4_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x561F7A8ull +#define NIC4_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x561F7B0ull +#define NIC4_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x561F7B8ull +#define NIC4_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x561F7C0ull +#define NIC4_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x561F7C8ull +#define NIC4_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x561F7D0ull +#define NIC4_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x561F7D8ull +#define NIC4_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x561F7E0ull +#define NIC4_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x561F7E8ull +#define NIC4_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x561F7F0ull +#define NIC4_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x561F7F8ull +#define NIC4_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x561F800ull +#define NIC4_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x561F808ull +#define NIC4_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x561F810ull +#define NIC4_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x561F818ull +#define NIC4_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC4_QPC0_AXUSER_CONG_QUE_BASE 0x561FB80ull +#define NIC4_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC4_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC4_QPC0_AXUSER_RXWQE_BASE 0x561FBE0ull +#define NIC4_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC4_QPC0_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC4_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x561FC40ull +#define NIC4_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC4_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC4_QPC0_AXUSER_DB_FIFO_BASE 0x561FCA0ull +#define NIC4_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC4_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC4_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x561FD00ull +#define NIC4_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC4_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC4_QPC0_AXUSER_ERR_FIFO_BASE 0x561FD60ull +#define NIC4_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC4_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC4_QPC0_AXUSER_QPC_RESP_BASE 0x561FDC0ull +#define NIC4_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC4_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC4_QPC0_AXUSER_QPC_REQ_BASE 0x561FE20ull +#define NIC4_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC4_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC4_QPC0_SPECIAL_BASE 0x561FE80ull +#define NIC4_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_QPC0_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5620000ull +#define NIC4_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5620080ull +#define NIC4_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5620100ull +#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5620180ull +#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_0_SPECIAL_BASE 0x5620E80ull +#define NIC4_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_0_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5621000ull +#define NIC4_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5621080ull +#define NIC4_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5621100ull +#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5621180ull +#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_1_SPECIAL_BASE 0x5621E80ull +#define NIC4_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_1_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5622000ull +#define NIC4_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5622080ull +#define NIC4_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5622100ull +#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5622180ull +#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_2_SPECIAL_BASE 0x5622E80ull +#define NIC4_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_2_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5623000ull +#define NIC4_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5623080ull +#define NIC4_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5623100ull +#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5623180ull +#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_3_SPECIAL_BASE 0x5623E80ull +#define NIC4_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_3_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5624000ull +#define NIC4_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5624080ull +#define NIC4_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5624100ull +#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5624180ull +#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_4_SPECIAL_BASE 0x5624E80ull +#define NIC4_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_4_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5625000ull +#define NIC4_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5625080ull +#define NIC4_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5625100ull +#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5625180ull +#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_5_SPECIAL_BASE 0x5625E80ull +#define NIC4_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_5_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5626000ull +#define NIC4_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5626080ull +#define NIC4_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5626100ull +#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5626180ull +#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_6_SPECIAL_BASE 0x5626E80ull +#define NIC4_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_6_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5627000ull +#define NIC4_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5627080ull +#define NIC4_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5627100ull +#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5627180ull +#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_7_SPECIAL_BASE 0x5627E80ull +#define NIC4_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_7_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5628000ull +#define NIC4_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5628080ull +#define NIC4_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5628100ull +#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5628180ull +#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_8_SPECIAL_BASE 0x5628E80ull +#define NIC4_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_8_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5629000ull +#define NIC4_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5629080ull +#define NIC4_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5629100ull +#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5629180ull +#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_9_SPECIAL_BASE 0x5629E80ull +#define NIC4_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_9_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_10_UNSECURE_DOORBELL0_BASE 0x562A000ull +#define NIC4_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_10_UNSECURE_DOORBELL1_BASE 0x562A080ull +#define NIC4_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x562A100ull +#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x562A180ull +#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_10_SPECIAL_BASE 0x562AE80ull +#define NIC4_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_10_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_11_UNSECURE_DOORBELL0_BASE 0x562B000ull +#define NIC4_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_11_UNSECURE_DOORBELL1_BASE 0x562B080ull +#define NIC4_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x562B100ull +#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x562B180ull +#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_11_SPECIAL_BASE 0x562BE80ull +#define NIC4_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_11_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_12_UNSECURE_DOORBELL0_BASE 0x562C000ull +#define NIC4_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_12_UNSECURE_DOORBELL1_BASE 0x562C080ull +#define NIC4_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x562C100ull +#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x562C180ull +#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_12_SPECIAL_BASE 0x562CE80ull +#define NIC4_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_12_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_13_UNSECURE_DOORBELL0_BASE 0x562D000ull +#define NIC4_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_13_UNSECURE_DOORBELL1_BASE 0x562D080ull +#define NIC4_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x562D100ull +#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x562D180ull +#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_13_SPECIAL_BASE 0x562DE80ull +#define NIC4_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_13_SPECIAL_SECTION 0x1800 +#define mmNIC4_UMR1_14_UNSECURE_DOORBELL0_BASE 0x562E000ull +#define NIC4_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC4_UMR1_14_UNSECURE_DOORBELL1_BASE 0x562E080ull +#define NIC4_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC4_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x562E100ull +#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC4_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x562E180ull +#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC4_UMR1_14_SPECIAL_BASE 0x562EE80ull +#define NIC4_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_14_SPECIAL_SECTION 0x1180 +#define mmNIC4_QM_DCCM1_BASE 0x5630000ull +#define NIC4_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC4_QM_DCCM1_SECTION 0x8000 +#define mmNIC4_QM_ARC_AUX1_BASE 0x5638000ull +#define NIC4_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC4_QM_ARC_AUX1_SECTION 0xE800 +#define mmNIC4_QM_ARC_AUX1_SPECIAL_BASE 0x5638E80ull +#define NIC4_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 +#define mmNIC4_QM1_BASE 0x563A000ull +#define NIC4_QM1_MAX_OFFSET 0x1000 +#define NIC4_QM1_SECTION 0x9000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x563A900ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x563A908ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x563A910ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x563A918ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x563A920ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x563A928ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x563A930ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x563A938ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x563A940ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x563A948ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x563A950ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x563A958ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x563A960ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x563A968ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x563A970ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x563A978ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC4_QM1_AXUSER_SECURED_BASE 0x563AB00ull +#define NIC4_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC4_QM1_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC4_QM1_AXUSER_NONSECURED_BASE 0x563AB80ull +#define NIC4_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC4_QM1_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC4_QM1_DBG_HBW_BASE 0x563AC00ull +#define NIC4_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC4_QM1_DBG_HBW_SECTION 0x8000 +#define mmNIC4_QM1_DBG_LBW_BASE 0x563AC80ull +#define NIC4_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC4_QM1_DBG_LBW_SECTION 0x1000 +#define mmNIC4_QM1_CGM_BASE 0x563AD80ull +#define NIC4_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC4_QM1_CGM_SECTION 0x1000 +#define mmNIC4_QM1_SPECIAL_BASE 0x563AE80ull +#define NIC4_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_QM1_SPECIAL_SECTION 0x4180 +#define mmNIC4_QPC1_BASE 0x563F000ull +#define NIC4_QPC1_MAX_OFFSET 0x1000 +#define NIC4_QPC1_SECTION 0x7200 +#define mmNIC4_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x563F720ull +#define NIC4_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x563F728ull +#define NIC4_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x563F730ull +#define NIC4_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x563F738ull +#define NIC4_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x563F740ull +#define NIC4_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x563F748ull +#define NIC4_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x563F750ull +#define NIC4_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x563F758ull +#define NIC4_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x563F760ull +#define NIC4_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x563F768ull +#define NIC4_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x563F770ull +#define NIC4_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x563F778ull +#define NIC4_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x563F780ull +#define NIC4_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x563F788ull +#define NIC4_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x563F790ull +#define NIC4_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x563F798ull +#define NIC4_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x563F7A0ull +#define NIC4_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x563F7A8ull +#define NIC4_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x563F7B0ull +#define NIC4_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x563F7B8ull +#define NIC4_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x563F7C0ull +#define NIC4_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x563F7C8ull +#define NIC4_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x563F7D0ull +#define NIC4_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x563F7D8ull +#define NIC4_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x563F7E0ull +#define NIC4_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x563F7E8ull +#define NIC4_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x563F7F0ull +#define NIC4_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x563F7F8ull +#define NIC4_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x563F800ull +#define NIC4_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x563F808ull +#define NIC4_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x563F810ull +#define NIC4_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC4_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x563F818ull +#define NIC4_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC4_QPC1_AXUSER_CONG_QUE_BASE 0x563FB80ull +#define NIC4_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC4_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC4_QPC1_AXUSER_RXWQE_BASE 0x563FBE0ull +#define NIC4_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC4_QPC1_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC4_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x563FC40ull +#define NIC4_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC4_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC4_QPC1_AXUSER_DB_FIFO_BASE 0x563FCA0ull +#define NIC4_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC4_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC4_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x563FD00ull +#define NIC4_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC4_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC4_QPC1_AXUSER_ERR_FIFO_BASE 0x563FD60ull +#define NIC4_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC4_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC4_QPC1_AXUSER_QPC_RESP_BASE 0x563FDC0ull +#define NIC4_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC4_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC4_QPC1_AXUSER_QPC_REQ_BASE 0x563FE20ull +#define NIC4_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC4_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC4_QPC1_SPECIAL_BASE 0x563FE80ull +#define NIC4_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_QPC1_SPECIAL_SECTION 0x8180 +#define mmNIC4_TMR_BASE 0x5648000ull +#define NIC4_TMR_MAX_OFFSET 0x1000 +#define NIC4_TMR_SECTION 0xD600 +#define mmNIC4_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5648D60ull +#define NIC4_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC4_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 +#define mmNIC4_TMR_AXUSER_TMR_FIFO_BASE 0x5648DC0ull +#define NIC4_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC4_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 +#define mmNIC4_TMR_AXUSER_TMR_FSM_BASE 0x5648E20ull +#define NIC4_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC4_TMR_AXUSER_TMR_FSM_SECTION 0x6000 +#define mmNIC4_TMR_SPECIAL_BASE 0x5648E80ull +#define NIC4_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_TMR_SPECIAL_SECTION 0x1800 +#define mmNIC4_RXB_CORE_BASE 0x5649000ull +#define NIC4_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC4_RXB_CORE_SECTION 0x6100 +#define mmNIC4_RXB_CORE_SCT_AWUSER_BASE 0x5649610ull +#define NIC4_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC4_RXB_CORE_SCT_AWUSER_SECTION 0x8700 +#define mmNIC4_RXB_CORE_SPECIAL_BASE 0x5649E80ull +#define NIC4_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_RXB_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC4_RXE0_BASE 0x564A000ull +#define NIC4_RXE0_MAX_OFFSET 0x1000 +#define NIC4_RXE0_SECTION 0x9000 +#define mmNIC4_RXE0_WQE_ARUSER_BASE 0x564A900ull +#define NIC4_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC4_RXE0_WQE_ARUSER_SECTION 0x5800 +#define mmNIC4_RXE0_SPECIAL_BASE 0x564AE80ull +#define NIC4_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_RXE0_SPECIAL_SECTION 0x1800 +#define mmNIC4_RXE1_BASE 0x564B000ull +#define NIC4_RXE1_MAX_OFFSET 0x1000 +#define NIC4_RXE1_SECTION 0x9000 +#define mmNIC4_RXE1_WQE_ARUSER_BASE 0x564B900ull +#define NIC4_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC4_RXE1_WQE_ARUSER_SECTION 0x5800 +#define mmNIC4_RXE1_SPECIAL_BASE 0x564BE80ull +#define NIC4_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_RXE1_SPECIAL_SECTION 0x1800 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ0_BASE 0x564C000ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ1_BASE 0x564C050ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ2_BASE 0x564C0A0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ3_BASE 0x564C0F0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ4_BASE 0x564C140ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ5_BASE 0x564C190ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ6_BASE 0x564C1E0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ7_BASE 0x564C230ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ8_BASE 0x564C280ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ9_BASE 0x564C2D0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ10_BASE 0x564C320ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ11_BASE 0x564C370ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ12_BASE 0x564C3C0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ13_BASE 0x564C410ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ14_BASE 0x564C460ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ15_BASE 0x564C4B0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ16_BASE 0x564C500ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ17_BASE 0x564C550ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ18_BASE 0x564C5A0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ19_BASE 0x564C5F0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ20_BASE 0x564C640ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ21_BASE 0x564C690ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ22_BASE 0x564C6E0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ23_BASE 0x564C730ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ24_BASE 0x564C780ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ25_BASE 0x564C7D0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ26_BASE 0x564C820ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ27_BASE 0x564C870ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ28_BASE 0x564C8C0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ29_BASE 0x564C910ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ30_BASE 0x564C960ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ31_BASE 0x564C9B0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC4_RXE0_AXUSER_SPECIAL_BASE 0x564CE80ull +#define NIC4_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_RXE0_AXUSER_SPECIAL_SECTION 0x1800 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ0_BASE 0x564D000ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ1_BASE 0x564D050ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ2_BASE 0x564D0A0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ3_BASE 0x564D0F0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ4_BASE 0x564D140ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ5_BASE 0x564D190ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ6_BASE 0x564D1E0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ7_BASE 0x564D230ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ8_BASE 0x564D280ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ9_BASE 0x564D2D0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ10_BASE 0x564D320ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ11_BASE 0x564D370ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ12_BASE 0x564D3C0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ13_BASE 0x564D410ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ14_BASE 0x564D460ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ15_BASE 0x564D4B0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ16_BASE 0x564D500ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ17_BASE 0x564D550ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ18_BASE 0x564D5A0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ19_BASE 0x564D5F0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ20_BASE 0x564D640ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ21_BASE 0x564D690ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ22_BASE 0x564D6E0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ23_BASE 0x564D730ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ24_BASE 0x564D780ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ25_BASE 0x564D7D0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ26_BASE 0x564D820ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ27_BASE 0x564D870ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ28_BASE 0x564D8C0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ29_BASE 0x564D910ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ30_BASE 0x564D960ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ31_BASE 0x564D9B0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC4_RXE1_AXUSER_SPECIAL_BASE 0x564DE80ull +#define NIC4_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_RXE1_AXUSER_SPECIAL_SECTION 0x2180 +#define mmNIC4_TXS0_BASE 0x5650000ull +#define NIC4_TXS0_MAX_OFFSET 0x1000 +#define NIC4_TXS0_SECTION 0xE800 +#define mmNIC4_TXS0_SPECIAL_BASE 0x5650E80ull +#define NIC4_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_TXS0_SPECIAL_SECTION 0x1800 +#define mmNIC4_TXS1_BASE 0x5651000ull +#define NIC4_TXS1_MAX_OFFSET 0x1000 +#define NIC4_TXS1_SECTION 0xE800 +#define mmNIC4_TXS1_SPECIAL_BASE 0x5651E80ull +#define NIC4_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_TXS1_SPECIAL_SECTION 0x1800 +#define mmNIC4_TXE0_BASE 0x5652000ull +#define NIC4_TXE0_MAX_OFFSET 0x1000 +#define NIC4_TXE0_SECTION 0xE800 +#define mmNIC4_TXE0_SPECIAL_BASE 0x5652E80ull +#define NIC4_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_TXE0_SPECIAL_SECTION 0x1800 +#define mmNIC4_TXE1_BASE 0x5653000ull +#define NIC4_TXE1_MAX_OFFSET 0x1000 +#define NIC4_TXE1_SECTION 0xE800 +#define mmNIC4_TXE1_SPECIAL_BASE 0x5653E80ull +#define NIC4_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_TXE1_SPECIAL_SECTION 0x1800 +#define mmNIC4_TXB_BASE 0x5654000ull +#define NIC4_TXB_MAX_OFFSET 0x1000 +#define NIC4_TXB_SECTION 0xE800 +#define mmNIC4_TXB_SPECIAL_BASE 0x5654E80ull +#define NIC4_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_TXB_SPECIAL_SECTION 0x1800 +#define mmNIC4_MSTR_IF_RR_SHRD_HBW_BASE 0x5655000ull +#define NIC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmNIC4_MSTR_IF_RR_PRVT_HBW_BASE 0x5655200ull +#define NIC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmNIC4_MSTR_IF_RR_SHRD_LBW_BASE 0x5655400ull +#define NIC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmNIC4_MSTR_IF_RR_PRVT_LBW_BASE 0x5655600ull +#define NIC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmNIC4_MSTR_IF_E2E_CRDT_BASE 0x5655800ull +#define NIC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC4_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmNIC4_MSTR_IF_AXUSER_BASE 0x5655A80ull +#define NIC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC4_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmNIC4_MSTR_IF_DBG_HBW_BASE 0x5655B00ull +#define NIC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC4_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmNIC4_MSTR_IF_DBG_LBW_BASE 0x5655B80ull +#define NIC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC4_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmNIC4_MSTR_IF_CORE_HBW_BASE 0x5655C00ull +#define NIC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC4_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmNIC4_MSTR_IF_CORE_LBW_BASE 0x5655D80ull +#define NIC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC4_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmNIC4_MSTR_IF_SPECIAL_BASE 0x5655E80ull +#define NIC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmNIC4_TX_AXUSER_BASE 0x5656000ull +#define NIC4_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC4_TX_AXUSER_SECTION 0x2000 +#define mmNIC4_SERDES0_BASE 0x5658000ull +#define NIC4_SERDES0_MAX_OFFSET 0x3E40 +#define NIC4_SERDES0_SECTION 0x4000 +#define mmNIC4_SERDES1_BASE 0x565C000ull +#define NIC4_SERDES1_MAX_OFFSET 0x3E40 +#define NIC4_SERDES1_SECTION 0x4000 +#define mmNIC4_PHY_BASE 0x5660000ull +#define NIC4_PHY_MAX_OFFSET 0x1000 +#define NIC4_PHY_SECTION 0xE800 +#define mmNIC4_PHY_SPECIAL_BASE 0x5660E80ull +#define NIC4_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_PHY_SPECIAL_SECTION 0x7180 +#define mmPRT4_MAC_AUX_BASE 0x5668000ull +#define PRT4_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT4_MAC_AUX_SECTION 0xE800 +#define mmPRT4_MAC_AUX_SPECIAL_BASE 0x5668E80ull +#define PRT4_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT4_MAC_AUX_SPECIAL_SECTION 0x1800 +#define mmPRT4_MAC_CORE_BASE 0x5669000ull +#define PRT4_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT4_MAC_CORE_SECTION 0xE800 +#define mmPRT4_MAC_CORE_SPECIAL_BASE 0x5669E80ull +#define PRT4_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT4_MAC_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC4_MAC_RS_FEC_BASE 0x566A000ull +#define NIC4_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC4_MAC_RS_FEC_SECTION 0x1000 +#define mmNIC4_MAC_GLOB_STAT_CONTROL_REG_BASE 0x566B000ull +#define NIC4_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000 +#define NIC4_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000 +#define mmNIC4_MAC_GLOB_STAT_RX0_BASE 0x566B100ull +#define NIC4_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00 +#define NIC4_MAC_GLOB_STAT_RX0_SECTION 0x8C00 +#define mmNIC4_MAC_GLOB_STAT_RX1_BASE 0x566B18Cull +#define NIC4_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00 +#define NIC4_MAC_GLOB_STAT_RX1_SECTION 0x8C00 +#define mmNIC4_MAC_GLOB_STAT_RX2_BASE 0x566B218ull +#define NIC4_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00 +#define NIC4_MAC_GLOB_STAT_RX2_SECTION 0x8C00 +#define mmNIC4_MAC_GLOB_STAT_RX3_BASE 0x566B2A4ull +#define NIC4_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00 +#define NIC4_MAC_GLOB_STAT_RX3_SECTION 0x8C00 +#define mmNIC4_MAC_GLOB_STAT_TX0_BASE 0x566B330ull +#define NIC4_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800 +#define NIC4_MAC_GLOB_STAT_TX0_SECTION 0x6800 +#define mmNIC4_MAC_GLOB_STAT_TX1_BASE 0x566B398ull +#define NIC4_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800 +#define NIC4_MAC_GLOB_STAT_TX1_SECTION 0x6800 +#define mmNIC4_MAC_GLOB_STAT_TX2_BASE 0x566B400ull +#define NIC4_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800 +#define NIC4_MAC_GLOB_STAT_TX2_SECTION 0x6800 +#define mmNIC4_MAC_GLOB_STAT_TX3_BASE 0x566B468ull +#define NIC4_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800 +#define NIC4_MAC_GLOB_STAT_TX3_SECTION 0x3980 +#define mmNIC4_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x566B800ull +#define NIC4_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC4_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000 +#define mmNIC4_MAC_CH0_MAC_PCS_BASE 0x566C000ull +#define NIC4_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC4_MAC_CH0_MAC_PCS_SECTION 0x4000 +#define mmNIC4_MAC_CH0_MAC_128_BASE 0x566C400ull +#define NIC4_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC4_MAC_CH0_MAC_128_SECTION 0x4000 +#define mmNIC4_MAC_CH0_MAC_AN_BASE 0x566C800ull +#define NIC4_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC4_MAC_CH0_MAC_AN_SECTION 0x8000 +#define mmNIC4_MAC_CH1_MAC_PCS_BASE 0x566D000ull +#define NIC4_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC4_MAC_CH1_MAC_PCS_SECTION 0x4000 +#define mmNIC4_MAC_CH1_MAC_128_BASE 0x566D400ull +#define NIC4_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC4_MAC_CH1_MAC_128_SECTION 0x4000 +#define mmNIC4_MAC_CH1_MAC_AN_BASE 0x566D800ull +#define NIC4_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC4_MAC_CH1_MAC_AN_SECTION 0x8000 +#define mmNIC4_MAC_CH2_MAC_PCS_BASE 0x566E000ull +#define NIC4_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC4_MAC_CH2_MAC_PCS_SECTION 0x4000 +#define mmNIC4_MAC_CH2_MAC_128_BASE 0x566E400ull +#define NIC4_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC4_MAC_CH2_MAC_128_SECTION 0x4000 +#define mmNIC4_MAC_CH2_MAC_AN_BASE 0x566E800ull +#define NIC4_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC4_MAC_CH2_MAC_AN_SECTION 0x8000 +#define mmNIC4_MAC_CH3_MAC_PCS_BASE 0x566F000ull +#define NIC4_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC4_MAC_CH3_MAC_PCS_SECTION 0x4000 +#define mmNIC4_MAC_CH3_MAC_128_BASE 0x566F400ull +#define NIC4_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC4_MAC_CH3_MAC_128_SECTION 0x4000 +#define mmNIC4_MAC_CH3_MAC_AN_BASE 0x566F800ull +#define NIC4_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC4_MAC_CH3_MAC_AN_SECTION 0x10800 +#define mmNIC5_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5680000ull +#define NIC5_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5680080ull +#define NIC5_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5680100ull +#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5680180ull +#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_0_SPECIAL_BASE 0x5680E80ull +#define NIC5_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_0_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5681000ull +#define NIC5_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5681080ull +#define NIC5_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5681100ull +#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5681180ull +#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_1_SPECIAL_BASE 0x5681E80ull +#define NIC5_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_1_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5682000ull +#define NIC5_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5682080ull +#define NIC5_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5682100ull +#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5682180ull +#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_2_SPECIAL_BASE 0x5682E80ull +#define NIC5_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_2_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5683000ull +#define NIC5_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5683080ull +#define NIC5_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5683100ull +#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5683180ull +#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_3_SPECIAL_BASE 0x5683E80ull +#define NIC5_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_3_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5684000ull +#define NIC5_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5684080ull +#define NIC5_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5684100ull +#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5684180ull +#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_4_SPECIAL_BASE 0x5684E80ull +#define NIC5_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_4_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5685000ull +#define NIC5_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5685080ull +#define NIC5_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5685100ull +#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5685180ull +#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_5_SPECIAL_BASE 0x5685E80ull +#define NIC5_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_5_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5686000ull +#define NIC5_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5686080ull +#define NIC5_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5686100ull +#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5686180ull +#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_6_SPECIAL_BASE 0x5686E80ull +#define NIC5_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_6_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5687000ull +#define NIC5_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5687080ull +#define NIC5_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5687100ull +#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5687180ull +#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_7_SPECIAL_BASE 0x5687E80ull +#define NIC5_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_7_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5688000ull +#define NIC5_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5688080ull +#define NIC5_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5688100ull +#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5688180ull +#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_8_SPECIAL_BASE 0x5688E80ull +#define NIC5_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_8_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5689000ull +#define NIC5_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5689080ull +#define NIC5_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5689100ull +#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5689180ull +#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_9_SPECIAL_BASE 0x5689E80ull +#define NIC5_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_9_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_10_UNSECURE_DOORBELL0_BASE 0x568A000ull +#define NIC5_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_10_UNSECURE_DOORBELL1_BASE 0x568A080ull +#define NIC5_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x568A100ull +#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x568A180ull +#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_10_SPECIAL_BASE 0x568AE80ull +#define NIC5_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_10_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_11_UNSECURE_DOORBELL0_BASE 0x568B000ull +#define NIC5_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_11_UNSECURE_DOORBELL1_BASE 0x568B080ull +#define NIC5_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x568B100ull +#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x568B180ull +#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_11_SPECIAL_BASE 0x568BE80ull +#define NIC5_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_11_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_12_UNSECURE_DOORBELL0_BASE 0x568C000ull +#define NIC5_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_12_UNSECURE_DOORBELL1_BASE 0x568C080ull +#define NIC5_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x568C100ull +#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x568C180ull +#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_12_SPECIAL_BASE 0x568CE80ull +#define NIC5_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_12_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_13_UNSECURE_DOORBELL0_BASE 0x568D000ull +#define NIC5_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_13_UNSECURE_DOORBELL1_BASE 0x568D080ull +#define NIC5_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x568D100ull +#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x568D180ull +#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_13_SPECIAL_BASE 0x568DE80ull +#define NIC5_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_13_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR0_14_UNSECURE_DOORBELL0_BASE 0x568E000ull +#define NIC5_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR0_14_UNSECURE_DOORBELL1_BASE 0x568E080ull +#define NIC5_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x568E100ull +#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x568E180ull +#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR0_14_SPECIAL_BASE 0x568EE80ull +#define NIC5_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_14_SPECIAL_SECTION 0x1180 +#define mmNIC5_QM_DCCM0_BASE 0x5690000ull +#define NIC5_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC5_QM_DCCM0_SECTION 0x8000 +#define mmNIC5_QM_ARC_AUX0_BASE 0x5698000ull +#define NIC5_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC5_QM_ARC_AUX0_SECTION 0xE800 +#define mmNIC5_QM_ARC_AUX0_SPECIAL_BASE 0x5698E80ull +#define NIC5_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 +#define mmNIC5_QM0_BASE 0x569A000ull +#define NIC5_QM0_MAX_OFFSET 0x1000 +#define NIC5_QM0_SECTION 0x9000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x569A900ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x569A908ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x569A910ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x569A918ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x569A920ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x569A928ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x569A930ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x569A938ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x569A940ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x569A948ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x569A950ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x569A958ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x569A960ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x569A968ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x569A970ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x569A978ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC5_QM0_AXUSER_SECURED_BASE 0x569AB00ull +#define NIC5_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC5_QM0_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC5_QM0_AXUSER_NONSECURED_BASE 0x569AB80ull +#define NIC5_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC5_QM0_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC5_QM0_DBG_HBW_BASE 0x569AC00ull +#define NIC5_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC5_QM0_DBG_HBW_SECTION 0x8000 +#define mmNIC5_QM0_DBG_LBW_BASE 0x569AC80ull +#define NIC5_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC5_QM0_DBG_LBW_SECTION 0x1000 +#define mmNIC5_QM0_CGM_BASE 0x569AD80ull +#define NIC5_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC5_QM0_CGM_SECTION 0x1000 +#define mmNIC5_QM0_SPECIAL_BASE 0x569AE80ull +#define NIC5_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_QM0_SPECIAL_SECTION 0x4180 +#define mmNIC5_QPC0_BASE 0x569F000ull +#define NIC5_QPC0_MAX_OFFSET 0x1000 +#define NIC5_QPC0_SECTION 0x7200 +#define mmNIC5_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x569F720ull +#define NIC5_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x569F728ull +#define NIC5_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x569F730ull +#define NIC5_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x569F738ull +#define NIC5_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x569F740ull +#define NIC5_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x569F748ull +#define NIC5_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x569F750ull +#define NIC5_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x569F758ull +#define NIC5_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x569F760ull +#define NIC5_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x569F768ull +#define NIC5_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x569F770ull +#define NIC5_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x569F778ull +#define NIC5_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x569F780ull +#define NIC5_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x569F788ull +#define NIC5_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x569F790ull +#define NIC5_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x569F798ull +#define NIC5_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x569F7A0ull +#define NIC5_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x569F7A8ull +#define NIC5_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x569F7B0ull +#define NIC5_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x569F7B8ull +#define NIC5_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x569F7C0ull +#define NIC5_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x569F7C8ull +#define NIC5_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x569F7D0ull +#define NIC5_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x569F7D8ull +#define NIC5_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x569F7E0ull +#define NIC5_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x569F7E8ull +#define NIC5_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x569F7F0ull +#define NIC5_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x569F7F8ull +#define NIC5_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x569F800ull +#define NIC5_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x569F808ull +#define NIC5_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x569F810ull +#define NIC5_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x569F818ull +#define NIC5_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC5_QPC0_AXUSER_CONG_QUE_BASE 0x569FB80ull +#define NIC5_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC5_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC5_QPC0_AXUSER_RXWQE_BASE 0x569FBE0ull +#define NIC5_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC5_QPC0_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC5_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x569FC40ull +#define NIC5_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC5_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC5_QPC0_AXUSER_DB_FIFO_BASE 0x569FCA0ull +#define NIC5_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC5_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC5_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x569FD00ull +#define NIC5_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC5_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC5_QPC0_AXUSER_ERR_FIFO_BASE 0x569FD60ull +#define NIC5_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC5_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC5_QPC0_AXUSER_QPC_RESP_BASE 0x569FDC0ull +#define NIC5_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC5_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC5_QPC0_AXUSER_QPC_REQ_BASE 0x569FE20ull +#define NIC5_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC5_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC5_QPC0_SPECIAL_BASE 0x569FE80ull +#define NIC5_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_QPC0_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_0_UNSECURE_DOORBELL0_BASE 0x56A0000ull +#define NIC5_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_0_UNSECURE_DOORBELL1_BASE 0x56A0080ull +#define NIC5_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x56A0100ull +#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x56A0180ull +#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_0_SPECIAL_BASE 0x56A0E80ull +#define NIC5_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_0_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_1_UNSECURE_DOORBELL0_BASE 0x56A1000ull +#define NIC5_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_1_UNSECURE_DOORBELL1_BASE 0x56A1080ull +#define NIC5_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x56A1100ull +#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x56A1180ull +#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_1_SPECIAL_BASE 0x56A1E80ull +#define NIC5_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_1_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_2_UNSECURE_DOORBELL0_BASE 0x56A2000ull +#define NIC5_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_2_UNSECURE_DOORBELL1_BASE 0x56A2080ull +#define NIC5_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x56A2100ull +#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x56A2180ull +#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_2_SPECIAL_BASE 0x56A2E80ull +#define NIC5_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_2_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_3_UNSECURE_DOORBELL0_BASE 0x56A3000ull +#define NIC5_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_3_UNSECURE_DOORBELL1_BASE 0x56A3080ull +#define NIC5_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x56A3100ull +#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x56A3180ull +#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_3_SPECIAL_BASE 0x56A3E80ull +#define NIC5_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_3_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_4_UNSECURE_DOORBELL0_BASE 0x56A4000ull +#define NIC5_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_4_UNSECURE_DOORBELL1_BASE 0x56A4080ull +#define NIC5_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x56A4100ull +#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x56A4180ull +#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_4_SPECIAL_BASE 0x56A4E80ull +#define NIC5_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_4_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_5_UNSECURE_DOORBELL0_BASE 0x56A5000ull +#define NIC5_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_5_UNSECURE_DOORBELL1_BASE 0x56A5080ull +#define NIC5_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x56A5100ull +#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x56A5180ull +#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_5_SPECIAL_BASE 0x56A5E80ull +#define NIC5_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_5_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_6_UNSECURE_DOORBELL0_BASE 0x56A6000ull +#define NIC5_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_6_UNSECURE_DOORBELL1_BASE 0x56A6080ull +#define NIC5_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x56A6100ull +#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x56A6180ull +#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_6_SPECIAL_BASE 0x56A6E80ull +#define NIC5_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_6_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_7_UNSECURE_DOORBELL0_BASE 0x56A7000ull +#define NIC5_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_7_UNSECURE_DOORBELL1_BASE 0x56A7080ull +#define NIC5_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x56A7100ull +#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x56A7180ull +#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_7_SPECIAL_BASE 0x56A7E80ull +#define NIC5_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_7_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_8_UNSECURE_DOORBELL0_BASE 0x56A8000ull +#define NIC5_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_8_UNSECURE_DOORBELL1_BASE 0x56A8080ull +#define NIC5_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x56A8100ull +#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x56A8180ull +#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_8_SPECIAL_BASE 0x56A8E80ull +#define NIC5_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_8_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_9_UNSECURE_DOORBELL0_BASE 0x56A9000ull +#define NIC5_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_9_UNSECURE_DOORBELL1_BASE 0x56A9080ull +#define NIC5_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x56A9100ull +#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x56A9180ull +#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_9_SPECIAL_BASE 0x56A9E80ull +#define NIC5_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_9_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_10_UNSECURE_DOORBELL0_BASE 0x56AA000ull +#define NIC5_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_10_UNSECURE_DOORBELL1_BASE 0x56AA080ull +#define NIC5_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x56AA100ull +#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x56AA180ull +#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_10_SPECIAL_BASE 0x56AAE80ull +#define NIC5_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_10_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_11_UNSECURE_DOORBELL0_BASE 0x56AB000ull +#define NIC5_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_11_UNSECURE_DOORBELL1_BASE 0x56AB080ull +#define NIC5_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x56AB100ull +#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x56AB180ull +#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_11_SPECIAL_BASE 0x56ABE80ull +#define NIC5_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_11_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_12_UNSECURE_DOORBELL0_BASE 0x56AC000ull +#define NIC5_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_12_UNSECURE_DOORBELL1_BASE 0x56AC080ull +#define NIC5_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x56AC100ull +#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x56AC180ull +#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_12_SPECIAL_BASE 0x56ACE80ull +#define NIC5_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_12_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_13_UNSECURE_DOORBELL0_BASE 0x56AD000ull +#define NIC5_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_13_UNSECURE_DOORBELL1_BASE 0x56AD080ull +#define NIC5_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x56AD100ull +#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x56AD180ull +#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_13_SPECIAL_BASE 0x56ADE80ull +#define NIC5_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_13_SPECIAL_SECTION 0x1800 +#define mmNIC5_UMR1_14_UNSECURE_DOORBELL0_BASE 0x56AE000ull +#define NIC5_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC5_UMR1_14_UNSECURE_DOORBELL1_BASE 0x56AE080ull +#define NIC5_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC5_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x56AE100ull +#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC5_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x56AE180ull +#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC5_UMR1_14_SPECIAL_BASE 0x56AEE80ull +#define NIC5_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_14_SPECIAL_SECTION 0x1180 +#define mmNIC5_QM_DCCM1_BASE 0x56B0000ull +#define NIC5_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC5_QM_DCCM1_SECTION 0x8000 +#define mmNIC5_QM_ARC_AUX1_BASE 0x56B8000ull +#define NIC5_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC5_QM_ARC_AUX1_SECTION 0xE800 +#define mmNIC5_QM_ARC_AUX1_SPECIAL_BASE 0x56B8E80ull +#define NIC5_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 +#define mmNIC5_QM1_BASE 0x56BA000ull +#define NIC5_QM1_MAX_OFFSET 0x1000 +#define NIC5_QM1_SECTION 0x9000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x56BA900ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x56BA908ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x56BA910ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x56BA918ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x56BA920ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x56BA928ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x56BA930ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x56BA938ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x56BA940ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x56BA948ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x56BA950ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x56BA958ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x56BA960ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x56BA968ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x56BA970ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x56BA978ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC5_QM1_AXUSER_SECURED_BASE 0x56BAB00ull +#define NIC5_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC5_QM1_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC5_QM1_AXUSER_NONSECURED_BASE 0x56BAB80ull +#define NIC5_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC5_QM1_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC5_QM1_DBG_HBW_BASE 0x56BAC00ull +#define NIC5_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC5_QM1_DBG_HBW_SECTION 0x8000 +#define mmNIC5_QM1_DBG_LBW_BASE 0x56BAC80ull +#define NIC5_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC5_QM1_DBG_LBW_SECTION 0x1000 +#define mmNIC5_QM1_CGM_BASE 0x56BAD80ull +#define NIC5_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC5_QM1_CGM_SECTION 0x1000 +#define mmNIC5_QM1_SPECIAL_BASE 0x56BAE80ull +#define NIC5_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_QM1_SPECIAL_SECTION 0x4180 +#define mmNIC5_QPC1_BASE 0x56BF000ull +#define NIC5_QPC1_MAX_OFFSET 0x1000 +#define NIC5_QPC1_SECTION 0x7200 +#define mmNIC5_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x56BF720ull +#define NIC5_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x56BF728ull +#define NIC5_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x56BF730ull +#define NIC5_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x56BF738ull +#define NIC5_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x56BF740ull +#define NIC5_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x56BF748ull +#define NIC5_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x56BF750ull +#define NIC5_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x56BF758ull +#define NIC5_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x56BF760ull +#define NIC5_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x56BF768ull +#define NIC5_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x56BF770ull +#define NIC5_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x56BF778ull +#define NIC5_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x56BF780ull +#define NIC5_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x56BF788ull +#define NIC5_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x56BF790ull +#define NIC5_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x56BF798ull +#define NIC5_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x56BF7A0ull +#define NIC5_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x56BF7A8ull +#define NIC5_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x56BF7B0ull +#define NIC5_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x56BF7B8ull +#define NIC5_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x56BF7C0ull +#define NIC5_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x56BF7C8ull +#define NIC5_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x56BF7D0ull +#define NIC5_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x56BF7D8ull +#define NIC5_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x56BF7E0ull +#define NIC5_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x56BF7E8ull +#define NIC5_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x56BF7F0ull +#define NIC5_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x56BF7F8ull +#define NIC5_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x56BF800ull +#define NIC5_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x56BF808ull +#define NIC5_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x56BF810ull +#define NIC5_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC5_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x56BF818ull +#define NIC5_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC5_QPC1_AXUSER_CONG_QUE_BASE 0x56BFB80ull +#define NIC5_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC5_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC5_QPC1_AXUSER_RXWQE_BASE 0x56BFBE0ull +#define NIC5_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC5_QPC1_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC5_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x56BFC40ull +#define NIC5_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC5_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC5_QPC1_AXUSER_DB_FIFO_BASE 0x56BFCA0ull +#define NIC5_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC5_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC5_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x56BFD00ull +#define NIC5_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC5_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC5_QPC1_AXUSER_ERR_FIFO_BASE 0x56BFD60ull +#define NIC5_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC5_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC5_QPC1_AXUSER_QPC_RESP_BASE 0x56BFDC0ull +#define NIC5_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC5_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC5_QPC1_AXUSER_QPC_REQ_BASE 0x56BFE20ull +#define NIC5_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC5_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC5_QPC1_SPECIAL_BASE 0x56BFE80ull +#define NIC5_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_QPC1_SPECIAL_SECTION 0x8180 +#define mmNIC5_TMR_BASE 0x56C8000ull +#define NIC5_TMR_MAX_OFFSET 0x1000 +#define NIC5_TMR_SECTION 0xD600 +#define mmNIC5_TMR_AXUSER_TMR_FREE_LIST_BASE 0x56C8D60ull +#define NIC5_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC5_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 +#define mmNIC5_TMR_AXUSER_TMR_FIFO_BASE 0x56C8DC0ull +#define NIC5_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC5_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 +#define mmNIC5_TMR_AXUSER_TMR_FSM_BASE 0x56C8E20ull +#define NIC5_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC5_TMR_AXUSER_TMR_FSM_SECTION 0x6000 +#define mmNIC5_TMR_SPECIAL_BASE 0x56C8E80ull +#define NIC5_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_TMR_SPECIAL_SECTION 0x1800 +#define mmNIC5_RXB_CORE_BASE 0x56C9000ull +#define NIC5_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC5_RXB_CORE_SECTION 0x6100 +#define mmNIC5_RXB_CORE_SCT_AWUSER_BASE 0x56C9610ull +#define NIC5_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC5_RXB_CORE_SCT_AWUSER_SECTION 0x8700 +#define mmNIC5_RXB_CORE_SPECIAL_BASE 0x56C9E80ull +#define NIC5_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_RXB_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC5_RXE0_BASE 0x56CA000ull +#define NIC5_RXE0_MAX_OFFSET 0x1000 +#define NIC5_RXE0_SECTION 0x9000 +#define mmNIC5_RXE0_WQE_ARUSER_BASE 0x56CA900ull +#define NIC5_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC5_RXE0_WQE_ARUSER_SECTION 0x5800 +#define mmNIC5_RXE0_SPECIAL_BASE 0x56CAE80ull +#define NIC5_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_RXE0_SPECIAL_SECTION 0x1800 +#define mmNIC5_RXE1_BASE 0x56CB000ull +#define NIC5_RXE1_MAX_OFFSET 0x1000 +#define NIC5_RXE1_SECTION 0x9000 +#define mmNIC5_RXE1_WQE_ARUSER_BASE 0x56CB900ull +#define NIC5_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC5_RXE1_WQE_ARUSER_SECTION 0x5800 +#define mmNIC5_RXE1_SPECIAL_BASE 0x56CBE80ull +#define NIC5_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_RXE1_SPECIAL_SECTION 0x1800 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ0_BASE 0x56CC000ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ1_BASE 0x56CC050ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ2_BASE 0x56CC0A0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ3_BASE 0x56CC0F0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ4_BASE 0x56CC140ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ5_BASE 0x56CC190ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ6_BASE 0x56CC1E0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ7_BASE 0x56CC230ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ8_BASE 0x56CC280ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ9_BASE 0x56CC2D0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ10_BASE 0x56CC320ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ11_BASE 0x56CC370ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ12_BASE 0x56CC3C0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ13_BASE 0x56CC410ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ14_BASE 0x56CC460ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ15_BASE 0x56CC4B0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ16_BASE 0x56CC500ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ17_BASE 0x56CC550ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ18_BASE 0x56CC5A0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ19_BASE 0x56CC5F0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ20_BASE 0x56CC640ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ21_BASE 0x56CC690ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ22_BASE 0x56CC6E0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ23_BASE 0x56CC730ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ24_BASE 0x56CC780ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ25_BASE 0x56CC7D0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ26_BASE 0x56CC820ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ27_BASE 0x56CC870ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ28_BASE 0x56CC8C0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ29_BASE 0x56CC910ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ30_BASE 0x56CC960ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ31_BASE 0x56CC9B0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC5_RXE0_AXUSER_SPECIAL_BASE 0x56CCE80ull +#define NIC5_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_RXE0_AXUSER_SPECIAL_SECTION 0x1800 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ0_BASE 0x56CD000ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ1_BASE 0x56CD050ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ2_BASE 0x56CD0A0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ3_BASE 0x56CD0F0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ4_BASE 0x56CD140ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ5_BASE 0x56CD190ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ6_BASE 0x56CD1E0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ7_BASE 0x56CD230ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ8_BASE 0x56CD280ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ9_BASE 0x56CD2D0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ10_BASE 0x56CD320ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ11_BASE 0x56CD370ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ12_BASE 0x56CD3C0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ13_BASE 0x56CD410ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ14_BASE 0x56CD460ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ15_BASE 0x56CD4B0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ16_BASE 0x56CD500ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ17_BASE 0x56CD550ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ18_BASE 0x56CD5A0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ19_BASE 0x56CD5F0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ20_BASE 0x56CD640ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ21_BASE 0x56CD690ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ22_BASE 0x56CD6E0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ23_BASE 0x56CD730ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ24_BASE 0x56CD780ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ25_BASE 0x56CD7D0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ26_BASE 0x56CD820ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ27_BASE 0x56CD870ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ28_BASE 0x56CD8C0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ29_BASE 0x56CD910ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ30_BASE 0x56CD960ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ31_BASE 0x56CD9B0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC5_RXE1_AXUSER_SPECIAL_BASE 0x56CDE80ull +#define NIC5_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_RXE1_AXUSER_SPECIAL_SECTION 0x2180 +#define mmNIC5_TXS0_BASE 0x56D0000ull +#define NIC5_TXS0_MAX_OFFSET 0x1000 +#define NIC5_TXS0_SECTION 0xE800 +#define mmNIC5_TXS0_SPECIAL_BASE 0x56D0E80ull +#define NIC5_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_TXS0_SPECIAL_SECTION 0x1800 +#define mmNIC5_TXS1_BASE 0x56D1000ull +#define NIC5_TXS1_MAX_OFFSET 0x1000 +#define NIC5_TXS1_SECTION 0xE800 +#define mmNIC5_TXS1_SPECIAL_BASE 0x56D1E80ull +#define NIC5_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_TXS1_SPECIAL_SECTION 0x1800 +#define mmNIC5_TXE0_BASE 0x56D2000ull +#define NIC5_TXE0_MAX_OFFSET 0x1000 +#define NIC5_TXE0_SECTION 0xE800 +#define mmNIC5_TXE0_SPECIAL_BASE 0x56D2E80ull +#define NIC5_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_TXE0_SPECIAL_SECTION 0x1800 +#define mmNIC5_TXE1_BASE 0x56D3000ull +#define NIC5_TXE1_MAX_OFFSET 0x1000 +#define NIC5_TXE1_SECTION 0xE800 +#define mmNIC5_TXE1_SPECIAL_BASE 0x56D3E80ull +#define NIC5_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_TXE1_SPECIAL_SECTION 0x1800 +#define mmNIC5_TXB_BASE 0x56D4000ull +#define NIC5_TXB_MAX_OFFSET 0x1000 +#define NIC5_TXB_SECTION 0xE800 +#define mmNIC5_TXB_SPECIAL_BASE 0x56D4E80ull +#define NIC5_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_TXB_SPECIAL_SECTION 0x1800 +#define mmNIC5_MSTR_IF_RR_SHRD_HBW_BASE 0x56D5000ull +#define NIC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmNIC5_MSTR_IF_RR_PRVT_HBW_BASE 0x56D5200ull +#define NIC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmNIC5_MSTR_IF_RR_SHRD_LBW_BASE 0x56D5400ull +#define NIC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmNIC5_MSTR_IF_RR_PRVT_LBW_BASE 0x56D5600ull +#define NIC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmNIC5_MSTR_IF_E2E_CRDT_BASE 0x56D5800ull +#define NIC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC5_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmNIC5_MSTR_IF_AXUSER_BASE 0x56D5A80ull +#define NIC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC5_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmNIC5_MSTR_IF_DBG_HBW_BASE 0x56D5B00ull +#define NIC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC5_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmNIC5_MSTR_IF_DBG_LBW_BASE 0x56D5B80ull +#define NIC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC5_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmNIC5_MSTR_IF_CORE_HBW_BASE 0x56D5C00ull +#define NIC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC5_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmNIC5_MSTR_IF_CORE_LBW_BASE 0x56D5D80ull +#define NIC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC5_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmNIC5_MSTR_IF_SPECIAL_BASE 0x56D5E80ull +#define NIC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmNIC5_TX_AXUSER_BASE 0x56D6000ull +#define NIC5_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC5_TX_AXUSER_SECTION 0x2000 +#define mmNIC5_SERDES0_BASE 0x56D8000ull +#define NIC5_SERDES0_MAX_OFFSET 0x3E40 +#define NIC5_SERDES0_SECTION 0x4000 +#define mmNIC5_SERDES1_BASE 0x56DC000ull +#define NIC5_SERDES1_MAX_OFFSET 0x3E40 +#define NIC5_SERDES1_SECTION 0x4000 +#define mmNIC5_PHY_BASE 0x56E0000ull +#define NIC5_PHY_MAX_OFFSET 0x1000 +#define NIC5_PHY_SECTION 0xE800 +#define mmNIC5_PHY_SPECIAL_BASE 0x56E0E80ull +#define NIC5_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_PHY_SPECIAL_SECTION 0x7180 +#define mmPRT5_MAC_AUX_BASE 0x56E8000ull +#define PRT5_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT5_MAC_AUX_SECTION 0xE800 +#define mmPRT5_MAC_AUX_SPECIAL_BASE 0x56E8E80ull +#define PRT5_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT5_MAC_AUX_SPECIAL_SECTION 0x1800 +#define mmPRT5_MAC_CORE_BASE 0x56E9000ull +#define PRT5_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT5_MAC_CORE_SECTION 0xE800 +#define mmPRT5_MAC_CORE_SPECIAL_BASE 0x56E9E80ull +#define PRT5_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT5_MAC_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC5_MAC_RS_FEC_BASE 0x56EA000ull +#define NIC5_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC5_MAC_RS_FEC_SECTION 0x1000 +#define mmNIC5_MAC_GLOB_STAT_CONTROL_REG_BASE 0x56EB000ull +#define NIC5_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000 +#define NIC5_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000 +#define mmNIC5_MAC_GLOB_STAT_RX0_BASE 0x56EB100ull +#define NIC5_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00 +#define NIC5_MAC_GLOB_STAT_RX0_SECTION 0x8C00 +#define mmNIC5_MAC_GLOB_STAT_RX1_BASE 0x56EB18Cull +#define NIC5_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00 +#define NIC5_MAC_GLOB_STAT_RX1_SECTION 0x8C00 +#define mmNIC5_MAC_GLOB_STAT_RX2_BASE 0x56EB218ull +#define NIC5_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00 +#define NIC5_MAC_GLOB_STAT_RX2_SECTION 0x8C00 +#define mmNIC5_MAC_GLOB_STAT_RX3_BASE 0x56EB2A4ull +#define NIC5_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00 +#define NIC5_MAC_GLOB_STAT_RX3_SECTION 0x8C00 +#define mmNIC5_MAC_GLOB_STAT_TX0_BASE 0x56EB330ull +#define NIC5_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800 +#define NIC5_MAC_GLOB_STAT_TX0_SECTION 0x6800 +#define mmNIC5_MAC_GLOB_STAT_TX1_BASE 0x56EB398ull +#define NIC5_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800 +#define NIC5_MAC_GLOB_STAT_TX1_SECTION 0x6800 +#define mmNIC5_MAC_GLOB_STAT_TX2_BASE 0x56EB400ull +#define NIC5_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800 +#define NIC5_MAC_GLOB_STAT_TX2_SECTION 0x6800 +#define mmNIC5_MAC_GLOB_STAT_TX3_BASE 0x56EB468ull +#define NIC5_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800 +#define NIC5_MAC_GLOB_STAT_TX3_SECTION 0x3980 +#define mmNIC5_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x56EB800ull +#define NIC5_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC5_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000 +#define mmNIC5_MAC_CH0_MAC_PCS_BASE 0x56EC000ull +#define NIC5_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC5_MAC_CH0_MAC_PCS_SECTION 0x4000 +#define mmNIC5_MAC_CH0_MAC_128_BASE 0x56EC400ull +#define NIC5_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC5_MAC_CH0_MAC_128_SECTION 0x4000 +#define mmNIC5_MAC_CH0_MAC_AN_BASE 0x56EC800ull +#define NIC5_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC5_MAC_CH0_MAC_AN_SECTION 0x8000 +#define mmNIC5_MAC_CH1_MAC_PCS_BASE 0x56ED000ull +#define NIC5_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC5_MAC_CH1_MAC_PCS_SECTION 0x4000 +#define mmNIC5_MAC_CH1_MAC_128_BASE 0x56ED400ull +#define NIC5_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC5_MAC_CH1_MAC_128_SECTION 0x4000 +#define mmNIC5_MAC_CH1_MAC_AN_BASE 0x56ED800ull +#define NIC5_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC5_MAC_CH1_MAC_AN_SECTION 0x8000 +#define mmNIC5_MAC_CH2_MAC_PCS_BASE 0x56EE000ull +#define NIC5_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC5_MAC_CH2_MAC_PCS_SECTION 0x4000 +#define mmNIC5_MAC_CH2_MAC_128_BASE 0x56EE400ull +#define NIC5_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC5_MAC_CH2_MAC_128_SECTION 0x4000 +#define mmNIC5_MAC_CH2_MAC_AN_BASE 0x56EE800ull +#define NIC5_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC5_MAC_CH2_MAC_AN_SECTION 0x8000 +#define mmNIC5_MAC_CH3_MAC_PCS_BASE 0x56EF000ull +#define NIC5_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC5_MAC_CH3_MAC_PCS_SECTION 0x4000 +#define mmNIC5_MAC_CH3_MAC_128_BASE 0x56EF400ull +#define NIC5_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC5_MAC_CH3_MAC_128_SECTION 0x4000 +#define mmNIC5_MAC_CH3_MAC_AN_BASE 0x56EF800ull +#define NIC5_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC5_MAC_CH3_MAC_AN_SECTION 0x10800 +#define mmNIC6_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5700000ull +#define NIC6_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5700080ull +#define NIC6_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5700100ull +#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5700180ull +#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_0_SPECIAL_BASE 0x5700E80ull +#define NIC6_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_0_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5701000ull +#define NIC6_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5701080ull +#define NIC6_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5701100ull +#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5701180ull +#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_1_SPECIAL_BASE 0x5701E80ull +#define NIC6_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_1_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5702000ull +#define NIC6_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5702080ull +#define NIC6_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5702100ull +#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5702180ull +#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_2_SPECIAL_BASE 0x5702E80ull +#define NIC6_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_2_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5703000ull +#define NIC6_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5703080ull +#define NIC6_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5703100ull +#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5703180ull +#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_3_SPECIAL_BASE 0x5703E80ull +#define NIC6_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_3_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5704000ull +#define NIC6_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5704080ull +#define NIC6_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5704100ull +#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5704180ull +#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_4_SPECIAL_BASE 0x5704E80ull +#define NIC6_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_4_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5705000ull +#define NIC6_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5705080ull +#define NIC6_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5705100ull +#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5705180ull +#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_5_SPECIAL_BASE 0x5705E80ull +#define NIC6_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_5_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5706000ull +#define NIC6_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5706080ull +#define NIC6_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5706100ull +#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5706180ull +#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_6_SPECIAL_BASE 0x5706E80ull +#define NIC6_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_6_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5707000ull +#define NIC6_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5707080ull +#define NIC6_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5707100ull +#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5707180ull +#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_7_SPECIAL_BASE 0x5707E80ull +#define NIC6_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_7_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5708000ull +#define NIC6_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5708080ull +#define NIC6_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5708100ull +#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5708180ull +#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_8_SPECIAL_BASE 0x5708E80ull +#define NIC6_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_8_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5709000ull +#define NIC6_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5709080ull +#define NIC6_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5709100ull +#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5709180ull +#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_9_SPECIAL_BASE 0x5709E80ull +#define NIC6_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_9_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_10_UNSECURE_DOORBELL0_BASE 0x570A000ull +#define NIC6_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_10_UNSECURE_DOORBELL1_BASE 0x570A080ull +#define NIC6_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x570A100ull +#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x570A180ull +#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_10_SPECIAL_BASE 0x570AE80ull +#define NIC6_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_10_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_11_UNSECURE_DOORBELL0_BASE 0x570B000ull +#define NIC6_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_11_UNSECURE_DOORBELL1_BASE 0x570B080ull +#define NIC6_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x570B100ull +#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x570B180ull +#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_11_SPECIAL_BASE 0x570BE80ull +#define NIC6_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_11_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_12_UNSECURE_DOORBELL0_BASE 0x570C000ull +#define NIC6_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_12_UNSECURE_DOORBELL1_BASE 0x570C080ull +#define NIC6_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x570C100ull +#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x570C180ull +#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_12_SPECIAL_BASE 0x570CE80ull +#define NIC6_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_12_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_13_UNSECURE_DOORBELL0_BASE 0x570D000ull +#define NIC6_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_13_UNSECURE_DOORBELL1_BASE 0x570D080ull +#define NIC6_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x570D100ull +#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x570D180ull +#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_13_SPECIAL_BASE 0x570DE80ull +#define NIC6_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_13_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR0_14_UNSECURE_DOORBELL0_BASE 0x570E000ull +#define NIC6_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR0_14_UNSECURE_DOORBELL1_BASE 0x570E080ull +#define NIC6_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x570E100ull +#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x570E180ull +#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR0_14_SPECIAL_BASE 0x570EE80ull +#define NIC6_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_14_SPECIAL_SECTION 0x1180 +#define mmNIC6_QM_DCCM0_BASE 0x5710000ull +#define NIC6_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC6_QM_DCCM0_SECTION 0x8000 +#define mmNIC6_QM_ARC_AUX0_BASE 0x5718000ull +#define NIC6_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC6_QM_ARC_AUX0_SECTION 0xE800 +#define mmNIC6_QM_ARC_AUX0_SPECIAL_BASE 0x5718E80ull +#define NIC6_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 +#define mmNIC6_QM0_BASE 0x571A000ull +#define NIC6_QM0_MAX_OFFSET 0x1000 +#define NIC6_QM0_SECTION 0x9000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x571A900ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x571A908ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x571A910ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x571A918ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x571A920ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x571A928ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x571A930ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x571A938ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x571A940ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x571A948ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x571A950ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x571A958ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x571A960ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x571A968ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x571A970ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x571A978ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC6_QM0_AXUSER_SECURED_BASE 0x571AB00ull +#define NIC6_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC6_QM0_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC6_QM0_AXUSER_NONSECURED_BASE 0x571AB80ull +#define NIC6_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC6_QM0_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC6_QM0_DBG_HBW_BASE 0x571AC00ull +#define NIC6_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC6_QM0_DBG_HBW_SECTION 0x8000 +#define mmNIC6_QM0_DBG_LBW_BASE 0x571AC80ull +#define NIC6_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC6_QM0_DBG_LBW_SECTION 0x1000 +#define mmNIC6_QM0_CGM_BASE 0x571AD80ull +#define NIC6_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC6_QM0_CGM_SECTION 0x1000 +#define mmNIC6_QM0_SPECIAL_BASE 0x571AE80ull +#define NIC6_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_QM0_SPECIAL_SECTION 0x4180 +#define mmNIC6_QPC0_BASE 0x571F000ull +#define NIC6_QPC0_MAX_OFFSET 0x1000 +#define NIC6_QPC0_SECTION 0x7200 +#define mmNIC6_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x571F720ull +#define NIC6_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x571F728ull +#define NIC6_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x571F730ull +#define NIC6_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x571F738ull +#define NIC6_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x571F740ull +#define NIC6_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x571F748ull +#define NIC6_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x571F750ull +#define NIC6_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x571F758ull +#define NIC6_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x571F760ull +#define NIC6_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x571F768ull +#define NIC6_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x571F770ull +#define NIC6_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x571F778ull +#define NIC6_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x571F780ull +#define NIC6_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x571F788ull +#define NIC6_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x571F790ull +#define NIC6_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x571F798ull +#define NIC6_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x571F7A0ull +#define NIC6_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x571F7A8ull +#define NIC6_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x571F7B0ull +#define NIC6_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x571F7B8ull +#define NIC6_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x571F7C0ull +#define NIC6_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x571F7C8ull +#define NIC6_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x571F7D0ull +#define NIC6_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x571F7D8ull +#define NIC6_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x571F7E0ull +#define NIC6_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x571F7E8ull +#define NIC6_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x571F7F0ull +#define NIC6_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x571F7F8ull +#define NIC6_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x571F800ull +#define NIC6_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x571F808ull +#define NIC6_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x571F810ull +#define NIC6_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x571F818ull +#define NIC6_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC6_QPC0_AXUSER_CONG_QUE_BASE 0x571FB80ull +#define NIC6_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC6_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC6_QPC0_AXUSER_RXWQE_BASE 0x571FBE0ull +#define NIC6_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC6_QPC0_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC6_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x571FC40ull +#define NIC6_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC6_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC6_QPC0_AXUSER_DB_FIFO_BASE 0x571FCA0ull +#define NIC6_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC6_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC6_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x571FD00ull +#define NIC6_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC6_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC6_QPC0_AXUSER_ERR_FIFO_BASE 0x571FD60ull +#define NIC6_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC6_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC6_QPC0_AXUSER_QPC_RESP_BASE 0x571FDC0ull +#define NIC6_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC6_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC6_QPC0_AXUSER_QPC_REQ_BASE 0x571FE20ull +#define NIC6_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC6_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC6_QPC0_SPECIAL_BASE 0x571FE80ull +#define NIC6_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_QPC0_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5720000ull +#define NIC6_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5720080ull +#define NIC6_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5720100ull +#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5720180ull +#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_0_SPECIAL_BASE 0x5720E80ull +#define NIC6_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_0_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5721000ull +#define NIC6_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5721080ull +#define NIC6_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5721100ull +#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5721180ull +#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_1_SPECIAL_BASE 0x5721E80ull +#define NIC6_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_1_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5722000ull +#define NIC6_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5722080ull +#define NIC6_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5722100ull +#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5722180ull +#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_2_SPECIAL_BASE 0x5722E80ull +#define NIC6_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_2_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5723000ull +#define NIC6_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5723080ull +#define NIC6_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5723100ull +#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5723180ull +#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_3_SPECIAL_BASE 0x5723E80ull +#define NIC6_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_3_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5724000ull +#define NIC6_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5724080ull +#define NIC6_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5724100ull +#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5724180ull +#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_4_SPECIAL_BASE 0x5724E80ull +#define NIC6_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_4_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5725000ull +#define NIC6_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5725080ull +#define NIC6_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5725100ull +#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5725180ull +#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_5_SPECIAL_BASE 0x5725E80ull +#define NIC6_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_5_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5726000ull +#define NIC6_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5726080ull +#define NIC6_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5726100ull +#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5726180ull +#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_6_SPECIAL_BASE 0x5726E80ull +#define NIC6_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_6_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5727000ull +#define NIC6_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5727080ull +#define NIC6_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5727100ull +#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5727180ull +#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_7_SPECIAL_BASE 0x5727E80ull +#define NIC6_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_7_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5728000ull +#define NIC6_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5728080ull +#define NIC6_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5728100ull +#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5728180ull +#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_8_SPECIAL_BASE 0x5728E80ull +#define NIC6_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_8_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5729000ull +#define NIC6_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5729080ull +#define NIC6_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5729100ull +#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5729180ull +#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_9_SPECIAL_BASE 0x5729E80ull +#define NIC6_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_9_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_10_UNSECURE_DOORBELL0_BASE 0x572A000ull +#define NIC6_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_10_UNSECURE_DOORBELL1_BASE 0x572A080ull +#define NIC6_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x572A100ull +#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x572A180ull +#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_10_SPECIAL_BASE 0x572AE80ull +#define NIC6_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_10_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_11_UNSECURE_DOORBELL0_BASE 0x572B000ull +#define NIC6_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_11_UNSECURE_DOORBELL1_BASE 0x572B080ull +#define NIC6_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x572B100ull +#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x572B180ull +#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_11_SPECIAL_BASE 0x572BE80ull +#define NIC6_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_11_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_12_UNSECURE_DOORBELL0_BASE 0x572C000ull +#define NIC6_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_12_UNSECURE_DOORBELL1_BASE 0x572C080ull +#define NIC6_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x572C100ull +#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x572C180ull +#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_12_SPECIAL_BASE 0x572CE80ull +#define NIC6_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_12_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_13_UNSECURE_DOORBELL0_BASE 0x572D000ull +#define NIC6_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_13_UNSECURE_DOORBELL1_BASE 0x572D080ull +#define NIC6_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x572D100ull +#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x572D180ull +#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_13_SPECIAL_BASE 0x572DE80ull +#define NIC6_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_13_SPECIAL_SECTION 0x1800 +#define mmNIC6_UMR1_14_UNSECURE_DOORBELL0_BASE 0x572E000ull +#define NIC6_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC6_UMR1_14_UNSECURE_DOORBELL1_BASE 0x572E080ull +#define NIC6_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC6_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x572E100ull +#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC6_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x572E180ull +#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC6_UMR1_14_SPECIAL_BASE 0x572EE80ull +#define NIC6_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_14_SPECIAL_SECTION 0x1180 +#define mmNIC6_QM_DCCM1_BASE 0x5730000ull +#define NIC6_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC6_QM_DCCM1_SECTION 0x8000 +#define mmNIC6_QM_ARC_AUX1_BASE 0x5738000ull +#define NIC6_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC6_QM_ARC_AUX1_SECTION 0xE800 +#define mmNIC6_QM_ARC_AUX1_SPECIAL_BASE 0x5738E80ull +#define NIC6_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 +#define mmNIC6_QM1_BASE 0x573A000ull +#define NIC6_QM1_MAX_OFFSET 0x1000 +#define NIC6_QM1_SECTION 0x9000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x573A900ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x573A908ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x573A910ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x573A918ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x573A920ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x573A928ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x573A930ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x573A938ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x573A940ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x573A948ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x573A950ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x573A958ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x573A960ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x573A968ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x573A970ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x573A978ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC6_QM1_AXUSER_SECURED_BASE 0x573AB00ull +#define NIC6_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC6_QM1_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC6_QM1_AXUSER_NONSECURED_BASE 0x573AB80ull +#define NIC6_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC6_QM1_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC6_QM1_DBG_HBW_BASE 0x573AC00ull +#define NIC6_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC6_QM1_DBG_HBW_SECTION 0x8000 +#define mmNIC6_QM1_DBG_LBW_BASE 0x573AC80ull +#define NIC6_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC6_QM1_DBG_LBW_SECTION 0x1000 +#define mmNIC6_QM1_CGM_BASE 0x573AD80ull +#define NIC6_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC6_QM1_CGM_SECTION 0x1000 +#define mmNIC6_QM1_SPECIAL_BASE 0x573AE80ull +#define NIC6_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_QM1_SPECIAL_SECTION 0x4180 +#define mmNIC6_QPC1_BASE 0x573F000ull +#define NIC6_QPC1_MAX_OFFSET 0x1000 +#define NIC6_QPC1_SECTION 0x7200 +#define mmNIC6_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x573F720ull +#define NIC6_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x573F728ull +#define NIC6_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x573F730ull +#define NIC6_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x573F738ull +#define NIC6_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x573F740ull +#define NIC6_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x573F748ull +#define NIC6_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x573F750ull +#define NIC6_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x573F758ull +#define NIC6_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x573F760ull +#define NIC6_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x573F768ull +#define NIC6_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x573F770ull +#define NIC6_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x573F778ull +#define NIC6_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x573F780ull +#define NIC6_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x573F788ull +#define NIC6_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x573F790ull +#define NIC6_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x573F798ull +#define NIC6_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x573F7A0ull +#define NIC6_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x573F7A8ull +#define NIC6_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x573F7B0ull +#define NIC6_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x573F7B8ull +#define NIC6_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x573F7C0ull +#define NIC6_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x573F7C8ull +#define NIC6_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x573F7D0ull +#define NIC6_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x573F7D8ull +#define NIC6_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x573F7E0ull +#define NIC6_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x573F7E8ull +#define NIC6_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x573F7F0ull +#define NIC6_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x573F7F8ull +#define NIC6_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x573F800ull +#define NIC6_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x573F808ull +#define NIC6_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x573F810ull +#define NIC6_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC6_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x573F818ull +#define NIC6_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC6_QPC1_AXUSER_CONG_QUE_BASE 0x573FB80ull +#define NIC6_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC6_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC6_QPC1_AXUSER_RXWQE_BASE 0x573FBE0ull +#define NIC6_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC6_QPC1_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC6_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x573FC40ull +#define NIC6_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC6_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC6_QPC1_AXUSER_DB_FIFO_BASE 0x573FCA0ull +#define NIC6_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC6_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC6_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x573FD00ull +#define NIC6_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC6_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC6_QPC1_AXUSER_ERR_FIFO_BASE 0x573FD60ull +#define NIC6_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC6_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC6_QPC1_AXUSER_QPC_RESP_BASE 0x573FDC0ull +#define NIC6_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC6_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC6_QPC1_AXUSER_QPC_REQ_BASE 0x573FE20ull +#define NIC6_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC6_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC6_QPC1_SPECIAL_BASE 0x573FE80ull +#define NIC6_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_QPC1_SPECIAL_SECTION 0x8180 +#define mmNIC6_TMR_BASE 0x5748000ull +#define NIC6_TMR_MAX_OFFSET 0x1000 +#define NIC6_TMR_SECTION 0xD600 +#define mmNIC6_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5748D60ull +#define NIC6_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC6_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 +#define mmNIC6_TMR_AXUSER_TMR_FIFO_BASE 0x5748DC0ull +#define NIC6_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC6_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 +#define mmNIC6_TMR_AXUSER_TMR_FSM_BASE 0x5748E20ull +#define NIC6_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC6_TMR_AXUSER_TMR_FSM_SECTION 0x6000 +#define mmNIC6_TMR_SPECIAL_BASE 0x5748E80ull +#define NIC6_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_TMR_SPECIAL_SECTION 0x1800 +#define mmNIC6_RXB_CORE_BASE 0x5749000ull +#define NIC6_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC6_RXB_CORE_SECTION 0x6100 +#define mmNIC6_RXB_CORE_SCT_AWUSER_BASE 0x5749610ull +#define NIC6_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC6_RXB_CORE_SCT_AWUSER_SECTION 0x8700 +#define mmNIC6_RXB_CORE_SPECIAL_BASE 0x5749E80ull +#define NIC6_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_RXB_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC6_RXE0_BASE 0x574A000ull +#define NIC6_RXE0_MAX_OFFSET 0x1000 +#define NIC6_RXE0_SECTION 0x9000 +#define mmNIC6_RXE0_WQE_ARUSER_BASE 0x574A900ull +#define NIC6_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC6_RXE0_WQE_ARUSER_SECTION 0x5800 +#define mmNIC6_RXE0_SPECIAL_BASE 0x574AE80ull +#define NIC6_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_RXE0_SPECIAL_SECTION 0x1800 +#define mmNIC6_RXE1_BASE 0x574B000ull +#define NIC6_RXE1_MAX_OFFSET 0x1000 +#define NIC6_RXE1_SECTION 0x9000 +#define mmNIC6_RXE1_WQE_ARUSER_BASE 0x574B900ull +#define NIC6_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC6_RXE1_WQE_ARUSER_SECTION 0x5800 +#define mmNIC6_RXE1_SPECIAL_BASE 0x574BE80ull +#define NIC6_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_RXE1_SPECIAL_SECTION 0x1800 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ0_BASE 0x574C000ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ1_BASE 0x574C050ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ2_BASE 0x574C0A0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ3_BASE 0x574C0F0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ4_BASE 0x574C140ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ5_BASE 0x574C190ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ6_BASE 0x574C1E0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ7_BASE 0x574C230ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ8_BASE 0x574C280ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ9_BASE 0x574C2D0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ10_BASE 0x574C320ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ11_BASE 0x574C370ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ12_BASE 0x574C3C0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ13_BASE 0x574C410ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ14_BASE 0x574C460ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ15_BASE 0x574C4B0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ16_BASE 0x574C500ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ17_BASE 0x574C550ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ18_BASE 0x574C5A0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ19_BASE 0x574C5F0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ20_BASE 0x574C640ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ21_BASE 0x574C690ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ22_BASE 0x574C6E0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ23_BASE 0x574C730ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ24_BASE 0x574C780ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ25_BASE 0x574C7D0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ26_BASE 0x574C820ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ27_BASE 0x574C870ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ28_BASE 0x574C8C0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ29_BASE 0x574C910ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ30_BASE 0x574C960ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ31_BASE 0x574C9B0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC6_RXE0_AXUSER_SPECIAL_BASE 0x574CE80ull +#define NIC6_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_RXE0_AXUSER_SPECIAL_SECTION 0x1800 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ0_BASE 0x574D000ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ1_BASE 0x574D050ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ2_BASE 0x574D0A0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ3_BASE 0x574D0F0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ4_BASE 0x574D140ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ5_BASE 0x574D190ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ6_BASE 0x574D1E0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ7_BASE 0x574D230ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ8_BASE 0x574D280ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ9_BASE 0x574D2D0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ10_BASE 0x574D320ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ11_BASE 0x574D370ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ12_BASE 0x574D3C0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ13_BASE 0x574D410ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ14_BASE 0x574D460ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ15_BASE 0x574D4B0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ16_BASE 0x574D500ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ17_BASE 0x574D550ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ18_BASE 0x574D5A0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ19_BASE 0x574D5F0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ20_BASE 0x574D640ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ21_BASE 0x574D690ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ22_BASE 0x574D6E0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ23_BASE 0x574D730ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ24_BASE 0x574D780ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ25_BASE 0x574D7D0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ26_BASE 0x574D820ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ27_BASE 0x574D870ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ28_BASE 0x574D8C0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ29_BASE 0x574D910ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ30_BASE 0x574D960ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ31_BASE 0x574D9B0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC6_RXE1_AXUSER_SPECIAL_BASE 0x574DE80ull +#define NIC6_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_RXE1_AXUSER_SPECIAL_SECTION 0x2180 +#define mmNIC6_TXS0_BASE 0x5750000ull +#define NIC6_TXS0_MAX_OFFSET 0x1000 +#define NIC6_TXS0_SECTION 0xE800 +#define mmNIC6_TXS0_SPECIAL_BASE 0x5750E80ull +#define NIC6_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_TXS0_SPECIAL_SECTION 0x1800 +#define mmNIC6_TXS1_BASE 0x5751000ull +#define NIC6_TXS1_MAX_OFFSET 0x1000 +#define NIC6_TXS1_SECTION 0xE800 +#define mmNIC6_TXS1_SPECIAL_BASE 0x5751E80ull +#define NIC6_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_TXS1_SPECIAL_SECTION 0x1800 +#define mmNIC6_TXE0_BASE 0x5752000ull +#define NIC6_TXE0_MAX_OFFSET 0x1000 +#define NIC6_TXE0_SECTION 0xE800 +#define mmNIC6_TXE0_SPECIAL_BASE 0x5752E80ull +#define NIC6_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_TXE0_SPECIAL_SECTION 0x1800 +#define mmNIC6_TXE1_BASE 0x5753000ull +#define NIC6_TXE1_MAX_OFFSET 0x1000 +#define NIC6_TXE1_SECTION 0xE800 +#define mmNIC6_TXE1_SPECIAL_BASE 0x5753E80ull +#define NIC6_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_TXE1_SPECIAL_SECTION 0x1800 +#define mmNIC6_TXB_BASE 0x5754000ull +#define NIC6_TXB_MAX_OFFSET 0x1000 +#define NIC6_TXB_SECTION 0xE800 +#define mmNIC6_TXB_SPECIAL_BASE 0x5754E80ull +#define NIC6_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_TXB_SPECIAL_SECTION 0x1800 +#define mmNIC6_MSTR_IF_RR_SHRD_HBW_BASE 0x5755000ull +#define NIC6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmNIC6_MSTR_IF_RR_PRVT_HBW_BASE 0x5755200ull +#define NIC6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmNIC6_MSTR_IF_RR_SHRD_LBW_BASE 0x5755400ull +#define NIC6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmNIC6_MSTR_IF_RR_PRVT_LBW_BASE 0x5755600ull +#define NIC6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmNIC6_MSTR_IF_E2E_CRDT_BASE 0x5755800ull +#define NIC6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC6_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmNIC6_MSTR_IF_AXUSER_BASE 0x5755A80ull +#define NIC6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC6_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmNIC6_MSTR_IF_DBG_HBW_BASE 0x5755B00ull +#define NIC6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC6_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmNIC6_MSTR_IF_DBG_LBW_BASE 0x5755B80ull +#define NIC6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC6_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmNIC6_MSTR_IF_CORE_HBW_BASE 0x5755C00ull +#define NIC6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC6_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmNIC6_MSTR_IF_CORE_LBW_BASE 0x5755D80ull +#define NIC6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC6_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmNIC6_MSTR_IF_SPECIAL_BASE 0x5755E80ull +#define NIC6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmNIC6_TX_AXUSER_BASE 0x5756000ull +#define NIC6_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC6_TX_AXUSER_SECTION 0x2000 +#define mmNIC6_SERDES0_BASE 0x5758000ull +#define NIC6_SERDES0_MAX_OFFSET 0x3E40 +#define NIC6_SERDES0_SECTION 0x4000 +#define mmNIC6_SERDES1_BASE 0x575C000ull +#define NIC6_SERDES1_MAX_OFFSET 0x3E40 +#define NIC6_SERDES1_SECTION 0x4000 +#define mmNIC6_PHY_BASE 0x5760000ull +#define NIC6_PHY_MAX_OFFSET 0x1000 +#define NIC6_PHY_SECTION 0xE800 +#define mmNIC6_PHY_SPECIAL_BASE 0x5760E80ull +#define NIC6_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_PHY_SPECIAL_SECTION 0x7180 +#define mmPRT6_MAC_AUX_BASE 0x5768000ull +#define PRT6_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT6_MAC_AUX_SECTION 0xE800 +#define mmPRT6_MAC_AUX_SPECIAL_BASE 0x5768E80ull +#define PRT6_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT6_MAC_AUX_SPECIAL_SECTION 0x1800 +#define mmPRT6_MAC_CORE_BASE 0x5769000ull +#define PRT6_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT6_MAC_CORE_SECTION 0xE800 +#define mmPRT6_MAC_CORE_SPECIAL_BASE 0x5769E80ull +#define PRT6_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT6_MAC_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC6_MAC_RS_FEC_BASE 0x576A000ull +#define NIC6_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC6_MAC_RS_FEC_SECTION 0x1000 +#define mmNIC6_MAC_GLOB_STAT_CONTROL_REG_BASE 0x576B000ull +#define NIC6_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000 +#define NIC6_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000 +#define mmNIC6_MAC_GLOB_STAT_RX0_BASE 0x576B100ull +#define NIC6_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00 +#define NIC6_MAC_GLOB_STAT_RX0_SECTION 0x8C00 +#define mmNIC6_MAC_GLOB_STAT_RX1_BASE 0x576B18Cull +#define NIC6_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00 +#define NIC6_MAC_GLOB_STAT_RX1_SECTION 0x8C00 +#define mmNIC6_MAC_GLOB_STAT_RX2_BASE 0x576B218ull +#define NIC6_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00 +#define NIC6_MAC_GLOB_STAT_RX2_SECTION 0x8C00 +#define mmNIC6_MAC_GLOB_STAT_RX3_BASE 0x576B2A4ull +#define NIC6_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00 +#define NIC6_MAC_GLOB_STAT_RX3_SECTION 0x8C00 +#define mmNIC6_MAC_GLOB_STAT_TX0_BASE 0x576B330ull +#define NIC6_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800 +#define NIC6_MAC_GLOB_STAT_TX0_SECTION 0x6800 +#define mmNIC6_MAC_GLOB_STAT_TX1_BASE 0x576B398ull +#define NIC6_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800 +#define NIC6_MAC_GLOB_STAT_TX1_SECTION 0x6800 +#define mmNIC6_MAC_GLOB_STAT_TX2_BASE 0x576B400ull +#define NIC6_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800 +#define NIC6_MAC_GLOB_STAT_TX2_SECTION 0x6800 +#define mmNIC6_MAC_GLOB_STAT_TX3_BASE 0x576B468ull +#define NIC6_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800 +#define NIC6_MAC_GLOB_STAT_TX3_SECTION 0x3980 +#define mmNIC6_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x576B800ull +#define NIC6_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC6_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000 +#define mmNIC6_MAC_CH0_MAC_PCS_BASE 0x576C000ull +#define NIC6_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC6_MAC_CH0_MAC_PCS_SECTION 0x4000 +#define mmNIC6_MAC_CH0_MAC_128_BASE 0x576C400ull +#define NIC6_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC6_MAC_CH0_MAC_128_SECTION 0x4000 +#define mmNIC6_MAC_CH0_MAC_AN_BASE 0x576C800ull +#define NIC6_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC6_MAC_CH0_MAC_AN_SECTION 0x8000 +#define mmNIC6_MAC_CH1_MAC_PCS_BASE 0x576D000ull +#define NIC6_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC6_MAC_CH1_MAC_PCS_SECTION 0x4000 +#define mmNIC6_MAC_CH1_MAC_128_BASE 0x576D400ull +#define NIC6_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC6_MAC_CH1_MAC_128_SECTION 0x4000 +#define mmNIC6_MAC_CH1_MAC_AN_BASE 0x576D800ull +#define NIC6_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC6_MAC_CH1_MAC_AN_SECTION 0x8000 +#define mmNIC6_MAC_CH2_MAC_PCS_BASE 0x576E000ull +#define NIC6_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC6_MAC_CH2_MAC_PCS_SECTION 0x4000 +#define mmNIC6_MAC_CH2_MAC_128_BASE 0x576E400ull +#define NIC6_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC6_MAC_CH2_MAC_128_SECTION 0x4000 +#define mmNIC6_MAC_CH2_MAC_AN_BASE 0x576E800ull +#define NIC6_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC6_MAC_CH2_MAC_AN_SECTION 0x8000 +#define mmNIC6_MAC_CH3_MAC_PCS_BASE 0x576F000ull +#define NIC6_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC6_MAC_CH3_MAC_PCS_SECTION 0x4000 +#define mmNIC6_MAC_CH3_MAC_128_BASE 0x576F400ull +#define NIC6_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC6_MAC_CH3_MAC_128_SECTION 0x4000 +#define mmNIC6_MAC_CH3_MAC_AN_BASE 0x576F800ull +#define NIC6_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC6_MAC_CH3_MAC_AN_SECTION 0x10800 +#define mmNIC7_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5780000ull +#define NIC7_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5780080ull +#define NIC7_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5780100ull +#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5780180ull +#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_0_SPECIAL_BASE 0x5780E80ull +#define NIC7_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_0_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5781000ull +#define NIC7_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5781080ull +#define NIC7_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5781100ull +#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5781180ull +#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_1_SPECIAL_BASE 0x5781E80ull +#define NIC7_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_1_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5782000ull +#define NIC7_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5782080ull +#define NIC7_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5782100ull +#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5782180ull +#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_2_SPECIAL_BASE 0x5782E80ull +#define NIC7_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_2_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5783000ull +#define NIC7_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5783080ull +#define NIC7_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5783100ull +#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5783180ull +#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_3_SPECIAL_BASE 0x5783E80ull +#define NIC7_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_3_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5784000ull +#define NIC7_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5784080ull +#define NIC7_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5784100ull +#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5784180ull +#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_4_SPECIAL_BASE 0x5784E80ull +#define NIC7_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_4_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5785000ull +#define NIC7_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5785080ull +#define NIC7_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5785100ull +#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5785180ull +#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_5_SPECIAL_BASE 0x5785E80ull +#define NIC7_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_5_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5786000ull +#define NIC7_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5786080ull +#define NIC7_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5786100ull +#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5786180ull +#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_6_SPECIAL_BASE 0x5786E80ull +#define NIC7_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_6_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5787000ull +#define NIC7_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5787080ull +#define NIC7_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5787100ull +#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5787180ull +#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_7_SPECIAL_BASE 0x5787E80ull +#define NIC7_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_7_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5788000ull +#define NIC7_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5788080ull +#define NIC7_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5788100ull +#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5788180ull +#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_8_SPECIAL_BASE 0x5788E80ull +#define NIC7_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_8_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5789000ull +#define NIC7_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5789080ull +#define NIC7_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5789100ull +#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5789180ull +#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_9_SPECIAL_BASE 0x5789E80ull +#define NIC7_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_9_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_10_UNSECURE_DOORBELL0_BASE 0x578A000ull +#define NIC7_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_10_UNSECURE_DOORBELL1_BASE 0x578A080ull +#define NIC7_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x578A100ull +#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x578A180ull +#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_10_SPECIAL_BASE 0x578AE80ull +#define NIC7_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_10_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_11_UNSECURE_DOORBELL0_BASE 0x578B000ull +#define NIC7_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_11_UNSECURE_DOORBELL1_BASE 0x578B080ull +#define NIC7_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x578B100ull +#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x578B180ull +#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_11_SPECIAL_BASE 0x578BE80ull +#define NIC7_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_11_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_12_UNSECURE_DOORBELL0_BASE 0x578C000ull +#define NIC7_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_12_UNSECURE_DOORBELL1_BASE 0x578C080ull +#define NIC7_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x578C100ull +#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x578C180ull +#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_12_SPECIAL_BASE 0x578CE80ull +#define NIC7_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_12_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_13_UNSECURE_DOORBELL0_BASE 0x578D000ull +#define NIC7_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_13_UNSECURE_DOORBELL1_BASE 0x578D080ull +#define NIC7_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x578D100ull +#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x578D180ull +#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_13_SPECIAL_BASE 0x578DE80ull +#define NIC7_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_13_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR0_14_UNSECURE_DOORBELL0_BASE 0x578E000ull +#define NIC7_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR0_14_UNSECURE_DOORBELL1_BASE 0x578E080ull +#define NIC7_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x578E100ull +#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x578E180ull +#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR0_14_SPECIAL_BASE 0x578EE80ull +#define NIC7_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_14_SPECIAL_SECTION 0x1180 +#define mmNIC7_QM_DCCM0_BASE 0x5790000ull +#define NIC7_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC7_QM_DCCM0_SECTION 0x8000 +#define mmNIC7_QM_ARC_AUX0_BASE 0x5798000ull +#define NIC7_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC7_QM_ARC_AUX0_SECTION 0xE800 +#define mmNIC7_QM_ARC_AUX0_SPECIAL_BASE 0x5798E80ull +#define NIC7_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 +#define mmNIC7_QM0_BASE 0x579A000ull +#define NIC7_QM0_MAX_OFFSET 0x1000 +#define NIC7_QM0_SECTION 0x9000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x579A900ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x579A908ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x579A910ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x579A918ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x579A920ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x579A928ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x579A930ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x579A938ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x579A940ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x579A948ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x579A950ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x579A958ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x579A960ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x579A968ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x579A970ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x579A978ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC7_QM0_AXUSER_SECURED_BASE 0x579AB00ull +#define NIC7_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC7_QM0_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC7_QM0_AXUSER_NONSECURED_BASE 0x579AB80ull +#define NIC7_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC7_QM0_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC7_QM0_DBG_HBW_BASE 0x579AC00ull +#define NIC7_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC7_QM0_DBG_HBW_SECTION 0x8000 +#define mmNIC7_QM0_DBG_LBW_BASE 0x579AC80ull +#define NIC7_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC7_QM0_DBG_LBW_SECTION 0x1000 +#define mmNIC7_QM0_CGM_BASE 0x579AD80ull +#define NIC7_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC7_QM0_CGM_SECTION 0x1000 +#define mmNIC7_QM0_SPECIAL_BASE 0x579AE80ull +#define NIC7_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_QM0_SPECIAL_SECTION 0x4180 +#define mmNIC7_QPC0_BASE 0x579F000ull +#define NIC7_QPC0_MAX_OFFSET 0x1000 +#define NIC7_QPC0_SECTION 0x7200 +#define mmNIC7_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x579F720ull +#define NIC7_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x579F728ull +#define NIC7_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x579F730ull +#define NIC7_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x579F738ull +#define NIC7_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x579F740ull +#define NIC7_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x579F748ull +#define NIC7_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x579F750ull +#define NIC7_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x579F758ull +#define NIC7_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x579F760ull +#define NIC7_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x579F768ull +#define NIC7_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x579F770ull +#define NIC7_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x579F778ull +#define NIC7_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x579F780ull +#define NIC7_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x579F788ull +#define NIC7_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x579F790ull +#define NIC7_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x579F798ull +#define NIC7_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x579F7A0ull +#define NIC7_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x579F7A8ull +#define NIC7_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x579F7B0ull +#define NIC7_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x579F7B8ull +#define NIC7_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x579F7C0ull +#define NIC7_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x579F7C8ull +#define NIC7_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x579F7D0ull +#define NIC7_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x579F7D8ull +#define NIC7_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x579F7E0ull +#define NIC7_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x579F7E8ull +#define NIC7_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x579F7F0ull +#define NIC7_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x579F7F8ull +#define NIC7_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x579F800ull +#define NIC7_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x579F808ull +#define NIC7_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x579F810ull +#define NIC7_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x579F818ull +#define NIC7_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC7_QPC0_AXUSER_CONG_QUE_BASE 0x579FB80ull +#define NIC7_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC7_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC7_QPC0_AXUSER_RXWQE_BASE 0x579FBE0ull +#define NIC7_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC7_QPC0_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC7_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x579FC40ull +#define NIC7_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC7_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC7_QPC0_AXUSER_DB_FIFO_BASE 0x579FCA0ull +#define NIC7_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC7_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC7_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x579FD00ull +#define NIC7_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC7_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC7_QPC0_AXUSER_ERR_FIFO_BASE 0x579FD60ull +#define NIC7_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC7_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC7_QPC0_AXUSER_QPC_RESP_BASE 0x579FDC0ull +#define NIC7_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC7_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC7_QPC0_AXUSER_QPC_REQ_BASE 0x579FE20ull +#define NIC7_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC7_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC7_QPC0_SPECIAL_BASE 0x579FE80ull +#define NIC7_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_QPC0_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_0_UNSECURE_DOORBELL0_BASE 0x57A0000ull +#define NIC7_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_0_UNSECURE_DOORBELL1_BASE 0x57A0080ull +#define NIC7_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x57A0100ull +#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x57A0180ull +#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_0_SPECIAL_BASE 0x57A0E80ull +#define NIC7_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_0_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_1_UNSECURE_DOORBELL0_BASE 0x57A1000ull +#define NIC7_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_1_UNSECURE_DOORBELL1_BASE 0x57A1080ull +#define NIC7_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x57A1100ull +#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x57A1180ull +#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_1_SPECIAL_BASE 0x57A1E80ull +#define NIC7_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_1_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_2_UNSECURE_DOORBELL0_BASE 0x57A2000ull +#define NIC7_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_2_UNSECURE_DOORBELL1_BASE 0x57A2080ull +#define NIC7_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x57A2100ull +#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x57A2180ull +#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_2_SPECIAL_BASE 0x57A2E80ull +#define NIC7_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_2_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_3_UNSECURE_DOORBELL0_BASE 0x57A3000ull +#define NIC7_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_3_UNSECURE_DOORBELL1_BASE 0x57A3080ull +#define NIC7_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x57A3100ull +#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x57A3180ull +#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_3_SPECIAL_BASE 0x57A3E80ull +#define NIC7_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_3_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_4_UNSECURE_DOORBELL0_BASE 0x57A4000ull +#define NIC7_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_4_UNSECURE_DOORBELL1_BASE 0x57A4080ull +#define NIC7_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x57A4100ull +#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x57A4180ull +#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_4_SPECIAL_BASE 0x57A4E80ull +#define NIC7_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_4_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_5_UNSECURE_DOORBELL0_BASE 0x57A5000ull +#define NIC7_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_5_UNSECURE_DOORBELL1_BASE 0x57A5080ull +#define NIC7_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x57A5100ull +#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x57A5180ull +#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_5_SPECIAL_BASE 0x57A5E80ull +#define NIC7_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_5_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_6_UNSECURE_DOORBELL0_BASE 0x57A6000ull +#define NIC7_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_6_UNSECURE_DOORBELL1_BASE 0x57A6080ull +#define NIC7_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x57A6100ull +#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x57A6180ull +#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_6_SPECIAL_BASE 0x57A6E80ull +#define NIC7_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_6_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_7_UNSECURE_DOORBELL0_BASE 0x57A7000ull +#define NIC7_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_7_UNSECURE_DOORBELL1_BASE 0x57A7080ull +#define NIC7_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x57A7100ull +#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x57A7180ull +#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_7_SPECIAL_BASE 0x57A7E80ull +#define NIC7_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_7_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_8_UNSECURE_DOORBELL0_BASE 0x57A8000ull +#define NIC7_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_8_UNSECURE_DOORBELL1_BASE 0x57A8080ull +#define NIC7_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x57A8100ull +#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x57A8180ull +#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_8_SPECIAL_BASE 0x57A8E80ull +#define NIC7_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_8_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_9_UNSECURE_DOORBELL0_BASE 0x57A9000ull +#define NIC7_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_9_UNSECURE_DOORBELL1_BASE 0x57A9080ull +#define NIC7_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x57A9100ull +#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x57A9180ull +#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_9_SPECIAL_BASE 0x57A9E80ull +#define NIC7_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_9_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_10_UNSECURE_DOORBELL0_BASE 0x57AA000ull +#define NIC7_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_10_UNSECURE_DOORBELL1_BASE 0x57AA080ull +#define NIC7_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x57AA100ull +#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x57AA180ull +#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_10_SPECIAL_BASE 0x57AAE80ull +#define NIC7_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_10_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_11_UNSECURE_DOORBELL0_BASE 0x57AB000ull +#define NIC7_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_11_UNSECURE_DOORBELL1_BASE 0x57AB080ull +#define NIC7_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x57AB100ull +#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x57AB180ull +#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_11_SPECIAL_BASE 0x57ABE80ull +#define NIC7_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_11_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_12_UNSECURE_DOORBELL0_BASE 0x57AC000ull +#define NIC7_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_12_UNSECURE_DOORBELL1_BASE 0x57AC080ull +#define NIC7_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x57AC100ull +#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x57AC180ull +#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_12_SPECIAL_BASE 0x57ACE80ull +#define NIC7_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_12_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_13_UNSECURE_DOORBELL0_BASE 0x57AD000ull +#define NIC7_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_13_UNSECURE_DOORBELL1_BASE 0x57AD080ull +#define NIC7_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x57AD100ull +#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x57AD180ull +#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_13_SPECIAL_BASE 0x57ADE80ull +#define NIC7_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_13_SPECIAL_SECTION 0x1800 +#define mmNIC7_UMR1_14_UNSECURE_DOORBELL0_BASE 0x57AE000ull +#define NIC7_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC7_UMR1_14_UNSECURE_DOORBELL1_BASE 0x57AE080ull +#define NIC7_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC7_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x57AE100ull +#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC7_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x57AE180ull +#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC7_UMR1_14_SPECIAL_BASE 0x57AEE80ull +#define NIC7_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_14_SPECIAL_SECTION 0x1180 +#define mmNIC7_QM_DCCM1_BASE 0x57B0000ull +#define NIC7_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC7_QM_DCCM1_SECTION 0x8000 +#define mmNIC7_QM_ARC_AUX1_BASE 0x57B8000ull +#define NIC7_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC7_QM_ARC_AUX1_SECTION 0xE800 +#define mmNIC7_QM_ARC_AUX1_SPECIAL_BASE 0x57B8E80ull +#define NIC7_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 +#define mmNIC7_QM1_BASE 0x57BA000ull +#define NIC7_QM1_MAX_OFFSET 0x1000 +#define NIC7_QM1_SECTION 0x9000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x57BA900ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x57BA908ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x57BA910ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x57BA918ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x57BA920ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x57BA928ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x57BA930ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x57BA938ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x57BA940ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x57BA948ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x57BA950ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x57BA958ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x57BA960ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x57BA968ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x57BA970ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x57BA978ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC7_QM1_AXUSER_SECURED_BASE 0x57BAB00ull +#define NIC7_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC7_QM1_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC7_QM1_AXUSER_NONSECURED_BASE 0x57BAB80ull +#define NIC7_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC7_QM1_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC7_QM1_DBG_HBW_BASE 0x57BAC00ull +#define NIC7_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC7_QM1_DBG_HBW_SECTION 0x8000 +#define mmNIC7_QM1_DBG_LBW_BASE 0x57BAC80ull +#define NIC7_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC7_QM1_DBG_LBW_SECTION 0x1000 +#define mmNIC7_QM1_CGM_BASE 0x57BAD80ull +#define NIC7_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC7_QM1_CGM_SECTION 0x1000 +#define mmNIC7_QM1_SPECIAL_BASE 0x57BAE80ull +#define NIC7_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_QM1_SPECIAL_SECTION 0x4180 +#define mmNIC7_QPC1_BASE 0x57BF000ull +#define NIC7_QPC1_MAX_OFFSET 0x1000 +#define NIC7_QPC1_SECTION 0x7200 +#define mmNIC7_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x57BF720ull +#define NIC7_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x57BF728ull +#define NIC7_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x57BF730ull +#define NIC7_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x57BF738ull +#define NIC7_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x57BF740ull +#define NIC7_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x57BF748ull +#define NIC7_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x57BF750ull +#define NIC7_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x57BF758ull +#define NIC7_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x57BF760ull +#define NIC7_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x57BF768ull +#define NIC7_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x57BF770ull +#define NIC7_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x57BF778ull +#define NIC7_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x57BF780ull +#define NIC7_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x57BF788ull +#define NIC7_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x57BF790ull +#define NIC7_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x57BF798ull +#define NIC7_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x57BF7A0ull +#define NIC7_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x57BF7A8ull +#define NIC7_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x57BF7B0ull +#define NIC7_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x57BF7B8ull +#define NIC7_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x57BF7C0ull +#define NIC7_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x57BF7C8ull +#define NIC7_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x57BF7D0ull +#define NIC7_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x57BF7D8ull +#define NIC7_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x57BF7E0ull +#define NIC7_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x57BF7E8ull +#define NIC7_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x57BF7F0ull +#define NIC7_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x57BF7F8ull +#define NIC7_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x57BF800ull +#define NIC7_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x57BF808ull +#define NIC7_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x57BF810ull +#define NIC7_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC7_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x57BF818ull +#define NIC7_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC7_QPC1_AXUSER_CONG_QUE_BASE 0x57BFB80ull +#define NIC7_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC7_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC7_QPC1_AXUSER_RXWQE_BASE 0x57BFBE0ull +#define NIC7_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC7_QPC1_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC7_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x57BFC40ull +#define NIC7_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC7_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC7_QPC1_AXUSER_DB_FIFO_BASE 0x57BFCA0ull +#define NIC7_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC7_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC7_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x57BFD00ull +#define NIC7_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC7_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC7_QPC1_AXUSER_ERR_FIFO_BASE 0x57BFD60ull +#define NIC7_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC7_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC7_QPC1_AXUSER_QPC_RESP_BASE 0x57BFDC0ull +#define NIC7_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC7_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC7_QPC1_AXUSER_QPC_REQ_BASE 0x57BFE20ull +#define NIC7_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC7_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC7_QPC1_SPECIAL_BASE 0x57BFE80ull +#define NIC7_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_QPC1_SPECIAL_SECTION 0x8180 +#define mmNIC7_TMR_BASE 0x57C8000ull +#define NIC7_TMR_MAX_OFFSET 0x1000 +#define NIC7_TMR_SECTION 0xD600 +#define mmNIC7_TMR_AXUSER_TMR_FREE_LIST_BASE 0x57C8D60ull +#define NIC7_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC7_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 +#define mmNIC7_TMR_AXUSER_TMR_FIFO_BASE 0x57C8DC0ull +#define NIC7_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC7_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 +#define mmNIC7_TMR_AXUSER_TMR_FSM_BASE 0x57C8E20ull +#define NIC7_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC7_TMR_AXUSER_TMR_FSM_SECTION 0x6000 +#define mmNIC7_TMR_SPECIAL_BASE 0x57C8E80ull +#define NIC7_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_TMR_SPECIAL_SECTION 0x1800 +#define mmNIC7_RXB_CORE_BASE 0x57C9000ull +#define NIC7_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC7_RXB_CORE_SECTION 0x6100 +#define mmNIC7_RXB_CORE_SCT_AWUSER_BASE 0x57C9610ull +#define NIC7_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC7_RXB_CORE_SCT_AWUSER_SECTION 0x8700 +#define mmNIC7_RXB_CORE_SPECIAL_BASE 0x57C9E80ull +#define NIC7_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_RXB_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC7_RXE0_BASE 0x57CA000ull +#define NIC7_RXE0_MAX_OFFSET 0x1000 +#define NIC7_RXE0_SECTION 0x9000 +#define mmNIC7_RXE0_WQE_ARUSER_BASE 0x57CA900ull +#define NIC7_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC7_RXE0_WQE_ARUSER_SECTION 0x5800 +#define mmNIC7_RXE0_SPECIAL_BASE 0x57CAE80ull +#define NIC7_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_RXE0_SPECIAL_SECTION 0x1800 +#define mmNIC7_RXE1_BASE 0x57CB000ull +#define NIC7_RXE1_MAX_OFFSET 0x1000 +#define NIC7_RXE1_SECTION 0x9000 +#define mmNIC7_RXE1_WQE_ARUSER_BASE 0x57CB900ull +#define NIC7_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC7_RXE1_WQE_ARUSER_SECTION 0x5800 +#define mmNIC7_RXE1_SPECIAL_BASE 0x57CBE80ull +#define NIC7_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_RXE1_SPECIAL_SECTION 0x1800 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ0_BASE 0x57CC000ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ1_BASE 0x57CC050ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ2_BASE 0x57CC0A0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ3_BASE 0x57CC0F0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ4_BASE 0x57CC140ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ5_BASE 0x57CC190ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ6_BASE 0x57CC1E0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ7_BASE 0x57CC230ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ8_BASE 0x57CC280ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ9_BASE 0x57CC2D0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ10_BASE 0x57CC320ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ11_BASE 0x57CC370ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ12_BASE 0x57CC3C0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ13_BASE 0x57CC410ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ14_BASE 0x57CC460ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ15_BASE 0x57CC4B0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ16_BASE 0x57CC500ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ17_BASE 0x57CC550ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ18_BASE 0x57CC5A0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ19_BASE 0x57CC5F0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ20_BASE 0x57CC640ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ21_BASE 0x57CC690ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ22_BASE 0x57CC6E0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ23_BASE 0x57CC730ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ24_BASE 0x57CC780ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ25_BASE 0x57CC7D0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ26_BASE 0x57CC820ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ27_BASE 0x57CC870ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ28_BASE 0x57CC8C0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ29_BASE 0x57CC910ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ30_BASE 0x57CC960ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ31_BASE 0x57CC9B0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC7_RXE0_AXUSER_SPECIAL_BASE 0x57CCE80ull +#define NIC7_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_RXE0_AXUSER_SPECIAL_SECTION 0x1800 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ0_BASE 0x57CD000ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ1_BASE 0x57CD050ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ2_BASE 0x57CD0A0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ3_BASE 0x57CD0F0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ4_BASE 0x57CD140ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ5_BASE 0x57CD190ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ6_BASE 0x57CD1E0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ7_BASE 0x57CD230ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ8_BASE 0x57CD280ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ9_BASE 0x57CD2D0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ10_BASE 0x57CD320ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ11_BASE 0x57CD370ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ12_BASE 0x57CD3C0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ13_BASE 0x57CD410ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ14_BASE 0x57CD460ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ15_BASE 0x57CD4B0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ16_BASE 0x57CD500ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ17_BASE 0x57CD550ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ18_BASE 0x57CD5A0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ19_BASE 0x57CD5F0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ20_BASE 0x57CD640ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ21_BASE 0x57CD690ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ22_BASE 0x57CD6E0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ23_BASE 0x57CD730ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ24_BASE 0x57CD780ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ25_BASE 0x57CD7D0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ26_BASE 0x57CD820ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ27_BASE 0x57CD870ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ28_BASE 0x57CD8C0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ29_BASE 0x57CD910ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ30_BASE 0x57CD960ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ31_BASE 0x57CD9B0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC7_RXE1_AXUSER_SPECIAL_BASE 0x57CDE80ull +#define NIC7_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_RXE1_AXUSER_SPECIAL_SECTION 0x2180 +#define mmNIC7_TXS0_BASE 0x57D0000ull +#define NIC7_TXS0_MAX_OFFSET 0x1000 +#define NIC7_TXS0_SECTION 0xE800 +#define mmNIC7_TXS0_SPECIAL_BASE 0x57D0E80ull +#define NIC7_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_TXS0_SPECIAL_SECTION 0x1800 +#define mmNIC7_TXS1_BASE 0x57D1000ull +#define NIC7_TXS1_MAX_OFFSET 0x1000 +#define NIC7_TXS1_SECTION 0xE800 +#define mmNIC7_TXS1_SPECIAL_BASE 0x57D1E80ull +#define NIC7_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_TXS1_SPECIAL_SECTION 0x1800 +#define mmNIC7_TXE0_BASE 0x57D2000ull +#define NIC7_TXE0_MAX_OFFSET 0x1000 +#define NIC7_TXE0_SECTION 0xE800 +#define mmNIC7_TXE0_SPECIAL_BASE 0x57D2E80ull +#define NIC7_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_TXE0_SPECIAL_SECTION 0x1800 +#define mmNIC7_TXE1_BASE 0x57D3000ull +#define NIC7_TXE1_MAX_OFFSET 0x1000 +#define NIC7_TXE1_SECTION 0xE800 +#define mmNIC7_TXE1_SPECIAL_BASE 0x57D3E80ull +#define NIC7_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_TXE1_SPECIAL_SECTION 0x1800 +#define mmNIC7_TXB_BASE 0x57D4000ull +#define NIC7_TXB_MAX_OFFSET 0x1000 +#define NIC7_TXB_SECTION 0xE800 +#define mmNIC7_TXB_SPECIAL_BASE 0x57D4E80ull +#define NIC7_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_TXB_SPECIAL_SECTION 0x1800 +#define mmNIC7_MSTR_IF_RR_SHRD_HBW_BASE 0x57D5000ull +#define NIC7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmNIC7_MSTR_IF_RR_PRVT_HBW_BASE 0x57D5200ull +#define NIC7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmNIC7_MSTR_IF_RR_SHRD_LBW_BASE 0x57D5400ull +#define NIC7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmNIC7_MSTR_IF_RR_PRVT_LBW_BASE 0x57D5600ull +#define NIC7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmNIC7_MSTR_IF_E2E_CRDT_BASE 0x57D5800ull +#define NIC7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC7_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmNIC7_MSTR_IF_AXUSER_BASE 0x57D5A80ull +#define NIC7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC7_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmNIC7_MSTR_IF_DBG_HBW_BASE 0x57D5B00ull +#define NIC7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC7_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmNIC7_MSTR_IF_DBG_LBW_BASE 0x57D5B80ull +#define NIC7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC7_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmNIC7_MSTR_IF_CORE_HBW_BASE 0x57D5C00ull +#define NIC7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC7_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmNIC7_MSTR_IF_CORE_LBW_BASE 0x57D5D80ull +#define NIC7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC7_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmNIC7_MSTR_IF_SPECIAL_BASE 0x57D5E80ull +#define NIC7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmNIC7_TX_AXUSER_BASE 0x57D6000ull +#define NIC7_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC7_TX_AXUSER_SECTION 0x2000 +#define mmNIC7_SERDES0_BASE 0x57D8000ull +#define NIC7_SERDES0_MAX_OFFSET 0x3E40 +#define NIC7_SERDES0_SECTION 0x4000 +#define mmNIC7_SERDES1_BASE 0x57DC000ull +#define NIC7_SERDES1_MAX_OFFSET 0x3E40 +#define NIC7_SERDES1_SECTION 0x4000 +#define mmNIC7_PHY_BASE 0x57E0000ull +#define NIC7_PHY_MAX_OFFSET 0x1000 +#define NIC7_PHY_SECTION 0xE800 +#define mmNIC7_PHY_SPECIAL_BASE 0x57E0E80ull +#define NIC7_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_PHY_SPECIAL_SECTION 0x7180 +#define mmPRT7_MAC_AUX_BASE 0x57E8000ull +#define PRT7_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT7_MAC_AUX_SECTION 0xE800 +#define mmPRT7_MAC_AUX_SPECIAL_BASE 0x57E8E80ull +#define PRT7_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT7_MAC_AUX_SPECIAL_SECTION 0x1800 +#define mmPRT7_MAC_CORE_BASE 0x57E9000ull +#define PRT7_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT7_MAC_CORE_SECTION 0xE800 +#define mmPRT7_MAC_CORE_SPECIAL_BASE 0x57E9E80ull +#define PRT7_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT7_MAC_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC7_MAC_RS_FEC_BASE 0x57EA000ull +#define NIC7_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC7_MAC_RS_FEC_SECTION 0x1000 +#define mmNIC7_MAC_GLOB_STAT_CONTROL_REG_BASE 0x57EB000ull +#define NIC7_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000 +#define NIC7_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000 +#define mmNIC7_MAC_GLOB_STAT_RX0_BASE 0x57EB100ull +#define NIC7_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00 +#define NIC7_MAC_GLOB_STAT_RX0_SECTION 0x8C00 +#define mmNIC7_MAC_GLOB_STAT_RX1_BASE 0x57EB18Cull +#define NIC7_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00 +#define NIC7_MAC_GLOB_STAT_RX1_SECTION 0x8C00 +#define mmNIC7_MAC_GLOB_STAT_RX2_BASE 0x57EB218ull +#define NIC7_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00 +#define NIC7_MAC_GLOB_STAT_RX2_SECTION 0x8C00 +#define mmNIC7_MAC_GLOB_STAT_RX3_BASE 0x57EB2A4ull +#define NIC7_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00 +#define NIC7_MAC_GLOB_STAT_RX3_SECTION 0x8C00 +#define mmNIC7_MAC_GLOB_STAT_TX0_BASE 0x57EB330ull +#define NIC7_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800 +#define NIC7_MAC_GLOB_STAT_TX0_SECTION 0x6800 +#define mmNIC7_MAC_GLOB_STAT_TX1_BASE 0x57EB398ull +#define NIC7_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800 +#define NIC7_MAC_GLOB_STAT_TX1_SECTION 0x6800 +#define mmNIC7_MAC_GLOB_STAT_TX2_BASE 0x57EB400ull +#define NIC7_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800 +#define NIC7_MAC_GLOB_STAT_TX2_SECTION 0x6800 +#define mmNIC7_MAC_GLOB_STAT_TX3_BASE 0x57EB468ull +#define NIC7_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800 +#define NIC7_MAC_GLOB_STAT_TX3_SECTION 0x3980 +#define mmNIC7_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x57EB800ull +#define NIC7_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC7_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000 +#define mmNIC7_MAC_CH0_MAC_PCS_BASE 0x57EC000ull +#define NIC7_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC7_MAC_CH0_MAC_PCS_SECTION 0x4000 +#define mmNIC7_MAC_CH0_MAC_128_BASE 0x57EC400ull +#define NIC7_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC7_MAC_CH0_MAC_128_SECTION 0x4000 +#define mmNIC7_MAC_CH0_MAC_AN_BASE 0x57EC800ull +#define NIC7_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC7_MAC_CH0_MAC_AN_SECTION 0x8000 +#define mmNIC7_MAC_CH1_MAC_PCS_BASE 0x57ED000ull +#define NIC7_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC7_MAC_CH1_MAC_PCS_SECTION 0x4000 +#define mmNIC7_MAC_CH1_MAC_128_BASE 0x57ED400ull +#define NIC7_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC7_MAC_CH1_MAC_128_SECTION 0x4000 +#define mmNIC7_MAC_CH1_MAC_AN_BASE 0x57ED800ull +#define NIC7_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC7_MAC_CH1_MAC_AN_SECTION 0x8000 +#define mmNIC7_MAC_CH2_MAC_PCS_BASE 0x57EE000ull +#define NIC7_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC7_MAC_CH2_MAC_PCS_SECTION 0x4000 +#define mmNIC7_MAC_CH2_MAC_128_BASE 0x57EE400ull +#define NIC7_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC7_MAC_CH2_MAC_128_SECTION 0x4000 +#define mmNIC7_MAC_CH2_MAC_AN_BASE 0x57EE800ull +#define NIC7_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC7_MAC_CH2_MAC_AN_SECTION 0x8000 +#define mmNIC7_MAC_CH3_MAC_PCS_BASE 0x57EF000ull +#define NIC7_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC7_MAC_CH3_MAC_PCS_SECTION 0x4000 +#define mmNIC7_MAC_CH3_MAC_128_BASE 0x57EF400ull +#define NIC7_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC7_MAC_CH3_MAC_128_SECTION 0x4000 +#define mmNIC7_MAC_CH3_MAC_AN_BASE 0x57EF800ull +#define NIC7_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC7_MAC_CH3_MAC_AN_SECTION 0x10800 +#define mmNIC8_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5800000ull +#define NIC8_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5800080ull +#define NIC8_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5800100ull +#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5800180ull +#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_0_SPECIAL_BASE 0x5800E80ull +#define NIC8_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_0_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5801000ull +#define NIC8_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5801080ull +#define NIC8_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5801100ull +#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5801180ull +#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_1_SPECIAL_BASE 0x5801E80ull +#define NIC8_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_1_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5802000ull +#define NIC8_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5802080ull +#define NIC8_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5802100ull +#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5802180ull +#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_2_SPECIAL_BASE 0x5802E80ull +#define NIC8_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_2_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5803000ull +#define NIC8_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5803080ull +#define NIC8_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5803100ull +#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5803180ull +#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_3_SPECIAL_BASE 0x5803E80ull +#define NIC8_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_3_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5804000ull +#define NIC8_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5804080ull +#define NIC8_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5804100ull +#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5804180ull +#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_4_SPECIAL_BASE 0x5804E80ull +#define NIC8_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_4_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5805000ull +#define NIC8_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5805080ull +#define NIC8_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5805100ull +#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5805180ull +#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_5_SPECIAL_BASE 0x5805E80ull +#define NIC8_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_5_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5806000ull +#define NIC8_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5806080ull +#define NIC8_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5806100ull +#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5806180ull +#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_6_SPECIAL_BASE 0x5806E80ull +#define NIC8_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_6_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5807000ull +#define NIC8_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5807080ull +#define NIC8_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5807100ull +#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5807180ull +#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_7_SPECIAL_BASE 0x5807E80ull +#define NIC8_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_7_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5808000ull +#define NIC8_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5808080ull +#define NIC8_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5808100ull +#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5808180ull +#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_8_SPECIAL_BASE 0x5808E80ull +#define NIC8_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_8_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5809000ull +#define NIC8_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5809080ull +#define NIC8_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5809100ull +#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5809180ull +#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_9_SPECIAL_BASE 0x5809E80ull +#define NIC8_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_9_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_10_UNSECURE_DOORBELL0_BASE 0x580A000ull +#define NIC8_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_10_UNSECURE_DOORBELL1_BASE 0x580A080ull +#define NIC8_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x580A100ull +#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x580A180ull +#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_10_SPECIAL_BASE 0x580AE80ull +#define NIC8_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_10_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_11_UNSECURE_DOORBELL0_BASE 0x580B000ull +#define NIC8_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_11_UNSECURE_DOORBELL1_BASE 0x580B080ull +#define NIC8_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x580B100ull +#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x580B180ull +#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_11_SPECIAL_BASE 0x580BE80ull +#define NIC8_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_11_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_12_UNSECURE_DOORBELL0_BASE 0x580C000ull +#define NIC8_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_12_UNSECURE_DOORBELL1_BASE 0x580C080ull +#define NIC8_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x580C100ull +#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x580C180ull +#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_12_SPECIAL_BASE 0x580CE80ull +#define NIC8_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_12_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_13_UNSECURE_DOORBELL0_BASE 0x580D000ull +#define NIC8_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_13_UNSECURE_DOORBELL1_BASE 0x580D080ull +#define NIC8_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x580D100ull +#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x580D180ull +#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_13_SPECIAL_BASE 0x580DE80ull +#define NIC8_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_13_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR0_14_UNSECURE_DOORBELL0_BASE 0x580E000ull +#define NIC8_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR0_14_UNSECURE_DOORBELL1_BASE 0x580E080ull +#define NIC8_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x580E100ull +#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x580E180ull +#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR0_14_SPECIAL_BASE 0x580EE80ull +#define NIC8_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_14_SPECIAL_SECTION 0x1180 +#define mmNIC8_QM_DCCM0_BASE 0x5810000ull +#define NIC8_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC8_QM_DCCM0_SECTION 0x8000 +#define mmNIC8_QM_ARC_AUX0_BASE 0x5818000ull +#define NIC8_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC8_QM_ARC_AUX0_SECTION 0xE800 +#define mmNIC8_QM_ARC_AUX0_SPECIAL_BASE 0x5818E80ull +#define NIC8_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 +#define mmNIC8_QM0_BASE 0x581A000ull +#define NIC8_QM0_MAX_OFFSET 0x1000 +#define NIC8_QM0_SECTION 0x9000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x581A900ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x581A908ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x581A910ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x581A918ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x581A920ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x581A928ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x581A930ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x581A938ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x581A940ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x581A948ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x581A950ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x581A958ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x581A960ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x581A968ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x581A970ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x581A978ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC8_QM0_AXUSER_SECURED_BASE 0x581AB00ull +#define NIC8_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC8_QM0_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC8_QM0_AXUSER_NONSECURED_BASE 0x581AB80ull +#define NIC8_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC8_QM0_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC8_QM0_DBG_HBW_BASE 0x581AC00ull +#define NIC8_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC8_QM0_DBG_HBW_SECTION 0x8000 +#define mmNIC8_QM0_DBG_LBW_BASE 0x581AC80ull +#define NIC8_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC8_QM0_DBG_LBW_SECTION 0x1000 +#define mmNIC8_QM0_CGM_BASE 0x581AD80ull +#define NIC8_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC8_QM0_CGM_SECTION 0x1000 +#define mmNIC8_QM0_SPECIAL_BASE 0x581AE80ull +#define NIC8_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_QM0_SPECIAL_SECTION 0x4180 +#define mmNIC8_QPC0_BASE 0x581F000ull +#define NIC8_QPC0_MAX_OFFSET 0x1000 +#define NIC8_QPC0_SECTION 0x7200 +#define mmNIC8_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x581F720ull +#define NIC8_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x581F728ull +#define NIC8_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x581F730ull +#define NIC8_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x581F738ull +#define NIC8_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x581F740ull +#define NIC8_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x581F748ull +#define NIC8_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x581F750ull +#define NIC8_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x581F758ull +#define NIC8_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x581F760ull +#define NIC8_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x581F768ull +#define NIC8_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x581F770ull +#define NIC8_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x581F778ull +#define NIC8_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x581F780ull +#define NIC8_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x581F788ull +#define NIC8_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x581F790ull +#define NIC8_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x581F798ull +#define NIC8_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x581F7A0ull +#define NIC8_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x581F7A8ull +#define NIC8_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x581F7B0ull +#define NIC8_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x581F7B8ull +#define NIC8_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x581F7C0ull +#define NIC8_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x581F7C8ull +#define NIC8_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x581F7D0ull +#define NIC8_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x581F7D8ull +#define NIC8_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x581F7E0ull +#define NIC8_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x581F7E8ull +#define NIC8_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x581F7F0ull +#define NIC8_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x581F7F8ull +#define NIC8_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x581F800ull +#define NIC8_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x581F808ull +#define NIC8_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x581F810ull +#define NIC8_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x581F818ull +#define NIC8_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC8_QPC0_AXUSER_CONG_QUE_BASE 0x581FB80ull +#define NIC8_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC8_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC8_QPC0_AXUSER_RXWQE_BASE 0x581FBE0ull +#define NIC8_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC8_QPC0_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC8_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x581FC40ull +#define NIC8_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC8_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC8_QPC0_AXUSER_DB_FIFO_BASE 0x581FCA0ull +#define NIC8_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC8_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC8_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x581FD00ull +#define NIC8_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC8_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC8_QPC0_AXUSER_ERR_FIFO_BASE 0x581FD60ull +#define NIC8_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC8_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC8_QPC0_AXUSER_QPC_RESP_BASE 0x581FDC0ull +#define NIC8_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC8_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC8_QPC0_AXUSER_QPC_REQ_BASE 0x581FE20ull +#define NIC8_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC8_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC8_QPC0_SPECIAL_BASE 0x581FE80ull +#define NIC8_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_QPC0_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5820000ull +#define NIC8_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5820080ull +#define NIC8_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5820100ull +#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5820180ull +#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_0_SPECIAL_BASE 0x5820E80ull +#define NIC8_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_0_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5821000ull +#define NIC8_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5821080ull +#define NIC8_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5821100ull +#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5821180ull +#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_1_SPECIAL_BASE 0x5821E80ull +#define NIC8_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_1_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5822000ull +#define NIC8_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5822080ull +#define NIC8_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5822100ull +#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5822180ull +#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_2_SPECIAL_BASE 0x5822E80ull +#define NIC8_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_2_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5823000ull +#define NIC8_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5823080ull +#define NIC8_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5823100ull +#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5823180ull +#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_3_SPECIAL_BASE 0x5823E80ull +#define NIC8_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_3_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5824000ull +#define NIC8_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5824080ull +#define NIC8_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5824100ull +#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5824180ull +#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_4_SPECIAL_BASE 0x5824E80ull +#define NIC8_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_4_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5825000ull +#define NIC8_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5825080ull +#define NIC8_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5825100ull +#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5825180ull +#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_5_SPECIAL_BASE 0x5825E80ull +#define NIC8_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_5_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5826000ull +#define NIC8_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5826080ull +#define NIC8_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5826100ull +#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5826180ull +#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_6_SPECIAL_BASE 0x5826E80ull +#define NIC8_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_6_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5827000ull +#define NIC8_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5827080ull +#define NIC8_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5827100ull +#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5827180ull +#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_7_SPECIAL_BASE 0x5827E80ull +#define NIC8_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_7_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5828000ull +#define NIC8_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5828080ull +#define NIC8_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5828100ull +#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5828180ull +#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_8_SPECIAL_BASE 0x5828E80ull +#define NIC8_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_8_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5829000ull +#define NIC8_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5829080ull +#define NIC8_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5829100ull +#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5829180ull +#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_9_SPECIAL_BASE 0x5829E80ull +#define NIC8_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_9_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_10_UNSECURE_DOORBELL0_BASE 0x582A000ull +#define NIC8_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_10_UNSECURE_DOORBELL1_BASE 0x582A080ull +#define NIC8_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x582A100ull +#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x582A180ull +#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_10_SPECIAL_BASE 0x582AE80ull +#define NIC8_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_10_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_11_UNSECURE_DOORBELL0_BASE 0x582B000ull +#define NIC8_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_11_UNSECURE_DOORBELL1_BASE 0x582B080ull +#define NIC8_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x582B100ull +#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x582B180ull +#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_11_SPECIAL_BASE 0x582BE80ull +#define NIC8_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_11_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_12_UNSECURE_DOORBELL0_BASE 0x582C000ull +#define NIC8_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_12_UNSECURE_DOORBELL1_BASE 0x582C080ull +#define NIC8_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x582C100ull +#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x582C180ull +#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_12_SPECIAL_BASE 0x582CE80ull +#define NIC8_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_12_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_13_UNSECURE_DOORBELL0_BASE 0x582D000ull +#define NIC8_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_13_UNSECURE_DOORBELL1_BASE 0x582D080ull +#define NIC8_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x582D100ull +#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x582D180ull +#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_13_SPECIAL_BASE 0x582DE80ull +#define NIC8_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_13_SPECIAL_SECTION 0x1800 +#define mmNIC8_UMR1_14_UNSECURE_DOORBELL0_BASE 0x582E000ull +#define NIC8_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC8_UMR1_14_UNSECURE_DOORBELL1_BASE 0x582E080ull +#define NIC8_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC8_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x582E100ull +#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC8_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x582E180ull +#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC8_UMR1_14_SPECIAL_BASE 0x582EE80ull +#define NIC8_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_14_SPECIAL_SECTION 0x1180 +#define mmNIC8_QM_DCCM1_BASE 0x5830000ull +#define NIC8_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC8_QM_DCCM1_SECTION 0x8000 +#define mmNIC8_QM_ARC_AUX1_BASE 0x5838000ull +#define NIC8_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC8_QM_ARC_AUX1_SECTION 0xE800 +#define mmNIC8_QM_ARC_AUX1_SPECIAL_BASE 0x5838E80ull +#define NIC8_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 +#define mmNIC8_QM1_BASE 0x583A000ull +#define NIC8_QM1_MAX_OFFSET 0x1000 +#define NIC8_QM1_SECTION 0x9000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x583A900ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x583A908ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x583A910ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x583A918ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x583A920ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x583A928ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x583A930ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x583A938ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x583A940ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x583A948ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x583A950ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x583A958ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x583A960ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x583A968ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x583A970ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x583A978ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC8_QM1_AXUSER_SECURED_BASE 0x583AB00ull +#define NIC8_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC8_QM1_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC8_QM1_AXUSER_NONSECURED_BASE 0x583AB80ull +#define NIC8_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC8_QM1_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC8_QM1_DBG_HBW_BASE 0x583AC00ull +#define NIC8_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC8_QM1_DBG_HBW_SECTION 0x8000 +#define mmNIC8_QM1_DBG_LBW_BASE 0x583AC80ull +#define NIC8_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC8_QM1_DBG_LBW_SECTION 0x1000 +#define mmNIC8_QM1_CGM_BASE 0x583AD80ull +#define NIC8_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC8_QM1_CGM_SECTION 0x1000 +#define mmNIC8_QM1_SPECIAL_BASE 0x583AE80ull +#define NIC8_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_QM1_SPECIAL_SECTION 0x4180 +#define mmNIC8_QPC1_BASE 0x583F000ull +#define NIC8_QPC1_MAX_OFFSET 0x1000 +#define NIC8_QPC1_SECTION 0x7200 +#define mmNIC8_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x583F720ull +#define NIC8_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x583F728ull +#define NIC8_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x583F730ull +#define NIC8_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x583F738ull +#define NIC8_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x583F740ull +#define NIC8_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x583F748ull +#define NIC8_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x583F750ull +#define NIC8_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x583F758ull +#define NIC8_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x583F760ull +#define NIC8_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x583F768ull +#define NIC8_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x583F770ull +#define NIC8_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x583F778ull +#define NIC8_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x583F780ull +#define NIC8_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x583F788ull +#define NIC8_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x583F790ull +#define NIC8_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x583F798ull +#define NIC8_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x583F7A0ull +#define NIC8_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x583F7A8ull +#define NIC8_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x583F7B0ull +#define NIC8_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x583F7B8ull +#define NIC8_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x583F7C0ull +#define NIC8_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x583F7C8ull +#define NIC8_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x583F7D0ull +#define NIC8_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x583F7D8ull +#define NIC8_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x583F7E0ull +#define NIC8_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x583F7E8ull +#define NIC8_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x583F7F0ull +#define NIC8_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x583F7F8ull +#define NIC8_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x583F800ull +#define NIC8_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x583F808ull +#define NIC8_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x583F810ull +#define NIC8_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC8_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x583F818ull +#define NIC8_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC8_QPC1_AXUSER_CONG_QUE_BASE 0x583FB80ull +#define NIC8_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC8_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC8_QPC1_AXUSER_RXWQE_BASE 0x583FBE0ull +#define NIC8_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC8_QPC1_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC8_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x583FC40ull +#define NIC8_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC8_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC8_QPC1_AXUSER_DB_FIFO_BASE 0x583FCA0ull +#define NIC8_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC8_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC8_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x583FD00ull +#define NIC8_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC8_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC8_QPC1_AXUSER_ERR_FIFO_BASE 0x583FD60ull +#define NIC8_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC8_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC8_QPC1_AXUSER_QPC_RESP_BASE 0x583FDC0ull +#define NIC8_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC8_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC8_QPC1_AXUSER_QPC_REQ_BASE 0x583FE20ull +#define NIC8_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC8_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC8_QPC1_SPECIAL_BASE 0x583FE80ull +#define NIC8_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_QPC1_SPECIAL_SECTION 0x8180 +#define mmNIC8_TMR_BASE 0x5848000ull +#define NIC8_TMR_MAX_OFFSET 0x1000 +#define NIC8_TMR_SECTION 0xD600 +#define mmNIC8_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5848D60ull +#define NIC8_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC8_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 +#define mmNIC8_TMR_AXUSER_TMR_FIFO_BASE 0x5848DC0ull +#define NIC8_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC8_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 +#define mmNIC8_TMR_AXUSER_TMR_FSM_BASE 0x5848E20ull +#define NIC8_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC8_TMR_AXUSER_TMR_FSM_SECTION 0x6000 +#define mmNIC8_TMR_SPECIAL_BASE 0x5848E80ull +#define NIC8_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_TMR_SPECIAL_SECTION 0x1800 +#define mmNIC8_RXB_CORE_BASE 0x5849000ull +#define NIC8_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC8_RXB_CORE_SECTION 0x6100 +#define mmNIC8_RXB_CORE_SCT_AWUSER_BASE 0x5849610ull +#define NIC8_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC8_RXB_CORE_SCT_AWUSER_SECTION 0x8700 +#define mmNIC8_RXB_CORE_SPECIAL_BASE 0x5849E80ull +#define NIC8_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_RXB_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC8_RXE0_BASE 0x584A000ull +#define NIC8_RXE0_MAX_OFFSET 0x1000 +#define NIC8_RXE0_SECTION 0x9000 +#define mmNIC8_RXE0_WQE_ARUSER_BASE 0x584A900ull +#define NIC8_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC8_RXE0_WQE_ARUSER_SECTION 0x5800 +#define mmNIC8_RXE0_SPECIAL_BASE 0x584AE80ull +#define NIC8_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_RXE0_SPECIAL_SECTION 0x1800 +#define mmNIC8_RXE1_BASE 0x584B000ull +#define NIC8_RXE1_MAX_OFFSET 0x1000 +#define NIC8_RXE1_SECTION 0x9000 +#define mmNIC8_RXE1_WQE_ARUSER_BASE 0x584B900ull +#define NIC8_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC8_RXE1_WQE_ARUSER_SECTION 0x5800 +#define mmNIC8_RXE1_SPECIAL_BASE 0x584BE80ull +#define NIC8_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_RXE1_SPECIAL_SECTION 0x1800 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ0_BASE 0x584C000ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ1_BASE 0x584C050ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ2_BASE 0x584C0A0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ3_BASE 0x584C0F0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ4_BASE 0x584C140ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ5_BASE 0x584C190ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ6_BASE 0x584C1E0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ7_BASE 0x584C230ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ8_BASE 0x584C280ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ9_BASE 0x584C2D0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ10_BASE 0x584C320ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ11_BASE 0x584C370ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ12_BASE 0x584C3C0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ13_BASE 0x584C410ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ14_BASE 0x584C460ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ15_BASE 0x584C4B0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ16_BASE 0x584C500ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ17_BASE 0x584C550ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ18_BASE 0x584C5A0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ19_BASE 0x584C5F0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ20_BASE 0x584C640ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ21_BASE 0x584C690ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ22_BASE 0x584C6E0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ23_BASE 0x584C730ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ24_BASE 0x584C780ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ25_BASE 0x584C7D0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ26_BASE 0x584C820ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ27_BASE 0x584C870ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ28_BASE 0x584C8C0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ29_BASE 0x584C910ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ30_BASE 0x584C960ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ31_BASE 0x584C9B0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC8_RXE0_AXUSER_SPECIAL_BASE 0x584CE80ull +#define NIC8_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_RXE0_AXUSER_SPECIAL_SECTION 0x1800 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ0_BASE 0x584D000ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ1_BASE 0x584D050ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ2_BASE 0x584D0A0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ3_BASE 0x584D0F0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ4_BASE 0x584D140ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ5_BASE 0x584D190ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ6_BASE 0x584D1E0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ7_BASE 0x584D230ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ8_BASE 0x584D280ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ9_BASE 0x584D2D0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ10_BASE 0x584D320ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ11_BASE 0x584D370ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ12_BASE 0x584D3C0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ13_BASE 0x584D410ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ14_BASE 0x584D460ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ15_BASE 0x584D4B0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ16_BASE 0x584D500ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ17_BASE 0x584D550ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ18_BASE 0x584D5A0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ19_BASE 0x584D5F0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ20_BASE 0x584D640ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ21_BASE 0x584D690ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ22_BASE 0x584D6E0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ23_BASE 0x584D730ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ24_BASE 0x584D780ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ25_BASE 0x584D7D0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ26_BASE 0x584D820ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ27_BASE 0x584D870ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ28_BASE 0x584D8C0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ29_BASE 0x584D910ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ30_BASE 0x584D960ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ31_BASE 0x584D9B0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC8_RXE1_AXUSER_SPECIAL_BASE 0x584DE80ull +#define NIC8_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_RXE1_AXUSER_SPECIAL_SECTION 0x2180 +#define mmNIC8_TXS0_BASE 0x5850000ull +#define NIC8_TXS0_MAX_OFFSET 0x1000 +#define NIC8_TXS0_SECTION 0xE800 +#define mmNIC8_TXS0_SPECIAL_BASE 0x5850E80ull +#define NIC8_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_TXS0_SPECIAL_SECTION 0x1800 +#define mmNIC8_TXS1_BASE 0x5851000ull +#define NIC8_TXS1_MAX_OFFSET 0x1000 +#define NIC8_TXS1_SECTION 0xE800 +#define mmNIC8_TXS1_SPECIAL_BASE 0x5851E80ull +#define NIC8_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_TXS1_SPECIAL_SECTION 0x1800 +#define mmNIC8_TXE0_BASE 0x5852000ull +#define NIC8_TXE0_MAX_OFFSET 0x1000 +#define NIC8_TXE0_SECTION 0xE800 +#define mmNIC8_TXE0_SPECIAL_BASE 0x5852E80ull +#define NIC8_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_TXE0_SPECIAL_SECTION 0x1800 +#define mmNIC8_TXE1_BASE 0x5853000ull +#define NIC8_TXE1_MAX_OFFSET 0x1000 +#define NIC8_TXE1_SECTION 0xE800 +#define mmNIC8_TXE1_SPECIAL_BASE 0x5853E80ull +#define NIC8_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_TXE1_SPECIAL_SECTION 0x1800 +#define mmNIC8_TXB_BASE 0x5854000ull +#define NIC8_TXB_MAX_OFFSET 0x1000 +#define NIC8_TXB_SECTION 0xE800 +#define mmNIC8_TXB_SPECIAL_BASE 0x5854E80ull +#define NIC8_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_TXB_SPECIAL_SECTION 0x1800 +#define mmNIC8_MSTR_IF_RR_SHRD_HBW_BASE 0x5855000ull +#define NIC8_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC8_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmNIC8_MSTR_IF_RR_PRVT_HBW_BASE 0x5855200ull +#define NIC8_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC8_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmNIC8_MSTR_IF_RR_SHRD_LBW_BASE 0x5855400ull +#define NIC8_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC8_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmNIC8_MSTR_IF_RR_PRVT_LBW_BASE 0x5855600ull +#define NIC8_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC8_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmNIC8_MSTR_IF_E2E_CRDT_BASE 0x5855800ull +#define NIC8_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC8_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmNIC8_MSTR_IF_AXUSER_BASE 0x5855A80ull +#define NIC8_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC8_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmNIC8_MSTR_IF_DBG_HBW_BASE 0x5855B00ull +#define NIC8_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC8_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmNIC8_MSTR_IF_DBG_LBW_BASE 0x5855B80ull +#define NIC8_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC8_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmNIC8_MSTR_IF_CORE_HBW_BASE 0x5855C00ull +#define NIC8_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC8_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmNIC8_MSTR_IF_CORE_LBW_BASE 0x5855D80ull +#define NIC8_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC8_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmNIC8_MSTR_IF_SPECIAL_BASE 0x5855E80ull +#define NIC8_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmNIC8_TX_AXUSER_BASE 0x5856000ull +#define NIC8_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC8_TX_AXUSER_SECTION 0x2000 +#define mmNIC8_SERDES0_BASE 0x5858000ull +#define NIC8_SERDES0_MAX_OFFSET 0x3E40 +#define NIC8_SERDES0_SECTION 0x4000 +#define mmNIC8_SERDES1_BASE 0x585C000ull +#define NIC8_SERDES1_MAX_OFFSET 0x3E40 +#define NIC8_SERDES1_SECTION 0x4000 +#define mmNIC8_PHY_BASE 0x5860000ull +#define NIC8_PHY_MAX_OFFSET 0x1000 +#define NIC8_PHY_SECTION 0xE800 +#define mmNIC8_PHY_SPECIAL_BASE 0x5860E80ull +#define NIC8_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_PHY_SPECIAL_SECTION 0x7180 +#define mmPRT8_MAC_AUX_BASE 0x5868000ull +#define PRT8_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT8_MAC_AUX_SECTION 0xE800 +#define mmPRT8_MAC_AUX_SPECIAL_BASE 0x5868E80ull +#define PRT8_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT8_MAC_AUX_SPECIAL_SECTION 0x1800 +#define mmPRT8_MAC_CORE_BASE 0x5869000ull +#define PRT8_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT8_MAC_CORE_SECTION 0xE800 +#define mmPRT8_MAC_CORE_SPECIAL_BASE 0x5869E80ull +#define PRT8_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT8_MAC_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC8_MAC_RS_FEC_BASE 0x586A000ull +#define NIC8_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC8_MAC_RS_FEC_SECTION 0x1000 +#define mmNIC8_MAC_GLOB_STAT_CONTROL_REG_BASE 0x586B000ull +#define NIC8_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000 +#define NIC8_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000 +#define mmNIC8_MAC_GLOB_STAT_RX0_BASE 0x586B100ull +#define NIC8_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00 +#define NIC8_MAC_GLOB_STAT_RX0_SECTION 0x8C00 +#define mmNIC8_MAC_GLOB_STAT_RX1_BASE 0x586B18Cull +#define NIC8_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00 +#define NIC8_MAC_GLOB_STAT_RX1_SECTION 0x8C00 +#define mmNIC8_MAC_GLOB_STAT_RX2_BASE 0x586B218ull +#define NIC8_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00 +#define NIC8_MAC_GLOB_STAT_RX2_SECTION 0x8C00 +#define mmNIC8_MAC_GLOB_STAT_RX3_BASE 0x586B2A4ull +#define NIC8_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00 +#define NIC8_MAC_GLOB_STAT_RX3_SECTION 0x8C00 +#define mmNIC8_MAC_GLOB_STAT_TX0_BASE 0x586B330ull +#define NIC8_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800 +#define NIC8_MAC_GLOB_STAT_TX0_SECTION 0x6800 +#define mmNIC8_MAC_GLOB_STAT_TX1_BASE 0x586B398ull +#define NIC8_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800 +#define NIC8_MAC_GLOB_STAT_TX1_SECTION 0x6800 +#define mmNIC8_MAC_GLOB_STAT_TX2_BASE 0x586B400ull +#define NIC8_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800 +#define NIC8_MAC_GLOB_STAT_TX2_SECTION 0x6800 +#define mmNIC8_MAC_GLOB_STAT_TX3_BASE 0x586B468ull +#define NIC8_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800 +#define NIC8_MAC_GLOB_STAT_TX3_SECTION 0x3980 +#define mmNIC8_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x586B800ull +#define NIC8_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC8_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000 +#define mmNIC8_MAC_CH0_MAC_PCS_BASE 0x586C000ull +#define NIC8_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC8_MAC_CH0_MAC_PCS_SECTION 0x4000 +#define mmNIC8_MAC_CH0_MAC_128_BASE 0x586C400ull +#define NIC8_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC8_MAC_CH0_MAC_128_SECTION 0x4000 +#define mmNIC8_MAC_CH0_MAC_AN_BASE 0x586C800ull +#define NIC8_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC8_MAC_CH0_MAC_AN_SECTION 0x8000 +#define mmNIC8_MAC_CH1_MAC_PCS_BASE 0x586D000ull +#define NIC8_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC8_MAC_CH1_MAC_PCS_SECTION 0x4000 +#define mmNIC8_MAC_CH1_MAC_128_BASE 0x586D400ull +#define NIC8_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC8_MAC_CH1_MAC_128_SECTION 0x4000 +#define mmNIC8_MAC_CH1_MAC_AN_BASE 0x586D800ull +#define NIC8_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC8_MAC_CH1_MAC_AN_SECTION 0x8000 +#define mmNIC8_MAC_CH2_MAC_PCS_BASE 0x586E000ull +#define NIC8_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC8_MAC_CH2_MAC_PCS_SECTION 0x4000 +#define mmNIC8_MAC_CH2_MAC_128_BASE 0x586E400ull +#define NIC8_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC8_MAC_CH2_MAC_128_SECTION 0x4000 +#define mmNIC8_MAC_CH2_MAC_AN_BASE 0x586E800ull +#define NIC8_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC8_MAC_CH2_MAC_AN_SECTION 0x8000 +#define mmNIC8_MAC_CH3_MAC_PCS_BASE 0x586F000ull +#define NIC8_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC8_MAC_CH3_MAC_PCS_SECTION 0x4000 +#define mmNIC8_MAC_CH3_MAC_128_BASE 0x586F400ull +#define NIC8_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC8_MAC_CH3_MAC_128_SECTION 0x4000 +#define mmNIC8_MAC_CH3_MAC_AN_BASE 0x586F800ull +#define NIC8_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC8_MAC_CH3_MAC_AN_SECTION 0x10800 +#define mmNIC9_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5880000ull +#define NIC9_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5880080ull +#define NIC9_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5880100ull +#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5880180ull +#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_0_SPECIAL_BASE 0x5880E80ull +#define NIC9_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_0_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5881000ull +#define NIC9_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5881080ull +#define NIC9_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5881100ull +#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5881180ull +#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_1_SPECIAL_BASE 0x5881E80ull +#define NIC9_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_1_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5882000ull +#define NIC9_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5882080ull +#define NIC9_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5882100ull +#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5882180ull +#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_2_SPECIAL_BASE 0x5882E80ull +#define NIC9_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_2_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5883000ull +#define NIC9_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5883080ull +#define NIC9_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5883100ull +#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5883180ull +#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_3_SPECIAL_BASE 0x5883E80ull +#define NIC9_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_3_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5884000ull +#define NIC9_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5884080ull +#define NIC9_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5884100ull +#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5884180ull +#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_4_SPECIAL_BASE 0x5884E80ull +#define NIC9_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_4_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5885000ull +#define NIC9_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5885080ull +#define NIC9_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5885100ull +#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5885180ull +#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_5_SPECIAL_BASE 0x5885E80ull +#define NIC9_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_5_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5886000ull +#define NIC9_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5886080ull +#define NIC9_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5886100ull +#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5886180ull +#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_6_SPECIAL_BASE 0x5886E80ull +#define NIC9_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_6_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5887000ull +#define NIC9_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5887080ull +#define NIC9_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5887100ull +#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5887180ull +#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_7_SPECIAL_BASE 0x5887E80ull +#define NIC9_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_7_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5888000ull +#define NIC9_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5888080ull +#define NIC9_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5888100ull +#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5888180ull +#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_8_SPECIAL_BASE 0x5888E80ull +#define NIC9_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_8_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5889000ull +#define NIC9_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5889080ull +#define NIC9_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5889100ull +#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5889180ull +#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_9_SPECIAL_BASE 0x5889E80ull +#define NIC9_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_9_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_10_UNSECURE_DOORBELL0_BASE 0x588A000ull +#define NIC9_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_10_UNSECURE_DOORBELL1_BASE 0x588A080ull +#define NIC9_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x588A100ull +#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x588A180ull +#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_10_SPECIAL_BASE 0x588AE80ull +#define NIC9_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_10_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_11_UNSECURE_DOORBELL0_BASE 0x588B000ull +#define NIC9_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_11_UNSECURE_DOORBELL1_BASE 0x588B080ull +#define NIC9_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x588B100ull +#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x588B180ull +#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_11_SPECIAL_BASE 0x588BE80ull +#define NIC9_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_11_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_12_UNSECURE_DOORBELL0_BASE 0x588C000ull +#define NIC9_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_12_UNSECURE_DOORBELL1_BASE 0x588C080ull +#define NIC9_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x588C100ull +#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x588C180ull +#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_12_SPECIAL_BASE 0x588CE80ull +#define NIC9_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_12_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_13_UNSECURE_DOORBELL0_BASE 0x588D000ull +#define NIC9_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_13_UNSECURE_DOORBELL1_BASE 0x588D080ull +#define NIC9_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x588D100ull +#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x588D180ull +#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_13_SPECIAL_BASE 0x588DE80ull +#define NIC9_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_13_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR0_14_UNSECURE_DOORBELL0_BASE 0x588E000ull +#define NIC9_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR0_14_UNSECURE_DOORBELL1_BASE 0x588E080ull +#define NIC9_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x588E100ull +#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x588E180ull +#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR0_14_SPECIAL_BASE 0x588EE80ull +#define NIC9_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_14_SPECIAL_SECTION 0x1180 +#define mmNIC9_QM_DCCM0_BASE 0x5890000ull +#define NIC9_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC9_QM_DCCM0_SECTION 0x8000 +#define mmNIC9_QM_ARC_AUX0_BASE 0x5898000ull +#define NIC9_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC9_QM_ARC_AUX0_SECTION 0xE800 +#define mmNIC9_QM_ARC_AUX0_SPECIAL_BASE 0x5898E80ull +#define NIC9_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 +#define mmNIC9_QM0_BASE 0x589A000ull +#define NIC9_QM0_MAX_OFFSET 0x1000 +#define NIC9_QM0_SECTION 0x9000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x589A900ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x589A908ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x589A910ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x589A918ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x589A920ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x589A928ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x589A930ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x589A938ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x589A940ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x589A948ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x589A950ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x589A958ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x589A960ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x589A968ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x589A970ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x589A978ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC9_QM0_AXUSER_SECURED_BASE 0x589AB00ull +#define NIC9_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC9_QM0_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC9_QM0_AXUSER_NONSECURED_BASE 0x589AB80ull +#define NIC9_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC9_QM0_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC9_QM0_DBG_HBW_BASE 0x589AC00ull +#define NIC9_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC9_QM0_DBG_HBW_SECTION 0x8000 +#define mmNIC9_QM0_DBG_LBW_BASE 0x589AC80ull +#define NIC9_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC9_QM0_DBG_LBW_SECTION 0x1000 +#define mmNIC9_QM0_CGM_BASE 0x589AD80ull +#define NIC9_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC9_QM0_CGM_SECTION 0x1000 +#define mmNIC9_QM0_SPECIAL_BASE 0x589AE80ull +#define NIC9_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_QM0_SPECIAL_SECTION 0x4180 +#define mmNIC9_QPC0_BASE 0x589F000ull +#define NIC9_QPC0_MAX_OFFSET 0x1000 +#define NIC9_QPC0_SECTION 0x7200 +#define mmNIC9_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x589F720ull +#define NIC9_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x589F728ull +#define NIC9_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x589F730ull +#define NIC9_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x589F738ull +#define NIC9_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x589F740ull +#define NIC9_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x589F748ull +#define NIC9_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x589F750ull +#define NIC9_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x589F758ull +#define NIC9_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x589F760ull +#define NIC9_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x589F768ull +#define NIC9_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x589F770ull +#define NIC9_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x589F778ull +#define NIC9_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x589F780ull +#define NIC9_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x589F788ull +#define NIC9_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x589F790ull +#define NIC9_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x589F798ull +#define NIC9_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x589F7A0ull +#define NIC9_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x589F7A8ull +#define NIC9_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x589F7B0ull +#define NIC9_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x589F7B8ull +#define NIC9_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x589F7C0ull +#define NIC9_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x589F7C8ull +#define NIC9_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x589F7D0ull +#define NIC9_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x589F7D8ull +#define NIC9_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x589F7E0ull +#define NIC9_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x589F7E8ull +#define NIC9_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x589F7F0ull +#define NIC9_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x589F7F8ull +#define NIC9_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x589F800ull +#define NIC9_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x589F808ull +#define NIC9_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x589F810ull +#define NIC9_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x589F818ull +#define NIC9_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC9_QPC0_AXUSER_CONG_QUE_BASE 0x589FB80ull +#define NIC9_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC9_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC9_QPC0_AXUSER_RXWQE_BASE 0x589FBE0ull +#define NIC9_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC9_QPC0_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC9_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x589FC40ull +#define NIC9_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC9_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC9_QPC0_AXUSER_DB_FIFO_BASE 0x589FCA0ull +#define NIC9_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC9_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC9_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x589FD00ull +#define NIC9_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC9_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC9_QPC0_AXUSER_ERR_FIFO_BASE 0x589FD60ull +#define NIC9_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC9_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC9_QPC0_AXUSER_QPC_RESP_BASE 0x589FDC0ull +#define NIC9_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC9_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC9_QPC0_AXUSER_QPC_REQ_BASE 0x589FE20ull +#define NIC9_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC9_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC9_QPC0_SPECIAL_BASE 0x589FE80ull +#define NIC9_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_QPC0_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_0_UNSECURE_DOORBELL0_BASE 0x58A0000ull +#define NIC9_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_0_UNSECURE_DOORBELL1_BASE 0x58A0080ull +#define NIC9_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x58A0100ull +#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x58A0180ull +#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_0_SPECIAL_BASE 0x58A0E80ull +#define NIC9_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_0_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_1_UNSECURE_DOORBELL0_BASE 0x58A1000ull +#define NIC9_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_1_UNSECURE_DOORBELL1_BASE 0x58A1080ull +#define NIC9_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x58A1100ull +#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x58A1180ull +#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_1_SPECIAL_BASE 0x58A1E80ull +#define NIC9_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_1_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_2_UNSECURE_DOORBELL0_BASE 0x58A2000ull +#define NIC9_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_2_UNSECURE_DOORBELL1_BASE 0x58A2080ull +#define NIC9_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x58A2100ull +#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x58A2180ull +#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_2_SPECIAL_BASE 0x58A2E80ull +#define NIC9_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_2_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_3_UNSECURE_DOORBELL0_BASE 0x58A3000ull +#define NIC9_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_3_UNSECURE_DOORBELL1_BASE 0x58A3080ull +#define NIC9_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x58A3100ull +#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x58A3180ull +#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_3_SPECIAL_BASE 0x58A3E80ull +#define NIC9_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_3_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_4_UNSECURE_DOORBELL0_BASE 0x58A4000ull +#define NIC9_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_4_UNSECURE_DOORBELL1_BASE 0x58A4080ull +#define NIC9_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x58A4100ull +#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x58A4180ull +#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_4_SPECIAL_BASE 0x58A4E80ull +#define NIC9_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_4_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_5_UNSECURE_DOORBELL0_BASE 0x58A5000ull +#define NIC9_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_5_UNSECURE_DOORBELL1_BASE 0x58A5080ull +#define NIC9_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x58A5100ull +#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x58A5180ull +#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_5_SPECIAL_BASE 0x58A5E80ull +#define NIC9_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_5_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_6_UNSECURE_DOORBELL0_BASE 0x58A6000ull +#define NIC9_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_6_UNSECURE_DOORBELL1_BASE 0x58A6080ull +#define NIC9_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x58A6100ull +#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x58A6180ull +#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_6_SPECIAL_BASE 0x58A6E80ull +#define NIC9_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_6_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_7_UNSECURE_DOORBELL0_BASE 0x58A7000ull +#define NIC9_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_7_UNSECURE_DOORBELL1_BASE 0x58A7080ull +#define NIC9_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x58A7100ull +#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x58A7180ull +#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_7_SPECIAL_BASE 0x58A7E80ull +#define NIC9_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_7_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_8_UNSECURE_DOORBELL0_BASE 0x58A8000ull +#define NIC9_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_8_UNSECURE_DOORBELL1_BASE 0x58A8080ull +#define NIC9_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x58A8100ull +#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x58A8180ull +#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_8_SPECIAL_BASE 0x58A8E80ull +#define NIC9_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_8_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_9_UNSECURE_DOORBELL0_BASE 0x58A9000ull +#define NIC9_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_9_UNSECURE_DOORBELL1_BASE 0x58A9080ull +#define NIC9_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x58A9100ull +#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x58A9180ull +#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_9_SPECIAL_BASE 0x58A9E80ull +#define NIC9_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_9_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_10_UNSECURE_DOORBELL0_BASE 0x58AA000ull +#define NIC9_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_10_UNSECURE_DOORBELL1_BASE 0x58AA080ull +#define NIC9_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x58AA100ull +#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x58AA180ull +#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_10_SPECIAL_BASE 0x58AAE80ull +#define NIC9_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_10_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_11_UNSECURE_DOORBELL0_BASE 0x58AB000ull +#define NIC9_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_11_UNSECURE_DOORBELL1_BASE 0x58AB080ull +#define NIC9_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x58AB100ull +#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x58AB180ull +#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_11_SPECIAL_BASE 0x58ABE80ull +#define NIC9_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_11_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_12_UNSECURE_DOORBELL0_BASE 0x58AC000ull +#define NIC9_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_12_UNSECURE_DOORBELL1_BASE 0x58AC080ull +#define NIC9_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x58AC100ull +#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x58AC180ull +#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_12_SPECIAL_BASE 0x58ACE80ull +#define NIC9_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_12_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_13_UNSECURE_DOORBELL0_BASE 0x58AD000ull +#define NIC9_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_13_UNSECURE_DOORBELL1_BASE 0x58AD080ull +#define NIC9_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x58AD100ull +#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x58AD180ull +#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_13_SPECIAL_BASE 0x58ADE80ull +#define NIC9_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_13_SPECIAL_SECTION 0x1800 +#define mmNIC9_UMR1_14_UNSECURE_DOORBELL0_BASE 0x58AE000ull +#define NIC9_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC9_UMR1_14_UNSECURE_DOORBELL1_BASE 0x58AE080ull +#define NIC9_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC9_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x58AE100ull +#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC9_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x58AE180ull +#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC9_UMR1_14_SPECIAL_BASE 0x58AEE80ull +#define NIC9_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_14_SPECIAL_SECTION 0x1180 +#define mmNIC9_QM_DCCM1_BASE 0x58B0000ull +#define NIC9_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC9_QM_DCCM1_SECTION 0x8000 +#define mmNIC9_QM_ARC_AUX1_BASE 0x58B8000ull +#define NIC9_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC9_QM_ARC_AUX1_SECTION 0xE800 +#define mmNIC9_QM_ARC_AUX1_SPECIAL_BASE 0x58B8E80ull +#define NIC9_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 +#define mmNIC9_QM1_BASE 0x58BA000ull +#define NIC9_QM1_MAX_OFFSET 0x1000 +#define NIC9_QM1_SECTION 0x9000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x58BA900ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x58BA908ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x58BA910ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x58BA918ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x58BA920ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x58BA928ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x58BA930ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x58BA938ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x58BA940ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x58BA948ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x58BA950ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x58BA958ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x58BA960ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x58BA968ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x58BA970ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x58BA978ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC9_QM1_AXUSER_SECURED_BASE 0x58BAB00ull +#define NIC9_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC9_QM1_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC9_QM1_AXUSER_NONSECURED_BASE 0x58BAB80ull +#define NIC9_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC9_QM1_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC9_QM1_DBG_HBW_BASE 0x58BAC00ull +#define NIC9_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC9_QM1_DBG_HBW_SECTION 0x8000 +#define mmNIC9_QM1_DBG_LBW_BASE 0x58BAC80ull +#define NIC9_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC9_QM1_DBG_LBW_SECTION 0x1000 +#define mmNIC9_QM1_CGM_BASE 0x58BAD80ull +#define NIC9_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC9_QM1_CGM_SECTION 0x1000 +#define mmNIC9_QM1_SPECIAL_BASE 0x58BAE80ull +#define NIC9_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_QM1_SPECIAL_SECTION 0x4180 +#define mmNIC9_QPC1_BASE 0x58BF000ull +#define NIC9_QPC1_MAX_OFFSET 0x1000 +#define NIC9_QPC1_SECTION 0x7200 +#define mmNIC9_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x58BF720ull +#define NIC9_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x58BF728ull +#define NIC9_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x58BF730ull +#define NIC9_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x58BF738ull +#define NIC9_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x58BF740ull +#define NIC9_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x58BF748ull +#define NIC9_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x58BF750ull +#define NIC9_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x58BF758ull +#define NIC9_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x58BF760ull +#define NIC9_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x58BF768ull +#define NIC9_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x58BF770ull +#define NIC9_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x58BF778ull +#define NIC9_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x58BF780ull +#define NIC9_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x58BF788ull +#define NIC9_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x58BF790ull +#define NIC9_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x58BF798ull +#define NIC9_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x58BF7A0ull +#define NIC9_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x58BF7A8ull +#define NIC9_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x58BF7B0ull +#define NIC9_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x58BF7B8ull +#define NIC9_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x58BF7C0ull +#define NIC9_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x58BF7C8ull +#define NIC9_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x58BF7D0ull +#define NIC9_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x58BF7D8ull +#define NIC9_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x58BF7E0ull +#define NIC9_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x58BF7E8ull +#define NIC9_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x58BF7F0ull +#define NIC9_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x58BF7F8ull +#define NIC9_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x58BF800ull +#define NIC9_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x58BF808ull +#define NIC9_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x58BF810ull +#define NIC9_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC9_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x58BF818ull +#define NIC9_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC9_QPC1_AXUSER_CONG_QUE_BASE 0x58BFB80ull +#define NIC9_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC9_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC9_QPC1_AXUSER_RXWQE_BASE 0x58BFBE0ull +#define NIC9_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC9_QPC1_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC9_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x58BFC40ull +#define NIC9_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC9_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC9_QPC1_AXUSER_DB_FIFO_BASE 0x58BFCA0ull +#define NIC9_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC9_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC9_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x58BFD00ull +#define NIC9_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC9_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC9_QPC1_AXUSER_ERR_FIFO_BASE 0x58BFD60ull +#define NIC9_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC9_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC9_QPC1_AXUSER_QPC_RESP_BASE 0x58BFDC0ull +#define NIC9_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC9_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC9_QPC1_AXUSER_QPC_REQ_BASE 0x58BFE20ull +#define NIC9_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC9_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC9_QPC1_SPECIAL_BASE 0x58BFE80ull +#define NIC9_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_QPC1_SPECIAL_SECTION 0x8180 +#define mmNIC9_TMR_BASE 0x58C8000ull +#define NIC9_TMR_MAX_OFFSET 0x1000 +#define NIC9_TMR_SECTION 0xD600 +#define mmNIC9_TMR_AXUSER_TMR_FREE_LIST_BASE 0x58C8D60ull +#define NIC9_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC9_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 +#define mmNIC9_TMR_AXUSER_TMR_FIFO_BASE 0x58C8DC0ull +#define NIC9_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC9_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 +#define mmNIC9_TMR_AXUSER_TMR_FSM_BASE 0x58C8E20ull +#define NIC9_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC9_TMR_AXUSER_TMR_FSM_SECTION 0x6000 +#define mmNIC9_TMR_SPECIAL_BASE 0x58C8E80ull +#define NIC9_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_TMR_SPECIAL_SECTION 0x1800 +#define mmNIC9_RXB_CORE_BASE 0x58C9000ull +#define NIC9_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC9_RXB_CORE_SECTION 0x6100 +#define mmNIC9_RXB_CORE_SCT_AWUSER_BASE 0x58C9610ull +#define NIC9_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC9_RXB_CORE_SCT_AWUSER_SECTION 0x8700 +#define mmNIC9_RXB_CORE_SPECIAL_BASE 0x58C9E80ull +#define NIC9_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_RXB_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC9_RXE0_BASE 0x58CA000ull +#define NIC9_RXE0_MAX_OFFSET 0x1000 +#define NIC9_RXE0_SECTION 0x9000 +#define mmNIC9_RXE0_WQE_ARUSER_BASE 0x58CA900ull +#define NIC9_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC9_RXE0_WQE_ARUSER_SECTION 0x5800 +#define mmNIC9_RXE0_SPECIAL_BASE 0x58CAE80ull +#define NIC9_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_RXE0_SPECIAL_SECTION 0x1800 +#define mmNIC9_RXE1_BASE 0x58CB000ull +#define NIC9_RXE1_MAX_OFFSET 0x1000 +#define NIC9_RXE1_SECTION 0x9000 +#define mmNIC9_RXE1_WQE_ARUSER_BASE 0x58CB900ull +#define NIC9_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC9_RXE1_WQE_ARUSER_SECTION 0x5800 +#define mmNIC9_RXE1_SPECIAL_BASE 0x58CBE80ull +#define NIC9_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_RXE1_SPECIAL_SECTION 0x1800 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ0_BASE 0x58CC000ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ1_BASE 0x58CC050ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ2_BASE 0x58CC0A0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ3_BASE 0x58CC0F0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ4_BASE 0x58CC140ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ5_BASE 0x58CC190ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ6_BASE 0x58CC1E0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ7_BASE 0x58CC230ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ8_BASE 0x58CC280ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ9_BASE 0x58CC2D0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ10_BASE 0x58CC320ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ11_BASE 0x58CC370ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ12_BASE 0x58CC3C0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ13_BASE 0x58CC410ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ14_BASE 0x58CC460ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ15_BASE 0x58CC4B0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ16_BASE 0x58CC500ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ17_BASE 0x58CC550ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ18_BASE 0x58CC5A0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ19_BASE 0x58CC5F0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ20_BASE 0x58CC640ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ21_BASE 0x58CC690ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ22_BASE 0x58CC6E0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ23_BASE 0x58CC730ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ24_BASE 0x58CC780ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ25_BASE 0x58CC7D0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ26_BASE 0x58CC820ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ27_BASE 0x58CC870ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ28_BASE 0x58CC8C0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ29_BASE 0x58CC910ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ30_BASE 0x58CC960ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ31_BASE 0x58CC9B0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC9_RXE0_AXUSER_SPECIAL_BASE 0x58CCE80ull +#define NIC9_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_RXE0_AXUSER_SPECIAL_SECTION 0x1800 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ0_BASE 0x58CD000ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ1_BASE 0x58CD050ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ2_BASE 0x58CD0A0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ3_BASE 0x58CD0F0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ4_BASE 0x58CD140ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ5_BASE 0x58CD190ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ6_BASE 0x58CD1E0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ7_BASE 0x58CD230ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ8_BASE 0x58CD280ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ9_BASE 0x58CD2D0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ10_BASE 0x58CD320ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ11_BASE 0x58CD370ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ12_BASE 0x58CD3C0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ13_BASE 0x58CD410ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ14_BASE 0x58CD460ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ15_BASE 0x58CD4B0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ16_BASE 0x58CD500ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ17_BASE 0x58CD550ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ18_BASE 0x58CD5A0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ19_BASE 0x58CD5F0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ20_BASE 0x58CD640ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ21_BASE 0x58CD690ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ22_BASE 0x58CD6E0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ23_BASE 0x58CD730ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ24_BASE 0x58CD780ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ25_BASE 0x58CD7D0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ26_BASE 0x58CD820ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ27_BASE 0x58CD870ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ28_BASE 0x58CD8C0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ29_BASE 0x58CD910ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ30_BASE 0x58CD960ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ31_BASE 0x58CD9B0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC9_RXE1_AXUSER_SPECIAL_BASE 0x58CDE80ull +#define NIC9_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_RXE1_AXUSER_SPECIAL_SECTION 0x2180 +#define mmNIC9_TXS0_BASE 0x58D0000ull +#define NIC9_TXS0_MAX_OFFSET 0x1000 +#define NIC9_TXS0_SECTION 0xE800 +#define mmNIC9_TXS0_SPECIAL_BASE 0x58D0E80ull +#define NIC9_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_TXS0_SPECIAL_SECTION 0x1800 +#define mmNIC9_TXS1_BASE 0x58D1000ull +#define NIC9_TXS1_MAX_OFFSET 0x1000 +#define NIC9_TXS1_SECTION 0xE800 +#define mmNIC9_TXS1_SPECIAL_BASE 0x58D1E80ull +#define NIC9_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_TXS1_SPECIAL_SECTION 0x1800 +#define mmNIC9_TXE0_BASE 0x58D2000ull +#define NIC9_TXE0_MAX_OFFSET 0x1000 +#define NIC9_TXE0_SECTION 0xE800 +#define mmNIC9_TXE0_SPECIAL_BASE 0x58D2E80ull +#define NIC9_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_TXE0_SPECIAL_SECTION 0x1800 +#define mmNIC9_TXE1_BASE 0x58D3000ull +#define NIC9_TXE1_MAX_OFFSET 0x1000 +#define NIC9_TXE1_SECTION 0xE800 +#define mmNIC9_TXE1_SPECIAL_BASE 0x58D3E80ull +#define NIC9_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_TXE1_SPECIAL_SECTION 0x1800 +#define mmNIC9_TXB_BASE 0x58D4000ull +#define NIC9_TXB_MAX_OFFSET 0x1000 +#define NIC9_TXB_SECTION 0xE800 +#define mmNIC9_TXB_SPECIAL_BASE 0x58D4E80ull +#define NIC9_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_TXB_SPECIAL_SECTION 0x1800 +#define mmNIC9_MSTR_IF_RR_SHRD_HBW_BASE 0x58D5000ull +#define NIC9_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC9_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmNIC9_MSTR_IF_RR_PRVT_HBW_BASE 0x58D5200ull +#define NIC9_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC9_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmNIC9_MSTR_IF_RR_SHRD_LBW_BASE 0x58D5400ull +#define NIC9_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC9_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmNIC9_MSTR_IF_RR_PRVT_LBW_BASE 0x58D5600ull +#define NIC9_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC9_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmNIC9_MSTR_IF_E2E_CRDT_BASE 0x58D5800ull +#define NIC9_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC9_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmNIC9_MSTR_IF_AXUSER_BASE 0x58D5A80ull +#define NIC9_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC9_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmNIC9_MSTR_IF_DBG_HBW_BASE 0x58D5B00ull +#define NIC9_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC9_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmNIC9_MSTR_IF_DBG_LBW_BASE 0x58D5B80ull +#define NIC9_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC9_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmNIC9_MSTR_IF_CORE_HBW_BASE 0x58D5C00ull +#define NIC9_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC9_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmNIC9_MSTR_IF_CORE_LBW_BASE 0x58D5D80ull +#define NIC9_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC9_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmNIC9_MSTR_IF_SPECIAL_BASE 0x58D5E80ull +#define NIC9_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmNIC9_TX_AXUSER_BASE 0x58D6000ull +#define NIC9_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC9_TX_AXUSER_SECTION 0x2000 +#define mmNIC9_SERDES0_BASE 0x58D8000ull +#define NIC9_SERDES0_MAX_OFFSET 0x3E40 +#define NIC9_SERDES0_SECTION 0x4000 +#define mmNIC9_SERDES1_BASE 0x58DC000ull +#define NIC9_SERDES1_MAX_OFFSET 0x3E40 +#define NIC9_SERDES1_SECTION 0x4000 +#define mmNIC9_PHY_BASE 0x58E0000ull +#define NIC9_PHY_MAX_OFFSET 0x1000 +#define NIC9_PHY_SECTION 0xE800 +#define mmNIC9_PHY_SPECIAL_BASE 0x58E0E80ull +#define NIC9_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_PHY_SPECIAL_SECTION 0x7180 +#define mmPRT9_MAC_AUX_BASE 0x58E8000ull +#define PRT9_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT9_MAC_AUX_SECTION 0xE800 +#define mmPRT9_MAC_AUX_SPECIAL_BASE 0x58E8E80ull +#define PRT9_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT9_MAC_AUX_SPECIAL_SECTION 0x1800 +#define mmPRT9_MAC_CORE_BASE 0x58E9000ull +#define PRT9_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT9_MAC_CORE_SECTION 0xE800 +#define mmPRT9_MAC_CORE_SPECIAL_BASE 0x58E9E80ull +#define PRT9_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT9_MAC_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC9_MAC_RS_FEC_BASE 0x58EA000ull +#define NIC9_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC9_MAC_RS_FEC_SECTION 0x1000 +#define mmNIC9_MAC_GLOB_STAT_CONTROL_REG_BASE 0x58EB000ull +#define NIC9_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000 +#define NIC9_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000 +#define mmNIC9_MAC_GLOB_STAT_RX0_BASE 0x58EB100ull +#define NIC9_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00 +#define NIC9_MAC_GLOB_STAT_RX0_SECTION 0x8C00 +#define mmNIC9_MAC_GLOB_STAT_RX1_BASE 0x58EB18Cull +#define NIC9_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00 +#define NIC9_MAC_GLOB_STAT_RX1_SECTION 0x8C00 +#define mmNIC9_MAC_GLOB_STAT_RX2_BASE 0x58EB218ull +#define NIC9_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00 +#define NIC9_MAC_GLOB_STAT_RX2_SECTION 0x8C00 +#define mmNIC9_MAC_GLOB_STAT_RX3_BASE 0x58EB2A4ull +#define NIC9_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00 +#define NIC9_MAC_GLOB_STAT_RX3_SECTION 0x8C00 +#define mmNIC9_MAC_GLOB_STAT_TX0_BASE 0x58EB330ull +#define NIC9_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800 +#define NIC9_MAC_GLOB_STAT_TX0_SECTION 0x6800 +#define mmNIC9_MAC_GLOB_STAT_TX1_BASE 0x58EB398ull +#define NIC9_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800 +#define NIC9_MAC_GLOB_STAT_TX1_SECTION 0x6800 +#define mmNIC9_MAC_GLOB_STAT_TX2_BASE 0x58EB400ull +#define NIC9_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800 +#define NIC9_MAC_GLOB_STAT_TX2_SECTION 0x6800 +#define mmNIC9_MAC_GLOB_STAT_TX3_BASE 0x58EB468ull +#define NIC9_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800 +#define NIC9_MAC_GLOB_STAT_TX3_SECTION 0x3980 +#define mmNIC9_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x58EB800ull +#define NIC9_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC9_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000 +#define mmNIC9_MAC_CH0_MAC_PCS_BASE 0x58EC000ull +#define NIC9_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC9_MAC_CH0_MAC_PCS_SECTION 0x4000 +#define mmNIC9_MAC_CH0_MAC_128_BASE 0x58EC400ull +#define NIC9_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC9_MAC_CH0_MAC_128_SECTION 0x4000 +#define mmNIC9_MAC_CH0_MAC_AN_BASE 0x58EC800ull +#define NIC9_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC9_MAC_CH0_MAC_AN_SECTION 0x8000 +#define mmNIC9_MAC_CH1_MAC_PCS_BASE 0x58ED000ull +#define NIC9_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC9_MAC_CH1_MAC_PCS_SECTION 0x4000 +#define mmNIC9_MAC_CH1_MAC_128_BASE 0x58ED400ull +#define NIC9_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC9_MAC_CH1_MAC_128_SECTION 0x4000 +#define mmNIC9_MAC_CH1_MAC_AN_BASE 0x58ED800ull +#define NIC9_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC9_MAC_CH1_MAC_AN_SECTION 0x8000 +#define mmNIC9_MAC_CH2_MAC_PCS_BASE 0x58EE000ull +#define NIC9_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC9_MAC_CH2_MAC_PCS_SECTION 0x4000 +#define mmNIC9_MAC_CH2_MAC_128_BASE 0x58EE400ull +#define NIC9_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC9_MAC_CH2_MAC_128_SECTION 0x4000 +#define mmNIC9_MAC_CH2_MAC_AN_BASE 0x58EE800ull +#define NIC9_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC9_MAC_CH2_MAC_AN_SECTION 0x8000 +#define mmNIC9_MAC_CH3_MAC_PCS_BASE 0x58EF000ull +#define NIC9_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC9_MAC_CH3_MAC_PCS_SECTION 0x4000 +#define mmNIC9_MAC_CH3_MAC_128_BASE 0x58EF400ull +#define NIC9_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC9_MAC_CH3_MAC_128_SECTION 0x4000 +#define mmNIC9_MAC_CH3_MAC_AN_BASE 0x58EF800ull +#define NIC9_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC9_MAC_CH3_MAC_AN_SECTION 0x10800 +#define mmNIC10_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5900000ull +#define NIC10_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5900080ull +#define NIC10_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5900100ull +#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5900180ull +#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_0_SPECIAL_BASE 0x5900E80ull +#define NIC10_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_0_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5901000ull +#define NIC10_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5901080ull +#define NIC10_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5901100ull +#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5901180ull +#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_1_SPECIAL_BASE 0x5901E80ull +#define NIC10_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_1_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5902000ull +#define NIC10_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5902080ull +#define NIC10_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5902100ull +#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5902180ull +#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_2_SPECIAL_BASE 0x5902E80ull +#define NIC10_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_2_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5903000ull +#define NIC10_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5903080ull +#define NIC10_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5903100ull +#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5903180ull +#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_3_SPECIAL_BASE 0x5903E80ull +#define NIC10_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_3_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5904000ull +#define NIC10_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5904080ull +#define NIC10_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5904100ull +#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5904180ull +#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_4_SPECIAL_BASE 0x5904E80ull +#define NIC10_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_4_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5905000ull +#define NIC10_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5905080ull +#define NIC10_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5905100ull +#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5905180ull +#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_5_SPECIAL_BASE 0x5905E80ull +#define NIC10_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_5_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5906000ull +#define NIC10_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5906080ull +#define NIC10_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5906100ull +#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5906180ull +#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_6_SPECIAL_BASE 0x5906E80ull +#define NIC10_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_6_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5907000ull +#define NIC10_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5907080ull +#define NIC10_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5907100ull +#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5907180ull +#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_7_SPECIAL_BASE 0x5907E80ull +#define NIC10_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_7_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5908000ull +#define NIC10_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5908080ull +#define NIC10_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5908100ull +#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5908180ull +#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_8_SPECIAL_BASE 0x5908E80ull +#define NIC10_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_8_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5909000ull +#define NIC10_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5909080ull +#define NIC10_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5909100ull +#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5909180ull +#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_9_SPECIAL_BASE 0x5909E80ull +#define NIC10_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_9_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_10_UNSECURE_DOORBELL0_BASE 0x590A000ull +#define NIC10_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_10_UNSECURE_DOORBELL1_BASE 0x590A080ull +#define NIC10_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x590A100ull +#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x590A180ull +#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_10_SPECIAL_BASE 0x590AE80ull +#define NIC10_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_10_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_11_UNSECURE_DOORBELL0_BASE 0x590B000ull +#define NIC10_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_11_UNSECURE_DOORBELL1_BASE 0x590B080ull +#define NIC10_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x590B100ull +#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x590B180ull +#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_11_SPECIAL_BASE 0x590BE80ull +#define NIC10_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_11_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_12_UNSECURE_DOORBELL0_BASE 0x590C000ull +#define NIC10_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_12_UNSECURE_DOORBELL1_BASE 0x590C080ull +#define NIC10_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x590C100ull +#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x590C180ull +#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_12_SPECIAL_BASE 0x590CE80ull +#define NIC10_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_12_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_13_UNSECURE_DOORBELL0_BASE 0x590D000ull +#define NIC10_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_13_UNSECURE_DOORBELL1_BASE 0x590D080ull +#define NIC10_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x590D100ull +#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x590D180ull +#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_13_SPECIAL_BASE 0x590DE80ull +#define NIC10_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_13_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR0_14_UNSECURE_DOORBELL0_BASE 0x590E000ull +#define NIC10_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR0_14_UNSECURE_DOORBELL1_BASE 0x590E080ull +#define NIC10_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x590E100ull +#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x590E180ull +#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR0_14_SPECIAL_BASE 0x590EE80ull +#define NIC10_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_14_SPECIAL_SECTION 0x1180 +#define mmNIC10_QM_DCCM0_BASE 0x5910000ull +#define NIC10_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC10_QM_DCCM0_SECTION 0x8000 +#define mmNIC10_QM_ARC_AUX0_BASE 0x5918000ull +#define NIC10_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC10_QM_ARC_AUX0_SECTION 0xE800 +#define mmNIC10_QM_ARC_AUX0_SPECIAL_BASE 0x5918E80ull +#define NIC10_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 +#define mmNIC10_QM0_BASE 0x591A000ull +#define NIC10_QM0_MAX_OFFSET 0x1000 +#define NIC10_QM0_SECTION 0x9000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x591A900ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x591A908ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x591A910ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x591A918ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x591A920ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x591A928ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x591A930ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x591A938ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x591A940ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x591A948ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x591A950ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x591A958ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x591A960ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x591A968ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x591A970ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x591A978ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC10_QM0_AXUSER_SECURED_BASE 0x591AB00ull +#define NIC10_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC10_QM0_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC10_QM0_AXUSER_NONSECURED_BASE 0x591AB80ull +#define NIC10_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC10_QM0_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC10_QM0_DBG_HBW_BASE 0x591AC00ull +#define NIC10_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC10_QM0_DBG_HBW_SECTION 0x8000 +#define mmNIC10_QM0_DBG_LBW_BASE 0x591AC80ull +#define NIC10_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC10_QM0_DBG_LBW_SECTION 0x1000 +#define mmNIC10_QM0_CGM_BASE 0x591AD80ull +#define NIC10_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC10_QM0_CGM_SECTION 0x1000 +#define mmNIC10_QM0_SPECIAL_BASE 0x591AE80ull +#define NIC10_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_QM0_SPECIAL_SECTION 0x4180 +#define mmNIC10_QPC0_BASE 0x591F000ull +#define NIC10_QPC0_MAX_OFFSET 0x1000 +#define NIC10_QPC0_SECTION 0x7200 +#define mmNIC10_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x591F720ull +#define NIC10_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x591F728ull +#define NIC10_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x591F730ull +#define NIC10_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x591F738ull +#define NIC10_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x591F740ull +#define NIC10_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x591F748ull +#define NIC10_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x591F750ull +#define NIC10_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x591F758ull +#define NIC10_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x591F760ull +#define NIC10_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x591F768ull +#define NIC10_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x591F770ull +#define NIC10_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x591F778ull +#define NIC10_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x591F780ull +#define NIC10_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x591F788ull +#define NIC10_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x591F790ull +#define NIC10_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x591F798ull +#define NIC10_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x591F7A0ull +#define NIC10_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x591F7A8ull +#define NIC10_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x591F7B0ull +#define NIC10_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x591F7B8ull +#define NIC10_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x591F7C0ull +#define NIC10_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x591F7C8ull +#define NIC10_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x591F7D0ull +#define NIC10_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x591F7D8ull +#define NIC10_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x591F7E0ull +#define NIC10_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x591F7E8ull +#define NIC10_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x591F7F0ull +#define NIC10_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x591F7F8ull +#define NIC10_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x591F800ull +#define NIC10_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x591F808ull +#define NIC10_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x591F810ull +#define NIC10_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x591F818ull +#define NIC10_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC10_QPC0_AXUSER_CONG_QUE_BASE 0x591FB80ull +#define NIC10_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC10_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC10_QPC0_AXUSER_RXWQE_BASE 0x591FBE0ull +#define NIC10_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC10_QPC0_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC10_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x591FC40ull +#define NIC10_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC10_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC10_QPC0_AXUSER_DB_FIFO_BASE 0x591FCA0ull +#define NIC10_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC10_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC10_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x591FD00ull +#define NIC10_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC10_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC10_QPC0_AXUSER_ERR_FIFO_BASE 0x591FD60ull +#define NIC10_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC10_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC10_QPC0_AXUSER_QPC_RESP_BASE 0x591FDC0ull +#define NIC10_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC10_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC10_QPC0_AXUSER_QPC_REQ_BASE 0x591FE20ull +#define NIC10_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC10_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC10_QPC0_SPECIAL_BASE 0x591FE80ull +#define NIC10_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_QPC0_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5920000ull +#define NIC10_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5920080ull +#define NIC10_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5920100ull +#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5920180ull +#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_0_SPECIAL_BASE 0x5920E80ull +#define NIC10_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_0_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5921000ull +#define NIC10_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5921080ull +#define NIC10_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5921100ull +#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5921180ull +#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_1_SPECIAL_BASE 0x5921E80ull +#define NIC10_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_1_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5922000ull +#define NIC10_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5922080ull +#define NIC10_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5922100ull +#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5922180ull +#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_2_SPECIAL_BASE 0x5922E80ull +#define NIC10_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_2_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5923000ull +#define NIC10_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5923080ull +#define NIC10_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5923100ull +#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5923180ull +#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_3_SPECIAL_BASE 0x5923E80ull +#define NIC10_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_3_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5924000ull +#define NIC10_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5924080ull +#define NIC10_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5924100ull +#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5924180ull +#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_4_SPECIAL_BASE 0x5924E80ull +#define NIC10_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_4_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5925000ull +#define NIC10_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5925080ull +#define NIC10_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5925100ull +#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5925180ull +#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_5_SPECIAL_BASE 0x5925E80ull +#define NIC10_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_5_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5926000ull +#define NIC10_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5926080ull +#define NIC10_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5926100ull +#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5926180ull +#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_6_SPECIAL_BASE 0x5926E80ull +#define NIC10_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_6_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5927000ull +#define NIC10_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5927080ull +#define NIC10_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5927100ull +#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5927180ull +#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_7_SPECIAL_BASE 0x5927E80ull +#define NIC10_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_7_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5928000ull +#define NIC10_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5928080ull +#define NIC10_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5928100ull +#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5928180ull +#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_8_SPECIAL_BASE 0x5928E80ull +#define NIC10_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_8_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5929000ull +#define NIC10_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5929080ull +#define NIC10_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5929100ull +#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5929180ull +#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_9_SPECIAL_BASE 0x5929E80ull +#define NIC10_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_9_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_10_UNSECURE_DOORBELL0_BASE 0x592A000ull +#define NIC10_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_10_UNSECURE_DOORBELL1_BASE 0x592A080ull +#define NIC10_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x592A100ull +#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x592A180ull +#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_10_SPECIAL_BASE 0x592AE80ull +#define NIC10_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_10_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_11_UNSECURE_DOORBELL0_BASE 0x592B000ull +#define NIC10_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_11_UNSECURE_DOORBELL1_BASE 0x592B080ull +#define NIC10_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x592B100ull +#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x592B180ull +#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_11_SPECIAL_BASE 0x592BE80ull +#define NIC10_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_11_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_12_UNSECURE_DOORBELL0_BASE 0x592C000ull +#define NIC10_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_12_UNSECURE_DOORBELL1_BASE 0x592C080ull +#define NIC10_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x592C100ull +#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x592C180ull +#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_12_SPECIAL_BASE 0x592CE80ull +#define NIC10_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_12_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_13_UNSECURE_DOORBELL0_BASE 0x592D000ull +#define NIC10_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_13_UNSECURE_DOORBELL1_BASE 0x592D080ull +#define NIC10_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x592D100ull +#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x592D180ull +#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_13_SPECIAL_BASE 0x592DE80ull +#define NIC10_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_13_SPECIAL_SECTION 0x1800 +#define mmNIC10_UMR1_14_UNSECURE_DOORBELL0_BASE 0x592E000ull +#define NIC10_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC10_UMR1_14_UNSECURE_DOORBELL1_BASE 0x592E080ull +#define NIC10_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC10_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x592E100ull +#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC10_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x592E180ull +#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC10_UMR1_14_SPECIAL_BASE 0x592EE80ull +#define NIC10_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_14_SPECIAL_SECTION 0x1180 +#define mmNIC10_QM_DCCM1_BASE 0x5930000ull +#define NIC10_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC10_QM_DCCM1_SECTION 0x8000 +#define mmNIC10_QM_ARC_AUX1_BASE 0x5938000ull +#define NIC10_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC10_QM_ARC_AUX1_SECTION 0xE800 +#define mmNIC10_QM_ARC_AUX1_SPECIAL_BASE 0x5938E80ull +#define NIC10_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 +#define mmNIC10_QM1_BASE 0x593A000ull +#define NIC10_QM1_MAX_OFFSET 0x1000 +#define NIC10_QM1_SECTION 0x9000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x593A900ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x593A908ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x593A910ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x593A918ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x593A920ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x593A928ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x593A930ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x593A938ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x593A940ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x593A948ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x593A950ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x593A958ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x593A960ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x593A968ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x593A970ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x593A978ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC10_QM1_AXUSER_SECURED_BASE 0x593AB00ull +#define NIC10_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC10_QM1_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC10_QM1_AXUSER_NONSECURED_BASE 0x593AB80ull +#define NIC10_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC10_QM1_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC10_QM1_DBG_HBW_BASE 0x593AC00ull +#define NIC10_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC10_QM1_DBG_HBW_SECTION 0x8000 +#define mmNIC10_QM1_DBG_LBW_BASE 0x593AC80ull +#define NIC10_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC10_QM1_DBG_LBW_SECTION 0x1000 +#define mmNIC10_QM1_CGM_BASE 0x593AD80ull +#define NIC10_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC10_QM1_CGM_SECTION 0x1000 +#define mmNIC10_QM1_SPECIAL_BASE 0x593AE80ull +#define NIC10_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_QM1_SPECIAL_SECTION 0x4180 +#define mmNIC10_QPC1_BASE 0x593F000ull +#define NIC10_QPC1_MAX_OFFSET 0x1000 +#define NIC10_QPC1_SECTION 0x7200 +#define mmNIC10_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x593F720ull +#define NIC10_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x593F728ull +#define NIC10_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x593F730ull +#define NIC10_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x593F738ull +#define NIC10_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x593F740ull +#define NIC10_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x593F748ull +#define NIC10_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x593F750ull +#define NIC10_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x593F758ull +#define NIC10_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x593F760ull +#define NIC10_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x593F768ull +#define NIC10_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x593F770ull +#define NIC10_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x593F778ull +#define NIC10_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x593F780ull +#define NIC10_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x593F788ull +#define NIC10_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x593F790ull +#define NIC10_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x593F798ull +#define NIC10_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x593F7A0ull +#define NIC10_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x593F7A8ull +#define NIC10_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x593F7B0ull +#define NIC10_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x593F7B8ull +#define NIC10_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x593F7C0ull +#define NIC10_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x593F7C8ull +#define NIC10_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x593F7D0ull +#define NIC10_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x593F7D8ull +#define NIC10_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x593F7E0ull +#define NIC10_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x593F7E8ull +#define NIC10_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x593F7F0ull +#define NIC10_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x593F7F8ull +#define NIC10_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x593F800ull +#define NIC10_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x593F808ull +#define NIC10_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x593F810ull +#define NIC10_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC10_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x593F818ull +#define NIC10_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC10_QPC1_AXUSER_CONG_QUE_BASE 0x593FB80ull +#define NIC10_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC10_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC10_QPC1_AXUSER_RXWQE_BASE 0x593FBE0ull +#define NIC10_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC10_QPC1_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC10_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x593FC40ull +#define NIC10_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC10_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC10_QPC1_AXUSER_DB_FIFO_BASE 0x593FCA0ull +#define NIC10_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC10_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC10_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x593FD00ull +#define NIC10_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC10_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC10_QPC1_AXUSER_ERR_FIFO_BASE 0x593FD60ull +#define NIC10_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC10_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC10_QPC1_AXUSER_QPC_RESP_BASE 0x593FDC0ull +#define NIC10_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC10_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC10_QPC1_AXUSER_QPC_REQ_BASE 0x593FE20ull +#define NIC10_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC10_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC10_QPC1_SPECIAL_BASE 0x593FE80ull +#define NIC10_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_QPC1_SPECIAL_SECTION 0x8180 +#define mmNIC10_TMR_BASE 0x5948000ull +#define NIC10_TMR_MAX_OFFSET 0x1000 +#define NIC10_TMR_SECTION 0xD600 +#define mmNIC10_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5948D60ull +#define NIC10_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC10_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 +#define mmNIC10_TMR_AXUSER_TMR_FIFO_BASE 0x5948DC0ull +#define NIC10_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC10_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 +#define mmNIC10_TMR_AXUSER_TMR_FSM_BASE 0x5948E20ull +#define NIC10_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC10_TMR_AXUSER_TMR_FSM_SECTION 0x6000 +#define mmNIC10_TMR_SPECIAL_BASE 0x5948E80ull +#define NIC10_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_TMR_SPECIAL_SECTION 0x1800 +#define mmNIC10_RXB_CORE_BASE 0x5949000ull +#define NIC10_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC10_RXB_CORE_SECTION 0x6100 +#define mmNIC10_RXB_CORE_SCT_AWUSER_BASE 0x5949610ull +#define NIC10_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC10_RXB_CORE_SCT_AWUSER_SECTION 0x8700 +#define mmNIC10_RXB_CORE_SPECIAL_BASE 0x5949E80ull +#define NIC10_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_RXB_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC10_RXE0_BASE 0x594A000ull +#define NIC10_RXE0_MAX_OFFSET 0x1000 +#define NIC10_RXE0_SECTION 0x9000 +#define mmNIC10_RXE0_WQE_ARUSER_BASE 0x594A900ull +#define NIC10_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC10_RXE0_WQE_ARUSER_SECTION 0x5800 +#define mmNIC10_RXE0_SPECIAL_BASE 0x594AE80ull +#define NIC10_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_RXE0_SPECIAL_SECTION 0x1800 +#define mmNIC10_RXE1_BASE 0x594B000ull +#define NIC10_RXE1_MAX_OFFSET 0x1000 +#define NIC10_RXE1_SECTION 0x9000 +#define mmNIC10_RXE1_WQE_ARUSER_BASE 0x594B900ull +#define NIC10_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC10_RXE1_WQE_ARUSER_SECTION 0x5800 +#define mmNIC10_RXE1_SPECIAL_BASE 0x594BE80ull +#define NIC10_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_RXE1_SPECIAL_SECTION 0x1800 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ0_BASE 0x594C000ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ1_BASE 0x594C050ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ2_BASE 0x594C0A0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ3_BASE 0x594C0F0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ4_BASE 0x594C140ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ5_BASE 0x594C190ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ6_BASE 0x594C1E0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ7_BASE 0x594C230ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ8_BASE 0x594C280ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ9_BASE 0x594C2D0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ10_BASE 0x594C320ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ11_BASE 0x594C370ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ12_BASE 0x594C3C0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ13_BASE 0x594C410ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ14_BASE 0x594C460ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ15_BASE 0x594C4B0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ16_BASE 0x594C500ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ17_BASE 0x594C550ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ18_BASE 0x594C5A0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ19_BASE 0x594C5F0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ20_BASE 0x594C640ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ21_BASE 0x594C690ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ22_BASE 0x594C6E0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ23_BASE 0x594C730ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ24_BASE 0x594C780ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ25_BASE 0x594C7D0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ26_BASE 0x594C820ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ27_BASE 0x594C870ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ28_BASE 0x594C8C0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ29_BASE 0x594C910ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ30_BASE 0x594C960ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ31_BASE 0x594C9B0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC10_RXE0_AXUSER_SPECIAL_BASE 0x594CE80ull +#define NIC10_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_RXE0_AXUSER_SPECIAL_SECTION 0x1800 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ0_BASE 0x594D000ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ1_BASE 0x594D050ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ2_BASE 0x594D0A0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ3_BASE 0x594D0F0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ4_BASE 0x594D140ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ5_BASE 0x594D190ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ6_BASE 0x594D1E0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ7_BASE 0x594D230ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ8_BASE 0x594D280ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ9_BASE 0x594D2D0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ10_BASE 0x594D320ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ11_BASE 0x594D370ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ12_BASE 0x594D3C0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ13_BASE 0x594D410ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ14_BASE 0x594D460ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ15_BASE 0x594D4B0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ16_BASE 0x594D500ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ17_BASE 0x594D550ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ18_BASE 0x594D5A0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ19_BASE 0x594D5F0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ20_BASE 0x594D640ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ21_BASE 0x594D690ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ22_BASE 0x594D6E0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ23_BASE 0x594D730ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ24_BASE 0x594D780ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ25_BASE 0x594D7D0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ26_BASE 0x594D820ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ27_BASE 0x594D870ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ28_BASE 0x594D8C0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ29_BASE 0x594D910ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ30_BASE 0x594D960ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ31_BASE 0x594D9B0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC10_RXE1_AXUSER_SPECIAL_BASE 0x594DE80ull +#define NIC10_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_RXE1_AXUSER_SPECIAL_SECTION 0x2180 +#define mmNIC10_TXS0_BASE 0x5950000ull +#define NIC10_TXS0_MAX_OFFSET 0x1000 +#define NIC10_TXS0_SECTION 0xE800 +#define mmNIC10_TXS0_SPECIAL_BASE 0x5950E80ull +#define NIC10_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_TXS0_SPECIAL_SECTION 0x1800 +#define mmNIC10_TXS1_BASE 0x5951000ull +#define NIC10_TXS1_MAX_OFFSET 0x1000 +#define NIC10_TXS1_SECTION 0xE800 +#define mmNIC10_TXS1_SPECIAL_BASE 0x5951E80ull +#define NIC10_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_TXS1_SPECIAL_SECTION 0x1800 +#define mmNIC10_TXE0_BASE 0x5952000ull +#define NIC10_TXE0_MAX_OFFSET 0x1000 +#define NIC10_TXE0_SECTION 0xE800 +#define mmNIC10_TXE0_SPECIAL_BASE 0x5952E80ull +#define NIC10_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_TXE0_SPECIAL_SECTION 0x1800 +#define mmNIC10_TXE1_BASE 0x5953000ull +#define NIC10_TXE1_MAX_OFFSET 0x1000 +#define NIC10_TXE1_SECTION 0xE800 +#define mmNIC10_TXE1_SPECIAL_BASE 0x5953E80ull +#define NIC10_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_TXE1_SPECIAL_SECTION 0x1800 +#define mmNIC10_TXB_BASE 0x5954000ull +#define NIC10_TXB_MAX_OFFSET 0x1000 +#define NIC10_TXB_SECTION 0xE800 +#define mmNIC10_TXB_SPECIAL_BASE 0x5954E80ull +#define NIC10_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_TXB_SPECIAL_SECTION 0x1800 +#define mmNIC10_MSTR_IF_RR_SHRD_HBW_BASE 0x5955000ull +#define NIC10_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC10_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmNIC10_MSTR_IF_RR_PRVT_HBW_BASE 0x5955200ull +#define NIC10_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC10_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmNIC10_MSTR_IF_RR_SHRD_LBW_BASE 0x5955400ull +#define NIC10_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC10_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmNIC10_MSTR_IF_RR_PRVT_LBW_BASE 0x5955600ull +#define NIC10_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC10_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmNIC10_MSTR_IF_E2E_CRDT_BASE 0x5955800ull +#define NIC10_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC10_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmNIC10_MSTR_IF_AXUSER_BASE 0x5955A80ull +#define NIC10_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC10_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmNIC10_MSTR_IF_DBG_HBW_BASE 0x5955B00ull +#define NIC10_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC10_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmNIC10_MSTR_IF_DBG_LBW_BASE 0x5955B80ull +#define NIC10_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC10_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmNIC10_MSTR_IF_CORE_HBW_BASE 0x5955C00ull +#define NIC10_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC10_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmNIC10_MSTR_IF_CORE_LBW_BASE 0x5955D80ull +#define NIC10_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC10_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmNIC10_MSTR_IF_SPECIAL_BASE 0x5955E80ull +#define NIC10_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmNIC10_TX_AXUSER_BASE 0x5956000ull +#define NIC10_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC10_TX_AXUSER_SECTION 0x2000 +#define mmNIC10_SERDES0_BASE 0x5958000ull +#define NIC10_SERDES0_MAX_OFFSET 0x3E40 +#define NIC10_SERDES0_SECTION 0x4000 +#define mmNIC10_SERDES1_BASE 0x595C000ull +#define NIC10_SERDES1_MAX_OFFSET 0x3E40 +#define NIC10_SERDES1_SECTION 0x4000 +#define mmNIC10_PHY_BASE 0x5960000ull +#define NIC10_PHY_MAX_OFFSET 0x1000 +#define NIC10_PHY_SECTION 0xE800 +#define mmNIC10_PHY_SPECIAL_BASE 0x5960E80ull +#define NIC10_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_PHY_SPECIAL_SECTION 0x7180 +#define mmPRT10_MAC_AUX_BASE 0x5968000ull +#define PRT10_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT10_MAC_AUX_SECTION 0xE800 +#define mmPRT10_MAC_AUX_SPECIAL_BASE 0x5968E80ull +#define PRT10_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT10_MAC_AUX_SPECIAL_SECTION 0x1800 +#define mmPRT10_MAC_CORE_BASE 0x5969000ull +#define PRT10_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT10_MAC_CORE_SECTION 0xE800 +#define mmPRT10_MAC_CORE_SPECIAL_BASE 0x5969E80ull +#define PRT10_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT10_MAC_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC10_MAC_RS_FEC_BASE 0x596A000ull +#define NIC10_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC10_MAC_RS_FEC_SECTION 0x1000 +#define mmNIC10_MAC_GLOB_STAT_CONTROL_REG_BASE 0x596B000ull +#define NIC10_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000 +#define NIC10_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000 +#define mmNIC10_MAC_GLOB_STAT_RX0_BASE 0x596B100ull +#define NIC10_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00 +#define NIC10_MAC_GLOB_STAT_RX0_SECTION 0x8C00 +#define mmNIC10_MAC_GLOB_STAT_RX1_BASE 0x596B18Cull +#define NIC10_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00 +#define NIC10_MAC_GLOB_STAT_RX1_SECTION 0x8C00 +#define mmNIC10_MAC_GLOB_STAT_RX2_BASE 0x596B218ull +#define NIC10_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00 +#define NIC10_MAC_GLOB_STAT_RX2_SECTION 0x8C00 +#define mmNIC10_MAC_GLOB_STAT_RX3_BASE 0x596B2A4ull +#define NIC10_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00 +#define NIC10_MAC_GLOB_STAT_RX3_SECTION 0x8C00 +#define mmNIC10_MAC_GLOB_STAT_TX0_BASE 0x596B330ull +#define NIC10_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800 +#define NIC10_MAC_GLOB_STAT_TX0_SECTION 0x6800 +#define mmNIC10_MAC_GLOB_STAT_TX1_BASE 0x596B398ull +#define NIC10_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800 +#define NIC10_MAC_GLOB_STAT_TX1_SECTION 0x6800 +#define mmNIC10_MAC_GLOB_STAT_TX2_BASE 0x596B400ull +#define NIC10_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800 +#define NIC10_MAC_GLOB_STAT_TX2_SECTION 0x6800 +#define mmNIC10_MAC_GLOB_STAT_TX3_BASE 0x596B468ull +#define NIC10_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800 +#define NIC10_MAC_GLOB_STAT_TX3_SECTION 0x3980 +#define mmNIC10_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x596B800ull +#define NIC10_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC10_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000 +#define mmNIC10_MAC_CH0_MAC_PCS_BASE 0x596C000ull +#define NIC10_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC10_MAC_CH0_MAC_PCS_SECTION 0x4000 +#define mmNIC10_MAC_CH0_MAC_128_BASE 0x596C400ull +#define NIC10_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC10_MAC_CH0_MAC_128_SECTION 0x4000 +#define mmNIC10_MAC_CH0_MAC_AN_BASE 0x596C800ull +#define NIC10_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC10_MAC_CH0_MAC_AN_SECTION 0x8000 +#define mmNIC10_MAC_CH1_MAC_PCS_BASE 0x596D000ull +#define NIC10_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC10_MAC_CH1_MAC_PCS_SECTION 0x4000 +#define mmNIC10_MAC_CH1_MAC_128_BASE 0x596D400ull +#define NIC10_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC10_MAC_CH1_MAC_128_SECTION 0x4000 +#define mmNIC10_MAC_CH1_MAC_AN_BASE 0x596D800ull +#define NIC10_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC10_MAC_CH1_MAC_AN_SECTION 0x8000 +#define mmNIC10_MAC_CH2_MAC_PCS_BASE 0x596E000ull +#define NIC10_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC10_MAC_CH2_MAC_PCS_SECTION 0x4000 +#define mmNIC10_MAC_CH2_MAC_128_BASE 0x596E400ull +#define NIC10_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC10_MAC_CH2_MAC_128_SECTION 0x4000 +#define mmNIC10_MAC_CH2_MAC_AN_BASE 0x596E800ull +#define NIC10_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC10_MAC_CH2_MAC_AN_SECTION 0x8000 +#define mmNIC10_MAC_CH3_MAC_PCS_BASE 0x596F000ull +#define NIC10_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC10_MAC_CH3_MAC_PCS_SECTION 0x4000 +#define mmNIC10_MAC_CH3_MAC_128_BASE 0x596F400ull +#define NIC10_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC10_MAC_CH3_MAC_128_SECTION 0x4000 +#define mmNIC10_MAC_CH3_MAC_AN_BASE 0x596F800ull +#define NIC10_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC10_MAC_CH3_MAC_AN_SECTION 0x10800 +#define mmNIC11_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5980000ull +#define NIC11_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5980080ull +#define NIC11_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5980100ull +#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5980180ull +#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_0_SPECIAL_BASE 0x5980E80ull +#define NIC11_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_0_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5981000ull +#define NIC11_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5981080ull +#define NIC11_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5981100ull +#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5981180ull +#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_1_SPECIAL_BASE 0x5981E80ull +#define NIC11_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_1_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5982000ull +#define NIC11_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5982080ull +#define NIC11_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5982100ull +#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5982180ull +#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_2_SPECIAL_BASE 0x5982E80ull +#define NIC11_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_2_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5983000ull +#define NIC11_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5983080ull +#define NIC11_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5983100ull +#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5983180ull +#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_3_SPECIAL_BASE 0x5983E80ull +#define NIC11_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_3_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5984000ull +#define NIC11_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5984080ull +#define NIC11_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5984100ull +#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5984180ull +#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_4_SPECIAL_BASE 0x5984E80ull +#define NIC11_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_4_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5985000ull +#define NIC11_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5985080ull +#define NIC11_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5985100ull +#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5985180ull +#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_5_SPECIAL_BASE 0x5985E80ull +#define NIC11_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_5_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5986000ull +#define NIC11_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5986080ull +#define NIC11_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5986100ull +#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5986180ull +#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_6_SPECIAL_BASE 0x5986E80ull +#define NIC11_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_6_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5987000ull +#define NIC11_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5987080ull +#define NIC11_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5987100ull +#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5987180ull +#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_7_SPECIAL_BASE 0x5987E80ull +#define NIC11_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_7_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5988000ull +#define NIC11_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5988080ull +#define NIC11_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5988100ull +#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5988180ull +#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_8_SPECIAL_BASE 0x5988E80ull +#define NIC11_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_8_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5989000ull +#define NIC11_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5989080ull +#define NIC11_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5989100ull +#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5989180ull +#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_9_SPECIAL_BASE 0x5989E80ull +#define NIC11_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_9_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_10_UNSECURE_DOORBELL0_BASE 0x598A000ull +#define NIC11_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_10_UNSECURE_DOORBELL1_BASE 0x598A080ull +#define NIC11_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x598A100ull +#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x598A180ull +#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_10_SPECIAL_BASE 0x598AE80ull +#define NIC11_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_10_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_11_UNSECURE_DOORBELL0_BASE 0x598B000ull +#define NIC11_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_11_UNSECURE_DOORBELL1_BASE 0x598B080ull +#define NIC11_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x598B100ull +#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x598B180ull +#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_11_SPECIAL_BASE 0x598BE80ull +#define NIC11_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_11_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_12_UNSECURE_DOORBELL0_BASE 0x598C000ull +#define NIC11_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_12_UNSECURE_DOORBELL1_BASE 0x598C080ull +#define NIC11_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x598C100ull +#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x598C180ull +#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_12_SPECIAL_BASE 0x598CE80ull +#define NIC11_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_12_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_13_UNSECURE_DOORBELL0_BASE 0x598D000ull +#define NIC11_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_13_UNSECURE_DOORBELL1_BASE 0x598D080ull +#define NIC11_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x598D100ull +#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x598D180ull +#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_13_SPECIAL_BASE 0x598DE80ull +#define NIC11_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_13_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR0_14_UNSECURE_DOORBELL0_BASE 0x598E000ull +#define NIC11_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR0_14_UNSECURE_DOORBELL1_BASE 0x598E080ull +#define NIC11_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x598E100ull +#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x598E180ull +#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR0_14_SPECIAL_BASE 0x598EE80ull +#define NIC11_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_14_SPECIAL_SECTION 0x1180 +#define mmNIC11_QM_DCCM0_BASE 0x5990000ull +#define NIC11_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC11_QM_DCCM0_SECTION 0x8000 +#define mmNIC11_QM_ARC_AUX0_BASE 0x5998000ull +#define NIC11_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC11_QM_ARC_AUX0_SECTION 0xE800 +#define mmNIC11_QM_ARC_AUX0_SPECIAL_BASE 0x5998E80ull +#define NIC11_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 +#define mmNIC11_QM0_BASE 0x599A000ull +#define NIC11_QM0_MAX_OFFSET 0x1000 +#define NIC11_QM0_SECTION 0x9000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x599A900ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x599A908ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x599A910ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x599A918ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x599A920ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x599A928ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x599A930ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x599A938ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x599A940ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x599A948ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x599A950ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x599A958ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x599A960ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x599A968ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x599A970ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x599A978ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC11_QM0_AXUSER_SECURED_BASE 0x599AB00ull +#define NIC11_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC11_QM0_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC11_QM0_AXUSER_NONSECURED_BASE 0x599AB80ull +#define NIC11_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC11_QM0_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC11_QM0_DBG_HBW_BASE 0x599AC00ull +#define NIC11_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC11_QM0_DBG_HBW_SECTION 0x8000 +#define mmNIC11_QM0_DBG_LBW_BASE 0x599AC80ull +#define NIC11_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC11_QM0_DBG_LBW_SECTION 0x1000 +#define mmNIC11_QM0_CGM_BASE 0x599AD80ull +#define NIC11_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC11_QM0_CGM_SECTION 0x1000 +#define mmNIC11_QM0_SPECIAL_BASE 0x599AE80ull +#define NIC11_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_QM0_SPECIAL_SECTION 0x4180 +#define mmNIC11_QPC0_BASE 0x599F000ull +#define NIC11_QPC0_MAX_OFFSET 0x1000 +#define NIC11_QPC0_SECTION 0x7200 +#define mmNIC11_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x599F720ull +#define NIC11_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x599F728ull +#define NIC11_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x599F730ull +#define NIC11_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x599F738ull +#define NIC11_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x599F740ull +#define NIC11_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x599F748ull +#define NIC11_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x599F750ull +#define NIC11_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x599F758ull +#define NIC11_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x599F760ull +#define NIC11_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x599F768ull +#define NIC11_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x599F770ull +#define NIC11_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x599F778ull +#define NIC11_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x599F780ull +#define NIC11_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x599F788ull +#define NIC11_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x599F790ull +#define NIC11_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x599F798ull +#define NIC11_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x599F7A0ull +#define NIC11_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x599F7A8ull +#define NIC11_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x599F7B0ull +#define NIC11_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x599F7B8ull +#define NIC11_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x599F7C0ull +#define NIC11_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x599F7C8ull +#define NIC11_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x599F7D0ull +#define NIC11_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x599F7D8ull +#define NIC11_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x599F7E0ull +#define NIC11_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x599F7E8ull +#define NIC11_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x599F7F0ull +#define NIC11_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x599F7F8ull +#define NIC11_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x599F800ull +#define NIC11_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x599F808ull +#define NIC11_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x599F810ull +#define NIC11_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x599F818ull +#define NIC11_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC11_QPC0_AXUSER_CONG_QUE_BASE 0x599FB80ull +#define NIC11_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC11_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC11_QPC0_AXUSER_RXWQE_BASE 0x599FBE0ull +#define NIC11_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC11_QPC0_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC11_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x599FC40ull +#define NIC11_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC11_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC11_QPC0_AXUSER_DB_FIFO_BASE 0x599FCA0ull +#define NIC11_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC11_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC11_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x599FD00ull +#define NIC11_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC11_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC11_QPC0_AXUSER_ERR_FIFO_BASE 0x599FD60ull +#define NIC11_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC11_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC11_QPC0_AXUSER_QPC_RESP_BASE 0x599FDC0ull +#define NIC11_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC11_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC11_QPC0_AXUSER_QPC_REQ_BASE 0x599FE20ull +#define NIC11_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC11_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC11_QPC0_SPECIAL_BASE 0x599FE80ull +#define NIC11_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_QPC0_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_0_UNSECURE_DOORBELL0_BASE 0x59A0000ull +#define NIC11_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_0_UNSECURE_DOORBELL1_BASE 0x59A0080ull +#define NIC11_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x59A0100ull +#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x59A0180ull +#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_0_SPECIAL_BASE 0x59A0E80ull +#define NIC11_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_0_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_1_UNSECURE_DOORBELL0_BASE 0x59A1000ull +#define NIC11_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_1_UNSECURE_DOORBELL1_BASE 0x59A1080ull +#define NIC11_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x59A1100ull +#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x59A1180ull +#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_1_SPECIAL_BASE 0x59A1E80ull +#define NIC11_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_1_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_2_UNSECURE_DOORBELL0_BASE 0x59A2000ull +#define NIC11_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_2_UNSECURE_DOORBELL1_BASE 0x59A2080ull +#define NIC11_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x59A2100ull +#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x59A2180ull +#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_2_SPECIAL_BASE 0x59A2E80ull +#define NIC11_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_2_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_3_UNSECURE_DOORBELL0_BASE 0x59A3000ull +#define NIC11_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_3_UNSECURE_DOORBELL1_BASE 0x59A3080ull +#define NIC11_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x59A3100ull +#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x59A3180ull +#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_3_SPECIAL_BASE 0x59A3E80ull +#define NIC11_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_3_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_4_UNSECURE_DOORBELL0_BASE 0x59A4000ull +#define NIC11_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_4_UNSECURE_DOORBELL1_BASE 0x59A4080ull +#define NIC11_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x59A4100ull +#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x59A4180ull +#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_4_SPECIAL_BASE 0x59A4E80ull +#define NIC11_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_4_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_5_UNSECURE_DOORBELL0_BASE 0x59A5000ull +#define NIC11_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_5_UNSECURE_DOORBELL1_BASE 0x59A5080ull +#define NIC11_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x59A5100ull +#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x59A5180ull +#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_5_SPECIAL_BASE 0x59A5E80ull +#define NIC11_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_5_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_6_UNSECURE_DOORBELL0_BASE 0x59A6000ull +#define NIC11_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_6_UNSECURE_DOORBELL1_BASE 0x59A6080ull +#define NIC11_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x59A6100ull +#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x59A6180ull +#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_6_SPECIAL_BASE 0x59A6E80ull +#define NIC11_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_6_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_7_UNSECURE_DOORBELL0_BASE 0x59A7000ull +#define NIC11_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_7_UNSECURE_DOORBELL1_BASE 0x59A7080ull +#define NIC11_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x59A7100ull +#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x59A7180ull +#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_7_SPECIAL_BASE 0x59A7E80ull +#define NIC11_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_7_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_8_UNSECURE_DOORBELL0_BASE 0x59A8000ull +#define NIC11_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_8_UNSECURE_DOORBELL1_BASE 0x59A8080ull +#define NIC11_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x59A8100ull +#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x59A8180ull +#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_8_SPECIAL_BASE 0x59A8E80ull +#define NIC11_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_8_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_9_UNSECURE_DOORBELL0_BASE 0x59A9000ull +#define NIC11_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_9_UNSECURE_DOORBELL1_BASE 0x59A9080ull +#define NIC11_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x59A9100ull +#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x59A9180ull +#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_9_SPECIAL_BASE 0x59A9E80ull +#define NIC11_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_9_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_10_UNSECURE_DOORBELL0_BASE 0x59AA000ull +#define NIC11_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_10_UNSECURE_DOORBELL1_BASE 0x59AA080ull +#define NIC11_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x59AA100ull +#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x59AA180ull +#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_10_SPECIAL_BASE 0x59AAE80ull +#define NIC11_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_10_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_11_UNSECURE_DOORBELL0_BASE 0x59AB000ull +#define NIC11_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_11_UNSECURE_DOORBELL1_BASE 0x59AB080ull +#define NIC11_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x59AB100ull +#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x59AB180ull +#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_11_SPECIAL_BASE 0x59ABE80ull +#define NIC11_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_11_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_12_UNSECURE_DOORBELL0_BASE 0x59AC000ull +#define NIC11_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_12_UNSECURE_DOORBELL1_BASE 0x59AC080ull +#define NIC11_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x59AC100ull +#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x59AC180ull +#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_12_SPECIAL_BASE 0x59ACE80ull +#define NIC11_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_12_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_13_UNSECURE_DOORBELL0_BASE 0x59AD000ull +#define NIC11_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_13_UNSECURE_DOORBELL1_BASE 0x59AD080ull +#define NIC11_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x59AD100ull +#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x59AD180ull +#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_13_SPECIAL_BASE 0x59ADE80ull +#define NIC11_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_13_SPECIAL_SECTION 0x1800 +#define mmNIC11_UMR1_14_UNSECURE_DOORBELL0_BASE 0x59AE000ull +#define NIC11_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 +#define mmNIC11_UMR1_14_UNSECURE_DOORBELL1_BASE 0x59AE080ull +#define NIC11_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 +#define mmNIC11_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x59AE100ull +#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 +#define mmNIC11_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x59AE180ull +#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 +#define mmNIC11_UMR1_14_SPECIAL_BASE 0x59AEE80ull +#define NIC11_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_14_SPECIAL_SECTION 0x1180 +#define mmNIC11_QM_DCCM1_BASE 0x59B0000ull +#define NIC11_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC11_QM_DCCM1_SECTION 0x8000 +#define mmNIC11_QM_ARC_AUX1_BASE 0x59B8000ull +#define NIC11_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC11_QM_ARC_AUX1_SECTION 0xE800 +#define mmNIC11_QM_ARC_AUX1_SPECIAL_BASE 0x59B8E80ull +#define NIC11_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 +#define mmNIC11_QM1_BASE 0x59BA000ull +#define NIC11_QM1_MAX_OFFSET 0x1000 +#define NIC11_QM1_SECTION 0x9000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x59BA900ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x59BA908ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x59BA910ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x59BA918ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x59BA920ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x59BA928ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x59BA930ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x59BA938ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x59BA940ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x59BA948ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x59BA950ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x59BA958ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x59BA960ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x59BA968ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x59BA970ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x59BA978ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 +#define mmNIC11_QM1_AXUSER_SECURED_BASE 0x59BAB00ull +#define NIC11_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC11_QM1_AXUSER_SECURED_SECTION 0x8000 +#define mmNIC11_QM1_AXUSER_NONSECURED_BASE 0x59BAB80ull +#define NIC11_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC11_QM1_AXUSER_NONSECURED_SECTION 0x8000 +#define mmNIC11_QM1_DBG_HBW_BASE 0x59BAC00ull +#define NIC11_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC11_QM1_DBG_HBW_SECTION 0x8000 +#define mmNIC11_QM1_DBG_LBW_BASE 0x59BAC80ull +#define NIC11_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC11_QM1_DBG_LBW_SECTION 0x1000 +#define mmNIC11_QM1_CGM_BASE 0x59BAD80ull +#define NIC11_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC11_QM1_CGM_SECTION 0x1000 +#define mmNIC11_QM1_SPECIAL_BASE 0x59BAE80ull +#define NIC11_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_QM1_SPECIAL_SECTION 0x4180 +#define mmNIC11_QPC1_BASE 0x59BF000ull +#define NIC11_QPC1_MAX_OFFSET 0x1000 +#define NIC11_QPC1_SECTION 0x7200 +#define mmNIC11_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x59BF720ull +#define NIC11_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x59BF728ull +#define NIC11_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x59BF730ull +#define NIC11_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x59BF738ull +#define NIC11_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x59BF740ull +#define NIC11_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x59BF748ull +#define NIC11_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x59BF750ull +#define NIC11_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x59BF758ull +#define NIC11_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x59BF760ull +#define NIC11_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x59BF768ull +#define NIC11_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x59BF770ull +#define NIC11_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x59BF778ull +#define NIC11_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x59BF780ull +#define NIC11_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x59BF788ull +#define NIC11_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x59BF790ull +#define NIC11_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x59BF798ull +#define NIC11_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x59BF7A0ull +#define NIC11_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x59BF7A8ull +#define NIC11_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x59BF7B0ull +#define NIC11_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x59BF7B8ull +#define NIC11_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x59BF7C0ull +#define NIC11_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x59BF7C8ull +#define NIC11_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x59BF7D0ull +#define NIC11_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x59BF7D8ull +#define NIC11_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x59BF7E0ull +#define NIC11_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x59BF7E8ull +#define NIC11_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x59BF7F0ull +#define NIC11_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x59BF7F8ull +#define NIC11_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x59BF800ull +#define NIC11_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x59BF808ull +#define NIC11_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x59BF810ull +#define NIC11_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 +#define mmNIC11_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x59BF818ull +#define NIC11_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 +#define mmNIC11_QPC1_AXUSER_CONG_QUE_BASE 0x59BFB80ull +#define NIC11_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC11_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 +#define mmNIC11_QPC1_AXUSER_RXWQE_BASE 0x59BFBE0ull +#define NIC11_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC11_QPC1_AXUSER_RXWQE_SECTION 0x6000 +#define mmNIC11_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x59BFC40ull +#define NIC11_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC11_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 +#define mmNIC11_QPC1_AXUSER_DB_FIFO_BASE 0x59BFCA0ull +#define NIC11_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC11_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 +#define mmNIC11_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x59BFD00ull +#define NIC11_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC11_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 +#define mmNIC11_QPC1_AXUSER_ERR_FIFO_BASE 0x59BFD60ull +#define NIC11_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC11_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 +#define mmNIC11_QPC1_AXUSER_QPC_RESP_BASE 0x59BFDC0ull +#define NIC11_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC11_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 +#define mmNIC11_QPC1_AXUSER_QPC_REQ_BASE 0x59BFE20ull +#define NIC11_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC11_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 +#define mmNIC11_QPC1_SPECIAL_BASE 0x59BFE80ull +#define NIC11_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_QPC1_SPECIAL_SECTION 0x8180 +#define mmNIC11_TMR_BASE 0x59C8000ull +#define NIC11_TMR_MAX_OFFSET 0x1000 +#define NIC11_TMR_SECTION 0xD600 +#define mmNIC11_TMR_AXUSER_TMR_FREE_LIST_BASE 0x59C8D60ull +#define NIC11_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC11_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 +#define mmNIC11_TMR_AXUSER_TMR_FIFO_BASE 0x59C8DC0ull +#define NIC11_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC11_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 +#define mmNIC11_TMR_AXUSER_TMR_FSM_BASE 0x59C8E20ull +#define NIC11_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC11_TMR_AXUSER_TMR_FSM_SECTION 0x6000 +#define mmNIC11_TMR_SPECIAL_BASE 0x59C8E80ull +#define NIC11_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_TMR_SPECIAL_SECTION 0x1800 +#define mmNIC11_RXB_CORE_BASE 0x59C9000ull +#define NIC11_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC11_RXB_CORE_SECTION 0x6100 +#define mmNIC11_RXB_CORE_SCT_AWUSER_BASE 0x59C9610ull +#define NIC11_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC11_RXB_CORE_SCT_AWUSER_SECTION 0x8700 +#define mmNIC11_RXB_CORE_SPECIAL_BASE 0x59C9E80ull +#define NIC11_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_RXB_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC11_RXE0_BASE 0x59CA000ull +#define NIC11_RXE0_MAX_OFFSET 0x1000 +#define NIC11_RXE0_SECTION 0x9000 +#define mmNIC11_RXE0_WQE_ARUSER_BASE 0x59CA900ull +#define NIC11_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC11_RXE0_WQE_ARUSER_SECTION 0x5800 +#define mmNIC11_RXE0_SPECIAL_BASE 0x59CAE80ull +#define NIC11_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_RXE0_SPECIAL_SECTION 0x1800 +#define mmNIC11_RXE1_BASE 0x59CB000ull +#define NIC11_RXE1_MAX_OFFSET 0x1000 +#define NIC11_RXE1_SECTION 0x9000 +#define mmNIC11_RXE1_WQE_ARUSER_BASE 0x59CB900ull +#define NIC11_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC11_RXE1_WQE_ARUSER_SECTION 0x5800 +#define mmNIC11_RXE1_SPECIAL_BASE 0x59CBE80ull +#define NIC11_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_RXE1_SPECIAL_SECTION 0x1800 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ0_BASE 0x59CC000ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ1_BASE 0x59CC050ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ2_BASE 0x59CC0A0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ3_BASE 0x59CC0F0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ4_BASE 0x59CC140ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ5_BASE 0x59CC190ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ6_BASE 0x59CC1E0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ7_BASE 0x59CC230ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ8_BASE 0x59CC280ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ9_BASE 0x59CC2D0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ10_BASE 0x59CC320ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ11_BASE 0x59CC370ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ12_BASE 0x59CC3C0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ13_BASE 0x59CC410ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ14_BASE 0x59CC460ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ15_BASE 0x59CC4B0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ16_BASE 0x59CC500ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ17_BASE 0x59CC550ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ18_BASE 0x59CC5A0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ19_BASE 0x59CC5F0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ20_BASE 0x59CC640ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ21_BASE 0x59CC690ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ22_BASE 0x59CC6E0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ23_BASE 0x59CC730ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ24_BASE 0x59CC780ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ25_BASE 0x59CC7D0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ26_BASE 0x59CC820ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ27_BASE 0x59CC870ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ28_BASE 0x59CC8C0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ29_BASE 0x59CC910ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ30_BASE 0x59CC960ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ31_BASE 0x59CC9B0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC11_RXE0_AXUSER_SPECIAL_BASE 0x59CCE80ull +#define NIC11_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_RXE0_AXUSER_SPECIAL_SECTION 0x1800 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ0_BASE 0x59CD000ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ1_BASE 0x59CD050ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ2_BASE 0x59CD0A0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ3_BASE 0x59CD0F0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ4_BASE 0x59CD140ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ5_BASE 0x59CD190ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ6_BASE 0x59CD1E0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ7_BASE 0x59CD230ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ8_BASE 0x59CD280ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ9_BASE 0x59CD2D0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ10_BASE 0x59CD320ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ11_BASE 0x59CD370ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ12_BASE 0x59CD3C0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ13_BASE 0x59CD410ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ14_BASE 0x59CD460ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ15_BASE 0x59CD4B0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ16_BASE 0x59CD500ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ17_BASE 0x59CD550ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ18_BASE 0x59CD5A0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ19_BASE 0x59CD5F0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ20_BASE 0x59CD640ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ21_BASE 0x59CD690ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ22_BASE 0x59CD6E0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ23_BASE 0x59CD730ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ24_BASE 0x59CD780ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ25_BASE 0x59CD7D0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ26_BASE 0x59CD820ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ27_BASE 0x59CD870ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ28_BASE 0x59CD8C0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ29_BASE 0x59CD910ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ30_BASE 0x59CD960ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ31_BASE 0x59CD9B0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 +#define mmNIC11_RXE1_AXUSER_SPECIAL_BASE 0x59CDE80ull +#define NIC11_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_RXE1_AXUSER_SPECIAL_SECTION 0x2180 +#define mmNIC11_TXS0_BASE 0x59D0000ull +#define NIC11_TXS0_MAX_OFFSET 0x1000 +#define NIC11_TXS0_SECTION 0xE800 +#define mmNIC11_TXS0_SPECIAL_BASE 0x59D0E80ull +#define NIC11_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_TXS0_SPECIAL_SECTION 0x1800 +#define mmNIC11_TXS1_BASE 0x59D1000ull +#define NIC11_TXS1_MAX_OFFSET 0x1000 +#define NIC11_TXS1_SECTION 0xE800 +#define mmNIC11_TXS1_SPECIAL_BASE 0x59D1E80ull +#define NIC11_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_TXS1_SPECIAL_SECTION 0x1800 +#define mmNIC11_TXE0_BASE 0x59D2000ull +#define NIC11_TXE0_MAX_OFFSET 0x1000 +#define NIC11_TXE0_SECTION 0xE800 +#define mmNIC11_TXE0_SPECIAL_BASE 0x59D2E80ull +#define NIC11_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_TXE0_SPECIAL_SECTION 0x1800 +#define mmNIC11_TXE1_BASE 0x59D3000ull +#define NIC11_TXE1_MAX_OFFSET 0x1000 +#define NIC11_TXE1_SECTION 0xE800 +#define mmNIC11_TXE1_SPECIAL_BASE 0x59D3E80ull +#define NIC11_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_TXE1_SPECIAL_SECTION 0x1800 +#define mmNIC11_TXB_BASE 0x59D4000ull +#define NIC11_TXB_MAX_OFFSET 0x1000 +#define NIC11_TXB_SECTION 0xE800 +#define mmNIC11_TXB_SPECIAL_BASE 0x59D4E80ull +#define NIC11_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_TXB_SPECIAL_SECTION 0x1800 +#define mmNIC11_MSTR_IF_RR_SHRD_HBW_BASE 0x59D5000ull +#define NIC11_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC11_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 +#define mmNIC11_MSTR_IF_RR_PRVT_HBW_BASE 0x59D5200ull +#define NIC11_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC11_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 +#define mmNIC11_MSTR_IF_RR_SHRD_LBW_BASE 0x59D5400ull +#define NIC11_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC11_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 +#define mmNIC11_MSTR_IF_RR_PRVT_LBW_BASE 0x59D5600ull +#define NIC11_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC11_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 +#define mmNIC11_MSTR_IF_E2E_CRDT_BASE 0x59D5800ull +#define NIC11_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC11_MSTR_IF_E2E_CRDT_SECTION 0x2800 +#define mmNIC11_MSTR_IF_AXUSER_BASE 0x59D5A80ull +#define NIC11_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC11_MSTR_IF_AXUSER_SECTION 0x8000 +#define mmNIC11_MSTR_IF_DBG_HBW_BASE 0x59D5B00ull +#define NIC11_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC11_MSTR_IF_DBG_HBW_SECTION 0x8000 +#define mmNIC11_MSTR_IF_DBG_LBW_BASE 0x59D5B80ull +#define NIC11_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC11_MSTR_IF_DBG_LBW_SECTION 0x8000 +#define mmNIC11_MSTR_IF_CORE_HBW_BASE 0x59D5C00ull +#define NIC11_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC11_MSTR_IF_CORE_HBW_SECTION 0x1800 +#define mmNIC11_MSTR_IF_CORE_LBW_BASE 0x59D5D80ull +#define NIC11_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC11_MSTR_IF_CORE_LBW_SECTION 0x1000 +#define mmNIC11_MSTR_IF_SPECIAL_BASE 0x59D5E80ull +#define NIC11_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_MSTR_IF_SPECIAL_SECTION 0x1800 +#define mmNIC11_TX_AXUSER_BASE 0x59D6000ull +#define NIC11_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC11_TX_AXUSER_SECTION 0x2000 +#define mmNIC11_SERDES0_BASE 0x59D8000ull +#define NIC11_SERDES0_MAX_OFFSET 0x3E40 +#define NIC11_SERDES0_SECTION 0x4000 +#define mmNIC11_SERDES1_BASE 0x59DC000ull +#define NIC11_SERDES1_MAX_OFFSET 0x3E40 +#define NIC11_SERDES1_SECTION 0x4000 +#define mmNIC11_PHY_BASE 0x59E0000ull +#define NIC11_PHY_MAX_OFFSET 0x1000 +#define NIC11_PHY_SECTION 0xE800 +#define mmNIC11_PHY_SPECIAL_BASE 0x59E0E80ull +#define NIC11_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_PHY_SPECIAL_SECTION 0x7180 +#define mmPRT11_MAC_AUX_BASE 0x59E8000ull +#define PRT11_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT11_MAC_AUX_SECTION 0xE800 +#define mmPRT11_MAC_AUX_SPECIAL_BASE 0x59E8E80ull +#define PRT11_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT11_MAC_AUX_SPECIAL_SECTION 0x1800 +#define mmPRT11_MAC_CORE_BASE 0x59E9000ull +#define PRT11_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT11_MAC_CORE_SECTION 0xE800 +#define mmPRT11_MAC_CORE_SPECIAL_BASE 0x59E9E80ull +#define PRT11_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT11_MAC_CORE_SPECIAL_SECTION 0x1800 +#define mmNIC11_MAC_RS_FEC_BASE 0x59EA000ull +#define NIC11_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC11_MAC_RS_FEC_SECTION 0x1000 +#define mmNIC11_MAC_GLOB_STAT_CONTROL_REG_BASE 0x59EB000ull +#define NIC11_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000 +#define NIC11_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000 +#define mmNIC11_MAC_GLOB_STAT_RX0_BASE 0x59EB100ull +#define NIC11_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00 +#define NIC11_MAC_GLOB_STAT_RX0_SECTION 0x8C00 +#define mmNIC11_MAC_GLOB_STAT_RX1_BASE 0x59EB18Cull +#define NIC11_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00 +#define NIC11_MAC_GLOB_STAT_RX1_SECTION 0x8C00 +#define mmNIC11_MAC_GLOB_STAT_RX2_BASE 0x59EB218ull +#define NIC11_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00 +#define NIC11_MAC_GLOB_STAT_RX2_SECTION 0x8C00 +#define mmNIC11_MAC_GLOB_STAT_RX3_BASE 0x59EB2A4ull +#define NIC11_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00 +#define NIC11_MAC_GLOB_STAT_RX3_SECTION 0x8C00 +#define mmNIC11_MAC_GLOB_STAT_TX0_BASE 0x59EB330ull +#define NIC11_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800 +#define NIC11_MAC_GLOB_STAT_TX0_SECTION 0x6800 +#define mmNIC11_MAC_GLOB_STAT_TX1_BASE 0x59EB398ull +#define NIC11_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800 +#define NIC11_MAC_GLOB_STAT_TX1_SECTION 0x6800 +#define mmNIC11_MAC_GLOB_STAT_TX2_BASE 0x59EB400ull +#define NIC11_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800 +#define NIC11_MAC_GLOB_STAT_TX2_SECTION 0x6800 +#define mmNIC11_MAC_GLOB_STAT_TX3_BASE 0x59EB468ull +#define NIC11_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800 +#define NIC11_MAC_GLOB_STAT_TX3_SECTION 0x3980 +#define mmNIC11_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x59EB800ull +#define NIC11_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC11_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000 +#define mmNIC11_MAC_CH0_MAC_PCS_BASE 0x59EC000ull +#define NIC11_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC11_MAC_CH0_MAC_PCS_SECTION 0x4000 +#define mmNIC11_MAC_CH0_MAC_128_BASE 0x59EC400ull +#define NIC11_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC11_MAC_CH0_MAC_128_SECTION 0x4000 +#define mmNIC11_MAC_CH0_MAC_AN_BASE 0x59EC800ull +#define NIC11_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC11_MAC_CH0_MAC_AN_SECTION 0x8000 +#define mmNIC11_MAC_CH1_MAC_PCS_BASE 0x59ED000ull +#define NIC11_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC11_MAC_CH1_MAC_PCS_SECTION 0x4000 +#define mmNIC11_MAC_CH1_MAC_128_BASE 0x59ED400ull +#define NIC11_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC11_MAC_CH1_MAC_128_SECTION 0x4000 +#define mmNIC11_MAC_CH1_MAC_AN_BASE 0x59ED800ull +#define NIC11_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC11_MAC_CH1_MAC_AN_SECTION 0x8000 +#define mmNIC11_MAC_CH2_MAC_PCS_BASE 0x59EE000ull +#define NIC11_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC11_MAC_CH2_MAC_PCS_SECTION 0x4000 +#define mmNIC11_MAC_CH2_MAC_128_BASE 0x59EE400ull +#define NIC11_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC11_MAC_CH2_MAC_128_SECTION 0x4000 +#define mmNIC11_MAC_CH2_MAC_AN_BASE 0x59EE800ull +#define NIC11_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC11_MAC_CH2_MAC_AN_SECTION 0x8000 +#define mmNIC11_MAC_CH3_MAC_PCS_BASE 0x59EF000ull +#define NIC11_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC11_MAC_CH3_MAC_PCS_SECTION 0x4000 +#define mmNIC11_MAC_CH3_MAC_128_BASE 0x59EF400ull +#define NIC11_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC11_MAC_CH3_MAC_128_SECTION 0x4000 +#define mmNIC11_MAC_CH3_MAC_AN_BASE 0x59EF800ull +#define NIC11_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC11_MAC_CH3_MAC_AN_SECTION 0x610800 +#define mmDCORE0_ROM_TABLE_L_BASE 0x6000000ull +#define DCORE0_ROM_TABLE_L_MAX_OFFSET 0x1000 +#define DCORE0_ROM_TABLE_L_SECTION 0x80000 +#define mmDCORE0_HMMU0_CS_ROM_TBL_BASE 0x6080000ull +#define DCORE0_HMMU0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_HMMU0_CS_STM_BASE 0x6081000ull +#define DCORE0_HMMU0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_CS_STM_SECTION 0x1000 +#define mmDCORE0_HMMU0_CS_CTI_BASE 0x6082000ull +#define DCORE0_HMMU0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_CS_CTI_SECTION 0x1000 +#define mmDCORE0_HMMU0_CS_ETF_BASE 0x6083000ull +#define DCORE0_HMMU0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_CS_ETF_SECTION 0x1000 +#define mmDCORE0_HMMU0_CS_SPMU_BASE 0x6084000ull +#define DCORE0_HMMU0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_CS_SPMU_SECTION 0x1000 +#define mmDCORE0_HMMU0_BMON_CTI_BASE 0x6085000ull +#define DCORE0_HMMU0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_BMON_CTI_SECTION 0x1000 +#define mmDCORE0_HMMU0_USER_CTI_BASE 0x6086000ull +#define DCORE0_HMMU0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_USER_CTI_SECTION 0x1000 +#define mmDCORE0_HMMU0_BMON_0_BASE 0x6087000ull +#define DCORE0_HMMU0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_BMON_0_SECTION 0x1000 +#define mmDCORE0_HMMU0_BMON_1_BASE 0x6088000ull +#define DCORE0_HMMU0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_BMON_1_SECTION 0x1000 +#define mmDCORE0_HMMU0_BMON_3_BASE 0x6089000ull +#define DCORE0_HMMU0_BMON_3_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_BMON_3_SECTION 0x1000 +#define mmDCORE0_HMMU0_BMON_2_BASE 0x608A000ull +#define DCORE0_HMMU0_BMON_2_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_BMON_2_SECTION 0x1000 +#define mmDCORE0_HMMU0_BMON_4_BASE 0x608B000ull +#define DCORE0_HMMU0_BMON_4_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_BMON_4_SECTION 0x5000 +#define mmDCORE0_HMMU1_CS_ROM_TBL_BASE 0x6090000ull +#define DCORE0_HMMU1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_HMMU1_CS_STM_BASE 0x6091000ull +#define DCORE0_HMMU1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_CS_STM_SECTION 0x1000 +#define mmDCORE0_HMMU1_CS_CTI_BASE 0x6092000ull +#define DCORE0_HMMU1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_CS_CTI_SECTION 0x1000 +#define mmDCORE0_HMMU1_CS_ETF_BASE 0x6093000ull +#define DCORE0_HMMU1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_CS_ETF_SECTION 0x1000 +#define mmDCORE0_HMMU1_CS_SPMU_BASE 0x6094000ull +#define DCORE0_HMMU1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_CS_SPMU_SECTION 0x1000 +#define mmDCORE0_HMMU1_BMON_CTI_BASE 0x6095000ull +#define DCORE0_HMMU1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_BMON_CTI_SECTION 0x1000 +#define mmDCORE0_HMMU1_USER_CTI_BASE 0x6096000ull +#define DCORE0_HMMU1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_USER_CTI_SECTION 0x1000 +#define mmDCORE0_HMMU1_BMON_0_BASE 0x6097000ull +#define DCORE0_HMMU1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_BMON_0_SECTION 0x1000 +#define mmDCORE0_HMMU1_BMON_1_BASE 0x6098000ull +#define DCORE0_HMMU1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_BMON_1_SECTION 0x1000 +#define mmDCORE0_HMMU1_BMON_3_BASE 0x6099000ull +#define DCORE0_HMMU1_BMON_3_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_BMON_3_SECTION 0x1000 +#define mmDCORE0_HMMU1_BMON_2_BASE 0x609A000ull +#define DCORE0_HMMU1_BMON_2_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_BMON_2_SECTION 0x1000 +#define mmDCORE0_HMMU1_BMON_4_BASE 0x609B000ull +#define DCORE0_HMMU1_BMON_4_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_BMON_4_SECTION 0x5000 +#define mmDCORE0_HMMU2_CS_ROM_TBL_BASE 0x60A0000ull +#define DCORE0_HMMU2_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_HMMU2_CS_STM_BASE 0x60A1000ull +#define DCORE0_HMMU2_CS_STM_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_CS_STM_SECTION 0x1000 +#define mmDCORE0_HMMU2_CS_CTI_BASE 0x60A2000ull +#define DCORE0_HMMU2_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_CS_CTI_SECTION 0x1000 +#define mmDCORE0_HMMU2_CS_ETF_BASE 0x60A3000ull +#define DCORE0_HMMU2_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_CS_ETF_SECTION 0x1000 +#define mmDCORE0_HMMU2_CS_SPMU_BASE 0x60A4000ull +#define DCORE0_HMMU2_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_CS_SPMU_SECTION 0x1000 +#define mmDCORE0_HMMU2_BMON_CTI_BASE 0x60A5000ull +#define DCORE0_HMMU2_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_BMON_CTI_SECTION 0x1000 +#define mmDCORE0_HMMU2_USER_CTI_BASE 0x60A6000ull +#define DCORE0_HMMU2_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_USER_CTI_SECTION 0x1000 +#define mmDCORE0_HMMU2_BMON_0_BASE 0x60A7000ull +#define DCORE0_HMMU2_BMON_0_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_BMON_0_SECTION 0x1000 +#define mmDCORE0_HMMU2_BMON_1_BASE 0x60A8000ull +#define DCORE0_HMMU2_BMON_1_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_BMON_1_SECTION 0x1000 +#define mmDCORE0_HMMU2_BMON_3_BASE 0x60A9000ull +#define DCORE0_HMMU2_BMON_3_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_BMON_3_SECTION 0x1000 +#define mmDCORE0_HMMU2_BMON_2_BASE 0x60AA000ull +#define DCORE0_HMMU2_BMON_2_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_BMON_2_SECTION 0x1000 +#define mmDCORE0_HMMU2_BMON_4_BASE 0x60AB000ull +#define DCORE0_HMMU2_BMON_4_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_BMON_4_SECTION 0x5000 +#define mmDCORE0_HMMU3_CS_ROM_TBL_BASE 0x60B0000ull +#define DCORE0_HMMU3_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_HMMU3_CS_STM_BASE 0x60B1000ull +#define DCORE0_HMMU3_CS_STM_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_CS_STM_SECTION 0x1000 +#define mmDCORE0_HMMU3_CS_CTI_BASE 0x60B2000ull +#define DCORE0_HMMU3_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_CS_CTI_SECTION 0x1000 +#define mmDCORE0_HMMU3_CS_ETF_BASE 0x60B3000ull +#define DCORE0_HMMU3_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_CS_ETF_SECTION 0x1000 +#define mmDCORE0_HMMU3_CS_SPMU_BASE 0x60B4000ull +#define DCORE0_HMMU3_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_CS_SPMU_SECTION 0x1000 +#define mmDCORE0_HMMU3_BMON_CTI_BASE 0x60B5000ull +#define DCORE0_HMMU3_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_BMON_CTI_SECTION 0x1000 +#define mmDCORE0_HMMU3_USER_CTI_BASE 0x60B6000ull +#define DCORE0_HMMU3_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_USER_CTI_SECTION 0x1000 +#define mmDCORE0_HMMU3_BMON_0_BASE 0x60B7000ull +#define DCORE0_HMMU3_BMON_0_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_BMON_0_SECTION 0x1000 +#define mmDCORE0_HMMU3_BMON_1_BASE 0x60B8000ull +#define DCORE0_HMMU3_BMON_1_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_BMON_1_SECTION 0x1000 +#define mmDCORE0_HMMU3_BMON_3_BASE 0x60B9000ull +#define DCORE0_HMMU3_BMON_3_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_BMON_3_SECTION 0x1000 +#define mmDCORE0_HMMU3_BMON_2_BASE 0x60BA000ull +#define DCORE0_HMMU3_BMON_2_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_BMON_2_SECTION 0x1000 +#define mmDCORE0_HMMU3_BMON_4_BASE 0x60BB000ull +#define DCORE0_HMMU3_BMON_4_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_BMON_4_SECTION 0x5000 +#define mmDCORE0_MME_CTRL_ROM_TABLE_BASE 0x60C0000ull +#define DCORE0_MME_CTRL_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_ROM_TABLE_SECTION 0x1000 +#define mmDCORE0_MME_CTRL_STM_BASE 0x60C1000ull +#define DCORE0_MME_CTRL_STM_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_STM_SECTION 0x1000 +#define mmDCORE0_MME_CTRL_CTI_BASE 0x60C2000ull +#define DCORE0_MME_CTRL_CTI_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_CTI_SECTION 0x1000 +#define mmDCORE0_MME_CTRL_ETF_BASE 0x60C3000ull +#define DCORE0_MME_CTRL_ETF_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_ETF_SECTION 0x1000 +#define mmDCORE0_MME_CTRL_SPMU_BASE 0x60C4000ull +#define DCORE0_MME_CTRL_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_SPMU_SECTION 0x1000 +#define mmDCORE0_MME_CTRL_CTI0_BASE 0x60C5000ull +#define DCORE0_MME_CTRL_CTI0_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_CTI0_SECTION 0x1000 +#define mmDCORE0_MME_CTRL_CTI1_BASE 0x60C6000ull +#define DCORE0_MME_CTRL_CTI1_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_CTI1_SECTION 0x1000 +#define mmDCORE0_MME_CTRL_BMON0_BASE 0x60C7000ull +#define DCORE0_MME_CTRL_BMON0_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_BMON0_SECTION 0x1000 +#define mmDCORE0_MME_CTRL_BMON1_BASE 0x60C8000ull +#define DCORE0_MME_CTRL_BMON1_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_BMON1_SECTION 0x1000 +#define mmDCORE0_MME_CTRL_BMON2_BASE 0x60C9000ull +#define DCORE0_MME_CTRL_BMON2_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_BMON2_SECTION 0x1000 +#define mmDCORE0_MME_CTRL_BMON3_BASE 0x60CA000ull +#define DCORE0_MME_CTRL_BMON3_MAX_OFFSET 0x1000 +#define DCORE0_MME_CTRL_BMON3_SECTION 0x1000 +#define mmDCORE0_MME_CTRL_ARC_RTT_BASE 0x60CB000ull +#define DCORE0_MME_CTRL_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_MME_CTRL_ARC_RTT_SECTION 0x5000 +#define mmDCORE0_MME_SBTE0_ROM_TBL_BASE 0x60D0000ull +#define DCORE0_MME_SBTE0_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE0_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_MME_SBTE0_STM_BASE 0x60D1000ull +#define DCORE0_MME_SBTE0_STM_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE0_STM_SECTION 0x1000 +#define mmDCORE0_MME_SBTE0_CTI_BASE 0x60D2000ull +#define DCORE0_MME_SBTE0_CTI_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE0_CTI_SECTION 0x1000 +#define mmDCORE0_MME_SBTE0_ETF_BASE 0x60D3000ull +#define DCORE0_MME_SBTE0_ETF_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE0_ETF_SECTION 0x1000 +#define mmDCORE0_MME_SBTE0_SPMU_BASE 0x60D4000ull +#define DCORE0_MME_SBTE0_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE0_SPMU_SECTION 0x1000 +#define mmDCORE0_MME_SBTE0_CTI0_BASE 0x60D5000ull +#define DCORE0_MME_SBTE0_CTI0_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE0_CTI0_SECTION 0x1000 +#define mmDCORE0_MME_SBTE0_CTI1_BASE 0x60D6000ull +#define DCORE0_MME_SBTE0_CTI1_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE0_CTI1_SECTION 0x1000 +#define mmDCORE0_MME_SBTE0_BMON0_BASE 0x60D7000ull +#define DCORE0_MME_SBTE0_BMON0_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE0_BMON0_SECTION 0x1000 +#define mmDCORE0_MME_SBTE1_ROM_TBL_BASE 0x60D8000ull +#define DCORE0_MME_SBTE1_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE1_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_MME_SBTE1_STM_BASE 0x60D9000ull +#define DCORE0_MME_SBTE1_STM_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE1_STM_SECTION 0x1000 +#define mmDCORE0_MME_SBTE1_CTI_BASE 0x60DA000ull +#define DCORE0_MME_SBTE1_CTI_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE1_CTI_SECTION 0x1000 +#define mmDCORE0_MME_SBTE1_ETF_BASE 0x60DB000ull +#define DCORE0_MME_SBTE1_ETF_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE1_ETF_SECTION 0x1000 +#define mmDCORE0_MME_SBTE1_SPMU_BASE 0x60DC000ull +#define DCORE0_MME_SBTE1_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE1_SPMU_SECTION 0x1000 +#define mmDCORE0_MME_SBTE1_CTI0_BASE 0x60DD000ull +#define DCORE0_MME_SBTE1_CTI0_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE1_CTI0_SECTION 0x1000 +#define mmDCORE0_MME_SBTE1_CTI1_BASE 0x60DE000ull +#define DCORE0_MME_SBTE1_CTI1_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE1_CTI1_SECTION 0x1000 +#define mmDCORE0_MME_SBTE1_BMON0_BASE 0x60DF000ull +#define DCORE0_MME_SBTE1_BMON0_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE1_BMON0_SECTION 0x1000 +#define mmDCORE0_MME_SBTE2_ROM_TBL_BASE 0x60E0000ull +#define DCORE0_MME_SBTE2_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE2_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_MME_SBTE2_STM_BASE 0x60E1000ull +#define DCORE0_MME_SBTE2_STM_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE2_STM_SECTION 0x1000 +#define mmDCORE0_MME_SBTE2_CTI_BASE 0x60E2000ull +#define DCORE0_MME_SBTE2_CTI_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE2_CTI_SECTION 0x1000 +#define mmDCORE0_MME_SBTE2_ETF_BASE 0x60E3000ull +#define DCORE0_MME_SBTE2_ETF_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE2_ETF_SECTION 0x1000 +#define mmDCORE0_MME_SBTE2_SPMU_BASE 0x60E4000ull +#define DCORE0_MME_SBTE2_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE2_SPMU_SECTION 0x1000 +#define mmDCORE0_MME_SBTE2_CTI0_BASE 0x60E5000ull +#define DCORE0_MME_SBTE2_CTI0_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE2_CTI0_SECTION 0x1000 +#define mmDCORE0_MME_SBTE2_CTI1_BASE 0x60E6000ull +#define DCORE0_MME_SBTE2_CTI1_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE2_CTI1_SECTION 0x1000 +#define mmDCORE0_MME_SBTE2_BMON0_BASE 0x60E7000ull +#define DCORE0_MME_SBTE2_BMON0_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE2_BMON0_SECTION 0x1000 +#define mmDCORE0_MME_SBTE3_ROM_TBL_BASE 0x60E8000ull +#define DCORE0_MME_SBTE3_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE3_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_MME_SBTE3_STM_BASE 0x60E9000ull +#define DCORE0_MME_SBTE3_STM_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE3_STM_SECTION 0x1000 +#define mmDCORE0_MME_SBTE3_CTI_BASE 0x60EA000ull +#define DCORE0_MME_SBTE3_CTI_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE3_CTI_SECTION 0x1000 +#define mmDCORE0_MME_SBTE3_ETF_BASE 0x60EB000ull +#define DCORE0_MME_SBTE3_ETF_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE3_ETF_SECTION 0x1000 +#define mmDCORE0_MME_SBTE3_SPMU_BASE 0x60EC000ull +#define DCORE0_MME_SBTE3_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE3_SPMU_SECTION 0x1000 +#define mmDCORE0_MME_SBTE3_CTI0_BASE 0x60ED000ull +#define DCORE0_MME_SBTE3_CTI0_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE3_CTI0_SECTION 0x1000 +#define mmDCORE0_MME_SBTE3_CTI1_BASE 0x60EE000ull +#define DCORE0_MME_SBTE3_CTI1_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE3_CTI1_SECTION 0x1000 +#define mmDCORE0_MME_SBTE3_BMON0_BASE 0x60EF000ull +#define DCORE0_MME_SBTE3_BMON0_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE3_BMON0_SECTION 0x1000 +#define mmDCORE0_MME_SBTE4_ROM_TBL_BASE 0x60F0000ull +#define DCORE0_MME_SBTE4_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE4_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_MME_SBTE4_STM_BASE 0x60F1000ull +#define DCORE0_MME_SBTE4_STM_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE4_STM_SECTION 0x1000 +#define mmDCORE0_MME_SBTE4_CTI_BASE 0x60F2000ull +#define DCORE0_MME_SBTE4_CTI_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE4_CTI_SECTION 0x1000 +#define mmDCORE0_MME_SBTE4_ETF_BASE 0x60F3000ull +#define DCORE0_MME_SBTE4_ETF_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE4_ETF_SECTION 0x1000 +#define mmDCORE0_MME_SBTE4_SPMU_BASE 0x60F4000ull +#define DCORE0_MME_SBTE4_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE4_SPMU_SECTION 0x1000 +#define mmDCORE0_MME_SBTE4_CTI0_BASE 0x60F5000ull +#define DCORE0_MME_SBTE4_CTI0_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE4_CTI0_SECTION 0x1000 +#define mmDCORE0_MME_SBTE4_CTI1_BASE 0x60F6000ull +#define DCORE0_MME_SBTE4_CTI1_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE4_CTI1_SECTION 0x1000 +#define mmDCORE0_MME_SBTE4_BMON0_BASE 0x60F7000ull +#define DCORE0_MME_SBTE4_BMON0_MAX_OFFSET 0x1000 +#define DCORE0_MME_SBTE4_BMON0_SECTION 0x9000 +#define mmDCORE0_MME_ACC_CS_ROM_TBL_BASE 0x6100000ull +#define DCORE0_MME_ACC_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_MME_ACC_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_MME_ACC_STM_BASE 0x6101000ull +#define DCORE0_MME_ACC_STM_MAX_OFFSET 0x1000 +#define DCORE0_MME_ACC_STM_SECTION 0x1000 +#define mmDCORE0_MME_ACC_CTI_BASE 0x6102000ull +#define DCORE0_MME_ACC_CTI_MAX_OFFSET 0x1000 +#define DCORE0_MME_ACC_CTI_SECTION 0x1000 +#define mmDCORE0_MME_ACC_ETF_BASE 0x6103000ull +#define DCORE0_MME_ACC_ETF_MAX_OFFSET 0x1000 +#define DCORE0_MME_ACC_ETF_SECTION 0x1000 +#define mmDCORE0_MME_ACC_SPMU_BASE 0x6104000ull +#define DCORE0_MME_ACC_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_MME_ACC_SPMU_SECTION 0x1000 +#define mmDCORE0_MME_ACC_CTI0_BASE 0x6105000ull +#define DCORE0_MME_ACC_CTI0_MAX_OFFSET 0x1000 +#define DCORE0_MME_ACC_CTI0_SECTION 0x1000 +#define mmDCORE0_MME_ACC_CTI1_BASE 0x6106000ull +#define DCORE0_MME_ACC_CTI1_MAX_OFFSET 0x1000 +#define DCORE0_MME_ACC_CTI1_SECTION 0x1000 +#define mmDCORE0_MME_ACC_BMON0_BASE 0x6107000ull +#define DCORE0_MME_ACC_BMON0_MAX_OFFSET 0x1000 +#define DCORE0_MME_ACC_BMON0_SECTION 0x1000 +#define mmDCORE0_MME_ACC_BMON1_BASE 0x6108000ull +#define DCORE0_MME_ACC_BMON1_MAX_OFFSET 0x1000 +#define DCORE0_MME_ACC_BMON1_SECTION 0x8000 +#define mmDCORE0_SM_CS_DBG_ROM_TBL_BASE 0x6110000ull +#define DCORE0_SM_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_SM_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_SM_STM_BASE 0x6111000ull +#define DCORE0_SM_STM_MAX_OFFSET 0x1000 +#define DCORE0_SM_STM_SECTION 0x1000 +#define mmDCORE0_SM_CTI_BASE 0x6112000ull +#define DCORE0_SM_CTI_MAX_OFFSET 0x1000 +#define DCORE0_SM_CTI_SECTION 0x1000 +#define mmDCORE0_SM_ETF_BASE 0x6113000ull +#define DCORE0_SM_ETF_MAX_OFFSET 0x1000 +#define DCORE0_SM_ETF_SECTION 0x1000 +#define mmDCORE0_SM_SPMU_BASE 0x6114000ull +#define DCORE0_SM_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_SM_SPMU_SECTION 0x1000 +#define mmDCORE0_SM_BMON_CTI_BASE 0x6115000ull +#define DCORE0_SM_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_SM_BMON_CTI_SECTION 0x1000 +#define mmDCORE0_SM_USER_CTI_BASE 0x6116000ull +#define DCORE0_SM_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_SM_USER_CTI_SECTION 0x1000 +#define mmDCORE0_SM_BMON_BASE 0x6117000ull +#define DCORE0_SM_BMON_MAX_OFFSET 0x1000 +#define DCORE0_SM_BMON_SECTION 0x1000 +#define mmDCORE0_SM_BMON1_BASE 0x6118000ull +#define DCORE0_SM_BMON1_MAX_OFFSET 0x1000 +#define DCORE0_SM_BMON1_SECTION 0x18000 +#define mmDCORE0_XFT_FUNNEL_BASE 0x6130000ull +#define DCORE0_XFT_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_XFT_FUNNEL_SECTION 0x8000 +#define mmDCORE0_TFT0_FUNNEL_BASE 0x6138000ull +#define DCORE0_TFT0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TFT0_FUNNEL_SECTION 0x1000 +#define mmDCORE0_TFT1_FUNNEL_BASE 0x6139000ull +#define DCORE0_TFT1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TFT1_FUNNEL_SECTION 0x1000 +#define mmDCORE0_TFT2_FUNNEL_BASE 0x613A000ull +#define DCORE0_TFT2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TFT2_FUNNEL_SECTION 0x7000 +#define mmDCORE0_RTR0_FUNNEL_BASE 0x6141000ull +#define DCORE0_RTR0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_RTR0_FUNNEL_SECTION 0x8000 +#define mmDCORE0_RTR1_FUNNEL_BASE 0x6149000ull +#define DCORE0_RTR1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_RTR1_FUNNEL_SECTION 0x8000 +#define mmDCORE0_RTR2_FUNNEL_BASE 0x6151000ull +#define DCORE0_RTR2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_RTR2_FUNNEL_SECTION 0x8000 +#define mmDCORE0_RTR3_FUNNEL_BASE 0x6159000ull +#define DCORE0_RTR3_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_RTR3_FUNNEL_SECTION 0x8000 +#define mmDCORE0_RTR4_FUNNEL_BASE 0x6161000ull +#define DCORE0_RTR4_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_RTR4_FUNNEL_SECTION 0x4000 +#define mmDCORE0_MIF0_FUNNEL_BASE 0x6165000ull +#define DCORE0_MIF0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_MIF0_FUNNEL_SECTION 0x4000 +#define mmDCORE0_RTR5_FUNNEL_BASE 0x6169000ull +#define DCORE0_RTR5_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_RTR5_FUNNEL_SECTION 0x4000 +#define mmDCORE0_MIF1_FUNNEL_BASE 0x616D000ull +#define DCORE0_MIF1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_MIF1_FUNNEL_SECTION 0x4000 +#define mmDCORE0_RTR6_FUNNEL_BASE 0x6171000ull +#define DCORE0_RTR6_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_RTR6_FUNNEL_SECTION 0x4000 +#define mmDCORE0_MIF2_FUNNEL_BASE 0x6175000ull +#define DCORE0_MIF2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_MIF2_FUNNEL_SECTION 0x4000 +#define mmDCORE0_RTR7_FUNNEL_BASE 0x6179000ull +#define DCORE0_RTR7_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_RTR7_FUNNEL_SECTION 0x4000 +#define mmDCORE0_MIF3_FUNNEL_BASE 0x617D000ull +#define DCORE0_MIF3_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_MIF3_FUNNEL_SECTION 0x43000 +#define mmDCORE0_EDMA0_CS_ROM_TBL_BASE 0x61C0000ull +#define DCORE0_EDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_EDMA0_CS_STM_BASE 0x61C1000ull +#define DCORE0_EDMA0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_CS_STM_SECTION 0x1000 +#define mmDCORE0_EDMA0_CS_CTI_BASE 0x61C2000ull +#define DCORE0_EDMA0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_CS_CTI_SECTION 0x1000 +#define mmDCORE0_EDMA0_CS_ETF_BASE 0x61C3000ull +#define DCORE0_EDMA0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_CS_ETF_SECTION 0x1000 +#define mmDCORE0_EDMA0_CS_SPMU_BASE 0x61C4000ull +#define DCORE0_EDMA0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_CS_SPMU_SECTION 0x1000 +#define mmDCORE0_EDMA0_BMON_CTI_BASE 0x61C5000ull +#define DCORE0_EDMA0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_BMON_CTI_SECTION 0x1000 +#define mmDCORE0_EDMA0_USER_CTI_BASE 0x61C6000ull +#define DCORE0_EDMA0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_USER_CTI_SECTION 0x1000 +#define mmDCORE0_EDMA0_BMON_0_BASE 0x61C7000ull +#define DCORE0_EDMA0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_BMON_0_SECTION 0x1000 +#define mmDCORE0_EDMA0_BMON_1_BASE 0x61C8000ull +#define DCORE0_EDMA0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_BMON_1_SECTION 0x1000 +#define mmDCORE0_EDMA0_QM_ARC_RTT_BASE 0x61C9000ull +#define DCORE0_EDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_EDMA0_QM_ARC_RTT_SECTION 0x7000 +#define mmDCORE0_EDMA1_CS_ROM_TBL_BASE 0x61D0000ull +#define DCORE0_EDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_EDMA1_CS_STM_BASE 0x61D1000ull +#define DCORE0_EDMA1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_CS_STM_SECTION 0x1000 +#define mmDCORE0_EDMA1_CS_CTI_BASE 0x61D2000ull +#define DCORE0_EDMA1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_CS_CTI_SECTION 0x1000 +#define mmDCORE0_EDMA1_CS_ETF_BASE 0x61D3000ull +#define DCORE0_EDMA1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_CS_ETF_SECTION 0x1000 +#define mmDCORE0_EDMA1_CS_SPMU_BASE 0x61D4000ull +#define DCORE0_EDMA1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_CS_SPMU_SECTION 0x1000 +#define mmDCORE0_EDMA1_BMON_CTI_BASE 0x61D5000ull +#define DCORE0_EDMA1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_BMON_CTI_SECTION 0x1000 +#define mmDCORE0_EDMA1_USER_CTI_BASE 0x61D6000ull +#define DCORE0_EDMA1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_USER_CTI_SECTION 0x1000 +#define mmDCORE0_EDMA1_BMON_0_BASE 0x61D7000ull +#define DCORE0_EDMA1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_BMON_0_SECTION 0x1000 +#define mmDCORE0_EDMA1_BMON_1_BASE 0x61D8000ull +#define DCORE0_EDMA1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_BMON_1_SECTION 0x1000 +#define mmDCORE0_EDMA1_QM_ARC_RTT_BASE 0x61D9000ull +#define DCORE0_EDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_EDMA1_QM_ARC_RTT_SECTION 0x7000 +#define mmDCORE0_VDEC0_CS_ROM_TBL_BASE 0x61E0000ull +#define DCORE0_VDEC0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_VDEC0_CS_STM_BASE 0x61E1000ull +#define DCORE0_VDEC0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_CS_STM_SECTION 0x1000 +#define mmDCORE0_VDEC0_CS_CTI_BASE 0x61E2000ull +#define DCORE0_VDEC0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_CS_CTI_SECTION 0x1000 +#define mmDCORE0_VDEC0_CS_ETF_BASE 0x61E3000ull +#define DCORE0_VDEC0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_CS_ETF_SECTION 0x1000 +#define mmDCORE0_VDEC0_CS_SPMU_BASE 0x61E4000ull +#define DCORE0_VDEC0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_CS_SPMU_SECTION 0x1000 +#define mmDCORE0_VDEC0_BMON_CTI_BASE 0x61E5000ull +#define DCORE0_VDEC0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_BMON_CTI_SECTION 0x1000 +#define mmDCORE0_VDEC0_USER_CTI_BASE 0x61E6000ull +#define DCORE0_VDEC0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_USER_CTI_SECTION 0x1000 +#define mmDCORE0_VDEC0_BMON_0_BASE 0x61E7000ull +#define DCORE0_VDEC0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_BMON_0_SECTION 0x1000 +#define mmDCORE0_VDEC0_BMON_1_BASE 0x61E8000ull +#define DCORE0_VDEC0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_BMON_1_SECTION 0x1000 +#define mmDCORE0_VDEC0_BMON_2_BASE 0x61E9000ull +#define DCORE0_VDEC0_BMON_2_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_BMON_2_SECTION 0x7000 +#define mmDCORE0_VDEC1_CS_ROM_TBL_BASE 0x61F0000ull +#define DCORE0_VDEC1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE0_VDEC1_CS_STM_BASE 0x61F1000ull +#define DCORE0_VDEC1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_CS_STM_SECTION 0x1000 +#define mmDCORE0_VDEC1_CS_CTI_BASE 0x61F2000ull +#define DCORE0_VDEC1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_CS_CTI_SECTION 0x1000 +#define mmDCORE0_VDEC1_CS_ETF_BASE 0x61F3000ull +#define DCORE0_VDEC1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_CS_ETF_SECTION 0x1000 +#define mmDCORE0_VDEC1_CS_SPMU_BASE 0x61F4000ull +#define DCORE0_VDEC1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_CS_SPMU_SECTION 0x1000 +#define mmDCORE0_VDEC1_BMON_CTI_BASE 0x61F5000ull +#define DCORE0_VDEC1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_BMON_CTI_SECTION 0x1000 +#define mmDCORE0_VDEC1_USER_CTI_BASE 0x61F6000ull +#define DCORE0_VDEC1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_USER_CTI_SECTION 0x1000 +#define mmDCORE0_VDEC1_BMON_0_BASE 0x61F7000ull +#define DCORE0_VDEC1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_BMON_0_SECTION 0x1000 +#define mmDCORE0_VDEC1_BMON_1_BASE 0x61F8000ull +#define DCORE0_VDEC1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_BMON_1_SECTION 0x1000 +#define mmDCORE0_VDEC1_BMON_2_BASE 0x61F9000ull +#define DCORE0_VDEC1_BMON_2_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_BMON_2_SECTION 0x7000 +#define mmDCORE1_ROM_TABLE_L_BASE 0x6200000ull +#define DCORE1_ROM_TABLE_L_MAX_OFFSET 0x1000 +#define DCORE1_ROM_TABLE_L_SECTION 0x80000 +#define mmDCORE1_HMMU0_CS_ROM_TBL_BASE 0x6280000ull +#define DCORE1_HMMU0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_HMMU0_CS_STM_BASE 0x6281000ull +#define DCORE1_HMMU0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_CS_STM_SECTION 0x1000 +#define mmDCORE1_HMMU0_CS_CTI_BASE 0x6282000ull +#define DCORE1_HMMU0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_CS_CTI_SECTION 0x1000 +#define mmDCORE1_HMMU0_CS_ETF_BASE 0x6283000ull +#define DCORE1_HMMU0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_CS_ETF_SECTION 0x1000 +#define mmDCORE1_HMMU0_CS_SPMU_BASE 0x6284000ull +#define DCORE1_HMMU0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_CS_SPMU_SECTION 0x1000 +#define mmDCORE1_HMMU0_BMON_CTI_BASE 0x6285000ull +#define DCORE1_HMMU0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_BMON_CTI_SECTION 0x1000 +#define mmDCORE1_HMMU0_USER_CTI_BASE 0x6286000ull +#define DCORE1_HMMU0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_USER_CTI_SECTION 0x1000 +#define mmDCORE1_HMMU0_BMON_0_BASE 0x6287000ull +#define DCORE1_HMMU0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_BMON_0_SECTION 0x1000 +#define mmDCORE1_HMMU0_BMON_1_BASE 0x6288000ull +#define DCORE1_HMMU0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_BMON_1_SECTION 0x1000 +#define mmDCORE1_HMMU0_BMON_3_BASE 0x6289000ull +#define DCORE1_HMMU0_BMON_3_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_BMON_3_SECTION 0x1000 +#define mmDCORE1_HMMU0_BMON_2_BASE 0x628A000ull +#define DCORE1_HMMU0_BMON_2_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_BMON_2_SECTION 0x1000 +#define mmDCORE1_HMMU0_BMON_4_BASE 0x628B000ull +#define DCORE1_HMMU0_BMON_4_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_BMON_4_SECTION 0x5000 +#define mmDCORE1_HMMU1_CS_ROM_TBL_BASE 0x6290000ull +#define DCORE1_HMMU1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_HMMU1_CS_STM_BASE 0x6291000ull +#define DCORE1_HMMU1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_CS_STM_SECTION 0x1000 +#define mmDCORE1_HMMU1_CS_CTI_BASE 0x6292000ull +#define DCORE1_HMMU1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_CS_CTI_SECTION 0x1000 +#define mmDCORE1_HMMU1_CS_ETF_BASE 0x6293000ull +#define DCORE1_HMMU1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_CS_ETF_SECTION 0x1000 +#define mmDCORE1_HMMU1_CS_SPMU_BASE 0x6294000ull +#define DCORE1_HMMU1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_CS_SPMU_SECTION 0x1000 +#define mmDCORE1_HMMU1_BMON_CTI_BASE 0x6295000ull +#define DCORE1_HMMU1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_BMON_CTI_SECTION 0x1000 +#define mmDCORE1_HMMU1_USER_CTI_BASE 0x6296000ull +#define DCORE1_HMMU1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_USER_CTI_SECTION 0x1000 +#define mmDCORE1_HMMU1_BMON_0_BASE 0x6297000ull +#define DCORE1_HMMU1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_BMON_0_SECTION 0x1000 +#define mmDCORE1_HMMU1_BMON_1_BASE 0x6298000ull +#define DCORE1_HMMU1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_BMON_1_SECTION 0x1000 +#define mmDCORE1_HMMU1_BMON_3_BASE 0x6299000ull +#define DCORE1_HMMU1_BMON_3_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_BMON_3_SECTION 0x1000 +#define mmDCORE1_HMMU1_BMON_2_BASE 0x629A000ull +#define DCORE1_HMMU1_BMON_2_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_BMON_2_SECTION 0x1000 +#define mmDCORE1_HMMU1_BMON_4_BASE 0x629B000ull +#define DCORE1_HMMU1_BMON_4_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_BMON_4_SECTION 0x5000 +#define mmDCORE1_HMMU2_CS_ROM_TBL_BASE 0x62A0000ull +#define DCORE1_HMMU2_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_HMMU2_CS_STM_BASE 0x62A1000ull +#define DCORE1_HMMU2_CS_STM_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_CS_STM_SECTION 0x1000 +#define mmDCORE1_HMMU2_CS_CTI_BASE 0x62A2000ull +#define DCORE1_HMMU2_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_CS_CTI_SECTION 0x1000 +#define mmDCORE1_HMMU2_CS_ETF_BASE 0x62A3000ull +#define DCORE1_HMMU2_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_CS_ETF_SECTION 0x1000 +#define mmDCORE1_HMMU2_CS_SPMU_BASE 0x62A4000ull +#define DCORE1_HMMU2_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_CS_SPMU_SECTION 0x1000 +#define mmDCORE1_HMMU2_BMON_CTI_BASE 0x62A5000ull +#define DCORE1_HMMU2_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_BMON_CTI_SECTION 0x1000 +#define mmDCORE1_HMMU2_USER_CTI_BASE 0x62A6000ull +#define DCORE1_HMMU2_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_USER_CTI_SECTION 0x1000 +#define mmDCORE1_HMMU2_BMON_0_BASE 0x62A7000ull +#define DCORE1_HMMU2_BMON_0_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_BMON_0_SECTION 0x1000 +#define mmDCORE1_HMMU2_BMON_1_BASE 0x62A8000ull +#define DCORE1_HMMU2_BMON_1_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_BMON_1_SECTION 0x1000 +#define mmDCORE1_HMMU2_BMON_3_BASE 0x62A9000ull +#define DCORE1_HMMU2_BMON_3_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_BMON_3_SECTION 0x1000 +#define mmDCORE1_HMMU2_BMON_2_BASE 0x62AA000ull +#define DCORE1_HMMU2_BMON_2_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_BMON_2_SECTION 0x1000 +#define mmDCORE1_HMMU2_BMON_4_BASE 0x62AB000ull +#define DCORE1_HMMU2_BMON_4_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_BMON_4_SECTION 0x5000 +#define mmDCORE1_HMMU3_CS_ROM_TBL_BASE 0x62B0000ull +#define DCORE1_HMMU3_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_HMMU3_CS_STM_BASE 0x62B1000ull +#define DCORE1_HMMU3_CS_STM_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_CS_STM_SECTION 0x1000 +#define mmDCORE1_HMMU3_CS_CTI_BASE 0x62B2000ull +#define DCORE1_HMMU3_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_CS_CTI_SECTION 0x1000 +#define mmDCORE1_HMMU3_CS_ETF_BASE 0x62B3000ull +#define DCORE1_HMMU3_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_CS_ETF_SECTION 0x1000 +#define mmDCORE1_HMMU3_CS_SPMU_BASE 0x62B4000ull +#define DCORE1_HMMU3_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_CS_SPMU_SECTION 0x1000 +#define mmDCORE1_HMMU3_BMON_CTI_BASE 0x62B5000ull +#define DCORE1_HMMU3_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_BMON_CTI_SECTION 0x1000 +#define mmDCORE1_HMMU3_USER_CTI_BASE 0x62B6000ull +#define DCORE1_HMMU3_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_USER_CTI_SECTION 0x1000 +#define mmDCORE1_HMMU3_BMON_0_BASE 0x62B7000ull +#define DCORE1_HMMU3_BMON_0_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_BMON_0_SECTION 0x1000 +#define mmDCORE1_HMMU3_BMON_1_BASE 0x62B8000ull +#define DCORE1_HMMU3_BMON_1_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_BMON_1_SECTION 0x1000 +#define mmDCORE1_HMMU3_BMON_3_BASE 0x62B9000ull +#define DCORE1_HMMU3_BMON_3_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_BMON_3_SECTION 0x1000 +#define mmDCORE1_HMMU3_BMON_2_BASE 0x62BA000ull +#define DCORE1_HMMU3_BMON_2_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_BMON_2_SECTION 0x1000 +#define mmDCORE1_HMMU3_BMON_4_BASE 0x62BB000ull +#define DCORE1_HMMU3_BMON_4_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_BMON_4_SECTION 0x5000 +#define mmDCORE1_MME_CTRL_ROM_TABLE_BASE 0x62C0000ull +#define DCORE1_MME_CTRL_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_ROM_TABLE_SECTION 0x1000 +#define mmDCORE1_MME_CTRL_STM_BASE 0x62C1000ull +#define DCORE1_MME_CTRL_STM_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_STM_SECTION 0x1000 +#define mmDCORE1_MME_CTRL_CTI_BASE 0x62C2000ull +#define DCORE1_MME_CTRL_CTI_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_CTI_SECTION 0x1000 +#define mmDCORE1_MME_CTRL_ETF_BASE 0x62C3000ull +#define DCORE1_MME_CTRL_ETF_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_ETF_SECTION 0x1000 +#define mmDCORE1_MME_CTRL_SPMU_BASE 0x62C4000ull +#define DCORE1_MME_CTRL_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_SPMU_SECTION 0x1000 +#define mmDCORE1_MME_CTRL_CTI0_BASE 0x62C5000ull +#define DCORE1_MME_CTRL_CTI0_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_CTI0_SECTION 0x1000 +#define mmDCORE1_MME_CTRL_CTI1_BASE 0x62C6000ull +#define DCORE1_MME_CTRL_CTI1_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_CTI1_SECTION 0x1000 +#define mmDCORE1_MME_CTRL_BMON0_BASE 0x62C7000ull +#define DCORE1_MME_CTRL_BMON0_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_BMON0_SECTION 0x1000 +#define mmDCORE1_MME_CTRL_BMON1_BASE 0x62C8000ull +#define DCORE1_MME_CTRL_BMON1_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_BMON1_SECTION 0x1000 +#define mmDCORE1_MME_CTRL_BMON2_BASE 0x62C9000ull +#define DCORE1_MME_CTRL_BMON2_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_BMON2_SECTION 0x1000 +#define mmDCORE1_MME_CTRL_BMON3_BASE 0x62CA000ull +#define DCORE1_MME_CTRL_BMON3_MAX_OFFSET 0x1000 +#define DCORE1_MME_CTRL_BMON3_SECTION 0x1000 +#define mmDCORE1_MME_CTRL_ARC_RTT_BASE 0x62CB000ull +#define DCORE1_MME_CTRL_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_MME_CTRL_ARC_RTT_SECTION 0x5000 +#define mmDCORE1_MME_SBTE0_ROM_TBL_BASE 0x62D0000ull +#define DCORE1_MME_SBTE0_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE0_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_MME_SBTE0_STM_BASE 0x62D1000ull +#define DCORE1_MME_SBTE0_STM_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE0_STM_SECTION 0x1000 +#define mmDCORE1_MME_SBTE0_CTI_BASE 0x62D2000ull +#define DCORE1_MME_SBTE0_CTI_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE0_CTI_SECTION 0x1000 +#define mmDCORE1_MME_SBTE0_ETF_BASE 0x62D3000ull +#define DCORE1_MME_SBTE0_ETF_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE0_ETF_SECTION 0x1000 +#define mmDCORE1_MME_SBTE0_SPMU_BASE 0x62D4000ull +#define DCORE1_MME_SBTE0_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE0_SPMU_SECTION 0x1000 +#define mmDCORE1_MME_SBTE0_CTI0_BASE 0x62D5000ull +#define DCORE1_MME_SBTE0_CTI0_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE0_CTI0_SECTION 0x1000 +#define mmDCORE1_MME_SBTE0_CTI1_BASE 0x62D6000ull +#define DCORE1_MME_SBTE0_CTI1_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE0_CTI1_SECTION 0x1000 +#define mmDCORE1_MME_SBTE0_BMON0_BASE 0x62D7000ull +#define DCORE1_MME_SBTE0_BMON0_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE0_BMON0_SECTION 0x1000 +#define mmDCORE1_MME_SBTE1_ROM_TBL_BASE 0x62D8000ull +#define DCORE1_MME_SBTE1_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE1_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_MME_SBTE1_STM_BASE 0x62D9000ull +#define DCORE1_MME_SBTE1_STM_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE1_STM_SECTION 0x1000 +#define mmDCORE1_MME_SBTE1_CTI_BASE 0x62DA000ull +#define DCORE1_MME_SBTE1_CTI_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE1_CTI_SECTION 0x1000 +#define mmDCORE1_MME_SBTE1_ETF_BASE 0x62DB000ull +#define DCORE1_MME_SBTE1_ETF_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE1_ETF_SECTION 0x1000 +#define mmDCORE1_MME_SBTE1_SPMU_BASE 0x62DC000ull +#define DCORE1_MME_SBTE1_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE1_SPMU_SECTION 0x1000 +#define mmDCORE1_MME_SBTE1_CTI0_BASE 0x62DD000ull +#define DCORE1_MME_SBTE1_CTI0_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE1_CTI0_SECTION 0x1000 +#define mmDCORE1_MME_SBTE1_CTI1_BASE 0x62DE000ull +#define DCORE1_MME_SBTE1_CTI1_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE1_CTI1_SECTION 0x1000 +#define mmDCORE1_MME_SBTE1_BMON0_BASE 0x62DF000ull +#define DCORE1_MME_SBTE1_BMON0_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE1_BMON0_SECTION 0x1000 +#define mmDCORE1_MME_SBTE2_ROM_TBL_BASE 0x62E0000ull +#define DCORE1_MME_SBTE2_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE2_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_MME_SBTE2_STM_BASE 0x62E1000ull +#define DCORE1_MME_SBTE2_STM_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE2_STM_SECTION 0x1000 +#define mmDCORE1_MME_SBTE2_CTI_BASE 0x62E2000ull +#define DCORE1_MME_SBTE2_CTI_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE2_CTI_SECTION 0x1000 +#define mmDCORE1_MME_SBTE2_ETF_BASE 0x62E3000ull +#define DCORE1_MME_SBTE2_ETF_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE2_ETF_SECTION 0x1000 +#define mmDCORE1_MME_SBTE2_SPMU_BASE 0x62E4000ull +#define DCORE1_MME_SBTE2_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE2_SPMU_SECTION 0x1000 +#define mmDCORE1_MME_SBTE2_CTI0_BASE 0x62E5000ull +#define DCORE1_MME_SBTE2_CTI0_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE2_CTI0_SECTION 0x1000 +#define mmDCORE1_MME_SBTE2_CTI1_BASE 0x62E6000ull +#define DCORE1_MME_SBTE2_CTI1_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE2_CTI1_SECTION 0x1000 +#define mmDCORE1_MME_SBTE2_BMON0_BASE 0x62E7000ull +#define DCORE1_MME_SBTE2_BMON0_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE2_BMON0_SECTION 0x1000 +#define mmDCORE1_MME_SBTE3_ROM_TBL_BASE 0x62E8000ull +#define DCORE1_MME_SBTE3_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE3_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_MME_SBTE3_STM_BASE 0x62E9000ull +#define DCORE1_MME_SBTE3_STM_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE3_STM_SECTION 0x1000 +#define mmDCORE1_MME_SBTE3_CTI_BASE 0x62EA000ull +#define DCORE1_MME_SBTE3_CTI_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE3_CTI_SECTION 0x1000 +#define mmDCORE1_MME_SBTE3_ETF_BASE 0x62EB000ull +#define DCORE1_MME_SBTE3_ETF_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE3_ETF_SECTION 0x1000 +#define mmDCORE1_MME_SBTE3_SPMU_BASE 0x62EC000ull +#define DCORE1_MME_SBTE3_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE3_SPMU_SECTION 0x1000 +#define mmDCORE1_MME_SBTE3_CTI0_BASE 0x62ED000ull +#define DCORE1_MME_SBTE3_CTI0_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE3_CTI0_SECTION 0x1000 +#define mmDCORE1_MME_SBTE3_CTI1_BASE 0x62EE000ull +#define DCORE1_MME_SBTE3_CTI1_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE3_CTI1_SECTION 0x1000 +#define mmDCORE1_MME_SBTE3_BMON0_BASE 0x62EF000ull +#define DCORE1_MME_SBTE3_BMON0_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE3_BMON0_SECTION 0x1000 +#define mmDCORE1_MME_SBTE4_ROM_TBL_BASE 0x62F0000ull +#define DCORE1_MME_SBTE4_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE4_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_MME_SBTE4_STM_BASE 0x62F1000ull +#define DCORE1_MME_SBTE4_STM_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE4_STM_SECTION 0x1000 +#define mmDCORE1_MME_SBTE4_CTI_BASE 0x62F2000ull +#define DCORE1_MME_SBTE4_CTI_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE4_CTI_SECTION 0x1000 +#define mmDCORE1_MME_SBTE4_ETF_BASE 0x62F3000ull +#define DCORE1_MME_SBTE4_ETF_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE4_ETF_SECTION 0x1000 +#define mmDCORE1_MME_SBTE4_SPMU_BASE 0x62F4000ull +#define DCORE1_MME_SBTE4_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE4_SPMU_SECTION 0x1000 +#define mmDCORE1_MME_SBTE4_CTI0_BASE 0x62F5000ull +#define DCORE1_MME_SBTE4_CTI0_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE4_CTI0_SECTION 0x1000 +#define mmDCORE1_MME_SBTE4_CTI1_BASE 0x62F6000ull +#define DCORE1_MME_SBTE4_CTI1_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE4_CTI1_SECTION 0x1000 +#define mmDCORE1_MME_SBTE4_BMON0_BASE 0x62F7000ull +#define DCORE1_MME_SBTE4_BMON0_MAX_OFFSET 0x1000 +#define DCORE1_MME_SBTE4_BMON0_SECTION 0x9000 +#define mmDCORE1_MME_ACC_CS_ROM_TBL_BASE 0x6300000ull +#define DCORE1_MME_ACC_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_MME_ACC_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_MME_ACC_STM_BASE 0x6301000ull +#define DCORE1_MME_ACC_STM_MAX_OFFSET 0x1000 +#define DCORE1_MME_ACC_STM_SECTION 0x1000 +#define mmDCORE1_MME_ACC_CTI_BASE 0x6302000ull +#define DCORE1_MME_ACC_CTI_MAX_OFFSET 0x1000 +#define DCORE1_MME_ACC_CTI_SECTION 0x1000 +#define mmDCORE1_MME_ACC_ETF_BASE 0x6303000ull +#define DCORE1_MME_ACC_ETF_MAX_OFFSET 0x1000 +#define DCORE1_MME_ACC_ETF_SECTION 0x1000 +#define mmDCORE1_MME_ACC_SPMU_BASE 0x6304000ull +#define DCORE1_MME_ACC_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_MME_ACC_SPMU_SECTION 0x1000 +#define mmDCORE1_MME_ACC_CTI0_BASE 0x6305000ull +#define DCORE1_MME_ACC_CTI0_MAX_OFFSET 0x1000 +#define DCORE1_MME_ACC_CTI0_SECTION 0x1000 +#define mmDCORE1_MME_ACC_CTI1_BASE 0x6306000ull +#define DCORE1_MME_ACC_CTI1_MAX_OFFSET 0x1000 +#define DCORE1_MME_ACC_CTI1_SECTION 0x1000 +#define mmDCORE1_MME_ACC_BMON0_BASE 0x6307000ull +#define DCORE1_MME_ACC_BMON0_MAX_OFFSET 0x1000 +#define DCORE1_MME_ACC_BMON0_SECTION 0x1000 +#define mmDCORE1_MME_ACC_BMON1_BASE 0x6308000ull +#define DCORE1_MME_ACC_BMON1_MAX_OFFSET 0x1000 +#define DCORE1_MME_ACC_BMON1_SECTION 0x8000 +#define mmDCORE1_SM_CS_DBG_ROM_TBL_BASE 0x6310000ull +#define DCORE1_SM_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_SM_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_SM_STM_BASE 0x6311000ull +#define DCORE1_SM_STM_MAX_OFFSET 0x1000 +#define DCORE1_SM_STM_SECTION 0x1000 +#define mmDCORE1_SM_CTI_BASE 0x6312000ull +#define DCORE1_SM_CTI_MAX_OFFSET 0x1000 +#define DCORE1_SM_CTI_SECTION 0x1000 +#define mmDCORE1_SM_ETF_BASE 0x6313000ull +#define DCORE1_SM_ETF_MAX_OFFSET 0x1000 +#define DCORE1_SM_ETF_SECTION 0x1000 +#define mmDCORE1_SM_SPMU_BASE 0x6314000ull +#define DCORE1_SM_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_SM_SPMU_SECTION 0x1000 +#define mmDCORE1_SM_BMON_CTI_BASE 0x6315000ull +#define DCORE1_SM_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_SM_BMON_CTI_SECTION 0x1000 +#define mmDCORE1_SM_USER_CTI_BASE 0x6316000ull +#define DCORE1_SM_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_SM_USER_CTI_SECTION 0x1000 +#define mmDCORE1_SM_BMON_BASE 0x6317000ull +#define DCORE1_SM_BMON_MAX_OFFSET 0x1000 +#define DCORE1_SM_BMON_SECTION 0x1000 +#define mmDCORE1_SM_BMON1_BASE 0x6318000ull +#define DCORE1_SM_BMON1_MAX_OFFSET 0x1000 +#define DCORE1_SM_BMON1_SECTION 0x18000 +#define mmDCORE1_XFT_FUNNEL_BASE 0x6330000ull +#define DCORE1_XFT_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_XFT_FUNNEL_SECTION 0x8000 +#define mmDCORE1_TFT0_FUNNEL_BASE 0x6338000ull +#define DCORE1_TFT0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TFT0_FUNNEL_SECTION 0x1000 +#define mmDCORE1_TFT1_FUNNEL_BASE 0x6339000ull +#define DCORE1_TFT1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TFT1_FUNNEL_SECTION 0x1000 +#define mmDCORE1_TFT2_FUNNEL_BASE 0x633A000ull +#define DCORE1_TFT2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TFT2_FUNNEL_SECTION 0x7000 +#define mmDCORE1_RTR0_FUNNEL_BASE 0x6341000ull +#define DCORE1_RTR0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_RTR0_FUNNEL_SECTION 0x4000 +#define mmDCORE1_MIF0_FUNNEL_BASE 0x6345000ull +#define DCORE1_MIF0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_MIF0_FUNNEL_SECTION 0x4000 +#define mmDCORE1_RTR1_FUNNEL_BASE 0x6349000ull +#define DCORE1_RTR1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_RTR1_FUNNEL_SECTION 0x4000 +#define mmDCORE1_MIF1_FUNNEL_BASE 0x634D000ull +#define DCORE1_MIF1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_MIF1_FUNNEL_SECTION 0x4000 +#define mmDCORE1_RTR2_FUNNEL_BASE 0x6351000ull +#define DCORE1_RTR2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_RTR2_FUNNEL_SECTION 0x4000 +#define mmDCORE1_MIF2_FUNNEL_BASE 0x6355000ull +#define DCORE1_MIF2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_MIF2_FUNNEL_SECTION 0x4000 +#define mmDCORE1_RTR3_FUNNEL_BASE 0x6359000ull +#define DCORE1_RTR3_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_RTR3_FUNNEL_SECTION 0x4000 +#define mmDCORE1_MIF3_FUNNEL_BASE 0x635D000ull +#define DCORE1_MIF3_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_MIF3_FUNNEL_SECTION 0x4000 +#define mmDCORE1_RTR4_FUNNEL_BASE 0x6361000ull +#define DCORE1_RTR4_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_RTR4_FUNNEL_SECTION 0x8000 +#define mmDCORE1_RTR5_FUNNEL_BASE 0x6369000ull +#define DCORE1_RTR5_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_RTR5_FUNNEL_SECTION 0x8000 +#define mmDCORE1_RTR6_FUNNEL_BASE 0x6371000ull +#define DCORE1_RTR6_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_RTR6_FUNNEL_SECTION 0x8000 +#define mmDCORE1_RTR7_FUNNEL_BASE 0x6379000ull +#define DCORE1_RTR7_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_RTR7_FUNNEL_SECTION 0x47000 +#define mmDCORE1_EDMA0_CS_ROM_TBL_BASE 0x63C0000ull +#define DCORE1_EDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_EDMA0_CS_STM_BASE 0x63C1000ull +#define DCORE1_EDMA0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_CS_STM_SECTION 0x1000 +#define mmDCORE1_EDMA0_CS_CTI_BASE 0x63C2000ull +#define DCORE1_EDMA0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_CS_CTI_SECTION 0x1000 +#define mmDCORE1_EDMA0_CS_ETF_BASE 0x63C3000ull +#define DCORE1_EDMA0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_CS_ETF_SECTION 0x1000 +#define mmDCORE1_EDMA0_CS_SPMU_BASE 0x63C4000ull +#define DCORE1_EDMA0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_CS_SPMU_SECTION 0x1000 +#define mmDCORE1_EDMA0_BMON_CTI_BASE 0x63C5000ull +#define DCORE1_EDMA0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_BMON_CTI_SECTION 0x1000 +#define mmDCORE1_EDMA0_USER_CTI_BASE 0x63C6000ull +#define DCORE1_EDMA0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_USER_CTI_SECTION 0x1000 +#define mmDCORE1_EDMA0_BMON_0_BASE 0x63C7000ull +#define DCORE1_EDMA0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_BMON_0_SECTION 0x1000 +#define mmDCORE1_EDMA0_BMON_1_BASE 0x63C8000ull +#define DCORE1_EDMA0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_BMON_1_SECTION 0x1000 +#define mmDCORE1_EDMA0_QM_ARC_RTT_BASE 0x63C9000ull +#define DCORE1_EDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_EDMA0_QM_ARC_RTT_SECTION 0x7000 +#define mmDCORE1_EDMA1_CS_ROM_TBL_BASE 0x63D0000ull +#define DCORE1_EDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_EDMA1_CS_STM_BASE 0x63D1000ull +#define DCORE1_EDMA1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_CS_STM_SECTION 0x1000 +#define mmDCORE1_EDMA1_CS_CTI_BASE 0x63D2000ull +#define DCORE1_EDMA1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_CS_CTI_SECTION 0x1000 +#define mmDCORE1_EDMA1_CS_ETF_BASE 0x63D3000ull +#define DCORE1_EDMA1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_CS_ETF_SECTION 0x1000 +#define mmDCORE1_EDMA1_CS_SPMU_BASE 0x63D4000ull +#define DCORE1_EDMA1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_CS_SPMU_SECTION 0x1000 +#define mmDCORE1_EDMA1_BMON_CTI_BASE 0x63D5000ull +#define DCORE1_EDMA1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_BMON_CTI_SECTION 0x1000 +#define mmDCORE1_EDMA1_USER_CTI_BASE 0x63D6000ull +#define DCORE1_EDMA1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_USER_CTI_SECTION 0x1000 +#define mmDCORE1_EDMA1_BMON_0_BASE 0x63D7000ull +#define DCORE1_EDMA1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_BMON_0_SECTION 0x1000 +#define mmDCORE1_EDMA1_BMON_1_BASE 0x63D8000ull +#define DCORE1_EDMA1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_BMON_1_SECTION 0x1000 +#define mmDCORE1_EDMA1_QM_ARC_RTT_BASE 0x63D9000ull +#define DCORE1_EDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_EDMA1_QM_ARC_RTT_SECTION 0x7000 +#define mmDCORE1_VDEC0_CS_ROM_TBL_BASE 0x63E0000ull +#define DCORE1_VDEC0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_VDEC0_CS_STM_BASE 0x63E1000ull +#define DCORE1_VDEC0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_CS_STM_SECTION 0x1000 +#define mmDCORE1_VDEC0_CS_CTI_BASE 0x63E2000ull +#define DCORE1_VDEC0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_CS_CTI_SECTION 0x1000 +#define mmDCORE1_VDEC0_CS_ETF_BASE 0x63E3000ull +#define DCORE1_VDEC0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_CS_ETF_SECTION 0x1000 +#define mmDCORE1_VDEC0_CS_SPMU_BASE 0x63E4000ull +#define DCORE1_VDEC0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_CS_SPMU_SECTION 0x1000 +#define mmDCORE1_VDEC0_BMON_CTI_BASE 0x63E5000ull +#define DCORE1_VDEC0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_BMON_CTI_SECTION 0x1000 +#define mmDCORE1_VDEC0_USER_CTI_BASE 0x63E6000ull +#define DCORE1_VDEC0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_USER_CTI_SECTION 0x1000 +#define mmDCORE1_VDEC0_BMON_0_BASE 0x63E7000ull +#define DCORE1_VDEC0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_BMON_0_SECTION 0x1000 +#define mmDCORE1_VDEC0_BMON_1_BASE 0x63E8000ull +#define DCORE1_VDEC0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_BMON_1_SECTION 0x1000 +#define mmDCORE1_VDEC0_BMON_2_BASE 0x63E9000ull +#define DCORE1_VDEC0_BMON_2_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_BMON_2_SECTION 0x7000 +#define mmDCORE1_VDEC1_CS_ROM_TBL_BASE 0x63F0000ull +#define DCORE1_VDEC1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE1_VDEC1_CS_STM_BASE 0x63F1000ull +#define DCORE1_VDEC1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_CS_STM_SECTION 0x1000 +#define mmDCORE1_VDEC1_CS_CTI_BASE 0x63F2000ull +#define DCORE1_VDEC1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_CS_CTI_SECTION 0x1000 +#define mmDCORE1_VDEC1_CS_ETF_BASE 0x63F3000ull +#define DCORE1_VDEC1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_CS_ETF_SECTION 0x1000 +#define mmDCORE1_VDEC1_CS_SPMU_BASE 0x63F4000ull +#define DCORE1_VDEC1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_CS_SPMU_SECTION 0x1000 +#define mmDCORE1_VDEC1_BMON_CTI_BASE 0x63F5000ull +#define DCORE1_VDEC1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_BMON_CTI_SECTION 0x1000 +#define mmDCORE1_VDEC1_USER_CTI_BASE 0x63F6000ull +#define DCORE1_VDEC1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_USER_CTI_SECTION 0x1000 +#define mmDCORE1_VDEC1_BMON_0_BASE 0x63F7000ull +#define DCORE1_VDEC1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_BMON_0_SECTION 0x1000 +#define mmDCORE1_VDEC1_BMON_1_BASE 0x63F8000ull +#define DCORE1_VDEC1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_BMON_1_SECTION 0x1000 +#define mmDCORE1_VDEC1_BMON_2_BASE 0x63F9000ull +#define DCORE1_VDEC1_BMON_2_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_BMON_2_SECTION 0x7000 +#define mmDCORE2_ROM_TABLE_L_BASE 0x6400000ull +#define DCORE2_ROM_TABLE_L_MAX_OFFSET 0x1000 +#define DCORE2_ROM_TABLE_L_SECTION 0x80000 +#define mmDCORE2_HMMU0_CS_ROM_TBL_BASE 0x6480000ull +#define DCORE2_HMMU0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_HMMU0_CS_STM_BASE 0x6481000ull +#define DCORE2_HMMU0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_CS_STM_SECTION 0x1000 +#define mmDCORE2_HMMU0_CS_CTI_BASE 0x6482000ull +#define DCORE2_HMMU0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_CS_CTI_SECTION 0x1000 +#define mmDCORE2_HMMU0_CS_ETF_BASE 0x6483000ull +#define DCORE2_HMMU0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_CS_ETF_SECTION 0x1000 +#define mmDCORE2_HMMU0_CS_SPMU_BASE 0x6484000ull +#define DCORE2_HMMU0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_CS_SPMU_SECTION 0x1000 +#define mmDCORE2_HMMU0_BMON_CTI_BASE 0x6485000ull +#define DCORE2_HMMU0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_BMON_CTI_SECTION 0x1000 +#define mmDCORE2_HMMU0_USER_CTI_BASE 0x6486000ull +#define DCORE2_HMMU0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_USER_CTI_SECTION 0x1000 +#define mmDCORE2_HMMU0_BMON_0_BASE 0x6487000ull +#define DCORE2_HMMU0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_BMON_0_SECTION 0x1000 +#define mmDCORE2_HMMU0_BMON_1_BASE 0x6488000ull +#define DCORE2_HMMU0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_BMON_1_SECTION 0x1000 +#define mmDCORE2_HMMU0_BMON_3_BASE 0x6489000ull +#define DCORE2_HMMU0_BMON_3_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_BMON_3_SECTION 0x1000 +#define mmDCORE2_HMMU0_BMON_2_BASE 0x648A000ull +#define DCORE2_HMMU0_BMON_2_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_BMON_2_SECTION 0x1000 +#define mmDCORE2_HMMU0_BMON_4_BASE 0x648B000ull +#define DCORE2_HMMU0_BMON_4_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_BMON_4_SECTION 0x5000 +#define mmDCORE2_HMMU1_CS_ROM_TBL_BASE 0x6490000ull +#define DCORE2_HMMU1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_HMMU1_CS_STM_BASE 0x6491000ull +#define DCORE2_HMMU1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_CS_STM_SECTION 0x1000 +#define mmDCORE2_HMMU1_CS_CTI_BASE 0x6492000ull +#define DCORE2_HMMU1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_CS_CTI_SECTION 0x1000 +#define mmDCORE2_HMMU1_CS_ETF_BASE 0x6493000ull +#define DCORE2_HMMU1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_CS_ETF_SECTION 0x1000 +#define mmDCORE2_HMMU1_CS_SPMU_BASE 0x6494000ull +#define DCORE2_HMMU1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_CS_SPMU_SECTION 0x1000 +#define mmDCORE2_HMMU1_BMON_CTI_BASE 0x6495000ull +#define DCORE2_HMMU1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_BMON_CTI_SECTION 0x1000 +#define mmDCORE2_HMMU1_USER_CTI_BASE 0x6496000ull +#define DCORE2_HMMU1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_USER_CTI_SECTION 0x1000 +#define mmDCORE2_HMMU1_BMON_0_BASE 0x6497000ull +#define DCORE2_HMMU1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_BMON_0_SECTION 0x1000 +#define mmDCORE2_HMMU1_BMON_1_BASE 0x6498000ull +#define DCORE2_HMMU1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_BMON_1_SECTION 0x1000 +#define mmDCORE2_HMMU1_BMON_3_BASE 0x6499000ull +#define DCORE2_HMMU1_BMON_3_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_BMON_3_SECTION 0x1000 +#define mmDCORE2_HMMU1_BMON_2_BASE 0x649A000ull +#define DCORE2_HMMU1_BMON_2_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_BMON_2_SECTION 0x1000 +#define mmDCORE2_HMMU1_BMON_4_BASE 0x649B000ull +#define DCORE2_HMMU1_BMON_4_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_BMON_4_SECTION 0x5000 +#define mmDCORE2_HMMU2_CS_ROM_TBL_BASE 0x64A0000ull +#define DCORE2_HMMU2_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_HMMU2_CS_STM_BASE 0x64A1000ull +#define DCORE2_HMMU2_CS_STM_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_CS_STM_SECTION 0x1000 +#define mmDCORE2_HMMU2_CS_CTI_BASE 0x64A2000ull +#define DCORE2_HMMU2_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_CS_CTI_SECTION 0x1000 +#define mmDCORE2_HMMU2_CS_ETF_BASE 0x64A3000ull +#define DCORE2_HMMU2_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_CS_ETF_SECTION 0x1000 +#define mmDCORE2_HMMU2_CS_SPMU_BASE 0x64A4000ull +#define DCORE2_HMMU2_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_CS_SPMU_SECTION 0x1000 +#define mmDCORE2_HMMU2_BMON_CTI_BASE 0x64A5000ull +#define DCORE2_HMMU2_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_BMON_CTI_SECTION 0x1000 +#define mmDCORE2_HMMU2_USER_CTI_BASE 0x64A6000ull +#define DCORE2_HMMU2_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_USER_CTI_SECTION 0x1000 +#define mmDCORE2_HMMU2_BMON_0_BASE 0x64A7000ull +#define DCORE2_HMMU2_BMON_0_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_BMON_0_SECTION 0x1000 +#define mmDCORE2_HMMU2_BMON_1_BASE 0x64A8000ull +#define DCORE2_HMMU2_BMON_1_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_BMON_1_SECTION 0x1000 +#define mmDCORE2_HMMU2_BMON_3_BASE 0x64A9000ull +#define DCORE2_HMMU2_BMON_3_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_BMON_3_SECTION 0x1000 +#define mmDCORE2_HMMU2_BMON_2_BASE 0x64AA000ull +#define DCORE2_HMMU2_BMON_2_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_BMON_2_SECTION 0x1000 +#define mmDCORE2_HMMU2_BMON_4_BASE 0x64AB000ull +#define DCORE2_HMMU2_BMON_4_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_BMON_4_SECTION 0x5000 +#define mmDCORE2_HMMU3_CS_ROM_TBL_BASE 0x64B0000ull +#define DCORE2_HMMU3_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_HMMU3_CS_STM_BASE 0x64B1000ull +#define DCORE2_HMMU3_CS_STM_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_CS_STM_SECTION 0x1000 +#define mmDCORE2_HMMU3_CS_CTI_BASE 0x64B2000ull +#define DCORE2_HMMU3_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_CS_CTI_SECTION 0x1000 +#define mmDCORE2_HMMU3_CS_ETF_BASE 0x64B3000ull +#define DCORE2_HMMU3_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_CS_ETF_SECTION 0x1000 +#define mmDCORE2_HMMU3_CS_SPMU_BASE 0x64B4000ull +#define DCORE2_HMMU3_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_CS_SPMU_SECTION 0x1000 +#define mmDCORE2_HMMU3_BMON_CTI_BASE 0x64B5000ull +#define DCORE2_HMMU3_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_BMON_CTI_SECTION 0x1000 +#define mmDCORE2_HMMU3_USER_CTI_BASE 0x64B6000ull +#define DCORE2_HMMU3_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_USER_CTI_SECTION 0x1000 +#define mmDCORE2_HMMU3_BMON_0_BASE 0x64B7000ull +#define DCORE2_HMMU3_BMON_0_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_BMON_0_SECTION 0x1000 +#define mmDCORE2_HMMU3_BMON_1_BASE 0x64B8000ull +#define DCORE2_HMMU3_BMON_1_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_BMON_1_SECTION 0x1000 +#define mmDCORE2_HMMU3_BMON_3_BASE 0x64B9000ull +#define DCORE2_HMMU3_BMON_3_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_BMON_3_SECTION 0x1000 +#define mmDCORE2_HMMU3_BMON_2_BASE 0x64BA000ull +#define DCORE2_HMMU3_BMON_2_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_BMON_2_SECTION 0x1000 +#define mmDCORE2_HMMU3_BMON_4_BASE 0x64BB000ull +#define DCORE2_HMMU3_BMON_4_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_BMON_4_SECTION 0x5000 +#define mmDCORE2_MME_CTRL_ROM_TABLE_BASE 0x64C0000ull +#define DCORE2_MME_CTRL_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_ROM_TABLE_SECTION 0x1000 +#define mmDCORE2_MME_CTRL_STM_BASE 0x64C1000ull +#define DCORE2_MME_CTRL_STM_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_STM_SECTION 0x1000 +#define mmDCORE2_MME_CTRL_CTI_BASE 0x64C2000ull +#define DCORE2_MME_CTRL_CTI_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_CTI_SECTION 0x1000 +#define mmDCORE2_MME_CTRL_ETF_BASE 0x64C3000ull +#define DCORE2_MME_CTRL_ETF_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_ETF_SECTION 0x1000 +#define mmDCORE2_MME_CTRL_SPMU_BASE 0x64C4000ull +#define DCORE2_MME_CTRL_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_SPMU_SECTION 0x1000 +#define mmDCORE2_MME_CTRL_CTI0_BASE 0x64C5000ull +#define DCORE2_MME_CTRL_CTI0_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_CTI0_SECTION 0x1000 +#define mmDCORE2_MME_CTRL_CTI1_BASE 0x64C6000ull +#define DCORE2_MME_CTRL_CTI1_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_CTI1_SECTION 0x1000 +#define mmDCORE2_MME_CTRL_BMON0_BASE 0x64C7000ull +#define DCORE2_MME_CTRL_BMON0_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_BMON0_SECTION 0x1000 +#define mmDCORE2_MME_CTRL_BMON1_BASE 0x64C8000ull +#define DCORE2_MME_CTRL_BMON1_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_BMON1_SECTION 0x1000 +#define mmDCORE2_MME_CTRL_BMON2_BASE 0x64C9000ull +#define DCORE2_MME_CTRL_BMON2_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_BMON2_SECTION 0x1000 +#define mmDCORE2_MME_CTRL_BMON3_BASE 0x64CA000ull +#define DCORE2_MME_CTRL_BMON3_MAX_OFFSET 0x1000 +#define DCORE2_MME_CTRL_BMON3_SECTION 0x1000 +#define mmDCORE2_MME_CTRL_ARC_RTT_BASE 0x64CB000ull +#define DCORE2_MME_CTRL_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_MME_CTRL_ARC_RTT_SECTION 0x5000 +#define mmDCORE2_MME_SBTE0_ROM_TBL_BASE 0x64D0000ull +#define DCORE2_MME_SBTE0_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE0_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_MME_SBTE0_STM_BASE 0x64D1000ull +#define DCORE2_MME_SBTE0_STM_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE0_STM_SECTION 0x1000 +#define mmDCORE2_MME_SBTE0_CTI_BASE 0x64D2000ull +#define DCORE2_MME_SBTE0_CTI_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE0_CTI_SECTION 0x1000 +#define mmDCORE2_MME_SBTE0_ETF_BASE 0x64D3000ull +#define DCORE2_MME_SBTE0_ETF_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE0_ETF_SECTION 0x1000 +#define mmDCORE2_MME_SBTE0_SPMU_BASE 0x64D4000ull +#define DCORE2_MME_SBTE0_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE0_SPMU_SECTION 0x1000 +#define mmDCORE2_MME_SBTE0_CTI0_BASE 0x64D5000ull +#define DCORE2_MME_SBTE0_CTI0_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE0_CTI0_SECTION 0x1000 +#define mmDCORE2_MME_SBTE0_CTI1_BASE 0x64D6000ull +#define DCORE2_MME_SBTE0_CTI1_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE0_CTI1_SECTION 0x1000 +#define mmDCORE2_MME_SBTE0_BMON0_BASE 0x64D7000ull +#define DCORE2_MME_SBTE0_BMON0_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE0_BMON0_SECTION 0x1000 +#define mmDCORE2_MME_SBTE1_ROM_TBL_BASE 0x64D8000ull +#define DCORE2_MME_SBTE1_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE1_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_MME_SBTE1_STM_BASE 0x64D9000ull +#define DCORE2_MME_SBTE1_STM_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE1_STM_SECTION 0x1000 +#define mmDCORE2_MME_SBTE1_CTI_BASE 0x64DA000ull +#define DCORE2_MME_SBTE1_CTI_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE1_CTI_SECTION 0x1000 +#define mmDCORE2_MME_SBTE1_ETF_BASE 0x64DB000ull +#define DCORE2_MME_SBTE1_ETF_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE1_ETF_SECTION 0x1000 +#define mmDCORE2_MME_SBTE1_SPMU_BASE 0x64DC000ull +#define DCORE2_MME_SBTE1_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE1_SPMU_SECTION 0x1000 +#define mmDCORE2_MME_SBTE1_CTI0_BASE 0x64DD000ull +#define DCORE2_MME_SBTE1_CTI0_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE1_CTI0_SECTION 0x1000 +#define mmDCORE2_MME_SBTE1_CTI1_BASE 0x64DE000ull +#define DCORE2_MME_SBTE1_CTI1_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE1_CTI1_SECTION 0x1000 +#define mmDCORE2_MME_SBTE1_BMON0_BASE 0x64DF000ull +#define DCORE2_MME_SBTE1_BMON0_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE1_BMON0_SECTION 0x1000 +#define mmDCORE2_MME_SBTE2_ROM_TBL_BASE 0x64E0000ull +#define DCORE2_MME_SBTE2_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE2_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_MME_SBTE2_STM_BASE 0x64E1000ull +#define DCORE2_MME_SBTE2_STM_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE2_STM_SECTION 0x1000 +#define mmDCORE2_MME_SBTE2_CTI_BASE 0x64E2000ull +#define DCORE2_MME_SBTE2_CTI_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE2_CTI_SECTION 0x1000 +#define mmDCORE2_MME_SBTE2_ETF_BASE 0x64E3000ull +#define DCORE2_MME_SBTE2_ETF_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE2_ETF_SECTION 0x1000 +#define mmDCORE2_MME_SBTE2_SPMU_BASE 0x64E4000ull +#define DCORE2_MME_SBTE2_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE2_SPMU_SECTION 0x1000 +#define mmDCORE2_MME_SBTE2_CTI0_BASE 0x64E5000ull +#define DCORE2_MME_SBTE2_CTI0_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE2_CTI0_SECTION 0x1000 +#define mmDCORE2_MME_SBTE2_CTI1_BASE 0x64E6000ull +#define DCORE2_MME_SBTE2_CTI1_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE2_CTI1_SECTION 0x1000 +#define mmDCORE2_MME_SBTE2_BMON0_BASE 0x64E7000ull +#define DCORE2_MME_SBTE2_BMON0_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE2_BMON0_SECTION 0x1000 +#define mmDCORE2_MME_SBTE3_ROM_TBL_BASE 0x64E8000ull +#define DCORE2_MME_SBTE3_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE3_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_MME_SBTE3_STM_BASE 0x64E9000ull +#define DCORE2_MME_SBTE3_STM_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE3_STM_SECTION 0x1000 +#define mmDCORE2_MME_SBTE3_CTI_BASE 0x64EA000ull +#define DCORE2_MME_SBTE3_CTI_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE3_CTI_SECTION 0x1000 +#define mmDCORE2_MME_SBTE3_ETF_BASE 0x64EB000ull +#define DCORE2_MME_SBTE3_ETF_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE3_ETF_SECTION 0x1000 +#define mmDCORE2_MME_SBTE3_SPMU_BASE 0x64EC000ull +#define DCORE2_MME_SBTE3_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE3_SPMU_SECTION 0x1000 +#define mmDCORE2_MME_SBTE3_CTI0_BASE 0x64ED000ull +#define DCORE2_MME_SBTE3_CTI0_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE3_CTI0_SECTION 0x1000 +#define mmDCORE2_MME_SBTE3_CTI1_BASE 0x64EE000ull +#define DCORE2_MME_SBTE3_CTI1_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE3_CTI1_SECTION 0x1000 +#define mmDCORE2_MME_SBTE3_BMON0_BASE 0x64EF000ull +#define DCORE2_MME_SBTE3_BMON0_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE3_BMON0_SECTION 0x1000 +#define mmDCORE2_MME_SBTE4_ROM_TBL_BASE 0x64F0000ull +#define DCORE2_MME_SBTE4_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE4_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_MME_SBTE4_STM_BASE 0x64F1000ull +#define DCORE2_MME_SBTE4_STM_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE4_STM_SECTION 0x1000 +#define mmDCORE2_MME_SBTE4_CTI_BASE 0x64F2000ull +#define DCORE2_MME_SBTE4_CTI_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE4_CTI_SECTION 0x1000 +#define mmDCORE2_MME_SBTE4_ETF_BASE 0x64F3000ull +#define DCORE2_MME_SBTE4_ETF_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE4_ETF_SECTION 0x1000 +#define mmDCORE2_MME_SBTE4_SPMU_BASE 0x64F4000ull +#define DCORE2_MME_SBTE4_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE4_SPMU_SECTION 0x1000 +#define mmDCORE2_MME_SBTE4_CTI0_BASE 0x64F5000ull +#define DCORE2_MME_SBTE4_CTI0_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE4_CTI0_SECTION 0x1000 +#define mmDCORE2_MME_SBTE4_CTI1_BASE 0x64F6000ull +#define DCORE2_MME_SBTE4_CTI1_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE4_CTI1_SECTION 0x1000 +#define mmDCORE2_MME_SBTE4_BMON0_BASE 0x64F7000ull +#define DCORE2_MME_SBTE4_BMON0_MAX_OFFSET 0x1000 +#define DCORE2_MME_SBTE4_BMON0_SECTION 0x9000 +#define mmDCORE2_MME_ACC_CS_ROM_TBL_BASE 0x6500000ull +#define DCORE2_MME_ACC_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_MME_ACC_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_MME_ACC_STM_BASE 0x6501000ull +#define DCORE2_MME_ACC_STM_MAX_OFFSET 0x1000 +#define DCORE2_MME_ACC_STM_SECTION 0x1000 +#define mmDCORE2_MME_ACC_CTI_BASE 0x6502000ull +#define DCORE2_MME_ACC_CTI_MAX_OFFSET 0x1000 +#define DCORE2_MME_ACC_CTI_SECTION 0x1000 +#define mmDCORE2_MME_ACC_ETF_BASE 0x6503000ull +#define DCORE2_MME_ACC_ETF_MAX_OFFSET 0x1000 +#define DCORE2_MME_ACC_ETF_SECTION 0x1000 +#define mmDCORE2_MME_ACC_SPMU_BASE 0x6504000ull +#define DCORE2_MME_ACC_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_MME_ACC_SPMU_SECTION 0x1000 +#define mmDCORE2_MME_ACC_CTI0_BASE 0x6505000ull +#define DCORE2_MME_ACC_CTI0_MAX_OFFSET 0x1000 +#define DCORE2_MME_ACC_CTI0_SECTION 0x1000 +#define mmDCORE2_MME_ACC_CTI1_BASE 0x6506000ull +#define DCORE2_MME_ACC_CTI1_MAX_OFFSET 0x1000 +#define DCORE2_MME_ACC_CTI1_SECTION 0x1000 +#define mmDCORE2_MME_ACC_BMON0_BASE 0x6507000ull +#define DCORE2_MME_ACC_BMON0_MAX_OFFSET 0x1000 +#define DCORE2_MME_ACC_BMON0_SECTION 0x1000 +#define mmDCORE2_MME_ACC_BMON1_BASE 0x6508000ull +#define DCORE2_MME_ACC_BMON1_MAX_OFFSET 0x1000 +#define DCORE2_MME_ACC_BMON1_SECTION 0x8000 +#define mmDCORE2_SM_CS_DBG_ROM_TBL_BASE 0x6510000ull +#define DCORE2_SM_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_SM_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_SM_STM_BASE 0x6511000ull +#define DCORE2_SM_STM_MAX_OFFSET 0x1000 +#define DCORE2_SM_STM_SECTION 0x1000 +#define mmDCORE2_SM_CTI_BASE 0x6512000ull +#define DCORE2_SM_CTI_MAX_OFFSET 0x1000 +#define DCORE2_SM_CTI_SECTION 0x1000 +#define mmDCORE2_SM_ETF_BASE 0x6513000ull +#define DCORE2_SM_ETF_MAX_OFFSET 0x1000 +#define DCORE2_SM_ETF_SECTION 0x1000 +#define mmDCORE2_SM_SPMU_BASE 0x6514000ull +#define DCORE2_SM_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_SM_SPMU_SECTION 0x1000 +#define mmDCORE2_SM_BMON_CTI_BASE 0x6515000ull +#define DCORE2_SM_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_SM_BMON_CTI_SECTION 0x1000 +#define mmDCORE2_SM_USER_CTI_BASE 0x6516000ull +#define DCORE2_SM_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_SM_USER_CTI_SECTION 0x1000 +#define mmDCORE2_SM_BMON_BASE 0x6517000ull +#define DCORE2_SM_BMON_MAX_OFFSET 0x1000 +#define DCORE2_SM_BMON_SECTION 0x1000 +#define mmDCORE2_SM_BMON1_BASE 0x6518000ull +#define DCORE2_SM_BMON1_MAX_OFFSET 0x1000 +#define DCORE2_SM_BMON1_SECTION 0x18000 +#define mmDCORE2_XFT_FUNNEL_BASE 0x6530000ull +#define DCORE2_XFT_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_XFT_FUNNEL_SECTION 0x8000 +#define mmDCORE2_TFT0_FUNNEL_BASE 0x6538000ull +#define DCORE2_TFT0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TFT0_FUNNEL_SECTION 0x1000 +#define mmDCORE2_TFT1_FUNNEL_BASE 0x6539000ull +#define DCORE2_TFT1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TFT1_FUNNEL_SECTION 0x1000 +#define mmDCORE2_TFT2_FUNNEL_BASE 0x653A000ull +#define DCORE2_TFT2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TFT2_FUNNEL_SECTION 0x7000 +#define mmDCORE2_RTR0_FUNNEL_BASE 0x6541000ull +#define DCORE2_RTR0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_RTR0_FUNNEL_SECTION 0x8000 +#define mmDCORE2_RTR1_FUNNEL_BASE 0x6549000ull +#define DCORE2_RTR1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_RTR1_FUNNEL_SECTION 0x8000 +#define mmDCORE2_RTR2_FUNNEL_BASE 0x6551000ull +#define DCORE2_RTR2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_RTR2_FUNNEL_SECTION 0x8000 +#define mmDCORE2_RTR3_FUNNEL_BASE 0x6559000ull +#define DCORE2_RTR3_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_RTR3_FUNNEL_SECTION 0x8000 +#define mmDCORE2_RTR4_FUNNEL_BASE 0x6561000ull +#define DCORE2_RTR4_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_RTR4_FUNNEL_SECTION 0x4000 +#define mmDCORE2_MIF0_FUNNEL_BASE 0x6565000ull +#define DCORE2_MIF0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_MIF0_FUNNEL_SECTION 0x4000 +#define mmDCORE2_RTR5_FUNNEL_BASE 0x6569000ull +#define DCORE2_RTR5_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_RTR5_FUNNEL_SECTION 0x4000 +#define mmDCORE2_MIF1_FUNNEL_BASE 0x656D000ull +#define DCORE2_MIF1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_MIF1_FUNNEL_SECTION 0x4000 +#define mmDCORE2_RTR6_FUNNEL_BASE 0x6571000ull +#define DCORE2_RTR6_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_RTR6_FUNNEL_SECTION 0x4000 +#define mmDCORE2_MIF2_FUNNEL_BASE 0x6575000ull +#define DCORE2_MIF2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_MIF2_FUNNEL_SECTION 0x4000 +#define mmDCORE2_RTR7_FUNNEL_BASE 0x6579000ull +#define DCORE2_RTR7_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_RTR7_FUNNEL_SECTION 0x4000 +#define mmDCORE2_MIF3_FUNNEL_BASE 0x657D000ull +#define DCORE2_MIF3_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_MIF3_FUNNEL_SECTION 0x43000 +#define mmDCORE2_EDMA0_CS_ROM_TBL_BASE 0x65C0000ull +#define DCORE2_EDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_EDMA0_CS_STM_BASE 0x65C1000ull +#define DCORE2_EDMA0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_CS_STM_SECTION 0x1000 +#define mmDCORE2_EDMA0_CS_CTI_BASE 0x65C2000ull +#define DCORE2_EDMA0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_CS_CTI_SECTION 0x1000 +#define mmDCORE2_EDMA0_CS_ETF_BASE 0x65C3000ull +#define DCORE2_EDMA0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_CS_ETF_SECTION 0x1000 +#define mmDCORE2_EDMA0_CS_SPMU_BASE 0x65C4000ull +#define DCORE2_EDMA0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_CS_SPMU_SECTION 0x1000 +#define mmDCORE2_EDMA0_BMON_CTI_BASE 0x65C5000ull +#define DCORE2_EDMA0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_BMON_CTI_SECTION 0x1000 +#define mmDCORE2_EDMA0_USER_CTI_BASE 0x65C6000ull +#define DCORE2_EDMA0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_USER_CTI_SECTION 0x1000 +#define mmDCORE2_EDMA0_BMON_0_BASE 0x65C7000ull +#define DCORE2_EDMA0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_BMON_0_SECTION 0x1000 +#define mmDCORE2_EDMA0_BMON_1_BASE 0x65C8000ull +#define DCORE2_EDMA0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_BMON_1_SECTION 0x1000 +#define mmDCORE2_EDMA0_QM_ARC_RTT_BASE 0x65C9000ull +#define DCORE2_EDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_EDMA0_QM_ARC_RTT_SECTION 0x7000 +#define mmDCORE2_EDMA1_CS_ROM_TBL_BASE 0x65D0000ull +#define DCORE2_EDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_EDMA1_CS_STM_BASE 0x65D1000ull +#define DCORE2_EDMA1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_CS_STM_SECTION 0x1000 +#define mmDCORE2_EDMA1_CS_CTI_BASE 0x65D2000ull +#define DCORE2_EDMA1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_CS_CTI_SECTION 0x1000 +#define mmDCORE2_EDMA1_CS_ETF_BASE 0x65D3000ull +#define DCORE2_EDMA1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_CS_ETF_SECTION 0x1000 +#define mmDCORE2_EDMA1_CS_SPMU_BASE 0x65D4000ull +#define DCORE2_EDMA1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_CS_SPMU_SECTION 0x1000 +#define mmDCORE2_EDMA1_BMON_CTI_BASE 0x65D5000ull +#define DCORE2_EDMA1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_BMON_CTI_SECTION 0x1000 +#define mmDCORE2_EDMA1_USER_CTI_BASE 0x65D6000ull +#define DCORE2_EDMA1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_USER_CTI_SECTION 0x1000 +#define mmDCORE2_EDMA1_BMON_0_BASE 0x65D7000ull +#define DCORE2_EDMA1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_BMON_0_SECTION 0x1000 +#define mmDCORE2_EDMA1_BMON_1_BASE 0x65D8000ull +#define DCORE2_EDMA1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_BMON_1_SECTION 0x1000 +#define mmDCORE2_EDMA1_QM_ARC_RTT_BASE 0x65D9000ull +#define DCORE2_EDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_EDMA1_QM_ARC_RTT_SECTION 0x7000 +#define mmDCORE2_VDEC0_CS_ROM_TBL_BASE 0x65E0000ull +#define DCORE2_VDEC0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_VDEC0_CS_STM_BASE 0x65E1000ull +#define DCORE2_VDEC0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_CS_STM_SECTION 0x1000 +#define mmDCORE2_VDEC0_CS_CTI_BASE 0x65E2000ull +#define DCORE2_VDEC0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_CS_CTI_SECTION 0x1000 +#define mmDCORE2_VDEC0_CS_ETF_BASE 0x65E3000ull +#define DCORE2_VDEC0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_CS_ETF_SECTION 0x1000 +#define mmDCORE2_VDEC0_CS_SPMU_BASE 0x65E4000ull +#define DCORE2_VDEC0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_CS_SPMU_SECTION 0x1000 +#define mmDCORE2_VDEC0_BMON_CTI_BASE 0x65E5000ull +#define DCORE2_VDEC0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_BMON_CTI_SECTION 0x1000 +#define mmDCORE2_VDEC0_USER_CTI_BASE 0x65E6000ull +#define DCORE2_VDEC0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_USER_CTI_SECTION 0x1000 +#define mmDCORE2_VDEC0_BMON_0_BASE 0x65E7000ull +#define DCORE2_VDEC0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_BMON_0_SECTION 0x1000 +#define mmDCORE2_VDEC0_BMON_1_BASE 0x65E8000ull +#define DCORE2_VDEC0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_BMON_1_SECTION 0x1000 +#define mmDCORE2_VDEC0_BMON_2_BASE 0x65E9000ull +#define DCORE2_VDEC0_BMON_2_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_BMON_2_SECTION 0x7000 +#define mmDCORE2_VDEC1_CS_ROM_TBL_BASE 0x65F0000ull +#define DCORE2_VDEC1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE2_VDEC1_CS_STM_BASE 0x65F1000ull +#define DCORE2_VDEC1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_CS_STM_SECTION 0x1000 +#define mmDCORE2_VDEC1_CS_CTI_BASE 0x65F2000ull +#define DCORE2_VDEC1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_CS_CTI_SECTION 0x1000 +#define mmDCORE2_VDEC1_CS_ETF_BASE 0x65F3000ull +#define DCORE2_VDEC1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_CS_ETF_SECTION 0x1000 +#define mmDCORE2_VDEC1_CS_SPMU_BASE 0x65F4000ull +#define DCORE2_VDEC1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_CS_SPMU_SECTION 0x1000 +#define mmDCORE2_VDEC1_BMON_CTI_BASE 0x65F5000ull +#define DCORE2_VDEC1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_BMON_CTI_SECTION 0x1000 +#define mmDCORE2_VDEC1_USER_CTI_BASE 0x65F6000ull +#define DCORE2_VDEC1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_USER_CTI_SECTION 0x1000 +#define mmDCORE2_VDEC1_BMON_0_BASE 0x65F7000ull +#define DCORE2_VDEC1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_BMON_0_SECTION 0x1000 +#define mmDCORE2_VDEC1_BMON_1_BASE 0x65F8000ull +#define DCORE2_VDEC1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_BMON_1_SECTION 0x1000 +#define mmDCORE2_VDEC1_BMON_2_BASE 0x65F9000ull +#define DCORE2_VDEC1_BMON_2_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_BMON_2_SECTION 0x7000 +#define mmDCORE3_ROM_TABLE_L_BASE 0x6600000ull +#define DCORE3_ROM_TABLE_L_MAX_OFFSET 0x1000 +#define DCORE3_ROM_TABLE_L_SECTION 0x80000 +#define mmDCORE3_HMMU0_CS_ROM_TBL_BASE 0x6680000ull +#define DCORE3_HMMU0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_HMMU0_CS_STM_BASE 0x6681000ull +#define DCORE3_HMMU0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_CS_STM_SECTION 0x1000 +#define mmDCORE3_HMMU0_CS_CTI_BASE 0x6682000ull +#define DCORE3_HMMU0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_CS_CTI_SECTION 0x1000 +#define mmDCORE3_HMMU0_CS_ETF_BASE 0x6683000ull +#define DCORE3_HMMU0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_CS_ETF_SECTION 0x1000 +#define mmDCORE3_HMMU0_CS_SPMU_BASE 0x6684000ull +#define DCORE3_HMMU0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_CS_SPMU_SECTION 0x1000 +#define mmDCORE3_HMMU0_BMON_CTI_BASE 0x6685000ull +#define DCORE3_HMMU0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_BMON_CTI_SECTION 0x1000 +#define mmDCORE3_HMMU0_USER_CTI_BASE 0x6686000ull +#define DCORE3_HMMU0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_USER_CTI_SECTION 0x1000 +#define mmDCORE3_HMMU0_BMON_0_BASE 0x6687000ull +#define DCORE3_HMMU0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_BMON_0_SECTION 0x1000 +#define mmDCORE3_HMMU0_BMON_1_BASE 0x6688000ull +#define DCORE3_HMMU0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_BMON_1_SECTION 0x1000 +#define mmDCORE3_HMMU0_BMON_3_BASE 0x6689000ull +#define DCORE3_HMMU0_BMON_3_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_BMON_3_SECTION 0x1000 +#define mmDCORE3_HMMU0_BMON_2_BASE 0x668A000ull +#define DCORE3_HMMU0_BMON_2_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_BMON_2_SECTION 0x1000 +#define mmDCORE3_HMMU0_BMON_4_BASE 0x668B000ull +#define DCORE3_HMMU0_BMON_4_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_BMON_4_SECTION 0x5000 +#define mmDCORE3_HMMU1_CS_ROM_TBL_BASE 0x6690000ull +#define DCORE3_HMMU1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_HMMU1_CS_STM_BASE 0x6691000ull +#define DCORE3_HMMU1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_CS_STM_SECTION 0x1000 +#define mmDCORE3_HMMU1_CS_CTI_BASE 0x6692000ull +#define DCORE3_HMMU1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_CS_CTI_SECTION 0x1000 +#define mmDCORE3_HMMU1_CS_ETF_BASE 0x6693000ull +#define DCORE3_HMMU1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_CS_ETF_SECTION 0x1000 +#define mmDCORE3_HMMU1_CS_SPMU_BASE 0x6694000ull +#define DCORE3_HMMU1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_CS_SPMU_SECTION 0x1000 +#define mmDCORE3_HMMU1_BMON_CTI_BASE 0x6695000ull +#define DCORE3_HMMU1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_BMON_CTI_SECTION 0x1000 +#define mmDCORE3_HMMU1_USER_CTI_BASE 0x6696000ull +#define DCORE3_HMMU1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_USER_CTI_SECTION 0x1000 +#define mmDCORE3_HMMU1_BMON_0_BASE 0x6697000ull +#define DCORE3_HMMU1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_BMON_0_SECTION 0x1000 +#define mmDCORE3_HMMU1_BMON_1_BASE 0x6698000ull +#define DCORE3_HMMU1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_BMON_1_SECTION 0x1000 +#define mmDCORE3_HMMU1_BMON_3_BASE 0x6699000ull +#define DCORE3_HMMU1_BMON_3_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_BMON_3_SECTION 0x1000 +#define mmDCORE3_HMMU1_BMON_2_BASE 0x669A000ull +#define DCORE3_HMMU1_BMON_2_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_BMON_2_SECTION 0x1000 +#define mmDCORE3_HMMU1_BMON_4_BASE 0x669B000ull +#define DCORE3_HMMU1_BMON_4_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_BMON_4_SECTION 0x5000 +#define mmDCORE3_HMMU2_CS_ROM_TBL_BASE 0x66A0000ull +#define DCORE3_HMMU2_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_HMMU2_CS_STM_BASE 0x66A1000ull +#define DCORE3_HMMU2_CS_STM_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_CS_STM_SECTION 0x1000 +#define mmDCORE3_HMMU2_CS_CTI_BASE 0x66A2000ull +#define DCORE3_HMMU2_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_CS_CTI_SECTION 0x1000 +#define mmDCORE3_HMMU2_CS_ETF_BASE 0x66A3000ull +#define DCORE3_HMMU2_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_CS_ETF_SECTION 0x1000 +#define mmDCORE3_HMMU2_CS_SPMU_BASE 0x66A4000ull +#define DCORE3_HMMU2_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_CS_SPMU_SECTION 0x1000 +#define mmDCORE3_HMMU2_BMON_CTI_BASE 0x66A5000ull +#define DCORE3_HMMU2_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_BMON_CTI_SECTION 0x1000 +#define mmDCORE3_HMMU2_USER_CTI_BASE 0x66A6000ull +#define DCORE3_HMMU2_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_USER_CTI_SECTION 0x1000 +#define mmDCORE3_HMMU2_BMON_0_BASE 0x66A7000ull +#define DCORE3_HMMU2_BMON_0_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_BMON_0_SECTION 0x1000 +#define mmDCORE3_HMMU2_BMON_1_BASE 0x66A8000ull +#define DCORE3_HMMU2_BMON_1_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_BMON_1_SECTION 0x1000 +#define mmDCORE3_HMMU2_BMON_3_BASE 0x66A9000ull +#define DCORE3_HMMU2_BMON_3_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_BMON_3_SECTION 0x1000 +#define mmDCORE3_HMMU2_BMON_2_BASE 0x66AA000ull +#define DCORE3_HMMU2_BMON_2_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_BMON_2_SECTION 0x1000 +#define mmDCORE3_HMMU2_BMON_4_BASE 0x66AB000ull +#define DCORE3_HMMU2_BMON_4_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_BMON_4_SECTION 0x5000 +#define mmDCORE3_HMMU3_CS_ROM_TBL_BASE 0x66B0000ull +#define DCORE3_HMMU3_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_HMMU3_CS_STM_BASE 0x66B1000ull +#define DCORE3_HMMU3_CS_STM_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_CS_STM_SECTION 0x1000 +#define mmDCORE3_HMMU3_CS_CTI_BASE 0x66B2000ull +#define DCORE3_HMMU3_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_CS_CTI_SECTION 0x1000 +#define mmDCORE3_HMMU3_CS_ETF_BASE 0x66B3000ull +#define DCORE3_HMMU3_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_CS_ETF_SECTION 0x1000 +#define mmDCORE3_HMMU3_CS_SPMU_BASE 0x66B4000ull +#define DCORE3_HMMU3_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_CS_SPMU_SECTION 0x1000 +#define mmDCORE3_HMMU3_BMON_CTI_BASE 0x66B5000ull +#define DCORE3_HMMU3_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_BMON_CTI_SECTION 0x1000 +#define mmDCORE3_HMMU3_USER_CTI_BASE 0x66B6000ull +#define DCORE3_HMMU3_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_USER_CTI_SECTION 0x1000 +#define mmDCORE3_HMMU3_BMON_0_BASE 0x66B7000ull +#define DCORE3_HMMU3_BMON_0_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_BMON_0_SECTION 0x1000 +#define mmDCORE3_HMMU3_BMON_1_BASE 0x66B8000ull +#define DCORE3_HMMU3_BMON_1_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_BMON_1_SECTION 0x1000 +#define mmDCORE3_HMMU3_BMON_3_BASE 0x66B9000ull +#define DCORE3_HMMU3_BMON_3_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_BMON_3_SECTION 0x1000 +#define mmDCORE3_HMMU3_BMON_2_BASE 0x66BA000ull +#define DCORE3_HMMU3_BMON_2_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_BMON_2_SECTION 0x1000 +#define mmDCORE3_HMMU3_BMON_4_BASE 0x66BB000ull +#define DCORE3_HMMU3_BMON_4_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_BMON_4_SECTION 0x5000 +#define mmDCORE3_MME_CTRL_ROM_TABLE_BASE 0x66C0000ull +#define DCORE3_MME_CTRL_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_ROM_TABLE_SECTION 0x1000 +#define mmDCORE3_MME_CTRL_STM_BASE 0x66C1000ull +#define DCORE3_MME_CTRL_STM_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_STM_SECTION 0x1000 +#define mmDCORE3_MME_CTRL_CTI_BASE 0x66C2000ull +#define DCORE3_MME_CTRL_CTI_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_CTI_SECTION 0x1000 +#define mmDCORE3_MME_CTRL_ETF_BASE 0x66C3000ull +#define DCORE3_MME_CTRL_ETF_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_ETF_SECTION 0x1000 +#define mmDCORE3_MME_CTRL_SPMU_BASE 0x66C4000ull +#define DCORE3_MME_CTRL_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_SPMU_SECTION 0x1000 +#define mmDCORE3_MME_CTRL_CTI0_BASE 0x66C5000ull +#define DCORE3_MME_CTRL_CTI0_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_CTI0_SECTION 0x1000 +#define mmDCORE3_MME_CTRL_CTI1_BASE 0x66C6000ull +#define DCORE3_MME_CTRL_CTI1_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_CTI1_SECTION 0x1000 +#define mmDCORE3_MME_CTRL_BMON0_BASE 0x66C7000ull +#define DCORE3_MME_CTRL_BMON0_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_BMON0_SECTION 0x1000 +#define mmDCORE3_MME_CTRL_BMON1_BASE 0x66C8000ull +#define DCORE3_MME_CTRL_BMON1_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_BMON1_SECTION 0x1000 +#define mmDCORE3_MME_CTRL_BMON2_BASE 0x66C9000ull +#define DCORE3_MME_CTRL_BMON2_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_BMON2_SECTION 0x1000 +#define mmDCORE3_MME_CTRL_BMON3_BASE 0x66CA000ull +#define DCORE3_MME_CTRL_BMON3_MAX_OFFSET 0x1000 +#define DCORE3_MME_CTRL_BMON3_SECTION 0x1000 +#define mmDCORE3_MME_CTRL_ARC_RTT_BASE 0x66CB000ull +#define DCORE3_MME_CTRL_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_MME_CTRL_ARC_RTT_SECTION 0x5000 +#define mmDCORE3_MME_SBTE0_ROM_TBL_BASE 0x66D0000ull +#define DCORE3_MME_SBTE0_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE0_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_MME_SBTE0_STM_BASE 0x66D1000ull +#define DCORE3_MME_SBTE0_STM_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE0_STM_SECTION 0x1000 +#define mmDCORE3_MME_SBTE0_CTI_BASE 0x66D2000ull +#define DCORE3_MME_SBTE0_CTI_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE0_CTI_SECTION 0x1000 +#define mmDCORE3_MME_SBTE0_ETF_BASE 0x66D3000ull +#define DCORE3_MME_SBTE0_ETF_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE0_ETF_SECTION 0x1000 +#define mmDCORE3_MME_SBTE0_SPMU_BASE 0x66D4000ull +#define DCORE3_MME_SBTE0_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE0_SPMU_SECTION 0x1000 +#define mmDCORE3_MME_SBTE0_CTI0_BASE 0x66D5000ull +#define DCORE3_MME_SBTE0_CTI0_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE0_CTI0_SECTION 0x1000 +#define mmDCORE3_MME_SBTE0_CTI1_BASE 0x66D6000ull +#define DCORE3_MME_SBTE0_CTI1_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE0_CTI1_SECTION 0x1000 +#define mmDCORE3_MME_SBTE0_BMON0_BASE 0x66D7000ull +#define DCORE3_MME_SBTE0_BMON0_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE0_BMON0_SECTION 0x1000 +#define mmDCORE3_MME_SBTE1_ROM_TBL_BASE 0x66D8000ull +#define DCORE3_MME_SBTE1_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE1_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_MME_SBTE1_STM_BASE 0x66D9000ull +#define DCORE3_MME_SBTE1_STM_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE1_STM_SECTION 0x1000 +#define mmDCORE3_MME_SBTE1_CTI_BASE 0x66DA000ull +#define DCORE3_MME_SBTE1_CTI_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE1_CTI_SECTION 0x1000 +#define mmDCORE3_MME_SBTE1_ETF_BASE 0x66DB000ull +#define DCORE3_MME_SBTE1_ETF_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE1_ETF_SECTION 0x1000 +#define mmDCORE3_MME_SBTE1_SPMU_BASE 0x66DC000ull +#define DCORE3_MME_SBTE1_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE1_SPMU_SECTION 0x1000 +#define mmDCORE3_MME_SBTE1_CTI0_BASE 0x66DD000ull +#define DCORE3_MME_SBTE1_CTI0_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE1_CTI0_SECTION 0x1000 +#define mmDCORE3_MME_SBTE1_CTI1_BASE 0x66DE000ull +#define DCORE3_MME_SBTE1_CTI1_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE1_CTI1_SECTION 0x1000 +#define mmDCORE3_MME_SBTE1_BMON0_BASE 0x66DF000ull +#define DCORE3_MME_SBTE1_BMON0_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE1_BMON0_SECTION 0x1000 +#define mmDCORE3_MME_SBTE2_ROM_TBL_BASE 0x66E0000ull +#define DCORE3_MME_SBTE2_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE2_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_MME_SBTE2_STM_BASE 0x66E1000ull +#define DCORE3_MME_SBTE2_STM_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE2_STM_SECTION 0x1000 +#define mmDCORE3_MME_SBTE2_CTI_BASE 0x66E2000ull +#define DCORE3_MME_SBTE2_CTI_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE2_CTI_SECTION 0x1000 +#define mmDCORE3_MME_SBTE2_ETF_BASE 0x66E3000ull +#define DCORE3_MME_SBTE2_ETF_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE2_ETF_SECTION 0x1000 +#define mmDCORE3_MME_SBTE2_SPMU_BASE 0x66E4000ull +#define DCORE3_MME_SBTE2_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE2_SPMU_SECTION 0x1000 +#define mmDCORE3_MME_SBTE2_CTI0_BASE 0x66E5000ull +#define DCORE3_MME_SBTE2_CTI0_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE2_CTI0_SECTION 0x1000 +#define mmDCORE3_MME_SBTE2_CTI1_BASE 0x66E6000ull +#define DCORE3_MME_SBTE2_CTI1_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE2_CTI1_SECTION 0x1000 +#define mmDCORE3_MME_SBTE2_BMON0_BASE 0x66E7000ull +#define DCORE3_MME_SBTE2_BMON0_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE2_BMON0_SECTION 0x1000 +#define mmDCORE3_MME_SBTE3_ROM_TBL_BASE 0x66E8000ull +#define DCORE3_MME_SBTE3_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE3_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_MME_SBTE3_STM_BASE 0x66E9000ull +#define DCORE3_MME_SBTE3_STM_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE3_STM_SECTION 0x1000 +#define mmDCORE3_MME_SBTE3_CTI_BASE 0x66EA000ull +#define DCORE3_MME_SBTE3_CTI_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE3_CTI_SECTION 0x1000 +#define mmDCORE3_MME_SBTE3_ETF_BASE 0x66EB000ull +#define DCORE3_MME_SBTE3_ETF_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE3_ETF_SECTION 0x1000 +#define mmDCORE3_MME_SBTE3_SPMU_BASE 0x66EC000ull +#define DCORE3_MME_SBTE3_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE3_SPMU_SECTION 0x1000 +#define mmDCORE3_MME_SBTE3_CTI0_BASE 0x66ED000ull +#define DCORE3_MME_SBTE3_CTI0_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE3_CTI0_SECTION 0x1000 +#define mmDCORE3_MME_SBTE3_CTI1_BASE 0x66EE000ull +#define DCORE3_MME_SBTE3_CTI1_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE3_CTI1_SECTION 0x1000 +#define mmDCORE3_MME_SBTE3_BMON0_BASE 0x66EF000ull +#define DCORE3_MME_SBTE3_BMON0_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE3_BMON0_SECTION 0x1000 +#define mmDCORE3_MME_SBTE4_ROM_TBL_BASE 0x66F0000ull +#define DCORE3_MME_SBTE4_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE4_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_MME_SBTE4_STM_BASE 0x66F1000ull +#define DCORE3_MME_SBTE4_STM_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE4_STM_SECTION 0x1000 +#define mmDCORE3_MME_SBTE4_CTI_BASE 0x66F2000ull +#define DCORE3_MME_SBTE4_CTI_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE4_CTI_SECTION 0x1000 +#define mmDCORE3_MME_SBTE4_ETF_BASE 0x66F3000ull +#define DCORE3_MME_SBTE4_ETF_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE4_ETF_SECTION 0x1000 +#define mmDCORE3_MME_SBTE4_SPMU_BASE 0x66F4000ull +#define DCORE3_MME_SBTE4_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE4_SPMU_SECTION 0x1000 +#define mmDCORE3_MME_SBTE4_CTI0_BASE 0x66F5000ull +#define DCORE3_MME_SBTE4_CTI0_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE4_CTI0_SECTION 0x1000 +#define mmDCORE3_MME_SBTE4_CTI1_BASE 0x66F6000ull +#define DCORE3_MME_SBTE4_CTI1_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE4_CTI1_SECTION 0x1000 +#define mmDCORE3_MME_SBTE4_BMON0_BASE 0x66F7000ull +#define DCORE3_MME_SBTE4_BMON0_MAX_OFFSET 0x1000 +#define DCORE3_MME_SBTE4_BMON0_SECTION 0x9000 +#define mmDCORE3_MME_ACC_CS_ROM_TBL_BASE 0x6700000ull +#define DCORE3_MME_ACC_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_MME_ACC_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_MME_ACC_STM_BASE 0x6701000ull +#define DCORE3_MME_ACC_STM_MAX_OFFSET 0x1000 +#define DCORE3_MME_ACC_STM_SECTION 0x1000 +#define mmDCORE3_MME_ACC_CTI_BASE 0x6702000ull +#define DCORE3_MME_ACC_CTI_MAX_OFFSET 0x1000 +#define DCORE3_MME_ACC_CTI_SECTION 0x1000 +#define mmDCORE3_MME_ACC_ETF_BASE 0x6703000ull +#define DCORE3_MME_ACC_ETF_MAX_OFFSET 0x1000 +#define DCORE3_MME_ACC_ETF_SECTION 0x1000 +#define mmDCORE3_MME_ACC_SPMU_BASE 0x6704000ull +#define DCORE3_MME_ACC_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_MME_ACC_SPMU_SECTION 0x1000 +#define mmDCORE3_MME_ACC_CTI0_BASE 0x6705000ull +#define DCORE3_MME_ACC_CTI0_MAX_OFFSET 0x1000 +#define DCORE3_MME_ACC_CTI0_SECTION 0x1000 +#define mmDCORE3_MME_ACC_CTI1_BASE 0x6706000ull +#define DCORE3_MME_ACC_CTI1_MAX_OFFSET 0x1000 +#define DCORE3_MME_ACC_CTI1_SECTION 0x1000 +#define mmDCORE3_MME_ACC_BMON0_BASE 0x6707000ull +#define DCORE3_MME_ACC_BMON0_MAX_OFFSET 0x1000 +#define DCORE3_MME_ACC_BMON0_SECTION 0x1000 +#define mmDCORE3_MME_ACC_BMON1_BASE 0x6708000ull +#define DCORE3_MME_ACC_BMON1_MAX_OFFSET 0x1000 +#define DCORE3_MME_ACC_BMON1_SECTION 0x8000 +#define mmDCORE3_SM_CS_DBG_ROM_TBL_BASE 0x6710000ull +#define DCORE3_SM_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_SM_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_SM_STM_BASE 0x6711000ull +#define DCORE3_SM_STM_MAX_OFFSET 0x1000 +#define DCORE3_SM_STM_SECTION 0x1000 +#define mmDCORE3_SM_CTI_BASE 0x6712000ull +#define DCORE3_SM_CTI_MAX_OFFSET 0x1000 +#define DCORE3_SM_CTI_SECTION 0x1000 +#define mmDCORE3_SM_ETF_BASE 0x6713000ull +#define DCORE3_SM_ETF_MAX_OFFSET 0x1000 +#define DCORE3_SM_ETF_SECTION 0x1000 +#define mmDCORE3_SM_SPMU_BASE 0x6714000ull +#define DCORE3_SM_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_SM_SPMU_SECTION 0x1000 +#define mmDCORE3_SM_BMON_CTI_BASE 0x6715000ull +#define DCORE3_SM_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_SM_BMON_CTI_SECTION 0x1000 +#define mmDCORE3_SM_USER_CTI_BASE 0x6716000ull +#define DCORE3_SM_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_SM_USER_CTI_SECTION 0x1000 +#define mmDCORE3_SM_BMON_BASE 0x6717000ull +#define DCORE3_SM_BMON_MAX_OFFSET 0x1000 +#define DCORE3_SM_BMON_SECTION 0x1000 +#define mmDCORE3_SM_BMON1_BASE 0x6718000ull +#define DCORE3_SM_BMON1_MAX_OFFSET 0x1000 +#define DCORE3_SM_BMON1_SECTION 0x18000 +#define mmDCORE3_XFT_FUNNEL_BASE 0x6730000ull +#define DCORE3_XFT_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_XFT_FUNNEL_SECTION 0x8000 +#define mmDCORE3_TFT0_FUNNEL_BASE 0x6738000ull +#define DCORE3_TFT0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TFT0_FUNNEL_SECTION 0x1000 +#define mmDCORE3_TFT1_FUNNEL_BASE 0x6739000ull +#define DCORE3_TFT1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TFT1_FUNNEL_SECTION 0x1000 +#define mmDCORE3_TFT2_FUNNEL_BASE 0x673A000ull +#define DCORE3_TFT2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TFT2_FUNNEL_SECTION 0x7000 +#define mmDCORE3_RTR0_FUNNEL_BASE 0x6741000ull +#define DCORE3_RTR0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_RTR0_FUNNEL_SECTION 0x4000 +#define mmDCORE3_MIF0_FUNNEL_BASE 0x6745000ull +#define DCORE3_MIF0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_MIF0_FUNNEL_SECTION 0x4000 +#define mmDCORE3_RTR1_FUNNEL_BASE 0x6749000ull +#define DCORE3_RTR1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_RTR1_FUNNEL_SECTION 0x4000 +#define mmDCORE3_MIF1_FUNNEL_BASE 0x674D000ull +#define DCORE3_MIF1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_MIF1_FUNNEL_SECTION 0x4000 +#define mmDCORE3_RTR2_FUNNEL_BASE 0x6751000ull +#define DCORE3_RTR2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_RTR2_FUNNEL_SECTION 0x4000 +#define mmDCORE3_MIF2_FUNNEL_BASE 0x6755000ull +#define DCORE3_MIF2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_MIF2_FUNNEL_SECTION 0x4000 +#define mmDCORE3_RTR3_FUNNEL_BASE 0x6759000ull +#define DCORE3_RTR3_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_RTR3_FUNNEL_SECTION 0x4000 +#define mmDCORE3_MIF3_FUNNEL_BASE 0x675D000ull +#define DCORE3_MIF3_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_MIF3_FUNNEL_SECTION 0x4000 +#define mmDCORE3_RTR4_FUNNEL_BASE 0x6761000ull +#define DCORE3_RTR4_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_RTR4_FUNNEL_SECTION 0x8000 +#define mmDCORE3_RTR5_FUNNEL_BASE 0x6769000ull +#define DCORE3_RTR5_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_RTR5_FUNNEL_SECTION 0x8000 +#define mmDCORE3_RTR6_FUNNEL_BASE 0x6771000ull +#define DCORE3_RTR6_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_RTR6_FUNNEL_SECTION 0x8000 +#define mmDCORE3_RTR7_FUNNEL_BASE 0x6779000ull +#define DCORE3_RTR7_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_RTR7_FUNNEL_SECTION 0x47000 +#define mmDCORE3_EDMA0_CS_ROM_TBL_BASE 0x67C0000ull +#define DCORE3_EDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_EDMA0_CS_STM_BASE 0x67C1000ull +#define DCORE3_EDMA0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_CS_STM_SECTION 0x1000 +#define mmDCORE3_EDMA0_CS_CTI_BASE 0x67C2000ull +#define DCORE3_EDMA0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_CS_CTI_SECTION 0x1000 +#define mmDCORE3_EDMA0_CS_ETF_BASE 0x67C3000ull +#define DCORE3_EDMA0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_CS_ETF_SECTION 0x1000 +#define mmDCORE3_EDMA0_CS_SPMU_BASE 0x67C4000ull +#define DCORE3_EDMA0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_CS_SPMU_SECTION 0x1000 +#define mmDCORE3_EDMA0_BMON_CTI_BASE 0x67C5000ull +#define DCORE3_EDMA0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_BMON_CTI_SECTION 0x1000 +#define mmDCORE3_EDMA0_USER_CTI_BASE 0x67C6000ull +#define DCORE3_EDMA0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_USER_CTI_SECTION 0x1000 +#define mmDCORE3_EDMA0_BMON_0_BASE 0x67C7000ull +#define DCORE3_EDMA0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_BMON_0_SECTION 0x1000 +#define mmDCORE3_EDMA0_BMON_1_BASE 0x67C8000ull +#define DCORE3_EDMA0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_BMON_1_SECTION 0x1000 +#define mmDCORE3_EDMA0_QM_ARC_RTT_BASE 0x67C9000ull +#define DCORE3_EDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_EDMA0_QM_ARC_RTT_SECTION 0x7000 +#define mmDCORE3_EDMA1_CS_ROM_TBL_BASE 0x67D0000ull +#define DCORE3_EDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_EDMA1_CS_STM_BASE 0x67D1000ull +#define DCORE3_EDMA1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_CS_STM_SECTION 0x1000 +#define mmDCORE3_EDMA1_CS_CTI_BASE 0x67D2000ull +#define DCORE3_EDMA1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_CS_CTI_SECTION 0x1000 +#define mmDCORE3_EDMA1_CS_ETF_BASE 0x67D3000ull +#define DCORE3_EDMA1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_CS_ETF_SECTION 0x1000 +#define mmDCORE3_EDMA1_CS_SPMU_BASE 0x67D4000ull +#define DCORE3_EDMA1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_CS_SPMU_SECTION 0x1000 +#define mmDCORE3_EDMA1_BMON_CTI_BASE 0x67D5000ull +#define DCORE3_EDMA1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_BMON_CTI_SECTION 0x1000 +#define mmDCORE3_EDMA1_USER_CTI_BASE 0x67D6000ull +#define DCORE3_EDMA1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_USER_CTI_SECTION 0x1000 +#define mmDCORE3_EDMA1_BMON_0_BASE 0x67D7000ull +#define DCORE3_EDMA1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_BMON_0_SECTION 0x1000 +#define mmDCORE3_EDMA1_BMON_1_BASE 0x67D8000ull +#define DCORE3_EDMA1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_BMON_1_SECTION 0x1000 +#define mmDCORE3_EDMA1_QM_ARC_RTT_BASE 0x67D9000ull +#define DCORE3_EDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_EDMA1_QM_ARC_RTT_SECTION 0x7000 +#define mmDCORE3_VDEC0_CS_ROM_TBL_BASE 0x67E0000ull +#define DCORE3_VDEC0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_VDEC0_CS_STM_BASE 0x67E1000ull +#define DCORE3_VDEC0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_CS_STM_SECTION 0x1000 +#define mmDCORE3_VDEC0_CS_CTI_BASE 0x67E2000ull +#define DCORE3_VDEC0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_CS_CTI_SECTION 0x1000 +#define mmDCORE3_VDEC0_CS_ETF_BASE 0x67E3000ull +#define DCORE3_VDEC0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_CS_ETF_SECTION 0x1000 +#define mmDCORE3_VDEC0_CS_SPMU_BASE 0x67E4000ull +#define DCORE3_VDEC0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_CS_SPMU_SECTION 0x1000 +#define mmDCORE3_VDEC0_BMON_CTI_BASE 0x67E5000ull +#define DCORE3_VDEC0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_BMON_CTI_SECTION 0x1000 +#define mmDCORE3_VDEC0_USER_CTI_BASE 0x67E6000ull +#define DCORE3_VDEC0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_USER_CTI_SECTION 0x1000 +#define mmDCORE3_VDEC0_BMON_0_BASE 0x67E7000ull +#define DCORE3_VDEC0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_BMON_0_SECTION 0x1000 +#define mmDCORE3_VDEC0_BMON_1_BASE 0x67E8000ull +#define DCORE3_VDEC0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_BMON_1_SECTION 0x1000 +#define mmDCORE3_VDEC0_BMON_2_BASE 0x67E9000ull +#define DCORE3_VDEC0_BMON_2_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_BMON_2_SECTION 0x7000 +#define mmDCORE3_VDEC1_CS_ROM_TBL_BASE 0x67F0000ull +#define DCORE3_VDEC1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_CS_ROM_TBL_SECTION 0x1000 +#define mmDCORE3_VDEC1_CS_STM_BASE 0x67F1000ull +#define DCORE3_VDEC1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_CS_STM_SECTION 0x1000 +#define mmDCORE3_VDEC1_CS_CTI_BASE 0x67F2000ull +#define DCORE3_VDEC1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_CS_CTI_SECTION 0x1000 +#define mmDCORE3_VDEC1_CS_ETF_BASE 0x67F3000ull +#define DCORE3_VDEC1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_CS_ETF_SECTION 0x1000 +#define mmDCORE3_VDEC1_CS_SPMU_BASE 0x67F4000ull +#define DCORE3_VDEC1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_CS_SPMU_SECTION 0x1000 +#define mmDCORE3_VDEC1_BMON_CTI_BASE 0x67F5000ull +#define DCORE3_VDEC1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_BMON_CTI_SECTION 0x1000 +#define mmDCORE3_VDEC1_USER_CTI_BASE 0x67F6000ull +#define DCORE3_VDEC1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_USER_CTI_SECTION 0x1000 +#define mmDCORE3_VDEC1_BMON_0_BASE 0x67F7000ull +#define DCORE3_VDEC1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_BMON_0_SECTION 0x1000 +#define mmDCORE3_VDEC1_BMON_1_BASE 0x67F8000ull +#define DCORE3_VDEC1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_BMON_1_SECTION 0x1000 +#define mmDCORE3_VDEC1_BMON_2_BASE 0x67F9000ull +#define DCORE3_VDEC1_BMON_2_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_BMON_2_SECTION 0x7000 +#define mmCA53_BASE 0x6800000ull +#define CA53_MAX_OFFSET 0x141000 +#define CA53_SECTION 0x400000 +#define mmPCI_ROM_TABLE_BASE 0x6C00000ull +#define PCI_ROM_TABLE_MAX_OFFSET 0x1000 +#define PCI_ROM_TABLE_SECTION 0x1000 +#define mmPCIE_STM_BASE 0x6C01000ull +#define PCIE_STM_MAX_OFFSET 0x1000 +#define PCIE_STM_SECTION 0x1000 +#define mmPCIE_ETF_BASE 0x6C02000ull +#define PCIE_ETF_MAX_OFFSET 0x1000 +#define PCIE_ETF_SECTION 0x1000 +#define mmPCIE_CTI_0_BASE 0x6C03000ull +#define PCIE_CTI_0_MAX_OFFSET 0x1000 +#define PCIE_CTI_0_SECTION 0x1000 +#define mmPCIE_SPMU_BASE 0x6C04000ull +#define PCIE_SPMU_MAX_OFFSET 0x1000 +#define PCIE_SPMU_SECTION 0x1000 +#define mmPCIE_CTI_1_BASE 0x6C05000ull +#define PCIE_CTI_1_MAX_OFFSET 0x1000 +#define PCIE_CTI_1_SECTION 0x2000 +#define mmPCIE_BMON_MSTR_WR_BASE 0x6C07000ull +#define PCIE_BMON_MSTR_WR_MAX_OFFSET 0x1000 +#define PCIE_BMON_MSTR_WR_SECTION 0x1000 +#define mmPCIE_BMON_MSTR_RD_BASE 0x6C08000ull +#define PCIE_BMON_MSTR_RD_MAX_OFFSET 0x1000 +#define PCIE_BMON_MSTR_RD_SECTION 0x1000 +#define mmPCIE_BMON_SLV_WR_BASE 0x6C09000ull +#define PCIE_BMON_SLV_WR_MAX_OFFSET 0x1000 +#define PCIE_BMON_SLV_WR_SECTION 0x1000 +#define mmPCIE_BMON_SLV_RD_BASE 0x6C0A000ull +#define PCIE_BMON_SLV_RD_MAX_OFFSET 0x1000 +#define PCIE_BMON_SLV_RD_SECTION 0x36000 +#define mmTOP_ROM_TABLE_BASE 0x6C40000ull +#define TOP_ROM_TABLE_MAX_OFFSET 0x1000 +#define TOP_ROM_TABLE_SECTION 0x1000 +#define mmPSOC_CTI_BASE 0x6C41000ull +#define PSOC_CTI_MAX_OFFSET 0x1000 +#define PSOC_CTI_SECTION 0x1000 +#define mmPSOC_STM_BASE 0x6C42000ull +#define PSOC_STM_MAX_OFFSET 0x1000 +#define PSOC_STM_SECTION 0x1000 +#define mmPSOC_FUNNEL_BASE 0x6C43000ull +#define PSOC_FUNNEL_MAX_OFFSET 0x1000 +#define PSOC_FUNNEL_SECTION 0x1000 +#define mmPSOC_ETR_BASE 0x6C44000ull +#define PSOC_ETR_MAX_OFFSET 0x1000 +#define PSOC_ETR_SECTION 0x1000 +#define mmPSOC_ETF_BASE 0x6C45000ull +#define PSOC_ETF_MAX_OFFSET 0x1000 +#define PSOC_ETF_SECTION 0x1000 +#define mmPSOC_TS_CTI_BASE 0x6C46000ull +#define PSOC_TS_CTI_MAX_OFFSET 0x1000 +#define PSOC_TS_CTI_SECTION 0xA000 +#define mmPSOC_ARC0_CS_DBG_ROM_TBL_BASE 0x6C50000ull +#define PSOC_ARC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmPSOC_ARC0_CS_STM_BASE 0x6C51000ull +#define PSOC_ARC0_CS_STM_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CS_STM_SECTION 0x1000 +#define mmPSOC_ARC0_CS_CTI_BASE 0x6C52000ull +#define PSOC_ARC0_CS_CTI_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CS_CTI_SECTION 0x1000 +#define mmPSOC_ARC0_CS_ETF_BASE 0x6C53000ull +#define PSOC_ARC0_CS_ETF_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CS_ETF_SECTION 0x1000 +#define mmPSOC_ARC0_CS_SPMU_BASE 0x6C54000ull +#define PSOC_ARC0_CS_SPMU_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CS_SPMU_SECTION 0x1000 +#define mmPSOC_ARC0_BMON_CTI_BASE 0x6C55000ull +#define PSOC_ARC0_BMON_CTI_MAX_OFFSET 0x1000 +#define PSOC_ARC0_BMON_CTI_SECTION 0x1000 +#define mmPSOC_ARC0_USER_CTI_BASE 0x6C56000ull +#define PSOC_ARC0_USER_CTI_MAX_OFFSET 0x1000 +#define PSOC_ARC0_USER_CTI_SECTION 0x1000 +#define mmPSOC_ARC0_BMON_0_BASE 0x6C57000ull +#define PSOC_ARC0_BMON_0_MAX_OFFSET 0x1000 +#define PSOC_ARC0_BMON_0_SECTION 0x1000 +#define mmPSOC_ARC0_BMON_1_BASE 0x6C58000ull +#define PSOC_ARC0_BMON_1_MAX_OFFSET 0x1000 +#define PSOC_ARC0_BMON_1_SECTION 0x6000 +#define mmPSOC_ARC0_RTT_BASE 0x6C5E000ull +#define PSOC_ARC0_RTT_MAX_OFFSET 0x1400 +#define PSOC_ARC0_RTT_SECTION 0x1000 +#define mmPSOC_ARC0_FUNNEL_BASE 0x6C5F000ull +#define PSOC_ARC0_FUNNEL_MAX_OFFSET 0x1000 +#define PSOC_ARC0_FUNNEL_SECTION 0x1000 +#define mmPSOC_ARC1_CS_DBG_ROM_TBL_BASE 0x6C60000ull +#define PSOC_ARC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmPSOC_ARC1_CS_STM_BASE 0x6C61000ull +#define PSOC_ARC1_CS_STM_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CS_STM_SECTION 0x1000 +#define mmPSOC_ARC1_CS_CTI_BASE 0x6C62000ull +#define PSOC_ARC1_CS_CTI_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CS_CTI_SECTION 0x1000 +#define mmPSOC_ARC1_CS_ETF_BASE 0x6C63000ull +#define PSOC_ARC1_CS_ETF_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CS_ETF_SECTION 0x1000 +#define mmPSOC_ARC1_CS_SPMU_BASE 0x6C64000ull +#define PSOC_ARC1_CS_SPMU_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CS_SPMU_SECTION 0x1000 +#define mmPSOC_ARC1_BMON_CTI_BASE 0x6C65000ull +#define PSOC_ARC1_BMON_CTI_MAX_OFFSET 0x1000 +#define PSOC_ARC1_BMON_CTI_SECTION 0x1000 +#define mmPSOC_ARC1_USER_CTI_BASE 0x6C66000ull +#define PSOC_ARC1_USER_CTI_MAX_OFFSET 0x1000 +#define PSOC_ARC1_USER_CTI_SECTION 0x1000 +#define mmPSOC_ARC1_BMON_0_BASE 0x6C67000ull +#define PSOC_ARC1_BMON_0_MAX_OFFSET 0x1000 +#define PSOC_ARC1_BMON_0_SECTION 0x1000 +#define mmPSOC_ARC1_BMON_1_BASE 0x6C68000ull +#define PSOC_ARC1_BMON_1_MAX_OFFSET 0x1000 +#define PSOC_ARC1_BMON_1_SECTION 0x6000 +#define mmPSOC_ARC1_RTT_BASE 0x6C6E000ull +#define PSOC_ARC1_RTT_MAX_OFFSET 0x1400 +#define PSOC_ARC1_RTT_SECTION 0x1000 +#define mmPSOC_ARC1_FUNNEL_BASE 0x6C6F000ull +#define PSOC_ARC1_FUNNEL_MAX_OFFSET 0x1000 +#define PSOC_ARC1_FUNNEL_SECTION 0x1000 +#define mmPSOC_ARC0_CTI0_BASE 0x6C70000ull +#define PSOC_ARC0_CTI0_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CTI0_SECTION 0x1000 +#define mmPSOC_ARC0_CTI1_BASE 0x6C71000ull +#define PSOC_ARC0_CTI1_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CTI1_SECTION 0x1000 +#define mmPSOC_ARC0_CTI2_BASE 0x6C72000ull +#define PSOC_ARC0_CTI2_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CTI2_SECTION 0x1000 +#define mmPSOC_ARC0_CTI3_BASE 0x6C73000ull +#define PSOC_ARC0_CTI3_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CTI3_SECTION 0x1000 +#define mmPSOC_ARC1_CTI0_BASE 0x6C74000ull +#define PSOC_ARC1_CTI0_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CTI0_SECTION 0x1000 +#define mmPSOC_ARC1_CTI1_BASE 0x6C75000ull +#define PSOC_ARC1_CTI1_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CTI1_SECTION 0x1000 +#define mmPSOC_ARC1_CTI2_BASE 0x6C76000ull +#define PSOC_ARC1_CTI2_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CTI2_SECTION 0x1000 +#define mmPSOC_ARC1_CTI3_BASE 0x6C77000ull +#define PSOC_ARC1_CTI3_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CTI3_SECTION 0x9000 +#define mmPDMA0_CS_ROM_TBL_BASE 0x6C80000ull +#define PDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define PDMA0_CS_ROM_TBL_SECTION 0x1000 +#define mmPDMA0_CS_STM_BASE 0x6C81000ull +#define PDMA0_CS_STM_MAX_OFFSET 0x1000 +#define PDMA0_CS_STM_SECTION 0x1000 +#define mmPDMA0_CS_CTI_BASE 0x6C82000ull +#define PDMA0_CS_CTI_MAX_OFFSET 0x1000 +#define PDMA0_CS_CTI_SECTION 0x1000 +#define mmPDMA0_CS_ETF_BASE 0x6C83000ull +#define PDMA0_CS_ETF_MAX_OFFSET 0x1000 +#define PDMA0_CS_ETF_SECTION 0x1000 +#define mmPDMA0_CS_SPMU_BASE 0x6C84000ull +#define PDMA0_CS_SPMU_MAX_OFFSET 0x1000 +#define PDMA0_CS_SPMU_SECTION 0x1000 +#define mmPDMA0_BMON_CTI_BASE 0x6C85000ull +#define PDMA0_BMON_CTI_MAX_OFFSET 0x1000 +#define PDMA0_BMON_CTI_SECTION 0x1000 +#define mmPDMA0_USER_CTI_BASE 0x6C86000ull +#define PDMA0_USER_CTI_MAX_OFFSET 0x1000 +#define PDMA0_USER_CTI_SECTION 0x1000 +#define mmPDMA0_BMON_0_BASE 0x6C87000ull +#define PDMA0_BMON_0_MAX_OFFSET 0x1000 +#define PDMA0_BMON_0_SECTION 0x1000 +#define mmPDMA0_BMON_1_BASE 0x6C88000ull +#define PDMA0_BMON_1_MAX_OFFSET 0x1000 +#define PDMA0_BMON_1_SECTION 0x1000 +#define mmPDMA0_QM_ARC_RTT_BASE 0x6C89000ull +#define PDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define PDMA0_QM_ARC_RTT_SECTION 0x7000 +#define mmPDMA1_CS_ROM_TBL_BASE 0x6C90000ull +#define PDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define PDMA1_CS_ROM_TBL_SECTION 0x1000 +#define mmPDMA1_CS_STM_BASE 0x6C91000ull +#define PDMA1_CS_STM_MAX_OFFSET 0x1000 +#define PDMA1_CS_STM_SECTION 0x1000 +#define mmPDMA1_CS_CTI_BASE 0x6C92000ull +#define PDMA1_CS_CTI_MAX_OFFSET 0x1000 +#define PDMA1_CS_CTI_SECTION 0x1000 +#define mmPDMA1_CS_ETF_BASE 0x6C93000ull +#define PDMA1_CS_ETF_MAX_OFFSET 0x1000 +#define PDMA1_CS_ETF_SECTION 0x1000 +#define mmPDMA1_CS_SPMU_BASE 0x6C94000ull +#define PDMA1_CS_SPMU_MAX_OFFSET 0x1000 +#define PDMA1_CS_SPMU_SECTION 0x1000 +#define mmPDMA1_BMON_CTI_BASE 0x6C95000ull +#define PDMA1_BMON_CTI_MAX_OFFSET 0x1000 +#define PDMA1_BMON_CTI_SECTION 0x1000 +#define mmPDMA1_USER_CTI_BASE 0x6C96000ull +#define PDMA1_USER_CTI_MAX_OFFSET 0x1000 +#define PDMA1_USER_CTI_SECTION 0x1000 +#define mmPDMA1_BMON_0_BASE 0x6C97000ull +#define PDMA1_BMON_0_MAX_OFFSET 0x1000 +#define PDMA1_BMON_0_SECTION 0x1000 +#define mmPDMA1_BMON_1_BASE 0x6C98000ull +#define PDMA1_BMON_1_MAX_OFFSET 0x1000 +#define PDMA1_BMON_1_SECTION 0x1000 +#define mmPDMA1_QM_ARC_RTT_BASE 0x6C99000ull +#define PDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define PDMA1_QM_ARC_RTT_SECTION 0x7000 +#define mmXDMA_FUNNEL_BASE 0x6CA0000ull +#define XDMA_FUNNEL_MAX_OFFSET 0x1000 +#define XDMA_FUNNEL_SECTION 0x21000 +#define mmCPU_ETF_0_BASE 0x6CC1000ull +#define CPU_ETF_0_MAX_OFFSET 0x1000 +#define CPU_ETF_0_SECTION 0x1000 +#define mmCPU_ETF_1_BASE 0x6CC2000ull +#define CPU_ETF_1_MAX_OFFSET 0x1000 +#define CPU_ETF_1_SECTION 0x2000 +#define mmCPU_CTI_BASE 0x6CC4000ull +#define CPU_CTI_MAX_OFFSET 0x1000 +#define CPU_CTI_SECTION 0x1000 +#define mmCPU_FUNNEL_BASE 0x6CC5000ull +#define CPU_FUNNEL_MAX_OFFSET 0x1000 +#define CPU_FUNNEL_SECTION 0x1000 +#define mmCPU_STM_BASE 0x6CC6000ull +#define CPU_STM_MAX_OFFSET 0x1000 +#define CPU_STM_SECTION 0x1000 +#define mmCPU_CTI_TRACE_BASE 0x6CC7000ull +#define CPU_CTI_TRACE_MAX_OFFSET 0x1000 +#define CPU_CTI_TRACE_SECTION 0x1000 +#define mmCPU_ETF_TRACE_BASE 0x6CC8000ull +#define CPU_ETF_TRACE_MAX_OFFSET 0x1000 +#define CPU_ETF_TRACE_SECTION 0x1000 +#define mmCPU_WR_BMON_BASE 0x6CC9000ull +#define CPU_WR_BMON_MAX_OFFSET 0x1000 +#define CPU_WR_BMON_SECTION 0x1000 +#define mmCPU_RD_BMON_BASE 0x6CCA000ull +#define CPU_RD_BMON_MAX_OFFSET 0x1000 +#define CPU_RD_BMON_SECTION 0x36000 +#define mmPMMU_CS_DBG_ROM_TBL_BASE 0x6D00000ull +#define PMMU_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define PMMU_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmPMMU_CS_STM_BASE 0x6D01000ull +#define PMMU_CS_STM_MAX_OFFSET 0x1000 +#define PMMU_CS_STM_SECTION 0x1000 +#define mmPMMU_CS_CTI_BASE 0x6D02000ull +#define PMMU_CS_CTI_MAX_OFFSET 0x1000 +#define PMMU_CS_CTI_SECTION 0x1000 +#define mmPMMU_CS_ETF_BASE 0x6D03000ull +#define PMMU_CS_ETF_MAX_OFFSET 0x1000 +#define PMMU_CS_ETF_SECTION 0x1000 +#define mmPMMU_CS_SPMU_BASE 0x6D04000ull +#define PMMU_CS_SPMU_MAX_OFFSET 0x1000 +#define PMMU_CS_SPMU_SECTION 0x1000 +#define mmPMMU_BMON_CTI_BASE 0x6D05000ull +#define PMMU_BMON_CTI_MAX_OFFSET 0x1000 +#define PMMU_BMON_CTI_SECTION 0x1000 +#define mmPMMU_USER_CTI_BASE 0x6D06000ull +#define PMMU_USER_CTI_MAX_OFFSET 0x1000 +#define PMMU_USER_CTI_SECTION 0x1000 +#define mmPMMU_BMON_0_BASE 0x6D07000ull +#define PMMU_BMON_0_MAX_OFFSET 0x1000 +#define PMMU_BMON_0_SECTION 0x1000 +#define mmPMMU_BMON_1_BASE 0x6D08000ull +#define PMMU_BMON_1_MAX_OFFSET 0x1000 +#define PMMU_BMON_1_SECTION 0x1000 +#define mmPMMU_BMON_2_BASE 0x6D09000ull +#define PMMU_BMON_2_MAX_OFFSET 0x1000 +#define PMMU_BMON_2_SECTION 0x1000 +#define mmPMMU_BMON_3_BASE 0x6D0A000ull +#define PMMU_BMON_3_MAX_OFFSET 0x1000 +#define PMMU_BMON_3_SECTION 0x1000 +#define mmPMMU_BMON_4_BASE 0x6D0B000ull +#define PMMU_BMON_4_MAX_OFFSET 0x1000 +#define PMMU_BMON_4_SECTION 0x1000 +#define mmPMMU_FUNNEL_BASE 0x6D0C000ull +#define PMMU_FUNNEL_MAX_OFFSET 0x1000 +#define PMMU_FUNNEL_SECTION 0x1000 +#define mmPMMU_FUNNEL_DEC_BASE 0x6D0D000ull +#define PMMU_FUNNEL_DEC_MAX_OFFSET 0x1000 +#define PMMU_FUNNEL_DEC_SECTION 0x33000 +#define mmDCORE0_XBAR_MID_FUNNEL_BASE 0x6D40000ull +#define DCORE0_XBAR_MID_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_XBAR_MID_FUNNEL_SECTION 0x8000 +#define mmDCORE0_XBAR_EDGE_FUNNEL_BASE 0x6D48000ull +#define DCORE0_XBAR_EDGE_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_XBAR_EDGE_FUNNEL_SECTION 0x8000 +#define mmDCORE1_XBAR_MID_FUNNEL_BASE 0x6D50000ull +#define DCORE1_XBAR_MID_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_XBAR_MID_FUNNEL_SECTION 0x8000 +#define mmDCORE1_XBAR_EDGE_FUNNEL_BASE 0x6D58000ull +#define DCORE1_XBAR_EDGE_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_XBAR_EDGE_FUNNEL_SECTION 0x8000 +#define mmDCORE2_XBAR_MID_FUNNEL_BASE 0x6D60000ull +#define DCORE2_XBAR_MID_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_XBAR_MID_FUNNEL_SECTION 0x8000 +#define mmDCORE2_XBAR_EDGE_FUNNEL_BASE 0x6D68000ull +#define DCORE2_XBAR_EDGE_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_XBAR_EDGE_FUNNEL_SECTION 0x8000 +#define mmDCORE3_XBAR_MID_FUNNEL_BASE 0x6D70000ull +#define DCORE3_XBAR_MID_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_XBAR_MID_FUNNEL_SECTION 0x8000 +#define mmDCORE3_XBAR_EDGE_FUNNEL_BASE 0x6D78000ull +#define DCORE3_XBAR_EDGE_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_XBAR_EDGE_FUNNEL_SECTION 0x88000 +#define mmROT0_CS_ROM_TBL_BASE 0x6E00000ull +#define ROT0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define ROT0_CS_ROM_TBL_SECTION 0x1000 +#define mmROT0_CS_STM_BASE 0x6E01000ull +#define ROT0_CS_STM_MAX_OFFSET 0x1000 +#define ROT0_CS_STM_SECTION 0x1000 +#define mmROT0_CS_CTI_BASE 0x6E02000ull +#define ROT0_CS_CTI_MAX_OFFSET 0x1000 +#define ROT0_CS_CTI_SECTION 0x1000 +#define mmROT0_CS_ETF_BASE 0x6E03000ull +#define ROT0_CS_ETF_MAX_OFFSET 0x1000 +#define ROT0_CS_ETF_SECTION 0x1000 +#define mmROT0_CS_SPMU_BASE 0x6E04000ull +#define ROT0_CS_SPMU_MAX_OFFSET 0x1000 +#define ROT0_CS_SPMU_SECTION 0x1000 +#define mmROT0_BMON_CTI_BASE 0x6E05000ull +#define ROT0_BMON_CTI_MAX_OFFSET 0x1000 +#define ROT0_BMON_CTI_SECTION 0x1000 +#define mmROT0_USER_CTI_BASE 0x6E06000ull +#define ROT0_USER_CTI_MAX_OFFSET 0x1000 +#define ROT0_USER_CTI_SECTION 0x1000 +#define mmROT0_BMON_0_BASE 0x6E07000ull +#define ROT0_BMON_0_MAX_OFFSET 0x1000 +#define ROT0_BMON_0_SECTION 0x1000 +#define mmROT0_BMON_1_BASE 0x6E08000ull +#define ROT0_BMON_1_MAX_OFFSET 0x1000 +#define ROT0_BMON_1_SECTION 0x1000 +#define mmROT0_BMON_2_BASE 0x6E09000ull +#define ROT0_BMON_2_MAX_OFFSET 0x1000 +#define ROT0_BMON_2_SECTION 0x1000 +#define mmROT0_BMON_3_BASE 0x6E0A000ull +#define ROT0_BMON_3_MAX_OFFSET 0x1000 +#define ROT0_BMON_3_SECTION 0x1000 +#define mmROT0_ARC_RTT_BASE 0x6E0B000ull +#define ROT0_ARC_RTT_MAX_OFFSET 0x1400 +#define ROT0_ARC_RTT_SECTION 0x5000 +#define mmROT1_CS_ROM_TBL_BASE 0x6E10000ull +#define ROT1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define ROT1_CS_ROM_TBL_SECTION 0x1000 +#define mmROT1_CS_STM_BASE 0x6E11000ull +#define ROT1_CS_STM_MAX_OFFSET 0x1000 +#define ROT1_CS_STM_SECTION 0x1000 +#define mmROT1_CS_CTI_BASE 0x6E12000ull +#define ROT1_CS_CTI_MAX_OFFSET 0x1000 +#define ROT1_CS_CTI_SECTION 0x1000 +#define mmROT1_CS_ETF_BASE 0x6E13000ull +#define ROT1_CS_ETF_MAX_OFFSET 0x1000 +#define ROT1_CS_ETF_SECTION 0x1000 +#define mmROT1_CS_SPMU_BASE 0x6E14000ull +#define ROT1_CS_SPMU_MAX_OFFSET 0x1000 +#define ROT1_CS_SPMU_SECTION 0x1000 +#define mmROT1_BMON_CTI_BASE 0x6E15000ull +#define ROT1_BMON_CTI_MAX_OFFSET 0x1000 +#define ROT1_BMON_CTI_SECTION 0x1000 +#define mmROT1_USER_CTI_BASE 0x6E16000ull +#define ROT1_USER_CTI_MAX_OFFSET 0x1000 +#define ROT1_USER_CTI_SECTION 0x1000 +#define mmROT1_BMON_0_BASE 0x6E17000ull +#define ROT1_BMON_0_MAX_OFFSET 0x1000 +#define ROT1_BMON_0_SECTION 0x1000 +#define mmROT1_BMON_1_BASE 0x6E18000ull +#define ROT1_BMON_1_MAX_OFFSET 0x1000 +#define ROT1_BMON_1_SECTION 0x1000 +#define mmROT1_BMON_2_BASE 0x6E19000ull +#define ROT1_BMON_2_MAX_OFFSET 0x1000 +#define ROT1_BMON_2_SECTION 0x1000 +#define mmROT1_BMON_3_BASE 0x6E1A000ull +#define ROT1_BMON_3_MAX_OFFSET 0x1000 +#define ROT1_BMON_3_SECTION 0x1000 +#define mmROT1_ARC_RTT_BASE 0x6E1B000ull +#define ROT1_ARC_RTT_MAX_OFFSET 0x1400 +#define ROT1_ARC_RTT_SECTION 0x65000 +#define mmARC_FARM_ARC0_RTT_BASE 0x6E80000ull +#define ARC_FARM_ARC0_RTT_MAX_OFFSET 0x1400 +#define ARC_FARM_ARC0_RTT_SECTION 0x1000 +#define mmARC_FARM_ARC1_RTT_BASE 0x6E81000ull +#define ARC_FARM_ARC1_RTT_MAX_OFFSET 0x1400 +#define ARC_FARM_ARC1_RTT_SECTION 0x1000 +#define mmARC_FARM_ARC2_RTT_BASE 0x6E82000ull +#define ARC_FARM_ARC2_RTT_MAX_OFFSET 0x1400 +#define ARC_FARM_ARC2_RTT_SECTION 0x1000 +#define mmARC_FARM_ARC3_RTT_BASE 0x6E83000ull +#define ARC_FARM_ARC3_RTT_MAX_OFFSET 0x1400 +#define ARC_FARM_ARC3_RTT_SECTION 0xD000 +#define mmARC_FARM_CS_ROM_TBL_BASE 0x6E90000ull +#define ARC_FARM_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define ARC_FARM_CS_ROM_TBL_SECTION 0x1000 +#define mmARC_FARM_CS_STM_BASE 0x6E91000ull +#define ARC_FARM_CS_STM_MAX_OFFSET 0x1000 +#define ARC_FARM_CS_STM_SECTION 0x1000 +#define mmARC_FARM_CS_CTI_BASE 0x6E92000ull +#define ARC_FARM_CS_CTI_MAX_OFFSET 0x1000 +#define ARC_FARM_CS_CTI_SECTION 0x1000 +#define mmARC_FARM_CS_ETF_BASE 0x6E93000ull +#define ARC_FARM_CS_ETF_MAX_OFFSET 0x1000 +#define ARC_FARM_CS_ETF_SECTION 0x1000 +#define mmARC_FARM_CS_SPMU_BASE 0x6E94000ull +#define ARC_FARM_CS_SPMU_MAX_OFFSET 0x1000 +#define ARC_FARM_CS_SPMU_SECTION 0x1000 +#define mmARC_FARM_BMON_CTI_BASE 0x6E95000ull +#define ARC_FARM_BMON_CTI_MAX_OFFSET 0x1000 +#define ARC_FARM_BMON_CTI_SECTION 0x1000 +#define mmARC_FARM_USER_CTI_BASE 0x6E96000ull +#define ARC_FARM_USER_CTI_MAX_OFFSET 0x1000 +#define ARC_FARM_USER_CTI_SECTION 0x1000 +#define mmARC_FARM_BMON_0_BASE 0x6E97000ull +#define ARC_FARM_BMON_0_MAX_OFFSET 0x1000 +#define ARC_FARM_BMON_0_SECTION 0x1000 +#define mmARC_FARM_BMON_1_BASE 0x6E98000ull +#define ARC_FARM_BMON_1_MAX_OFFSET 0x1000 +#define ARC_FARM_BMON_1_SECTION 0x1000 +#define mmARC_FARM_BMON_2_BASE 0x6E99000ull +#define ARC_FARM_BMON_2_MAX_OFFSET 0x1000 +#define ARC_FARM_BMON_2_SECTION 0x1000 +#define mmARC_FARM_BMON_3_BASE 0x6E9A000ull +#define ARC_FARM_BMON_3_MAX_OFFSET 0x1000 +#define ARC_FARM_BMON_3_SECTION 0x1000 +#define mmARC_FARM_CTI_BASE 0x6E9B000ull +#define ARC_FARM_CTI_MAX_OFFSET 0x1000 +#define ARC_FARM_CTI_SECTION 0x1000 +#define mmARC_FARM_FUNNEL_BASE 0x6E9C000ull +#define ARC_FARM_FUNNEL_MAX_OFFSET 0x1000 +#define ARC_FARM_FUNNEL_SECTION 0x4000 +#define mmKDMA_CS_ROM_TBL_BASE 0x6EA0000ull +#define KDMA_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define KDMA_CS_ROM_TBL_SECTION 0x1000 +#define mmKDMA_CS_STM_BASE 0x6EA1000ull +#define KDMA_CS_STM_MAX_OFFSET 0x1000 +#define KDMA_CS_STM_SECTION 0x1000 +#define mmKDMA_CS_CTI_BASE 0x6EA2000ull +#define KDMA_CS_CTI_MAX_OFFSET 0x1000 +#define KDMA_CS_CTI_SECTION 0x1000 +#define mmKDMA_CS_ETF_BASE 0x6EA3000ull +#define KDMA_CS_ETF_MAX_OFFSET 0x1000 +#define KDMA_CS_ETF_SECTION 0x1000 +#define mmKDMA_CS_SPMU_BASE 0x6EA4000ull +#define KDMA_CS_SPMU_MAX_OFFSET 0x1000 +#define KDMA_CS_SPMU_SECTION 0x1000 +#define mmKDMA_BMON_CTI_BASE 0x6EA5000ull +#define KDMA_BMON_CTI_MAX_OFFSET 0x1000 +#define KDMA_BMON_CTI_SECTION 0x1000 +#define mmKDMA_USER_CTI_BASE 0x6EA6000ull +#define KDMA_USER_CTI_MAX_OFFSET 0x1000 +#define KDMA_USER_CTI_SECTION 0x1000 +#define mmKDMA_BMON_0_BASE 0x6EA7000ull +#define KDMA_BMON_0_MAX_OFFSET 0x1000 +#define KDMA_BMON_0_SECTION 0x1000 +#define mmKDMA_BMON_1_BASE 0x6EA8000ull +#define KDMA_BMON_1_MAX_OFFSET 0x1000 +#define KDMA_BMON_1_SECTION 0x1000 +#define mmKDMA_BMON_2_BASE 0x6EA9000ull +#define KDMA_BMON_2_MAX_OFFSET 0x1000 +#define KDMA_BMON_2_SECTION 0x1000 +#define mmKDMA_BMON_3_BASE 0x6EAA000ull +#define KDMA_BMON_3_MAX_OFFSET 0x1000 +#define KDMA_BMON_3_SECTION 0x56000 +#define mmPCIE_VDEC0_CS_DBG_ROM_TBL_BASE 0x6F00000ull +#define PCIE_VDEC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmPCIE_VDEC0_CS_STM_BASE 0x6F01000ull +#define PCIE_VDEC0_CS_STM_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_CS_STM_SECTION 0x1000 +#define mmPCIE_VDEC0_CS_CTI_BASE 0x6F02000ull +#define PCIE_VDEC0_CS_CTI_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_CS_CTI_SECTION 0x1000 +#define mmPCIE_VDEC0_CS_ETF_BASE 0x6F03000ull +#define PCIE_VDEC0_CS_ETF_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_CS_ETF_SECTION 0x1000 +#define mmPCIE_VDEC0_CS_SPMU_BASE 0x6F04000ull +#define PCIE_VDEC0_CS_SPMU_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_CS_SPMU_SECTION 0x1000 +#define mmPCIE_VDEC0_BMON_CTI_BASE 0x6F05000ull +#define PCIE_VDEC0_BMON_CTI_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_BMON_CTI_SECTION 0x1000 +#define mmPCIE_VDEC0_USER_CTI_BASE 0x6F06000ull +#define PCIE_VDEC0_USER_CTI_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_USER_CTI_SECTION 0x1000 +#define mmPCIE_VDEC0_BMON_0_BASE 0x6F07000ull +#define PCIE_VDEC0_BMON_0_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_BMON_0_SECTION 0x1000 +#define mmPCIE_VDEC0_BMON_1_BASE 0x6F08000ull +#define PCIE_VDEC0_BMON_1_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_BMON_1_SECTION 0x1000 +#define mmPCIE_VDEC0_BMON_2_BASE 0x6F09000ull +#define PCIE_VDEC0_BMON_2_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_BMON_2_SECTION 0x7000 +#define mmPCIE_VDEC1_CS_DBG_ROM_TBL_BASE 0x6F10000ull +#define PCIE_VDEC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmPCIE_VDEC1_CS_STM_BASE 0x6F11000ull +#define PCIE_VDEC1_CS_STM_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_CS_STM_SECTION 0x1000 +#define mmPCIE_VDEC1_CS_CTI_BASE 0x6F12000ull +#define PCIE_VDEC1_CS_CTI_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_CS_CTI_SECTION 0x1000 +#define mmPCIE_VDEC1_CS_ETF_BASE 0x6F13000ull +#define PCIE_VDEC1_CS_ETF_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_CS_ETF_SECTION 0x1000 +#define mmPCIE_VDEC1_CS_SPMU_BASE 0x6F14000ull +#define PCIE_VDEC1_CS_SPMU_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_CS_SPMU_SECTION 0x1000 +#define mmPCIE_VDEC1_BMON_CTI_BASE 0x6F15000ull +#define PCIE_VDEC1_BMON_CTI_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_BMON_CTI_SECTION 0x1000 +#define mmPCIE_VDEC1_USER_CTI_BASE 0x6F16000ull +#define PCIE_VDEC1_USER_CTI_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_USER_CTI_SECTION 0x1000 +#define mmPCIE_VDEC1_BMON_0_BASE 0x6F17000ull +#define PCIE_VDEC1_BMON_0_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_BMON_0_SECTION 0x1000 +#define mmPCIE_VDEC1_BMON_1_BASE 0x6F18000ull +#define PCIE_VDEC1_BMON_1_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_BMON_1_SECTION 0x1000 +#define mmPCIE_VDEC1_BMON_2_BASE 0x6F19000ull +#define PCIE_VDEC1_BMON_2_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_BMON_2_SECTION 0xF7000 +#define mmHBM0_MC0_CS_DBG_ROM_TBL_BASE 0x7010000ull +#define HBM0_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM0_MC0_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmHBM0_MC0_CS_STM_BASE 0x7011000ull +#define HBM0_MC0_CS_STM_MAX_OFFSET 0x1000 +#define HBM0_MC0_CS_STM_SECTION 0x1000 +#define mmHBM0_MC0_CS_CTI_BASE 0x7012000ull +#define HBM0_MC0_CS_CTI_MAX_OFFSET 0x1000 +#define HBM0_MC0_CS_CTI_SECTION 0x1000 +#define mmHBM0_MC0_CS_ETF_BASE 0x7013000ull +#define HBM0_MC0_CS_ETF_MAX_OFFSET 0x1000 +#define HBM0_MC0_CS_ETF_SECTION 0x1000 +#define mmHBM0_MC0_CS_SPMU_BASE 0x7014000ull +#define HBM0_MC0_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM0_MC0_CS_SPMU_SECTION 0x1000 +#define mmHBM0_MC0_BMON_CTI_BASE 0x7015000ull +#define HBM0_MC0_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM0_MC0_BMON_CTI_SECTION 0x1000 +#define mmHBM0_MC0_USER_CTI_BASE 0x7016000ull +#define HBM0_MC0_USER_CTI_MAX_OFFSET 0x1000 +#define HBM0_MC0_USER_CTI_SECTION 0xA000 +#define mmHBM0_MC0_FUNNEL_BASE 0x7020000ull +#define HBM0_MC0_FUNNEL_MAX_OFFSET 0x1000 +#define HBM0_MC0_FUNNEL_SECTION 0x30000 +#define mmHBM0_MC1_CS_DBG_ROM_TBL_BASE 0x7050000ull +#define HBM0_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM0_MC1_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmHBM0_MC1_CS_STM_BASE 0x7051000ull +#define HBM0_MC1_CS_STM_MAX_OFFSET 0x1000 +#define HBM0_MC1_CS_STM_SECTION 0x1000 +#define mmHBM0_MC1_CS_CTI_BASE 0x7052000ull +#define HBM0_MC1_CS_CTI_MAX_OFFSET 0x1000 +#define HBM0_MC1_CS_CTI_SECTION 0x1000 +#define mmHBM0_MC1_CS_ETF_BASE 0x7053000ull +#define HBM0_MC1_CS_ETF_MAX_OFFSET 0x1000 +#define HBM0_MC1_CS_ETF_SECTION 0x1000 +#define mmHBM0_MC1_CS_SPMU_BASE 0x7054000ull +#define HBM0_MC1_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM0_MC1_CS_SPMU_SECTION 0x1000 +#define mmHBM0_MC1_BMON_CTI_BASE 0x7055000ull +#define HBM0_MC1_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM0_MC1_BMON_CTI_SECTION 0x1000 +#define mmHBM0_MC1_USER_CTI_BASE 0x7056000ull +#define HBM0_MC1_USER_CTI_MAX_OFFSET 0x1000 +#define HBM0_MC1_USER_CTI_SECTION 0xA000 +#define mmHBM0_MC1_FUNNEL_BASE 0x7060000ull +#define HBM0_MC1_FUNNEL_MAX_OFFSET 0x1000 +#define HBM0_MC1_FUNNEL_SECTION 0x30000 +#define mmHBM1_MC0_CS_DBG_ROM_TBL_BASE 0x7090000ull +#define HBM1_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM1_MC0_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmHBM1_MC0_CS_STM_BASE 0x7091000ull +#define HBM1_MC0_CS_STM_MAX_OFFSET 0x1000 +#define HBM1_MC0_CS_STM_SECTION 0x1000 +#define mmHBM1_MC0_CS_CTI_BASE 0x7092000ull +#define HBM1_MC0_CS_CTI_MAX_OFFSET 0x1000 +#define HBM1_MC0_CS_CTI_SECTION 0x1000 +#define mmHBM1_MC0_CS_ETF_BASE 0x7093000ull +#define HBM1_MC0_CS_ETF_MAX_OFFSET 0x1000 +#define HBM1_MC0_CS_ETF_SECTION 0x1000 +#define mmHBM1_MC0_CS_SPMU_BASE 0x7094000ull +#define HBM1_MC0_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM1_MC0_CS_SPMU_SECTION 0x1000 +#define mmHBM1_MC0_BMON_CTI_BASE 0x7095000ull +#define HBM1_MC0_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM1_MC0_BMON_CTI_SECTION 0x1000 +#define mmHBM1_MC0_USER_CTI_BASE 0x7096000ull +#define HBM1_MC0_USER_CTI_MAX_OFFSET 0x1000 +#define HBM1_MC0_USER_CTI_SECTION 0xA000 +#define mmHBM1_MC0_FUNNEL_BASE 0x70A0000ull +#define HBM1_MC0_FUNNEL_MAX_OFFSET 0x1000 +#define HBM1_MC0_FUNNEL_SECTION 0x30000 +#define mmHBM1_MC1_CS_DBG_ROM_TBL_BASE 0x70D0000ull +#define HBM1_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM1_MC1_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmHBM1_MC1_CS_STM_BASE 0x70D1000ull +#define HBM1_MC1_CS_STM_MAX_OFFSET 0x1000 +#define HBM1_MC1_CS_STM_SECTION 0x1000 +#define mmHBM1_MC1_CS_CTI_BASE 0x70D2000ull +#define HBM1_MC1_CS_CTI_MAX_OFFSET 0x1000 +#define HBM1_MC1_CS_CTI_SECTION 0x1000 +#define mmHBM1_MC1_CS_ETF_BASE 0x70D3000ull +#define HBM1_MC1_CS_ETF_MAX_OFFSET 0x1000 +#define HBM1_MC1_CS_ETF_SECTION 0x1000 +#define mmHBM1_MC1_CS_SPMU_BASE 0x70D4000ull +#define HBM1_MC1_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM1_MC1_CS_SPMU_SECTION 0x1000 +#define mmHBM1_MC1_BMON_CTI_BASE 0x70D5000ull +#define HBM1_MC1_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM1_MC1_BMON_CTI_SECTION 0x1000 +#define mmHBM1_MC1_USER_CTI_BASE 0x70D6000ull +#define HBM1_MC1_USER_CTI_MAX_OFFSET 0x1000 +#define HBM1_MC1_USER_CTI_SECTION 0xA000 +#define mmHBM1_MC1_FUNNEL_BASE 0x70E0000ull +#define HBM1_MC1_FUNNEL_MAX_OFFSET 0x1000 +#define HBM1_MC1_FUNNEL_SECTION 0x30000 +#define mmHBM2_MC0_CS_DBG_ROM_TBL_BASE 0x7110000ull +#define HBM2_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM2_MC0_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmHBM2_MC0_CS_STM_BASE 0x7111000ull +#define HBM2_MC0_CS_STM_MAX_OFFSET 0x1000 +#define HBM2_MC0_CS_STM_SECTION 0x1000 +#define mmHBM2_MC0_CS_CTI_BASE 0x7112000ull +#define HBM2_MC0_CS_CTI_MAX_OFFSET 0x1000 +#define HBM2_MC0_CS_CTI_SECTION 0x1000 +#define mmHBM2_MC0_CS_ETF_BASE 0x7113000ull +#define HBM2_MC0_CS_ETF_MAX_OFFSET 0x1000 +#define HBM2_MC0_CS_ETF_SECTION 0x1000 +#define mmHBM2_MC0_CS_SPMU_BASE 0x7114000ull +#define HBM2_MC0_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM2_MC0_CS_SPMU_SECTION 0x1000 +#define mmHBM2_MC0_BMON_CTI_BASE 0x7115000ull +#define HBM2_MC0_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM2_MC0_BMON_CTI_SECTION 0x1000 +#define mmHBM2_MC0_USER_CTI_BASE 0x7116000ull +#define HBM2_MC0_USER_CTI_MAX_OFFSET 0x1000 +#define HBM2_MC0_USER_CTI_SECTION 0xA000 +#define mmHBM2_MC0_FUNNEL_BASE 0x7120000ull +#define HBM2_MC0_FUNNEL_MAX_OFFSET 0x1000 +#define HBM2_MC0_FUNNEL_SECTION 0x30000 +#define mmHBM2_MC1_CS_DBG_ROM_TBL_BASE 0x7150000ull +#define HBM2_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM2_MC1_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmHBM2_MC1_CS_STM_BASE 0x7151000ull +#define HBM2_MC1_CS_STM_MAX_OFFSET 0x1000 +#define HBM2_MC1_CS_STM_SECTION 0x1000 +#define mmHBM2_MC1_CS_CTI_BASE 0x7152000ull +#define HBM2_MC1_CS_CTI_MAX_OFFSET 0x1000 +#define HBM2_MC1_CS_CTI_SECTION 0x1000 +#define mmHBM2_MC1_CS_ETF_BASE 0x7153000ull +#define HBM2_MC1_CS_ETF_MAX_OFFSET 0x1000 +#define HBM2_MC1_CS_ETF_SECTION 0x1000 +#define mmHBM2_MC1_CS_SPMU_BASE 0x7154000ull +#define HBM2_MC1_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM2_MC1_CS_SPMU_SECTION 0x1000 +#define mmHBM2_MC1_BMON_CTI_BASE 0x7155000ull +#define HBM2_MC1_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM2_MC1_BMON_CTI_SECTION 0x1000 +#define mmHBM2_MC1_USER_CTI_BASE 0x7156000ull +#define HBM2_MC1_USER_CTI_MAX_OFFSET 0x1000 +#define HBM2_MC1_USER_CTI_SECTION 0xA000 +#define mmHBM2_MC1_FUNNEL_BASE 0x7160000ull +#define HBM2_MC1_FUNNEL_MAX_OFFSET 0x1000 +#define HBM2_MC1_FUNNEL_SECTION 0x30000 +#define mmHBM3_MC0_CS_DBG_ROM_TBL_BASE 0x7190000ull +#define HBM3_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM3_MC0_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmHBM3_MC0_CS_STM_BASE 0x7191000ull +#define HBM3_MC0_CS_STM_MAX_OFFSET 0x1000 +#define HBM3_MC0_CS_STM_SECTION 0x1000 +#define mmHBM3_MC0_CS_CTI_BASE 0x7192000ull +#define HBM3_MC0_CS_CTI_MAX_OFFSET 0x1000 +#define HBM3_MC0_CS_CTI_SECTION 0x1000 +#define mmHBM3_MC0_CS_ETF_BASE 0x7193000ull +#define HBM3_MC0_CS_ETF_MAX_OFFSET 0x1000 +#define HBM3_MC0_CS_ETF_SECTION 0x1000 +#define mmHBM3_MC0_CS_SPMU_BASE 0x7194000ull +#define HBM3_MC0_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM3_MC0_CS_SPMU_SECTION 0x1000 +#define mmHBM3_MC0_BMON_CTI_BASE 0x7195000ull +#define HBM3_MC0_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM3_MC0_BMON_CTI_SECTION 0x1000 +#define mmHBM3_MC0_USER_CTI_BASE 0x7196000ull +#define HBM3_MC0_USER_CTI_MAX_OFFSET 0x1000 +#define HBM3_MC0_USER_CTI_SECTION 0xA000 +#define mmHBM3_MC0_FUNNEL_BASE 0x71A0000ull +#define HBM3_MC0_FUNNEL_MAX_OFFSET 0x1000 +#define HBM3_MC0_FUNNEL_SECTION 0x30000 +#define mmHBM3_MC1_CS_DBG_ROM_TBL_BASE 0x71D0000ull +#define HBM3_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM3_MC1_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmHBM3_MC1_CS_STM_BASE 0x71D1000ull +#define HBM3_MC1_CS_STM_MAX_OFFSET 0x1000 +#define HBM3_MC1_CS_STM_SECTION 0x1000 +#define mmHBM3_MC1_CS_CTI_BASE 0x71D2000ull +#define HBM3_MC1_CS_CTI_MAX_OFFSET 0x1000 +#define HBM3_MC1_CS_CTI_SECTION 0x1000 +#define mmHBM3_MC1_CS_ETF_BASE 0x71D3000ull +#define HBM3_MC1_CS_ETF_MAX_OFFSET 0x1000 +#define HBM3_MC1_CS_ETF_SECTION 0x1000 +#define mmHBM3_MC1_CS_SPMU_BASE 0x71D4000ull +#define HBM3_MC1_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM3_MC1_CS_SPMU_SECTION 0x1000 +#define mmHBM3_MC1_BMON_CTI_BASE 0x71D5000ull +#define HBM3_MC1_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM3_MC1_BMON_CTI_SECTION 0x1000 +#define mmHBM3_MC1_USER_CTI_BASE 0x71D6000ull +#define HBM3_MC1_USER_CTI_MAX_OFFSET 0x1000 +#define HBM3_MC1_USER_CTI_SECTION 0xA000 +#define mmHBM3_MC1_FUNNEL_BASE 0x71E0000ull +#define HBM3_MC1_FUNNEL_MAX_OFFSET 0x1000 +#define HBM3_MC1_FUNNEL_SECTION 0x30000 +#define mmHBM4_MC0_CS_DBG_ROM_TBL_BASE 0x7210000ull +#define HBM4_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM4_MC0_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmHBM4_MC0_CS_STM_BASE 0x7211000ull +#define HBM4_MC0_CS_STM_MAX_OFFSET 0x1000 +#define HBM4_MC0_CS_STM_SECTION 0x1000 +#define mmHBM4_MC0_CS_CTI_BASE 0x7212000ull +#define HBM4_MC0_CS_CTI_MAX_OFFSET 0x1000 +#define HBM4_MC0_CS_CTI_SECTION 0x1000 +#define mmHBM4_MC0_CS_ETF_BASE 0x7213000ull +#define HBM4_MC0_CS_ETF_MAX_OFFSET 0x1000 +#define HBM4_MC0_CS_ETF_SECTION 0x1000 +#define mmHBM4_MC0_CS_SPMU_BASE 0x7214000ull +#define HBM4_MC0_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM4_MC0_CS_SPMU_SECTION 0x1000 +#define mmHBM4_MC0_BMON_CTI_BASE 0x7215000ull +#define HBM4_MC0_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM4_MC0_BMON_CTI_SECTION 0x1000 +#define mmHBM4_MC0_USER_CTI_BASE 0x7216000ull +#define HBM4_MC0_USER_CTI_MAX_OFFSET 0x1000 +#define HBM4_MC0_USER_CTI_SECTION 0xA000 +#define mmHBM4_MC0_FUNNEL_BASE 0x7220000ull +#define HBM4_MC0_FUNNEL_MAX_OFFSET 0x1000 +#define HBM4_MC0_FUNNEL_SECTION 0x30000 +#define mmHBM4_MC1_CS_DBG_ROM_TBL_BASE 0x7250000ull +#define HBM4_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM4_MC1_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmHBM4_MC1_CS_STM_BASE 0x7251000ull +#define HBM4_MC1_CS_STM_MAX_OFFSET 0x1000 +#define HBM4_MC1_CS_STM_SECTION 0x1000 +#define mmHBM4_MC1_CS_CTI_BASE 0x7252000ull +#define HBM4_MC1_CS_CTI_MAX_OFFSET 0x1000 +#define HBM4_MC1_CS_CTI_SECTION 0x1000 +#define mmHBM4_MC1_CS_ETF_BASE 0x7253000ull +#define HBM4_MC1_CS_ETF_MAX_OFFSET 0x1000 +#define HBM4_MC1_CS_ETF_SECTION 0x1000 +#define mmHBM4_MC1_CS_SPMU_BASE 0x7254000ull +#define HBM4_MC1_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM4_MC1_CS_SPMU_SECTION 0x1000 +#define mmHBM4_MC1_BMON_CTI_BASE 0x7255000ull +#define HBM4_MC1_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM4_MC1_BMON_CTI_SECTION 0x1000 +#define mmHBM4_MC1_USER_CTI_BASE 0x7256000ull +#define HBM4_MC1_USER_CTI_MAX_OFFSET 0x1000 +#define HBM4_MC1_USER_CTI_SECTION 0xA000 +#define mmHBM4_MC1_FUNNEL_BASE 0x7260000ull +#define HBM4_MC1_FUNNEL_MAX_OFFSET 0x1000 +#define HBM4_MC1_FUNNEL_SECTION 0x30000 +#define mmHBM5_MC0_CS_DBG_ROM_TBL_BASE 0x7290000ull +#define HBM5_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM5_MC0_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmHBM5_MC0_CS_STM_BASE 0x7291000ull +#define HBM5_MC0_CS_STM_MAX_OFFSET 0x1000 +#define HBM5_MC0_CS_STM_SECTION 0x1000 +#define mmHBM5_MC0_CS_CTI_BASE 0x7292000ull +#define HBM5_MC0_CS_CTI_MAX_OFFSET 0x1000 +#define HBM5_MC0_CS_CTI_SECTION 0x1000 +#define mmHBM5_MC0_CS_ETF_BASE 0x7293000ull +#define HBM5_MC0_CS_ETF_MAX_OFFSET 0x1000 +#define HBM5_MC0_CS_ETF_SECTION 0x1000 +#define mmHBM5_MC0_CS_SPMU_BASE 0x7294000ull +#define HBM5_MC0_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM5_MC0_CS_SPMU_SECTION 0x1000 +#define mmHBM5_MC0_BMON_CTI_BASE 0x7295000ull +#define HBM5_MC0_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM5_MC0_BMON_CTI_SECTION 0x1000 +#define mmHBM5_MC0_USER_CTI_BASE 0x7296000ull +#define HBM5_MC0_USER_CTI_MAX_OFFSET 0x1000 +#define HBM5_MC0_USER_CTI_SECTION 0xA000 +#define mmHBM5_MC0_FUNNEL_BASE 0x72A0000ull +#define HBM5_MC0_FUNNEL_MAX_OFFSET 0x1000 +#define HBM5_MC0_FUNNEL_SECTION 0x30000 +#define mmHBM5_MC1_CS_DBG_ROM_TBL_BASE 0x72D0000ull +#define HBM5_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM5_MC1_CS_DBG_ROM_TBL_SECTION 0x1000 +#define mmHBM5_MC1_CS_STM_BASE 0x72D1000ull +#define HBM5_MC1_CS_STM_MAX_OFFSET 0x1000 +#define HBM5_MC1_CS_STM_SECTION 0x1000 +#define mmHBM5_MC1_CS_CTI_BASE 0x72D2000ull +#define HBM5_MC1_CS_CTI_MAX_OFFSET 0x1000 +#define HBM5_MC1_CS_CTI_SECTION 0x1000 +#define mmHBM5_MC1_CS_ETF_BASE 0x72D3000ull +#define HBM5_MC1_CS_ETF_MAX_OFFSET 0x1000 +#define HBM5_MC1_CS_ETF_SECTION 0x1000 +#define mmHBM5_MC1_CS_SPMU_BASE 0x72D4000ull +#define HBM5_MC1_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM5_MC1_CS_SPMU_SECTION 0x1000 +#define mmHBM5_MC1_BMON_CTI_BASE 0x72D5000ull +#define HBM5_MC1_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM5_MC1_BMON_CTI_SECTION 0x1000 +#define mmHBM5_MC1_USER_CTI_BASE 0x72D6000ull +#define HBM5_MC1_USER_CTI_MAX_OFFSET 0x1000 +#define HBM5_MC1_USER_CTI_SECTION 0xA000 +#define mmHBM5_MC1_FUNNEL_BASE 0x72E0000ull +#define HBM5_MC1_FUNNEL_MAX_OFFSET 0x1000 +#define HBM5_MC1_FUNNEL_SECTION 0x20000 +#define mmNIC0_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7300000ull +#define NIC0_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 +#define mmNIC0_DBG_STM_0_BASE 0x7301000ull +#define NIC0_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_STM_0_SECTION 0x1000 +#define mmNIC0_DBG_CTI_0_BASE 0x7302000ull +#define NIC0_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_CTI_0_SECTION 0x1000 +#define mmNIC0_DBG_ETF_0_BASE 0x7303000ull +#define NIC0_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_ETF_0_SECTION 0x1000 +#define mmNIC0_DBG_SPMU_0_BASE 0x7304000ull +#define NIC0_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_SPMU_0_SECTION 0x1000 +#define mmNIC0_DBG_USER_CTI_0_BASE 0x7305000ull +#define NIC0_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_USER_CTI_0_SECTION 0x1000 +#define mmNIC0_DBG_BMON_CTI_0_BASE 0x7306000ull +#define NIC0_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_BMON_CTI_0_SECTION 0x1000 +#define mmNIC0_DBG_BMON0_0_BASE 0x7307000ull +#define NIC0_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_BMON0_0_SECTION 0x1000 +#define mmNIC0_DBG_BMON1_0_BASE 0x7308000ull +#define NIC0_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_BMON1_0_SECTION 0x1000 +#define mmNIC0_DBG_BMON2_0_BASE 0x7309000ull +#define NIC0_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_BMON2_0_SECTION 0x7000 +#define mmNIC0_DBG_ARC_RTT0_BASE 0x7310000ull +#define NIC0_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC0_DBG_ARC_RTT0_SECTION 0x10000 +#define mmNIC0_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7320000ull +#define NIC0_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 +#define mmNIC0_DBG_STM_1_BASE 0x7321000ull +#define NIC0_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_STM_1_SECTION 0x1000 +#define mmNIC0_DBG_CTI_1_BASE 0x7322000ull +#define NIC0_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_CTI_1_SECTION 0x1000 +#define mmNIC0_DBG_ETF_1_BASE 0x7323000ull +#define NIC0_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_ETF_1_SECTION 0x1000 +#define mmNIC0_DBG_SPMU_1_BASE 0x7324000ull +#define NIC0_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_SPMU_1_SECTION 0x1000 +#define mmNIC0_DBG_USER_CTI_1_BASE 0x7325000ull +#define NIC0_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_USER_CTI_1_SECTION 0x1000 +#define mmNIC0_DBG_BMON_CTI_1_BASE 0x7326000ull +#define NIC0_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_BMON_CTI_1_SECTION 0x1000 +#define mmNIC0_DBG_BMON0_1_BASE 0x7327000ull +#define NIC0_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_BMON0_1_SECTION 0x1000 +#define mmNIC0_DBG_BMON1_1_BASE 0x7328000ull +#define NIC0_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_BMON1_1_SECTION 0x1000 +#define mmNIC0_DBG_BMON2_1_BASE 0x7329000ull +#define NIC0_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_BMON2_1_SECTION 0x7000 +#define mmNIC0_DBG_ARC_RTT1_BASE 0x7330000ull +#define NIC0_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC0_DBG_ARC_RTT1_SECTION 0x8000 +#define mmNIC0_DBG_FUNNEL_TX_BASE 0x7338000ull +#define NIC0_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC0_DBG_FUNNEL_TX_SECTION 0x1000 +#define mmNIC0_DBG_FUNNEL_NCH_BASE 0x7339000ull +#define NIC0_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC0_DBG_FUNNEL_NCH_SECTION 0x7000 +#define mmNIC1_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7340000ull +#define NIC1_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 +#define mmNIC1_DBG_STM_0_BASE 0x7341000ull +#define NIC1_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_STM_0_SECTION 0x1000 +#define mmNIC1_DBG_CTI_0_BASE 0x7342000ull +#define NIC1_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_CTI_0_SECTION 0x1000 +#define mmNIC1_DBG_ETF_0_BASE 0x7343000ull +#define NIC1_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_ETF_0_SECTION 0x1000 +#define mmNIC1_DBG_SPMU_0_BASE 0x7344000ull +#define NIC1_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_SPMU_0_SECTION 0x1000 +#define mmNIC1_DBG_USER_CTI_0_BASE 0x7345000ull +#define NIC1_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_USER_CTI_0_SECTION 0x1000 +#define mmNIC1_DBG_BMON_CTI_0_BASE 0x7346000ull +#define NIC1_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_BMON_CTI_0_SECTION 0x1000 +#define mmNIC1_DBG_BMON0_0_BASE 0x7347000ull +#define NIC1_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_BMON0_0_SECTION 0x1000 +#define mmNIC1_DBG_BMON1_0_BASE 0x7348000ull +#define NIC1_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_BMON1_0_SECTION 0x1000 +#define mmNIC1_DBG_BMON2_0_BASE 0x7349000ull +#define NIC1_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_BMON2_0_SECTION 0x7000 +#define mmNIC1_DBG_ARC_RTT0_BASE 0x7350000ull +#define NIC1_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC1_DBG_ARC_RTT0_SECTION 0x10000 +#define mmNIC1_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7360000ull +#define NIC1_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 +#define mmNIC1_DBG_STM_1_BASE 0x7361000ull +#define NIC1_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_STM_1_SECTION 0x1000 +#define mmNIC1_DBG_CTI_1_BASE 0x7362000ull +#define NIC1_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_CTI_1_SECTION 0x1000 +#define mmNIC1_DBG_ETF_1_BASE 0x7363000ull +#define NIC1_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_ETF_1_SECTION 0x1000 +#define mmNIC1_DBG_SPMU_1_BASE 0x7364000ull +#define NIC1_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_SPMU_1_SECTION 0x1000 +#define mmNIC1_DBG_USER_CTI_1_BASE 0x7365000ull +#define NIC1_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_USER_CTI_1_SECTION 0x1000 +#define mmNIC1_DBG_BMON_CTI_1_BASE 0x7366000ull +#define NIC1_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_BMON_CTI_1_SECTION 0x1000 +#define mmNIC1_DBG_BMON0_1_BASE 0x7367000ull +#define NIC1_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_BMON0_1_SECTION 0x1000 +#define mmNIC1_DBG_BMON1_1_BASE 0x7368000ull +#define NIC1_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_BMON1_1_SECTION 0x1000 +#define mmNIC1_DBG_BMON2_1_BASE 0x7369000ull +#define NIC1_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_BMON2_1_SECTION 0x7000 +#define mmNIC1_DBG_ARC_RTT1_BASE 0x7370000ull +#define NIC1_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC1_DBG_ARC_RTT1_SECTION 0x8000 +#define mmNIC1_DBG_FUNNEL_TX_BASE 0x7378000ull +#define NIC1_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC1_DBG_FUNNEL_TX_SECTION 0x1000 +#define mmNIC1_DBG_FUNNEL_NCH_BASE 0x7379000ull +#define NIC1_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC1_DBG_FUNNEL_NCH_SECTION 0x7000 +#define mmNIC2_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7380000ull +#define NIC2_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 +#define mmNIC2_DBG_STM_0_BASE 0x7381000ull +#define NIC2_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_STM_0_SECTION 0x1000 +#define mmNIC2_DBG_CTI_0_BASE 0x7382000ull +#define NIC2_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_CTI_0_SECTION 0x1000 +#define mmNIC2_DBG_ETF_0_BASE 0x7383000ull +#define NIC2_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_ETF_0_SECTION 0x1000 +#define mmNIC2_DBG_SPMU_0_BASE 0x7384000ull +#define NIC2_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_SPMU_0_SECTION 0x1000 +#define mmNIC2_DBG_USER_CTI_0_BASE 0x7385000ull +#define NIC2_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_USER_CTI_0_SECTION 0x1000 +#define mmNIC2_DBG_BMON_CTI_0_BASE 0x7386000ull +#define NIC2_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_BMON_CTI_0_SECTION 0x1000 +#define mmNIC2_DBG_BMON0_0_BASE 0x7387000ull +#define NIC2_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_BMON0_0_SECTION 0x1000 +#define mmNIC2_DBG_BMON1_0_BASE 0x7388000ull +#define NIC2_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_BMON1_0_SECTION 0x1000 +#define mmNIC2_DBG_BMON2_0_BASE 0x7389000ull +#define NIC2_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_BMON2_0_SECTION 0x7000 +#define mmNIC2_DBG_ARC_RTT0_BASE 0x7390000ull +#define NIC2_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC2_DBG_ARC_RTT0_SECTION 0x10000 +#define mmNIC2_DBG_CS_DBG_ROM_TABLE_1_BASE 0x73A0000ull +#define NIC2_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 +#define mmNIC2_DBG_STM_1_BASE 0x73A1000ull +#define NIC2_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_STM_1_SECTION 0x1000 +#define mmNIC2_DBG_CTI_1_BASE 0x73A2000ull +#define NIC2_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_CTI_1_SECTION 0x1000 +#define mmNIC2_DBG_ETF_1_BASE 0x73A3000ull +#define NIC2_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_ETF_1_SECTION 0x1000 +#define mmNIC2_DBG_SPMU_1_BASE 0x73A4000ull +#define NIC2_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_SPMU_1_SECTION 0x1000 +#define mmNIC2_DBG_USER_CTI_1_BASE 0x73A5000ull +#define NIC2_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_USER_CTI_1_SECTION 0x1000 +#define mmNIC2_DBG_BMON_CTI_1_BASE 0x73A6000ull +#define NIC2_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_BMON_CTI_1_SECTION 0x1000 +#define mmNIC2_DBG_BMON0_1_BASE 0x73A7000ull +#define NIC2_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_BMON0_1_SECTION 0x1000 +#define mmNIC2_DBG_BMON1_1_BASE 0x73A8000ull +#define NIC2_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_BMON1_1_SECTION 0x1000 +#define mmNIC2_DBG_BMON2_1_BASE 0x73A9000ull +#define NIC2_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_BMON2_1_SECTION 0x7000 +#define mmNIC2_DBG_ARC_RTT1_BASE 0x73B0000ull +#define NIC2_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC2_DBG_ARC_RTT1_SECTION 0x8000 +#define mmNIC2_DBG_FUNNEL_TX_BASE 0x73B8000ull +#define NIC2_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC2_DBG_FUNNEL_TX_SECTION 0x1000 +#define mmNIC2_DBG_FUNNEL_NCH_BASE 0x73B9000ull +#define NIC2_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC2_DBG_FUNNEL_NCH_SECTION 0x7000 +#define mmNIC3_DBG_CS_DBG_ROM_TABLE_0_BASE 0x73C0000ull +#define NIC3_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 +#define mmNIC3_DBG_STM_0_BASE 0x73C1000ull +#define NIC3_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_STM_0_SECTION 0x1000 +#define mmNIC3_DBG_CTI_0_BASE 0x73C2000ull +#define NIC3_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_CTI_0_SECTION 0x1000 +#define mmNIC3_DBG_ETF_0_BASE 0x73C3000ull +#define NIC3_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_ETF_0_SECTION 0x1000 +#define mmNIC3_DBG_SPMU_0_BASE 0x73C4000ull +#define NIC3_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_SPMU_0_SECTION 0x1000 +#define mmNIC3_DBG_USER_CTI_0_BASE 0x73C5000ull +#define NIC3_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_USER_CTI_0_SECTION 0x1000 +#define mmNIC3_DBG_BMON_CTI_0_BASE 0x73C6000ull +#define NIC3_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_BMON_CTI_0_SECTION 0x1000 +#define mmNIC3_DBG_BMON0_0_BASE 0x73C7000ull +#define NIC3_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_BMON0_0_SECTION 0x1000 +#define mmNIC3_DBG_BMON1_0_BASE 0x73C8000ull +#define NIC3_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_BMON1_0_SECTION 0x1000 +#define mmNIC3_DBG_BMON2_0_BASE 0x73C9000ull +#define NIC3_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_BMON2_0_SECTION 0x7000 +#define mmNIC3_DBG_ARC_RTT0_BASE 0x73D0000ull +#define NIC3_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC3_DBG_ARC_RTT0_SECTION 0x10000 +#define mmNIC3_DBG_CS_DBG_ROM_TABLE_1_BASE 0x73E0000ull +#define NIC3_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 +#define mmNIC3_DBG_STM_1_BASE 0x73E1000ull +#define NIC3_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_STM_1_SECTION 0x1000 +#define mmNIC3_DBG_CTI_1_BASE 0x73E2000ull +#define NIC3_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_CTI_1_SECTION 0x1000 +#define mmNIC3_DBG_ETF_1_BASE 0x73E3000ull +#define NIC3_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_ETF_1_SECTION 0x1000 +#define mmNIC3_DBG_SPMU_1_BASE 0x73E4000ull +#define NIC3_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_SPMU_1_SECTION 0x1000 +#define mmNIC3_DBG_USER_CTI_1_BASE 0x73E5000ull +#define NIC3_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_USER_CTI_1_SECTION 0x1000 +#define mmNIC3_DBG_BMON_CTI_1_BASE 0x73E6000ull +#define NIC3_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_BMON_CTI_1_SECTION 0x1000 +#define mmNIC3_DBG_BMON0_1_BASE 0x73E7000ull +#define NIC3_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_BMON0_1_SECTION 0x1000 +#define mmNIC3_DBG_BMON1_1_BASE 0x73E8000ull +#define NIC3_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_BMON1_1_SECTION 0x1000 +#define mmNIC3_DBG_BMON2_1_BASE 0x73E9000ull +#define NIC3_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_BMON2_1_SECTION 0x7000 +#define mmNIC3_DBG_ARC_RTT1_BASE 0x73F0000ull +#define NIC3_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC3_DBG_ARC_RTT1_SECTION 0x8000 +#define mmNIC3_DBG_FUNNEL_TX_BASE 0x73F8000ull +#define NIC3_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC3_DBG_FUNNEL_TX_SECTION 0x1000 +#define mmNIC3_DBG_FUNNEL_NCH_BASE 0x73F9000ull +#define NIC3_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC3_DBG_FUNNEL_NCH_SECTION 0x7000 +#define mmNIC4_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7400000ull +#define NIC4_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 +#define mmNIC4_DBG_STM_0_BASE 0x7401000ull +#define NIC4_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_STM_0_SECTION 0x1000 +#define mmNIC4_DBG_CTI_0_BASE 0x7402000ull +#define NIC4_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_CTI_0_SECTION 0x1000 +#define mmNIC4_DBG_ETF_0_BASE 0x7403000ull +#define NIC4_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_ETF_0_SECTION 0x1000 +#define mmNIC4_DBG_SPMU_0_BASE 0x7404000ull +#define NIC4_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_SPMU_0_SECTION 0x1000 +#define mmNIC4_DBG_USER_CTI_0_BASE 0x7405000ull +#define NIC4_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_USER_CTI_0_SECTION 0x1000 +#define mmNIC4_DBG_BMON_CTI_0_BASE 0x7406000ull +#define NIC4_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_BMON_CTI_0_SECTION 0x1000 +#define mmNIC4_DBG_BMON0_0_BASE 0x7407000ull +#define NIC4_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_BMON0_0_SECTION 0x1000 +#define mmNIC4_DBG_BMON1_0_BASE 0x7408000ull +#define NIC4_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_BMON1_0_SECTION 0x1000 +#define mmNIC4_DBG_BMON2_0_BASE 0x7409000ull +#define NIC4_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_BMON2_0_SECTION 0x7000 +#define mmNIC4_DBG_ARC_RTT0_BASE 0x7410000ull +#define NIC4_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC4_DBG_ARC_RTT0_SECTION 0x10000 +#define mmNIC4_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7420000ull +#define NIC4_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 +#define mmNIC4_DBG_STM_1_BASE 0x7421000ull +#define NIC4_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_STM_1_SECTION 0x1000 +#define mmNIC4_DBG_CTI_1_BASE 0x7422000ull +#define NIC4_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_CTI_1_SECTION 0x1000 +#define mmNIC4_DBG_ETF_1_BASE 0x7423000ull +#define NIC4_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_ETF_1_SECTION 0x1000 +#define mmNIC4_DBG_SPMU_1_BASE 0x7424000ull +#define NIC4_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_SPMU_1_SECTION 0x1000 +#define mmNIC4_DBG_USER_CTI_1_BASE 0x7425000ull +#define NIC4_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_USER_CTI_1_SECTION 0x1000 +#define mmNIC4_DBG_BMON_CTI_1_BASE 0x7426000ull +#define NIC4_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_BMON_CTI_1_SECTION 0x1000 +#define mmNIC4_DBG_BMON0_1_BASE 0x7427000ull +#define NIC4_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_BMON0_1_SECTION 0x1000 +#define mmNIC4_DBG_BMON1_1_BASE 0x7428000ull +#define NIC4_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_BMON1_1_SECTION 0x1000 +#define mmNIC4_DBG_BMON2_1_BASE 0x7429000ull +#define NIC4_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_BMON2_1_SECTION 0x7000 +#define mmNIC4_DBG_ARC_RTT1_BASE 0x7430000ull +#define NIC4_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC4_DBG_ARC_RTT1_SECTION 0x8000 +#define mmNIC4_DBG_FUNNEL_TX_BASE 0x7438000ull +#define NIC4_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC4_DBG_FUNNEL_TX_SECTION 0x1000 +#define mmNIC4_DBG_FUNNEL_NCH_BASE 0x7439000ull +#define NIC4_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC4_DBG_FUNNEL_NCH_SECTION 0x7000 +#define mmNIC5_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7440000ull +#define NIC5_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 +#define mmNIC5_DBG_STM_0_BASE 0x7441000ull +#define NIC5_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_STM_0_SECTION 0x1000 +#define mmNIC5_DBG_CTI_0_BASE 0x7442000ull +#define NIC5_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_CTI_0_SECTION 0x1000 +#define mmNIC5_DBG_ETF_0_BASE 0x7443000ull +#define NIC5_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_ETF_0_SECTION 0x1000 +#define mmNIC5_DBG_SPMU_0_BASE 0x7444000ull +#define NIC5_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_SPMU_0_SECTION 0x1000 +#define mmNIC5_DBG_USER_CTI_0_BASE 0x7445000ull +#define NIC5_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_USER_CTI_0_SECTION 0x1000 +#define mmNIC5_DBG_BMON_CTI_0_BASE 0x7446000ull +#define NIC5_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_BMON_CTI_0_SECTION 0x1000 +#define mmNIC5_DBG_BMON0_0_BASE 0x7447000ull +#define NIC5_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_BMON0_0_SECTION 0x1000 +#define mmNIC5_DBG_BMON1_0_BASE 0x7448000ull +#define NIC5_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_BMON1_0_SECTION 0x1000 +#define mmNIC5_DBG_BMON2_0_BASE 0x7449000ull +#define NIC5_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_BMON2_0_SECTION 0x7000 +#define mmNIC5_DBG_ARC_RTT0_BASE 0x7450000ull +#define NIC5_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC5_DBG_ARC_RTT0_SECTION 0x10000 +#define mmNIC5_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7460000ull +#define NIC5_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 +#define mmNIC5_DBG_STM_1_BASE 0x7461000ull +#define NIC5_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_STM_1_SECTION 0x1000 +#define mmNIC5_DBG_CTI_1_BASE 0x7462000ull +#define NIC5_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_CTI_1_SECTION 0x1000 +#define mmNIC5_DBG_ETF_1_BASE 0x7463000ull +#define NIC5_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_ETF_1_SECTION 0x1000 +#define mmNIC5_DBG_SPMU_1_BASE 0x7464000ull +#define NIC5_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_SPMU_1_SECTION 0x1000 +#define mmNIC5_DBG_USER_CTI_1_BASE 0x7465000ull +#define NIC5_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_USER_CTI_1_SECTION 0x1000 +#define mmNIC5_DBG_BMON_CTI_1_BASE 0x7466000ull +#define NIC5_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_BMON_CTI_1_SECTION 0x1000 +#define mmNIC5_DBG_BMON0_1_BASE 0x7467000ull +#define NIC5_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_BMON0_1_SECTION 0x1000 +#define mmNIC5_DBG_BMON1_1_BASE 0x7468000ull +#define NIC5_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_BMON1_1_SECTION 0x1000 +#define mmNIC5_DBG_BMON2_1_BASE 0x7469000ull +#define NIC5_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_BMON2_1_SECTION 0x7000 +#define mmNIC5_DBG_ARC_RTT1_BASE 0x7470000ull +#define NIC5_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC5_DBG_ARC_RTT1_SECTION 0x8000 +#define mmNIC5_DBG_FUNNEL_TX_BASE 0x7478000ull +#define NIC5_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC5_DBG_FUNNEL_TX_SECTION 0x1000 +#define mmNIC5_DBG_FUNNEL_NCH_BASE 0x7479000ull +#define NIC5_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC5_DBG_FUNNEL_NCH_SECTION 0x7000 +#define mmNIC6_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7480000ull +#define NIC6_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 +#define mmNIC6_DBG_STM_0_BASE 0x7481000ull +#define NIC6_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_STM_0_SECTION 0x1000 +#define mmNIC6_DBG_CTI_0_BASE 0x7482000ull +#define NIC6_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_CTI_0_SECTION 0x1000 +#define mmNIC6_DBG_ETF_0_BASE 0x7483000ull +#define NIC6_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_ETF_0_SECTION 0x1000 +#define mmNIC6_DBG_SPMU_0_BASE 0x7484000ull +#define NIC6_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_SPMU_0_SECTION 0x1000 +#define mmNIC6_DBG_USER_CTI_0_BASE 0x7485000ull +#define NIC6_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_USER_CTI_0_SECTION 0x1000 +#define mmNIC6_DBG_BMON_CTI_0_BASE 0x7486000ull +#define NIC6_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_BMON_CTI_0_SECTION 0x1000 +#define mmNIC6_DBG_BMON0_0_BASE 0x7487000ull +#define NIC6_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_BMON0_0_SECTION 0x1000 +#define mmNIC6_DBG_BMON1_0_BASE 0x7488000ull +#define NIC6_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_BMON1_0_SECTION 0x1000 +#define mmNIC6_DBG_BMON2_0_BASE 0x7489000ull +#define NIC6_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_BMON2_0_SECTION 0x7000 +#define mmNIC6_DBG_ARC_RTT0_BASE 0x7490000ull +#define NIC6_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC6_DBG_ARC_RTT0_SECTION 0x10000 +#define mmNIC6_DBG_CS_DBG_ROM_TABLE_1_BASE 0x74A0000ull +#define NIC6_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 +#define mmNIC6_DBG_STM_1_BASE 0x74A1000ull +#define NIC6_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_STM_1_SECTION 0x1000 +#define mmNIC6_DBG_CTI_1_BASE 0x74A2000ull +#define NIC6_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_CTI_1_SECTION 0x1000 +#define mmNIC6_DBG_ETF_1_BASE 0x74A3000ull +#define NIC6_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_ETF_1_SECTION 0x1000 +#define mmNIC6_DBG_SPMU_1_BASE 0x74A4000ull +#define NIC6_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_SPMU_1_SECTION 0x1000 +#define mmNIC6_DBG_USER_CTI_1_BASE 0x74A5000ull +#define NIC6_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_USER_CTI_1_SECTION 0x1000 +#define mmNIC6_DBG_BMON_CTI_1_BASE 0x74A6000ull +#define NIC6_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_BMON_CTI_1_SECTION 0x1000 +#define mmNIC6_DBG_BMON0_1_BASE 0x74A7000ull +#define NIC6_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_BMON0_1_SECTION 0x1000 +#define mmNIC6_DBG_BMON1_1_BASE 0x74A8000ull +#define NIC6_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_BMON1_1_SECTION 0x1000 +#define mmNIC6_DBG_BMON2_1_BASE 0x74A9000ull +#define NIC6_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_BMON2_1_SECTION 0x7000 +#define mmNIC6_DBG_ARC_RTT1_BASE 0x74B0000ull +#define NIC6_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC6_DBG_ARC_RTT1_SECTION 0x8000 +#define mmNIC6_DBG_FUNNEL_TX_BASE 0x74B8000ull +#define NIC6_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC6_DBG_FUNNEL_TX_SECTION 0x1000 +#define mmNIC6_DBG_FUNNEL_NCH_BASE 0x74B9000ull +#define NIC6_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC6_DBG_FUNNEL_NCH_SECTION 0x7000 +#define mmNIC7_DBG_CS_DBG_ROM_TABLE_0_BASE 0x74C0000ull +#define NIC7_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 +#define mmNIC7_DBG_STM_0_BASE 0x74C1000ull +#define NIC7_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_STM_0_SECTION 0x1000 +#define mmNIC7_DBG_CTI_0_BASE 0x74C2000ull +#define NIC7_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_CTI_0_SECTION 0x1000 +#define mmNIC7_DBG_ETF_0_BASE 0x74C3000ull +#define NIC7_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_ETF_0_SECTION 0x1000 +#define mmNIC7_DBG_SPMU_0_BASE 0x74C4000ull +#define NIC7_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_SPMU_0_SECTION 0x1000 +#define mmNIC7_DBG_USER_CTI_0_BASE 0x74C5000ull +#define NIC7_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_USER_CTI_0_SECTION 0x1000 +#define mmNIC7_DBG_BMON_CTI_0_BASE 0x74C6000ull +#define NIC7_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_BMON_CTI_0_SECTION 0x1000 +#define mmNIC7_DBG_BMON0_0_BASE 0x74C7000ull +#define NIC7_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_BMON0_0_SECTION 0x1000 +#define mmNIC7_DBG_BMON1_0_BASE 0x74C8000ull +#define NIC7_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_BMON1_0_SECTION 0x1000 +#define mmNIC7_DBG_BMON2_0_BASE 0x74C9000ull +#define NIC7_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_BMON2_0_SECTION 0x7000 +#define mmNIC7_DBG_ARC_RTT0_BASE 0x74D0000ull +#define NIC7_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC7_DBG_ARC_RTT0_SECTION 0x10000 +#define mmNIC7_DBG_CS_DBG_ROM_TABLE_1_BASE 0x74E0000ull +#define NIC7_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 +#define mmNIC7_DBG_STM_1_BASE 0x74E1000ull +#define NIC7_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_STM_1_SECTION 0x1000 +#define mmNIC7_DBG_CTI_1_BASE 0x74E2000ull +#define NIC7_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_CTI_1_SECTION 0x1000 +#define mmNIC7_DBG_ETF_1_BASE 0x74E3000ull +#define NIC7_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_ETF_1_SECTION 0x1000 +#define mmNIC7_DBG_SPMU_1_BASE 0x74E4000ull +#define NIC7_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_SPMU_1_SECTION 0x1000 +#define mmNIC7_DBG_USER_CTI_1_BASE 0x74E5000ull +#define NIC7_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_USER_CTI_1_SECTION 0x1000 +#define mmNIC7_DBG_BMON_CTI_1_BASE 0x74E6000ull +#define NIC7_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_BMON_CTI_1_SECTION 0x1000 +#define mmNIC7_DBG_BMON0_1_BASE 0x74E7000ull +#define NIC7_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_BMON0_1_SECTION 0x1000 +#define mmNIC7_DBG_BMON1_1_BASE 0x74E8000ull +#define NIC7_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_BMON1_1_SECTION 0x1000 +#define mmNIC7_DBG_BMON2_1_BASE 0x74E9000ull +#define NIC7_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_BMON2_1_SECTION 0x7000 +#define mmNIC7_DBG_ARC_RTT1_BASE 0x74F0000ull +#define NIC7_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC7_DBG_ARC_RTT1_SECTION 0x8000 +#define mmNIC7_DBG_FUNNEL_TX_BASE 0x74F8000ull +#define NIC7_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC7_DBG_FUNNEL_TX_SECTION 0x1000 +#define mmNIC7_DBG_FUNNEL_NCH_BASE 0x74F9000ull +#define NIC7_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC7_DBG_FUNNEL_NCH_SECTION 0x7000 +#define mmNIC8_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7500000ull +#define NIC8_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 +#define mmNIC8_DBG_STM_0_BASE 0x7501000ull +#define NIC8_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_STM_0_SECTION 0x1000 +#define mmNIC8_DBG_CTI_0_BASE 0x7502000ull +#define NIC8_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_CTI_0_SECTION 0x1000 +#define mmNIC8_DBG_ETF_0_BASE 0x7503000ull +#define NIC8_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_ETF_0_SECTION 0x1000 +#define mmNIC8_DBG_SPMU_0_BASE 0x7504000ull +#define NIC8_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_SPMU_0_SECTION 0x1000 +#define mmNIC8_DBG_USER_CTI_0_BASE 0x7505000ull +#define NIC8_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_USER_CTI_0_SECTION 0x1000 +#define mmNIC8_DBG_BMON_CTI_0_BASE 0x7506000ull +#define NIC8_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_BMON_CTI_0_SECTION 0x1000 +#define mmNIC8_DBG_BMON0_0_BASE 0x7507000ull +#define NIC8_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_BMON0_0_SECTION 0x1000 +#define mmNIC8_DBG_BMON1_0_BASE 0x7508000ull +#define NIC8_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_BMON1_0_SECTION 0x1000 +#define mmNIC8_DBG_BMON2_0_BASE 0x7509000ull +#define NIC8_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_BMON2_0_SECTION 0x7000 +#define mmNIC8_DBG_ARC_RTT0_BASE 0x7510000ull +#define NIC8_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC8_DBG_ARC_RTT0_SECTION 0x10000 +#define mmNIC8_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7520000ull +#define NIC8_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 +#define mmNIC8_DBG_STM_1_BASE 0x7521000ull +#define NIC8_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_STM_1_SECTION 0x1000 +#define mmNIC8_DBG_CTI_1_BASE 0x7522000ull +#define NIC8_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_CTI_1_SECTION 0x1000 +#define mmNIC8_DBG_ETF_1_BASE 0x7523000ull +#define NIC8_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_ETF_1_SECTION 0x1000 +#define mmNIC8_DBG_SPMU_1_BASE 0x7524000ull +#define NIC8_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_SPMU_1_SECTION 0x1000 +#define mmNIC8_DBG_USER_CTI_1_BASE 0x7525000ull +#define NIC8_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_USER_CTI_1_SECTION 0x1000 +#define mmNIC8_DBG_BMON_CTI_1_BASE 0x7526000ull +#define NIC8_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_BMON_CTI_1_SECTION 0x1000 +#define mmNIC8_DBG_BMON0_1_BASE 0x7527000ull +#define NIC8_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_BMON0_1_SECTION 0x1000 +#define mmNIC8_DBG_BMON1_1_BASE 0x7528000ull +#define NIC8_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_BMON1_1_SECTION 0x1000 +#define mmNIC8_DBG_BMON2_1_BASE 0x7529000ull +#define NIC8_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_BMON2_1_SECTION 0x7000 +#define mmNIC8_DBG_ARC_RTT1_BASE 0x7530000ull +#define NIC8_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC8_DBG_ARC_RTT1_SECTION 0x8000 +#define mmNIC8_DBG_FUNNEL_TX_BASE 0x7538000ull +#define NIC8_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC8_DBG_FUNNEL_TX_SECTION 0x1000 +#define mmNIC8_DBG_FUNNEL_NCH_BASE 0x7539000ull +#define NIC8_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC8_DBG_FUNNEL_NCH_SECTION 0x7000 +#define mmNIC9_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7540000ull +#define NIC9_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 +#define mmNIC9_DBG_STM_0_BASE 0x7541000ull +#define NIC9_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_STM_0_SECTION 0x1000 +#define mmNIC9_DBG_CTI_0_BASE 0x7542000ull +#define NIC9_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_CTI_0_SECTION 0x1000 +#define mmNIC9_DBG_ETF_0_BASE 0x7543000ull +#define NIC9_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_ETF_0_SECTION 0x1000 +#define mmNIC9_DBG_SPMU_0_BASE 0x7544000ull +#define NIC9_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_SPMU_0_SECTION 0x1000 +#define mmNIC9_DBG_USER_CTI_0_BASE 0x7545000ull +#define NIC9_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_USER_CTI_0_SECTION 0x1000 +#define mmNIC9_DBG_BMON_CTI_0_BASE 0x7546000ull +#define NIC9_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_BMON_CTI_0_SECTION 0x1000 +#define mmNIC9_DBG_BMON0_0_BASE 0x7547000ull +#define NIC9_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_BMON0_0_SECTION 0x1000 +#define mmNIC9_DBG_BMON1_0_BASE 0x7548000ull +#define NIC9_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_BMON1_0_SECTION 0x1000 +#define mmNIC9_DBG_BMON2_0_BASE 0x7549000ull +#define NIC9_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_BMON2_0_SECTION 0x7000 +#define mmNIC9_DBG_ARC_RTT0_BASE 0x7550000ull +#define NIC9_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC9_DBG_ARC_RTT0_SECTION 0x10000 +#define mmNIC9_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7560000ull +#define NIC9_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 +#define mmNIC9_DBG_STM_1_BASE 0x7561000ull +#define NIC9_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_STM_1_SECTION 0x1000 +#define mmNIC9_DBG_CTI_1_BASE 0x7562000ull +#define NIC9_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_CTI_1_SECTION 0x1000 +#define mmNIC9_DBG_ETF_1_BASE 0x7563000ull +#define NIC9_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_ETF_1_SECTION 0x1000 +#define mmNIC9_DBG_SPMU_1_BASE 0x7564000ull +#define NIC9_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_SPMU_1_SECTION 0x1000 +#define mmNIC9_DBG_USER_CTI_1_BASE 0x7565000ull +#define NIC9_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_USER_CTI_1_SECTION 0x1000 +#define mmNIC9_DBG_BMON_CTI_1_BASE 0x7566000ull +#define NIC9_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_BMON_CTI_1_SECTION 0x1000 +#define mmNIC9_DBG_BMON0_1_BASE 0x7567000ull +#define NIC9_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_BMON0_1_SECTION 0x1000 +#define mmNIC9_DBG_BMON1_1_BASE 0x7568000ull +#define NIC9_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_BMON1_1_SECTION 0x1000 +#define mmNIC9_DBG_BMON2_1_BASE 0x7569000ull +#define NIC9_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_BMON2_1_SECTION 0x7000 +#define mmNIC9_DBG_ARC_RTT1_BASE 0x7570000ull +#define NIC9_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC9_DBG_ARC_RTT1_SECTION 0x8000 +#define mmNIC9_DBG_FUNNEL_TX_BASE 0x7578000ull +#define NIC9_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC9_DBG_FUNNEL_TX_SECTION 0x1000 +#define mmNIC9_DBG_FUNNEL_NCH_BASE 0x7579000ull +#define NIC9_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC9_DBG_FUNNEL_NCH_SECTION 0x7000 +#define mmNIC10_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7580000ull +#define NIC10_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 +#define mmNIC10_DBG_STM_0_BASE 0x7581000ull +#define NIC10_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_STM_0_SECTION 0x1000 +#define mmNIC10_DBG_CTI_0_BASE 0x7582000ull +#define NIC10_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_CTI_0_SECTION 0x1000 +#define mmNIC10_DBG_ETF_0_BASE 0x7583000ull +#define NIC10_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_ETF_0_SECTION 0x1000 +#define mmNIC10_DBG_SPMU_0_BASE 0x7584000ull +#define NIC10_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_SPMU_0_SECTION 0x1000 +#define mmNIC10_DBG_USER_CTI_0_BASE 0x7585000ull +#define NIC10_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_USER_CTI_0_SECTION 0x1000 +#define mmNIC10_DBG_BMON_CTI_0_BASE 0x7586000ull +#define NIC10_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_BMON_CTI_0_SECTION 0x1000 +#define mmNIC10_DBG_BMON0_0_BASE 0x7587000ull +#define NIC10_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_BMON0_0_SECTION 0x1000 +#define mmNIC10_DBG_BMON1_0_BASE 0x7588000ull +#define NIC10_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_BMON1_0_SECTION 0x1000 +#define mmNIC10_DBG_BMON2_0_BASE 0x7589000ull +#define NIC10_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_BMON2_0_SECTION 0x7000 +#define mmNIC10_DBG_ARC_RTT0_BASE 0x7590000ull +#define NIC10_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC10_DBG_ARC_RTT0_SECTION 0x10000 +#define mmNIC10_DBG_CS_DBG_ROM_TABLE_1_BASE 0x75A0000ull +#define NIC10_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 +#define mmNIC10_DBG_STM_1_BASE 0x75A1000ull +#define NIC10_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_STM_1_SECTION 0x1000 +#define mmNIC10_DBG_CTI_1_BASE 0x75A2000ull +#define NIC10_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_CTI_1_SECTION 0x1000 +#define mmNIC10_DBG_ETF_1_BASE 0x75A3000ull +#define NIC10_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_ETF_1_SECTION 0x1000 +#define mmNIC10_DBG_SPMU_1_BASE 0x75A4000ull +#define NIC10_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_SPMU_1_SECTION 0x1000 +#define mmNIC10_DBG_USER_CTI_1_BASE 0x75A5000ull +#define NIC10_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_USER_CTI_1_SECTION 0x1000 +#define mmNIC10_DBG_BMON_CTI_1_BASE 0x75A6000ull +#define NIC10_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_BMON_CTI_1_SECTION 0x1000 +#define mmNIC10_DBG_BMON0_1_BASE 0x75A7000ull +#define NIC10_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_BMON0_1_SECTION 0x1000 +#define mmNIC10_DBG_BMON1_1_BASE 0x75A8000ull +#define NIC10_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_BMON1_1_SECTION 0x1000 +#define mmNIC10_DBG_BMON2_1_BASE 0x75A9000ull +#define NIC10_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_BMON2_1_SECTION 0x7000 +#define mmNIC10_DBG_ARC_RTT1_BASE 0x75B0000ull +#define NIC10_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC10_DBG_ARC_RTT1_SECTION 0x8000 +#define mmNIC10_DBG_FUNNEL_TX_BASE 0x75B8000ull +#define NIC10_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC10_DBG_FUNNEL_TX_SECTION 0x1000 +#define mmNIC10_DBG_FUNNEL_NCH_BASE 0x75B9000ull +#define NIC10_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC10_DBG_FUNNEL_NCH_SECTION 0x7000 +#define mmNIC11_DBG_CS_DBG_ROM_TABLE_0_BASE 0x75C0000ull +#define NIC11_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 +#define mmNIC11_DBG_STM_0_BASE 0x75C1000ull +#define NIC11_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_STM_0_SECTION 0x1000 +#define mmNIC11_DBG_CTI_0_BASE 0x75C2000ull +#define NIC11_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_CTI_0_SECTION 0x1000 +#define mmNIC11_DBG_ETF_0_BASE 0x75C3000ull +#define NIC11_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_ETF_0_SECTION 0x1000 +#define mmNIC11_DBG_SPMU_0_BASE 0x75C4000ull +#define NIC11_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_SPMU_0_SECTION 0x1000 +#define mmNIC11_DBG_USER_CTI_0_BASE 0x75C5000ull +#define NIC11_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_USER_CTI_0_SECTION 0x1000 +#define mmNIC11_DBG_BMON_CTI_0_BASE 0x75C6000ull +#define NIC11_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_BMON_CTI_0_SECTION 0x1000 +#define mmNIC11_DBG_BMON0_0_BASE 0x75C7000ull +#define NIC11_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_BMON0_0_SECTION 0x1000 +#define mmNIC11_DBG_BMON1_0_BASE 0x75C8000ull +#define NIC11_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_BMON1_0_SECTION 0x1000 +#define mmNIC11_DBG_BMON2_0_BASE 0x75C9000ull +#define NIC11_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_BMON2_0_SECTION 0x7000 +#define mmNIC11_DBG_ARC_RTT0_BASE 0x75D0000ull +#define NIC11_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC11_DBG_ARC_RTT0_SECTION 0x10000 +#define mmNIC11_DBG_CS_DBG_ROM_TABLE_1_BASE 0x75E0000ull +#define NIC11_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 +#define mmNIC11_DBG_STM_1_BASE 0x75E1000ull +#define NIC11_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_STM_1_SECTION 0x1000 +#define mmNIC11_DBG_CTI_1_BASE 0x75E2000ull +#define NIC11_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_CTI_1_SECTION 0x1000 +#define mmNIC11_DBG_ETF_1_BASE 0x75E3000ull +#define NIC11_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_ETF_1_SECTION 0x1000 +#define mmNIC11_DBG_SPMU_1_BASE 0x75E4000ull +#define NIC11_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_SPMU_1_SECTION 0x1000 +#define mmNIC11_DBG_USER_CTI_1_BASE 0x75E5000ull +#define NIC11_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_USER_CTI_1_SECTION 0x1000 +#define mmNIC11_DBG_BMON_CTI_1_BASE 0x75E6000ull +#define NIC11_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_BMON_CTI_1_SECTION 0x1000 +#define mmNIC11_DBG_BMON0_1_BASE 0x75E7000ull +#define NIC11_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_BMON0_1_SECTION 0x1000 +#define mmNIC11_DBG_BMON1_1_BASE 0x75E8000ull +#define NIC11_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_BMON1_1_SECTION 0x1000 +#define mmNIC11_DBG_BMON2_1_BASE 0x75E9000ull +#define NIC11_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_BMON2_1_SECTION 0x7000 +#define mmNIC11_DBG_ARC_RTT1_BASE 0x75F0000ull +#define NIC11_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC11_DBG_ARC_RTT1_SECTION 0x8000 +#define mmNIC11_DBG_FUNNEL_TX_BASE 0x75F8000ull +#define NIC11_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC11_DBG_FUNNEL_TX_SECTION 0x1000 +#define mmNIC11_DBG_FUNNEL_NCH_BASE 0x75F9000ull +#define NIC11_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 + +#endif /* GAUDI2_BLOCKS_LINUX_DRIVER_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h new file mode 100644 index 000000000000..d0e2c68a639f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h @@ -0,0 +1,550 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2020-2022 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef ASIC_REG_GAUDI2_REGS_H_ +#define ASIC_REG_GAUDI2_REGS_H_ + +#include "gaudi2_blocks_linux_driver.h" +#include "psoc_reset_conf_regs.h" +#include "psoc_global_conf_regs.h" +#include "cpu_if_regs.h" +#include "pcie_aux_regs.h" +#include "pcie_dbi_regs.h" +#include "pcie_wrap_regs.h" +#include "pmmu_hbw_stlb_regs.h" +#include "psoc_timestamp_regs.h" +#include "psoc_etr_regs.h" +#include "xbar_edge_0_regs.h" +#include "xbar_mid_0_regs.h" +#include "arc_farm_kdma_regs.h" +#include "arc_farm_kdma_ctx_regs.h" +#include "arc_farm_kdma_kdma_cgm_regs.h" +#include "arc_farm_arc0_aux_regs.h" +#include "arc_farm_arc0_acp_eng_regs.h" +#include "arc_farm_kdma_ctx_axuser_regs.h" +#include "arc_farm_arc0_dup_eng_axuser_regs.h" +#include "arc_farm_arc0_dup_eng_regs.h" +#include "dcore0_sync_mngr_objs_regs.h" +#include "dcore0_sync_mngr_glbl_regs.h" +#include "dcore0_sync_mngr_mstr_if_axuser_regs.h" +#include "pdma0_qm_arc_aux_regs.h" +#include "pdma0_core_ctx_regs.h" +#include "pdma0_core_regs.h" +#include "pdma0_qm_axuser_secured_regs.h" +#include "pdma0_qm_regs.h" +#include "pdma0_qm_cgm_regs.h" +#include "pdma0_core_ctx_axuser_regs.h" +#include "pdma1_core_ctx_axuser_regs.h" +#include "pdma0_qm_axuser_nonsecured_regs.h" +#include "pdma1_qm_axuser_nonsecured_regs.h" +#include "dcore0_tpc0_qm_regs.h" +#include "dcore0_tpc0_qm_cgm_regs.h" +#include "dcore0_tpc0_qm_axuser_nonsecured_regs.h" +#include "dcore0_tpc0_qm_arc_aux_regs.h" +#include "dcore0_tpc0_cfg_regs.h" +#include "dcore0_tpc0_cfg_qm_regs.h" +#include "dcore0_tpc0_cfg_axuser_regs.h" +#include "dcore0_tpc0_cfg_qm_sync_object_regs.h" +#include "dcore0_tpc0_cfg_kernel_regs.h" +#include "dcore0_tpc0_cfg_kernel_tensor_0_regs.h" +#include "dcore0_tpc0_cfg_qm_tensor_0_regs.h" +#include "dcore0_tpc0_cfg_special_regs.h" +#include "dcore0_tpc0_eml_funnel_regs.h" +#include "dcore0_tpc0_eml_etf_regs.h" +#include "dcore0_tpc0_eml_stm_regs.h" +#include "dcore0_tpc0_eml_busmon_0_regs.h" +#include "dcore0_tpc0_eml_spmu_regs.h" +#include "pmmu_pif_regs.h" +#include "dcore0_edma0_qm_cgm_regs.h" +#include "dcore0_edma0_core_regs.h" +#include "dcore0_edma0_qm_regs.h" +#include "dcore0_edma0_qm_arc_aux_regs.h" +#include "dcore0_edma0_core_ctx_regs.h" +#include "dcore0_edma0_core_ctx_axuser_regs.h" +#include "dcore0_edma0_qm_axuser_nonsecured_regs.h" +#include "dcore0_edma1_core_ctx_axuser_regs.h" +#include "dcore0_edma1_qm_axuser_nonsecured_regs.h" +#include "dcore0_hmmu0_stlb_regs.h" +#include "dcore0_hmmu0_mmu_regs.h" +#include "rot0_qm_regs.h" +#include "rot0_qm_cgm_regs.h" +#include "rot0_qm_arc_aux_regs.h" +#include "rot0_regs.h" +#include "rot0_desc_regs.h" +#include "rot0_qm_axuser_nonsecured_regs.h" +#include "dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h" +#include "dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h" +#include "dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h" +#include "dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h" +#include "dcore0_rtr0_ctrl_regs.h" +#include "dcore0_dec0_cmd_regs.h" +#include "dcore0_vdec0_brdg_ctrl_regs.h" +#include "dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h" +#include "dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h" +#include "dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h" +#include "dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h" +#include "dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h" +#include "dcore0_vdec0_ctrl_special_regs.h" +#include "pcie_vdec0_brdg_ctrl_axuser_dec_regs.h" +#include "pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h" +#include "pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h" +#include "pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h" +#include "pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h" +#include "pcie_dec0_cmd_regs.h" +#include "pcie_vdec0_brdg_ctrl_regs.h" +#include "pcie_vdec0_ctrl_special_regs.h" +#include "dcore0_mme_qm_regs.h" +#include "dcore0_mme_qm_arc_aux_regs.h" +#include "dcore0_mme_qm_axuser_secured_regs.h" +#include "dcore0_mme_qm_cgm_regs.h" +#include "dcore0_mme_qm_arc_acp_eng_regs.h" +#include "dcore0_mme_qm_axuser_nonsecured_regs.h" +#include "dcore0_mme_qm_arc_dup_eng_regs.h" +#include "dcore0_mme_qm_arc_dup_eng_axuser_regs.h" +#include "dcore0_mme_sbte0_mstr_if_axuser_regs.h" +#include "dcore0_mme_wb0_mstr_if_axuser_regs.h" +#include "dcore0_mme_acc_regs.h" +#include "dcore0_mme_ctrl_lo_regs.h" +#include "dcore1_mme_ctrl_lo_regs.h" +#include "dcore3_mme_ctrl_lo_regs.h" +#include "dcore0_mme_ctrl_lo_mme_axuser_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_cout0_master_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_cout0_slave_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_cout1_master_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_cout1_slave_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_in0_master_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_in0_slave_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_in1_master_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_in1_slave_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_in2_master_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_in2_slave_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_in3_master_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_in3_slave_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_in4_master_regs.h" +#include "dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h" +#include "dcore0_mme_ctrl_lo_arch_base_addr_regs.h" +#include "dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h" +#include "dcore0_mme_ctrl_lo_arch_non_tensor_start_regs.h" +#include "dcore0_mme_ctrl_lo_arch_tensor_a_regs.h" +#include "dcore0_mme_ctrl_lo_arch_tensor_b_regs.h" +#include "dcore0_mme_ctrl_lo_arch_tensor_cout_regs.h" + +#include "pdma0_qm_masks.h" +#include "pdma0_core_masks.h" +#include "pdma0_core_special_masks.h" +#include "psoc_global_conf_masks.h" +#include "psoc_reset_conf_masks.h" +#include "arc_farm_kdma_masks.h" +#include "arc_farm_kdma_ctx_masks.h" +#include "arc_farm_arc0_aux_masks.h" +#include "arc_farm_kdma_ctx_axuser_masks.h" +#include "dcore0_sync_mngr_objs_masks.h" +#include "dcore0_sync_mngr_glbl_masks.h" +#include "dcore0_sync_mngr_mstr_if_axuser_masks.h" +#include "dcore0_tpc0_cfg_masks.h" +#include "dcore0_mme_ctrl_lo_masks.h" +#include "dcore0_mme_sbte0_masks.h" +#include "dcore0_edma0_qm_masks.h" +#include "dcore0_edma0_core_masks.h" +#include "dcore0_hmmu0_stlb_masks.h" +#include "dcore0_hmmu0_mmu_masks.h" +#include "dcore0_dec0_cmd_masks.h" +#include "dcore0_vdec0_brdg_ctrl_masks.h" +#include "pcie_dec0_cmd_masks.h" +#include "pcie_vdec0_brdg_ctrl_masks.h" +#include "rot0_masks.h" +#include "pmmu_hbw_stlb_masks.h" +#include "psoc_etr_masks.h" + +#define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR 0x4800040 + +#define SM_OBJS_PROT_BITS_OFFS 0x14000 + +#define DCORE_OFFSET (mmDCORE1_TPC0_QM_BASE - mmDCORE0_TPC0_QM_BASE) +#define DCORE_EDMA_OFFSET (mmDCORE0_EDMA1_QM_BASE - mmDCORE0_EDMA0_QM_BASE) +#define DCORE_TPC_OFFSET (mmDCORE0_TPC1_QM_BASE - mmDCORE0_TPC0_QM_BASE) +#define DCORE_DEC_OFFSET (mmDCORE0_DEC1_VSI_BASE - mmDCORE0_DEC0_VSI_BASE) +#define DCORE_HMMU_OFFSET (mmDCORE0_HMMU1_MMU_BASE - mmDCORE0_HMMU0_MMU_BASE) +#define NIC_QM_OFFSET (mmNIC0_QM1_BASE - mmNIC0_QM0_BASE) +#define PDMA_OFFSET (mmPDMA1_QM_BASE - mmPDMA0_QM_BASE) +#define ROT_OFFSET (mmROT1_BASE - mmROT0_BASE) + +#define TPC_CFG_BASE_ADDRESS_HIGH_OFFSET \ + (mmDCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH - mmDCORE0_TPC0_CFG_BASE) + +#define TPC_CFG_SM_BASE_ADDRESS_HIGH_OFFSET \ + (mmDCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH - mmDCORE0_TPC0_CFG_BASE) + +#define TPC_CFG_STALL_OFFSET (mmDCORE0_TPC0_CFG_TPC_STALL - mmDCORE0_TPC0_CFG_BASE) +#define TPC_CFG_STALL_ON_ERR_OFFSET (mmDCORE0_TPC0_CFG_STALL_ON_ERR - mmDCORE0_TPC0_CFG_BASE) +#define TPC_CFG_TPC_INTR_MASK_OFFSET (mmDCORE0_TPC0_CFG_TPC_INTR_MASK - mmDCORE0_TPC0_CFG_BASE) +#define TPC_CFG_MSS_CONFIG_OFFSET (mmDCORE0_TPC0_CFG_MSS_CONFIG - mmDCORE0_TPC0_CFG_BASE) + +#define MME_ACC_INTR_MASK_OFFSET (mmDCORE0_MME_ACC_INTR_MASK - mmDCORE0_MME_ACC_BASE) +#define MME_ACC_WR_AXI_AGG_COUT0_OFFSET (mmDCORE0_MME_ACC_WR_AXI_AGG_COUT0 - mmDCORE0_MME_ACC_BASE) +#define MME_ACC_WR_AXI_AGG_COUT1_OFFSET (mmDCORE0_MME_ACC_WR_AXI_AGG_COUT1 - mmDCORE0_MME_ACC_BASE) +#define MME_ACC_AP_LFSR_POLY_OFFSET (mmDCORE0_MME_ACC_AP_LFSR_POLY - mmDCORE0_MME_ACC_BASE) +#define MME_ACC_AP_LFSR_SEED_SEL_OFFSET (mmDCORE0_MME_ACC_AP_LFSR_SEED_SEL - mmDCORE0_MME_ACC_BASE) +#define MME_ACC_AP_LFSR_SEED_WDATA_OFFSET \ + (mmDCORE0_MME_ACC_AP_LFSR_SEED_WDATA - mmDCORE0_MME_ACC_BASE) + +#define DMA_CORE_CFG_0_OFFSET (mmARC_FARM_KDMA_CFG_0 - mmARC_FARM_KDMA_BASE) +#define DMA_CORE_CFG_1_OFFSET (mmARC_FARM_KDMA_CFG_1 - mmARC_FARM_KDMA_BASE) +#define DMA_CORE_PROT_OFFSET (mmARC_FARM_KDMA_PROT - mmARC_FARM_KDMA_BASE) +#define DMA_CORE_ERRMSG_ADDR_LO_OFFSET (mmARC_FARM_KDMA_ERRMSG_ADDR_LO - mmARC_FARM_KDMA_BASE) +#define DMA_CORE_ERRMSG_ADDR_HI_OFFSET (mmARC_FARM_KDMA_ERRMSG_ADDR_HI - mmARC_FARM_KDMA_BASE) +#define DMA_CORE_ERRMSG_WDATA_OFFSET (mmARC_FARM_KDMA_ERRMSG_WDATA - mmARC_FARM_KDMA_BASE) + +#define QM_PQ_BASE_LO_0_OFFSET (mmPDMA0_QM_PQ_BASE_LO_0 - mmPDMA0_QM_BASE) +#define QM_PQ_BASE_HI_0_OFFSET (mmPDMA0_QM_PQ_BASE_HI_0 - mmPDMA0_QM_BASE) +#define QM_PQ_SIZE_0_OFFSET (mmPDMA0_QM_PQ_SIZE_0 - mmPDMA0_QM_BASE) +#define QM_PQ_PI_0_OFFSET (mmPDMA0_QM_PQ_PI_0 - mmPDMA0_QM_BASE) +#define QM_PQ_CI_0_OFFSET (mmPDMA0_QM_PQ_CI_0 - mmPDMA0_QM_BASE) +#define QM_CP_FENCE0_CNT_0_OFFSET (mmPDMA0_QM_CP_FENCE0_CNT_0 - mmPDMA0_QM_BASE) + +#define QM_CP_MSG_BASE0_ADDR_LO_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 - mmPDMA0_QM_BASE) +#define QM_CP_MSG_BASE0_ADDR_HI_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 - mmPDMA0_QM_BASE) +#define QM_CP_MSG_BASE1_ADDR_LO_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 - mmPDMA0_QM_BASE) +#define QM_CP_MSG_BASE1_ADDR_HI_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 - mmPDMA0_QM_BASE) + +#define QM_CP_CFG_OFFSET (mmPDMA0_QM_CP_CFG - mmPDMA0_QM_BASE) +#define QM_PQC_HBW_BASE_LO_0_OFFSET (mmPDMA0_QM_PQC_HBW_BASE_LO_0 - mmPDMA0_QM_BASE) +#define QM_PQC_HBW_BASE_HI_0_OFFSET (mmPDMA0_QM_PQC_HBW_BASE_HI_0 - mmPDMA0_QM_BASE) +#define QM_PQC_SIZE_0_OFFSET (mmPDMA0_QM_PQC_SIZE_0 - mmPDMA0_QM_BASE) +#define QM_PQC_PI_0_OFFSET (mmPDMA0_QM_PQC_PI_0 - mmPDMA0_QM_BASE) +#define QM_PQC_LBW_WDATA_0_OFFSET (mmPDMA0_QM_PQC_LBW_WDATA_0 - mmPDMA0_QM_BASE) +#define QM_PQC_LBW_BASE_LO_0_OFFSET (mmPDMA0_QM_PQC_LBW_BASE_LO_0 - mmPDMA0_QM_BASE) +#define QM_PQC_LBW_BASE_HI_0_OFFSET (mmPDMA0_QM_PQC_LBW_BASE_HI_0 - mmPDMA0_QM_BASE) +#define QM_GLBL_ERR_ADDR_LO_OFFSET (mmPDMA0_QM_GLBL_ERR_ADDR_LO - mmPDMA0_QM_BASE) +#define QM_PQC_CFG_OFFSET (mmPDMA0_QM_PQC_CFG - mmPDMA0_QM_BASE) +#define QM_ARB_CFG_0_OFFSET (mmPDMA0_QM_ARB_CFG_0 - mmPDMA0_QM_BASE) +#define QM_GLBL_CFG0_OFFSET (mmPDMA0_QM_GLBL_CFG0 - mmPDMA0_QM_BASE) +#define QM_GLBL_CFG1_OFFSET (mmPDMA0_QM_GLBL_CFG1 - mmPDMA0_QM_BASE) +#define QM_GLBL_CFG2_OFFSET (mmPDMA0_QM_GLBL_CFG2 - mmPDMA0_QM_BASE) +#define QM_GLBL_PROT_OFFSET (mmPDMA0_QM_GLBL_PROT - mmPDMA0_QM_BASE) +#define QM_GLBL_ERR_CFG_OFFSET (mmPDMA0_QM_GLBL_ERR_CFG - mmPDMA0_QM_BASE) +#define QM_GLBL_ERR_CFG1_OFFSET (mmPDMA0_QM_GLBL_ERR_CFG1 - mmPDMA0_QM_BASE) +#define QM_GLBL_ERR_ADDR_HI_OFFSET (mmPDMA0_QM_GLBL_ERR_ADDR_HI - mmPDMA0_QM_BASE) +#define QM_GLBL_ERR_WDATA_OFFSET (mmPDMA0_QM_GLBL_ERR_WDATA - mmPDMA0_QM_BASE) +#define QM_ARB_ERR_MSG_EN_OFFSET (mmPDMA0_QM_ARB_ERR_MSG_EN - mmPDMA0_QM_BASE) +#define QM_ARB_SLV_CHOISE_WDT_OFFSET (mmPDMA0_QM_ARB_SLV_CHOICE_WDT - mmPDMA0_QM_BASE) +#define QM_FENCE2_OFFSET (mmPDMA0_QM_CP_FENCE2_RDATA_0 - mmPDMA0_QM_BASE) +#define QM_SEI_STATUS_OFFSET (mmPDMA0_QM_SEI_STATUS - mmPDMA0_QM_BASE) + +#define SFT_OFFSET (mmSFT1_HBW_RTR_IF0_RTR_H3_BASE - mmSFT0_HBW_RTR_IF0_RTR_H3_BASE) +#define SFT_IF_RTR_OFFSET (mmSFT0_HBW_RTR_IF1_RTR_H3_BASE - mmSFT0_HBW_RTR_IF0_RTR_H3_BASE) + +#define ARC_HALT_REQ_OFFSET (mmARC_FARM_ARC0_AUX_RUN_HALT_REQ - mmARC_FARM_ARC0_AUX_BASE) + +#define ARC_REGION_CFG_OFFSET(region) \ + (mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_0 + (region * 4) - mmARC_FARM_ARC0_AUX_BASE) + +#define ARC_DCCM_UPPER_EN_OFFSET \ + (mmARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN - mmARC_FARM_ARC0_AUX_BASE) + +#define PCIE_VDEC_OFFSET \ + (mmPCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE - mmPCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define DCORE_MME_SBTE_OFFSET \ + (mmDCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define DCORE_MME_WB_OFFSET \ + (mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define DCORE_RTR_OFFSET \ + (mmDCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define DCORE_VDEC_OFFSET \ + (mmDCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define MMU_OFFSET(REG) (REG - mmDCORE0_HMMU0_MMU_BASE) +#define MMU_BYPASS_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_BYPASS) +#define MMU_SPI_SEI_MASK_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_SPI_SEI_MASK) +#define MMU_SPI_SEI_CAUSE_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_SPI_SEI_CAUSE) +#define MMU_ENABLE_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_ENABLE) +#define MMU_DDR_RANGE_REG_ENABLE MMU_OFFSET(mmDCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE) +#define MMU_RR_SEC_MIN_63_32_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_0) +#define MMU_RR_SEC_MIN_31_0_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_0) +#define MMU_RR_SEC_MAX_63_32_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_0) +#define MMU_RR_SEC_MAX_31_0_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_0) +#define MMU_RR_PRIV_MIN_63_32_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_0) +#define MMU_RR_PRIV_MIN_31_0_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_0) +#define MMU_RR_PRIV_MAX_63_32_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_0) +#define MMU_RR_PRIV_MAX_31_0_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_0) +#define MMU_INTERRUPT_CLR_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_INTERRUPT_CLR) + +#define STLB_OFFSET(REG) (REG - mmDCORE0_HMMU0_STLB_BASE) +#define STLB_BUSY_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_BUSY) +#define STLB_ASID_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_ASID) +#define STLB_HOP0_PA43_12_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_HOP0_PA43_12) +#define STLB_HOP0_PA63_44_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_HOP0_PA63_44) +#define STLB_HOP_CONFIGURATION_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_HOP_CONFIGURATION) +#define STLB_INV_ALL_START_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_INV_ALL_START) +#define STLB_SRAM_INIT_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_SRAM_INIT) +#define STLB_SET_THRESHOLD_HOP3_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3) +#define STLB_SET_THRESHOLD_HOP2_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2) +#define STLB_SET_THRESHOLD_HOP1_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1) +#define STLB_SET_THRESHOLD_HOP0_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0) +#define STLB_RANGE_INV_START_LSB_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_START_LSB) +#define STLB_RANGE_INV_START_MSB_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_START_MSB) +#define STLB_RANGE_INV_END_LSB_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_END_LSB) +#define STLB_RANGE_INV_END_MSB_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_END_MSB) + +#define STLB_LL_LOOKUP_MASK_63_32_OFFSET \ + STLB_OFFSET(mmDCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32) + +#define STLB_RANGE_CACHE_INVALIDATION_OFFSET \ + STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION) + +/* RTR CTR RAZWI related offsets */ +#define RTR_MSTR_IF_OFFSET (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_RTR0_CTRL_BASE) + +#define RTR_LBW_MSTR_IF_OFFSET \ + (mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_RTR0_CTRL_BASE) + +/* RAZWI captured hbw aw addr high */ +#define DEC_RAZWI_HBW_AW_ADDR_HI \ + (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_HI_ADDR - mmDCORE0_RTR0_CTRL_BASE) + +/* RAZWI captured hbw aw addr low */ +#define DEC_RAZWI_HBW_AW_ADDR_LO \ + (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_LO_ADDR - mmDCORE0_RTR0_CTRL_BASE) + +/* RAZWI captured hbw aw set */ +#define DEC_RAZWI_HBW_AW_SET \ + (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_SET - mmDCORE0_RTR0_CTRL_BASE) + +/* RAZWI captured hbw ar addr high */ +#define DEC_RAZWI_HBW_AR_ADDR_HI \ + (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_HI_ADDR - mmDCORE0_RTR0_CTRL_BASE) + +/* RAZWI captured hbw ar addr low */ +#define DEC_RAZWI_HBW_AR_ADDR_LO \ + (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_LO_ADDR - mmDCORE0_RTR0_CTRL_BASE) + +/* RAZWI captured hbw ar set */ +#define DEC_RAZWI_HBW_AR_SET \ + (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_SET - mmDCORE0_RTR0_CTRL_BASE) + +/* RAZWI captured lbw aw addr */ +#define DEC_RAZWI_LBW_AW_ADDR \ + (mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AW_ADDR - mmDCORE0_RTR0_CTRL_BASE) + +/* RAZWI captured lbw aw set */ +#define DEC_RAZWI_LBW_AW_SET \ + (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_SET - mmDCORE0_RTR0_CTRL_BASE) + +/* RAZWI captured lbw ar addr */ +#define DEC_RAZWI_LBW_AR_ADDR \ + (mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AR_ADDR - mmDCORE0_RTR0_CTRL_BASE) + +/* RAZWI captured lbw ar set */ +#define DEC_RAZWI_LBW_AR_SET \ + (mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AR_SET - mmDCORE0_RTR0_CTRL_BASE) + +/* RAZWI captured shared hbw aw addr high */ +#define RR_SHRD_HBW_AW_RAZWI_HI \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_HI - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI captured shared hbw aw addr low */ +#define RR_SHRD_HBW_AW_RAZWI_LO \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_LO - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI captured shared hbw ar addr high */ +#define RR_SHRD_HBW_AR_RAZWI_HI \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_HI - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI captured shared hbw ar addr low */ +#define RR_SHRD_HBW_AR_RAZWI_LO \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_LO - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI captured shared aw XY coordinates */ +#define RR_SHRD_HBW_AW_RAZWI_XY \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_XY - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI captured shared ar XY coordinates */ +#define RR_SHRD_HBW_AR_RAZWI_XY \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_XY - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI hbw shared occurred due to write access */ +#define RR_SHRD_HBW_AW_RAZWI_HAPPENED \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_HAPPENED - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI hbw shared occurred due to read access */ +#define RR_SHRD_HBW_AR_RAZWI_HAPPENED \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_HAPPENED - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI captured shared lbw aw addr */ +#define RR_SHRD_LBW_AW_RAZWI \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI captured shared lbw ar addr */ +#define RR_SHRD_LBW_AR_RAZWI \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI captured shared lbw aw XY coordinates */ +#define RR_SHRD_LBW_AW_RAZWI_XY \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI_XY - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI captured shared lbw ar XY coordinates */ +#define RR_SHRD_LBW_AR_RAZWI_XY \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI_XY - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI lbw shared occurred due to write access */ +#define RR_SHRD_LBW_AW_RAZWI_HAPPENED \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI_HAPPENED - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +/* RAZWI lbw shared occurred due to read access */ +#define RR_SHRD_LBW_AR_RAZWI_HAPPENED \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI_HAPPENED - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define BRDG_CTRL_BLOCK_OFFSET (mmDCORE0_VDEC0_BRDG_CTRL_BASE - mmDCORE0_DEC0_CMD_BASE) +#define SPECIAL_BLOCK_OFFSET (mmDCORE0_VDEC0_BRDG_CTRL_SPECIAL_BASE - mmDCORE0_DEC0_CMD_BASE) +#define SFT_DCORE_OFFSET (mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE) +#define SFT_IF_OFFSET (mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE) + +#define BRDG_CTRL_NRM_MSIX_LBW_AWADDR \ + (mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR - mmDCORE0_VDEC0_BRDG_CTRL_BASE) + +#define BRDG_CTRL_NRM_MSIX_LBW_WDATA \ + (mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA - mmDCORE0_VDEC0_BRDG_CTRL_BASE) + +#define BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR \ + (mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR - mmDCORE0_VDEC0_BRDG_CTRL_BASE) + +#define BRDG_CTRL_ABNRM_MSIX_LBW_WDATA \ + (mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA - mmDCORE0_VDEC0_BRDG_CTRL_BASE) + +#define RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_SEC_RANGE_MIN_HI_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_HI_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_SEC_RANGE_MIN_LO_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_LO_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_SEC_RANGE_MAX_HI_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_HI_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_SEC_RANGE_MAX_LO_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_LO_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define RR_LBW_SEC_RANGE_MIN_SHORT_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE) + +#define RR_LBW_SEC_RANGE_MAX_SHORT_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE) + +#define RR_LBW_PRIV_RANGE_MIN_SHORT_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE) + +#define RR_LBW_PRIV_RANGE_MAX_SHORT_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE) + +#define RR_LBW_SEC_RANGE_MIN_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE) + +#define RR_LBW_SEC_RANGE_MAX_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE) + +#define RR_LBW_PRIV_RANGE_MIN_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE) + +#define RR_LBW_PRIV_RANGE_MAX_0_OFFSET \ + (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_0 - \ + mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE) + +#define ARC_AUX_DCCM_QUEUE_PUSH_REG_0_OFFSET \ + (mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_0 - mmARC_FARM_ARC0_AUX_BASE) + +#define MMU_STATIC_MULTI_PAGE_SIZE_OFFSET \ + (mmDCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE - mmDCORE0_HMMU0_MMU_BASE) + +#define HBM_MC_SPI_TEMP_PIN_CHG_MASK BIT(0) +#define HBM_MC_SPI_THR_ENG_MASK BIT(1) +#define HBM_MC_SPI_THR_DIS_ENG_MASK BIT(2) +#define HBM_MC_SPI_IEEE1500_COMP_MASK BIT(3) +#define HBM_MC_SPI_IEEE1500_PAUSED_MASK BIT(4) + +#include "nic0_qpc0_regs.h" +#include "nic0_qm0_regs.h" +#include "nic0_qm_arc_aux0_regs.h" +#include "nic0_qm0_cgm_regs.h" +#include "nic0_umr0_0_completion_queue_ci_1_regs.h" +#include "nic0_umr0_0_unsecure_doorbell0_regs.h" + +#define NIC_OFFSET (mmNIC1_MSTR_IF_RR_SHRD_HBW_BASE - mmNIC0_MSTR_IF_RR_SHRD_HBW_BASE) + +#define NIC_UMR_OFFSET \ + (mmNIC0_UMR0_1_UNSECURE_DOORBELL0_BASE - mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE) + +#endif /* ASIC_REG_GAUDI2_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qm0_cgm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qm0_cgm_regs.h new file mode 100644 index 000000000000..d49906a68511 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qm0_cgm_regs.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC0_QM0_CGM_REGS_H_ +#define ASIC_REG_NIC0_QM0_CGM_REGS_H_ + +/* + ***************************************** + * NIC0_QM0_CGM + * (Prototype: QMAN_CGM) + ***************************************** + */ + +#define mmNIC0_QM0_CGM_CFG 0x541AD80 + +#define mmNIC0_QM0_CGM_STS 0x541AD84 + +#define mmNIC0_QM0_CGM_CFG1 0x541AD88 + +#endif /* ASIC_REG_NIC0_QM0_CGM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qm0_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qm0_regs.h new file mode 100644 index 000000000000..acb19c1cd4bd --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qm0_regs.h @@ -0,0 +1,1057 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC0_QM0_REGS_H_ +#define ASIC_REG_NIC0_QM0_REGS_H_ + +/* + ***************************************** + * NIC0_QM0 + * (Prototype: QMAN) + ***************************************** + */ + +#define mmNIC0_QM0_GLBL_CFG0 0x541A000 + +#define mmNIC0_QM0_GLBL_CFG1 0x541A004 + +#define mmNIC0_QM0_GLBL_CFG2 0x541A008 + +#define mmNIC0_QM0_GLBL_ERR_CFG 0x541A00C + +#define mmNIC0_QM0_GLBL_ERR_CFG1 0x541A010 + +#define mmNIC0_QM0_GLBL_ERR_ARC_HALT_EN 0x541A014 + +#define mmNIC0_QM0_GLBL_AXCACHE 0x541A018 + +#define mmNIC0_QM0_GLBL_STS0 0x541A01C + +#define mmNIC0_QM0_GLBL_STS1 0x541A020 + +#define mmNIC0_QM0_GLBL_ERR_STS_0 0x541A024 + +#define mmNIC0_QM0_GLBL_ERR_STS_1 0x541A028 + +#define mmNIC0_QM0_GLBL_ERR_STS_2 0x541A02C + +#define mmNIC0_QM0_GLBL_ERR_STS_3 0x541A030 + +#define mmNIC0_QM0_GLBL_ERR_STS_4 0x541A034 + +#define mmNIC0_QM0_GLBL_ERR_MSG_EN_0 0x541A038 + +#define mmNIC0_QM0_GLBL_ERR_MSG_EN_1 0x541A03C + +#define mmNIC0_QM0_GLBL_ERR_MSG_EN_2 0x541A040 + +#define mmNIC0_QM0_GLBL_ERR_MSG_EN_3 0x541A044 + +#define mmNIC0_QM0_GLBL_ERR_MSG_EN_4 0x541A048 + +#define mmNIC0_QM0_GLBL_PROT 0x541A04C + +#define mmNIC0_QM0_PQ_BASE_LO_0 0x541A050 + +#define mmNIC0_QM0_PQ_BASE_LO_1 0x541A054 + +#define mmNIC0_QM0_PQ_BASE_LO_2 0x541A058 + +#define mmNIC0_QM0_PQ_BASE_LO_3 0x541A05C + +#define mmNIC0_QM0_PQ_BASE_HI_0 0x541A060 + +#define mmNIC0_QM0_PQ_BASE_HI_1 0x541A064 + +#define mmNIC0_QM0_PQ_BASE_HI_2 0x541A068 + +#define mmNIC0_QM0_PQ_BASE_HI_3 0x541A06C + +#define mmNIC0_QM0_PQ_SIZE_0 0x541A070 + +#define mmNIC0_QM0_PQ_SIZE_1 0x541A074 + +#define mmNIC0_QM0_PQ_SIZE_2 0x541A078 + +#define mmNIC0_QM0_PQ_SIZE_3 0x541A07C + +#define mmNIC0_QM0_PQ_PI_0 0x541A080 + +#define mmNIC0_QM0_PQ_PI_1 0x541A084 + +#define mmNIC0_QM0_PQ_PI_2 0x541A088 + +#define mmNIC0_QM0_PQ_PI_3 0x541A08C + +#define mmNIC0_QM0_PQ_CI_0 0x541A090 + +#define mmNIC0_QM0_PQ_CI_1 0x541A094 + +#define mmNIC0_QM0_PQ_CI_2 0x541A098 + +#define mmNIC0_QM0_PQ_CI_3 0x541A09C + +#define mmNIC0_QM0_PQ_CFG0_0 0x541A0A0 + +#define mmNIC0_QM0_PQ_CFG0_1 0x541A0A4 + +#define mmNIC0_QM0_PQ_CFG0_2 0x541A0A8 + +#define mmNIC0_QM0_PQ_CFG0_3 0x541A0AC + +#define mmNIC0_QM0_PQ_CFG1_0 0x541A0B0 + +#define mmNIC0_QM0_PQ_CFG1_1 0x541A0B4 + +#define mmNIC0_QM0_PQ_CFG1_2 0x541A0B8 + +#define mmNIC0_QM0_PQ_CFG1_3 0x541A0BC + +#define mmNIC0_QM0_PQ_STS0_0 0x541A0C0 + +#define mmNIC0_QM0_PQ_STS0_1 0x541A0C4 + +#define mmNIC0_QM0_PQ_STS0_2 0x541A0C8 + +#define mmNIC0_QM0_PQ_STS0_3 0x541A0CC + +#define mmNIC0_QM0_PQ_STS1_0 0x541A0D0 + +#define mmNIC0_QM0_PQ_STS1_1 0x541A0D4 + +#define mmNIC0_QM0_PQ_STS1_2 0x541A0D8 + +#define mmNIC0_QM0_PQ_STS1_3 0x541A0DC + +#define mmNIC0_QM0_CQ_CFG0_0 0x541A0E0 + +#define mmNIC0_QM0_CQ_CFG0_1 0x541A0E4 + +#define mmNIC0_QM0_CQ_CFG0_2 0x541A0E8 + +#define mmNIC0_QM0_CQ_CFG0_3 0x541A0EC + +#define mmNIC0_QM0_CQ_CFG0_4 0x541A0F0 + +#define mmNIC0_QM0_CQ_STS0_0 0x541A0F4 + +#define mmNIC0_QM0_CQ_STS0_1 0x541A0F8 + +#define mmNIC0_QM0_CQ_STS0_2 0x541A0FC + +#define mmNIC0_QM0_CQ_STS0_3 0x541A100 + +#define mmNIC0_QM0_CQ_STS0_4 0x541A104 + +#define mmNIC0_QM0_CQ_CFG1_0 0x541A108 + +#define mmNIC0_QM0_CQ_CFG1_1 0x541A10C + +#define mmNIC0_QM0_CQ_CFG1_2 0x541A110 + +#define mmNIC0_QM0_CQ_CFG1_3 0x541A114 + +#define mmNIC0_QM0_CQ_CFG1_4 0x541A118 + +#define mmNIC0_QM0_CQ_STS1_0 0x541A11C + +#define mmNIC0_QM0_CQ_STS1_1 0x541A120 + +#define mmNIC0_QM0_CQ_STS1_2 0x541A124 + +#define mmNIC0_QM0_CQ_STS1_3 0x541A128 + +#define mmNIC0_QM0_CQ_STS1_4 0x541A12C + +#define mmNIC0_QM0_CQ_PTR_LO_0 0x541A150 + +#define mmNIC0_QM0_CQ_PTR_HI_0 0x541A154 + +#define mmNIC0_QM0_CQ_TSIZE_0 0x541A158 + +#define mmNIC0_QM0_CQ_CTL_0 0x541A15C + +#define mmNIC0_QM0_CQ_PTR_LO_1 0x541A160 + +#define mmNIC0_QM0_CQ_PTR_HI_1 0x541A164 + +#define mmNIC0_QM0_CQ_TSIZE_1 0x541A168 + +#define mmNIC0_QM0_CQ_CTL_1 0x541A16C + +#define mmNIC0_QM0_CQ_PTR_LO_2 0x541A170 + +#define mmNIC0_QM0_CQ_PTR_HI_2 0x541A174 + +#define mmNIC0_QM0_CQ_TSIZE_2 0x541A178 + +#define mmNIC0_QM0_CQ_CTL_2 0x541A17C + +#define mmNIC0_QM0_CQ_PTR_LO_3 0x541A180 + +#define mmNIC0_QM0_CQ_PTR_HI_3 0x541A184 + +#define mmNIC0_QM0_CQ_TSIZE_3 0x541A188 + +#define mmNIC0_QM0_CQ_CTL_3 0x541A18C + +#define mmNIC0_QM0_CQ_PTR_LO_4 0x541A190 + +#define mmNIC0_QM0_CQ_PTR_HI_4 0x541A194 + +#define mmNIC0_QM0_CQ_TSIZE_4 0x541A198 + +#define mmNIC0_QM0_CQ_CTL_4 0x541A19C + +#define mmNIC0_QM0_CQ_TSIZE_STS_0 0x541A1A0 + +#define mmNIC0_QM0_CQ_TSIZE_STS_1 0x541A1A4 + +#define mmNIC0_QM0_CQ_TSIZE_STS_2 0x541A1A8 + +#define mmNIC0_QM0_CQ_TSIZE_STS_3 0x541A1AC + +#define mmNIC0_QM0_CQ_TSIZE_STS_4 0x541A1B0 + +#define mmNIC0_QM0_CQ_PTR_LO_STS_0 0x541A1B4 + +#define mmNIC0_QM0_CQ_PTR_LO_STS_1 0x541A1B8 + +#define mmNIC0_QM0_CQ_PTR_LO_STS_2 0x541A1BC + +#define mmNIC0_QM0_CQ_PTR_LO_STS_3 0x541A1C0 + +#define mmNIC0_QM0_CQ_PTR_LO_STS_4 0x541A1C4 + +#define mmNIC0_QM0_CQ_PTR_HI_STS_0 0x541A1C8 + +#define mmNIC0_QM0_CQ_PTR_HI_STS_1 0x541A1CC + +#define mmNIC0_QM0_CQ_PTR_HI_STS_2 0x541A1D0 + +#define mmNIC0_QM0_CQ_PTR_HI_STS_3 0x541A1D4 + +#define mmNIC0_QM0_CQ_PTR_HI_STS_4 0x541A1D8 + +#define mmNIC0_QM0_CQ_IFIFO_STS_0 0x541A1DC + +#define mmNIC0_QM0_CQ_IFIFO_STS_1 0x541A1E0 + +#define mmNIC0_QM0_CQ_IFIFO_STS_2 0x541A1E4 + +#define mmNIC0_QM0_CQ_IFIFO_STS_3 0x541A1E8 + +#define mmNIC0_QM0_CQ_IFIFO_STS_4 0x541A1EC + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0 0x541A1F0 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_1 0x541A1F4 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_2 0x541A1F8 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_3 0x541A1FC + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_4 0x541A200 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0 0x541A204 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_1 0x541A208 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_2 0x541A20C + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_3 0x541A210 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_4 0x541A214 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0 0x541A218 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_1 0x541A21C + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_2 0x541A220 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_3 0x541A224 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_4 0x541A228 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0 0x541A22C + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_1 0x541A230 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_2 0x541A234 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_3 0x541A238 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_4 0x541A23C + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0 0x541A240 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_1 0x541A244 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2 0x541A248 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_3 0x541A24C + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_4 0x541A250 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0 0x541A254 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_1 0x541A258 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_2 0x541A25C + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_3 0x541A260 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_4 0x541A264 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0 0x541A268 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_1 0x541A26C + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_2 0x541A270 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_3 0x541A274 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_4 0x541A278 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0 0x541A27C + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_1 0x541A280 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_2 0x541A284 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_3 0x541A288 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_4 0x541A28C + +#define mmNIC0_QM0_CP_FENCE0_RDATA_0 0x541A290 + +#define mmNIC0_QM0_CP_FENCE0_RDATA_1 0x541A294 + +#define mmNIC0_QM0_CP_FENCE0_RDATA_2 0x541A298 + +#define mmNIC0_QM0_CP_FENCE0_RDATA_3 0x541A29C + +#define mmNIC0_QM0_CP_FENCE0_RDATA_4 0x541A2A0 + +#define mmNIC0_QM0_CP_FENCE1_RDATA_0 0x541A2A4 + +#define mmNIC0_QM0_CP_FENCE1_RDATA_1 0x541A2A8 + +#define mmNIC0_QM0_CP_FENCE1_RDATA_2 0x541A2AC + +#define mmNIC0_QM0_CP_FENCE1_RDATA_3 0x541A2B0 + +#define mmNIC0_QM0_CP_FENCE1_RDATA_4 0x541A2B4 + +#define mmNIC0_QM0_CP_FENCE2_RDATA_0 0x541A2B8 + +#define mmNIC0_QM0_CP_FENCE2_RDATA_1 0x541A2BC + +#define mmNIC0_QM0_CP_FENCE2_RDATA_2 0x541A2C0 + +#define mmNIC0_QM0_CP_FENCE2_RDATA_3 0x541A2C4 + +#define mmNIC0_QM0_CP_FENCE2_RDATA_4 0x541A2C8 + +#define mmNIC0_QM0_CP_FENCE3_RDATA_0 0x541A2CC + +#define mmNIC0_QM0_CP_FENCE3_RDATA_1 0x541A2D0 + +#define mmNIC0_QM0_CP_FENCE3_RDATA_2 0x541A2D4 + +#define mmNIC0_QM0_CP_FENCE3_RDATA_3 0x541A2D8 + +#define mmNIC0_QM0_CP_FENCE3_RDATA_4 0x541A2DC + +#define mmNIC0_QM0_CP_FENCE0_CNT_0 0x541A2E0 + +#define mmNIC0_QM0_CP_FENCE0_CNT_1 0x541A2E4 + +#define mmNIC0_QM0_CP_FENCE0_CNT_2 0x541A2E8 + +#define mmNIC0_QM0_CP_FENCE0_CNT_3 0x541A2EC + +#define mmNIC0_QM0_CP_FENCE0_CNT_4 0x541A2F0 + +#define mmNIC0_QM0_CP_FENCE1_CNT_0 0x541A2F4 + +#define mmNIC0_QM0_CP_FENCE1_CNT_1 0x541A2F8 + +#define mmNIC0_QM0_CP_FENCE1_CNT_2 0x541A2FC + +#define mmNIC0_QM0_CP_FENCE1_CNT_3 0x541A300 + +#define mmNIC0_QM0_CP_FENCE1_CNT_4 0x541A304 + +#define mmNIC0_QM0_CP_FENCE2_CNT_0 0x541A308 + +#define mmNIC0_QM0_CP_FENCE2_CNT_1 0x541A30C + +#define mmNIC0_QM0_CP_FENCE2_CNT_2 0x541A310 + +#define mmNIC0_QM0_CP_FENCE2_CNT_3 0x541A314 + +#define mmNIC0_QM0_CP_FENCE2_CNT_4 0x541A318 + +#define mmNIC0_QM0_CP_FENCE3_CNT_0 0x541A31C + +#define mmNIC0_QM0_CP_FENCE3_CNT_1 0x541A320 + +#define mmNIC0_QM0_CP_FENCE3_CNT_2 0x541A324 + +#define mmNIC0_QM0_CP_FENCE3_CNT_3 0x541A328 + +#define mmNIC0_QM0_CP_FENCE3_CNT_4 0x541A32C + +#define mmNIC0_QM0_CP_BARRIER_CFG 0x541A330 + +#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET 0x541A334 + +#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET 0x541A338 + +#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET 0x541A33C + +#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_0 0x541A340 + +#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_1 0x541A344 + +#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_2 0x541A348 + +#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_3 0x541A34C + +#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_4 0x541A350 + +#define mmNIC0_QM0_CP_STS_0 0x541A368 + +#define mmNIC0_QM0_CP_STS_1 0x541A36C + +#define mmNIC0_QM0_CP_STS_2 0x541A370 + +#define mmNIC0_QM0_CP_STS_3 0x541A374 + +#define mmNIC0_QM0_CP_STS_4 0x541A378 + +#define mmNIC0_QM0_CP_CURRENT_INST_LO_0 0x541A37C + +#define mmNIC0_QM0_CP_CURRENT_INST_LO_1 0x541A380 + +#define mmNIC0_QM0_CP_CURRENT_INST_LO_2 0x541A384 + +#define mmNIC0_QM0_CP_CURRENT_INST_LO_3 0x541A388 + +#define mmNIC0_QM0_CP_CURRENT_INST_LO_4 0x541A38C + +#define mmNIC0_QM0_CP_CURRENT_INST_HI_0 0x541A390 + +#define mmNIC0_QM0_CP_CURRENT_INST_HI_1 0x541A394 + +#define mmNIC0_QM0_CP_CURRENT_INST_HI_2 0x541A398 + +#define mmNIC0_QM0_CP_CURRENT_INST_HI_3 0x541A39C + +#define mmNIC0_QM0_CP_CURRENT_INST_HI_4 0x541A3A0 + +#define mmNIC0_QM0_CP_PRED_0 0x541A3A4 + +#define mmNIC0_QM0_CP_PRED_1 0x541A3A8 + +#define mmNIC0_QM0_CP_PRED_2 0x541A3AC + +#define mmNIC0_QM0_CP_PRED_3 0x541A3B0 + +#define mmNIC0_QM0_CP_PRED_4 0x541A3B4 + +#define mmNIC0_QM0_CP_PRED_UPEN_0 0x541A3B8 + +#define mmNIC0_QM0_CP_PRED_UPEN_1 0x541A3BC + +#define mmNIC0_QM0_CP_PRED_UPEN_2 0x541A3C0 + +#define mmNIC0_QM0_CP_PRED_UPEN_3 0x541A3C4 + +#define mmNIC0_QM0_CP_PRED_UPEN_4 0x541A3C8 + +#define mmNIC0_QM0_CP_DBG_0_0 0x541A3CC + +#define mmNIC0_QM0_CP_DBG_0_1 0x541A3D0 + +#define mmNIC0_QM0_CP_DBG_0_2 0x541A3D4 + +#define mmNIC0_QM0_CP_DBG_0_3 0x541A3D8 + +#define mmNIC0_QM0_CP_DBG_0_4 0x541A3DC + +#define mmNIC0_QM0_CP_CPDMA_UP_CRED_0 0x541A3E0 + +#define mmNIC0_QM0_CP_CPDMA_UP_CRED_1 0x541A3E4 + +#define mmNIC0_QM0_CP_CPDMA_UP_CRED_2 0x541A3E8 + +#define mmNIC0_QM0_CP_CPDMA_UP_CRED_3 0x541A3EC + +#define mmNIC0_QM0_CP_CPDMA_UP_CRED_4 0x541A3F0 + +#define mmNIC0_QM0_CP_IN_DATA_LO_0 0x541A3F4 + +#define mmNIC0_QM0_CP_IN_DATA_LO_1 0x541A3F8 + +#define mmNIC0_QM0_CP_IN_DATA_LO_2 0x541A3FC + +#define mmNIC0_QM0_CP_IN_DATA_LO_3 0x541A400 + +#define mmNIC0_QM0_CP_IN_DATA_LO_4 0x541A404 + +#define mmNIC0_QM0_CP_IN_DATA_HI_0 0x541A408 + +#define mmNIC0_QM0_CP_IN_DATA_HI_1 0x541A40C + +#define mmNIC0_QM0_CP_IN_DATA_HI_2 0x541A410 + +#define mmNIC0_QM0_CP_IN_DATA_HI_3 0x541A414 + +#define mmNIC0_QM0_CP_IN_DATA_HI_4 0x541A418 + +#define mmNIC0_QM0_PQC_HBW_BASE_LO_0 0x541A41C + +#define mmNIC0_QM0_PQC_HBW_BASE_LO_1 0x541A420 + +#define mmNIC0_QM0_PQC_HBW_BASE_LO_2 0x541A424 + +#define mmNIC0_QM0_PQC_HBW_BASE_LO_3 0x541A428 + +#define mmNIC0_QM0_PQC_HBW_BASE_HI_0 0x541A42C + +#define mmNIC0_QM0_PQC_HBW_BASE_HI_1 0x541A430 + +#define mmNIC0_QM0_PQC_HBW_BASE_HI_2 0x541A434 + +#define mmNIC0_QM0_PQC_HBW_BASE_HI_3 0x541A438 + +#define mmNIC0_QM0_PQC_SIZE_0 0x541A43C + +#define mmNIC0_QM0_PQC_SIZE_1 0x541A440 + +#define mmNIC0_QM0_PQC_SIZE_2 0x541A444 + +#define mmNIC0_QM0_PQC_SIZE_3 0x541A448 + +#define mmNIC0_QM0_PQC_PI_0 0x541A44C + +#define mmNIC0_QM0_PQC_PI_1 0x541A450 + +#define mmNIC0_QM0_PQC_PI_2 0x541A454 + +#define mmNIC0_QM0_PQC_PI_3 0x541A458 + +#define mmNIC0_QM0_PQC_LBW_WDATA_0 0x541A45C + +#define mmNIC0_QM0_PQC_LBW_WDATA_1 0x541A460 + +#define mmNIC0_QM0_PQC_LBW_WDATA_2 0x541A464 + +#define mmNIC0_QM0_PQC_LBW_WDATA_3 0x541A468 + +#define mmNIC0_QM0_PQC_LBW_BASE_LO_0 0x541A46C + +#define mmNIC0_QM0_PQC_LBW_BASE_LO_1 0x541A470 + +#define mmNIC0_QM0_PQC_LBW_BASE_LO_2 0x541A474 + +#define mmNIC0_QM0_PQC_LBW_BASE_LO_3 0x541A478 + +#define mmNIC0_QM0_PQC_LBW_BASE_HI_0 0x541A47C + +#define mmNIC0_QM0_PQC_LBW_BASE_HI_1 0x541A480 + +#define mmNIC0_QM0_PQC_LBW_BASE_HI_2 0x541A484 + +#define mmNIC0_QM0_PQC_LBW_BASE_HI_3 0x541A488 + +#define mmNIC0_QM0_PQC_CFG 0x541A48C + +#define mmNIC0_QM0_PQC_SECURE_PUSH_IND 0x541A490 + +#define mmNIC0_QM0_ARB_MASK 0x541A4A0 + +#define mmNIC0_QM0_ARB_CFG_0 0x541A4A4 + +#define mmNIC0_QM0_ARB_CHOICE_Q_PUSH 0x541A4A8 + +#define mmNIC0_QM0_ARB_WRR_WEIGHT_0 0x541A4AC + +#define mmNIC0_QM0_ARB_WRR_WEIGHT_1 0x541A4B0 + +#define mmNIC0_QM0_ARB_WRR_WEIGHT_2 0x541A4B4 + +#define mmNIC0_QM0_ARB_WRR_WEIGHT_3 0x541A4B8 + +#define mmNIC0_QM0_ARB_CFG_1 0x541A4BC + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_0 0x541A4C0 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_1 0x541A4C4 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_2 0x541A4C8 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_3 0x541A4CC + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_4 0x541A4D0 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_5 0x541A4D4 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_6 0x541A4D8 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_7 0x541A4DC + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_8 0x541A4E0 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_9 0x541A4E4 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_10 0x541A4E8 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_11 0x541A4EC + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_12 0x541A4F0 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_13 0x541A4F4 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_14 0x541A4F8 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_15 0x541A4FC + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_16 0x541A500 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_17 0x541A504 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_18 0x541A508 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_19 0x541A50C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_20 0x541A510 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_21 0x541A514 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_22 0x541A518 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_23 0x541A51C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_24 0x541A520 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_25 0x541A524 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_26 0x541A528 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_27 0x541A52C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_28 0x541A530 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_29 0x541A534 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_30 0x541A538 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_31 0x541A53C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_32 0x541A540 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_33 0x541A544 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_34 0x541A548 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_35 0x541A54C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_36 0x541A550 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_37 0x541A554 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_38 0x541A558 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_39 0x541A55C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_40 0x541A560 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_41 0x541A564 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_42 0x541A568 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_43 0x541A56C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_44 0x541A570 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_45 0x541A574 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_46 0x541A578 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_47 0x541A57C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_48 0x541A580 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_49 0x541A584 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_50 0x541A588 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_51 0x541A58C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_52 0x541A590 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_53 0x541A594 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_54 0x541A598 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_55 0x541A59C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_56 0x541A5A0 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_57 0x541A5A4 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_58 0x541A5A8 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_59 0x541A5AC + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_60 0x541A5B0 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_61 0x541A5B4 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_62 0x541A5B8 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_63 0x541A5BC + +#define mmNIC0_QM0_ARB_MST_CRED_INC 0x541A5E0 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_0 0x541A5E4 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_1 0x541A5E8 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_2 0x541A5EC + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_3 0x541A5F0 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_4 0x541A5F4 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_5 0x541A5F8 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_6 0x541A5FC + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_7 0x541A600 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_8 0x541A604 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_9 0x541A608 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_10 0x541A60C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_11 0x541A610 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_12 0x541A614 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_13 0x541A618 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_14 0x541A61C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_15 0x541A620 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_16 0x541A624 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_17 0x541A628 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_18 0x541A62C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_19 0x541A630 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_20 0x541A634 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_21 0x541A638 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_22 0x541A63C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_23 0x541A640 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_24 0x541A644 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_25 0x541A648 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_26 0x541A64C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_27 0x541A650 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_28 0x541A654 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_29 0x541A658 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_30 0x541A65C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_31 0x541A660 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_32 0x541A664 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_33 0x541A668 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_34 0x541A66C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_35 0x541A670 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_36 0x541A674 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_37 0x541A678 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_38 0x541A67C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_39 0x541A680 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_40 0x541A684 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_41 0x541A688 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_42 0x541A68C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_43 0x541A690 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_44 0x541A694 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_45 0x541A698 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_46 0x541A69C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_47 0x541A6A0 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_48 0x541A6A4 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_49 0x541A6A8 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_50 0x541A6AC + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_51 0x541A6B0 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_52 0x541A6B4 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_53 0x541A6B8 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_54 0x541A6BC + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_55 0x541A6C0 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_56 0x541A6C4 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_57 0x541A6C8 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_58 0x541A6CC + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_59 0x541A6D0 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_60 0x541A6D4 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_61 0x541A6D8 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_62 0x541A6DC + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_63 0x541A6E0 + +#define mmNIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST 0x541A704 + +#define mmNIC0_QM0_ARB_MST_SLAVE_EN 0x541A708 + +#define mmNIC0_QM0_ARB_MST_SLAVE_EN_1 0x541A70C + +#define mmNIC0_QM0_ARB_SLV_CHOICE_WDT 0x541A710 + +#define mmNIC0_QM0_ARB_SLV_ID 0x541A714 + +#define mmNIC0_QM0_ARB_MST_QUIET_PER 0x541A718 + +#define mmNIC0_QM0_ARB_MSG_MAX_INFLIGHT 0x541A744 + +#define mmNIC0_QM0_ARB_BASE_LO 0x541A754 + +#define mmNIC0_QM0_ARB_BASE_HI 0x541A758 + +#define mmNIC0_QM0_ARB_STATE_STS 0x541A780 + +#define mmNIC0_QM0_ARB_CHOICE_FULLNESS_STS 0x541A784 + +#define mmNIC0_QM0_ARB_MSG_STS 0x541A788 + +#define mmNIC0_QM0_ARB_SLV_CHOICE_Q_HEAD 0x541A78C + +#define mmNIC0_QM0_ARB_ERR_CAUSE 0x541A79C + +#define mmNIC0_QM0_ARB_ERR_MSG_EN 0x541A7A0 + +#define mmNIC0_QM0_ARB_ERR_STS_DRP 0x541A7A8 + +#define mmNIC0_QM0_ARB_MST_CRED_STS 0x541A7B0 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_1 0x541A7B4 + +#define mmNIC0_QM0_CSMR_STRICT_PRIO_CFG 0x541A7FC + +#define mmNIC0_QM0_ARC_CQ_CFG0 0x541A800 + +#define mmNIC0_QM0_ARC_CQ_CFG1 0x541A804 + +#define mmNIC0_QM0_ARC_CQ_PTR_LO 0x541A808 + +#define mmNIC0_QM0_ARC_CQ_PTR_HI 0x541A80C + +#define mmNIC0_QM0_ARC_CQ_TSIZE 0x541A810 + +#define mmNIC0_QM0_ARC_CQ_CTL 0x541A814 + +#define mmNIC0_QM0_ARC_CQ_IFIFO_STS 0x541A81C + +#define mmNIC0_QM0_ARC_CQ_STS0 0x541A820 + +#define mmNIC0_QM0_ARC_CQ_STS1 0x541A824 + +#define mmNIC0_QM0_ARC_CQ_TSIZE_STS 0x541A828 + +#define mmNIC0_QM0_ARC_CQ_PTR_LO_STS 0x541A82C + +#define mmNIC0_QM0_ARC_CQ_PTR_HI_STS 0x541A830 + +#define mmNIC0_QM0_CP_WR_ARC_ADDR_HI 0x541A834 + +#define mmNIC0_QM0_CP_WR_ARC_ADDR_LO 0x541A838 + +#define mmNIC0_QM0_ARC_CQ_IFIFO_MSG_BASE_HI 0x541A83C + +#define mmNIC0_QM0_ARC_CQ_IFIFO_MSG_BASE_LO 0x541A840 + +#define mmNIC0_QM0_ARC_CQ_CTL_MSG_BASE_HI 0x541A844 + +#define mmNIC0_QM0_ARC_CQ_CTL_MSG_BASE_LO 0x541A848 + +#define mmNIC0_QM0_CQ_IFIFO_MSG_BASE_HI 0x541A84C + +#define mmNIC0_QM0_CQ_IFIFO_MSG_BASE_LO 0x541A850 + +#define mmNIC0_QM0_CQ_CTL_MSG_BASE_HI 0x541A854 + +#define mmNIC0_QM0_CQ_CTL_MSG_BASE_LO 0x541A858 + +#define mmNIC0_QM0_ADDR_OVRD 0x541A85C + +#define mmNIC0_QM0_CQ_IFIFO_CI_0 0x541A860 + +#define mmNIC0_QM0_CQ_IFIFO_CI_1 0x541A864 + +#define mmNIC0_QM0_CQ_IFIFO_CI_2 0x541A868 + +#define mmNIC0_QM0_CQ_IFIFO_CI_3 0x541A86C + +#define mmNIC0_QM0_CQ_IFIFO_CI_4 0x541A870 + +#define mmNIC0_QM0_ARC_CQ_IFIFO_CI 0x541A874 + +#define mmNIC0_QM0_CQ_CTL_CI_0 0x541A878 + +#define mmNIC0_QM0_CQ_CTL_CI_1 0x541A87C + +#define mmNIC0_QM0_CQ_CTL_CI_2 0x541A880 + +#define mmNIC0_QM0_CQ_CTL_CI_3 0x541A884 + +#define mmNIC0_QM0_CQ_CTL_CI_4 0x541A888 + +#define mmNIC0_QM0_ARC_CQ_CTL_CI 0x541A88C + +#define mmNIC0_QM0_CP_CFG 0x541A890 + +#define mmNIC0_QM0_CP_EXT_SWITCH 0x541A894 + +#define mmNIC0_QM0_CP_SWITCH_WD_SET 0x541A898 + +#define mmNIC0_QM0_CP_SWITCH_WD 0x541A89C + +#define mmNIC0_QM0_ARC_LB_ADDR_BASE_LO 0x541A8A4 + +#define mmNIC0_QM0_ARC_LB_ADDR_BASE_HI 0x541A8A8 + +#define mmNIC0_QM0_ENGINE_BASE_ADDR_HI 0x541A8AC + +#define mmNIC0_QM0_ENGINE_BASE_ADDR_LO 0x541A8B0 + +#define mmNIC0_QM0_ENGINE_ADDR_RANGE_SIZE 0x541A8B4 + +#define mmNIC0_QM0_QM_ARC_AUX_BASE_ADDR_HI 0x541A8B8 + +#define mmNIC0_QM0_QM_ARC_AUX_BASE_ADDR_LO 0x541A8BC + +#define mmNIC0_QM0_QM_BASE_ADDR_HI 0x541A8C0 + +#define mmNIC0_QM0_QM_BASE_ADDR_LO 0x541A8C4 + +#define mmNIC0_QM0_ARC_PQC_SECURE_PUSH_IND 0x541A8C8 + +#define mmNIC0_QM0_PQC_STS_0_0 0x541A8D0 + +#define mmNIC0_QM0_PQC_STS_0_1 0x541A8D4 + +#define mmNIC0_QM0_PQC_STS_0_2 0x541A8D8 + +#define mmNIC0_QM0_PQC_STS_0_3 0x541A8DC + +#define mmNIC0_QM0_PQC_STS_1_0 0x541A8E0 + +#define mmNIC0_QM0_PQC_STS_1_1 0x541A8E4 + +#define mmNIC0_QM0_PQC_STS_1_2 0x541A8E8 + +#define mmNIC0_QM0_PQC_STS_1_3 0x541A8EC + +#define mmNIC0_QM0_SEI_STATUS 0x541A8F0 + +#define mmNIC0_QM0_SEI_MASK 0x541A8F4 + +#define mmNIC0_QM0_GLBL_ERR_ADDR_LO 0x541AD00 + +#define mmNIC0_QM0_GLBL_ERR_ADDR_HI 0x541AD04 + +#define mmNIC0_QM0_GLBL_ERR_WDATA 0x541AD08 + +#define mmNIC0_QM0_L2H_MASK_LO 0x541AD14 + +#define mmNIC0_QM0_L2H_MASK_HI 0x541AD18 + +#define mmNIC0_QM0_L2H_CMPR_LO 0x541AD1C + +#define mmNIC0_QM0_L2H_CMPR_HI 0x541AD20 + +#define mmNIC0_QM0_LOCAL_RANGE_BASE 0x541AD24 + +#define mmNIC0_QM0_LOCAL_RANGE_SIZE 0x541AD28 + +#define mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_1 0x541AD30 + +#define mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_0 0x541AD34 + +#define mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_1 0x541AD38 + +#define mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_0 0x541AD3C + +#define mmNIC0_QM0_IND_GW_APB_CFG 0x541AD40 + +#define mmNIC0_QM0_IND_GW_APB_WDATA 0x541AD44 + +#define mmNIC0_QM0_IND_GW_APB_RDATA 0x541AD48 + +#define mmNIC0_QM0_IND_GW_APB_STATUS 0x541AD4C + +#define mmNIC0_QM0_PERF_CNT_FREE_LO 0x541AD60 + +#define mmNIC0_QM0_PERF_CNT_FREE_HI 0x541AD64 + +#define mmNIC0_QM0_PERF_CNT_IDLE_LO 0x541AD68 + +#define mmNIC0_QM0_PERF_CNT_IDLE_HI 0x541AD6C + +#define mmNIC0_QM0_PERF_CNT_CFG 0x541AD70 + +#endif /* ASIC_REG_NIC0_QM0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qm_arc_aux0_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qm_arc_aux0_regs.h new file mode 100644 index 000000000000..5f380a44dd21 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qm_arc_aux0_regs.h @@ -0,0 +1,591 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC0_QM_ARC_AUX0_REGS_H_ +#define ASIC_REG_NIC0_QM_ARC_AUX0_REGS_H_ + +/* + ***************************************** + * NIC0_QM_ARC_AUX0 + * (Prototype: QMAN_ARC_AUX) + ***************************************** + */ + +#define mmNIC0_QM_ARC_AUX0_RUN_HALT_REQ 0x5418100 + +#define mmNIC0_QM_ARC_AUX0_RUN_HALT_ACK 0x5418104 + +#define mmNIC0_QM_ARC_AUX0_RST_VEC_ADDR 0x5418108 + +#define mmNIC0_QM_ARC_AUX0_DBG_MODE 0x541810C + +#define mmNIC0_QM_ARC_AUX0_CLUSTER_NUM 0x5418110 + +#define mmNIC0_QM_ARC_AUX0_ARC_NUM 0x5418114 + +#define mmNIC0_QM_ARC_AUX0_WAKE_UP_EVENT 0x5418118 + +#define mmNIC0_QM_ARC_AUX0_DCCM_SYS_ADDR_BASE 0x541811C + +#define mmNIC0_QM_ARC_AUX0_CTI_AP_STS 0x5418120 + +#define mmNIC0_QM_ARC_AUX0_CTI_CFG_MUX_SEL 0x5418124 + +#define mmNIC0_QM_ARC_AUX0_ARC_RST 0x5418128 + +#define mmNIC0_QM_ARC_AUX0_ARC_RST_REQ 0x541812C + +#define mmNIC0_QM_ARC_AUX0_SRAM_LSB_ADDR 0x5418130 + +#define mmNIC0_QM_ARC_AUX0_SRAM_MSB_ADDR 0x5418134 + +#define mmNIC0_QM_ARC_AUX0_PCIE_LSB_ADDR 0x5418138 + +#define mmNIC0_QM_ARC_AUX0_PCIE_MSB_ADDR 0x541813C + +#define mmNIC0_QM_ARC_AUX0_CFG_LSB_ADDR 0x5418140 + +#define mmNIC0_QM_ARC_AUX0_CFG_MSB_ADDR 0x5418144 + +#define mmNIC0_QM_ARC_AUX0_HBM0_LSB_ADDR 0x5418150 + +#define mmNIC0_QM_ARC_AUX0_HBM0_MSB_ADDR 0x5418154 + +#define mmNIC0_QM_ARC_AUX0_HBM1_LSB_ADDR 0x5418158 + +#define mmNIC0_QM_ARC_AUX0_HBM1_MSB_ADDR 0x541815C + +#define mmNIC0_QM_ARC_AUX0_HBM2_LSB_ADDR 0x5418160 + +#define mmNIC0_QM_ARC_AUX0_HBM2_MSB_ADDR 0x5418164 + +#define mmNIC0_QM_ARC_AUX0_HBM3_LSB_ADDR 0x5418168 + +#define mmNIC0_QM_ARC_AUX0_HBM3_MSB_ADDR 0x541816C + +#define mmNIC0_QM_ARC_AUX0_HBM0_OFFSET 0x5418170 + +#define mmNIC0_QM_ARC_AUX0_HBM1_OFFSET 0x5418174 + +#define mmNIC0_QM_ARC_AUX0_HBM2_OFFSET 0x5418178 + +#define mmNIC0_QM_ARC_AUX0_HBM3_OFFSET 0x541817C + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_0 0x5418180 + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_1 0x5418184 + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_2 0x5418188 + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_3 0x541818C + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_4 0x5418190 + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_5 0x5418194 + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_6 0x5418198 + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_0 0x541819C + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_1 0x54181A0 + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_2 0x54181A4 + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_3 0x54181A8 + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_4 0x54181AC + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_5 0x54181B0 + +#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_6 0x54181B4 + +#define mmNIC0_QM_ARC_AUX0_ARC_CBU_AWCACHE_OVR 0x54181B8 + +#define mmNIC0_QM_ARC_AUX0_ARC_LBU_AWCACHE_OVR 0x54181BC + +#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_0 0x54181C0 + +#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_1 0x54181C4 + +#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_2 0x54181C8 + +#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_3 0x54181CC + +#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_4 0x54181D0 + +#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_5 0x54181D4 + +#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_6 0x54181D8 + +#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_7 0x54181DC + +#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_0 0x54181E0 + +#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_1 0x54181E4 + +#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_2 0x54181E8 + +#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_3 0x54181EC + +#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_4 0x54181F0 + +#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_5 0x54181F4 + +#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_6 0x54181F8 + +#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_7 0x54181FC + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_0 0x5418200 + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_1 0x5418204 + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_2 0x5418208 + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_3 0x541820C + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_4 0x5418210 + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_5 0x5418214 + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_6 0x5418218 + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_7 0x541821C + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_8 0x5418220 + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_9 0x5418224 + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_10 0x5418228 + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_11 0x541822C + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_12 0x5418230 + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_13 0x5418234 + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_14 0x5418238 + +#define mmNIC0_QM_ARC_AUX0_SW_INTR_15 0x541823C + +#define mmNIC0_QM_ARC_AUX0_IRQ_INTR_MASK_0 0x5418280 + +#define mmNIC0_QM_ARC_AUX0_IRQ_INTR_MASK_1 0x5418284 + +#define mmNIC0_QM_ARC_AUX0_ARC_SEI_INTR_STS 0x5418290 + +#define mmNIC0_QM_ARC_AUX0_ARC_SEI_INTR_CLR 0x5418294 + +#define mmNIC0_QM_ARC_AUX0_ARC_SEI_INTR_MASK 0x5418298 + +#define mmNIC0_QM_ARC_AUX0_ARC_EXCPTN_CAUSE 0x541829C + +#define mmNIC0_QM_ARC_AUX0_SEI_INTR_HALT_EN 0x54182A0 + +#define mmNIC0_QM_ARC_AUX0_ARC_SEI_INTR_HALT_MASK 0x54182A4 + +#define mmNIC0_QM_ARC_AUX0_QMAN_SEI_INTR_HALT_MASK 0x54182A8 + +#define mmNIC0_QM_ARC_AUX0_ARC_REI_INTR_STS 0x54182B0 + +#define mmNIC0_QM_ARC_AUX0_ARC_REI_INTR_CLR 0x54182B4 + +#define mmNIC0_QM_ARC_AUX0_ARC_REI_INTR_MASK 0x54182B8 + +#define mmNIC0_QM_ARC_AUX0_DCCM_ECC_ERR_ADDR 0x54182BC + +#define mmNIC0_QM_ARC_AUX0_DCCM_ECC_SYNDROME 0x54182C0 + +#define mmNIC0_QM_ARC_AUX0_I_CACHE_ECC_ERR_ADDR 0x54182C4 + +#define mmNIC0_QM_ARC_AUX0_I_CACHE_ECC_SYNDROME 0x54182C8 + +#define mmNIC0_QM_ARC_AUX0_D_CACHE_ECC_ERR_ADDR 0x54182CC + +#define mmNIC0_QM_ARC_AUX0_D_CACHE_ECC_SYNDROME 0x54182D0 + +#define mmNIC0_QM_ARC_AUX0_LBW_TRMINATE_AWADDR_ERR 0x54182E0 + +#define mmNIC0_QM_ARC_AUX0_LBW_TRMINATE_ARADDR_ERR 0x54182E4 + +#define mmNIC0_QM_ARC_AUX0_CFG_LBW_TERMINATE_BRESP 0x54182E8 + +#define mmNIC0_QM_ARC_AUX0_CFG_LBW_TERMINATE_RRESP 0x54182EC + +#define mmNIC0_QM_ARC_AUX0_CFG_LBW_TERMINATE_AXLEN 0x54182F0 + +#define mmNIC0_QM_ARC_AUX0_CFG_LBW_TERMINATE_AXSIZE 0x54182F4 + +#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_0 0x5418300 + +#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_1 0x5418304 + +#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_2 0x5418308 + +#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_3 0x541830C + +#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_4 0x5418310 + +#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_5 0x5418314 + +#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_6 0x5418318 + +#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_7 0x541831C + +#define mmNIC0_QM_ARC_AUX0_TOTAL_CBU_WR_CNT 0x5418320 + +#define mmNIC0_QM_ARC_AUX0_INFLIGHT_CBU_WR_CNT 0x5418324 + +#define mmNIC0_QM_ARC_AUX0_TOTAL_CBU_RD_CNT 0x5418328 + +#define mmNIC0_QM_ARC_AUX0_INFLIGHT_CBU_RD_CNT 0x541832C + +#define mmNIC0_QM_ARC_AUX0_TOTAL_LBU_WR_CNT 0x5418330 + +#define mmNIC0_QM_ARC_AUX0_INFLIGHT_LBU_WR_CNT 0x5418334 + +#define mmNIC0_QM_ARC_AUX0_TOTAL_LBU_RD_CNT 0x5418338 + +#define mmNIC0_QM_ARC_AUX0_INFLIGHT_LBU_RD_CNT 0x541833C + +#define mmNIC0_QM_ARC_AUX0_CBU_ARUSER_OVR 0x5418350 + +#define mmNIC0_QM_ARC_AUX0_CBU_ARUSER_OVR_EN 0x5418354 + +#define mmNIC0_QM_ARC_AUX0_CBU_AWUSER_OVR 0x5418358 + +#define mmNIC0_QM_ARC_AUX0_CBU_AWUSER_OVR_EN 0x541835C + +#define mmNIC0_QM_ARC_AUX0_CBU_ARUSER_MSB_OVR 0x5418360 + +#define mmNIC0_QM_ARC_AUX0_CBU_ARUSER_MSB_OVR_EN 0x5418364 + +#define mmNIC0_QM_ARC_AUX0_CBU_AWUSER_MSB_OVR 0x5418368 + +#define mmNIC0_QM_ARC_AUX0_CBU_AWUSER_MSB_OVR_EN 0x541836C + +#define mmNIC0_QM_ARC_AUX0_CBU_AXCACHE_OVR 0x5418370 + +#define mmNIC0_QM_ARC_AUX0_CBU_LOCK_OVR 0x5418374 + +#define mmNIC0_QM_ARC_AUX0_CBU_PROT_OVR 0x5418378 + +#define mmNIC0_QM_ARC_AUX0_CBU_MAX_OUTSTANDING 0x541837C + +#define mmNIC0_QM_ARC_AUX0_CBU_EARLY_BRESP_EN 0x5418380 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORCE_RSP_OK 0x5418384 + +#define mmNIC0_QM_ARC_AUX0_CBU_NO_WR_INFLIGHT 0x541838C + +#define mmNIC0_QM_ARC_AUX0_CBU_SEI_INTR_ID 0x5418390 + +#define mmNIC0_QM_ARC_AUX0_LBU_ARUSER_OVR 0x5418400 + +#define mmNIC0_QM_ARC_AUX0_LBU_ARUSER_OVR_EN 0x5418404 + +#define mmNIC0_QM_ARC_AUX0_LBU_AWUSER_OVR 0x5418408 + +#define mmNIC0_QM_ARC_AUX0_LBU_AWUSER_OVR_EN 0x541840C + +#define mmNIC0_QM_ARC_AUX0_LBU_AXCACHE_OVR 0x5418420 + +#define mmNIC0_QM_ARC_AUX0_LBU_LOCK_OVR 0x5418424 + +#define mmNIC0_QM_ARC_AUX0_LBU_PROT_OVR 0x5418428 + +#define mmNIC0_QM_ARC_AUX0_LBU_MAX_OUTSTANDING 0x541842C + +#define mmNIC0_QM_ARC_AUX0_LBU_EARLY_BRESP_EN 0x5418430 + +#define mmNIC0_QM_ARC_AUX0_LBU_FORCE_RSP_OK 0x5418434 + +#define mmNIC0_QM_ARC_AUX0_LBU_NO_WR_INFLIGHT 0x541843C + +#define mmNIC0_QM_ARC_AUX0_LBU_SEI_INTR_ID 0x5418440 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_0 0x5418500 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_1 0x5418504 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_2 0x5418508 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_3 0x541850C + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_4 0x5418510 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_5 0x5418514 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_6 0x5418518 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_7 0x541851C + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_0 0x5418520 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_1 0x5418524 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_2 0x5418528 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_3 0x541852C + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_4 0x5418530 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_5 0x5418534 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_6 0x5418538 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_7 0x541853C + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_0 0x5418540 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_1 0x5418544 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_2 0x5418548 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_3 0x541854C + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_4 0x5418550 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_5 0x5418554 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_6 0x5418558 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_7 0x541855C + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_0 0x5418560 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_1 0x5418564 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_2 0x5418568 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_3 0x541856C + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_4 0x5418570 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_5 0x5418574 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_6 0x5418578 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_7 0x541857C + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_0 0x5418580 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_1 0x5418584 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_2 0x5418588 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_3 0x541858C + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_4 0x5418590 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_5 0x5418594 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_6 0x5418598 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_7 0x541859C + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_0 0x54185A0 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_1 0x54185A4 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_2 0x54185A8 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_3 0x54185AC + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_4 0x54185B0 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_5 0x54185B4 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_6 0x54185B8 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_7 0x54185BC + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_0 0x54185C0 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_1 0x54185C4 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_2 0x54185C8 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_3 0x54185CC + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_4 0x54185D0 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_5 0x54185D4 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_6 0x54185D8 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_7 0x54185DC + +#define mmNIC0_QM_ARC_AUX0_GENERAL_Q_VLD_ENTRY_MASK 0x54185E0 + +#define mmNIC0_QM_ARC_AUX0_NIC_Q_VLD_ENTRY_MASK 0x54185E4 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_DROP_EN 0x5418620 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_WARN_MSG 0x5418624 + +#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_ALERT_MSG 0x5418628 + +#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWPROT 0x5418630 + +#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWUSER 0x5418634 + +#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWBURST 0x5418638 + +#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWLOCK 0x541863C + +#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWCACHE 0x5418640 + +#define mmNIC0_QM_ARC_AUX0_DCCM_WRR_ARB_WEIGHT 0x5418644 + +#define mmNIC0_QM_ARC_AUX0_DCCM_Q_PUSH_FIFO_FULL_CFG 0x5418648 + +#define mmNIC0_QM_ARC_AUX0_DCCM_Q_PUSH_FIFO_CNT 0x541864C + +#define mmNIC0_QM_ARC_AUX0_QMAN_CQ_IFIFO_SHADOW_CI 0x5418650 + +#define mmNIC0_QM_ARC_AUX0_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x5418654 + +#define mmNIC0_QM_ARC_AUX0_QMAN_CQ_SHADOW_CI 0x5418658 + +#define mmNIC0_QM_ARC_AUX0_QMAN_ARC_CQ_SHADOW_CI 0x541865C + +#define mmNIC0_QM_ARC_AUX0_AUX2APB_PROT 0x5418700 + +#define mmNIC0_QM_ARC_AUX0_LBW_FORK_WIN_EN 0x5418704 + +#define mmNIC0_QM_ARC_AUX0_QMAN_LBW_FORK_BASE_ADDR0 0x5418708 + +#define mmNIC0_QM_ARC_AUX0_QMAN_LBW_FORK_ADDR_MASK0 0x541870C + +#define mmNIC0_QM_ARC_AUX0_QMAN_LBW_FORK_BASE_ADDR1 0x5418710 + +#define mmNIC0_QM_ARC_AUX0_QMAN_LBW_FORK_ADDR_MASK1 0x5418714 + +#define mmNIC0_QM_ARC_AUX0_FARM_LBW_FORK_BASE_ADDR0 0x5418718 + +#define mmNIC0_QM_ARC_AUX0_FARM_LBW_FORK_ADDR_MASK0 0x541871C + +#define mmNIC0_QM_ARC_AUX0_FARM_LBW_FORK_BASE_ADDR1 0x5418720 + +#define mmNIC0_QM_ARC_AUX0_FARM_LBW_FORK_ADDR_MASK1 0x5418724 + +#define mmNIC0_QM_ARC_AUX0_LBW_APB_FORK_MAX_ADDR0 0x5418728 + +#define mmNIC0_QM_ARC_AUX0_LBW_APB_FORK_MAX_ADDR1 0x541872C + +#define mmNIC0_QM_ARC_AUX0_ARC_ACC_ENGS_LBW_FORK_MASK 0x5418730 + +#define mmNIC0_QM_ARC_AUX0_ARC_DUP_ENG_LBW_FORK_ADDR 0x5418734 + +#define mmNIC0_QM_ARC_AUX0_ARC_ACP_ENG_LBW_FORK_ADDR 0x5418738 + +#define mmNIC0_QM_ARC_AUX0_ARC_ACC_ENGS_VIRTUAL_ADDR 0x541873C + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_WIN_EN 0x5418740 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR0_LSB 0x5418750 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR0_MSB 0x5418754 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK0_LSB 0x5418758 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK0_MSB 0x541875C + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR1_LSB 0x5418760 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR1_MSB 0x5418764 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK1_LSB 0x5418768 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK1_MSB 0x541876C + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR2_LSB 0x5418770 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR2_MSB 0x5418774 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK2_LSB 0x5418778 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK2_MSB 0x541877C + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR3_LSB 0x5418780 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR3_MSB 0x5418784 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK3_LSB 0x5418788 + +#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK3_MSB 0x541878C + +#define mmNIC0_QM_ARC_AUX0_CBU_TRMINATE_ARADDR_LSB 0x5418790 + +#define mmNIC0_QM_ARC_AUX0_CBU_TRMINATE_ARADDR_MSB 0x5418794 + +#define mmNIC0_QM_ARC_AUX0_CFG_CBU_TERMINATE_BRESP 0x5418798 + +#define mmNIC0_QM_ARC_AUX0_CFG_CBU_TERMINATE_RRESP 0x541879C + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_0 0x5418800 + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_1 0x5418804 + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_2 0x5418808 + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_3 0x541880C + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_4 0x5418810 + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_5 0x5418814 + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_6 0x5418818 + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_7 0x541881C + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_8 0x5418820 + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_9 0x5418824 + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_10 0x5418828 + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_11 0x541882C + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_12 0x5418830 + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_13 0x5418834 + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_14 0x5418838 + +#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_15 0x541883C + +#define mmNIC0_QM_ARC_AUX0_DCCM_TRMINATE_AWADDR_ERR 0x5418840 + +#define mmNIC0_QM_ARC_AUX0_DCCM_TRMINATE_ARADDR_ERR 0x5418844 + +#define mmNIC0_QM_ARC_AUX0_CFG_DCCM_TERMINATE_BRESP 0x5418848 + +#define mmNIC0_QM_ARC_AUX0_CFG_DCCM_TERMINATE_RRESP 0x541884C + +#define mmNIC0_QM_ARC_AUX0_CFG_DCCM_TERMINATE_EN 0x5418850 + +#define mmNIC0_QM_ARC_AUX0_CFG_DCCM_SECURE_REGION 0x5418854 + +#define mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_WR_IF_CNT 0x5418900 + +#define mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_CTL 0x5418904 + +#define mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_ADDR_MSK 0x5418908 + +#define mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_ADDR 0x541890C + +#define mmNIC0_QM_ARC_AUX0_ARC_ACC_ENGS_BUSER 0x5418910 + +#define mmNIC0_QM_ARC_AUX0_MME_ARC_UPPER_DCCM_EN 0x5418920 + +#endif /* ASIC_REG_NIC0_QM_ARC_AUX0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qpc0_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qpc0_regs.h new file mode 100644 index 000000000000..eaee29da4244 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_qpc0_regs.h @@ -0,0 +1,905 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC0_QPC0_REGS_H_ +#define ASIC_REG_NIC0_QPC0_REGS_H_ + +/* + ***************************************** + * NIC0_QPC0 + * (Prototype: NIC_QPC) + ***************************************** + */ + +#define mmNIC0_QPC0_REQ_QPC_CACHE_INVALIDATE 0x541F000 + +#define mmNIC0_QPC0_REQ_QPC_CACHE_INV_STATUS 0x541F004 + +#define mmNIC0_QPC0_REQ_STATIC_CONFIG 0x541F008 + +#define mmNIC0_QPC0_REQ_BASE_ADDRESS_63_32 0x541F00C + +#define mmNIC0_QPC0_REQ_BASE_ADDRESS_31_7 0x541F010 + +#define mmNIC0_QPC0_REQ_CLEAN_LINK_LIST 0x541F014 + +#define mmNIC0_QPC0_REQ_ERR_FIFO_PUSH_63_32 0x541F018 + +#define mmNIC0_QPC0_REQ_ERR_FIFO_PUSH_31_0 0x541F01C + +#define mmNIC0_QPC0_REQ_ERR_QP_STATE_63_32 0x541F020 + +#define mmNIC0_QPC0_REQ_ERR_QP_STATE_31_0 0x541F024 + +#define mmNIC0_QPC0_RETRY_COUNT_MAX 0x541F028 + +#define mmNIC0_QPC0_AXI_PROT 0x541F030 + +#define mmNIC0_QPC0_RES_QPC_CACHE_INVALIDATE 0x541F034 + +#define mmNIC0_QPC0_RES_QPC_CACHE_INV_STATUS 0x541F038 + +#define mmNIC0_QPC0_RES_STATIC_CONFIG 0x541F03C + +#define mmNIC0_QPC0_RES_BASE_ADDRESS_63_32 0x541F040 + +#define mmNIC0_QPC0_RES_BASE_ADDRESS_31_7 0x541F044 + +#define mmNIC0_QPC0_RES_CLEAN_LINK_LIST 0x541F048 + +#define mmNIC0_QPC0_ERR_FIFO_WRITE_INDEX 0x541F050 + +#define mmNIC0_QPC0_ERR_FIFO_PRODUCER_INDEX 0x541F054 + +#define mmNIC0_QPC0_ERR_FIFO_CONSUMER_INDEX 0x541F058 + +#define mmNIC0_QPC0_ERR_FIFO_MASK 0x541F05C + +#define mmNIC0_QPC0_ERR_FIFO_CREDIT 0x541F060 + +#define mmNIC0_QPC0_ERR_FIFO_CFG 0x541F064 + +#define mmNIC0_QPC0_ERR_FIFO_INTR_MASK 0x541F068 + +#define mmNIC0_QPC0_ERR_FIFO_BASE_ADDR_63_32 0x541F06C + +#define mmNIC0_QPC0_ERR_FIFO_BASE_ADDR_31_7 0x541F070 + +#define mmNIC0_QPC0_GW_BUSY 0x541F080 + +#define mmNIC0_QPC0_GW_CTRL 0x541F084 + +#define mmNIC0_QPC0_GW_DATA_0 0x541F08C + +#define mmNIC0_QPC0_GW_DATA_1 0x541F090 + +#define mmNIC0_QPC0_GW_DATA_2 0x541F094 + +#define mmNIC0_QPC0_GW_DATA_3 0x541F098 + +#define mmNIC0_QPC0_GW_DATA_4 0x541F09C + +#define mmNIC0_QPC0_GW_DATA_5 0x541F0A0 + +#define mmNIC0_QPC0_GW_DATA_6 0x541F0A4 + +#define mmNIC0_QPC0_GW_DATA_7 0x541F0A8 + +#define mmNIC0_QPC0_GW_DATA_8 0x541F0AC + +#define mmNIC0_QPC0_GW_DATA_9 0x541F0B0 + +#define mmNIC0_QPC0_GW_DATA_10 0x541F0B4 + +#define mmNIC0_QPC0_GW_DATA_11 0x541F0B8 + +#define mmNIC0_QPC0_GW_DATA_12 0x541F0BC + +#define mmNIC0_QPC0_GW_DATA_13 0x541F0C0 + +#define mmNIC0_QPC0_GW_DATA_14 0x541F0C4 + +#define mmNIC0_QPC0_GW_DATA_15 0x541F0C8 + +#define mmNIC0_QPC0_GW_DATA_16 0x541F0CC + +#define mmNIC0_QPC0_GW_DATA_17 0x541F0D0 + +#define mmNIC0_QPC0_GW_DATA_18 0x541F0D4 + +#define mmNIC0_QPC0_GW_DATA_19 0x541F0D8 + +#define mmNIC0_QPC0_GW_DATA_20 0x541F0DC + +#define mmNIC0_QPC0_GW_DATA_21 0x541F0E0 + +#define mmNIC0_QPC0_GW_DATA_22 0x541F0E4 + +#define mmNIC0_QPC0_GW_DATA_23 0x541F0E8 + +#define mmNIC0_QPC0_GW_DATA_24 0x541F0EC + +#define mmNIC0_QPC0_GW_DATA_25 0x541F0F0 + +#define mmNIC0_QPC0_GW_DATA_26 0x541F0F4 + +#define mmNIC0_QPC0_GW_DATA_27 0x541F0F8 + +#define mmNIC0_QPC0_GW_DATA_28 0x541F0FC + +#define mmNIC0_QPC0_GW_DATA_29 0x541F100 + +#define mmNIC0_QPC0_GW_DATA_30 0x541F104 + +#define mmNIC0_QPC0_GW_DATA_31 0x541F108 + +#define mmNIC0_QPC0_GW_MASK_0 0x541F124 + +#define mmNIC0_QPC0_GW_MASK_1 0x541F128 + +#define mmNIC0_QPC0_GW_MASK_2 0x541F12C + +#define mmNIC0_QPC0_GW_MASK_3 0x541F130 + +#define mmNIC0_QPC0_GW_MASK_4 0x541F134 + +#define mmNIC0_QPC0_GW_MASK_5 0x541F138 + +#define mmNIC0_QPC0_GW_MASK_6 0x541F13C + +#define mmNIC0_QPC0_GW_MASK_7 0x541F140 + +#define mmNIC0_QPC0_GW_MASK_8 0x541F144 + +#define mmNIC0_QPC0_GW_MASK_9 0x541F148 + +#define mmNIC0_QPC0_GW_MASK_10 0x541F14C + +#define mmNIC0_QPC0_GW_MASK_11 0x541F150 + +#define mmNIC0_QPC0_GW_MASK_12 0x541F154 + +#define mmNIC0_QPC0_GW_MASK_13 0x541F158 + +#define mmNIC0_QPC0_GW_MASK_14 0x541F15C + +#define mmNIC0_QPC0_GW_MASK_15 0x541F160 + +#define mmNIC0_QPC0_GW_MASK_16 0x541F164 + +#define mmNIC0_QPC0_GW_MASK_17 0x541F168 + +#define mmNIC0_QPC0_GW_MASK_18 0x541F16C + +#define mmNIC0_QPC0_GW_MASK_19 0x541F170 + +#define mmNIC0_QPC0_GW_MASK_20 0x541F174 + +#define mmNIC0_QPC0_GW_MASK_21 0x541F178 + +#define mmNIC0_QPC0_GW_MASK_22 0x541F17C + +#define mmNIC0_QPC0_GW_MASK_23 0x541F180 + +#define mmNIC0_QPC0_GW_MASK_24 0x541F184 + +#define mmNIC0_QPC0_GW_MASK_25 0x541F188 + +#define mmNIC0_QPC0_GW_MASK_26 0x541F18C + +#define mmNIC0_QPC0_GW_MASK_27 0x541F190 + +#define mmNIC0_QPC0_GW_MASK_28 0x541F194 + +#define mmNIC0_QPC0_GW_MASK_29 0x541F198 + +#define mmNIC0_QPC0_GW_MASK_30 0x541F19C + +#define mmNIC0_QPC0_GW_MASK_31 0x541F1A0 + +#define mmNIC0_QPC0_CC_TIMEOUT 0x541F1B0 + +#define mmNIC0_QPC0_CC_WINDOW_INC_EN 0x541F1FC + +#define mmNIC0_QPC0_CC_TICK_WRAP 0x541F200 + +#define mmNIC0_QPC0_CC_ROLLBACK 0x541F204 + +#define mmNIC0_QPC0_CC_MAX_WINDOW_SIZE 0x541F208 + +#define mmNIC0_QPC0_CC_MIN_WINDOW_SIZE 0x541F20C + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_0 0x541F210 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_1 0x541F214 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_2 0x541F218 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_3 0x541F21C + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_4 0x541F220 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_5 0x541F224 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_6 0x541F228 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_7 0x541F22C + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_8 0x541F230 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_9 0x541F234 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_10 0x541F238 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_11 0x541F23C + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_12 0x541F240 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_13 0x541F244 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_14 0x541F248 + +#define mmNIC0_QPC0_CC_ALPHA_LINEAR_15 0x541F24C + +#define mmNIC0_QPC0_CC_ALPHA_LOG_0 0x541F250 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_1 0x541F254 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_2 0x541F258 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_3 0x541F25C + +#define mmNIC0_QPC0_CC_ALPHA_LOG_4 0x541F260 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_5 0x541F264 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_6 0x541F268 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_7 0x541F26C + +#define mmNIC0_QPC0_CC_ALPHA_LOG_8 0x541F270 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_9 0x541F274 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_10 0x541F278 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_11 0x541F27C + +#define mmNIC0_QPC0_CC_ALPHA_LOG_12 0x541F280 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_13 0x541F284 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_14 0x541F288 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_15 0x541F28C + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_0 0x541F290 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_1 0x541F294 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_2 0x541F298 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_3 0x541F29C + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_4 0x541F2A0 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_5 0x541F2A4 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_6 0x541F2A8 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_7 0x541F2AC + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_8 0x541F2B0 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_9 0x541F2B4 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_10 0x541F2B8 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_11 0x541F2BC + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_12 0x541F2C0 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_13 0x541F2C4 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_14 0x541F2C8 + +#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_15 0x541F2CC + +#define mmNIC0_QPC0_CC_WINDOW_INC_0 0x541F2D0 + +#define mmNIC0_QPC0_CC_WINDOW_INC_1 0x541F2D4 + +#define mmNIC0_QPC0_CC_WINDOW_INC_2 0x541F2D8 + +#define mmNIC0_QPC0_CC_WINDOW_INC_3 0x541F2DC + +#define mmNIC0_QPC0_CC_WINDOW_INC_4 0x541F2E0 + +#define mmNIC0_QPC0_CC_WINDOW_INC_5 0x541F2E4 + +#define mmNIC0_QPC0_CC_WINDOW_INC_6 0x541F2E8 + +#define mmNIC0_QPC0_CC_WINDOW_INC_7 0x541F2EC + +#define mmNIC0_QPC0_CC_WINDOW_INC_8 0x541F2F0 + +#define mmNIC0_QPC0_CC_WINDOW_INC_9 0x541F2F4 + +#define mmNIC0_QPC0_CC_WINDOW_INC_10 0x541F2F8 + +#define mmNIC0_QPC0_CC_WINDOW_INC_11 0x541F2FC + +#define mmNIC0_QPC0_CC_WINDOW_INC_12 0x541F300 + +#define mmNIC0_QPC0_CC_WINDOW_INC_13 0x541F304 + +#define mmNIC0_QPC0_CC_WINDOW_INC_14 0x541F308 + +#define mmNIC0_QPC0_CC_WINDOW_INC_15 0x541F30C + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_0 0x541F310 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_1 0x541F314 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_2 0x541F318 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_3 0x541F31C + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_4 0x541F320 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_5 0x541F324 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_6 0x541F328 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_7 0x541F32C + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_8 0x541F330 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_9 0x541F334 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_10 0x541F338 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_11 0x541F33C + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_12 0x541F340 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_13 0x541F344 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_14 0x541F348 + +#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_15 0x541F34C + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_0 0x541F360 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_1 0x541F364 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_2 0x541F368 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_3 0x541F36C + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_4 0x541F370 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_5 0x541F374 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_6 0x541F378 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_7 0x541F37C + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_8 0x541F380 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_9 0x541F384 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_10 0x541F388 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_11 0x541F38C + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_12 0x541F390 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_13 0x541F394 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_14 0x541F398 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_15 0x541F39C + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_16 0x541F3A0 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_17 0x541F3A4 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_18 0x541F3A8 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_19 0x541F3AC + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_20 0x541F3B0 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_21 0x541F3B4 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_22 0x541F3B8 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_23 0x541F3BC + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_24 0x541F3C0 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_25 0x541F3C4 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_26 0x541F3C8 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_27 0x541F3CC + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_28 0x541F3D0 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_29 0x541F3D4 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_30 0x541F3D8 + +#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_31 0x541F3DC + +#define mmNIC0_QPC0_DB_FIFO_CFG_0 0x541F3E0 + +#define mmNIC0_QPC0_DB_FIFO_CFG_1 0x541F3E4 + +#define mmNIC0_QPC0_DB_FIFO_CFG_2 0x541F3E8 + +#define mmNIC0_QPC0_DB_FIFO_CFG_3 0x541F3EC + +#define mmNIC0_QPC0_DB_FIFO_CFG_4 0x541F3F0 + +#define mmNIC0_QPC0_DB_FIFO_CFG_5 0x541F3F4 + +#define mmNIC0_QPC0_DB_FIFO_CFG_6 0x541F3F8 + +#define mmNIC0_QPC0_DB_FIFO_CFG_7 0x541F3FC + +#define mmNIC0_QPC0_DB_FIFO_CFG_8 0x541F400 + +#define mmNIC0_QPC0_DB_FIFO_CFG_9 0x541F404 + +#define mmNIC0_QPC0_DB_FIFO_CFG_10 0x541F408 + +#define mmNIC0_QPC0_DB_FIFO_CFG_11 0x541F40C + +#define mmNIC0_QPC0_DB_FIFO_CFG_12 0x541F410 + +#define mmNIC0_QPC0_DB_FIFO_CFG_13 0x541F414 + +#define mmNIC0_QPC0_DB_FIFO_CFG_14 0x541F418 + +#define mmNIC0_QPC0_DB_FIFO_CFG_15 0x541F41C + +#define mmNIC0_QPC0_DB_FIFO_CFG_16 0x541F420 + +#define mmNIC0_QPC0_DB_FIFO_CFG_17 0x541F424 + +#define mmNIC0_QPC0_DB_FIFO_CFG_18 0x541F428 + +#define mmNIC0_QPC0_DB_FIFO_CFG_19 0x541F42C + +#define mmNIC0_QPC0_DB_FIFO_CFG_20 0x541F430 + +#define mmNIC0_QPC0_DB_FIFO_CFG_21 0x541F434 + +#define mmNIC0_QPC0_DB_FIFO_CFG_22 0x541F438 + +#define mmNIC0_QPC0_DB_FIFO_CFG_23 0x541F43C + +#define mmNIC0_QPC0_DB_FIFO_CFG_24 0x541F440 + +#define mmNIC0_QPC0_DB_FIFO_CFG_25 0x541F444 + +#define mmNIC0_QPC0_DB_FIFO_CFG_26 0x541F448 + +#define mmNIC0_QPC0_DB_FIFO_CFG_27 0x541F44C + +#define mmNIC0_QPC0_DB_FIFO_CFG_28 0x541F450 + +#define mmNIC0_QPC0_DB_FIFO_CFG_29 0x541F454 + +#define mmNIC0_QPC0_DB_FIFO_CFG_30 0x541F458 + +#define mmNIC0_QPC0_DB_FIFO_CFG_31 0x541F45C + +#define mmNIC0_QPC0_SECURED_DB_FIRST32 0x541F460 + +#define mmNIC0_QPC0_SECURED_DB_SECOND32 0x541F464 + +#define mmNIC0_QPC0_SECURED_DB_THIRD32 0x541F468 + +#define mmNIC0_QPC0_SECURED_DB_FOURTH32 0x541F46C + +#define mmNIC0_QPC0_PRIVILEGE_DB_FIRST32 0x541F470 + +#define mmNIC0_QPC0_PRIVILEGE_DB_SECOND32 0x541F474 + +#define mmNIC0_QPC0_PRIVILEGE_DB_THIRD32 0x541F478 + +#define mmNIC0_QPC0_PRIVILEGE_DB_FOURTH32 0x541F47C + +#define mmNIC0_QPC0_DBG_INDICATION 0x541F480 + +#define mmNIC0_QPC0_WTD_WC_FSM 0x541F484 + +#define mmNIC0_QPC0_WTD_SLICE_FSM 0x541F488 + +#define mmNIC0_QPC0_REQ_TX_EMPTY_CNT 0x541F48C + +#define mmNIC0_QPC0_RES_TX_EMPTY_CNT 0x541F490 + +#define mmNIC0_QPC0_NUM_ROLLBACKS 0x541F494 + +#define mmNIC0_QPC0_LAST_QP_ROLLED_BACK 0x541F498 + +#define mmNIC0_QPC0_NUM_TIMEOUTS 0x541F49C + +#define mmNIC0_QPC0_LAST_QP_TIMED_OUT 0x541F4A0 + +#define mmNIC0_QPC0_WTD_SLICE_FSM_HI 0x541F4A4 + +#define mmNIC0_QPC0_INTERRUPT_BASE_0 0x541F4B0 + +#define mmNIC0_QPC0_INTERRUPT_BASE_1 0x541F4B4 + +#define mmNIC0_QPC0_INTERRUPT_BASE_2 0x541F4B8 + +#define mmNIC0_QPC0_INTERRUPT_BASE_3 0x541F4BC + +#define mmNIC0_QPC0_INTERRUPT_BASE_4 0x541F4C0 + +#define mmNIC0_QPC0_INTERRUPT_BASE_5 0x541F4C4 + +#define mmNIC0_QPC0_INTERRUPT_BASE_6 0x541F4C8 + +#define mmNIC0_QPC0_INTERRUPT_BASE_7 0x541F4CC + +#define mmNIC0_QPC0_INTERRUPT_BASE_8 0x541F4D0 + +#define mmNIC0_QPC0_INTERRUPT_BASE_9 0x541F4D4 + +#define mmNIC0_QPC0_INTERRUPT_BASE_10 0x541F4D8 + +#define mmNIC0_QPC0_INTERRUPT_DATA_0 0x541F4DC + +#define mmNIC0_QPC0_INTERRUPT_DATA_1 0x541F4E0 + +#define mmNIC0_QPC0_INTERRUPT_DATA_2 0x541F4E4 + +#define mmNIC0_QPC0_INTERRUPT_DATA_3 0x541F4E8 + +#define mmNIC0_QPC0_INTERRUPT_DATA_4 0x541F4EC + +#define mmNIC0_QPC0_INTERRUPT_DATA_5 0x541F4F0 + +#define mmNIC0_QPC0_INTERRUPT_DATA_6 0x541F4F4 + +#define mmNIC0_QPC0_INTERRUPT_DATA_7 0x541F4F8 + +#define mmNIC0_QPC0_INTERRUPT_DATA_8 0x541F4FC + +#define mmNIC0_QPC0_INTERRUPT_DATA_9 0x541F500 + +#define mmNIC0_QPC0_INTERRUPT_DATA_10 0x541F504 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_0 0x541F600 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_1 0x541F604 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_2 0x541F608 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_3 0x541F60C + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_4 0x541F610 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_5 0x541F614 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_6 0x541F618 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_7 0x541F61C + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_8 0x541F620 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_9 0x541F624 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_10 0x541F628 + +#define mmNIC0_QPC0_DBG_COUNT_SELECT_11 0x541F62C + +#define mmNIC0_QPC0_DOORBELL_SECURITY 0x541F648 + +#define mmNIC0_QPC0_DBG_CFG 0x541F64C + +#define mmNIC0_QPC0_RES_RING0_PI 0x541F650 + +#define mmNIC0_QPC0_RES_RING0_CI 0x541F654 + +#define mmNIC0_QPC0_RES_RING0_CFG 0x541F658 + +#define mmNIC0_QPC0_RES_RING1_PI 0x541F65C + +#define mmNIC0_QPC0_RES_RING1_CI 0x541F660 + +#define mmNIC0_QPC0_RES_RING1_CFG 0x541F664 + +#define mmNIC0_QPC0_RES_RING2_PI 0x541F668 + +#define mmNIC0_QPC0_RES_RING2_CI 0x541F66C + +#define mmNIC0_QPC0_RES_RING2_CFG 0x541F670 + +#define mmNIC0_QPC0_RES_RING3_PI 0x541F674 + +#define mmNIC0_QPC0_RES_RING3_CI 0x541F678 + +#define mmNIC0_QPC0_RES_RING3_CFG 0x541F67C + +#define mmNIC0_QPC0_REQ_RING0_CI 0x541F680 + +#define mmNIC0_QPC0_REQ_RING1_CI 0x541F684 + +#define mmNIC0_QPC0_REQ_RING2_CI 0x541F688 + +#define mmNIC0_QPC0_REQ_RING3_CI 0x541F68C + +#define mmNIC0_QPC0_INTERRUPT_CAUSE 0x541F690 + +#define mmNIC0_QPC0_INTERRUPT_MASK 0x541F694 + +#define mmNIC0_QPC0_INTERRUPT_CLR 0x541F698 + +#define mmNIC0_QPC0_INTERRUPT_EN 0x541F69C + +#define mmNIC0_QPC0_INTERRUPT_CFG 0x541F6F0 + +#define mmNIC0_QPC0_INTERRUPT_RESP_ERR_CAUSE 0x541F6F4 + +#define mmNIC0_QPC0_INTERRUPT_RESP_ERR_MASK 0x541F6F8 + +#define mmNIC0_QPC0_INTERRUPR_RESP_ERR_CLR 0x541F700 + +#define mmNIC0_QPC0_TMR_GW_VALID 0x541F704 + +#define mmNIC0_QPC0_TMR_GW_DATA0 0x541F708 + +#define mmNIC0_QPC0_TMR_GW_DATA1 0x541F70C + +#define mmNIC0_QPC0_RNR_RETRY_COUNT_EN 0x541F710 + +#define mmNIC0_QPC0_EVENT_QUE_BASE_ADDR_63_32 0x541F830 + +#define mmNIC0_QPC0_EVENT_QUE_BASE_ADDR_31_7 0x541F834 + +#define mmNIC0_QPC0_EVENT_QUE_LOG_SIZE 0x541F838 + +#define mmNIC0_QPC0_EVENT_QUE_WRITE_INDEX 0x541F83C + +#define mmNIC0_QPC0_EVENT_QUE_PRODUCER_INDEX 0x541F840 + +#define mmNIC0_QPC0_EVENT_QUE_PI_ADDR_63_32 0x541F844 + +#define mmNIC0_QPC0_EVENT_QUE_PI_ADDR_31_7 0x541F848 + +#define mmNIC0_QPC0_EVENT_QUE_CONSUMER_INDEX_CB 0x541F84C + +#define mmNIC0_QPC0_EVENT_QUE_CFG 0x541F850 + +#define mmNIC0_QPC0_LBW_PROT 0x541F858 + +#define mmNIC0_QPC0_MEM_WRITE_INIT 0x541F85C + +#define mmNIC0_QPC0_QMAN_DOORBELL 0x541F8E8 + +#define mmNIC0_QPC0_QMAN_DOORBELL_QPN 0x541F8EC + +#define mmNIC0_QPC0_SECURED_CQ_NUMBER 0x541F8F0 + +#define mmNIC0_QPC0_SECURED_CQ_CONSUMER_INDEX 0x541F8F4 + +#define mmNIC0_QPC0_PRIVILEGE_CQ_NUMBER 0x541F8F8 + +#define mmNIC0_QPC0_PRIVILEGE_CQ_CONSUMER_INDEX 0x541F8FC + +#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_0 0x541F900 + +#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_1 0x541F904 + +#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_2 0x541F908 + +#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_3 0x541F90C + +#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_0 0x541F910 + +#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_1 0x541F914 + +#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_2 0x541F918 + +#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_3 0x541F91C + +#define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_0 0x541F920 + +#define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_1 0x541F924 + +#define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_2 0x541F928 + +#define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_3 0x541F92C + +#define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_0 0x541F930 + +#define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_1 0x541F934 + +#define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_2 0x541F938 + +#define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_3 0x541F93C + +#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_0 0x541F940 + +#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_1 0x541F944 + +#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_2 0x541F948 + +#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_3 0x541F94C + +#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_0 0x541F950 + +#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_1 0x541F954 + +#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_2 0x541F958 + +#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_3 0x541F95C + +#define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_0 0x541F960 + +#define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_1 0x541F964 + +#define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_2 0x541F968 + +#define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_3 0x541F96C + +#define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_0 0x541F970 + +#define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_1 0x541F974 + +#define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_2 0x541F978 + +#define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_3 0x541F97C + +#define mmNIC0_QPC0_WQE_MEM_WRITE_AXI_PROT 0x541F980 + +#define mmNIC0_QPC0_WQ_UPPER_THRESHOLD 0x541F984 + +#define mmNIC0_QPC0_WQ_LOWER_THRESHOLD 0x541F988 + +#define mmNIC0_QPC0_WQ_BP_2ARC_ADDR 0x541F98C + +#define mmNIC0_QPC0_WQ_BP_2QMAN_ADDR 0x541F990 + +#define mmNIC0_QPC0_WTD_CONFIG 0x541F994 + +#define mmNIC0_QPC0_REQTX_ERR_FIFO_PUSH_63_32 0x541F998 + +#define mmNIC0_QPC0_REQTX_ERR_FIFO_PUSH_31_0 0x541F99C + +#define mmNIC0_QPC0_REQTX_ERR_QP_STATE_63_32 0x541F9A0 + +#define mmNIC0_QPC0_REQTX_ERR_QP_STATE_31_0 0x541F9A4 + +#define mmNIC0_QPC0_EVENT_QUE_CONSUMER_INDEX 0x541F9A8 + +#define mmNIC0_QPC0_ARM_CQ_NUM 0x541F9AC + +#define mmNIC0_QPC0_ARM_CQ_INDEX 0x541F9B0 + +#define mmNIC0_QPC0_QPC_CLOCK_GATE 0x541F9B4 + +#define mmNIC0_QPC0_QPC_CLOCK_GATE_DIS 0x541F9B8 + +#define mmNIC0_QPC0_CONG_QUE_BASE_ADDR_63_32 0x541F9BC + +#define mmNIC0_QPC0_CONG_QUE_BASE_ADDR_31_7 0x541F9C0 + +#define mmNIC0_QPC0_CONG_QUE_LOG_SIZE 0x541F9C4 + +#define mmNIC0_QPC0_CONG_QUE_WRITE_INDEX 0x541F9C8 + +#define mmNIC0_QPC0_CONG_QUE_PRODUCER_INDEX 0x541F9CC + +#define mmNIC0_QPC0_CONG_QUE_PI_ADDR_63_32 0x541F9D0 + +#define mmNIC0_QPC0_CONG_QUE_PI_ADDR_31_7 0x541F9D4 + +#define mmNIC0_QPC0_CONG_QUE_CONSUMER_INDEX_CB 0x541F9D8 + +#define mmNIC0_QPC0_CONG_QUE_CFG 0x541F9DC + +#define mmNIC0_QPC0_CONG_QUE_CONSUMER_INDEX 0x541F9E0 + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_0 0x541FA00 + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_1 0x541FA04 + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_2 0x541FA08 + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_3 0x541FA0C + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_4 0x541FA10 + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_5 0x541FA14 + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_6 0x541FA18 + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_7 0x541FA1C + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_8 0x541FA20 + +#define mmNIC0_QPC0_LINEAR_WQE_STATIC_9 0x541FA24 + +#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_0 0x541FA40 + +#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_1 0x541FA44 + +#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_2 0x541FA48 + +#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_3 0x541FA4C + +#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_4 0x541FA50 + +#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_5 0x541FA54 + +#define mmNIC0_QPC0_LINEAR_WQE_QPN 0x541FA58 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_0 0x541FA80 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_1 0x541FA84 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_2 0x541FA88 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_3 0x541FA8C + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_4 0x541FA90 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_5 0x541FA94 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_6 0x541FA98 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_7 0x541FA9C + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_8 0x541FAA0 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_9 0x541FAA4 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_10 0x541FAA8 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_11 0x541FAAC + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_12 0x541FAB0 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_13 0x541FAB4 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_14 0x541FAB8 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_15 0x541FABC + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_16 0x541FAC0 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_17 0x541FAC4 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_0 0x541FAE0 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_1 0x541FAE4 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_2 0x541FAE8 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_3 0x541FAEC + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_4 0x541FAF0 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_5 0x541FAF4 + +#define mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN 0x541FAF8 + +#endif /* ASIC_REG_NIC0_QPC0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_umr0_0_completion_queue_ci_1_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_umr0_0_completion_queue_ci_1_regs.h new file mode 100644 index 000000000000..2153319a50a0 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_umr0_0_completion_queue_ci_1_regs.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_REGS_H_ +#define ASIC_REG_NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_REGS_H_ + +/* + ***************************************** + * NIC0_UMR0_0_COMPLETION_QUEUE_CI_1 + * (Prototype: COMPLETION_QUEUE_CI) + ***************************************** + */ + +#define mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_NUMBER 0x5400180 + +#define mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX 0x5400184 + +#endif /* ASIC_REG_NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_umr0_0_unsecure_doorbell0_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_umr0_0_unsecure_doorbell0_regs.h new file mode 100644 index 000000000000..de8eac74c2fb --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/nic0_umr0_0_unsecure_doorbell0_regs.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC0_UMR0_0_UNSECURE_DOORBELL0_REGS_H_ +#define ASIC_REG_NIC0_UMR0_0_UNSECURE_DOORBELL0_REGS_H_ + +/* + ***************************************** + * NIC0_UMR0_0_UNSECURE_DOORBELL0 + * (Prototype: NIC_UNSEC_DBELL) + ***************************************** + */ + +#define mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 0x5400000 + +#define mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_SECOND32 0x5400004 + +#define mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_THIRD32 0x5400008 + +#define mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FOURTH32 0x540000C + +#endif /* ASIC_REG_NIC0_UMR0_0_UNSECURE_DOORBELL0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_aux_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_aux_regs.h new file mode 100644 index 000000000000..44182fc18234 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_aux_regs.h @@ -0,0 +1,293 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_AUX_REGS_H_ +#define ASIC_REG_PCIE_AUX_REGS_H_ + +/* + ***************************************** + * PCIE_AUX + * (Prototype: PCIE_AUX) + ***************************************** + */ + +#define mmPCIE_AUX_APB_TIMEOUT 0x4C07004 + +#define mmPCIE_AUX_SW_GENERAL_PURPOSE_0 0x4C07008 + +#define mmPCIE_AUX_SW_GENERAL_PURPOSE_1 0x4C0700C + +#define mmPCIE_AUX_SW_GENERAL_PURPOSE_2 0x4C07010 + +#define mmPCIE_AUX_SW_GENERAL_PURPOSE_3 0x4C07014 + +#define mmPCIE_AUX_SW_GENERAL_PURPOSE_4 0x4C07018 + +#define mmPCIE_AUX_SW_GENERAL_PURPOSE_5 0x4C0701C + +#define mmPCIE_AUX_SW_GENERAL_PURPOSE_6 0x4C07020 + +#define mmPCIE_AUX_SW_GENERAL_PURPOSE_7 0x4C07024 + +#define mmPCIE_AUX_PHY_INIT 0x4C07100 + +#define mmPCIE_AUX_LTR_MAX_LATENCY 0x4C07138 + +#define mmPCIE_AUX_BAR0_START_L 0x4C07160 + +#define mmPCIE_AUX_BAR0_START_H 0x4C07164 + +#define mmPCIE_AUX_BAR1_START 0x4C07168 + +#define mmPCIE_AUX_BAR2_START_L 0x4C0716C + +#define mmPCIE_AUX_BAR2_START_H 0x4C07170 + +#define mmPCIE_AUX_BAR3_START 0x4C07174 + +#define mmPCIE_AUX_BAR4_START_L 0x4C07178 + +#define mmPCIE_AUX_BAR4_START_H 0x4C0717C + +#define mmPCIE_AUX_BAR5_START 0x4C07180 + +#define mmPCIE_AUX_BAR0_LIMIT_L 0x4C07184 + +#define mmPCIE_AUX_BAR0_LIMIT_H 0x4C07188 + +#define mmPCIE_AUX_BAR1_LIMIT 0x4C0718C + +#define mmPCIE_AUX_BAR2_LIMIT_L 0x4C07190 + +#define mmPCIE_AUX_BAR2_LIMIT_H 0x4C07194 + +#define mmPCIE_AUX_BAR3_LIMIT 0x4C07198 + +#define mmPCIE_AUX_BAR4_LIMIT_L 0x4C0719C + +#define mmPCIE_AUX_BAR4_LIMIT_H 0x4C07200 + +#define mmPCIE_AUX_BAR5_LIMIT 0x4C07204 + +#define mmPCIE_AUX_BUS_MASTER_EN 0x4C07208 + +#define mmPCIE_AUX_MEM_SPACE_EN 0x4C0720C + +#define mmPCIE_AUX_MAX_RD_REQ_SIZE 0x4C07210 + +#define mmPCIE_AUX_MAX_PAYLOAD_SIZE 0x4C07214 + +#define mmPCIE_AUX_EXT_TAG_EN 0x4C07218 + +#define mmPCIE_AUX_RCB 0x4C0721C + +#define mmPCIE_AUX_PM_NO_SOFT_RST 0x4C07220 + +#define mmPCIE_AUX_PBUS_NUM 0x4C07224 + +#define mmPCIE_AUX_PBUS_DEV_NUM 0x4C07228 + +#define mmPCIE_AUX_NO_SNOOP_EN 0x4C0722C + +#define mmPCIE_AUX_RELAX_ORDER_EN 0x4C07230 + +#define mmPCIE_AUX_HP_SLOT_CTRL_ACCESS 0x4C07234 + +#define mmPCIE_AUX_DLL_STATE_CHGED_EN 0x4C07238 + +#define mmPCIE_AUX_CMP_CPLED_INT_EN 0x4C0723C + +#define mmPCIE_AUX_HP_INT_EN 0x4C07340 + +#define mmPCIE_AUX_PRE_DET_CHGEN_EN 0x4C07344 + +#define mmPCIE_AUX_MRL_SENSOR_CHGED_EN 0x4C07348 + +#define mmPCIE_AUX_PWR_FAULT_DET_EN 0x4C0734C + +#define mmPCIE_AUX_ATTEN_BUTTON_PRESSED_EN 0x4C07350 + +#define mmPCIE_AUX_PF_FLR_ACTIVE 0x4C07360 + +#define mmPCIE_AUX_PF_FLR_DONE 0x4C07364 + +#define mmPCIE_AUX_FLR_INT 0x4C07390 + +#define mmPCIE_AUX_FLR_CTRL 0x4C07394 + +#define mmPCIE_AUX_LTR_M_EN 0x4C073B0 + +#define mmPCIE_AUX_LTSSM_EN 0x4C07428 + +#define mmPCIE_AUX_SYS_INTR 0x4C07440 + +#define mmPCIE_AUX_INT_DISABLE 0x4C07444 + +#define mmPCIE_AUX_SMLH_LINK_UP 0x4C07448 + +#define mmPCIE_AUX_PM_CURR_STATE 0x4C07450 + +#define mmPCIE_AUX_RDLH_LINK_UP 0x4C07458 + +#define mmPCIE_AUX_BRDG_SLV_XFER_PENDING 0x4C0745C + +#define mmPCIE_AUX_BRDG_DBI_XFER_PENDING 0x4C07460 + +#define mmPCIE_AUX_AUTO_SP_DIS 0x4C07478 + +#define mmPCIE_AUX_DBI 0x4C07490 + +#define mmPCIE_AUX_DBI_32 0x4C07494 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_0 0x4C074A4 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_1 0x4C074A8 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_2 0x4C074AC + +#define mmPCIE_AUX_DIAG_STATUS_BUS_3 0x4C074B0 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_4 0x4C074B4 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_5 0x4C074B8 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_6 0x4C074BC + +#define mmPCIE_AUX_DIAG_STATUS_BUS_7 0x4C074C0 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_8 0x4C074C4 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_9 0x4C074C8 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_10 0x4C074CC + +#define mmPCIE_AUX_DIAG_STATUS_BUS_11 0x4C074D0 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_12 0x4C074D4 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_13 0x4C074D8 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_14 0x4C074DC + +#define mmPCIE_AUX_DIAG_STATUS_BUS_15 0x4C074E0 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_16 0x4C074E4 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_17 0x4C074E8 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_18 0x4C074EC + +#define mmPCIE_AUX_DIAG_STATUS_BUS_19 0x4C074F0 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_20 0x4C074F4 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_21 0x4C074F8 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_22 0x4C074FC + +#define mmPCIE_AUX_DIAG_STATUS_BUS_23 0x4C07500 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_24 0x4C07504 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_25 0x4C07508 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_26 0x4C0750C + +#define mmPCIE_AUX_DIAG_STATUS_BUS_27 0x4C07510 + +#define mmPCIE_AUX_DIAG_STATUS_BUS_28 0x4C07514 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_0 0x4C07640 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_1 0x4C07644 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_2 0x4C07648 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_3 0x4C0764C + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_4 0x4C07650 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_5 0x4C07654 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_6 0x4C07658 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_7 0x4C0765C + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_8 0x4C07660 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_9 0x4C07664 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_10 0x4C07668 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_11 0x4C0766C + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_12 0x4C07670 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_13 0x4C07674 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_14 0x4C07678 + +#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_15 0x4C0767C + +#define mmPCIE_AUX_CDM_RAS_DES_SD_COMMON_0 0x4C07744 + +#define mmPCIE_AUX_CDM_RAS_DES_SD_COMMON_1 0x4C07748 + +#define mmPCIE_AUX_CDM_RAS_DES_SD_COMMON_2 0x4C0774C + +#define mmPCIE_AUX_APP_RAS_DES_TBA_CTRL 0x4C07774 + +#define mmPCIE_AUX_PM_MASTER_STATE 0x4C07838 + +#define mmPCIE_AUX_PM_SLAVE_STATE 0x4C0783C + +#define mmPCIE_AUX_PM_DSTATE 0x4C07840 + +#define mmPCIE_AUX_PM_PME_EN 0x4C07844 + +#define mmPCIE_AUX_PM_LINKST_IN_L0S 0x4C07848 + +#define mmPCIE_AUX_PM_LINKST_IN_L1 0x4C0784C + +#define mmPCIE_AUX_PM_LINKST_IN_L2 0x4C07850 + +#define mmPCIE_AUX_PM_LINKST_L2_EXIT 0x4C07854 + +#define mmPCIE_AUX_PM_STATUS 0x4C07858 + +#define mmPCIE_AUX_APP_READY_ENTER_L23 0x4C0785C + +#define mmPCIE_AUX_APP_XFER_PENDING 0x4C07860 + +#define mmPCIE_AUX_APP_REQ_L1 0x4C07930 + +#define mmPCIE_AUX_AUX_PM_EN 0x4C07934 + +#define mmPCIE_AUX_APPS_PM_XMT_PME 0x4C07938 + +#define mmPCIE_AUX_OUTBAND_PWRUP_CMD 0x4C07940 + +#define mmPCIE_AUX_PERST 0x4C079B8 + +#define mmPCIE_AUX_DBI_RO_WR_DISABLE 0x4C079BC + +#define mmPCIE_AUX_HOLD_PHY_RST 0x4C079C0 + +#define mmPCIE_AUX_TLP_INTERNAL_ERR_REP 0x4C079C4 + +#define mmPCIE_AUX_APP_SRIS_MODE 0x4C079C8 + +#define mmPCIE_AUX_BUS_MSTR_EN_CLR_INTR 0x4C079CC + +#define mmPCIE_AUX_BUS_MSTR_EN_CLR_INTR_MASK 0x4C079D0 + +#endif /* ASIC_REG_PCIE_AUX_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_dbi_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_dbi_regs.h new file mode 100644 index 000000000000..cc5842ec6ceb --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_dbi_regs.h @@ -0,0 +1,422 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_DBI_REGS_H_ +#define ASIC_REG_PCIE_DBI_REGS_H_ + +/* + ***************************************** + * PCIE_DBI + * (Prototype: PCIE_DBI) + ***************************************** + */ + +#define mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG 0x4C02000 + +#define mmPCIE_DBI_STATUS_COMMAND_REG 0x4C02004 + +#define mmPCIE_DBI_CLASS_CODE_REVISION_ID 0x4C02008 + +#define mmPCIE_DBI_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG 0x4C0200C + +#define mmPCIE_DBI_BAR0_REG 0x4C02010 + +#define mmPCIE_DBI_BAR1_REG 0x4C02014 + +#define mmPCIE_DBI_BAR2_REG 0x4C02018 + +#define mmPCIE_DBI_BAR3_REG 0x4C0201C + +#define mmPCIE_DBI_BAR4_REG 0x4C02020 + +#define mmPCIE_DBI_BAR5_REG 0x4C02024 + +#define mmPCIE_DBI_CARDBUS_CIS_PTR_REG 0x4C02028 + +#define mmPCIE_DBI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG 0x4C0202C + +#define mmPCIE_DBI_EXP_ROM_BASE_ADDR_REG 0x4C02030 + +#define mmPCIE_DBI_PCI_CAP_PTR_REG 0x4C02034 + +#define mmPCIE_DBI_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG \ +0x4C0203C + +#define mmPCIE_DBI_CAP_ID_NXT_PTR_REG 0x4C02040 + +#define mmPCIE_DBI_CON_STATUS_REG 0x4C02044 + +#define mmPCIE_DBI_PCI_MSI_CAP_ID_NEXT_CTRL_REG 0x4C02050 + +#define mmPCIE_DBI_MSI_CAP_OFF_04H_REG 0x4C02054 + +#define mmPCIE_DBI_MSI_CAP_OFF_08H_REG 0x4C02058 + +#define mmPCIE_DBI_MSI_CAP_OFF_0CH_REG 0x4C0205C + +#define mmPCIE_DBI_MSI_CAP_OFF_10H_REG 0x4C02060 + +#define mmPCIE_DBI_MSI_CAP_OFF_14H_REG 0x4C02064 + +#define mmPCIE_DBI_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG 0x4C02070 + +#define mmPCIE_DBI_DEVICE_CAPABILITIES_REG 0x4C02074 + +#define mmPCIE_DBI_DEVICE_CONTROL_DEVICE_STATUS 0x4C02078 + +#define mmPCIE_DBI_LINK_CAPABILITIES_REG 0x4C0207C + +#define mmPCIE_DBI_LINK_CONTROL_LINK_STATUS_REG 0x4C02080 + +#define mmPCIE_DBI_DEVICE_CAPABILITIES2_REG 0x4C02094 + +#define mmPCIE_DBI_DEVICE_CONTROL2_DEVICE_STATUS2_REG 0x4C02098 + +#define mmPCIE_DBI_LINK_CAPABILITIES2_REG 0x4C0209C + +#define mmPCIE_DBI_LINK_CONTROL2_LINK_STATUS2_REG 0x4C020A0 + +#define mmPCIE_DBI_PCI_MSIX_CAP_ID_NEXT_CTRL_REG 0x4C020B0 + +#define mmPCIE_DBI_MSIX_TABLE_OFFSET_REG 0x4C020B4 + +#define mmPCIE_DBI_MSIX_PBA_OFFSET_REG 0x4C020B8 + +#define mmPCIE_DBI_AER_EXT_CAP_HDR_OFF 0x4C02100 + +#define mmPCIE_DBI_UNCORR_ERR_STATUS_OFF 0x4C02104 + +#define mmPCIE_DBI_UNCORR_ERR_MASK_OFF 0x4C02108 + +#define mmPCIE_DBI_UNCORR_ERR_SEV_OFF 0x4C0210C + +#define mmPCIE_DBI_CORR_ERR_STATUS_OFF 0x4C02110 + +#define mmPCIE_DBI_CORR_ERR_MASK_OFF 0x4C02114 + +#define mmPCIE_DBI_ADV_ERR_CAP_CTRL_OFF 0x4C02118 + +#define mmPCIE_DBI_HDR_LOG_0_OFF 0x4C0211C + +#define mmPCIE_DBI_HDR_LOG_1_OFF 0x4C02120 + +#define mmPCIE_DBI_HDR_LOG_2_OFF 0x4C02124 + +#define mmPCIE_DBI_HDR_LOG_3_OFF 0x4C02128 + +#define mmPCIE_DBI_TLP_PREFIX_LOG_1_OFF 0x4C02138 + +#define mmPCIE_DBI_TLP_PREFIX_LOG_2_OFF 0x4C0213C + +#define mmPCIE_DBI_TLP_PREFIX_LOG_3_OFF 0x4C02140 + +#define mmPCIE_DBI_TLP_PREFIX_LOG_4_OFF 0x4C02144 + +#define mmPCIE_DBI_SPCIE_CAP_HEADER_REG 0x4C02148 + +#define mmPCIE_DBI_LINK_CONTROL3_REG 0x4C0214C + +#define mmPCIE_DBI_LANE_ERR_STATUS_REG 0x4C02150 + +#define mmPCIE_DBI_SPCIE_CAP_OFF_0CH_REG 0x4C02154 + +#define mmPCIE_DBI_SPCIE_CAP_OFF_10H_REG 0x4C02158 + +#define mmPCIE_DBI_SPCIE_CAP_OFF_14H_REG 0x4C0215C + +#define mmPCIE_DBI_SPCIE_CAP_OFF_18H_REG 0x4C02160 + +#define mmPCIE_DBI_SPCIE_CAP_OFF_1CH_REG 0x4C02164 + +#define mmPCIE_DBI_SPCIE_CAP_OFF_20H_REG 0x4C02168 + +#define mmPCIE_DBI_SPCIE_CAP_OFF_24H_REG 0x4C0216C + +#define mmPCIE_DBI_SPCIE_CAP_OFF_28H_REG 0x4C02170 + +#define mmPCIE_DBI_PL16G_EXT_CAP_HDR_REG 0x4C02178 + +#define mmPCIE_DBI_PL16G_CAPABILITY_REG 0x4C0217C + +#define mmPCIE_DBI_PL16G_CONTROL_REG 0x4C02180 + +#define mmPCIE_DBI_PL16G_STATUS_REG 0x4C02184 + +#define mmPCIE_DBI_PL16G_LC_DPAR_STATUS_REG 0x4C02188 + +#define mmPCIE_DBI_PL16G_FIRST_RETIMER_DPAR_STATUS_REG 0x4C0218C + +#define mmPCIE_DBI_PL16G_SECOND_RETIMER_DPAR_STATUS_REG 0x4C02190 + +#define mmPCIE_DBI_PL16G_CAP_OFF_20H_REG 0x4C02198 + +#define mmPCIE_DBI_PL16G_CAP_OFF_24H_REG 0x4C0219C + +#define mmPCIE_DBI_PL16G_CAP_OFF_28H_REG 0x4C021A0 + +#define mmPCIE_DBI_PL16G_CAP_OFF_2CH_REG 0x4C021A4 + +#define mmPCIE_DBI_MARGIN_EXT_CAP_HDR_REG 0x4C021A8 + +#define mmPCIE_DBI_MARGIN_PORT_CAPABILITIES_STATUS_REG 0x4C021AC + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS0_REG 0x4C021B0 + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS1_REG 0x4C021B4 + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS2_REG 0x4C021B8 + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS3_REG 0x4C021BC + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS4_REG 0x4C021C0 + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS5_REG 0x4C021C4 + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS6_REG 0x4C021C8 + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS7_REG 0x4C021CC + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS8_REG 0x4C021D0 + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS9_REG 0x4C021D4 + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS10_REG 0x4C021D8 + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS11_REG 0x4C021DC + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS12_REG 0x4C021E0 + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS13_REG 0x4C021E4 + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS14_REG 0x4C021E8 + +#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS15_REG 0x4C021EC + +#define mmPCIE_DBI_LTR_CAP_HDR_REG 0x4C021F0 + +#define mmPCIE_DBI_LTR_LATENCY_REG 0x4C021F4 + +#define mmPCIE_DBI_RAS_DES_CAP_HEADER_REG 0x4C021F8 + +#define mmPCIE_DBI_VENDOR_SPECIFIC_HEADER_REG 0x4C021FC + +#define mmPCIE_DBI_EVENT_COUNTER_CONTROL_REG 0x4C02200 + +#define mmPCIE_DBI_EVENT_COUNTER_DATA_REG 0x4C02204 + +#define mmPCIE_DBI_TIME_BASED_ANALYSIS_CONTROL_REG 0x4C02208 + +#define mmPCIE_DBI_TIME_BASED_ANALYSIS_DATA_REG 0x4C0220C + +#define mmPCIE_DBI_TIME_BASED_ANALYSIS_DATA_63_32_REG 0x4C02210 + +#define mmPCIE_DBI_EINJ_ENABLE_REG 0x4C02228 + +#define mmPCIE_DBI_EINJ0_CRC_REG 0x4C0222C + +#define mmPCIE_DBI_EINJ1_SEQNUM_REG 0x4C02230 + +#define mmPCIE_DBI_EINJ2_DLLP_REG 0x4C02234 + +#define mmPCIE_DBI_EINJ3_SYMBOL_REG 0x4C02238 + +#define mmPCIE_DBI_EINJ4_FC_REG 0x4C0223C + +#define mmPCIE_DBI_EINJ5_SP_TLP_REG 0x4C02240 + +#define mmPCIE_DBI_EINJ6_COMPARE_POINT_H0_REG 0x4C02244 + +#define mmPCIE_DBI_EINJ6_COMPARE_POINT_H1_REG 0x4C02248 + +#define mmPCIE_DBI_EINJ6_COMPARE_POINT_H2_REG 0x4C0224C + +#define mmPCIE_DBI_EINJ6_COMPARE_POINT_H3_REG 0x4C02250 + +#define mmPCIE_DBI_EINJ6_COMPARE_VALUE_H0_REG 0x4C02254 + +#define mmPCIE_DBI_EINJ6_COMPARE_VALUE_H1_REG 0x4C02258 + +#define mmPCIE_DBI_EINJ6_COMPARE_VALUE_H2_REG 0x4C0225C + +#define mmPCIE_DBI_EINJ6_COMPARE_VALUE_H3_REG 0x4C02260 + +#define mmPCIE_DBI_EINJ6_CHANGE_POINT_H0_REG 0x4C02264 + +#define mmPCIE_DBI_EINJ6_CHANGE_POINT_H1_REG 0x4C02268 + +#define mmPCIE_DBI_EINJ6_CHANGE_POINT_H2_REG 0x4C0226C + +#define mmPCIE_DBI_EINJ6_CHANGE_POINT_H3_REG 0x4C02270 + +#define mmPCIE_DBI_EINJ6_CHANGE_VALUE_H0_REG 0x4C02274 + +#define mmPCIE_DBI_EINJ6_CHANGE_VALUE_H1_REG 0x4C02278 + +#define mmPCIE_DBI_EINJ6_CHANGE_VALUE_H2_REG 0x4C0227C + +#define mmPCIE_DBI_EINJ6_CHANGE_VALUE_H3_REG 0x4C02280 + +#define mmPCIE_DBI_EINJ6_TLP_REG 0x4C02284 + +#define mmPCIE_DBI_SD_CONTROL1_REG 0x4C02298 + +#define mmPCIE_DBI_SD_CONTROL2_REG 0x4C0229C + +#define mmPCIE_DBI_SD_STATUS_L1LANE_REG 0x4C022A8 + +#define mmPCIE_DBI_SD_STATUS_L1LTSSM_REG 0x4C022AC + +#define mmPCIE_DBI_SD_STATUS_PM_REG 0x4C022B0 + +#define mmPCIE_DBI_SD_STATUS_L2_REG 0x4C022B4 + +#define mmPCIE_DBI_SD_STATUS_L3FC_REG 0x4C022B8 + +#define mmPCIE_DBI_SD_STATUS_L3_REG 0x4C022BC + +#define mmPCIE_DBI_SD_EQ_CONTROL1_REG 0x4C022C8 + +#define mmPCIE_DBI_SD_EQ_CONTROL2_REG 0x4C022CC + +#define mmPCIE_DBI_SD_EQ_CONTROL3_REG 0x4C022D0 + +#define mmPCIE_DBI_SD_EQ_STATUS1_REG 0x4C022D8 + +#define mmPCIE_DBI_SD_EQ_STATUS2_REG 0x4C022DC + +#define mmPCIE_DBI_SD_EQ_STATUS3_REG 0x4C022E0 + +#define mmPCIE_DBI_DATA_LINK_FEATURE_EXT_HDR_OFF 0x4C022F8 + +#define mmPCIE_DBI_DATA_LINK_FEATURE_CAP_OFF 0x4C022FC + +#define mmPCIE_DBI_DATA_LINK_FEATURE_STATUS_OFF 0x4C02300 + +#define mmPCIE_DBI_ACK_LATENCY_TIMER_OFF 0x4C02700 + +#define mmPCIE_DBI_VENDOR_SPEC_DLLP_OFF 0x4C02704 + +#define mmPCIE_DBI_PORT_FORCE_OFF 0x4C02708 + +#define mmPCIE_DBI_ACK_F_ASPM_CTRL_OFF 0x4C0270C + +#define mmPCIE_DBI_PORT_LINK_CTRL_OFF 0x4C02710 + +#define mmPCIE_DBI_LANE_SKEW_OFF 0x4C02714 + +#define mmPCIE_DBI_TIMER_CTRL_MAX_FUNC_NUM_OFF 0x4C02718 + +#define mmPCIE_DBI_SYMBOL_TIMER_FILTER_1_OFF 0x4C0271C + +#define mmPCIE_DBI_FILTER_MASK_2_OFF 0x4C02720 + +#define mmPCIE_DBI_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF 0x4C02724 + +#define mmPCIE_DBI_PL_DEBUG0_OFF 0x4C02728 + +#define mmPCIE_DBI_PL_DEBUG1_OFF 0x4C0272C + +#define mmPCIE_DBI_TX_P_FC_CREDIT_STATUS_OFF 0x4C02730 + +#define mmPCIE_DBI_TX_NP_FC_CREDIT_STATUS_OFF 0x4C02734 + +#define mmPCIE_DBI_TX_CPL_FC_CREDIT_STATUS_OFF 0x4C02738 + +#define mmPCIE_DBI_QUEUE_STATUS_OFF 0x4C0273C + +#define mmPCIE_DBI_VC_TX_ARBI_1_OFF 0x4C02740 + +#define mmPCIE_DBI_VC_TX_ARBI_2_OFF 0x4C02744 + +#define mmPCIE_DBI_VC0_P_RX_Q_CTRL_OFF 0x4C02748 + +#define mmPCIE_DBI_VC0_NP_RX_Q_CTRL_OFF 0x4C0274C + +#define mmPCIE_DBI_VC0_CPL_RX_Q_CTRL_OFF 0x4C02750 + +#define mmPCIE_DBI_GEN2_CTRL_OFF 0x4C0280C + +#define mmPCIE_DBI_PHY_STATUS_OFF 0x4C02810 + +#define mmPCIE_DBI_PHY_CONTROL_OFF 0x4C02814 + +#define mmPCIE_DBI_TRGT_MAP_CTRL_OFF 0x4C0281C + +#define mmPCIE_DBI_CLOCK_GATING_CTRL_OFF 0x4C0288C + +#define mmPCIE_DBI_GEN3_RELATED_OFF 0x4C02890 + +#define mmPCIE_DBI_GEN3_EQ_CONTROL_OFF 0x4C028A8 + +#define mmPCIE_DBI_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF 0x4C028AC + +#define mmPCIE_DBI_ORDER_RULE_CTRL_OFF 0x4C028B4 + +#define mmPCIE_DBI_PIPE_LOOPBACK_CONTROL_OFF 0x4C028B8 + +#define mmPCIE_DBI_MISC_CONTROL_1_OFF 0x4C028BC + +#define mmPCIE_DBI_MULTI_LANE_CONTROL_OFF 0x4C028C0 + +#define mmPCIE_DBI_PHY_INTEROP_CTRL_OFF 0x4C028C4 + +#define mmPCIE_DBI_TRGT_CPL_LUT_DELETE_ENTRY_OFF 0x4C028C8 + +#define mmPCIE_DBI_LINK_FLUSH_CONTROL_OFF 0x4C028CC + +#define mmPCIE_DBI_AMBA_ERROR_RESPONSE_DEFAULT_OFF 0x4C028D0 + +#define mmPCIE_DBI_AMBA_LINK_TIMEOUT_OFF 0x4C028D4 + +#define mmPCIE_DBI_AMBA_ORDERING_CTRL_OFF 0x4C028D8 + +#define mmPCIE_DBI_COHERENCY_CONTROL_1_OFF 0x4C028E0 + +#define mmPCIE_DBI_COHERENCY_CONTROL_2_OFF 0x4C028E4 + +#define mmPCIE_DBI_COHERENCY_CONTROL_3_OFF 0x4C028E8 + +#define mmPCIE_DBI_AXI_MSTR_MSG_ADDR_LOW_OFF 0x4C028F0 + +#define mmPCIE_DBI_AXI_MSTR_MSG_ADDR_HIGH_OFF 0x4C028F4 + +#define mmPCIE_DBI_PCIE_VERSION_NUMBER_OFF 0x4C028F8 + +#define mmPCIE_DBI_PCIE_VERSION_TYPE_OFF 0x4C028FC + +#define mmPCIE_DBI_MSIX_ADDRESS_MATCH_LOW_OFF 0x4C02940 + +#define mmPCIE_DBI_MSIX_ADDRESS_MATCH_HIGH_OFF 0x4C02944 + +#define mmPCIE_DBI_MSIX_DOORBELL_OFF 0x4C02948 + +#define mmPCIE_DBI_MSIX_RAM_CTRL_OFF 0x4C0294C + +#define mmPCIE_DBI_PL_LTR_LATENCY_OFF 0x4C02B30 + +#define mmPCIE_DBI_AUX_CLK_FREQ_OFF 0x4C02B40 + +#define mmPCIE_DBI_POWERDOWN_CTRL_STATUS_OFF 0x4C02B48 + +#define mmPCIE_DBI_PHY_VIEWPORT_CTLSTS_OFF 0x4C02B70 + +#define mmPCIE_DBI_PHY_VIEWPORT_DATA_OFF 0x4C02B74 + +#define mmPCIE_DBI_GEN4_LANE_MARGINING_1_OFF 0x4C02B80 + +#define mmPCIE_DBI_GEN4_LANE_MARGINING_2_OFF 0x4C02B84 + +#define mmPCIE_DBI_PIPE_RELATED_OFF 0x4C02B90 + +#define mmPCIE_DBI_RX_SERIALIZATION_Q_CTRL_OFF 0x4C02C00 + +#endif /* ASIC_REG_PCIE_DBI_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_dec0_cmd_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_dec0_cmd_masks.h new file mode 100644 index 000000000000..2b5af010c7a5 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_dec0_cmd_masks.h @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_DEC0_CMD_MASKS_H_ +#define ASIC_REG_PCIE_DEC0_CMD_MASKS_H_ + +/* + ***************************************** + * PCIE_DEC0_CMD + * (Prototype: VSI_CMD) + ***************************************** + */ + +/* PCIE_DEC0_CMD_SWREG0 */ +#define PCIE_DEC0_CMD_SWREG0_SW_HW_VERSION_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG0_SW_HW_VERSION_MASK 0xFFFF +#define PCIE_DEC0_CMD_SWREG0_SW_HW_ID_SHIFT 16 +#define PCIE_DEC0_CMD_SWREG0_SW_HW_ID_MASK 0xFFFF0000 + +/* PCIE_DEC0_CMD_SWREG1 */ +#define PCIE_DEC0_CMD_SWREG1_SW_HW_BUILDDATE_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG1_SW_HW_BUILDDATE_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG2 */ +#define PCIE_DEC0_CMD_SWREG2_SW_EXT_NORM_INTR_SRC_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG2_SW_EXT_NORM_INTR_SRC_MASK 0xFFFF +#define PCIE_DEC0_CMD_SWREG2_SW_EXT_ABN_INTR_SRC_SHIFT 16 +#define PCIE_DEC0_CMD_SWREG2_SW_EXT_ABN_INTR_SRC_MASK 0xFFFF0000 + +/* PCIE_DEC0_CMD_SWREG3 */ +#define PCIE_DEC0_CMD_SWREG3_SW_EXE_CMDBUF_COUNT_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG3_SW_EXE_CMDBUF_COUNT_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG4 */ +#define PCIE_DEC0_CMD_SWREG4_SW_CMD_EXE_LSB_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG4_SW_CMD_EXE_LSB_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG5 */ +#define PCIE_DEC0_CMD_SWREG5_SW_CMD_EXE_MSB_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG5_SW_CMD_EXE_MSB_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG6 */ +#define PCIE_DEC0_CMD_SWREG6_SW_AXI_TOTALARLEN_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG6_SW_AXI_TOTALARLEN_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG7 */ +#define PCIE_DEC0_CMD_SWREG7_SW_AXI_TOTALR_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG7_SW_AXI_TOTALR_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG8 */ +#define PCIE_DEC0_CMD_SWREG8_SW_AXI_TOTALAR_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG8_SW_AXI_TOTALAR_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG9 */ +#define PCIE_DEC0_CMD_SWREG9_SW_AXI_TOTALRLAST_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG9_SW_AXI_TOTALRLAST_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG10 */ +#define PCIE_DEC0_CMD_SWREG10_SW_AXI_TOTALAWLEN_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG10_SW_AXI_TOTALAWLEN_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG11 */ +#define PCIE_DEC0_CMD_SWREG11_SW_AXI_TOTALW_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG11_SW_AXI_TOTALW_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG12 */ +#define PCIE_DEC0_CMD_SWREG12_SW_AXI_TOTALAW_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG12_SW_AXI_TOTALAW_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG13 */ +#define PCIE_DEC0_CMD_SWREG13_SW_AXI_TOTALWLAST_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG13_SW_AXI_TOTALWLAST_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG14 */ +#define PCIE_DEC0_CMD_SWREG14_SW_AXI_TOTALB_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG14_SW_AXI_TOTALB_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG15 */ +#define PCIE_DEC0_CMD_SWREG15_SW_WORK_STATE_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG15_SW_WORK_STATE_MASK 0x7 +#define PCIE_DEC0_CMD_SWREG15_RSV_SHIFT 3 +#define PCIE_DEC0_CMD_SWREG15_RSV_MASK 0x3FFFF8 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_BREADY_SHIFT 22 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_BREADY_MASK 0x400000 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_BVALID_SHIFT 23 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_BVALID_MASK 0x800000 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_WREADY_SHIFT 24 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_WREADY_MASK 0x1000000 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_WVALID_SHIFT 25 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_WVALID_MASK 0x2000000 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_AWREADY_SHIFT 26 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_AWREADY_MASK 0x4000000 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_AWVALID_SHIFT 27 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_AWVALID_MASK 0x8000000 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_RREADY_SHIFT 28 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_RREADY_MASK 0x10000000 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_RVALID_SHIFT 29 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_RVALID_MASK 0x20000000 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_ARREADY_SHIFT 30 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_ARREADY_MASK 0x40000000 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_ARVALID_SHIFT 31 +#define PCIE_DEC0_CMD_SWREG15_SW_AXI_ARVALID_MASK 0x80000000 + +/* PCIE_DEC0_CMD_SWREG16 */ +#define PCIE_DEC0_CMD_SWREG16_SW_START_TRIGGER_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG16_SW_START_TRIGGER_MASK 0x1 +#define PCIE_DEC0_CMD_SWREG16_SW_RESET_ALL_SHIFT 1 +#define PCIE_DEC0_CMD_SWREG16_SW_RESET_ALL_MASK 0x2 +#define PCIE_DEC0_CMD_SWREG16_SW_RESET_CORE_SHIFT 2 +#define PCIE_DEC0_CMD_SWREG16_SW_RESET_CORE_MASK 0x4 +#define PCIE_DEC0_CMD_SWREG16_SW_ABORT_MODE_SHIFT 3 +#define PCIE_DEC0_CMD_SWREG16_SW_ABORT_MODE_MASK 0x8 +#define PCIE_DEC0_CMD_SWREG16_SW_CORE_CLK_GATE_DISABLE_SHIFT 4 +#define PCIE_DEC0_CMD_SWREG16_SW_CORE_CLK_GATE_DISABLE_MASK 0x10 +#define PCIE_DEC0_CMD_SWREG16_SW_MASTER_OUT_CLK_GATE_DISABLE_SHIFT 5 +#define PCIE_DEC0_CMD_SWREG16_SW_MASTER_OUT_CLK_GATE_DISABLE_MASK 0x20 +#define PCIE_DEC0_CMD_SWREG16_SW_AXI_CLK_GATE_DISABLE_SHIFT 6 +#define PCIE_DEC0_CMD_SWREG16_SW_AXI_CLK_GATE_DISABLE_MASK 0x40 +#define PCIE_DEC0_CMD_SWREG16_RSV_SHIFT 7 +#define PCIE_DEC0_CMD_SWREG16_RSV_MASK 0xFFFFFF80 + +/* PCIE_DEC0_CMD_SWREG17 */ +#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_ENDCMD_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_ENDCMD_MASK 0x1 +#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_BUSERR_SHIFT 1 +#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_BUSERR_MASK 0x2 +#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_TIMEOUT_SHIFT 2 +#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_TIMEOUT_MASK 0x4 +#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_CMDERR_SHIFT 3 +#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_CMDERR_MASK 0x8 +#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_ABORT_SHIFT 4 +#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_ABORT_MASK 0x10 +#define PCIE_DEC0_CMD_SWREG17_RSV_1_SHIFT 5 +#define PCIE_DEC0_CMD_SWREG17_RSV_1_MASK 0x20 +#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_JMP_SHIFT 6 +#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_JMP_MASK 0x40 +#define PCIE_DEC0_CMD_SWREG17_RSV_SHIFT 7 +#define PCIE_DEC0_CMD_SWREG17_RSV_MASK 0xFFFFFF80 + +/* PCIE_DEC0_CMD_SWREG18 */ +#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_ENDCMD_EN_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_ENDCMD_EN_MASK 0x1 +#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_BUSERR_EN_SHIFT 1 +#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_BUSERR_EN_MASK 0x2 +#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_TIMEOUT_EN_SHIFT 2 +#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_TIMEOUT_EN_MASK 0x4 +#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_CMDERR_EN_SHIFT 3 +#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_CMDERR_EN_MASK 0x8 +#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_ABORT_EN_SHIFT 4 +#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_ABORT_EN_MASK 0x10 +#define PCIE_DEC0_CMD_SWREG18_RSV_1_SHIFT 5 +#define PCIE_DEC0_CMD_SWREG18_RSV_1_MASK 0x20 +#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_JMP_EN_SHIFT 6 +#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_JMP_EN_MASK 0x40 +#define PCIE_DEC0_CMD_SWREG18_RSV_SHIFT 7 +#define PCIE_DEC0_CMD_SWREG18_RSV_MASK 0xFFFFFF80 + +/* PCIE_DEC0_CMD_SWREG19 */ +#define PCIE_DEC0_CMD_SWREG19_SW_TIMEOUT_CYCLES_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG19_SW_TIMEOUT_CYCLES_MASK 0x7FFFFFFF +#define PCIE_DEC0_CMD_SWREG19_SW_TIMEOUT_ENABLE_SHIFT 31 +#define PCIE_DEC0_CMD_SWREG19_SW_TIMEOUT_ENABLE_MASK 0x80000000 + +/* PCIE_DEC0_CMD_SWREG20 */ +#define PCIE_DEC0_CMD_SWREG20_SW_CMDBUF_EXE_ADDR_LSB_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG20_SW_CMDBUF_EXE_ADDR_LSB_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG21 */ +#define PCIE_DEC0_CMD_SWREG21_SW_CMDBUF_EXE_ADDR_MSB_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG21_SW_CMDBUF_EXE_ADDR_MSB_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG22 */ +#define PCIE_DEC0_CMD_SWREG22_SW_CMDBUF_EXE_LENGTH_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG22_SW_CMDBUF_EXE_LENGTH_MASK 0xFFFF +#define PCIE_DEC0_CMD_SWREG22_RSV_SHIFT 16 +#define PCIE_DEC0_CMD_SWREG22_RSV_MASK 0xFFFF0000 + +/* PCIE_DEC0_CMD_SWREG23 */ +#define PCIE_DEC0_CMD_SWREG23_SW_AXI_ID_WR_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG23_SW_AXI_ID_WR_MASK 0xFF +#define PCIE_DEC0_CMD_SWREG23_SW_AXI_ID_RD_SHIFT 8 +#define PCIE_DEC0_CMD_SWREG23_SW_AXI_ID_RD_MASK 0xFF00 +#define PCIE_DEC0_CMD_SWREG23_SW_MAX_BURST_LEN_SHIFT 16 +#define PCIE_DEC0_CMD_SWREG23_SW_MAX_BURST_LEN_MASK 0xFF0000 +#define PCIE_DEC0_CMD_SWREG23_RSV_SHIFT 24 +#define PCIE_DEC0_CMD_SWREG23_RSV_MASK 0xF000000 +#define PCIE_DEC0_CMD_SWREG23_SW_CMD_SWAP_SHIFT 28 +#define PCIE_DEC0_CMD_SWREG23_SW_CMD_SWAP_MASK 0xF0000000 + +/* PCIE_DEC0_CMD_SWREG24 */ +#define PCIE_DEC0_CMD_SWREG24_SW_RDY_CMDBUF_COUNT_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG24_SW_RDY_CMDBUF_COUNT_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG25 */ +#define PCIE_DEC0_CMD_SWREG25_SW_EXT_NORM_INTR_GATE_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG25_SW_EXT_NORM_INTR_GATE_MASK 0xFFFF +#define PCIE_DEC0_CMD_SWREG25_SW_EXT_ABN_INTR_GATE_SHIFT 16 +#define PCIE_DEC0_CMD_SWREG25_SW_EXT_ABN_INTR_GATE_MASK 0xFFFF0000 + +/* PCIE_DEC0_CMD_SWREG26 */ +#define PCIE_DEC0_CMD_SWREG26_SW_CMDBUF_EXE_ID_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG26_SW_CMDBUF_EXE_ID_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG64 */ +#define PCIE_DEC0_CMD_SWREG64_SW_DUMMY0_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG64_SW_DUMMY0_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG65 */ +#define PCIE_DEC0_CMD_SWREG65_SW_DUMMY1_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG65_SW_DUMMY1_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG66 */ +#define PCIE_DEC0_CMD_SWREG66_SW_DUMMY2_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG66_SW_DUMMY2_MASK 0xFFFFFFFF + +/* PCIE_DEC0_CMD_SWREG67 */ +#define PCIE_DEC0_CMD_SWREG67_SW_DUMMY3_SHIFT 0 +#define PCIE_DEC0_CMD_SWREG67_SW_DUMMY3_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_PCIE_DEC0_CMD_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_dec0_cmd_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_dec0_cmd_regs.h new file mode 100644 index 000000000000..dc7d3f6a4b50 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_dec0_cmd_regs.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_DEC0_CMD_REGS_H_ +#define ASIC_REG_PCIE_DEC0_CMD_REGS_H_ + +/* + ***************************************** + * PCIE_DEC0_CMD + * (Prototype: VSI_CMD) + ***************************************** + */ + +#define mmPCIE_DEC0_CMD_SWREG0 0x4F00000 + +#define mmPCIE_DEC0_CMD_SWREG1 0x4F00004 + +#define mmPCIE_DEC0_CMD_SWREG2 0x4F00008 + +#define mmPCIE_DEC0_CMD_SWREG3 0x4F0000C + +#define mmPCIE_DEC0_CMD_SWREG4 0x4F00010 + +#define mmPCIE_DEC0_CMD_SWREG5 0x4F00014 + +#define mmPCIE_DEC0_CMD_SWREG6 0x4F00018 + +#define mmPCIE_DEC0_CMD_SWREG7 0x4F0001C + +#define mmPCIE_DEC0_CMD_SWREG8 0x4F00020 + +#define mmPCIE_DEC0_CMD_SWREG9 0x4F00024 + +#define mmPCIE_DEC0_CMD_SWREG10 0x4F00028 + +#define mmPCIE_DEC0_CMD_SWREG11 0x4F0002C + +#define mmPCIE_DEC0_CMD_SWREG12 0x4F00030 + +#define mmPCIE_DEC0_CMD_SWREG13 0x4F00034 + +#define mmPCIE_DEC0_CMD_SWREG14 0x4F00038 + +#define mmPCIE_DEC0_CMD_SWREG15 0x4F0003C + +#define mmPCIE_DEC0_CMD_SWREG16 0x4F00040 + +#define mmPCIE_DEC0_CMD_SWREG17 0x4F00044 + +#define mmPCIE_DEC0_CMD_SWREG18 0x4F00048 + +#define mmPCIE_DEC0_CMD_SWREG19 0x4F0004C + +#define mmPCIE_DEC0_CMD_SWREG20 0x4F00050 + +#define mmPCIE_DEC0_CMD_SWREG21 0x4F00054 + +#define mmPCIE_DEC0_CMD_SWREG22 0x4F00058 + +#define mmPCIE_DEC0_CMD_SWREG23 0x4F0005C + +#define mmPCIE_DEC0_CMD_SWREG24 0x4F00060 + +#define mmPCIE_DEC0_CMD_SWREG25 0x4F00064 + +#define mmPCIE_DEC0_CMD_SWREG26 0x4F00068 + +#define mmPCIE_DEC0_CMD_SWREG64 0x4F00100 + +#define mmPCIE_DEC0_CMD_SWREG65 0x4F00104 + +#define mmPCIE_DEC0_CMD_SWREG66 0x4F00108 + +#define mmPCIE_DEC0_CMD_SWREG67 0x4F0010C + +#endif /* ASIC_REG_PCIE_DEC0_CMD_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_dec_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_dec_regs.h new file mode 100644 index 000000000000..242c6525bd71 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_dec_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_REGS_H_ +#define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_REGS_H_ + +/* + ***************************************** + * PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_ASID 0x4F03C00 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_MMU_BP 0x4F03C04 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_STRONG_ORDER 0x4F03C08 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_NO_SNOOP 0x4F03C0C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_WR_REDUCTION 0x4F03C10 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RD_ATOMIC 0x4F03C14 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_QOS 0x4F03C18 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RSVD 0x4F03C1C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_EMEM_CPAGE 0x4F03C20 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_CORE 0x4F03C24 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_E2E_COORD 0x4F03C28 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_WR_OVRD_LO 0x4F03C30 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_WR_OVRD_HI 0x4F03C34 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RD_OVRD_LO 0x4F03C38 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RD_OVRD_HI 0x4F03C3C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_COORD 0x4F03C40 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_LOCK 0x4F03C44 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_RSVD 0x4F03C48 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_OVRD 0x4F03C4C + +#endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h new file mode 100644 index 000000000000..98d035463561 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_REGS_H_ +#define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_REGS_H_ + +/* + ***************************************** + * PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_ASID 0x4F03B00 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_MMU_BP 0x4F03B04 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_STRONG_ORDER 0x4F03B08 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_NO_SNOOP 0x4F03B0C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_WR_REDUCTION 0x4F03B10 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_RD_ATOMIC 0x4F03B14 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_QOS 0x4F03B18 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_RSVD 0x4F03B1C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_EMEM_CPAGE 0x4F03B20 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_CORE 0x4F03B24 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_E2E_COORD 0x4F03B28 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_WR_OVRD_LO 0x4F03B30 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_WR_OVRD_HI 0x4F03B34 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_RD_OVRD_LO 0x4F03B38 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_RD_OVRD_HI 0x4F03B3C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_LB_COORD 0x4F03B40 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_LB_LOCK 0x4F03B44 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_LB_RSVD 0x4F03B48 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_LB_OVRD 0x4F03B4C + +#endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h new file mode 100644 index 000000000000..33ef37619417 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_REGS_H_ +#define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_REGS_H_ + +/* + ***************************************** + * PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_ASID 0x4F03900 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_MMU_BP 0x4F03904 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_STRONG_ORDER 0x4F03908 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_NO_SNOOP 0x4F0390C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_WR_REDUCTION 0x4F03910 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_RD_ATOMIC 0x4F03914 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_QOS 0x4F03918 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_RSVD 0x4F0391C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_EMEM_CPAGE 0x4F03920 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_CORE 0x4F03924 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_E2E_COORD 0x4F03928 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_WR_OVRD_LO 0x4F03930 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_WR_OVRD_HI 0x4F03934 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_RD_OVRD_LO 0x4F03938 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_RD_OVRD_HI 0x4F0393C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_LB_COORD 0x4F03940 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_LB_LOCK 0x4F03944 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_LB_RSVD 0x4F03948 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_LB_OVRD 0x4F0394C + +#endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h new file mode 100644 index 000000000000..c4587d5d6406 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_REGS_H_ +#define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_REGS_H_ + +/* + ***************************************** + * PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_ASID 0x4F03A00 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_MMU_BP 0x4F03A04 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_STRONG_ORDER 0x4F03A08 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_NO_SNOOP 0x4F03A0C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_WR_REDUCTION 0x4F03A10 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_RD_ATOMIC 0x4F03A14 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_QOS 0x4F03A18 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_RSVD 0x4F03A1C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_EMEM_CPAGE 0x4F03A20 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_CORE 0x4F03A24 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_E2E_COORD 0x4F03A28 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_WR_OVRD_LO 0x4F03A30 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_WR_OVRD_HI 0x4F03A34 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_RD_OVRD_LO 0x4F03A38 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_RD_OVRD_HI 0x4F03A3C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_LB_COORD 0x4F03A40 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_LB_LOCK 0x4F03A44 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_LB_RSVD 0x4F03A48 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_LB_OVRD 0x4F03A4C + +#endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h new file mode 100644 index 000000000000..35349ad375d0 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_REGS_H_ +#define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_REGS_H_ + +/* + ***************************************** + * PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_ASID 0x4F03800 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_MMU_BP 0x4F03804 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_STRONG_ORDER 0x4F03808 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_NO_SNOOP 0x4F0380C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_WR_REDUCTION 0x4F03810 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RD_ATOMIC 0x4F03814 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_QOS 0x4F03818 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RSVD 0x4F0381C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_EMEM_CPAGE 0x4F03820 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_CORE 0x4F03824 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_E2E_COORD 0x4F03828 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_WR_OVRD_LO 0x4F03830 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_WR_OVRD_HI 0x4F03834 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RD_OVRD_LO 0x4F03838 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RD_OVRD_HI 0x4F0383C + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_COORD 0x4F03840 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_LOCK 0x4F03844 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_RSVD 0x4F03848 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_OVRD 0x4F0384C + +#endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_masks.h new file mode 100644 index 000000000000..d29837883216 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_masks.h @@ -0,0 +1,580 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_MASKS_H_ +#define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_MASKS_H_ + +/* + ***************************************** + * PCIE_VDEC0_BRDG_CTRL + * (Prototype: VDEC_BRDG_CTRL) + ***************************************** + */ + +/* PCIE_VDEC0_BRDG_CTRL_CGM_DISABLE */ +#define PCIE_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_MASK 0x1 + +/* PCIE_VDEC0_BRDG_CTRL_IDLE_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_APB_CGM_CNT */ +#define PCIE_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_MASK 0xFFFF + +/* PCIE_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT */ +#define PCIE_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_MASK 0xFFFF + +/* PCIE_VDEC0_BRDG_CTRL_GRACEFUL */ +#define PCIE_VDEC0_BRDG_CTRL_GRACEFUL_STOP_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK 0x1 +#define PCIE_VDEC0_BRDG_CTRL_GRACEFUL_PEND_SHIFT 4 +#define PCIE_VDEC0_BRDG_CTRL_GRACEFUL_PEND_MASK 0x10 + +/* PCIE_VDEC0_BRDG_CTRL_IDLE_CGM_CNT */ +#define PCIE_VDEC0_BRDG_CTRL_IDLE_CGM_CNT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_IDLE_CGM_CNT_VAL_MASK 0xFFFF + +/* PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR */ +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_HBW_SEI_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_HBW_SEI_MASK 0x1 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_HBW_SEI_SHIFT 1 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_HBW_SEI_MASK 0x2 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_HBW_SEI_SHIFT 2 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_HBW_SEI_MASK 0x4 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_HBW_SEI_SHIFT 3 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_HBW_SEI_MASK 0x8 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_LBW_SEI_SHIFT 4 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_LBW_SEI_MASK 0x10 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_LBW_SEI_SHIFT 5 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_LBW_SEI_MASK 0x20 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_LBW_SEI_SHIFT 6 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_LBW_SEI_MASK 0x40 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_LBW_SEI_SHIFT 7 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_LBW_SEI_MASK 0x80 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_VCD_LBW_SEI_SHIFT 8 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_VCD_LBW_SEI_MASK 0x100 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_L2C_LBW_SEI_SHIFT 9 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_L2C_LBW_SEI_MASK 0x200 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_NRM_LBW_SEI_SHIFT 10 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_NRM_LBW_SEI_MASK 0x400 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_ABNRM_LBW_SEI_SHIFT 11 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_ABNRM_LBW_SEI_MASK 0x800 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_SEI_SHIFT 12 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_SEI_MASK 0x1000 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_APB_SEI_SHIFT 13 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_APB_SEI_MASK 0x2000 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_TRC_APB_SEI_SHIFT 14 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_TRC_APB_SEI_MASK 0x4000 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_MSTR_IF_SEI_SHIFT 15 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_MSTR_IF_SEI_MASK 0x8000 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_AXI_SPLIT_BRESP_ERR_SEI_SHIFT 16 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_AXI_SPLIT_BRESP_ERR_SEI_MASK 0x10000 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_WR_VIOL_SEI_SHIFT 17 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_WR_VIOL_SEI_MASK 0x20000 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_RD_VIOL_SEI_SHIFT 18 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_RD_VIOL_SEI_MASK 0x40000 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_WR_VIOL_SEI_SHIFT 19 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_WR_VIOL_SEI_MASK 0x80000 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_RD_VIOL_SEI_SHIFT 20 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_RD_VIOL_SEI_MASK 0x100000 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_VCD_SPI_SHIFT 21 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_VCD_SPI_MASK 0x200000 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_L2C_SPI_SHIFT 22 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_L2C_SPI_MASK 0x400000 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_NRM_SPI_SHIFT 23 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_NRM_SPI_MASK 0x800000 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_ABNRM_SPI_SHIFT 24 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_ABNRM_SPI_MASK 0x1000000 + +/* PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE */ +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLEN_GT_31_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLEN_GT_31_MASK 0x1 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_SHIFT 1 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_MASK 0x2 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWBURST_VIOL_SHIFT 2 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWBURST_VIOL_MASK 0x4 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWADDR_SIZE_ALIGN_VIOL_SHIFT 3 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWADDR_SIZE_ALIGN_VIOL_MASK 0x8 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_SHIFT 4 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_MASK 0x10 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLEN_GT_31_SHIFT 5 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLEN_GT_31_MASK 0x20 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLOCK_VIOL_SHIFT 6 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLOCK_VIOL_MASK 0x40 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_SHIFT 7 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_MASK 0x80 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_SHIFT 8 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_MASK \ +0x100 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_SHIFT 9 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_MASK 0x200 + +/* PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE */ +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_READ_ACCESS_VIOL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_READ_ACCESS_VIOL_MASK 0x1 +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_SHIFT 1 +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_MASK 0x2 +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWADDR_ALIGN_VIOL_SHIFT 2 +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWADDR_ALIGN_VIOL_MASK 0x4 +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_SHIFT 3 +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_MASK 0x8 +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLEN_VIOL_SHIFT 4 +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLEN_VIOL_MASK 0x10 +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_WSTRB_VIOL_SHIFT 5 +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_WSTRB_VIOL_MASK 0x20 + +/* PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM */ +#define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AW_VIOL_CLR_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AW_VIOL_CLR_MASK 0x1 +#define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AR_VIOL_CLR_SHIFT 1 +#define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AR_VIOL_CLR_MASK 0x2 +#define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_LBW_AW_VIOL_CLR_SHIFT 2 +#define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_LBW_AW_VIOL_CLR_MASK 0x4 + +/* PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK_MASK_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK_MASK_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK_MASK_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK_MASK_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK_VAL_MASK 0x1 + +/* PCIE_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK_VAL_MASK 0x1 + +/* PCIE_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK_VAL_MASK 0x1 + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK_VAL_MASK 0x1 + +/* PCIE_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_AWSIZE_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_AWSIZE_MASK 0x7 +#define PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_ARSIZE_SHIFT 3 +#define PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_ARSIZE_MASK 0x38 +#define PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_LBW_LEGAL_AWSIZE_SHIFT 6 +#define PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_LBW_LEGAL_AWSIZE_MASK 0x1C0 + +/* PCIE_VDEC0_BRDG_CTRL_ARC_MSG_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_ARC_MSG_MASK_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ARC_MSG_MASK_VAL_MASK 0x1 + +/* PCIE_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA */ +#define PCIE_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA_VAL_MASK 0xFF + +/* PCIE_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA */ +#define PCIE_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA_VAL_MASK 0xFF + +/* PCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL */ +#define PCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR */ +#define PCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L_IND_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L_IND_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H_IND_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H_IND_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L_IND_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L_IND_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H_IND_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H_IND_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_STAT_CNTR_EN */ +#define PCIE_VDEC0_BRDG_CTRL_STAT_CNTR_EN_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_STAT_CNTR_EN_VAL_MASK 0x1 + +/* PCIE_VDEC0_BRDG_CTRL_VCD_INTR_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_INTR_MASK_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_INTR_MASK_VAL_MASK 0x1 + +/* PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_WR_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_WR_MASK 0x1 +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_RD_SHIFT 1 +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_RD_MASK 0x2 +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_LBW_SHIFT 2 +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_LBW_MASK 0x4 + +/* PCIE_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA */ +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_L2C_INTR_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_INTR_MASK_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_INTR_MASK_VAL_MASK 0x1 + +/* PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_WR_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_WR_MASK 0x1 +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_RD_SHIFT 1 +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_RD_MASK 0x2 +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_LBW_SHIFT 2 +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_LBW_MASK 0x4 + +/* PCIE_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA */ +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_NRM_INTR_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_INTR_MASK_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_INTR_MASK_VAL_MASK 0x1 + +/* PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_WR_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_WR_MASK 0x1 +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_RD_SHIFT 1 +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_RD_MASK 0x2 +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_LBW_SHIFT 2 +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_LBW_MASK 0x4 + +/* PCIE_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA */ +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK_VAL_MASK 0x1 + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_WR_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_WR_MASK 0x1 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_RD_SHIFT 1 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_RD_MASK 0x2 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_LBW_SHIFT 2 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_LBW_MASK 0x4 + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR */ +#define PCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT_VAL_MASK 0x7 + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA */ +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID */ +#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID_ID_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID_ID_MASK 0xFF + +/* PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG */ +#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_RESP_OK_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_RESP_OK_MASK 0x1 +#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_WR_BUF_SHIFT 1 +#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_WR_BUF_MASK 0x2 +#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_RD_OS_SHIFT 8 +#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_RD_OS_MASK 0xFF00 +#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_WR_OS_SHIFT 16 +#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_WR_OS_MASK 0xFF0000 + +/* PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT */ +#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT_VAL_MASK 0x1 + +/* PCIE_VDEC0_BRDG_CTRL_HWEVENT_MASK */ +#define PCIE_VDEC0_BRDG_CTRL_HWEVENT_MASK_MASK_SHIFT 1 +#define PCIE_VDEC0_BRDG_CTRL_HWEVENT_MASK_MASK_MASK 0x2 + +/* PCIE_VDEC0_BRDG_CTRL_HWEVENT_CNTXT */ +#define PCIE_VDEC0_BRDG_CTRL_HWEVENT_CNTXT_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_HWEVENT_CNTXT_VAL_MASK 0xFFFF + +/* PCIE_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP */ +#define PCIE_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP_ERR_RESP_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP_ERR_RESP_MASK 0x3 + +/* PCIE_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP */ +#define PCIE_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP_ERR_RESP_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP_ERR_RESP_MASK 0x3 + +/* PCIE_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP */ +#define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_WR_ERR_RESP_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_WR_ERR_RESP_MASK 0x3 +#define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_RD_ERR_RESP_SHIFT 2 +#define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_RD_ERR_RESP_MASK 0xC + +/* PCIE_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS */ +#define PCIE_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AW_STA_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AW_STA_MASK 0x1 +#define PCIE_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AR_STA_SHIFT 1 +#define PCIE_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AR_STA_MASK 0x2 + +/* PCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L */ +#define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H */ +#define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L */ +#define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L_VAL_MASK 0xFFFFFFFF + +/* PCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H */ +#define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H_VAL_SHIFT 0 +#define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H_VAL_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_regs.h new file mode 100644 index 000000000000..c7badd212f2b --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_regs.h @@ -0,0 +1,245 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_REGS_H_ +#define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_REGS_H_ + +/* + ***************************************** + * PCIE_VDEC0_BRDG_CTRL + * (Prototype: VDEC_BRDG_CTRL) + ***************************************** + */ + +#define mmPCIE_VDEC0_BRDG_CTRL_CGM_DISABLE 0x4F03100 + +#define mmPCIE_VDEC0_BRDG_CTRL_IDLE_MASK 0x4F03104 + +#define mmPCIE_VDEC0_BRDG_CTRL_APB_CGM_CNT 0x4F03108 + +#define mmPCIE_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT 0x4F0310C + +#define mmPCIE_VDEC0_BRDG_CTRL_GRACEFUL 0x4F03110 + +#define mmPCIE_VDEC0_BRDG_CTRL_IDLE_CGM_CNT 0x4F03114 + +#define mmPCIE_VDEC0_BRDG_CTRL_CAUSE_INTR 0x4F03120 + +#define mmPCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE 0x4F03124 + +#define mmPCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE 0x4F03128 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM 0x4F0312C + +#define mmPCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK 0x4F03130 + +#define mmPCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK 0x4F03134 + +#define mmPCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK 0x4F03138 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK 0x4F03160 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK 0x4F03170 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK 0x4F03180 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK 0x4F03190 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT 0x4F031A0 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT 0x4F031A4 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT 0x4F031B0 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT 0x4F031B4 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT 0x4F031C0 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT 0x4F031C4 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE 0x4F031D0 + +#define mmPCIE_VDEC0_BRDG_CTRL_ARC_MSG_MASK 0x4F03200 + +#define mmPCIE_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA 0x4F03230 + +#define mmPCIE_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA 0x4F03260 + +#define mmPCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL 0x4F03270 + +#define mmPCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR 0x4F03280 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L 0x4F03290 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H 0x4F03294 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L 0x4F032A0 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H 0x4F032A4 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L 0x4F032B0 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H 0x4F032B4 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L 0x4F032C0 + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H 0x4F032C4 + +#define mmPCIE_VDEC0_BRDG_CTRL_STAT_CNTR_EN 0x4F032D0 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_INTR_MASK 0x4F03300 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK 0x4F03310 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR 0x4F03320 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR 0x4F03330 + +#define mmPCIE_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR 0x4F03334 + +#define mmPCIE_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR 0x4F03338 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR 0x4F03340 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR 0x4F03350 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA 0x4F03360 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT 0x4F03380 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L 0x4F03390 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H 0x4F03394 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT 0x4F033C0 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR 0x4F033D0 + +#define mmPCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA 0x4F033E0 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_INTR_MASK 0x4F03400 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK 0x4F03410 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR 0x4F03420 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR 0x4F03430 + +#define mmPCIE_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR 0x4F03434 + +#define mmPCIE_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR 0x4F03438 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR 0x4F03440 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR 0x4F03450 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA 0x4F03460 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT 0x4F03480 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L 0x4F03490 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H 0x4F03494 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT 0x4F034C0 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR 0x4F034D0 + +#define mmPCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA 0x4F034E0 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_INTR_MASK 0x4F03500 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK 0x4F03510 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR 0x4F03520 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR 0x4F03530 + +#define mmPCIE_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR 0x4F03534 + +#define mmPCIE_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR 0x4F03538 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR 0x4F03540 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR 0x4F03550 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA 0x4F03560 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT 0x4F03580 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L 0x4F03590 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H 0x4F03594 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT 0x4F035C0 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR 0x4F035D0 + +#define mmPCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA 0x4F035E0 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK 0x4F03600 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK 0x4F03610 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR 0x4F03620 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR 0x4F03630 + +#define mmPCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR 0x4F03634 + +#define mmPCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR 0x4F03638 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR 0x4F03640 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR 0x4F03650 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA 0x4F03660 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT 0x4F03680 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L 0x4F03690 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H 0x4F03694 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT 0x4F036C0 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR 0x4F036D0 + +#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA 0x4F036E0 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID 0x4F03700 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG 0x4F03704 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT 0x4F03708 + +#define mmPCIE_VDEC0_BRDG_CTRL_HWEVENT_MASK 0x4F0370C + +#define mmPCIE_VDEC0_BRDG_CTRL_HWEVENT_CNTXT 0x4F03714 + +#define mmPCIE_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP 0x4F03718 + +#define mmPCIE_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP 0x4F0371C + +#define mmPCIE_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP 0x4F03720 + +#define mmPCIE_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS 0x4F03724 + +#define mmPCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L 0x4F03728 + +#define mmPCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H 0x4F0372C + +#define mmPCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L 0x4F03730 + +#define mmPCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H 0x4F03734 + +#endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_ctrl_special_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_ctrl_special_regs.h new file mode 100644 index 000000000000..491b0cd935af --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_ctrl_special_regs.h @@ -0,0 +1,185 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_VDEC0_CTRL_SPECIAL_REGS_H_ +#define ASIC_REG_PCIE_VDEC0_CTRL_SPECIAL_REGS_H_ + +/* + ***************************************** + * PCIE_VDEC0_CTRL_SPECIAL + * (Prototype: SPECIAL_REGS) + ***************************************** + */ + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_0 0x4F04E80 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_1 0x4F04E84 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_2 0x4F04E88 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_3 0x4F04E8C + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_4 0x4F04E90 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_5 0x4F04E94 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_6 0x4F04E98 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_7 0x4F04E9C + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_8 0x4F04EA0 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_9 0x4F04EA4 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_10 0x4F04EA8 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_11 0x4F04EAC + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_12 0x4F04EB0 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_13 0x4F04EB4 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_14 0x4F04EB8 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_15 0x4F04EBC + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_16 0x4F04EC0 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_17 0x4F04EC4 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_18 0x4F04EC8 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_19 0x4F04ECC + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_20 0x4F04ED0 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_21 0x4F04ED4 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_22 0x4F04ED8 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_23 0x4F04EDC + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_24 0x4F04EE0 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_25 0x4F04EE4 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_26 0x4F04EE8 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_27 0x4F04EEC + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_28 0x4F04EF0 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_29 0x4F04EF4 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_30 0x4F04EF8 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_31 0x4F04EFC + +#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_GW_DATA 0x4F04F00 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_GW_REQ 0x4F04F04 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_NUMOF 0x4F04F0C + +#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_SEL 0x4F04F10 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_CTL 0x4F04F14 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_ERR_MASK 0x4F04F18 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_GLBL_ERR_MASK 0x4F04F1C + +#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_ERR_STS 0x4F04F20 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_ERR_ADDR 0x4F04F24 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_RM 0x4F04F28 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_ERR_MASK 0x4F04F40 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_ERR_ADDR 0x4F04F44 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_ERR_CAUSE 0x4F04F48 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SPARE_0 0x4F04F60 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SPARE_1 0x4F04F64 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SPARE_2 0x4F04F68 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SPARE_3 0x4F04F6C + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_0 0x4F04F80 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_1 0x4F04F84 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_2 0x4F04F88 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_3 0x4F04F8C + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_4 0x4F04F90 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_5 0x4F04F94 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_6 0x4F04F98 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_7 0x4F04F9C + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_8 0x4F04FA0 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_9 0x4F04FA4 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_10 0x4F04FA8 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_11 0x4F04FAC + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_12 0x4F04FB0 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_13 0x4F04FB4 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_14 0x4F04FB8 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_15 0x4F04FBC + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_16 0x4F04FC0 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_17 0x4F04FC4 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_18 0x4F04FC8 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_19 0x4F04FCC + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_20 0x4F04FD0 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_21 0x4F04FD4 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_22 0x4F04FD8 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_23 0x4F04FDC + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_24 0x4F04FE0 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_25 0x4F04FE4 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_26 0x4F04FE8 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_27 0x4F04FEC + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_28 0x4F04FF0 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_29 0x4F04FF4 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_30 0x4F04FF8 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_31 0x4F04FFC + +#endif /* ASIC_REG_PCIE_VDEC0_CTRL_SPECIAL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_wrap_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_wrap_regs.h new file mode 100644 index 000000000000..a09422f2f281 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pcie_wrap_regs.h @@ -0,0 +1,601 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PCIE_WRAP_REGS_H_ +#define ASIC_REG_PCIE_WRAP_REGS_H_ + +/* + ***************************************** + * PCIE_WRAP + * (Prototype: PCIE_WRAP) + ***************************************** + */ + +#define mmPCIE_WRAP_INTR_GEN_MASK_MIN_ADDR_0 0x4C01000 + +#define mmPCIE_WRAP_INTR_GEN_MASK_MIN_ADDR_1 0x4C01004 + +#define mmPCIE_WRAP_INTR_GEN_MASK_MAX_ADDR_0 0x4C01008 + +#define mmPCIE_WRAP_INTR_GEN_MASK_MAX_ADDR_1 0x4C0100C + +#define mmPCIE_WRAP_INTR_GEN_MASK_TIMER 0x4C01010 + +#define mmPCIE_WRAP_INTR_GEN_MASK_CTRL 0x4C01014 + +#define mmPCIE_WRAP_MSIX_DOORBELL_OFF_ADDR 0x4C01018 + +#define mmPCIE_WRAP_MSIX_MASK_CTRL 0x4C0101C + +#define mmPCIE_WRAP_PHY_FW_SRAM_ADDR_L_0 0x4C01020 + +#define mmPCIE_WRAP_PHY_FW_SRAM_ADDR_L_1 0x4C01024 + +#define mmPCIE_WRAP_PHY_FW_SRAM_ADDR_H_0 0x4C01028 + +#define mmPCIE_WRAP_PHY_FW_SRAM_ADDR_H_1 0x4C0102C + +#define mmPCIE_WRAP_PHY_FW_SRAM_CFG_ADDR 0x4C01030 + +#define mmPCIE_WRAP_MSIX_GW 0x4C01034 + +#define mmPCIE_WRAP_MSIX_GW_VEC 0x4C01038 + +#define mmPCIE_WRAP_MSIX_GW_INTR 0x4C0103C + +#define mmPCIE_WRAP_MSIX_GW_TABLE_0 0x4C01040 + +#define mmPCIE_WRAP_MSIX_GW_TABLE_1 0x4C01044 + +#define mmPCIE_WRAP_MSIX_GW_TABLE_2 0x4C01048 + +#define mmPCIE_WRAP_MSIX_GW_TABLE_3 0x4C0104C + +#define mmPCIE_WRAP_MSIX_GW_TABLE_4 0x4C01050 + +#define mmPCIE_WRAP_MSIX_GW_TABLE_5 0x4C01054 + +#define mmPCIE_WRAP_MSIX_GW_TABLE_6 0x4C01058 + +#define mmPCIE_WRAP_MSIX_GW_TABLE_7 0x4C0105C + +#define mmPCIE_WRAP_MSIX_GW_TABLE_8 0x4C01060 + +#define mmPCIE_WRAP_MSIX_GW_TABLE_9 0x4C01064 + +#define mmPCIE_WRAP_MSIX_GW_TABLE_10 0x4C01068 + +#define mmPCIE_WRAP_MSIX_GW_TABLE_11 0x4C0106C + +#define mmPCIE_WRAP_MSIX_GW_TABLE_12 0x4C01070 + +#define mmPCIE_WRAP_MSIX_GW_TABLE_13 0x4C01074 + +#define mmPCIE_WRAP_MSIX_GW_TABLE_14 0x4C01078 + +#define mmPCIE_WRAP_MSIX_GW_TABLE_15 0x4C0107C + +#define mmPCIE_WRAP_VUART_RX_0 0x4C01100 + +#define mmPCIE_WRAP_VUART_RX_1 0x4C01104 + +#define mmPCIE_WRAP_VUART_RX_2 0x4C01108 + +#define mmPCIE_WRAP_VUART_TX_0 0x4C0110C + +#define mmPCIE_WRAP_VUART_TX_1 0x4C01110 + +#define mmPCIE_WRAP_VUART_TX_2 0x4C01114 + +#define mmPCIE_WRAP_MSI_GW_BLOCK 0x4C01120 + +#define mmPCIE_WRAP_PHY_FW_FSM_SIZE 0x4C0120C + +#define mmPCIE_WRAP_HOST_ACCESS_TERMINATION 0x4C01210 + +#define mmPCIE_WRAP_ILLEGAL_LBW_REQ_CTRL 0x4C01214 + +#define mmPCIE_WRAP_ILLEGAL_LBW_REQ_ADDR_0 0x4C01218 + +#define mmPCIE_WRAP_ILLEGAL_LBW_REQ_ADDR_1 0x4C0121C + +#define mmPCIE_WRAP_ILLEGAL_LBW_REQ_INTR 0x4C01220 + +#define mmPCIE_WRAP_OUTBOUND_ADDR_LSB 0x4C01224 + +#define mmPCIE_WRAP_LBW_WSTRB_OVRD 0x4C01228 + +#define mmPCIE_WRAP_LBW_GW_ADDR_0 0x4C01304 + +#define mmPCIE_WRAP_LBW_GW_ADDR_1 0x4C01308 + +#define mmPCIE_WRAP_LBW_GW_ADDR_2 0x4C0130C + +#define mmPCIE_WRAP_LBW_GW_ADDR_3 0x4C01310 + +#define mmPCIE_WRAP_LBW_GW_ADDR_4 0x4C01314 + +#define mmPCIE_WRAP_LBW_GW_ADDR_5 0x4C01318 + +#define mmPCIE_WRAP_LBW_GW_ADDR_6 0x4C0131C + +#define mmPCIE_WRAP_LBW_GW_ADDR_7 0x4C01320 + +#define mmPCIE_WRAP_LBW_GW_DATA_0 0x4C01324 + +#define mmPCIE_WRAP_LBW_GW_DATA_1 0x4C01328 + +#define mmPCIE_WRAP_LBW_GW_DATA_2 0x4C0132C + +#define mmPCIE_WRAP_LBW_GW_DATA_3 0x4C01330 + +#define mmPCIE_WRAP_LBW_GW_DATA_4 0x4C01334 + +#define mmPCIE_WRAP_LBW_GW_DATA_5 0x4C01338 + +#define mmPCIE_WRAP_LBW_GW_DATA_6 0x4C0133C + +#define mmPCIE_WRAP_LBW_GW_DATA_7 0x4C01340 + +#define mmPCIE_WRAP_LBW_GW_GO_0 0x4C01344 + +#define mmPCIE_WRAP_LBW_GW_GO_1 0x4C01348 + +#define mmPCIE_WRAP_LBW_GW_GO_2 0x4C0134C + +#define mmPCIE_WRAP_LBW_GW_GO_3 0x4C01350 + +#define mmPCIE_WRAP_LBW_GW_GO_4 0x4C01354 + +#define mmPCIE_WRAP_LBW_GW_GO_5 0x4C01358 + +#define mmPCIE_WRAP_LBW_GW_GO_6 0x4C0135C + +#define mmPCIE_WRAP_LBW_GW_GO_7 0x4C01360 + +#define mmPCIE_WRAP_LBW_GW_STATUS_0 0x4C01364 + +#define mmPCIE_WRAP_LBW_GW_STATUS_1 0x4C01368 + +#define mmPCIE_WRAP_LBW_GW_STATUS_2 0x4C0136C + +#define mmPCIE_WRAP_LBW_GW_STATUS_3 0x4C01370 + +#define mmPCIE_WRAP_LBW_GW_STATUS_4 0x4C01374 + +#define mmPCIE_WRAP_LBW_GW_STATUS_5 0x4C01378 + +#define mmPCIE_WRAP_LBW_GW_STATUS_6 0x4C0137C + +#define mmPCIE_WRAP_LBW_GW_STATUS_7 0x4C01380 + +#define mmPCIE_WRAP_OUTBOUND_OUTSTANDING 0x4C013F4 + +#define mmPCIE_WRAP_MASK_REQ 0x4C01404 + +#define mmPCIE_WRAP_ONE_IN_FLIGHT 0x4C01408 + +#define mmPCIE_WRAP_IND_AWPROT 0x4C0140C + +#define mmPCIE_WRAP_SLV_AWMISC_INFO 0x4C01500 + +#define mmPCIE_WRAP_SLV_AWMISC_INFO_HDR_34DW_0 0x4C01504 + +#define mmPCIE_WRAP_SLV_AWMISC_INFO_HDR_34DW_1 0x4C01508 + +#define mmPCIE_WRAP_SLV_AWMISC_INFO_P_TAG 0x4C0150C + +#define mmPCIE_WRAP_SLV_AWMISC_INFO_ATU_BYPAS 0x4C01510 + +#define mmPCIE_WRAP_SLV_AWMISC_INFO_FUNC_NUM 0x4C01514 + +#define mmPCIE_WRAP_SLV_AWMISC_INFO_VFUNC_ACT 0x4C01518 + +#define mmPCIE_WRAP_SLV_AWMISC_INFO_VFUNC_NUM 0x4C0151C + +#define mmPCIE_WRAP_SLV_AWMISC_INFO_TLPPRFX 0x4C01520 + +#define mmPCIE_WRAP_SLV_ARMISC_INFO 0x4C01524 + +#define mmPCIE_WRAP_SLV_ARMISC_INFO_TLPPRFX 0x4C01528 + +#define mmPCIE_WRAP_SLV_ARMISC_INFO_ATU_BYP 0x4C0152C + +#define mmPCIE_WRAP_SLV_ARMISC_INFO_FUNC_NUM 0x4C01530 + +#define mmPCIE_WRAP_SLV_ARMISC_INFO_VFUNC_ACT 0x4C01534 + +#define mmPCIE_WRAP_SLV_ARMISC_INFO_VFUNC_NUM 0x4C01538 + +#define mmPCIE_WRAP_MESO_FIFO_CTRL_0 0x4C01640 + +#define mmPCIE_WRAP_MESO_FIFO_CTRL_1 0x4C01644 + +#define mmPCIE_WRAP_MESO_FIFO_W_LFSR_POLY_0 0x4C01648 + +#define mmPCIE_WRAP_MESO_FIFO_W_LFSR_POLY_1 0x4C0164C + +#define mmPCIE_WRAP_MESO_FIFO_R_LFSR_POLY_0 0x4C01650 + +#define mmPCIE_WRAP_MESO_FIFO_R_LFSR_POLY_1 0x4C01654 + +#define mmPCIE_WRAP_MESO_FIFO_W_PUSH_CNT_0 0x4C01658 + +#define mmPCIE_WRAP_MESO_FIFO_W_PUSH_CNT_1 0x4C0165C + +#define mmPCIE_WRAP_MESO_FIFO_W_BP_CNT_0 0x4C01660 + +#define mmPCIE_WRAP_MESO_FIFO_W_BP_CNT_1 0x4C01664 + +#define mmPCIE_WRAP_MESO_FIFO_R_ERR_CNT_0 0x4C01668 + +#define mmPCIE_WRAP_MESO_FIFO_R_ERR_CNT_1 0x4C0166C + +#define mmPCIE_WRAP_MESO_FIFO_R_POP_CNT_0 0x4C01670 + +#define mmPCIE_WRAP_MESO_FIFO_R_POP_CNT_1 0x4C01674 + +#define mmPCIE_WRAP_MESO_FIFO_W_LFSR_0 0x4C01678 + +#define mmPCIE_WRAP_MESO_FIFO_W_LFSR_1 0x4C0167C + +#define mmPCIE_WRAP_MESO_FIFO_R_LFSR_0 0x4C01680 + +#define mmPCIE_WRAP_MESO_FIFO_R_LFSR_1 0x4C01684 + +#define mmPCIE_WRAP_MESO_FIFO_W_PUSH_LFSR_0 0x4C01688 + +#define mmPCIE_WRAP_MESO_FIFO_W_PUSH_LFSR_1 0x4C0168C + +#define mmPCIE_WRAP_MESO_FIFO_R_POP_LFSR_0 0x4C01690 + +#define mmPCIE_WRAP_MESO_FIFO_R_POP_LFSR_1 0x4C01694 + +#define mmPCIE_WRAP_MESO_FIFO_W_BP_PERIOD_0 0x4C01698 + +#define mmPCIE_WRAP_MESO_FIFO_W_BP_PERIOD_1 0x4C0169C + +#define mmPCIE_WRAP_MESO_FIFO_R_BP_PERIOD_0 0x4C016A0 + +#define mmPCIE_WRAP_MESO_FIFO_R_BP_PERIOD_1 0x4C016A4 + +#define mmPCIE_WRAP_MESO_FIFO_W_USED_CNT_0 0x4C016A8 + +#define mmPCIE_WRAP_MESO_FIFO_W_USED_CNT_1 0x4C016AC + +#define mmPCIE_WRAP_MESO_FIFO_R_USED_CNT_0 0x4C016B0 + +#define mmPCIE_WRAP_MESO_FIFO_R_USED_CNT_1 0x4C016B4 + +#define mmPCIE_WRAP_P2P_TABLE_0 0x4C01900 + +#define mmPCIE_WRAP_P2P_TABLE_1 0x4C01904 + +#define mmPCIE_WRAP_P2P_TABLE_2 0x4C01908 + +#define mmPCIE_WRAP_P2P_TABLE_3 0x4C0190C + +#define mmPCIE_WRAP_P2P_TABLE_4 0x4C01910 + +#define mmPCIE_WRAP_P2P_TABLE_5 0x4C01914 + +#define mmPCIE_WRAP_P2P_TABLE_6 0x4C01918 + +#define mmPCIE_WRAP_P2P_TABLE_7 0x4C0191C + +#define mmPCIE_WRAP_P2P_TABLE_8 0x4C01920 + +#define mmPCIE_WRAP_P2P_TABLE_9 0x4C01924 + +#define mmPCIE_WRAP_P2P_TABLE_10 0x4C01928 + +#define mmPCIE_WRAP_P2P_TABLE_11 0x4C0192C + +#define mmPCIE_WRAP_P2P_TABLE_12 0x4C01930 + +#define mmPCIE_WRAP_P2P_TABLE_13 0x4C01934 + +#define mmPCIE_WRAP_P2P_TABLE_14 0x4C01938 + +#define mmPCIE_WRAP_P2P_TABLE_15 0x4C0193C + +#define mmPCIE_WRAP_P2P_TABLE_16 0x4C01940 + +#define mmPCIE_WRAP_P2P_TABLE_17 0x4C01944 + +#define mmPCIE_WRAP_P2P_TABLE_18 0x4C01948 + +#define mmPCIE_WRAP_P2P_TABLE_19 0x4C0194C + +#define mmPCIE_WRAP_P2P_TABLE_20 0x4C01950 + +#define mmPCIE_WRAP_P2P_TABLE_21 0x4C01954 + +#define mmPCIE_WRAP_P2P_TABLE_22 0x4C01958 + +#define mmPCIE_WRAP_P2P_TABLE_23 0x4C0195C + +#define mmPCIE_WRAP_P2P_TABLE_24 0x4C01960 + +#define mmPCIE_WRAP_P2P_TABLE_25 0x4C01964 + +#define mmPCIE_WRAP_P2P_TABLE_26 0x4C01968 + +#define mmPCIE_WRAP_P2P_TABLE_27 0x4C0196C + +#define mmPCIE_WRAP_P2P_TABLE_28 0x4C01970 + +#define mmPCIE_WRAP_P2P_TABLE_29 0x4C01974 + +#define mmPCIE_WRAP_P2P_TABLE_30 0x4C01978 + +#define mmPCIE_WRAP_P2P_TABLE_31 0x4C0197C + +#define mmPCIE_WRAP_P2P_TABLE_32 0x4C01980 + +#define mmPCIE_WRAP_P2P_TABLE_33 0x4C01984 + +#define mmPCIE_WRAP_P2P_TABLE_34 0x4C01988 + +#define mmPCIE_WRAP_P2P_TABLE_35 0x4C0198C + +#define mmPCIE_WRAP_P2P_TABLE_36 0x4C01990 + +#define mmPCIE_WRAP_P2P_TABLE_37 0x4C01994 + +#define mmPCIE_WRAP_P2P_TABLE_38 0x4C01998 + +#define mmPCIE_WRAP_P2P_TABLE_39 0x4C0199C + +#define mmPCIE_WRAP_P2P_TABLE_40 0x4C019A0 + +#define mmPCIE_WRAP_P2P_TABLE_41 0x4C019A4 + +#define mmPCIE_WRAP_P2P_TABLE_42 0x4C019A8 + +#define mmPCIE_WRAP_P2P_TABLE_43 0x4C019AC + +#define mmPCIE_WRAP_P2P_TABLE_44 0x4C019B0 + +#define mmPCIE_WRAP_P2P_TABLE_45 0x4C019B4 + +#define mmPCIE_WRAP_P2P_TABLE_46 0x4C019B8 + +#define mmPCIE_WRAP_P2P_TABLE_47 0x4C019BC + +#define mmPCIE_WRAP_P2P_TABLE_48 0x4C019C0 + +#define mmPCIE_WRAP_P2P_TABLE_49 0x4C019C4 + +#define mmPCIE_WRAP_P2P_TABLE_50 0x4C019C8 + +#define mmPCIE_WRAP_P2P_TABLE_51 0x4C019CC + +#define mmPCIE_WRAP_P2P_TABLE_52 0x4C019D0 + +#define mmPCIE_WRAP_P2P_TABLE_53 0x4C019D4 + +#define mmPCIE_WRAP_P2P_TABLE_54 0x4C019D8 + +#define mmPCIE_WRAP_P2P_TABLE_55 0x4C019DC + +#define mmPCIE_WRAP_P2P_TABLE_56 0x4C019E0 + +#define mmPCIE_WRAP_P2P_TABLE_57 0x4C019E4 + +#define mmPCIE_WRAP_P2P_TABLE_58 0x4C019E8 + +#define mmPCIE_WRAP_P2P_TABLE_59 0x4C019EC + +#define mmPCIE_WRAP_P2P_TABLE_60 0x4C019F0 + +#define mmPCIE_WRAP_P2P_TABLE_61 0x4C019F4 + +#define mmPCIE_WRAP_P2P_TABLE_62 0x4C019F8 + +#define mmPCIE_WRAP_P2P_TABLE_63 0x4C019FC + +#define mmPCIE_WRAP_P2P_EN 0x4C01A00 + +#define mmPCIE_WRAP_P2P_REQ_ID 0x4C01A04 + +#define mmPCIE_WRAP_P2P_INTR 0x4C01A08 + +#define mmPCIE_WRAP_P2P_TERMINATE_RESP 0x4C01A0C + +#define mmPCIE_WRAP_GIC_INTR_TERMINATE_CTRL 0x4C01A10 + +#define mmPCIE_WRAP_GIC_INTR_TERMINATE_CNT 0x4C01A14 + +#define mmPCIE_WRAP_CPU_HOT_RST 0x4C01AE0 + +#define mmPCIE_WRAP_LBW_AXI_SPLIT_MAX_OUTSTAN 0x4C01B2C + +#define mmPCIE_WRAP_AXI_SPLIT_NO_WR_INFLIGHT 0x4C01B30 + +#define mmPCIE_WRAP_PCIE_WR_BUF 0x4C01B34 + +#define mmPCIE_WRAP_PCIE_CACHE_OVR 0x4C01B38 + +#define mmPCIE_WRAP_PCIE_LOCK_OVR 0x4C01B3C + +#define mmPCIE_WRAP_PCIE_PROT_OVR 0x4C01B40 + +#define mmPCIE_WRAP_PCIE_ARUSER_OVR_0 0x4C01B44 + +#define mmPCIE_WRAP_PCIE_ARUSER_OVR_1 0x4C01B48 + +#define mmPCIE_WRAP_PCIE_AWUSER_OVR_0 0x4C01B4C + +#define mmPCIE_WRAP_PCIE_AWUSER_OVR_1 0x4C01B50 + +#define mmPCIE_WRAP_PCIE_ARUSER_OVR_EN_0 0x4C01B54 + +#define mmPCIE_WRAP_PCIE_ARUSER_OVR_EN_1 0x4C01B58 + +#define mmPCIE_WRAP_PCIE_AWUSER_OVR_EN_0 0x4C01B5C + +#define mmPCIE_WRAP_PCIE_AWUSER_OVR_EN_1 0x4C01B60 + +#define mmPCIE_WRAP_PCIE_MAX_OUTSTAND 0x4C01B64 + +#define mmPCIE_WRAP_PCIE_MST_IN 0x4C01B68 + +#define mmPCIE_WRAP_PCIE_RSP_OK 0x4C01B6C + +#define mmPCIE_WRAP_AXI_SPLIT_INTR_0 0x4C01B70 + +#define mmPCIE_WRAP_AXI_SPLIT_INTR_1 0x4C01B74 + +#define mmPCIE_WRAP_AXI_DRAIN_MSTR_IF_CFG_0 0x4C01B7C + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_0 0x4C01B80 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_1 0x4C01B84 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_2 0x4C01B88 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_3 0x4C01B8C + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_4 0x4C01B90 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_5 0x4C01B94 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_6 0x4C01B98 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_7 0x4C01B9C + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_8 0x4C01BA0 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_9 0x4C01BA4 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_10 0x4C01BA8 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_11 0x4C01BAC + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_12 0x4C01BB0 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_13 0x4C01BB4 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_14 0x4C01BB8 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_15 0x4C01BBC + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_16 0x4C01BC0 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_17 0x4C01BC4 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_18 0x4C01BC8 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_19 0x4C01BCC + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_20 0x4C01BD0 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_21 0x4C01BD4 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_22 0x4C01BD8 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_23 0x4C01BDC + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_24 0x4C01BE0 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_25 0x4C01BE4 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_26 0x4C01BE8 + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_27 0x4C01BEC + +#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_28 0x4C01BF0 + +#define mmPCIE_WRAP_AXI_DRAIN_ACTIVE 0x4C01D48 + +#define mmPCIE_WRAP_AXI_DRAIN_IND 0x4C01D4C + +#define mmPCIE_WRAP_HBW_DRAIN_TIMEOUT 0x4C01D50 + +#define mmPCIE_WRAP_HBW_DRAIN_CFG 0x4C01D54 + +#define mmPCIE_WRAP_LBW_DRAIN_TIMEOUT 0x4C01D58 + +#define mmPCIE_WRAP_LBW_DRAIN_CFG 0x4C01D5C + +#define mmPCIE_WRAP_LBW_DRAIN_DELAY_EN_CNT 0x4C01D60 + +#define mmPCIE_WRAP_PHY_FW_FSM 0x4C01D64 + +#define mmPCIE_WRAP_PCIE_PHY_BASE_ADDR_L 0x4C01D68 + +#define mmPCIE_WRAP_PCIE_PHY_BASE_ADDR_H 0x4C01D6C + +#define mmPCIE_WRAP_PCIE_CORE_BASE_ADDR_L 0x4C01D70 + +#define mmPCIE_WRAP_PCIE_CORE_BASE_ADDR_H 0x4C01D74 + +#define mmPCIE_WRAP_SPMU_INTR 0x4C01DE4 + +#define mmPCIE_WRAP_AXI_INTR 0x4C01DE8 + +#define mmPCIE_WRAP_PCIE_IC_SEI_INTR_IND 0x4C01DEC + +#define mmPCIE_WRAP_PMMU_RTR_CFG 0x4C01DF0 + +#define mmPCIE_WRAP_PSOC_RST_CTRL 0x4C01DF4 + +#define mmPCIE_WRAP_PSOC_BOOT_MNG_DONE 0x4C01DF8 + +#define mmPCIE_WRAP_ASID_MOD_CTRL 0x4C01DFC + +#define mmPCIE_WRAP_ASID_MOD_ADDR_L_0 0x4C01E00 + +#define mmPCIE_WRAP_ASID_MOD_ADDR_L_1 0x4C01E04 + +#define mmPCIE_WRAP_ASID_MOD_ADDR_H_0 0x4C01E08 + +#define mmPCIE_WRAP_ASID_MOD_ADDR_H_1 0x4C01E0C + +#define mmPCIE_WRAP_CS_TRACE_AXI_CTRL 0x4C01E10 + +#define mmPCIE_WRAP_FLR_FSM_CTRL 0x4C01E14 + +#define mmPCIE_WRAP_HBW_DRAIN_WR_ADDR_0 0x4C01E18 + +#define mmPCIE_WRAP_HBW_DRAIN_WR_ADDR_1 0x4C01E1C + +#define mmPCIE_WRAP_HBW_DRAIN_RD_ADDR_0 0x4C01E20 + +#define mmPCIE_WRAP_HBW_DRAIN_RD_ADDR_1 0x4C01E24 + +#define mmPCIE_WRAP_HBW_DRAIN_STAMP 0x4C01E28 + +#define mmPCIE_WRAP_LBW_DRAIN_WR_ADDR_0 0x4C01E2C + +#define mmPCIE_WRAP_LBW_DRAIN_WR_ADDR_1 0x4C01E30 + +#define mmPCIE_WRAP_LBW_DRAIN_RD_ADDR_0 0x4C01E34 + +#define mmPCIE_WRAP_LBW_DRAIN_RD_ADDR_1 0x4C01E38 + +#define mmPCIE_WRAP_LBW_DRAIN_STAMP 0x4C01E3C + +#define mmPCIE_WRAP_EXTMEM_HBM_LOC 0x4C01E40 + +#define mmPCIE_WRAP_EXTMEM_PC_LOC 0x4C01E44 + +#define mmPCIE_WRAP_EXTMEM_NONLIN_HBM 0x4C01E48 + +#define mmPCIE_WRAP_EXTMEM_NONLIN_PC 0x4C01E4C + +#define mmPCIE_WRAP_EXTMEM_NONLIN_HBM_NUM 0x4C01E50 + +#define mmPCIE_WRAP_EXTMEM_NONLIN_HBM_MAP 0x4C01E54 + +#endif /* ASIC_REG_PCIE_WRAP_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_ctx_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_ctx_axuser_regs.h new file mode 100644 index 000000000000..bacbe4c6fc3c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_ctx_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA0_CORE_CTX_AXUSER_REGS_H_ +#define ASIC_REG_PDMA0_CORE_CTX_AXUSER_REGS_H_ + +/* + ***************************************** + * PDMA0_CORE_CTX_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmPDMA0_CORE_CTX_AXUSER_HB_ASID 0x4C8B800 + +#define mmPDMA0_CORE_CTX_AXUSER_HB_MMU_BP 0x4C8B804 + +#define mmPDMA0_CORE_CTX_AXUSER_HB_STRONG_ORDER 0x4C8B808 + +#define mmPDMA0_CORE_CTX_AXUSER_HB_NO_SNOOP 0x4C8B80C + +#define mmPDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION 0x4C8B810 + +#define mmPDMA0_CORE_CTX_AXUSER_HB_RD_ATOMIC 0x4C8B814 + +#define mmPDMA0_CORE_CTX_AXUSER_HB_QOS 0x4C8B818 + +#define mmPDMA0_CORE_CTX_AXUSER_HB_RSVD 0x4C8B81C + +#define mmPDMA0_CORE_CTX_AXUSER_HB_EMEM_CPAGE 0x4C8B820 + +#define mmPDMA0_CORE_CTX_AXUSER_HB_CORE 0x4C8B824 + +#define mmPDMA0_CORE_CTX_AXUSER_E2E_COORD 0x4C8B828 + +#define mmPDMA0_CORE_CTX_AXUSER_HB_WR_OVRD_LO 0x4C8B830 + +#define mmPDMA0_CORE_CTX_AXUSER_HB_WR_OVRD_HI 0x4C8B834 + +#define mmPDMA0_CORE_CTX_AXUSER_HB_RD_OVRD_LO 0x4C8B838 + +#define mmPDMA0_CORE_CTX_AXUSER_HB_RD_OVRD_HI 0x4C8B83C + +#define mmPDMA0_CORE_CTX_AXUSER_LB_COORD 0x4C8B840 + +#define mmPDMA0_CORE_CTX_AXUSER_LB_LOCK 0x4C8B844 + +#define mmPDMA0_CORE_CTX_AXUSER_LB_RSVD 0x4C8B848 + +#define mmPDMA0_CORE_CTX_AXUSER_LB_OVRD 0x4C8B84C + +#endif /* ASIC_REG_PDMA0_CORE_CTX_AXUSER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_ctx_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_ctx_regs.h new file mode 100644 index 000000000000..02b57f07cfaf --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_ctx_regs.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA0_CORE_CTX_REGS_H_ +#define ASIC_REG_PDMA0_CORE_CTX_REGS_H_ + +/* + ***************************************** + * PDMA0_CORE_CTX + * (Prototype: DMA_CORE_CTX) + ***************************************** + */ + +#define mmPDMA0_CORE_CTX_RATE_LIM_TKN 0x4C8B860 + +#define mmPDMA0_CORE_CTX_PWRLP 0x4C8B864 + +#define mmPDMA0_CORE_CTX_TE_NUMROWS 0x4C8B868 + +#define mmPDMA0_CORE_CTX_IDX 0x4C8B86C + +#define mmPDMA0_CORE_CTX_IDX_INC 0x4C8B870 + +#define mmPDMA0_CORE_CTX_CTRL 0x4C8B874 + +#define mmPDMA0_CORE_CTX_SRC_TSIZE_0 0x4C8B878 + +#define mmPDMA0_CORE_CTX_SRC_TSIZE_1 0x4C8B87C + +#define mmPDMA0_CORE_CTX_SRC_STRIDE_1 0x4C8B880 + +#define mmPDMA0_CORE_CTX_SRC_TSIZE_2 0x4C8B884 + +#define mmPDMA0_CORE_CTX_SRC_STRIDE_2 0x4C8B888 + +#define mmPDMA0_CORE_CTX_SRC_TSIZE_3 0x4C8B88C + +#define mmPDMA0_CORE_CTX_SRC_STRIDE_3 0x4C8B890 + +#define mmPDMA0_CORE_CTX_SRC_TSIZE_4 0x4C8B894 + +#define mmPDMA0_CORE_CTX_SRC_STRIDE_4 0x4C8B898 + +#define mmPDMA0_CORE_CTX_DST_TSIZE_1 0x4C8B89C + +#define mmPDMA0_CORE_CTX_DST_STRIDE_1 0x4C8B8A0 + +#define mmPDMA0_CORE_CTX_DST_TSIZE_2 0x4C8B8A4 + +#define mmPDMA0_CORE_CTX_DST_STRIDE_2 0x4C8B8A8 + +#define mmPDMA0_CORE_CTX_DST_TSIZE_3 0x4C8B8AC + +#define mmPDMA0_CORE_CTX_DST_STRIDE_3 0x4C8B8B0 + +#define mmPDMA0_CORE_CTX_DST_TSIZE_4 0x4C8B8B4 + +#define mmPDMA0_CORE_CTX_DST_STRIDE_4 0x4C8B8B8 + +#define mmPDMA0_CORE_CTX_WR_COMP_ADDR_HI 0x4C8B8BC + +#define mmPDMA0_CORE_CTX_WR_COMP_ADDR_LO 0x4C8B8C0 + +#define mmPDMA0_CORE_CTX_WR_COMP_WDATA 0x4C8B8C4 + +#define mmPDMA0_CORE_CTX_SRC_OFFSET_LO 0x4C8B8C8 + +#define mmPDMA0_CORE_CTX_SRC_OFFSET_HI 0x4C8B8CC + +#define mmPDMA0_CORE_CTX_DST_OFFSET_LO 0x4C8B8D0 + +#define mmPDMA0_CORE_CTX_DST_OFFSET_HI 0x4C8B8D4 + +#define mmPDMA0_CORE_CTX_SRC_BASE_LO 0x4C8B8D8 + +#define mmPDMA0_CORE_CTX_SRC_BASE_HI 0x4C8B8DC + +#define mmPDMA0_CORE_CTX_DST_BASE_LO 0x4C8B8E0 + +#define mmPDMA0_CORE_CTX_DST_BASE_HI 0x4C8B8E4 + +#define mmPDMA0_CORE_CTX_DST_TSIZE_0 0x4C8B8E8 + +#define mmPDMA0_CORE_CTX_COMMIT 0x4C8B8EC + +#endif /* ASIC_REG_PDMA0_CORE_CTX_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_masks.h new file mode 100644 index 000000000000..909cda03c246 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_masks.h @@ -0,0 +1,415 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA0_CORE_MASKS_H_ +#define ASIC_REG_PDMA0_CORE_MASKS_H_ + +/* + ***************************************** + * PDMA0_CORE + * (Prototype: DMA_CORE) + ***************************************** + */ + +/* PDMA0_CORE_CFG_0 */ +#define PDMA0_CORE_CFG_0_EN_SHIFT 0 +#define PDMA0_CORE_CFG_0_EN_MASK 0x1 + +/* PDMA0_CORE_CFG_1 */ +#define PDMA0_CORE_CFG_1_HALT_SHIFT 0 +#define PDMA0_CORE_CFG_1_HALT_MASK 0x1 +#define PDMA0_CORE_CFG_1_FLUSH_SHIFT 1 +#define PDMA0_CORE_CFG_1_FLUSH_MASK 0x2 + +/* PDMA0_CORE_PROT */ +#define PDMA0_CORE_PROT_VAL_SHIFT 0 +#define PDMA0_CORE_PROT_VAL_MASK 0x1 +#define PDMA0_CORE_PROT_ERR_VAL_SHIFT 1 +#define PDMA0_CORE_PROT_ERR_VAL_MASK 0x2 + +/* PDMA0_CORE_CKG */ +#define PDMA0_CORE_CKG_HBW_RBUF_SHIFT 0 +#define PDMA0_CORE_CKG_HBW_RBUF_MASK 0x1 +#define PDMA0_CORE_CKG_LBW_RBUF_KDMA_SHIFT 1 +#define PDMA0_CORE_CKG_LBW_RBUF_KDMA_MASK 0x2 +#define PDMA0_CORE_CKG_TE_SHIFT 2 +#define PDMA0_CORE_CKG_TE_MASK 0x4 + +/* PDMA0_CORE_RD_GLBL */ +#define PDMA0_CORE_RD_GLBL_LBW_VIA_HBW_SHIFT 0 +#define PDMA0_CORE_RD_GLBL_LBW_VIA_HBW_MASK 0x1 +#define PDMA0_CORE_RD_GLBL_HBW_FORCE_MISS_SHIFT 4 +#define PDMA0_CORE_RD_GLBL_HBW_FORCE_MISS_MASK 0x10 +#define PDMA0_CORE_RD_GLBL_LBW_FORCE_MISS_SHIFT 5 +#define PDMA0_CORE_RD_GLBL_LBW_FORCE_MISS_MASK 0x20 + +/* PDMA0_CORE_RD_HBW_MAX_OUTSTAND */ +#define PDMA0_CORE_RD_HBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define PDMA0_CORE_RD_HBW_MAX_OUTSTAND_VAL_MASK 0xFFF + +/* PDMA0_CORE_RD_HBW_MAX_SIZE */ +#define PDMA0_CORE_RD_HBW_MAX_SIZE_DATA_SHIFT 0 +#define PDMA0_CORE_RD_HBW_MAX_SIZE_DATA_MASK 0xFFF +#define PDMA0_CORE_RD_HBW_MAX_SIZE_MD_SHIFT 16 +#define PDMA0_CORE_RD_HBW_MAX_SIZE_MD_MASK 0xFFF0000 + +/* PDMA0_CORE_RD_HBW_ARCACHE */ +#define PDMA0_CORE_RD_HBW_ARCACHE_VAL_SHIFT 0 +#define PDMA0_CORE_RD_HBW_ARCACHE_VAL_MASK 0xF + +/* PDMA0_CORE_RD_HBW_INFLIGHTS */ +#define PDMA0_CORE_RD_HBW_INFLIGHTS_VAL_SHIFT 0 +#define PDMA0_CORE_RD_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_RD_HBW_RATE_LIM_CFG */ +#define PDMA0_CORE_RD_HBW_RATE_LIM_CFG_TOUT_SHIFT 0 +#define PDMA0_CORE_RD_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF +#define PDMA0_CORE_RD_HBW_RATE_LIM_CFG_SAT_SHIFT 16 +#define PDMA0_CORE_RD_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 +#define PDMA0_CORE_RD_HBW_RATE_LIM_CFG_EN_SHIFT 31 +#define PDMA0_CORE_RD_HBW_RATE_LIM_CFG_EN_MASK 0x80000000 + +/* PDMA0_CORE_RD_LBW_MAX_OUTSTAND */ +#define PDMA0_CORE_RD_LBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define PDMA0_CORE_RD_LBW_MAX_OUTSTAND_VAL_MASK 0xFFF + +/* PDMA0_CORE_RD_LBW_MAX_SIZE */ +#define PDMA0_CORE_RD_LBW_MAX_SIZE_DATA_SHIFT 0 +#define PDMA0_CORE_RD_LBW_MAX_SIZE_DATA_MASK 0xFFF +#define PDMA0_CORE_RD_LBW_MAX_SIZE_MD_SHIFT 16 +#define PDMA0_CORE_RD_LBW_MAX_SIZE_MD_MASK 0xFFF0000 + +/* PDMA0_CORE_RD_LBW_ARCACHE */ +#define PDMA0_CORE_RD_LBW_ARCACHE_VAL_SHIFT 0 +#define PDMA0_CORE_RD_LBW_ARCACHE_VAL_MASK 0xF + +/* PDMA0_CORE_RD_LBW_INFLIGHTS */ +#define PDMA0_CORE_RD_LBW_INFLIGHTS_VAL_SHIFT 0 +#define PDMA0_CORE_RD_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_RD_LBW_RATE_LIM_CFG */ +#define PDMA0_CORE_RD_LBW_RATE_LIM_CFG_TOUT_SHIFT 0 +#define PDMA0_CORE_RD_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF +#define PDMA0_CORE_RD_LBW_RATE_LIM_CFG_SAT_SHIFT 16 +#define PDMA0_CORE_RD_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 +#define PDMA0_CORE_RD_LBW_RATE_LIM_CFG_EN_SHIFT 31 +#define PDMA0_CORE_RD_LBW_RATE_LIM_CFG_EN_MASK 0x80000000 + +/* PDMA0_CORE_WR_HBW_MAX_OUTSTAND */ +#define PDMA0_CORE_WR_HBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define PDMA0_CORE_WR_HBW_MAX_OUTSTAND_VAL_MASK 0xFFFF + +/* PDMA0_CORE_WR_HBW_MAX_AWID */ +#define PDMA0_CORE_WR_HBW_MAX_AWID_VAL_SHIFT 0 +#define PDMA0_CORE_WR_HBW_MAX_AWID_VAL_MASK 0x3FFF + +/* PDMA0_CORE_WR_HBW_AWCACHE */ +#define PDMA0_CORE_WR_HBW_AWCACHE_VAL_SHIFT 0 +#define PDMA0_CORE_WR_HBW_AWCACHE_VAL_MASK 0xF + +/* PDMA0_CORE_WR_HBW_INFLIGHTS */ +#define PDMA0_CORE_WR_HBW_INFLIGHTS_VAL_SHIFT 0 +#define PDMA0_CORE_WR_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_WR_HBW_RATE_LIM_CFG */ +#define PDMA0_CORE_WR_HBW_RATE_LIM_CFG_TOUT_SHIFT 0 +#define PDMA0_CORE_WR_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF +#define PDMA0_CORE_WR_HBW_RATE_LIM_CFG_SAT_SHIFT 16 +#define PDMA0_CORE_WR_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 +#define PDMA0_CORE_WR_HBW_RATE_LIM_CFG_EN_SHIFT 31 +#define PDMA0_CORE_WR_HBW_RATE_LIM_CFG_EN_MASK 0x80000000 + +/* PDMA0_CORE_WR_LBW_MAX_OUTSTAND */ +#define PDMA0_CORE_WR_LBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define PDMA0_CORE_WR_LBW_MAX_OUTSTAND_VAL_MASK 0xFFFF + +/* PDMA0_CORE_WR_LBW_MAX_AWID */ +#define PDMA0_CORE_WR_LBW_MAX_AWID_VAL_SHIFT 0 +#define PDMA0_CORE_WR_LBW_MAX_AWID_VAL_MASK 0x7F + +/* PDMA0_CORE_WR_LBW_AWCACHE */ +#define PDMA0_CORE_WR_LBW_AWCACHE_VAL_SHIFT 0 +#define PDMA0_CORE_WR_LBW_AWCACHE_VAL_MASK 0xF + +/* PDMA0_CORE_WR_LBW_INFLIGHTS */ +#define PDMA0_CORE_WR_LBW_INFLIGHTS_VAL_SHIFT 0 +#define PDMA0_CORE_WR_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_WR_LBW_RATE_LIM_CFG */ +#define PDMA0_CORE_WR_LBW_RATE_LIM_CFG_TOUT_SHIFT 0 +#define PDMA0_CORE_WR_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF +#define PDMA0_CORE_WR_LBW_RATE_LIM_CFG_SAT_SHIFT 16 +#define PDMA0_CORE_WR_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 +#define PDMA0_CORE_WR_LBW_RATE_LIM_CFG_EN_SHIFT 31 +#define PDMA0_CORE_WR_LBW_RATE_LIM_CFG_EN_MASK 0x80000000 + +/* PDMA0_CORE_WR_COMP_MAX_OUTSTAND */ +#define PDMA0_CORE_WR_COMP_MAX_OUTSTAND_VAL_SHIFT 0 +#define PDMA0_CORE_WR_COMP_MAX_OUTSTAND_VAL_MASK 0x1F + +/* PDMA0_CORE_WR_COMP_AWUSER */ +#define PDMA0_CORE_WR_COMP_AWUSER_VAL_SHIFT 0 +#define PDMA0_CORE_WR_COMP_AWUSER_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_ERR_CFG */ +#define PDMA0_CORE_ERR_CFG_ERR_MSG_EN_SHIFT 0 +#define PDMA0_CORE_ERR_CFG_ERR_MSG_EN_MASK 0x1 +#define PDMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT 1 +#define PDMA0_CORE_ERR_CFG_STOP_ON_ERR_MASK 0x2 + +/* PDMA0_CORE_ERR_CAUSE */ +#define PDMA0_CORE_ERR_CAUSE_HBW_RD_ERR_SHIFT 0 +#define PDMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK 0x1 +#define PDMA0_CORE_ERR_CAUSE_HBW_WR_ERR_SHIFT 1 +#define PDMA0_CORE_ERR_CAUSE_HBW_WR_ERR_MASK 0x2 +#define PDMA0_CORE_ERR_CAUSE_LBW_MSG_WR_ERR_SHIFT 2 +#define PDMA0_CORE_ERR_CAUSE_LBW_MSG_WR_ERR_MASK 0x4 +#define PDMA0_CORE_ERR_CAUSE_DESC_OVF_SHIFT 3 +#define PDMA0_CORE_ERR_CAUSE_DESC_OVF_MASK 0x8 +#define PDMA0_CORE_ERR_CAUSE_LBW_RD_ERR_SHIFT 4 +#define PDMA0_CORE_ERR_CAUSE_LBW_RD_ERR_MASK 0x10 +#define PDMA0_CORE_ERR_CAUSE_LBW_WR_ERR_SHIFT 5 +#define PDMA0_CORE_ERR_CAUSE_LBW_WR_ERR_MASK 0x20 +#define PDMA0_CORE_ERR_CAUSE_TE_DESC_FIFO_OVFL_SHIFT 6 +#define PDMA0_CORE_ERR_CAUSE_TE_DESC_FIFO_OVFL_MASK 0x40 +#define PDMA0_CORE_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_SHIFT 7 +#define PDMA0_CORE_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_MASK 0x80 + +/* PDMA0_CORE_ERRMSG_ADDR_LO */ +#define PDMA0_CORE_ERRMSG_ADDR_LO_VAL_SHIFT 0 +#define PDMA0_CORE_ERRMSG_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_ERRMSG_ADDR_HI */ +#define PDMA0_CORE_ERRMSG_ADDR_HI_VAL_SHIFT 0 +#define PDMA0_CORE_ERRMSG_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_ERRMSG_WDATA */ +#define PDMA0_CORE_ERRMSG_WDATA_VAL_SHIFT 0 +#define PDMA0_CORE_ERRMSG_WDATA_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_STS0 */ +#define PDMA0_CORE_STS0_RD_REQ_CNT_SHIFT 0 +#define PDMA0_CORE_STS0_RD_REQ_CNT_MASK 0x7FFF +#define PDMA0_CORE_STS0_WR_REQ_CNT_SHIFT 16 +#define PDMA0_CORE_STS0_WR_REQ_CNT_MASK 0x7FFF0000 +#define PDMA0_CORE_STS0_BUSY_SHIFT 31 +#define PDMA0_CORE_STS0_BUSY_MASK 0x80000000 + +/* PDMA0_CORE_STS1 */ +#define PDMA0_CORE_STS1_IS_HALT_SHIFT 0 +#define PDMA0_CORE_STS1_IS_HALT_MASK 0x1 + +/* PDMA0_CORE_STS_RD_CTX_SEL */ +#define PDMA0_CORE_STS_RD_CTX_SEL_VAL_SHIFT 0 +#define PDMA0_CORE_STS_RD_CTX_SEL_VAL_MASK 0x7 +#define PDMA0_CORE_STS_RD_CTX_SEL_STRIDE_SHIFT 8 +#define PDMA0_CORE_STS_RD_CTX_SEL_STRIDE_MASK 0x100 + +/* PDMA0_CORE_STS_RD_CTX_SIZE */ +#define PDMA0_CORE_STS_RD_CTX_SIZE_VAL_SHIFT 0 +#define PDMA0_CORE_STS_RD_CTX_SIZE_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_STS_RD_CTX_BASE_LO */ +#define PDMA0_CORE_STS_RD_CTX_BASE_LO_VAL_SHIFT 0 +#define PDMA0_CORE_STS_RD_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_STS_RD_CTX_BASE_HI */ +#define PDMA0_CORE_STS_RD_CTX_BASE_HI_VAL_SHIFT 0 +#define PDMA0_CORE_STS_RD_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_STS_RD_CTX_ID */ +#define PDMA0_CORE_STS_RD_CTX_ID_VAL_SHIFT 0 +#define PDMA0_CORE_STS_RD_CTX_ID_VAL_MASK 0xFFFF + +/* PDMA0_CORE_STS_RD_HB_AXI_ADDR_LO */ +#define PDMA0_CORE_STS_RD_HB_AXI_ADDR_LO_VAL_SHIFT 0 +#define PDMA0_CORE_STS_RD_HB_AXI_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_STS_RD_HB_AXI_ADDR_HI */ +#define PDMA0_CORE_STS_RD_HB_AXI_ADDR_HI_VAL_SHIFT 0 +#define PDMA0_CORE_STS_RD_HB_AXI_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_STS_RD_LB_AXI_ADDR */ +#define PDMA0_CORE_STS_RD_LB_AXI_ADDR_VAL_SHIFT 0 +#define PDMA0_CORE_STS_RD_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF +#define PDMA0_CORE_STS_RD_LB_AXI_ADDR_RDY_SHIFT 30 +#define PDMA0_CORE_STS_RD_LB_AXI_ADDR_RDY_MASK 0x40000000 +#define PDMA0_CORE_STS_RD_LB_AXI_ADDR_VLD_SHIFT 31 +#define PDMA0_CORE_STS_RD_LB_AXI_ADDR_VLD_MASK 0x80000000 + +/* PDMA0_CORE_STS_WR_CTX_SEL */ +#define PDMA0_CORE_STS_WR_CTX_SEL_VAL_SHIFT 0 +#define PDMA0_CORE_STS_WR_CTX_SEL_VAL_MASK 0x7 +#define PDMA0_CORE_STS_WR_CTX_SEL_STRIDE_SHIFT 8 +#define PDMA0_CORE_STS_WR_CTX_SEL_STRIDE_MASK 0x100 + +/* PDMA0_CORE_STS_WR_CTX_SIZE */ +#define PDMA0_CORE_STS_WR_CTX_SIZE_VAL_SHIFT 0 +#define PDMA0_CORE_STS_WR_CTX_SIZE_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_STS_WR_CTX_BASE_LO */ +#define PDMA0_CORE_STS_WR_CTX_BASE_LO_VAL_SHIFT 0 +#define PDMA0_CORE_STS_WR_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_STS_WR_CTX_BASE_HI */ +#define PDMA0_CORE_STS_WR_CTX_BASE_HI_VAL_SHIFT 0 +#define PDMA0_CORE_STS_WR_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_STS_WR_CTX_ID */ +#define PDMA0_CORE_STS_WR_CTX_ID_VAL_SHIFT 0 +#define PDMA0_CORE_STS_WR_CTX_ID_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO */ +#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VAL_SHIFT 0 +#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VAL_MASK 0x3FFFF +#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_RDY_SHIFT 30 +#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_RDY_MASK 0x40000000 +#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VLD_SHIFT 31 +#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VLD_MASK 0x80000000 + +/* PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI */ +#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VAL_SHIFT 0 +#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VAL_MASK 0x3FFFF +#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_RDY_SHIFT 30 +#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_RDY_MASK 0x40000000 +#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VLD_SHIFT 31 +#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VLD_MASK 0x80000000 + +/* PDMA0_CORE_STS_WR_LB_AXI_ADDR */ +#define PDMA0_CORE_STS_WR_LB_AXI_ADDR_VAL_SHIFT 0 +#define PDMA0_CORE_STS_WR_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF +#define PDMA0_CORE_STS_WR_LB_AXI_ADDR_RDY_SHIFT 30 +#define PDMA0_CORE_STS_WR_LB_AXI_ADDR_RDY_MASK 0x40000000 +#define PDMA0_CORE_STS_WR_LB_AXI_ADDR_VLD_SHIFT 31 +#define PDMA0_CORE_STS_WR_LB_AXI_ADDR_VLD_MASK 0x80000000 + +/* PDMA0_CORE_PWRLP_CFG */ +#define PDMA0_CORE_PWRLP_CFG_GLBL_EN_SHIFT 0 +#define PDMA0_CORE_PWRLP_CFG_GLBL_EN_MASK 0x1 +#define PDMA0_CORE_PWRLP_CFG_CLR_SHIFT 4 +#define PDMA0_CORE_PWRLP_CFG_CLR_MASK 0x10 + +/* PDMA0_CORE_PWRLP_STS */ +#define PDMA0_CORE_PWRLP_STS_RLVL_SHIFT 0 +#define PDMA0_CORE_PWRLP_STS_RLVL_MASK 0x7F +#define PDMA0_CORE_PWRLP_STS_WLVL_SHIFT 8 +#define PDMA0_CORE_PWRLP_STS_WLVL_MASK 0x7F00 +#define PDMA0_CORE_PWRLP_STS_RCNT_SHIFT 16 +#define PDMA0_CORE_PWRLP_STS_RCNT_MASK 0x7F0000 +#define PDMA0_CORE_PWRLP_STS_WCNT_SHIFT 23 +#define PDMA0_CORE_PWRLP_STS_WCNT_MASK 0x3F800000 +#define PDMA0_CORE_PWRLP_STS_RFULL_SHIFT 30 +#define PDMA0_CORE_PWRLP_STS_RFULL_MASK 0x40000000 +#define PDMA0_CORE_PWRLP_STS_WFULL_SHIFT 31 +#define PDMA0_CORE_PWRLP_STS_WFULL_MASK 0x80000000 + +/* PDMA0_CORE_DBG_DESC_CNT */ +#define PDMA0_CORE_DBG_DESC_CNT_VAL_SHIFT 0 +#define PDMA0_CORE_DBG_DESC_CNT_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_DBG_STS */ +#define PDMA0_CORE_DBG_STS_RD_CTX_FULL_SHIFT 0 +#define PDMA0_CORE_DBG_STS_RD_CTX_FULL_MASK 0x1 +#define PDMA0_CORE_DBG_STS_WR_CTX_FULL_SHIFT 1 +#define PDMA0_CORE_DBG_STS_WR_CTX_FULL_MASK 0x2 +#define PDMA0_CORE_DBG_STS_WR_COMP_FULL_SHIFT 2 +#define PDMA0_CORE_DBG_STS_WR_COMP_FULL_MASK 0x4 +#define PDMA0_CORE_DBG_STS_RD_CTX_EMPTY_SHIFT 3 +#define PDMA0_CORE_DBG_STS_RD_CTX_EMPTY_MASK 0x8 +#define PDMA0_CORE_DBG_STS_WR_CTX_EMPTY_SHIFT 4 +#define PDMA0_CORE_DBG_STS_WR_CTX_EMPTY_MASK 0x10 +#define PDMA0_CORE_DBG_STS_WR_COMP_EMPTY_SHIFT 5 +#define PDMA0_CORE_DBG_STS_WR_COMP_EMPTY_MASK 0x20 +#define PDMA0_CORE_DBG_STS_TE_EMPTY_SHIFT 6 +#define PDMA0_CORE_DBG_STS_TE_EMPTY_MASK 0x40 +#define PDMA0_CORE_DBG_STS_TE_BUSY_SHIFT 7 +#define PDMA0_CORE_DBG_STS_TE_BUSY_MASK 0x80 +#define PDMA0_CORE_DBG_STS_GSKT_EMPTY_SHIFT 8 +#define PDMA0_CORE_DBG_STS_GSKT_EMPTY_MASK 0x100 +#define PDMA0_CORE_DBG_STS_GSKT_FULL_SHIFT 9 +#define PDMA0_CORE_DBG_STS_GSKT_FULL_MASK 0x200 +#define PDMA0_CORE_DBG_STS_RD_AGU_CS_SHIFT 10 +#define PDMA0_CORE_DBG_STS_RD_AGU_CS_MASK 0x400 +#define PDMA0_CORE_DBG_STS_WR_AGU_CS_SHIFT 11 +#define PDMA0_CORE_DBG_STS_WR_AGU_CS_MASK 0x800 + +/* PDMA0_CORE_DBG_BUF_STS */ +#define PDMA0_CORE_DBG_BUF_STS_HBW_FULLNESS_SHIFT 0 +#define PDMA0_CORE_DBG_BUF_STS_HBW_FULLNESS_MASK 0xFFF +#define PDMA0_CORE_DBG_BUF_STS_LBW_FULLNESS_SHIFT 16 +#define PDMA0_CORE_DBG_BUF_STS_LBW_FULLNESS_MASK 0xFFF0000 + +/* PDMA0_CORE_DBG_RD_DESC_ID */ +#define PDMA0_CORE_DBG_RD_DESC_ID_VAL_SHIFT 0 +#define PDMA0_CORE_DBG_RD_DESC_ID_VAL_MASK 0xFFFF + +/* PDMA0_CORE_DBG_WR_DESC_ID */ +#define PDMA0_CORE_DBG_WR_DESC_ID_VAL_SHIFT 0 +#define PDMA0_CORE_DBG_WR_DESC_ID_VAL_MASK 0xFFFF + +/* PDMA0_CORE_APB_DMA_LBW_BASE */ +#define PDMA0_CORE_APB_DMA_LBW_BASE_VAL_SHIFT 0 +#define PDMA0_CORE_APB_DMA_LBW_BASE_VAL_MASK 0xFFFF + +/* PDMA0_CORE_APB_MSTR_IF_LBW_BASE */ +#define PDMA0_CORE_APB_MSTR_IF_LBW_BASE_VAL_SHIFT 0 +#define PDMA0_CORE_APB_MSTR_IF_LBW_BASE_VAL_MASK 0xFFFF + +/* PDMA0_CORE_E2E_CRED_ASYNC_CFG */ +#define PDMA0_CORE_E2E_CRED_ASYNC_CFG_Y_X_FORCE_SHIFT 0 +#define PDMA0_CORE_E2E_CRED_ASYNC_CFG_Y_X_FORCE_MASK 0x1FF +#define PDMA0_CORE_E2E_CRED_ASYNC_CFG_FORCE_EN_SHIFT 9 +#define PDMA0_CORE_E2E_CRED_ASYNC_CFG_FORCE_EN_MASK 0x200 + +/* PDMA0_CORE_DBG_APB_ENABLER */ +#define PDMA0_CORE_DBG_APB_ENABLER_DIS_SHIFT 0 +#define PDMA0_CORE_DBG_APB_ENABLER_DIS_MASK 0x1 + +/* PDMA0_CORE_L2H_CMPR_LO */ +#define PDMA0_CORE_L2H_CMPR_LO_VAL_SHIFT 20 +#define PDMA0_CORE_L2H_CMPR_LO_VAL_MASK 0xFFF00000 + +/* PDMA0_CORE_L2H_CMPR_HI */ +#define PDMA0_CORE_L2H_CMPR_HI_VAL_SHIFT 0 +#define PDMA0_CORE_L2H_CMPR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_L2H_MASK_LO */ +#define PDMA0_CORE_L2H_MASK_LO_VAL_SHIFT 20 +#define PDMA0_CORE_L2H_MASK_LO_VAL_MASK 0xFFF00000 + +/* PDMA0_CORE_L2H_MASK_HI */ +#define PDMA0_CORE_L2H_MASK_HI_VAL_SHIFT 0 +#define PDMA0_CORE_L2H_MASK_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_IDLE_IND_MASK */ +#define PDMA0_CORE_IDLE_IND_MASK_DESC_SHIFT 0 +#define PDMA0_CORE_IDLE_IND_MASK_DESC_MASK 0x1 +#define PDMA0_CORE_IDLE_IND_MASK_COMP_SHIFT 1 +#define PDMA0_CORE_IDLE_IND_MASK_COMP_MASK 0x2 +#define PDMA0_CORE_IDLE_IND_MASK_INSTAGE_SHIFT 2 +#define PDMA0_CORE_IDLE_IND_MASK_INSTAGE_MASK 0x4 +#define PDMA0_CORE_IDLE_IND_MASK_CORE_SHIFT 3 +#define PDMA0_CORE_IDLE_IND_MASK_CORE_MASK 0x8 +#define PDMA0_CORE_IDLE_IND_MASK_DESC_CNT_STS_SHIFT 8 +#define PDMA0_CORE_IDLE_IND_MASK_DESC_CNT_STS_MASK 0x1F00 +#define PDMA0_CORE_IDLE_IND_MASK_COMP_CNT_STS_SHIFT 16 +#define PDMA0_CORE_IDLE_IND_MASK_COMP_CNT_STS_MASK 0x1F0000 +#define PDMA0_CORE_IDLE_IND_MASK_INSTAGE_EMPTY_SHIFT 24 +#define PDMA0_CORE_IDLE_IND_MASK_INSTAGE_EMPTY_MASK 0x1000000 +#define PDMA0_CORE_IDLE_IND_MASK_CORE_IDLE_STS_SHIFT 25 +#define PDMA0_CORE_IDLE_IND_MASK_CORE_IDLE_STS_MASK 0x2000000 + +/* PDMA0_CORE_APB_ENABLER */ +#define PDMA0_CORE_APB_ENABLER_DIS_SHIFT 0 +#define PDMA0_CORE_APB_ENABLER_DIS_MASK 0x1 + +#endif /* ASIC_REG_PDMA0_CORE_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_regs.h new file mode 100644 index 000000000000..84079b5077e2 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_regs.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA0_CORE_REGS_H_ +#define ASIC_REG_PDMA0_CORE_REGS_H_ + +/* + ***************************************** + * PDMA0_CORE + * (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmPDMA0_CORE_CFG_0 0x4C8B000 + +#define mmPDMA0_CORE_CFG_1 0x4C8B004 + +#define mmPDMA0_CORE_PROT 0x4C8B008 + +#define mmPDMA0_CORE_CKG 0x4C8B00C + +#define mmPDMA0_CORE_RD_GLBL 0x4C8B07C + +#define mmPDMA0_CORE_RD_HBW_MAX_OUTSTAND 0x4C8B080 + +#define mmPDMA0_CORE_RD_HBW_MAX_SIZE 0x4C8B084 + +#define mmPDMA0_CORE_RD_HBW_ARCACHE 0x4C8B088 + +#define mmPDMA0_CORE_RD_HBW_INFLIGHTS 0x4C8B090 + +#define mmPDMA0_CORE_RD_HBW_RATE_LIM_CFG 0x4C8B094 + +#define mmPDMA0_CORE_RD_LBW_MAX_OUTSTAND 0x4C8B0C0 + +#define mmPDMA0_CORE_RD_LBW_MAX_SIZE 0x4C8B0C4 + +#define mmPDMA0_CORE_RD_LBW_ARCACHE 0x4C8B0C8 + +#define mmPDMA0_CORE_RD_LBW_INFLIGHTS 0x4C8B0D0 + +#define mmPDMA0_CORE_RD_LBW_RATE_LIM_CFG 0x4C8B0D4 + +#define mmPDMA0_CORE_WR_HBW_MAX_OUTSTAND 0x4C8B100 + +#define mmPDMA0_CORE_WR_HBW_MAX_AWID 0x4C8B104 + +#define mmPDMA0_CORE_WR_HBW_AWCACHE 0x4C8B108 + +#define mmPDMA0_CORE_WR_HBW_INFLIGHTS 0x4C8B10C + +#define mmPDMA0_CORE_WR_HBW_RATE_LIM_CFG 0x4C8B110 + +#define mmPDMA0_CORE_WR_LBW_MAX_OUTSTAND 0x4C8B140 + +#define mmPDMA0_CORE_WR_LBW_MAX_AWID 0x4C8B144 + +#define mmPDMA0_CORE_WR_LBW_AWCACHE 0x4C8B148 + +#define mmPDMA0_CORE_WR_LBW_INFLIGHTS 0x4C8B14C + +#define mmPDMA0_CORE_WR_LBW_RATE_LIM_CFG 0x4C8B150 + +#define mmPDMA0_CORE_WR_COMP_MAX_OUTSTAND 0x4C8B180 + +#define mmPDMA0_CORE_WR_COMP_AWUSER 0x4C8B184 + +#define mmPDMA0_CORE_ERR_CFG 0x4C8B300 + +#define mmPDMA0_CORE_ERR_CAUSE 0x4C8B304 + +#define mmPDMA0_CORE_ERRMSG_ADDR_LO 0x4C8B308 + +#define mmPDMA0_CORE_ERRMSG_ADDR_HI 0x4C8B30C + +#define mmPDMA0_CORE_ERRMSG_WDATA 0x4C8B310 + +#define mmPDMA0_CORE_STS0 0x4C8B380 + +#define mmPDMA0_CORE_STS1 0x4C8B384 + +#define mmPDMA0_CORE_STS_RD_CTX_SEL 0x4C8B400 + +#define mmPDMA0_CORE_STS_RD_CTX_SIZE 0x4C8B404 + +#define mmPDMA0_CORE_STS_RD_CTX_BASE_LO 0x4C8B408 + +#define mmPDMA0_CORE_STS_RD_CTX_BASE_HI 0x4C8B40C + +#define mmPDMA0_CORE_STS_RD_CTX_ID 0x4C8B410 + +#define mmPDMA0_CORE_STS_RD_HB_AXI_ADDR_LO 0x4C8B414 + +#define mmPDMA0_CORE_STS_RD_HB_AXI_ADDR_HI 0x4C8B418 + +#define mmPDMA0_CORE_STS_RD_LB_AXI_ADDR 0x4C8B41C + +#define mmPDMA0_CORE_STS_WR_CTX_SEL 0x4C8B420 + +#define mmPDMA0_CORE_STS_WR_CTX_SIZE 0x4C8B424 + +#define mmPDMA0_CORE_STS_WR_CTX_BASE_LO 0x4C8B428 + +#define mmPDMA0_CORE_STS_WR_CTX_BASE_HI 0x4C8B42C + +#define mmPDMA0_CORE_STS_WR_CTX_ID 0x4C8B430 + +#define mmPDMA0_CORE_STS_WR_HB_AXI_ADDR_LO 0x4C8B434 + +#define mmPDMA0_CORE_STS_WR_HB_AXI_ADDR_HI 0x4C8B438 + +#define mmPDMA0_CORE_STS_WR_LB_AXI_ADDR 0x4C8B43C + +#define mmPDMA0_CORE_PWRLP_CFG 0x4C8B700 + +#define mmPDMA0_CORE_PWRLP_STS 0x4C8B704 + +#define mmPDMA0_CORE_DBG_DESC_CNT 0x4C8B710 + +#define mmPDMA0_CORE_DBG_STS 0x4C8B714 + +#define mmPDMA0_CORE_DBG_BUF_STS 0x4C8B718 + +#define mmPDMA0_CORE_DBG_RD_DESC_ID 0x4C8B720 + +#define mmPDMA0_CORE_DBG_WR_DESC_ID 0x4C8B724 + +#define mmPDMA0_CORE_APB_DMA_LBW_BASE 0x4C8B728 + +#define mmPDMA0_CORE_APB_MSTR_IF_LBW_BASE 0x4C8B72C + +#define mmPDMA0_CORE_E2E_CRED_ASYNC_CFG 0x4C8B730 + +#define mmPDMA0_CORE_DBG_APB_ENABLER 0x4C8BE1C + +#define mmPDMA0_CORE_L2H_CMPR_LO 0x4C8BE20 + +#define mmPDMA0_CORE_L2H_CMPR_HI 0x4C8BE24 + +#define mmPDMA0_CORE_L2H_MASK_LO 0x4C8BE28 + +#define mmPDMA0_CORE_L2H_MASK_HI 0x4C8BE2C + +#define mmPDMA0_CORE_IDLE_IND_MASK 0x4C8BE30 + +#define mmPDMA0_CORE_APB_ENABLER 0x4C8BE34 + +#endif /* ASIC_REG_PDMA0_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_special_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_special_masks.h new file mode 100644 index 000000000000..15d257e3830e --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_core_special_masks.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA0_CORE_SPECIAL_MASKS_H_ +#define ASIC_REG_PDMA0_CORE_SPECIAL_MASKS_H_ + +/* + ***************************************** + * PDMA0_CORE_SPECIAL + * (Prototype: SPECIAL_REGS) + ***************************************** + */ + +/* PDMA0_CORE_SPECIAL_GLBL_PRIV */ +#define PDMA0_CORE_SPECIAL_GLBL_PRIV_VAL_SHIFT 0 +#define PDMA0_CORE_SPECIAL_GLBL_PRIV_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_SPECIAL_MEM_GW_DATA */ +#define PDMA0_CORE_SPECIAL_MEM_GW_DATA_VAL_SHIFT 0 +#define PDMA0_CORE_SPECIAL_MEM_GW_DATA_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_SPECIAL_MEM_GW_REQ */ +#define PDMA0_CORE_SPECIAL_MEM_GW_REQ_ADDR_SHIFT 0 +#define PDMA0_CORE_SPECIAL_MEM_GW_REQ_ADDR_MASK 0x3FFFFF +#define PDMA0_CORE_SPECIAL_MEM_GW_REQ_MID_SHIFT 22 +#define PDMA0_CORE_SPECIAL_MEM_GW_REQ_MID_MASK 0x3FC00000 +#define PDMA0_CORE_SPECIAL_MEM_GW_REQ_WNR_SHIFT 30 +#define PDMA0_CORE_SPECIAL_MEM_GW_REQ_WNR_MASK 0x40000000 +#define PDMA0_CORE_SPECIAL_MEM_GW_REQ_VLD_SHIFT 31 +#define PDMA0_CORE_SPECIAL_MEM_GW_REQ_VLD_MASK 0x80000000 + +/* PDMA0_CORE_SPECIAL_MEM_NUMOF */ +#define PDMA0_CORE_SPECIAL_MEM_NUMOF_VAL_SHIFT 0 +#define PDMA0_CORE_SPECIAL_MEM_NUMOF_VAL_MASK 0xFF + +/* PDMA0_CORE_SPECIAL_MEM_ECC_SEL */ +#define PDMA0_CORE_SPECIAL_MEM_ECC_SEL_VAL_SHIFT 0 +#define PDMA0_CORE_SPECIAL_MEM_ECC_SEL_VAL_MASK 0xFF + +/* PDMA0_CORE_SPECIAL_MEM_ECC_CTL */ +#define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_INJ_SHIFT 0 +#define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_INJ_MASK 0x1 +#define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_DERR_INJ_SHIFT 1 +#define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_DERR_INJ_MASK 0x2 +#define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_CLR_SHIFT 2 +#define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_CLR_MASK 0x4 +#define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_DERR_CLR_SHIFT 3 +#define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_DERR_CLR_MASK 0x8 + +/* PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK */ +#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_SERR_SHIFT 0 +#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_SERR_MASK 0x1 +#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_DERR_SHIFT 1 +#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_DERR_MASK 0x2 + +/* PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK */ +#define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_SERR_SHIFT 0 +#define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_SERR_MASK 0x1 +#define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_DERR_SHIFT 1 +#define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_DERR_MASK 0x2 + +/* PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS */ +#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_SYND_SHIFT 0 +#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_SYND_MASK 0xFFFF +#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_SERR_SHIFT 16 +#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_SERR_MASK 0x10000 +#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_DERR_SHIFT 17 +#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_DERR_MASK 0x20000 + +/* PDMA0_CORE_SPECIAL_MEM_ECC_ERR_ADDR */ +#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_ADDR_VAL_SHIFT 0 +#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_ADDR_VAL_MASK 0xFFFF + +/* PDMA0_CORE_SPECIAL_MEM_RM */ +#define PDMA0_CORE_SPECIAL_MEM_RM_VAL_SHIFT 0 +#define PDMA0_CORE_SPECIAL_MEM_RM_VAL_MASK 0x3FFFFFFF + +/* PDMA0_CORE_SPECIAL_GLBL_ERR_MASK */ +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_RD_SHIFT 0 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_RD_MASK 0x1 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_SEC_RD_SHIFT 1 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_SEC_RD_MASK 0x2 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_RD_SHIFT 2 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_RD_MASK 0x4 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_WR_SHIFT 3 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_WR_MASK 0x8 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_SEC_WR_SHIFT 4 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_SEC_WR_MASK 0x10 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_WR_SHIFT 5 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_WR_MASK 0x20 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_EXT_SEC_WR_SHIFT 16 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_EXT_SEC_WR_MASK 0x10000 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_EXT_UNMAPPED_WR_SHIFT 17 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_EXT_UNMAPPED_WR_MASK 0x20000 + +/* PDMA0_CORE_SPECIAL_GLBL_ERR_ADDR */ +#define PDMA0_CORE_SPECIAL_GLBL_ERR_ADDR_VAL_SHIFT 0 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_ADDR_VAL_MASK 0xFFFFFFFF + +/* PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE */ +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_SHIFT 0 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_MASK 0x1 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD_SHIFT 1 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD_MASK 0x2 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD_SHIFT 2 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD_MASK 0x4 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR_SHIFT 3 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR_MASK 0x8 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR_SHIFT 4 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR_MASK 0x10 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR_SHIFT 5 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR_MASK 0x20 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR_SHIFT 16 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR_MASK 0x10000 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR_SHIFT 17 +#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR_MASK 0x20000 + +/* PDMA0_CORE_SPECIAL_GLBL_SPARE */ +#define PDMA0_CORE_SPECIAL_GLBL_SPARE_R_SHIFT 0 +#define PDMA0_CORE_SPECIAL_GLBL_SPARE_R_MASK 0xFFFFFFFF + +/* PDMA0_CORE_SPECIAL_GLBL_SEC */ +#define PDMA0_CORE_SPECIAL_GLBL_SEC_VAL_SHIFT 0 +#define PDMA0_CORE_SPECIAL_GLBL_SEC_VAL_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_PDMA0_CORE_SPECIAL_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_arc_aux_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_arc_aux_regs.h new file mode 100644 index 000000000000..9b1cb609d134 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_arc_aux_regs.h @@ -0,0 +1,591 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA0_QM_ARC_AUX_REGS_H_ +#define ASIC_REG_PDMA0_QM_ARC_AUX_REGS_H_ + +/* + ***************************************** + * PDMA0_QM_ARC_AUX + * (Prototype: QMAN_ARC_AUX) + ***************************************** + */ + +#define mmPDMA0_QM_ARC_AUX_RUN_HALT_REQ 0x4C88100 + +#define mmPDMA0_QM_ARC_AUX_RUN_HALT_ACK 0x4C88104 + +#define mmPDMA0_QM_ARC_AUX_RST_VEC_ADDR 0x4C88108 + +#define mmPDMA0_QM_ARC_AUX_DBG_MODE 0x4C8810C + +#define mmPDMA0_QM_ARC_AUX_CLUSTER_NUM 0x4C88110 + +#define mmPDMA0_QM_ARC_AUX_ARC_NUM 0x4C88114 + +#define mmPDMA0_QM_ARC_AUX_WAKE_UP_EVENT 0x4C88118 + +#define mmPDMA0_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x4C8811C + +#define mmPDMA0_QM_ARC_AUX_CTI_AP_STS 0x4C88120 + +#define mmPDMA0_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x4C88124 + +#define mmPDMA0_QM_ARC_AUX_ARC_RST 0x4C88128 + +#define mmPDMA0_QM_ARC_AUX_ARC_RST_REQ 0x4C8812C + +#define mmPDMA0_QM_ARC_AUX_SRAM_LSB_ADDR 0x4C88130 + +#define mmPDMA0_QM_ARC_AUX_SRAM_MSB_ADDR 0x4C88134 + +#define mmPDMA0_QM_ARC_AUX_PCIE_LSB_ADDR 0x4C88138 + +#define mmPDMA0_QM_ARC_AUX_PCIE_MSB_ADDR 0x4C8813C + +#define mmPDMA0_QM_ARC_AUX_CFG_LSB_ADDR 0x4C88140 + +#define mmPDMA0_QM_ARC_AUX_CFG_MSB_ADDR 0x4C88144 + +#define mmPDMA0_QM_ARC_AUX_HBM0_LSB_ADDR 0x4C88150 + +#define mmPDMA0_QM_ARC_AUX_HBM0_MSB_ADDR 0x4C88154 + +#define mmPDMA0_QM_ARC_AUX_HBM1_LSB_ADDR 0x4C88158 + +#define mmPDMA0_QM_ARC_AUX_HBM1_MSB_ADDR 0x4C8815C + +#define mmPDMA0_QM_ARC_AUX_HBM2_LSB_ADDR 0x4C88160 + +#define mmPDMA0_QM_ARC_AUX_HBM2_MSB_ADDR 0x4C88164 + +#define mmPDMA0_QM_ARC_AUX_HBM3_LSB_ADDR 0x4C88168 + +#define mmPDMA0_QM_ARC_AUX_HBM3_MSB_ADDR 0x4C8816C + +#define mmPDMA0_QM_ARC_AUX_HBM0_OFFSET 0x4C88170 + +#define mmPDMA0_QM_ARC_AUX_HBM1_OFFSET 0x4C88174 + +#define mmPDMA0_QM_ARC_AUX_HBM2_OFFSET 0x4C88178 + +#define mmPDMA0_QM_ARC_AUX_HBM3_OFFSET 0x4C8817C + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x4C88180 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x4C88184 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x4C88188 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x4C8818C + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x4C88190 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x4C88194 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x4C88198 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x4C8819C + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x4C881A0 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x4C881A4 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x4C881A8 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x4C881AC + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x4C881B0 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x4C881B4 + +#define mmPDMA0_QM_ARC_AUX_ARC_CBU_AWCACHE_OVR 0x4C881B8 + +#define mmPDMA0_QM_ARC_AUX_ARC_LBU_AWCACHE_OVR 0x4C881BC + +#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_0 0x4C881C0 + +#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_1 0x4C881C4 + +#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_2 0x4C881C8 + +#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_3 0x4C881CC + +#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_4 0x4C881D0 + +#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_5 0x4C881D4 + +#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_6 0x4C881D8 + +#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_7 0x4C881DC + +#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_0 0x4C881E0 + +#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_1 0x4C881E4 + +#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_2 0x4C881E8 + +#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_3 0x4C881EC + +#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_4 0x4C881F0 + +#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_5 0x4C881F4 + +#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_6 0x4C881F8 + +#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_7 0x4C881FC + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_0 0x4C88200 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_1 0x4C88204 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_2 0x4C88208 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_3 0x4C8820C + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_4 0x4C88210 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_5 0x4C88214 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_6 0x4C88218 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_7 0x4C8821C + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_8 0x4C88220 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_9 0x4C88224 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_10 0x4C88228 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_11 0x4C8822C + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_12 0x4C88230 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_13 0x4C88234 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_14 0x4C88238 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_15 0x4C8823C + +#define mmPDMA0_QM_ARC_AUX_IRQ_INTR_MASK_0 0x4C88280 + +#define mmPDMA0_QM_ARC_AUX_IRQ_INTR_MASK_1 0x4C88284 + +#define mmPDMA0_QM_ARC_AUX_ARC_SEI_INTR_STS 0x4C88290 + +#define mmPDMA0_QM_ARC_AUX_ARC_SEI_INTR_CLR 0x4C88294 + +#define mmPDMA0_QM_ARC_AUX_ARC_SEI_INTR_MASK 0x4C88298 + +#define mmPDMA0_QM_ARC_AUX_ARC_EXCPTN_CAUSE 0x4C8829C + +#define mmPDMA0_QM_ARC_AUX_SEI_INTR_HALT_EN 0x4C882A0 + +#define mmPDMA0_QM_ARC_AUX_ARC_SEI_INTR_HALT_MASK 0x4C882A4 + +#define mmPDMA0_QM_ARC_AUX_QMAN_SEI_INTR_HALT_MASK 0x4C882A8 + +#define mmPDMA0_QM_ARC_AUX_ARC_REI_INTR_STS 0x4C882B0 + +#define mmPDMA0_QM_ARC_AUX_ARC_REI_INTR_CLR 0x4C882B4 + +#define mmPDMA0_QM_ARC_AUX_ARC_REI_INTR_MASK 0x4C882B8 + +#define mmPDMA0_QM_ARC_AUX_DCCM_ECC_ERR_ADDR 0x4C882BC + +#define mmPDMA0_QM_ARC_AUX_DCCM_ECC_SYNDROME 0x4C882C0 + +#define mmPDMA0_QM_ARC_AUX_I_CACHE_ECC_ERR_ADDR 0x4C882C4 + +#define mmPDMA0_QM_ARC_AUX_I_CACHE_ECC_SYNDROME 0x4C882C8 + +#define mmPDMA0_QM_ARC_AUX_D_CACHE_ECC_ERR_ADDR 0x4C882CC + +#define mmPDMA0_QM_ARC_AUX_D_CACHE_ECC_SYNDROME 0x4C882D0 + +#define mmPDMA0_QM_ARC_AUX_LBW_TRMINATE_AWADDR_ERR 0x4C882E0 + +#define mmPDMA0_QM_ARC_AUX_LBW_TRMINATE_ARADDR_ERR 0x4C882E4 + +#define mmPDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_BRESP 0x4C882E8 + +#define mmPDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_RRESP 0x4C882EC + +#define mmPDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXLEN 0x4C882F0 + +#define mmPDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXSIZE 0x4C882F4 + +#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_0 0x4C88300 + +#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_1 0x4C88304 + +#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_2 0x4C88308 + +#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_3 0x4C8830C + +#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_4 0x4C88310 + +#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_5 0x4C88314 + +#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_6 0x4C88318 + +#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_7 0x4C8831C + +#define mmPDMA0_QM_ARC_AUX_TOTAL_CBU_WR_CNT 0x4C88320 + +#define mmPDMA0_QM_ARC_AUX_INFLIGHT_CBU_WR_CNT 0x4C88324 + +#define mmPDMA0_QM_ARC_AUX_TOTAL_CBU_RD_CNT 0x4C88328 + +#define mmPDMA0_QM_ARC_AUX_INFLIGHT_CBU_RD_CNT 0x4C8832C + +#define mmPDMA0_QM_ARC_AUX_TOTAL_LBU_WR_CNT 0x4C88330 + +#define mmPDMA0_QM_ARC_AUX_INFLIGHT_LBU_WR_CNT 0x4C88334 + +#define mmPDMA0_QM_ARC_AUX_TOTAL_LBU_RD_CNT 0x4C88338 + +#define mmPDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT 0x4C8833C + +#define mmPDMA0_QM_ARC_AUX_CBU_ARUSER_OVR 0x4C88350 + +#define mmPDMA0_QM_ARC_AUX_CBU_ARUSER_OVR_EN 0x4C88354 + +#define mmPDMA0_QM_ARC_AUX_CBU_AWUSER_OVR 0x4C88358 + +#define mmPDMA0_QM_ARC_AUX_CBU_AWUSER_OVR_EN 0x4C8835C + +#define mmPDMA0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR 0x4C88360 + +#define mmPDMA0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR_EN 0x4C88364 + +#define mmPDMA0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR 0x4C88368 + +#define mmPDMA0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR_EN 0x4C8836C + +#define mmPDMA0_QM_ARC_AUX_CBU_AXCACHE_OVR 0x4C88370 + +#define mmPDMA0_QM_ARC_AUX_CBU_LOCK_OVR 0x4C88374 + +#define mmPDMA0_QM_ARC_AUX_CBU_PROT_OVR 0x4C88378 + +#define mmPDMA0_QM_ARC_AUX_CBU_MAX_OUTSTANDING 0x4C8837C + +#define mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN 0x4C88380 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORCE_RSP_OK 0x4C88384 + +#define mmPDMA0_QM_ARC_AUX_CBU_NO_WR_INFLIGHT 0x4C8838C + +#define mmPDMA0_QM_ARC_AUX_CBU_SEI_INTR_ID 0x4C88390 + +#define mmPDMA0_QM_ARC_AUX_LBU_ARUSER_OVR 0x4C88400 + +#define mmPDMA0_QM_ARC_AUX_LBU_ARUSER_OVR_EN 0x4C88404 + +#define mmPDMA0_QM_ARC_AUX_LBU_AWUSER_OVR 0x4C88408 + +#define mmPDMA0_QM_ARC_AUX_LBU_AWUSER_OVR_EN 0x4C8840C + +#define mmPDMA0_QM_ARC_AUX_LBU_AXCACHE_OVR 0x4C88420 + +#define mmPDMA0_QM_ARC_AUX_LBU_LOCK_OVR 0x4C88424 + +#define mmPDMA0_QM_ARC_AUX_LBU_PROT_OVR 0x4C88428 + +#define mmPDMA0_QM_ARC_AUX_LBU_MAX_OUTSTANDING 0x4C8842C + +#define mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN 0x4C88430 + +#define mmPDMA0_QM_ARC_AUX_LBU_FORCE_RSP_OK 0x4C88434 + +#define mmPDMA0_QM_ARC_AUX_LBU_NO_WR_INFLIGHT 0x4C8843C + +#define mmPDMA0_QM_ARC_AUX_LBU_SEI_INTR_ID 0x4C88440 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0 0x4C88500 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_1 0x4C88504 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_2 0x4C88508 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_3 0x4C8850C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_4 0x4C88510 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_5 0x4C88514 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_6 0x4C88518 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_7 0x4C8851C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_0 0x4C88520 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_1 0x4C88524 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_2 0x4C88528 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_3 0x4C8852C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_4 0x4C88530 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_5 0x4C88534 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_6 0x4C88538 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_7 0x4C8853C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_0 0x4C88540 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_1 0x4C88544 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_2 0x4C88548 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_3 0x4C8854C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_4 0x4C88550 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_5 0x4C88554 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_6 0x4C88558 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_7 0x4C8855C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_0 0x4C88560 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_1 0x4C88564 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_2 0x4C88568 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_3 0x4C8856C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_4 0x4C88570 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_5 0x4C88574 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_6 0x4C88578 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_7 0x4C8857C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_0 0x4C88580 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_1 0x4C88584 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_2 0x4C88588 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_3 0x4C8858C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_4 0x4C88590 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_5 0x4C88594 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_6 0x4C88598 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_7 0x4C8859C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x4C885A0 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x4C885A4 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x4C885A8 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x4C885AC + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x4C885B0 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x4C885B4 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x4C885B8 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x4C885BC + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x4C885C0 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x4C885C4 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x4C885C8 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x4C885CC + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x4C885D0 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x4C885D4 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x4C885D8 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x4C885DC + +#define mmPDMA0_QM_ARC_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x4C885E0 + +#define mmPDMA0_QM_ARC_AUX_NIC_Q_VLD_ENTRY_MASK 0x4C885E4 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_DROP_EN 0x4C88620 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_WARN_MSG 0x4C88624 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG 0x4C88628 + +#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWPROT 0x4C88630 + +#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWUSER 0x4C88634 + +#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWBURST 0x4C88638 + +#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWLOCK 0x4C8863C + +#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWCACHE 0x4C88640 + +#define mmPDMA0_QM_ARC_AUX_DCCM_WRR_ARB_WEIGHT 0x4C88644 + +#define mmPDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x4C88648 + +#define mmPDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT 0x4C8864C + +#define mmPDMA0_QM_ARC_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x4C88650 + +#define mmPDMA0_QM_ARC_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x4C88654 + +#define mmPDMA0_QM_ARC_AUX_QMAN_CQ_SHADOW_CI 0x4C88658 + +#define mmPDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI 0x4C8865C + +#define mmPDMA0_QM_ARC_AUX_AUX2APB_PROT 0x4C88700 + +#define mmPDMA0_QM_ARC_AUX_LBW_FORK_WIN_EN 0x4C88704 + +#define mmPDMA0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x4C88708 + +#define mmPDMA0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x4C8870C + +#define mmPDMA0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x4C88710 + +#define mmPDMA0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x4C88714 + +#define mmPDMA0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR0 0x4C88718 + +#define mmPDMA0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK0 0x4C8871C + +#define mmPDMA0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR1 0x4C88720 + +#define mmPDMA0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK1 0x4C88724 + +#define mmPDMA0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR0 0x4C88728 + +#define mmPDMA0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR1 0x4C8872C + +#define mmPDMA0_QM_ARC_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x4C88730 + +#define mmPDMA0_QM_ARC_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x4C88734 + +#define mmPDMA0_QM_ARC_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x4C88738 + +#define mmPDMA0_QM_ARC_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x4C8873C + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_WIN_EN 0x4C88740 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_LSB 0x4C88750 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_MSB 0x4C88754 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_LSB 0x4C88758 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_MSB 0x4C8875C + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_LSB 0x4C88760 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_MSB 0x4C88764 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_LSB 0x4C88768 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_MSB 0x4C8876C + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_LSB 0x4C88770 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_MSB 0x4C88774 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_LSB 0x4C88778 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_MSB 0x4C8877C + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_LSB 0x4C88780 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_MSB 0x4C88784 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_LSB 0x4C88788 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_MSB 0x4C8878C + +#define mmPDMA0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_LSB 0x4C88790 + +#define mmPDMA0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_MSB 0x4C88794 + +#define mmPDMA0_QM_ARC_AUX_CFG_CBU_TERMINATE_BRESP 0x4C88798 + +#define mmPDMA0_QM_ARC_AUX_CFG_CBU_TERMINATE_RRESP 0x4C8879C + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_0 0x4C88800 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_1 0x4C88804 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_2 0x4C88808 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_3 0x4C8880C + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_4 0x4C88810 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_5 0x4C88814 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_6 0x4C88818 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_7 0x4C8881C + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_8 0x4C88820 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_9 0x4C88824 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_10 0x4C88828 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_11 0x4C8882C + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_12 0x4C88830 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_13 0x4C88834 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_14 0x4C88838 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_15 0x4C8883C + +#define mmPDMA0_QM_ARC_AUX_DCCM_TRMINATE_AWADDR_ERR 0x4C88840 + +#define mmPDMA0_QM_ARC_AUX_DCCM_TRMINATE_ARADDR_ERR 0x4C88844 + +#define mmPDMA0_QM_ARC_AUX_CFG_DCCM_TERMINATE_BRESP 0x4C88848 + +#define mmPDMA0_QM_ARC_AUX_CFG_DCCM_TERMINATE_RRESP 0x4C8884C + +#define mmPDMA0_QM_ARC_AUX_CFG_DCCM_TERMINATE_EN 0x4C88850 + +#define mmPDMA0_QM_ARC_AUX_CFG_DCCM_SECURE_REGION 0x4C88854 + +#define mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x4C88900 + +#define mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_CTL 0x4C88904 + +#define mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x4C88908 + +#define mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR 0x4C8890C + +#define mmPDMA0_QM_ARC_AUX_ARC_ACC_ENGS_BUSER 0x4C88910 + +#define mmPDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN 0x4C88920 + +#endif /* ASIC_REG_PDMA0_QM_ARC_AUX_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_axuser_nonsecured_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_axuser_nonsecured_regs.h new file mode 100644 index 000000000000..d2e0756ec5f2 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_axuser_nonsecured_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA0_QM_AXUSER_NONSECURED_REGS_H_ +#define ASIC_REG_PDMA0_QM_AXUSER_NONSECURED_REGS_H_ + +/* + ***************************************** + * PDMA0_QM_AXUSER_NONSECURED + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_ASID 0x4C8AB80 + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_MMU_BP 0x4C8AB84 + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x4C8AB88 + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x4C8AB8C + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x4C8AB90 + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x4C8AB94 + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_QOS 0x4C8AB98 + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_RSVD 0x4C8AB9C + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x4C8ABA0 + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_CORE 0x4C8ABA4 + +#define mmPDMA0_QM_AXUSER_NONSECURED_E2E_COORD 0x4C8ABA8 + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x4C8ABB0 + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x4C8ABB4 + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x4C8ABB8 + +#define mmPDMA0_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x4C8ABBC + +#define mmPDMA0_QM_AXUSER_NONSECURED_LB_COORD 0x4C8ABC0 + +#define mmPDMA0_QM_AXUSER_NONSECURED_LB_LOCK 0x4C8ABC4 + +#define mmPDMA0_QM_AXUSER_NONSECURED_LB_RSVD 0x4C8ABC8 + +#define mmPDMA0_QM_AXUSER_NONSECURED_LB_OVRD 0x4C8ABCC + +#endif /* ASIC_REG_PDMA0_QM_AXUSER_NONSECURED_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_axuser_secured_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_axuser_secured_regs.h new file mode 100644 index 000000000000..8bf0516b83f7 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_axuser_secured_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA0_QM_AXUSER_SECURED_REGS_H_ +#define ASIC_REG_PDMA0_QM_AXUSER_SECURED_REGS_H_ + +/* + ***************************************** + * PDMA0_QM_AXUSER_SECURED + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmPDMA0_QM_AXUSER_SECURED_HB_ASID 0x4C8AB00 + +#define mmPDMA0_QM_AXUSER_SECURED_HB_MMU_BP 0x4C8AB04 + +#define mmPDMA0_QM_AXUSER_SECURED_HB_STRONG_ORDER 0x4C8AB08 + +#define mmPDMA0_QM_AXUSER_SECURED_HB_NO_SNOOP 0x4C8AB0C + +#define mmPDMA0_QM_AXUSER_SECURED_HB_WR_REDUCTION 0x4C8AB10 + +#define mmPDMA0_QM_AXUSER_SECURED_HB_RD_ATOMIC 0x4C8AB14 + +#define mmPDMA0_QM_AXUSER_SECURED_HB_QOS 0x4C8AB18 + +#define mmPDMA0_QM_AXUSER_SECURED_HB_RSVD 0x4C8AB1C + +#define mmPDMA0_QM_AXUSER_SECURED_HB_EMEM_CPAGE 0x4C8AB20 + +#define mmPDMA0_QM_AXUSER_SECURED_HB_CORE 0x4C8AB24 + +#define mmPDMA0_QM_AXUSER_SECURED_E2E_COORD 0x4C8AB28 + +#define mmPDMA0_QM_AXUSER_SECURED_HB_WR_OVRD_LO 0x4C8AB30 + +#define mmPDMA0_QM_AXUSER_SECURED_HB_WR_OVRD_HI 0x4C8AB34 + +#define mmPDMA0_QM_AXUSER_SECURED_HB_RD_OVRD_LO 0x4C8AB38 + +#define mmPDMA0_QM_AXUSER_SECURED_HB_RD_OVRD_HI 0x4C8AB3C + +#define mmPDMA0_QM_AXUSER_SECURED_LB_COORD 0x4C8AB40 + +#define mmPDMA0_QM_AXUSER_SECURED_LB_LOCK 0x4C8AB44 + +#define mmPDMA0_QM_AXUSER_SECURED_LB_RSVD 0x4C8AB48 + +#define mmPDMA0_QM_AXUSER_SECURED_LB_OVRD 0x4C8AB4C + +#endif /* ASIC_REG_PDMA0_QM_AXUSER_SECURED_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_cgm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_cgm_regs.h new file mode 100644 index 000000000000..96c0ce176e73 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_cgm_regs.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA0_QM_CGM_REGS_H_ +#define ASIC_REG_PDMA0_QM_CGM_REGS_H_ + +/* + ***************************************** + * PDMA0_QM_CGM + * (Prototype: QMAN_CGM) + ***************************************** + */ + +#define mmPDMA0_QM_CGM_CFG 0x4C8AD80 + +#define mmPDMA0_QM_CGM_STS 0x4C8AD84 + +#define mmPDMA0_QM_CGM_CFG1 0x4C8AD88 + +#endif /* ASIC_REG_PDMA0_QM_CGM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_masks.h new file mode 100644 index 000000000000..b79cae8f5571 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_masks.h @@ -0,0 +1,1165 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA0_QM_MASKS_H_ +#define ASIC_REG_PDMA0_QM_MASKS_H_ + +/* + ***************************************** + * PDMA0_QM + * (Prototype: QMAN) + ***************************************** + */ + +/* PDMA0_QM_GLBL_CFG0 */ +#define PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0 +#define PDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF +#define PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT 4 +#define PDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0 +#define PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT 9 +#define PDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00 +#define PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT 14 +#define PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000 + +/* PDMA0_QM_GLBL_CFG1 */ +#define PDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0 +#define PDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF +#define PDMA0_QM_GLBL_CFG1_CQF_STOP_SHIFT 4 +#define PDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0 +#define PDMA0_QM_GLBL_CFG1_CP_STOP_SHIFT 9 +#define PDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00 +#define PDMA0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 16 +#define PDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000 +#define PDMA0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 20 +#define PDMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000 +#define PDMA0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 25 +#define PDMA0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000 + +/* PDMA0_QM_GLBL_CFG2 */ +#define PDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_SHIFT 0 +#define PDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_MASK 0x1 +#define PDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_SHIFT 1 +#define PDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_MASK 0x2 +#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWUSER_OVRD_SHIFT 4 +#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWUSER_OVRD_MASK 0x10 +#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARUSER_OVRD_SHIFT 5 +#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARUSER_OVRD_MASK 0x20 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWUSER_OVRD_SHIFT 6 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWUSER_OVRD_MASK 0x40 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARUSER_OVRD_SHIFT 7 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARUSER_OVRD_MASK 0x80 +#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWPROT_OVRD_SHIFT 8 +#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWPROT_OVRD_MASK 0x100 +#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARPROT_OVRD_SHIFT 9 +#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARPROT_OVRD_MASK 0x200 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWPROT_OVRD_SHIFT 10 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWPROT_OVRD_MASK 0x400 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARPROT_OVRD_SHIFT 11 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARPROT_OVRD_MASK 0x800 +#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWCACHE_OVRD_SHIFT 12 +#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWCACHE_OVRD_MASK 0x1000 +#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARCACHE_OVRD_SHIFT 13 +#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARCACHE_OVRD_MASK 0x2000 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWCACHE_OVRD_SHIFT 14 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWCACHE_OVRD_MASK 0x4000 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARCACHE_OVRD_SHIFT 15 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARCACHE_OVRD_MASK 0x8000 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_BUSER_OVRD_SHIFT 16 +#define PDMA0_QM_GLBL_CFG2_ARC_LBW_BUSER_OVRD_MASK 0x10000 + +/* PDMA0_QM_GLBL_ERR_CFG */ +#define PDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0 +#define PDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF +#define PDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 +#define PDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0 +#define PDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9 +#define PDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00 +#define PDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16 +#define PDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000 +#define PDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20 +#define PDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000 +#define PDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25 +#define PDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000 +#define PDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31 +#define PDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000 + +/* PDMA0_QM_GLBL_ERR_CFG1 */ +#define PDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_SHIFT 0 +#define PDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_MASK 0x1 +#define PDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_SHIFT 1 +#define PDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_MASK 0x2 +#define PDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_SHIFT 2 +#define PDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_MASK 0x4 + +/* PDMA0_QM_GLBL_ERR_ARC_HALT_EN */ +#define PDMA0_QM_GLBL_ERR_ARC_HALT_EN_ERR_IND_SHIFT 0 +#define PDMA0_QM_GLBL_ERR_ARC_HALT_EN_ERR_IND_MASK 0xFFFFFF + +/* PDMA0_QM_GLBL_AXCACHE */ +#define PDMA0_QM_GLBL_AXCACHE_HBW_AR_SHIFT 0 +#define PDMA0_QM_GLBL_AXCACHE_HBW_AR_MASK 0xF +#define PDMA0_QM_GLBL_AXCACHE_HBW_AW_SHIFT 16 +#define PDMA0_QM_GLBL_AXCACHE_HBW_AW_MASK 0xF0000 +#define PDMA0_QM_GLBL_AXCACHE_LBW_AW_SHIFT 20 +#define PDMA0_QM_GLBL_AXCACHE_LBW_AW_MASK 0xF00000 +#define PDMA0_QM_GLBL_AXCACHE_LBW_AR_SHIFT 24 +#define PDMA0_QM_GLBL_AXCACHE_LBW_AR_MASK 0xF000000 + +/* PDMA0_QM_GLBL_STS0 */ +#define PDMA0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0 +#define PDMA0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF +#define PDMA0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4 +#define PDMA0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0 +#define PDMA0_QM_GLBL_STS0_CP_IDLE_SHIFT 9 +#define PDMA0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00 +#define PDMA0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16 +#define PDMA0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000 +#define PDMA0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20 +#define PDMA0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000 +#define PDMA0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25 +#define PDMA0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000 +#define PDMA0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31 +#define PDMA0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000 + +/* PDMA0_QM_GLBL_STS1 */ +#define PDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_SHIFT 0 +#define PDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_MASK 0x1 +#define PDMA0_QM_GLBL_STS1_ARC_CQF_IS_STOP_SHIFT 1 +#define PDMA0_QM_GLBL_STS1_ARC_CQF_IS_STOP_MASK 0x2 + +/* PDMA0_QM_GLBL_ERR_STS */ +#define PDMA0_QM_GLBL_ERR_STS_PQF_RD_ERR_SHIFT 0 +#define PDMA0_QM_GLBL_ERR_STS_PQF_RD_ERR_MASK 0x1 +#define PDMA0_QM_GLBL_ERR_STS_CQF_RD_ERR_SHIFT 1 +#define PDMA0_QM_GLBL_ERR_STS_CQF_RD_ERR_MASK 0x2 +#define PDMA0_QM_GLBL_ERR_STS_CP_RD_ERR_SHIFT 2 +#define PDMA0_QM_GLBL_ERR_STS_CP_RD_ERR_MASK 0x4 +#define PDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_SHIFT 3 +#define PDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_MASK 0x8 +#define PDMA0_QM_GLBL_ERR_STS_CP_STOP_OP_SHIFT 4 +#define PDMA0_QM_GLBL_ERR_STS_CP_STOP_OP_MASK 0x10 +#define PDMA0_QM_GLBL_ERR_STS_CP_MSG_WR_ERR_SHIFT 5 +#define PDMA0_QM_GLBL_ERR_STS_CP_MSG_WR_ERR_MASK 0x20 +#define PDMA0_QM_GLBL_ERR_STS_CP_WREG_ERR_SHIFT 6 +#define PDMA0_QM_GLBL_ERR_STS_CP_WREG_ERR_MASK 0x40 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE0_OVF_ERR_SHIFT 8 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE0_OVF_ERR_MASK 0x100 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE1_OVF_ERR_SHIFT 9 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE1_OVF_ERR_MASK 0x200 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE2_OVF_ERR_SHIFT 10 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE2_OVF_ERR_MASK 0x400 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE3_OVF_ERR_SHIFT 11 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE3_OVF_ERR_MASK 0x800 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE0_UDF_ERR_SHIFT 12 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE1_UDF_ERR_SHIFT 13 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE2_UDF_ERR_SHIFT 14 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE3_UDF_ERR_SHIFT 15 +#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE3_UDF_ERR_MASK 0x8000 +#define PDMA0_QM_GLBL_ERR_STS_CPDMA_UP_OVF_ERR_SHIFT 16 +#define PDMA0_QM_GLBL_ERR_STS_CPDMA_UP_OVF_ERR_MASK 0x10000 +#define PDMA0_QM_GLBL_ERR_STS_PQC_L2H_ERR_SHIFT 17 +#define PDMA0_QM_GLBL_ERR_STS_PQC_L2H_ERR_MASK 0x20000 +#define PDMA0_QM_GLBL_ERR_STS_RSVD_18_24_SHIFT 18 +#define PDMA0_QM_GLBL_ERR_STS_RSVD_18_24_MASK 0x1FC0000 + +/* PDMA0_QM_GLBL_ERR_STS_4 */ +#define PDMA0_QM_GLBL_ERR_STS_4_RSVD0_SHIFT 0 +#define PDMA0_QM_GLBL_ERR_STS_4_RSVD0_MASK 0x1 +#define PDMA0_QM_GLBL_ERR_STS_4_CQF_RD_ERR_SHIFT 1 +#define PDMA0_QM_GLBL_ERR_STS_4_CQF_RD_ERR_MASK 0x2 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_RD_ERR_SHIFT 2 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_RD_ERR_MASK 0x4 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_STOP_OP_SHIFT 4 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_STOP_OP_MASK 0x10 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_MSG_WR_ERR_SHIFT 5 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_MSG_WR_ERR_MASK 0x20 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_WREG_ERR_SHIFT 6 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_WREG_ERR_MASK 0x40 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_UDF_ERR_MASK 0x8000 +#define PDMA0_QM_GLBL_ERR_STS_4_CPDMA_UP_OVF_ERR_SHIFT 16 +#define PDMA0_QM_GLBL_ERR_STS_4_CPDMA_UP_OVF_ERR_MASK 0x10000 +#define PDMA0_QM_GLBL_ERR_STS_4_RSVD17_SHIFT 17 +#define PDMA0_QM_GLBL_ERR_STS_4_RSVD17_MASK 0x20000 +#define PDMA0_QM_GLBL_ERR_STS_4_CQ_WR_IFIFO_CI_ERR_SHIFT 18 +#define PDMA0_QM_GLBL_ERR_STS_4_CQ_WR_IFIFO_CI_ERR_MASK 0x40000 +#define PDMA0_QM_GLBL_ERR_STS_4_CQ_WR_CTL_CI_ERR_SHIFT 19 +#define PDMA0_QM_GLBL_ERR_STS_4_CQ_WR_CTL_CI_ERR_MASK 0x80000 +#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQF_RD_ERR_SHIFT 20 +#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQF_RD_ERR_MASK 0x100000 +#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_IFIFO_CI_ERR_SHIFT 21 +#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_IFIFO_CI_ERR_MASK 0x200000 +#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_CTL_CI_ERR_SHIFT 22 +#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_CTL_CI_ERR_MASK 0x400000 +#define PDMA0_QM_GLBL_ERR_STS_4_ARC_AXI_ERR_SHIFT 23 +#define PDMA0_QM_GLBL_ERR_STS_4_ARC_AXI_ERR_MASK 0x800000 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_SWITCH_WDT_ERR_SHIFT 24 +#define PDMA0_QM_GLBL_ERR_STS_4_CP_SWITCH_WDT_ERR_MASK 0x1000000 + +/* PDMA0_QM_GLBL_ERR_MSG_EN */ +#define PDMA0_QM_GLBL_ERR_MSG_EN_PQF_RD_ERR_SHIFT 0 +#define PDMA0_QM_GLBL_ERR_MSG_EN_PQF_RD_ERR_MASK 0x1 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CQF_RD_ERR_SHIFT 1 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CQF_RD_ERR_MASK 0x2 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_RD_ERR_SHIFT 2 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_RD_ERR_MASK 0x4 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_STOP_OP_SHIFT 4 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_STOP_OP_MASK 0x10 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_MSG_WR_ERR_SHIFT 5 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_MSG_WR_ERR_MASK 0x20 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_WREG_ERR_SHIFT 6 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_WREG_ERR_MASK 0x40 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CPDMA_UP_OVF_ERR_SHIFT 16 +#define PDMA0_QM_GLBL_ERR_MSG_EN_CPDMA_UP_OVF_ERR_MASK 0x10000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_PQC_L2H_ERR_SHIFT 17 +#define PDMA0_QM_GLBL_ERR_MSG_EN_PQC_L2H_ERR_MASK 0x20000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_RSVD_18_24_SHIFT 18 +#define PDMA0_QM_GLBL_ERR_MSG_EN_RSVD_18_24_MASK 0x1FC0000 + +/* PDMA0_QM_GLBL_ERR_MSG_EN_4 */ +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD0_SHIFT 0 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD0_MASK 0x1 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQF_RD_ERR_SHIFT 1 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQF_RD_ERR_MASK 0x2 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_RD_ERR_SHIFT 2 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_RD_ERR_MASK 0x4 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_STOP_OP_SHIFT 4 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_STOP_OP_MASK 0x10 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_WREG_ERR_SHIFT 6 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_WREG_ERR_MASK 0x40 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CPDMA_UP_OVF_ERR_SHIFT 16 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CPDMA_UP_OVF_ERR_MASK 0x10000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD17_SHIFT 17 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD17_MASK 0x20000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_IFIFO_CI_ERR_SHIFT 18 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_IFIFO_CI_ERR_MASK 0x40000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_CTL_CI_ERR_SHIFT 19 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_CTL_CI_ERR_MASK 0x80000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQF_RD_ERR_SHIFT 20 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQF_RD_ERR_MASK 0x100000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_IFIFO_CI_ERR_SHIFT 21 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_IFIFO_CI_ERR_MASK 0x200000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_CTL_CI_ERR_SHIFT 22 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_CTL_CI_ERR_MASK 0x400000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_AXI_ERR_SHIFT 23 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_AXI_ERR_MASK 0x800000 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_SWITCH_WDT_ERR_SHIFT 24 +#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_SWITCH_WDT_ERR_MASK 0x1000000 + +/* PDMA0_QM_GLBL_PROT */ +#define PDMA0_QM_GLBL_PROT_PQF_SHIFT 0 +#define PDMA0_QM_GLBL_PROT_PQF_MASK 0xF +#define PDMA0_QM_GLBL_PROT_CQF_SHIFT 4 +#define PDMA0_QM_GLBL_PROT_CQF_MASK 0x1F0 +#define PDMA0_QM_GLBL_PROT_CP_SHIFT 9 +#define PDMA0_QM_GLBL_PROT_CP_MASK 0x3E00 +#define PDMA0_QM_GLBL_PROT_ERR_SHIFT 14 +#define PDMA0_QM_GLBL_PROT_ERR_MASK 0x4000 +#define PDMA0_QM_GLBL_PROT_ARB_SHIFT 15 +#define PDMA0_QM_GLBL_PROT_ARB_MASK 0x8000 +#define PDMA0_QM_GLBL_PROT_PQC_SHIFT 16 +#define PDMA0_QM_GLBL_PROT_PQC_MASK 0x10000 +#define PDMA0_QM_GLBL_PROT_CQ_IFIFO_MSG_SHIFT 17 +#define PDMA0_QM_GLBL_PROT_CQ_IFIFO_MSG_MASK 0x20000 +#define PDMA0_QM_GLBL_PROT_ARC_CQ_IFIFO_MSG_SHIFT 18 +#define PDMA0_QM_GLBL_PROT_ARC_CQ_IFIFO_MSG_MASK 0x40000 +#define PDMA0_QM_GLBL_PROT_CQ_CTL_MSG_SHIFT 19 +#define PDMA0_QM_GLBL_PROT_CQ_CTL_MSG_MASK 0x80000 +#define PDMA0_QM_GLBL_PROT_ARC_CQ_CTL_MSG_SHIFT 20 +#define PDMA0_QM_GLBL_PROT_ARC_CQ_CTL_MSG_MASK 0x100000 +#define PDMA0_QM_GLBL_PROT_CP_WR_ARC_SHIFT 21 +#define PDMA0_QM_GLBL_PROT_CP_WR_ARC_MASK 0x200000 +#define PDMA0_QM_GLBL_PROT_ARC_CQF_SHIFT 22 +#define PDMA0_QM_GLBL_PROT_ARC_CQF_MASK 0x400000 +#define PDMA0_QM_GLBL_PROT_ARC_CORE_SHIFT 23 +#define PDMA0_QM_GLBL_PROT_ARC_CORE_MASK 0x800000 + +/* PDMA0_QM_PQ_BASE_LO */ +#define PDMA0_QM_PQ_BASE_LO_VAL_SHIFT 0 +#define PDMA0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PQ_BASE_HI */ +#define PDMA0_QM_PQ_BASE_HI_VAL_SHIFT 0 +#define PDMA0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PQ_SIZE */ +#define PDMA0_QM_PQ_SIZE_VAL_SHIFT 0 +#define PDMA0_QM_PQ_SIZE_VAL_MASK 0x1F + +/* PDMA0_QM_PQ_PI */ +#define PDMA0_QM_PQ_PI_VAL_SHIFT 0 +#define PDMA0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PQ_CI */ +#define PDMA0_QM_PQ_CI_VAL_SHIFT 0 +#define PDMA0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PQ_CFG0 */ +#define PDMA0_QM_PQ_CFG0_FORCE_STALL_SHIFT 0 +#define PDMA0_QM_PQ_CFG0_FORCE_STALL_MASK 0x1 + +/* PDMA0_QM_PQ_CFG1 */ +#define PDMA0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0 +#define PDMA0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFF +#define PDMA0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define PDMA0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000 + +/* PDMA0_QM_PQ_STS0 */ +#define PDMA0_QM_PQ_STS0_CREDIT_CNT_SHIFT 0 +#define PDMA0_QM_PQ_STS0_CREDIT_CNT_MASK 0xFF +#define PDMA0_QM_PQ_STS0_FREE_CNT_SHIFT 8 +#define PDMA0_QM_PQ_STS0_FREE_CNT_MASK 0xFF00 +#define PDMA0_QM_PQ_STS0_INFLIGHT_CNT_SHIFT 16 +#define PDMA0_QM_PQ_STS0_INFLIGHT_CNT_MASK 0xFF0000 + +/* PDMA0_QM_PQ_STS1 */ +#define PDMA0_QM_PQ_STS1_BUF_EMPTY_SHIFT 0 +#define PDMA0_QM_PQ_STS1_BUF_EMPTY_MASK 0x1 +#define PDMA0_QM_PQ_STS1_BUSY_SHIFT 1 +#define PDMA0_QM_PQ_STS1_BUSY_MASK 0x2 + +/* PDMA0_QM_CQ_CFG0 */ +#define PDMA0_QM_CQ_CFG0_IF_B2B_EN_SHIFT 0 +#define PDMA0_QM_CQ_CFG0_IF_B2B_EN_MASK 0x1 +#define PDMA0_QM_CQ_CFG0_IF_MSG_EN_SHIFT 1 +#define PDMA0_QM_CQ_CFG0_IF_MSG_EN_MASK 0x2 +#define PDMA0_QM_CQ_CFG0_CTL_MSG_EN_SHIFT 2 +#define PDMA0_QM_CQ_CFG0_CTL_MSG_EN_MASK 0x4 + +/* PDMA0_QM_CQ_STS0 */ +#define PDMA0_QM_CQ_STS0_CREDIT_CNT_SHIFT 0 +#define PDMA0_QM_CQ_STS0_CREDIT_CNT_MASK 0xFF +#define PDMA0_QM_CQ_STS0_FREE_CNT_SHIFT 8 +#define PDMA0_QM_CQ_STS0_FREE_CNT_MASK 0xFF00 +#define PDMA0_QM_CQ_STS0_INFLIGHT_CNT_SHIFT 16 +#define PDMA0_QM_CQ_STS0_INFLIGHT_CNT_MASK 0xFF0000 + +/* PDMA0_QM_CQ_CFG1 */ +#define PDMA0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define PDMA0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFF +#define PDMA0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define PDMA0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000 + +/* PDMA0_QM_CQ_STS1 */ +#define PDMA0_QM_CQ_STS1_BUF_EMPTY_SHIFT 0 +#define PDMA0_QM_CQ_STS1_BUF_EMPTY_MASK 0x1 +#define PDMA0_QM_CQ_STS1_BUSY_SHIFT 1 +#define PDMA0_QM_CQ_STS1_BUSY_MASK 0x2 + +/* PDMA0_QM_CQ_PTR_LO_0 */ +#define PDMA0_QM_CQ_PTR_LO_0_VAL_SHIFT 0 +#define PDMA0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_PTR_HI_0 */ +#define PDMA0_QM_CQ_PTR_HI_0_VAL_SHIFT 0 +#define PDMA0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_TSIZE_0 */ +#define PDMA0_QM_CQ_TSIZE_0_VAL_SHIFT 0 +#define PDMA0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_CTL_0 */ +#define PDMA0_QM_CQ_CTL_0_UP_SHIFT 28 +#define PDMA0_QM_CQ_CTL_0_UP_MASK 0xF0000000 + +/* PDMA0_QM_CQ_PTR_LO_1 */ +#define PDMA0_QM_CQ_PTR_LO_1_VAL_SHIFT 0 +#define PDMA0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_PTR_HI_1 */ +#define PDMA0_QM_CQ_PTR_HI_1_VAL_SHIFT 0 +#define PDMA0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_TSIZE_1 */ +#define PDMA0_QM_CQ_TSIZE_1_VAL_SHIFT 0 +#define PDMA0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_CTL_1 */ +#define PDMA0_QM_CQ_CTL_1_UP_SHIFT 28 +#define PDMA0_QM_CQ_CTL_1_UP_MASK 0xF0000000 + +/* PDMA0_QM_CQ_PTR_LO_2 */ +#define PDMA0_QM_CQ_PTR_LO_2_VAL_SHIFT 0 +#define PDMA0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_PTR_HI_2 */ +#define PDMA0_QM_CQ_PTR_HI_2_VAL_SHIFT 0 +#define PDMA0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_TSIZE_2 */ +#define PDMA0_QM_CQ_TSIZE_2_VAL_SHIFT 0 +#define PDMA0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_CTL_2 */ +#define PDMA0_QM_CQ_CTL_2_UP_SHIFT 28 +#define PDMA0_QM_CQ_CTL_2_UP_MASK 0xF0000000 + +/* PDMA0_QM_CQ_PTR_LO_3 */ +#define PDMA0_QM_CQ_PTR_LO_3_VAL_SHIFT 0 +#define PDMA0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_PTR_HI_3 */ +#define PDMA0_QM_CQ_PTR_HI_3_VAL_SHIFT 0 +#define PDMA0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_TSIZE_3 */ +#define PDMA0_QM_CQ_TSIZE_3_VAL_SHIFT 0 +#define PDMA0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_CTL_3 */ +#define PDMA0_QM_CQ_CTL_3_UP_SHIFT 28 +#define PDMA0_QM_CQ_CTL_3_UP_MASK 0xF0000000 + +/* PDMA0_QM_CQ_PTR_LO_4 */ +#define PDMA0_QM_CQ_PTR_LO_4_VAL_SHIFT 0 +#define PDMA0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_PTR_HI_4 */ +#define PDMA0_QM_CQ_PTR_HI_4_VAL_SHIFT 0 +#define PDMA0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_TSIZE_4 */ +#define PDMA0_QM_CQ_TSIZE_4_VAL_SHIFT 0 +#define PDMA0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_CTL_4 */ +#define PDMA0_QM_CQ_CTL_4_UP_SHIFT 28 +#define PDMA0_QM_CQ_CTL_4_UP_MASK 0xF0000000 + +/* PDMA0_QM_CQ_TSIZE_STS */ +#define PDMA0_QM_CQ_TSIZE_STS_VAL_SHIFT 0 +#define PDMA0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_PTR_LO_STS */ +#define PDMA0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define PDMA0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_PTR_HI_STS */ +#define PDMA0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define PDMA0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_IFIFO_STS */ +#define PDMA0_QM_CQ_IFIFO_STS_CNT_SHIFT 0 +#define PDMA0_QM_CQ_IFIFO_STS_CNT_MASK 0x7 +#define PDMA0_QM_CQ_IFIFO_STS_RDY_SHIFT 4 +#define PDMA0_QM_CQ_IFIFO_STS_RDY_MASK 0x10 +#define PDMA0_QM_CQ_IFIFO_STS_CTL_STALL_SHIFT 8 +#define PDMA0_QM_CQ_IFIFO_STS_CTL_STALL_MASK 0x100 + +/* PDMA0_QM_CP_MSG_BASE0_ADDR_LO */ +#define PDMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 +#define PDMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_MSG_BASE0_ADDR_HI */ +#define PDMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 +#define PDMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_MSG_BASE1_ADDR_LO */ +#define PDMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 +#define PDMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_MSG_BASE1_ADDR_HI */ +#define PDMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 +#define PDMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_MSG_BASE2_ADDR_LO */ +#define PDMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 +#define PDMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_MSG_BASE2_ADDR_HI */ +#define PDMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 +#define PDMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_MSG_BASE3_ADDR_LO */ +#define PDMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 +#define PDMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_MSG_BASE3_ADDR_HI */ +#define PDMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 +#define PDMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_FENCE0_RDATA */ +#define PDMA0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 +#define PDMA0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF + +/* PDMA0_QM_CP_FENCE1_RDATA */ +#define PDMA0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 +#define PDMA0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF + +/* PDMA0_QM_CP_FENCE2_RDATA */ +#define PDMA0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 +#define PDMA0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF + +/* PDMA0_QM_CP_FENCE3_RDATA */ +#define PDMA0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 +#define PDMA0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF + +/* PDMA0_QM_CP_FENCE0_CNT */ +#define PDMA0_QM_CP_FENCE0_CNT_VAL_SHIFT 0 +#define PDMA0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF + +/* PDMA0_QM_CP_FENCE1_CNT */ +#define PDMA0_QM_CP_FENCE1_CNT_VAL_SHIFT 0 +#define PDMA0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF + +/* PDMA0_QM_CP_FENCE2_CNT */ +#define PDMA0_QM_CP_FENCE2_CNT_VAL_SHIFT 0 +#define PDMA0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF + +/* PDMA0_QM_CP_FENCE3_CNT */ +#define PDMA0_QM_CP_FENCE3_CNT_VAL_SHIFT 0 +#define PDMA0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF + +/* PDMA0_QM_CP_BARRIER_CFG */ +#define PDMA0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0 +#define PDMA0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF +#define PDMA0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16 +#define PDMA0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000 + +/* PDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */ +#define PDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 +#define PDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFF + +/* PDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET */ +#define PDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 +#define PDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFF + +/* PDMA0_QM_CP_LDMA_TSIZE_OFFSET */ +#define PDMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 +#define PDMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFF + +/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_0 */ +#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_0_VAL_SHIFT 0 +#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_0_VAL_MASK 0xFFFF + +/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_1 */ +#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_1_VAL_SHIFT 0 +#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_1_VAL_MASK 0xFFFF + +/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_2 */ +#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_2_VAL_SHIFT 0 +#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_2_VAL_MASK 0xFFFF + +/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_3 */ +#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_3_VAL_SHIFT 0 +#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_3_VAL_MASK 0xFFFF + +/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_4 */ +#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_4_VAL_SHIFT 0 +#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_4_VAL_MASK 0xFFFF + +/* PDMA0_QM_CP_STS */ +#define PDMA0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 +#define PDMA0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFF +#define PDMA0_QM_CP_STS_ERDY_SHIFT 8 +#define PDMA0_QM_CP_STS_ERDY_MASK 0x100 +#define PDMA0_QM_CP_STS_SWITCH_EN_SHIFT 9 +#define PDMA0_QM_CP_STS_SWITCH_EN_MASK 0x200 +#define PDMA0_QM_CP_STS_MRDY_SHIFT 10 +#define PDMA0_QM_CP_STS_MRDY_MASK 0x400 +#define PDMA0_QM_CP_STS_SW_STOP_SHIFT 11 +#define PDMA0_QM_CP_STS_SW_STOP_MASK 0x800 +#define PDMA0_QM_CP_STS_FENCE_ID_SHIFT 12 +#define PDMA0_QM_CP_STS_FENCE_ID_MASK 0x3000 +#define PDMA0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 14 +#define PDMA0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x4000 +#define PDMA0_QM_CP_STS_FENCE_TARGET_SHIFT 16 +#define PDMA0_QM_CP_STS_FENCE_TARGET_MASK 0x3FFF0000 +#define PDMA0_QM_CP_STS_CUR_CQ_SHIFT 30 +#define PDMA0_QM_CP_STS_CUR_CQ_MASK 0x40000000 + +/* PDMA0_QM_CP_CURRENT_INST_LO */ +#define PDMA0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0 +#define PDMA0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_CURRENT_INST_HI */ +#define PDMA0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0 +#define PDMA0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_PRED */ +#define PDMA0_QM_CP_PRED_VAL_SHIFT 0 +#define PDMA0_QM_CP_PRED_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_PRED_UPEN */ +#define PDMA0_QM_CP_PRED_UPEN_VAL_SHIFT 0 +#define PDMA0_QM_CP_PRED_UPEN_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_DBG_0 */ +#define PDMA0_QM_CP_DBG_0_CS_SHIFT 0 +#define PDMA0_QM_CP_DBG_0_CS_MASK 0x1F +#define PDMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 5 +#define PDMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x20 +#define PDMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 6 +#define PDMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x40 +#define PDMA0_QM_CP_DBG_0_MREB_STALL_SHIFT 7 +#define PDMA0_QM_CP_DBG_0_MREB_STALL_MASK 0x80 +#define PDMA0_QM_CP_DBG_0_STALL_SHIFT 8 +#define PDMA0_QM_CP_DBG_0_STALL_MASK 0x100 + +/* PDMA0_QM_CP_CPDMA_UP_CRED */ +#define PDMA0_QM_CP_CPDMA_UP_CRED_TH_SHIFT 0 +#define PDMA0_QM_CP_CPDMA_UP_CRED_TH_MASK 0x3 +#define PDMA0_QM_CP_CPDMA_UP_CRED_VAL_SHIFT 8 +#define PDMA0_QM_CP_CPDMA_UP_CRED_VAL_MASK 0x300 + +/* PDMA0_QM_CP_IN_DATA_LO */ +#define PDMA0_QM_CP_IN_DATA_LO_VAL_SHIFT 0 +#define PDMA0_QM_CP_IN_DATA_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_IN_DATA_HI */ +#define PDMA0_QM_CP_IN_DATA_HI_VAL_SHIFT 0 +#define PDMA0_QM_CP_IN_DATA_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PQC_HBW_BASE_LO */ +#define PDMA0_QM_PQC_HBW_BASE_LO_VAL_SHIFT 0 +#define PDMA0_QM_PQC_HBW_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PQC_HBW_BASE_HI */ +#define PDMA0_QM_PQC_HBW_BASE_HI_VAL_SHIFT 0 +#define PDMA0_QM_PQC_HBW_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PQC_SIZE */ +#define PDMA0_QM_PQC_SIZE_VAL_SHIFT 0 +#define PDMA0_QM_PQC_SIZE_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PQC_PI */ +#define PDMA0_QM_PQC_PI_VAL_SHIFT 0 +#define PDMA0_QM_PQC_PI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PQC_LBW_WDATA */ +#define PDMA0_QM_PQC_LBW_WDATA_VAL_SHIFT 0 +#define PDMA0_QM_PQC_LBW_WDATA_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PQC_LBW_BASE_LO */ +#define PDMA0_QM_PQC_LBW_BASE_LO_VAL_SHIFT 0 +#define PDMA0_QM_PQC_LBW_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PQC_LBW_BASE_HI */ +#define PDMA0_QM_PQC_LBW_BASE_HI_VAL_SHIFT 0 +#define PDMA0_QM_PQC_LBW_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PQC_CFG */ +#define PDMA0_QM_PQC_CFG_EN_SHIFT 0 +#define PDMA0_QM_PQC_CFG_EN_MASK 0x1 +#define PDMA0_QM_PQC_CFG_DIRECT_SHIFT 4 +#define PDMA0_QM_PQC_CFG_DIRECT_MASK 0x10 + +/* PDMA0_QM_PQC_SECURE_PUSH_IND */ +#define PDMA0_QM_PQC_SECURE_PUSH_IND_CP_NUM_SHIFT 0 +#define PDMA0_QM_PQC_SECURE_PUSH_IND_CP_NUM_MASK 0x3 + +/* PDMA0_QM_ARB_MASK */ +#define PDMA0_QM_ARB_MASK_VAL_SHIFT 0 +#define PDMA0_QM_ARB_MASK_VAL_MASK 0xF + +/* PDMA0_QM_ARB_CFG_0 */ +#define PDMA0_QM_ARB_CFG_0_PRIO_TYPE_SHIFT 0 +#define PDMA0_QM_ARB_CFG_0_PRIO_TYPE_MASK 0x1 +#define PDMA0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4 +#define PDMA0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10 +#define PDMA0_QM_ARB_CFG_0_EN_SHIFT 8 +#define PDMA0_QM_ARB_CFG_0_EN_MASK 0x100 +#define PDMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 9 +#define PDMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x200 + +/* PDMA0_QM_ARB_CHOICE_Q_PUSH */ +#define PDMA0_QM_ARB_CHOICE_Q_PUSH_VAL_SHIFT 0 +#define PDMA0_QM_ARB_CHOICE_Q_PUSH_VAL_MASK 0x3 + +/* PDMA0_QM_ARB_WRR_WEIGHT */ +#define PDMA0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0 +#define PDMA0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFF + +/* PDMA0_QM_ARB_CFG_1 */ +#define PDMA0_QM_ARB_CFG_1_CLR_SHIFT 0 +#define PDMA0_QM_ARB_CFG_1_CLR_MASK 0x1 + +/* PDMA0_QM_ARB_MST_AVAIL_CRED */ +#define PDMA0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0 +#define PDMA0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F + +/* PDMA0_QM_ARB_MST_CRED_INC */ +#define PDMA0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0 +#define PDMA0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARB_MST_CHOICE_PUSH_OFST */ +#define PDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_VAL_SHIFT 0 +#define PDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST */ +#define PDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0 +#define PDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARB_MST_SLAVE_EN */ +#define PDMA0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0 +#define PDMA0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARB_MST_SLAVE_EN_1 */ +#define PDMA0_QM_ARB_MST_SLAVE_EN_1_VAL_SHIFT 0 +#define PDMA0_QM_ARB_MST_SLAVE_EN_1_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARB_SLV_CHOICE_WDT */ +#define PDMA0_QM_ARB_SLV_CHOICE_WDT_VAL_SHIFT 0 +#define PDMA0_QM_ARB_SLV_CHOICE_WDT_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARB_SLV_ID */ +#define PDMA0_QM_ARB_SLV_ID_VAL_SHIFT 0 +#define PDMA0_QM_ARB_SLV_ID_VAL_MASK 0x7F + +/* PDMA0_QM_ARB_MST_QUIET_PER */ +#define PDMA0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0 +#define PDMA0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARB_MSG_MAX_INFLIGHT */ +#define PDMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0 +#define PDMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F + +/* PDMA0_QM_ARB_BASE_LO */ +#define PDMA0_QM_ARB_BASE_LO_VAL_SHIFT 0 +#define PDMA0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARB_BASE_HI */ +#define PDMA0_QM_ARB_BASE_HI_VAL_SHIFT 0 +#define PDMA0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARB_STATE_STS */ +#define PDMA0_QM_ARB_STATE_STS_VAL_SHIFT 0 +#define PDMA0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARB_CHOICE_FULLNESS_STS */ +#define PDMA0_QM_ARB_CHOICE_FULLNESS_STS_VAL_SHIFT 0 +#define PDMA0_QM_ARB_CHOICE_FULLNESS_STS_VAL_MASK 0x7F + +/* PDMA0_QM_ARB_MSG_STS */ +#define PDMA0_QM_ARB_MSG_STS_FULL_SHIFT 0 +#define PDMA0_QM_ARB_MSG_STS_FULL_MASK 0x1 +#define PDMA0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1 +#define PDMA0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2 + +/* PDMA0_QM_ARB_SLV_CHOICE_Q_HEAD */ +#define PDMA0_QM_ARB_SLV_CHOICE_Q_HEAD_VAL_SHIFT 0 +#define PDMA0_QM_ARB_SLV_CHOICE_Q_HEAD_VAL_MASK 0x3 + +/* PDMA0_QM_ARB_ERR_CAUSE */ +#define PDMA0_QM_ARB_ERR_CAUSE_CHOICE_OVF_SHIFT 0 +#define PDMA0_QM_ARB_ERR_CAUSE_CHOICE_OVF_MASK 0x1 +#define PDMA0_QM_ARB_ERR_CAUSE_CHOICE_WDT_SHIFT 1 +#define PDMA0_QM_ARB_ERR_CAUSE_CHOICE_WDT_MASK 0x2 +#define PDMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2 +#define PDMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4 + +/* PDMA0_QM_ARB_ERR_MSG_EN */ +#define PDMA0_QM_ARB_ERR_MSG_EN_CHOICE_OVF_SHIFT 0 +#define PDMA0_QM_ARB_ERR_MSG_EN_CHOICE_OVF_MASK 0x1 +#define PDMA0_QM_ARB_ERR_MSG_EN_CHOICE_WDT_SHIFT 1 +#define PDMA0_QM_ARB_ERR_MSG_EN_CHOICE_WDT_MASK 0x2 +#define PDMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2 +#define PDMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 + +/* PDMA0_QM_ARB_ERR_STS_DRP */ +#define PDMA0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0 +#define PDMA0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3 + +/* PDMA0_QM_ARB_MST_CRED_STS */ +#define PDMA0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0 +#define PDMA0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F +#define PDMA0_QM_ARB_MST_CRED_STS_IDX_SHIFT 24 +#define PDMA0_QM_ARB_MST_CRED_STS_IDX_MASK 0x1F000000 + +/* PDMA0_QM_ARB_MST_CRED_STS_1 */ +#define PDMA0_QM_ARB_MST_CRED_STS_1_VAL_SHIFT 0 +#define PDMA0_QM_ARB_MST_CRED_STS_1_VAL_MASK 0x7F +#define PDMA0_QM_ARB_MST_CRED_STS_1_IDX_SHIFT 24 +#define PDMA0_QM_ARB_MST_CRED_STS_1_IDX_MASK 0x1F000000 + +/* PDMA0_QM_CSMR_STRICT_PRIO_CFG */ +#define PDMA0_QM_CSMR_STRICT_PRIO_CFG_ARB_TYPE_SHIFT 0 +#define PDMA0_QM_CSMR_STRICT_PRIO_CFG_ARB_TYPE_MASK 0x1 +#define PDMA0_QM_CSMR_STRICT_PRIO_CFG_PER_ENTRY_SHIFT 4 +#define PDMA0_QM_CSMR_STRICT_PRIO_CFG_PER_ENTRY_MASK 0x10 + +/* PDMA0_QM_ARC_CQ_CFG0 */ +#define PDMA0_QM_ARC_CQ_CFG0_IF_B2B_EN_SHIFT 0 +#define PDMA0_QM_ARC_CQ_CFG0_IF_B2B_EN_MASK 0x1 +#define PDMA0_QM_ARC_CQ_CFG0_IF_MSG_EN_SHIFT 1 +#define PDMA0_QM_ARC_CQ_CFG0_IF_MSG_EN_MASK 0x2 +#define PDMA0_QM_ARC_CQ_CFG0_CTL_MSG_EN_SHIFT 2 +#define PDMA0_QM_ARC_CQ_CFG0_CTL_MSG_EN_MASK 0x4 + +/* PDMA0_QM_ARC_CQ_CFG1 */ +#define PDMA0_QM_ARC_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define PDMA0_QM_ARC_CQ_CFG1_CREDIT_LIM_MASK 0xFF +#define PDMA0_QM_ARC_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define PDMA0_QM_ARC_CQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000 + +/* PDMA0_QM_ARC_CQ_PTR_LO */ +#define PDMA0_QM_ARC_CQ_PTR_LO_VAL_SHIFT 0 +#define PDMA0_QM_ARC_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_CQ_PTR_HI */ +#define PDMA0_QM_ARC_CQ_PTR_HI_VAL_SHIFT 0 +#define PDMA0_QM_ARC_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_CQ_TSIZE */ +#define PDMA0_QM_ARC_CQ_TSIZE_VAL_SHIFT 0 +#define PDMA0_QM_ARC_CQ_TSIZE_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_CQ_CTL */ +#define PDMA0_QM_ARC_CQ_CTL_UP_SHIFT 28 +#define PDMA0_QM_ARC_CQ_CTL_UP_MASK 0xF0000000 + +/* PDMA0_QM_ARC_CQ_IFIFO_STS */ +#define PDMA0_QM_ARC_CQ_IFIFO_STS_CNT_SHIFT 0 +#define PDMA0_QM_ARC_CQ_IFIFO_STS_CNT_MASK 0x7 +#define PDMA0_QM_ARC_CQ_IFIFO_STS_RDY_SHIFT 4 +#define PDMA0_QM_ARC_CQ_IFIFO_STS_RDY_MASK 0x10 +#define PDMA0_QM_ARC_CQ_IFIFO_STS_CTL_STALL_SHIFT 8 +#define PDMA0_QM_ARC_CQ_IFIFO_STS_CTL_STALL_MASK 0x100 + +/* PDMA0_QM_ARC_CQ_STS0 */ +#define PDMA0_QM_ARC_CQ_STS0_CREDIT_CNT_SHIFT 0 +#define PDMA0_QM_ARC_CQ_STS0_CREDIT_CNT_MASK 0xFF +#define PDMA0_QM_ARC_CQ_STS0_FREE_CNT_SHIFT 8 +#define PDMA0_QM_ARC_CQ_STS0_FREE_CNT_MASK 0xFF00 +#define PDMA0_QM_ARC_CQ_STS0_INFLIGHT_CNT_SHIFT 16 +#define PDMA0_QM_ARC_CQ_STS0_INFLIGHT_CNT_MASK 0xFF0000 + +/* PDMA0_QM_ARC_CQ_STS1 */ +#define PDMA0_QM_ARC_CQ_STS1_BUF_EMPTY_SHIFT 0 +#define PDMA0_QM_ARC_CQ_STS1_BUF_EMPTY_MASK 0x1 +#define PDMA0_QM_ARC_CQ_STS1_BUSY_SHIFT 1 +#define PDMA0_QM_ARC_CQ_STS1_BUSY_MASK 0x2 + +/* PDMA0_QM_ARC_CQ_TSIZE_STS */ +#define PDMA0_QM_ARC_CQ_TSIZE_STS_VAL_SHIFT 0 +#define PDMA0_QM_ARC_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_CQ_PTR_LO_STS */ +#define PDMA0_QM_ARC_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define PDMA0_QM_ARC_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_CQ_PTR_HI_STS */ +#define PDMA0_QM_ARC_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define PDMA0_QM_ARC_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_WR_ARC_ADDR_HI */ +#define PDMA0_QM_CP_WR_ARC_ADDR_HI_VAL_SHIFT 0 +#define PDMA0_QM_CP_WR_ARC_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_WR_ARC_ADDR_LO */ +#define PDMA0_QM_CP_WR_ARC_ADDR_LO_VAL_SHIFT 0 +#define PDMA0_QM_CP_WR_ARC_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI */ +#define PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI_VAL_SHIFT 0 +#define PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO */ +#define PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO_VAL_SHIFT 0 +#define PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI */ +#define PDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI_VAL_SHIFT 0 +#define PDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO */ +#define PDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO_VAL_SHIFT 0 +#define PDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_IFIFO_MSG_BASE_HI */ +#define PDMA0_QM_CQ_IFIFO_MSG_BASE_HI_VAL_SHIFT 0 +#define PDMA0_QM_CQ_IFIFO_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_IFIFO_MSG_BASE_LO */ +#define PDMA0_QM_CQ_IFIFO_MSG_BASE_LO_VAL_SHIFT 0 +#define PDMA0_QM_CQ_IFIFO_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_CTL_MSG_BASE_HI */ +#define PDMA0_QM_CQ_CTL_MSG_BASE_HI_VAL_SHIFT 0 +#define PDMA0_QM_CQ_CTL_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_CTL_MSG_BASE_LO */ +#define PDMA0_QM_CQ_CTL_MSG_BASE_LO_VAL_SHIFT 0 +#define PDMA0_QM_CQ_CTL_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ADDR_OVRD */ +#define PDMA0_QM_ADDR_OVRD_IDX_SHIFT 0 +#define PDMA0_QM_ADDR_OVRD_IDX_MASK 0xFF + +/* PDMA0_QM_CQ_IFIFO_CI */ +#define PDMA0_QM_CQ_IFIFO_CI_VAL_SHIFT 0 +#define PDMA0_QM_CQ_IFIFO_CI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_CQ_IFIFO_CI */ +#define PDMA0_QM_ARC_CQ_IFIFO_CI_VAL_SHIFT 0 +#define PDMA0_QM_ARC_CQ_IFIFO_CI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CQ_CTL_CI */ +#define PDMA0_QM_CQ_CTL_CI_VAL_SHIFT 0 +#define PDMA0_QM_CQ_CTL_CI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_CQ_CTL_CI */ +#define PDMA0_QM_ARC_CQ_CTL_CI_VAL_SHIFT 0 +#define PDMA0_QM_ARC_CQ_CTL_CI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_CFG */ +#define PDMA0_QM_CP_CFG_SWITCH_EN_SHIFT 0 +#define PDMA0_QM_CP_CFG_SWITCH_EN_MASK 0x1 +#define PDMA0_QM_CP_CFG_SWITCH_WD_EN_SHIFT 1 +#define PDMA0_QM_CP_CFG_SWITCH_WD_EN_MASK 0x2 + +/* PDMA0_QM_CP_EXT_SWITCH */ +#define PDMA0_QM_CP_EXT_SWITCH_VAL_SHIFT 0 +#define PDMA0_QM_CP_EXT_SWITCH_VAL_MASK 0x1 + +/* PDMA0_QM_CP_SWITCH_WD_SET */ +#define PDMA0_QM_CP_SWITCH_WD_SET_VAL_SHIFT 0 +#define PDMA0_QM_CP_SWITCH_WD_SET_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_CP_SWITCH_WD */ +#define PDMA0_QM_CP_SWITCH_WD_VAL_SHIFT 0 +#define PDMA0_QM_CP_SWITCH_WD_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_LB_ADDR_BASE_LO */ +#define PDMA0_QM_ARC_LB_ADDR_BASE_LO_VAL_SHIFT 0 +#define PDMA0_QM_ARC_LB_ADDR_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_LB_ADDR_BASE_HI */ +#define PDMA0_QM_ARC_LB_ADDR_BASE_HI_VAL_SHIFT 0 +#define PDMA0_QM_ARC_LB_ADDR_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ENGINE_BASE_ADDR_HI */ +#define PDMA0_QM_ENGINE_BASE_ADDR_HI_VAL_SHIFT 0 +#define PDMA0_QM_ENGINE_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ENGINE_BASE_ADDR_LO */ +#define PDMA0_QM_ENGINE_BASE_ADDR_LO_VAL_SHIFT 0 +#define PDMA0_QM_ENGINE_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ENGINE_ADDR_RANGE_SIZE */ +#define PDMA0_QM_ENGINE_ADDR_RANGE_SIZE_VAL_SHIFT 0 +#define PDMA0_QM_ENGINE_ADDR_RANGE_SIZE_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI */ +#define PDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI_VAL_SHIFT 0 +#define PDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO */ +#define PDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO_VAL_SHIFT 0 +#define PDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_QM_BASE_ADDR_HI */ +#define PDMA0_QM_QM_BASE_ADDR_HI_VAL_SHIFT 0 +#define PDMA0_QM_QM_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_QM_BASE_ADDR_LO */ +#define PDMA0_QM_QM_BASE_ADDR_LO_VAL_SHIFT 0 +#define PDMA0_QM_QM_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_ARC_PQC_SECURE_PUSH_IND */ +#define PDMA0_QM_ARC_PQC_SECURE_PUSH_IND_CP_NUM_SHIFT 0 +#define PDMA0_QM_ARC_PQC_SECURE_PUSH_IND_CP_NUM_MASK 0x3 + +/* PDMA0_QM_PQC_STS_0 */ +#define PDMA0_QM_PQC_STS_0_COMP_DATA_SHIFT 0 +#define PDMA0_QM_PQC_STS_0_COMP_DATA_MASK 0xFFFF +#define PDMA0_QM_PQC_STS_0_COMP_OFST_SHIFT 16 +#define PDMA0_QM_PQC_STS_0_COMP_OFST_MASK 0xFFFF0000 + +/* PDMA0_QM_PQC_STS_1 */ +#define PDMA0_QM_PQC_STS_1_COMP_FIFO_CNTR_SHIFT 0 +#define PDMA0_QM_PQC_STS_1_COMP_FIFO_CNTR_MASK 0xF +#define PDMA0_QM_PQC_STS_1_COMP_FIFO_EMPTY_SHIFT 4 +#define PDMA0_QM_PQC_STS_1_COMP_FIFO_EMPTY_MASK 0x10 +#define PDMA0_QM_PQC_STS_1_COMP_FIFO_FULL_SHIFT 5 +#define PDMA0_QM_PQC_STS_1_COMP_FIFO_FULL_MASK 0x20 + +/* PDMA0_QM_SEI_STATUS */ +#define PDMA0_QM_SEI_STATUS_QM_INT_SHIFT 0 +#define PDMA0_QM_SEI_STATUS_QM_INT_MASK 0x1 +#define PDMA0_QM_SEI_STATUS_ARC_INT_SHIFT 1 +#define PDMA0_QM_SEI_STATUS_ARC_INT_MASK 0x2 + +/* PDMA0_QM_SEI_MASK */ +#define PDMA0_QM_SEI_MASK_QM_INT_SHIFT 0 +#define PDMA0_QM_SEI_MASK_QM_INT_MASK 0x1 +#define PDMA0_QM_SEI_MASK_ARC_INT_SHIFT 1 +#define PDMA0_QM_SEI_MASK_ARC_INT_MASK 0x2 + +/* PDMA0_QM_GLBL_ERR_ADDR_LO */ +#define PDMA0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 +#define PDMA0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_GLBL_ERR_ADDR_HI */ +#define PDMA0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 +#define PDMA0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_GLBL_ERR_WDATA */ +#define PDMA0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0 +#define PDMA0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_L2H_MASK_LO */ +#define PDMA0_QM_L2H_MASK_LO_VAL_SHIFT 20 +#define PDMA0_QM_L2H_MASK_LO_VAL_MASK 0xFFF00000 + +/* PDMA0_QM_L2H_MASK_HI */ +#define PDMA0_QM_L2H_MASK_HI_VAL_SHIFT 0 +#define PDMA0_QM_L2H_MASK_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_L2H_CMPR_LO */ +#define PDMA0_QM_L2H_CMPR_LO_VAL_SHIFT 20 +#define PDMA0_QM_L2H_CMPR_LO_VAL_MASK 0xFFF00000 + +/* PDMA0_QM_L2H_CMPR_HI */ +#define PDMA0_QM_L2H_CMPR_HI_VAL_SHIFT 0 +#define PDMA0_QM_L2H_CMPR_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_LOCAL_RANGE_BASE */ +#define PDMA0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 0 +#define PDMA0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF + +/* PDMA0_QM_LOCAL_RANGE_SIZE */ +#define PDMA0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 0 +#define PDMA0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF + +/* PDMA0_QM_HBW_RD_RATE_LIM_CFG_1 */ +#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31 +#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* PDMA0_QM_LBW_WR_RATE_LIM_CFG_0 */ +#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* PDMA0_QM_LBW_WR_RATE_LIM_CFG_1 */ +#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31 +#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* PDMA0_QM_HBW_RD_RATE_LIM_CFG_0 */ +#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* PDMA0_QM_IND_GW_APB_CFG */ +#define PDMA0_QM_IND_GW_APB_CFG_ADDR_SHIFT 0 +#define PDMA0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF +#define PDMA0_QM_IND_GW_APB_CFG_CMD_SHIFT 31 +#define PDMA0_QM_IND_GW_APB_CFG_CMD_MASK 0x80000000 + +/* PDMA0_QM_IND_GW_APB_WDATA */ +#define PDMA0_QM_IND_GW_APB_WDATA_VAL_SHIFT 0 +#define PDMA0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_IND_GW_APB_RDATA */ +#define PDMA0_QM_IND_GW_APB_RDATA_VAL_SHIFT 0 +#define PDMA0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_IND_GW_APB_STATUS */ +#define PDMA0_QM_IND_GW_APB_STATUS_RDY_SHIFT 0 +#define PDMA0_QM_IND_GW_APB_STATUS_RDY_MASK 0x1 +#define PDMA0_QM_IND_GW_APB_STATUS_ERR_SHIFT 1 +#define PDMA0_QM_IND_GW_APB_STATUS_ERR_MASK 0x2 + +/* PDMA0_QM_PERF_CNT_FREE_LO */ +#define PDMA0_QM_PERF_CNT_FREE_LO_VAL_SHIFT 0 +#define PDMA0_QM_PERF_CNT_FREE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PERF_CNT_FREE_HI */ +#define PDMA0_QM_PERF_CNT_FREE_HI_VAL_SHIFT 0 +#define PDMA0_QM_PERF_CNT_FREE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PERF_CNT_IDLE_LO */ +#define PDMA0_QM_PERF_CNT_IDLE_LO_VAL_SHIFT 0 +#define PDMA0_QM_PERF_CNT_IDLE_LO_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PERF_CNT_IDLE_HI */ +#define PDMA0_QM_PERF_CNT_IDLE_HI_VAL_SHIFT 0 +#define PDMA0_QM_PERF_CNT_IDLE_HI_VAL_MASK 0xFFFFFFFF + +/* PDMA0_QM_PERF_CNT_CFG */ +#define PDMA0_QM_PERF_CNT_CFG_PQ_MASK_SHIFT 0 +#define PDMA0_QM_PERF_CNT_CFG_PQ_MASK_MASK 0xF +#define PDMA0_QM_PERF_CNT_CFG_CQ_MASK_SHIFT 8 +#define PDMA0_QM_PERF_CNT_CFG_CQ_MASK_MASK 0x1F00 +#define PDMA0_QM_PERF_CNT_CFG_CP_MASK_SHIFT 16 +#define PDMA0_QM_PERF_CNT_CFG_CP_MASK_MASK 0x1F0000 +#define PDMA0_QM_PERF_CNT_CFG_AGENT_MASK_SHIFT 24 +#define PDMA0_QM_PERF_CNT_CFG_AGENT_MASK_MASK 0x1000000 +#define PDMA0_QM_PERF_CNT_CFG_EN_FREE_SHIFT 30 +#define PDMA0_QM_PERF_CNT_CFG_EN_FREE_MASK 0x40000000 +#define PDMA0_QM_PERF_CNT_CFG_EN_IDLE_SHIFT 31 +#define PDMA0_QM_PERF_CNT_CFG_EN_IDLE_MASK 0x80000000 + +#endif /* ASIC_REG_PDMA0_QM_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_regs.h new file mode 100644 index 000000000000..77d803c938d4 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma0_qm_regs.h @@ -0,0 +1,1057 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA0_QM_REGS_H_ +#define ASIC_REG_PDMA0_QM_REGS_H_ + +/* + ***************************************** + * PDMA0_QM + * (Prototype: QMAN) + ***************************************** + */ + +#define mmPDMA0_QM_GLBL_CFG0 0x4C8A000 + +#define mmPDMA0_QM_GLBL_CFG1 0x4C8A004 + +#define mmPDMA0_QM_GLBL_CFG2 0x4C8A008 + +#define mmPDMA0_QM_GLBL_ERR_CFG 0x4C8A00C + +#define mmPDMA0_QM_GLBL_ERR_CFG1 0x4C8A010 + +#define mmPDMA0_QM_GLBL_ERR_ARC_HALT_EN 0x4C8A014 + +#define mmPDMA0_QM_GLBL_AXCACHE 0x4C8A018 + +#define mmPDMA0_QM_GLBL_STS0 0x4C8A01C + +#define mmPDMA0_QM_GLBL_STS1 0x4C8A020 + +#define mmPDMA0_QM_GLBL_ERR_STS_0 0x4C8A024 + +#define mmPDMA0_QM_GLBL_ERR_STS_1 0x4C8A028 + +#define mmPDMA0_QM_GLBL_ERR_STS_2 0x4C8A02C + +#define mmPDMA0_QM_GLBL_ERR_STS_3 0x4C8A030 + +#define mmPDMA0_QM_GLBL_ERR_STS_4 0x4C8A034 + +#define mmPDMA0_QM_GLBL_ERR_MSG_EN_0 0x4C8A038 + +#define mmPDMA0_QM_GLBL_ERR_MSG_EN_1 0x4C8A03C + +#define mmPDMA0_QM_GLBL_ERR_MSG_EN_2 0x4C8A040 + +#define mmPDMA0_QM_GLBL_ERR_MSG_EN_3 0x4C8A044 + +#define mmPDMA0_QM_GLBL_ERR_MSG_EN_4 0x4C8A048 + +#define mmPDMA0_QM_GLBL_PROT 0x4C8A04C + +#define mmPDMA0_QM_PQ_BASE_LO_0 0x4C8A050 + +#define mmPDMA0_QM_PQ_BASE_LO_1 0x4C8A054 + +#define mmPDMA0_QM_PQ_BASE_LO_2 0x4C8A058 + +#define mmPDMA0_QM_PQ_BASE_LO_3 0x4C8A05C + +#define mmPDMA0_QM_PQ_BASE_HI_0 0x4C8A060 + +#define mmPDMA0_QM_PQ_BASE_HI_1 0x4C8A064 + +#define mmPDMA0_QM_PQ_BASE_HI_2 0x4C8A068 + +#define mmPDMA0_QM_PQ_BASE_HI_3 0x4C8A06C + +#define mmPDMA0_QM_PQ_SIZE_0 0x4C8A070 + +#define mmPDMA0_QM_PQ_SIZE_1 0x4C8A074 + +#define mmPDMA0_QM_PQ_SIZE_2 0x4C8A078 + +#define mmPDMA0_QM_PQ_SIZE_3 0x4C8A07C + +#define mmPDMA0_QM_PQ_PI_0 0x4C8A080 + +#define mmPDMA0_QM_PQ_PI_1 0x4C8A084 + +#define mmPDMA0_QM_PQ_PI_2 0x4C8A088 + +#define mmPDMA0_QM_PQ_PI_3 0x4C8A08C + +#define mmPDMA0_QM_PQ_CI_0 0x4C8A090 + +#define mmPDMA0_QM_PQ_CI_1 0x4C8A094 + +#define mmPDMA0_QM_PQ_CI_2 0x4C8A098 + +#define mmPDMA0_QM_PQ_CI_3 0x4C8A09C + +#define mmPDMA0_QM_PQ_CFG0_0 0x4C8A0A0 + +#define mmPDMA0_QM_PQ_CFG0_1 0x4C8A0A4 + +#define mmPDMA0_QM_PQ_CFG0_2 0x4C8A0A8 + +#define mmPDMA0_QM_PQ_CFG0_3 0x4C8A0AC + +#define mmPDMA0_QM_PQ_CFG1_0 0x4C8A0B0 + +#define mmPDMA0_QM_PQ_CFG1_1 0x4C8A0B4 + +#define mmPDMA0_QM_PQ_CFG1_2 0x4C8A0B8 + +#define mmPDMA0_QM_PQ_CFG1_3 0x4C8A0BC + +#define mmPDMA0_QM_PQ_STS0_0 0x4C8A0C0 + +#define mmPDMA0_QM_PQ_STS0_1 0x4C8A0C4 + +#define mmPDMA0_QM_PQ_STS0_2 0x4C8A0C8 + +#define mmPDMA0_QM_PQ_STS0_3 0x4C8A0CC + +#define mmPDMA0_QM_PQ_STS1_0 0x4C8A0D0 + +#define mmPDMA0_QM_PQ_STS1_1 0x4C8A0D4 + +#define mmPDMA0_QM_PQ_STS1_2 0x4C8A0D8 + +#define mmPDMA0_QM_PQ_STS1_3 0x4C8A0DC + +#define mmPDMA0_QM_CQ_CFG0_0 0x4C8A0E0 + +#define mmPDMA0_QM_CQ_CFG0_1 0x4C8A0E4 + +#define mmPDMA0_QM_CQ_CFG0_2 0x4C8A0E8 + +#define mmPDMA0_QM_CQ_CFG0_3 0x4C8A0EC + +#define mmPDMA0_QM_CQ_CFG0_4 0x4C8A0F0 + +#define mmPDMA0_QM_CQ_STS0_0 0x4C8A0F4 + +#define mmPDMA0_QM_CQ_STS0_1 0x4C8A0F8 + +#define mmPDMA0_QM_CQ_STS0_2 0x4C8A0FC + +#define mmPDMA0_QM_CQ_STS0_3 0x4C8A100 + +#define mmPDMA0_QM_CQ_STS0_4 0x4C8A104 + +#define mmPDMA0_QM_CQ_CFG1_0 0x4C8A108 + +#define mmPDMA0_QM_CQ_CFG1_1 0x4C8A10C + +#define mmPDMA0_QM_CQ_CFG1_2 0x4C8A110 + +#define mmPDMA0_QM_CQ_CFG1_3 0x4C8A114 + +#define mmPDMA0_QM_CQ_CFG1_4 0x4C8A118 + +#define mmPDMA0_QM_CQ_STS1_0 0x4C8A11C + +#define mmPDMA0_QM_CQ_STS1_1 0x4C8A120 + +#define mmPDMA0_QM_CQ_STS1_2 0x4C8A124 + +#define mmPDMA0_QM_CQ_STS1_3 0x4C8A128 + +#define mmPDMA0_QM_CQ_STS1_4 0x4C8A12C + +#define mmPDMA0_QM_CQ_PTR_LO_0 0x4C8A150 + +#define mmPDMA0_QM_CQ_PTR_HI_0 0x4C8A154 + +#define mmPDMA0_QM_CQ_TSIZE_0 0x4C8A158 + +#define mmPDMA0_QM_CQ_CTL_0 0x4C8A15C + +#define mmPDMA0_QM_CQ_PTR_LO_1 0x4C8A160 + +#define mmPDMA0_QM_CQ_PTR_HI_1 0x4C8A164 + +#define mmPDMA0_QM_CQ_TSIZE_1 0x4C8A168 + +#define mmPDMA0_QM_CQ_CTL_1 0x4C8A16C + +#define mmPDMA0_QM_CQ_PTR_LO_2 0x4C8A170 + +#define mmPDMA0_QM_CQ_PTR_HI_2 0x4C8A174 + +#define mmPDMA0_QM_CQ_TSIZE_2 0x4C8A178 + +#define mmPDMA0_QM_CQ_CTL_2 0x4C8A17C + +#define mmPDMA0_QM_CQ_PTR_LO_3 0x4C8A180 + +#define mmPDMA0_QM_CQ_PTR_HI_3 0x4C8A184 + +#define mmPDMA0_QM_CQ_TSIZE_3 0x4C8A188 + +#define mmPDMA0_QM_CQ_CTL_3 0x4C8A18C + +#define mmPDMA0_QM_CQ_PTR_LO_4 0x4C8A190 + +#define mmPDMA0_QM_CQ_PTR_HI_4 0x4C8A194 + +#define mmPDMA0_QM_CQ_TSIZE_4 0x4C8A198 + +#define mmPDMA0_QM_CQ_CTL_4 0x4C8A19C + +#define mmPDMA0_QM_CQ_TSIZE_STS_0 0x4C8A1A0 + +#define mmPDMA0_QM_CQ_TSIZE_STS_1 0x4C8A1A4 + +#define mmPDMA0_QM_CQ_TSIZE_STS_2 0x4C8A1A8 + +#define mmPDMA0_QM_CQ_TSIZE_STS_3 0x4C8A1AC + +#define mmPDMA0_QM_CQ_TSIZE_STS_4 0x4C8A1B0 + +#define mmPDMA0_QM_CQ_PTR_LO_STS_0 0x4C8A1B4 + +#define mmPDMA0_QM_CQ_PTR_LO_STS_1 0x4C8A1B8 + +#define mmPDMA0_QM_CQ_PTR_LO_STS_2 0x4C8A1BC + +#define mmPDMA0_QM_CQ_PTR_LO_STS_3 0x4C8A1C0 + +#define mmPDMA0_QM_CQ_PTR_LO_STS_4 0x4C8A1C4 + +#define mmPDMA0_QM_CQ_PTR_HI_STS_0 0x4C8A1C8 + +#define mmPDMA0_QM_CQ_PTR_HI_STS_1 0x4C8A1CC + +#define mmPDMA0_QM_CQ_PTR_HI_STS_2 0x4C8A1D0 + +#define mmPDMA0_QM_CQ_PTR_HI_STS_3 0x4C8A1D4 + +#define mmPDMA0_QM_CQ_PTR_HI_STS_4 0x4C8A1D8 + +#define mmPDMA0_QM_CQ_IFIFO_STS_0 0x4C8A1DC + +#define mmPDMA0_QM_CQ_IFIFO_STS_1 0x4C8A1E0 + +#define mmPDMA0_QM_CQ_IFIFO_STS_2 0x4C8A1E4 + +#define mmPDMA0_QM_CQ_IFIFO_STS_3 0x4C8A1E8 + +#define mmPDMA0_QM_CQ_IFIFO_STS_4 0x4C8A1EC + +#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 0x4C8A1F0 + +#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_1 0x4C8A1F4 + +#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_2 0x4C8A1F8 + +#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_3 0x4C8A1FC + +#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_4 0x4C8A200 + +#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 0x4C8A204 + +#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_1 0x4C8A208 + +#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_2 0x4C8A20C + +#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_3 0x4C8A210 + +#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_4 0x4C8A214 + +#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 0x4C8A218 + +#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_1 0x4C8A21C + +#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_2 0x4C8A220 + +#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_3 0x4C8A224 + +#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_4 0x4C8A228 + +#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 0x4C8A22C + +#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_1 0x4C8A230 + +#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_2 0x4C8A234 + +#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_3 0x4C8A238 + +#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_4 0x4C8A23C + +#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 0x4C8A240 + +#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_1 0x4C8A244 + +#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 0x4C8A248 + +#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_3 0x4C8A24C + +#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_4 0x4C8A250 + +#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 0x4C8A254 + +#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_1 0x4C8A258 + +#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_2 0x4C8A25C + +#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_3 0x4C8A260 + +#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_4 0x4C8A264 + +#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 0x4C8A268 + +#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_1 0x4C8A26C + +#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_2 0x4C8A270 + +#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_3 0x4C8A274 + +#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_4 0x4C8A278 + +#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 0x4C8A27C + +#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_1 0x4C8A280 + +#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_2 0x4C8A284 + +#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_3 0x4C8A288 + +#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_4 0x4C8A28C + +#define mmPDMA0_QM_CP_FENCE0_RDATA_0 0x4C8A290 + +#define mmPDMA0_QM_CP_FENCE0_RDATA_1 0x4C8A294 + +#define mmPDMA0_QM_CP_FENCE0_RDATA_2 0x4C8A298 + +#define mmPDMA0_QM_CP_FENCE0_RDATA_3 0x4C8A29C + +#define mmPDMA0_QM_CP_FENCE0_RDATA_4 0x4C8A2A0 + +#define mmPDMA0_QM_CP_FENCE1_RDATA_0 0x4C8A2A4 + +#define mmPDMA0_QM_CP_FENCE1_RDATA_1 0x4C8A2A8 + +#define mmPDMA0_QM_CP_FENCE1_RDATA_2 0x4C8A2AC + +#define mmPDMA0_QM_CP_FENCE1_RDATA_3 0x4C8A2B0 + +#define mmPDMA0_QM_CP_FENCE1_RDATA_4 0x4C8A2B4 + +#define mmPDMA0_QM_CP_FENCE2_RDATA_0 0x4C8A2B8 + +#define mmPDMA0_QM_CP_FENCE2_RDATA_1 0x4C8A2BC + +#define mmPDMA0_QM_CP_FENCE2_RDATA_2 0x4C8A2C0 + +#define mmPDMA0_QM_CP_FENCE2_RDATA_3 0x4C8A2C4 + +#define mmPDMA0_QM_CP_FENCE2_RDATA_4 0x4C8A2C8 + +#define mmPDMA0_QM_CP_FENCE3_RDATA_0 0x4C8A2CC + +#define mmPDMA0_QM_CP_FENCE3_RDATA_1 0x4C8A2D0 + +#define mmPDMA0_QM_CP_FENCE3_RDATA_2 0x4C8A2D4 + +#define mmPDMA0_QM_CP_FENCE3_RDATA_3 0x4C8A2D8 + +#define mmPDMA0_QM_CP_FENCE3_RDATA_4 0x4C8A2DC + +#define mmPDMA0_QM_CP_FENCE0_CNT_0 0x4C8A2E0 + +#define mmPDMA0_QM_CP_FENCE0_CNT_1 0x4C8A2E4 + +#define mmPDMA0_QM_CP_FENCE0_CNT_2 0x4C8A2E8 + +#define mmPDMA0_QM_CP_FENCE0_CNT_3 0x4C8A2EC + +#define mmPDMA0_QM_CP_FENCE0_CNT_4 0x4C8A2F0 + +#define mmPDMA0_QM_CP_FENCE1_CNT_0 0x4C8A2F4 + +#define mmPDMA0_QM_CP_FENCE1_CNT_1 0x4C8A2F8 + +#define mmPDMA0_QM_CP_FENCE1_CNT_2 0x4C8A2FC + +#define mmPDMA0_QM_CP_FENCE1_CNT_3 0x4C8A300 + +#define mmPDMA0_QM_CP_FENCE1_CNT_4 0x4C8A304 + +#define mmPDMA0_QM_CP_FENCE2_CNT_0 0x4C8A308 + +#define mmPDMA0_QM_CP_FENCE2_CNT_1 0x4C8A30C + +#define mmPDMA0_QM_CP_FENCE2_CNT_2 0x4C8A310 + +#define mmPDMA0_QM_CP_FENCE2_CNT_3 0x4C8A314 + +#define mmPDMA0_QM_CP_FENCE2_CNT_4 0x4C8A318 + +#define mmPDMA0_QM_CP_FENCE3_CNT_0 0x4C8A31C + +#define mmPDMA0_QM_CP_FENCE3_CNT_1 0x4C8A320 + +#define mmPDMA0_QM_CP_FENCE3_CNT_2 0x4C8A324 + +#define mmPDMA0_QM_CP_FENCE3_CNT_3 0x4C8A328 + +#define mmPDMA0_QM_CP_FENCE3_CNT_4 0x4C8A32C + +#define mmPDMA0_QM_CP_BARRIER_CFG 0x4C8A330 + +#define mmPDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0x4C8A334 + +#define mmPDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET 0x4C8A338 + +#define mmPDMA0_QM_CP_LDMA_TSIZE_OFFSET 0x4C8A33C + +#define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_0 0x4C8A340 + +#define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_1 0x4C8A344 + +#define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_2 0x4C8A348 + +#define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_3 0x4C8A34C + +#define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_4 0x4C8A350 + +#define mmPDMA0_QM_CP_STS_0 0x4C8A368 + +#define mmPDMA0_QM_CP_STS_1 0x4C8A36C + +#define mmPDMA0_QM_CP_STS_2 0x4C8A370 + +#define mmPDMA0_QM_CP_STS_3 0x4C8A374 + +#define mmPDMA0_QM_CP_STS_4 0x4C8A378 + +#define mmPDMA0_QM_CP_CURRENT_INST_LO_0 0x4C8A37C + +#define mmPDMA0_QM_CP_CURRENT_INST_LO_1 0x4C8A380 + +#define mmPDMA0_QM_CP_CURRENT_INST_LO_2 0x4C8A384 + +#define mmPDMA0_QM_CP_CURRENT_INST_LO_3 0x4C8A388 + +#define mmPDMA0_QM_CP_CURRENT_INST_LO_4 0x4C8A38C + +#define mmPDMA0_QM_CP_CURRENT_INST_HI_0 0x4C8A390 + +#define mmPDMA0_QM_CP_CURRENT_INST_HI_1 0x4C8A394 + +#define mmPDMA0_QM_CP_CURRENT_INST_HI_2 0x4C8A398 + +#define mmPDMA0_QM_CP_CURRENT_INST_HI_3 0x4C8A39C + +#define mmPDMA0_QM_CP_CURRENT_INST_HI_4 0x4C8A3A0 + +#define mmPDMA0_QM_CP_PRED_0 0x4C8A3A4 + +#define mmPDMA0_QM_CP_PRED_1 0x4C8A3A8 + +#define mmPDMA0_QM_CP_PRED_2 0x4C8A3AC + +#define mmPDMA0_QM_CP_PRED_3 0x4C8A3B0 + +#define mmPDMA0_QM_CP_PRED_4 0x4C8A3B4 + +#define mmPDMA0_QM_CP_PRED_UPEN_0 0x4C8A3B8 + +#define mmPDMA0_QM_CP_PRED_UPEN_1 0x4C8A3BC + +#define mmPDMA0_QM_CP_PRED_UPEN_2 0x4C8A3C0 + +#define mmPDMA0_QM_CP_PRED_UPEN_3 0x4C8A3C4 + +#define mmPDMA0_QM_CP_PRED_UPEN_4 0x4C8A3C8 + +#define mmPDMA0_QM_CP_DBG_0_0 0x4C8A3CC + +#define mmPDMA0_QM_CP_DBG_0_1 0x4C8A3D0 + +#define mmPDMA0_QM_CP_DBG_0_2 0x4C8A3D4 + +#define mmPDMA0_QM_CP_DBG_0_3 0x4C8A3D8 + +#define mmPDMA0_QM_CP_DBG_0_4 0x4C8A3DC + +#define mmPDMA0_QM_CP_CPDMA_UP_CRED_0 0x4C8A3E0 + +#define mmPDMA0_QM_CP_CPDMA_UP_CRED_1 0x4C8A3E4 + +#define mmPDMA0_QM_CP_CPDMA_UP_CRED_2 0x4C8A3E8 + +#define mmPDMA0_QM_CP_CPDMA_UP_CRED_3 0x4C8A3EC + +#define mmPDMA0_QM_CP_CPDMA_UP_CRED_4 0x4C8A3F0 + +#define mmPDMA0_QM_CP_IN_DATA_LO_0 0x4C8A3F4 + +#define mmPDMA0_QM_CP_IN_DATA_LO_1 0x4C8A3F8 + +#define mmPDMA0_QM_CP_IN_DATA_LO_2 0x4C8A3FC + +#define mmPDMA0_QM_CP_IN_DATA_LO_3 0x4C8A400 + +#define mmPDMA0_QM_CP_IN_DATA_LO_4 0x4C8A404 + +#define mmPDMA0_QM_CP_IN_DATA_HI_0 0x4C8A408 + +#define mmPDMA0_QM_CP_IN_DATA_HI_1 0x4C8A40C + +#define mmPDMA0_QM_CP_IN_DATA_HI_2 0x4C8A410 + +#define mmPDMA0_QM_CP_IN_DATA_HI_3 0x4C8A414 + +#define mmPDMA0_QM_CP_IN_DATA_HI_4 0x4C8A418 + +#define mmPDMA0_QM_PQC_HBW_BASE_LO_0 0x4C8A41C + +#define mmPDMA0_QM_PQC_HBW_BASE_LO_1 0x4C8A420 + +#define mmPDMA0_QM_PQC_HBW_BASE_LO_2 0x4C8A424 + +#define mmPDMA0_QM_PQC_HBW_BASE_LO_3 0x4C8A428 + +#define mmPDMA0_QM_PQC_HBW_BASE_HI_0 0x4C8A42C + +#define mmPDMA0_QM_PQC_HBW_BASE_HI_1 0x4C8A430 + +#define mmPDMA0_QM_PQC_HBW_BASE_HI_2 0x4C8A434 + +#define mmPDMA0_QM_PQC_HBW_BASE_HI_3 0x4C8A438 + +#define mmPDMA0_QM_PQC_SIZE_0 0x4C8A43C + +#define mmPDMA0_QM_PQC_SIZE_1 0x4C8A440 + +#define mmPDMA0_QM_PQC_SIZE_2 0x4C8A444 + +#define mmPDMA0_QM_PQC_SIZE_3 0x4C8A448 + +#define mmPDMA0_QM_PQC_PI_0 0x4C8A44C + +#define mmPDMA0_QM_PQC_PI_1 0x4C8A450 + +#define mmPDMA0_QM_PQC_PI_2 0x4C8A454 + +#define mmPDMA0_QM_PQC_PI_3 0x4C8A458 + +#define mmPDMA0_QM_PQC_LBW_WDATA_0 0x4C8A45C + +#define mmPDMA0_QM_PQC_LBW_WDATA_1 0x4C8A460 + +#define mmPDMA0_QM_PQC_LBW_WDATA_2 0x4C8A464 + +#define mmPDMA0_QM_PQC_LBW_WDATA_3 0x4C8A468 + +#define mmPDMA0_QM_PQC_LBW_BASE_LO_0 0x4C8A46C + +#define mmPDMA0_QM_PQC_LBW_BASE_LO_1 0x4C8A470 + +#define mmPDMA0_QM_PQC_LBW_BASE_LO_2 0x4C8A474 + +#define mmPDMA0_QM_PQC_LBW_BASE_LO_3 0x4C8A478 + +#define mmPDMA0_QM_PQC_LBW_BASE_HI_0 0x4C8A47C + +#define mmPDMA0_QM_PQC_LBW_BASE_HI_1 0x4C8A480 + +#define mmPDMA0_QM_PQC_LBW_BASE_HI_2 0x4C8A484 + +#define mmPDMA0_QM_PQC_LBW_BASE_HI_3 0x4C8A488 + +#define mmPDMA0_QM_PQC_CFG 0x4C8A48C + +#define mmPDMA0_QM_PQC_SECURE_PUSH_IND 0x4C8A490 + +#define mmPDMA0_QM_ARB_MASK 0x4C8A4A0 + +#define mmPDMA0_QM_ARB_CFG_0 0x4C8A4A4 + +#define mmPDMA0_QM_ARB_CHOICE_Q_PUSH 0x4C8A4A8 + +#define mmPDMA0_QM_ARB_WRR_WEIGHT_0 0x4C8A4AC + +#define mmPDMA0_QM_ARB_WRR_WEIGHT_1 0x4C8A4B0 + +#define mmPDMA0_QM_ARB_WRR_WEIGHT_2 0x4C8A4B4 + +#define mmPDMA0_QM_ARB_WRR_WEIGHT_3 0x4C8A4B8 + +#define mmPDMA0_QM_ARB_CFG_1 0x4C8A4BC + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_0 0x4C8A4C0 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_1 0x4C8A4C4 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_2 0x4C8A4C8 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_3 0x4C8A4CC + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_4 0x4C8A4D0 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_5 0x4C8A4D4 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_6 0x4C8A4D8 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_7 0x4C8A4DC + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_8 0x4C8A4E0 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_9 0x4C8A4E4 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_10 0x4C8A4E8 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_11 0x4C8A4EC + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_12 0x4C8A4F0 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_13 0x4C8A4F4 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_14 0x4C8A4F8 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_15 0x4C8A4FC + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_16 0x4C8A500 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_17 0x4C8A504 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_18 0x4C8A508 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_19 0x4C8A50C + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_20 0x4C8A510 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_21 0x4C8A514 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_22 0x4C8A518 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_23 0x4C8A51C + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_24 0x4C8A520 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_25 0x4C8A524 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_26 0x4C8A528 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_27 0x4C8A52C + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_28 0x4C8A530 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_29 0x4C8A534 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_30 0x4C8A538 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_31 0x4C8A53C + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_32 0x4C8A540 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_33 0x4C8A544 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_34 0x4C8A548 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_35 0x4C8A54C + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_36 0x4C8A550 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_37 0x4C8A554 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_38 0x4C8A558 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_39 0x4C8A55C + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_40 0x4C8A560 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_41 0x4C8A564 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_42 0x4C8A568 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_43 0x4C8A56C + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_44 0x4C8A570 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_45 0x4C8A574 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_46 0x4C8A578 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_47 0x4C8A57C + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_48 0x4C8A580 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_49 0x4C8A584 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_50 0x4C8A588 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_51 0x4C8A58C + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_52 0x4C8A590 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_53 0x4C8A594 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_54 0x4C8A598 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_55 0x4C8A59C + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_56 0x4C8A5A0 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_57 0x4C8A5A4 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_58 0x4C8A5A8 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_59 0x4C8A5AC + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_60 0x4C8A5B0 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_61 0x4C8A5B4 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_62 0x4C8A5B8 + +#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_63 0x4C8A5BC + +#define mmPDMA0_QM_ARB_MST_CRED_INC 0x4C8A5E0 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0 0x4C8A5E4 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1 0x4C8A5E8 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2 0x4C8A5EC + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3 0x4C8A5F0 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4 0x4C8A5F4 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5 0x4C8A5F8 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6 0x4C8A5FC + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7 0x4C8A600 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8 0x4C8A604 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9 0x4C8A608 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10 0x4C8A60C + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11 0x4C8A610 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12 0x4C8A614 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13 0x4C8A618 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14 0x4C8A61C + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15 0x4C8A620 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16 0x4C8A624 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17 0x4C8A628 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18 0x4C8A62C + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19 0x4C8A630 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20 0x4C8A634 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21 0x4C8A638 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22 0x4C8A63C + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23 0x4C8A640 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24 0x4C8A644 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25 0x4C8A648 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26 0x4C8A64C + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27 0x4C8A650 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28 0x4C8A654 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29 0x4C8A658 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30 0x4C8A65C + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31 0x4C8A660 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32 0x4C8A664 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33 0x4C8A668 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34 0x4C8A66C + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35 0x4C8A670 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36 0x4C8A674 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37 0x4C8A678 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38 0x4C8A67C + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39 0x4C8A680 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40 0x4C8A684 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41 0x4C8A688 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42 0x4C8A68C + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43 0x4C8A690 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44 0x4C8A694 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45 0x4C8A698 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46 0x4C8A69C + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47 0x4C8A6A0 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48 0x4C8A6A4 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49 0x4C8A6A8 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50 0x4C8A6AC + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51 0x4C8A6B0 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52 0x4C8A6B4 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53 0x4C8A6B8 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54 0x4C8A6BC + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55 0x4C8A6C0 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56 0x4C8A6C4 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57 0x4C8A6C8 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58 0x4C8A6CC + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59 0x4C8A6D0 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60 0x4C8A6D4 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61 0x4C8A6D8 + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62 0x4C8A6DC + +#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63 0x4C8A6E0 + +#define mmPDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x4C8A704 + +#define mmPDMA0_QM_ARB_MST_SLAVE_EN 0x4C8A708 + +#define mmPDMA0_QM_ARB_MST_SLAVE_EN_1 0x4C8A70C + +#define mmPDMA0_QM_ARB_SLV_CHOICE_WDT 0x4C8A710 + +#define mmPDMA0_QM_ARB_SLV_ID 0x4C8A714 + +#define mmPDMA0_QM_ARB_MST_QUIET_PER 0x4C8A718 + +#define mmPDMA0_QM_ARB_MSG_MAX_INFLIGHT 0x4C8A744 + +#define mmPDMA0_QM_ARB_BASE_LO 0x4C8A754 + +#define mmPDMA0_QM_ARB_BASE_HI 0x4C8A758 + +#define mmPDMA0_QM_ARB_STATE_STS 0x4C8A780 + +#define mmPDMA0_QM_ARB_CHOICE_FULLNESS_STS 0x4C8A784 + +#define mmPDMA0_QM_ARB_MSG_STS 0x4C8A788 + +#define mmPDMA0_QM_ARB_SLV_CHOICE_Q_HEAD 0x4C8A78C + +#define mmPDMA0_QM_ARB_ERR_CAUSE 0x4C8A79C + +#define mmPDMA0_QM_ARB_ERR_MSG_EN 0x4C8A7A0 + +#define mmPDMA0_QM_ARB_ERR_STS_DRP 0x4C8A7A8 + +#define mmPDMA0_QM_ARB_MST_CRED_STS 0x4C8A7B0 + +#define mmPDMA0_QM_ARB_MST_CRED_STS_1 0x4C8A7B4 + +#define mmPDMA0_QM_CSMR_STRICT_PRIO_CFG 0x4C8A7FC + +#define mmPDMA0_QM_ARC_CQ_CFG0 0x4C8A800 + +#define mmPDMA0_QM_ARC_CQ_CFG1 0x4C8A804 + +#define mmPDMA0_QM_ARC_CQ_PTR_LO 0x4C8A808 + +#define mmPDMA0_QM_ARC_CQ_PTR_HI 0x4C8A80C + +#define mmPDMA0_QM_ARC_CQ_TSIZE 0x4C8A810 + +#define mmPDMA0_QM_ARC_CQ_CTL 0x4C8A814 + +#define mmPDMA0_QM_ARC_CQ_IFIFO_STS 0x4C8A81C + +#define mmPDMA0_QM_ARC_CQ_STS0 0x4C8A820 + +#define mmPDMA0_QM_ARC_CQ_STS1 0x4C8A824 + +#define mmPDMA0_QM_ARC_CQ_TSIZE_STS 0x4C8A828 + +#define mmPDMA0_QM_ARC_CQ_PTR_LO_STS 0x4C8A82C + +#define mmPDMA0_QM_ARC_CQ_PTR_HI_STS 0x4C8A830 + +#define mmPDMA0_QM_CP_WR_ARC_ADDR_HI 0x4C8A834 + +#define mmPDMA0_QM_CP_WR_ARC_ADDR_LO 0x4C8A838 + +#define mmPDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI 0x4C8A83C + +#define mmPDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO 0x4C8A840 + +#define mmPDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI 0x4C8A844 + +#define mmPDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO 0x4C8A848 + +#define mmPDMA0_QM_CQ_IFIFO_MSG_BASE_HI 0x4C8A84C + +#define mmPDMA0_QM_CQ_IFIFO_MSG_BASE_LO 0x4C8A850 + +#define mmPDMA0_QM_CQ_CTL_MSG_BASE_HI 0x4C8A854 + +#define mmPDMA0_QM_CQ_CTL_MSG_BASE_LO 0x4C8A858 + +#define mmPDMA0_QM_ADDR_OVRD 0x4C8A85C + +#define mmPDMA0_QM_CQ_IFIFO_CI_0 0x4C8A860 + +#define mmPDMA0_QM_CQ_IFIFO_CI_1 0x4C8A864 + +#define mmPDMA0_QM_CQ_IFIFO_CI_2 0x4C8A868 + +#define mmPDMA0_QM_CQ_IFIFO_CI_3 0x4C8A86C + +#define mmPDMA0_QM_CQ_IFIFO_CI_4 0x4C8A870 + +#define mmPDMA0_QM_ARC_CQ_IFIFO_CI 0x4C8A874 + +#define mmPDMA0_QM_CQ_CTL_CI_0 0x4C8A878 + +#define mmPDMA0_QM_CQ_CTL_CI_1 0x4C8A87C + +#define mmPDMA0_QM_CQ_CTL_CI_2 0x4C8A880 + +#define mmPDMA0_QM_CQ_CTL_CI_3 0x4C8A884 + +#define mmPDMA0_QM_CQ_CTL_CI_4 0x4C8A888 + +#define mmPDMA0_QM_ARC_CQ_CTL_CI 0x4C8A88C + +#define mmPDMA0_QM_CP_CFG 0x4C8A890 + +#define mmPDMA0_QM_CP_EXT_SWITCH 0x4C8A894 + +#define mmPDMA0_QM_CP_SWITCH_WD_SET 0x4C8A898 + +#define mmPDMA0_QM_CP_SWITCH_WD 0x4C8A89C + +#define mmPDMA0_QM_ARC_LB_ADDR_BASE_LO 0x4C8A8A4 + +#define mmPDMA0_QM_ARC_LB_ADDR_BASE_HI 0x4C8A8A8 + +#define mmPDMA0_QM_ENGINE_BASE_ADDR_HI 0x4C8A8AC + +#define mmPDMA0_QM_ENGINE_BASE_ADDR_LO 0x4C8A8B0 + +#define mmPDMA0_QM_ENGINE_ADDR_RANGE_SIZE 0x4C8A8B4 + +#define mmPDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI 0x4C8A8B8 + +#define mmPDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO 0x4C8A8BC + +#define mmPDMA0_QM_QM_BASE_ADDR_HI 0x4C8A8C0 + +#define mmPDMA0_QM_QM_BASE_ADDR_LO 0x4C8A8C4 + +#define mmPDMA0_QM_ARC_PQC_SECURE_PUSH_IND 0x4C8A8C8 + +#define mmPDMA0_QM_PQC_STS_0_0 0x4C8A8D0 + +#define mmPDMA0_QM_PQC_STS_0_1 0x4C8A8D4 + +#define mmPDMA0_QM_PQC_STS_0_2 0x4C8A8D8 + +#define mmPDMA0_QM_PQC_STS_0_3 0x4C8A8DC + +#define mmPDMA0_QM_PQC_STS_1_0 0x4C8A8E0 + +#define mmPDMA0_QM_PQC_STS_1_1 0x4C8A8E4 + +#define mmPDMA0_QM_PQC_STS_1_2 0x4C8A8E8 + +#define mmPDMA0_QM_PQC_STS_1_3 0x4C8A8EC + +#define mmPDMA0_QM_SEI_STATUS 0x4C8A8F0 + +#define mmPDMA0_QM_SEI_MASK 0x4C8A8F4 + +#define mmPDMA0_QM_GLBL_ERR_ADDR_LO 0x4C8AD00 + +#define mmPDMA0_QM_GLBL_ERR_ADDR_HI 0x4C8AD04 + +#define mmPDMA0_QM_GLBL_ERR_WDATA 0x4C8AD08 + +#define mmPDMA0_QM_L2H_MASK_LO 0x4C8AD14 + +#define mmPDMA0_QM_L2H_MASK_HI 0x4C8AD18 + +#define mmPDMA0_QM_L2H_CMPR_LO 0x4C8AD1C + +#define mmPDMA0_QM_L2H_CMPR_HI 0x4C8AD20 + +#define mmPDMA0_QM_LOCAL_RANGE_BASE 0x4C8AD24 + +#define mmPDMA0_QM_LOCAL_RANGE_SIZE 0x4C8AD28 + +#define mmPDMA0_QM_HBW_RD_RATE_LIM_CFG_1 0x4C8AD30 + +#define mmPDMA0_QM_LBW_WR_RATE_LIM_CFG_0 0x4C8AD34 + +#define mmPDMA0_QM_LBW_WR_RATE_LIM_CFG_1 0x4C8AD38 + +#define mmPDMA0_QM_HBW_RD_RATE_LIM_CFG_0 0x4C8AD3C + +#define mmPDMA0_QM_IND_GW_APB_CFG 0x4C8AD40 + +#define mmPDMA0_QM_IND_GW_APB_WDATA 0x4C8AD44 + +#define mmPDMA0_QM_IND_GW_APB_RDATA 0x4C8AD48 + +#define mmPDMA0_QM_IND_GW_APB_STATUS 0x4C8AD4C + +#define mmPDMA0_QM_PERF_CNT_FREE_LO 0x4C8AD60 + +#define mmPDMA0_QM_PERF_CNT_FREE_HI 0x4C8AD64 + +#define mmPDMA0_QM_PERF_CNT_IDLE_LO 0x4C8AD68 + +#define mmPDMA0_QM_PERF_CNT_IDLE_HI 0x4C8AD6C + +#define mmPDMA0_QM_PERF_CNT_CFG 0x4C8AD70 + +#endif /* ASIC_REG_PDMA0_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma1_core_ctx_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma1_core_ctx_axuser_regs.h new file mode 100644 index 000000000000..ccc6dfd22dd7 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma1_core_ctx_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA1_CORE_CTX_AXUSER_REGS_H_ +#define ASIC_REG_PDMA1_CORE_CTX_AXUSER_REGS_H_ + +/* + ***************************************** + * PDMA1_CORE_CTX_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmPDMA1_CORE_CTX_AXUSER_HB_ASID 0x4C9B800 + +#define mmPDMA1_CORE_CTX_AXUSER_HB_MMU_BP 0x4C9B804 + +#define mmPDMA1_CORE_CTX_AXUSER_HB_STRONG_ORDER 0x4C9B808 + +#define mmPDMA1_CORE_CTX_AXUSER_HB_NO_SNOOP 0x4C9B80C + +#define mmPDMA1_CORE_CTX_AXUSER_HB_WR_REDUCTION 0x4C9B810 + +#define mmPDMA1_CORE_CTX_AXUSER_HB_RD_ATOMIC 0x4C9B814 + +#define mmPDMA1_CORE_CTX_AXUSER_HB_QOS 0x4C9B818 + +#define mmPDMA1_CORE_CTX_AXUSER_HB_RSVD 0x4C9B81C + +#define mmPDMA1_CORE_CTX_AXUSER_HB_EMEM_CPAGE 0x4C9B820 + +#define mmPDMA1_CORE_CTX_AXUSER_HB_CORE 0x4C9B824 + +#define mmPDMA1_CORE_CTX_AXUSER_E2E_COORD 0x4C9B828 + +#define mmPDMA1_CORE_CTX_AXUSER_HB_WR_OVRD_LO 0x4C9B830 + +#define mmPDMA1_CORE_CTX_AXUSER_HB_WR_OVRD_HI 0x4C9B834 + +#define mmPDMA1_CORE_CTX_AXUSER_HB_RD_OVRD_LO 0x4C9B838 + +#define mmPDMA1_CORE_CTX_AXUSER_HB_RD_OVRD_HI 0x4C9B83C + +#define mmPDMA1_CORE_CTX_AXUSER_LB_COORD 0x4C9B840 + +#define mmPDMA1_CORE_CTX_AXUSER_LB_LOCK 0x4C9B844 + +#define mmPDMA1_CORE_CTX_AXUSER_LB_RSVD 0x4C9B848 + +#define mmPDMA1_CORE_CTX_AXUSER_LB_OVRD 0x4C9B84C + +#endif /* ASIC_REG_PDMA1_CORE_CTX_AXUSER_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma1_qm_axuser_nonsecured_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma1_qm_axuser_nonsecured_regs.h new file mode 100644 index 000000000000..5fd72d050fff --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pdma1_qm_axuser_nonsecured_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA1_QM_AXUSER_NONSECURED_REGS_H_ +#define ASIC_REG_PDMA1_QM_AXUSER_NONSECURED_REGS_H_ + +/* + ***************************************** + * PDMA1_QM_AXUSER_NONSECURED + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_ASID 0x4C9AB80 + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_MMU_BP 0x4C9AB84 + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x4C9AB88 + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x4C9AB8C + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x4C9AB90 + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x4C9AB94 + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_QOS 0x4C9AB98 + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_RSVD 0x4C9AB9C + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x4C9ABA0 + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_CORE 0x4C9ABA4 + +#define mmPDMA1_QM_AXUSER_NONSECURED_E2E_COORD 0x4C9ABA8 + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x4C9ABB0 + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x4C9ABB4 + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x4C9ABB8 + +#define mmPDMA1_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x4C9ABBC + +#define mmPDMA1_QM_AXUSER_NONSECURED_LB_COORD 0x4C9ABC0 + +#define mmPDMA1_QM_AXUSER_NONSECURED_LB_LOCK 0x4C9ABC4 + +#define mmPDMA1_QM_AXUSER_NONSECURED_LB_RSVD 0x4C9ABC8 + +#define mmPDMA1_QM_AXUSER_NONSECURED_LB_OVRD 0x4C9ABCC + +#endif /* ASIC_REG_PDMA1_QM_AXUSER_NONSECURED_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_masks.h new file mode 100644 index 000000000000..0276506ea523 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_masks.h @@ -0,0 +1,334 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PMMU_HBW_STLB_MASKS_H_ +#define ASIC_REG_PMMU_HBW_STLB_MASKS_H_ + +/* + ***************************************** + * PMMU_HBW_STLB + * (Prototype: STLB) + ***************************************** + */ + +/* PMMU_HBW_STLB_BUSY */ +#define PMMU_HBW_STLB_BUSY_BUSY_SHIFT 0 +#define PMMU_HBW_STLB_BUSY_BUSY_MASK 0xFFFFFFFF + +/* PMMU_HBW_STLB_ASID */ +#define PMMU_HBW_STLB_ASID_ASID_SHIFT 0 +#define PMMU_HBW_STLB_ASID_ASID_MASK 0x3FF + +/* PMMU_HBW_STLB_HOP0_PA43_12 */ +#define PMMU_HBW_STLB_HOP0_PA43_12_HOP0_PA43_12_SHIFT 0 +#define PMMU_HBW_STLB_HOP0_PA43_12_HOP0_PA43_12_MASK 0xFFFFFFFF + +/* PMMU_HBW_STLB_HOP0_PA63_44 */ +#define PMMU_HBW_STLB_HOP0_PA63_44_HOP0_PA63_44_SHIFT 0 +#define PMMU_HBW_STLB_HOP0_PA63_44_HOP0_PA63_44_MASK 0xFFFFF + +/* PMMU_HBW_STLB_CACHE_INV */ +#define PMMU_HBW_STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0 +#define PMMU_HBW_STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF +#define PMMU_HBW_STLB_CACHE_INV_INDEX_MASK_SHIFT 8 +#define PMMU_HBW_STLB_CACHE_INV_INDEX_MASK_MASK 0xFF00 + +/* PMMU_HBW_STLB_CACHE_INV_BASE_39_8 */ +#define PMMU_HBW_STLB_CACHE_INV_BASE_39_8_PA_SHIFT 0 +#define PMMU_HBW_STLB_CACHE_INV_BASE_39_8_PA_MASK 0xFFFFFFFF + +/* PMMU_HBW_STLB_CACHE_INV_BASE_63_40 */ +#define PMMU_HBW_STLB_CACHE_INV_BASE_63_40_PA_SHIFT 0 +#define PMMU_HBW_STLB_CACHE_INV_BASE_63_40_PA_MASK 0xFFFFFF + +/* PMMU_HBW_STLB_STLB_FEATURE_EN */ +#define PMMU_HBW_STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_SHIFT 0 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_MASK 0x1 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_SHIFT 1 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_MASK 0x2 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_LOOKUP_EN_SHIFT 2 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_LOOKUP_EN_MASK 0x4 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_BYPASS_SHIFT 3 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_BYPASS_MASK 0x8 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_BANK_STOP_SHIFT 4 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_BANK_STOP_MASK 0x10 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_TRACE_EN_SHIFT 5 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_TRACE_EN_MASK 0x20 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_FOLLOWER_EN_SHIFT 6 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK 0x40 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_CACHING_EN_SHIFT 7 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_CACHING_EN_MASK 0x1F80 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_FOLLOWING_NUM_LIMIT_SHIFT 13 +#define PMMU_HBW_STLB_STLB_FEATURE_EN_FOLLOWING_NUM_LIMIT_MASK 0xE000 + +/* PMMU_HBW_STLB_STLB_AXI_CACHE */ +#define PMMU_HBW_STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_SHIFT 0 +#define PMMU_HBW_STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_MASK 0xF +#define PMMU_HBW_STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_SHIFT 4 +#define PMMU_HBW_STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_MASK 0xF0 +#define PMMU_HBW_STLB_STLB_AXI_CACHE_INV_ARCACHE_SHIFT 8 +#define PMMU_HBW_STLB_STLB_AXI_CACHE_INV_ARCACHE_MASK 0xF00 + +/* PMMU_HBW_STLB_HOP_CONFIGURATION */ +#define PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_HOP_SHIFT 0 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_HOP_MASK 0x7 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_SHIFT 4 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_MASK 0x70 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_SHIFT 8 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_MASK 0x700 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_LAST_HOP_SHIFT 12 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_LAST_HOP_MASK 0x7000 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_SHIFT 16 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_MASK 0x70000 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_SHIFT 20 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_MASK 0x100000 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_SHIFT 21 +#define PMMU_HBW_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_MASK 0x7E00000 + +/* PMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_63_32 */ +#define PMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_SHIFT 0 +#define PMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_MASK 0xFFFFFFFF + +/* PMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_31_0 */ +#define PMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_31_0_R_SHIFT 0 +#define PMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_31_0_R_MASK 0xFFFFFFFF + +/* PMMU_HBW_STLB_INV_ALL_START */ +#define PMMU_HBW_STLB_INV_ALL_START_R_SHIFT 0 +#define PMMU_HBW_STLB_INV_ALL_START_R_MASK 0x1 + +/* PMMU_HBW_STLB_INV_ALL_SET */ +#define PMMU_HBW_STLB_INV_ALL_SET_R_SHIFT 0 +#define PMMU_HBW_STLB_INV_ALL_SET_R_MASK 0xFF + +/* PMMU_HBW_STLB_INV_PS */ +#define PMMU_HBW_STLB_INV_PS_R_SHIFT 0 +#define PMMU_HBW_STLB_INV_PS_R_MASK 0x3 + +/* PMMU_HBW_STLB_INV_CONSUMER_INDEX */ +#define PMMU_HBW_STLB_INV_CONSUMER_INDEX_R_SHIFT 0 +#define PMMU_HBW_STLB_INV_CONSUMER_INDEX_R_MASK 0xFF + +/* PMMU_HBW_STLB_INV_HIT_COUNT */ +#define PMMU_HBW_STLB_INV_HIT_COUNT_R_SHIFT 0 +#define PMMU_HBW_STLB_INV_HIT_COUNT_R_MASK 0x7FF + +/* PMMU_HBW_STLB_INV_SET */ +#define PMMU_HBW_STLB_INV_SET_R_SHIFT 0 +#define PMMU_HBW_STLB_INV_SET_R_MASK 0xFF + +/* PMMU_HBW_STLB_SRAM_INIT */ +#define PMMU_HBW_STLB_SRAM_INIT_BUSY_TAG_SHIFT 0 +#define PMMU_HBW_STLB_SRAM_INIT_BUSY_TAG_MASK 0x3 +#define PMMU_HBW_STLB_SRAM_INIT_BUSY_SLICE_SHIFT 2 +#define PMMU_HBW_STLB_SRAM_INIT_BUSY_SLICE_MASK 0xC +#define PMMU_HBW_STLB_SRAM_INIT_BUSY_DATA_SHIFT 4 +#define PMMU_HBW_STLB_SRAM_INIT_BUSY_DATA_MASK 0x10 + +/* PMMU_HBW_STLB_MEM_CACHE_INVALIDATION */ + +/* PMMU_HBW_STLB_MEM_CACHE_INV_STATUS */ +#define PMMU_HBW_STLB_MEM_CACHE_INV_STATUS_INVALIDATE_DONE_SHIFT 0 +#define PMMU_HBW_STLB_MEM_CACHE_INV_STATUS_INVALIDATE_DONE_MASK 0x1 +#define PMMU_HBW_STLB_MEM_CACHE_INV_STATUS_CACHE_IDLE_SHIFT 1 +#define PMMU_HBW_STLB_MEM_CACHE_INV_STATUS_CACHE_IDLE_MASK 0x2 + +/* PMMU_HBW_STLB_MEM_CACHE_BASE_38_7 */ +#define PMMU_HBW_STLB_MEM_CACHE_BASE_38_7_R_SHIFT 0 +#define PMMU_HBW_STLB_MEM_CACHE_BASE_38_7_R_MASK 0xFFFFFFFF + +/* PMMU_HBW_STLB_MEM_CACHE_BASE_63_39 */ +#define PMMU_HBW_STLB_MEM_CACHE_BASE_63_39_R_SHIFT 0 +#define PMMU_HBW_STLB_MEM_CACHE_BASE_63_39_R_MASK 0x1FFFFFF + +/* PMMU_HBW_STLB_MEM_CACHE_CONFIG */ +#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_CACHE_HOP_EN_SHIFT 0 +#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_CACHE_HOP_EN_MASK 0x3F +#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_CACHE_HOP_PREFETCH_EN_SHIFT 6 +#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_CACHE_HOP_PREFETCH_EN_MASK 0xFC0 +#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_BYPASS_EN_SHIFT 12 +#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_BYPASS_EN_MASK 0x1000 +#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_RELEASE_INVALIDATE_SHIFT 13 +#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_RELEASE_INVALIDATE_MASK 0x2000 + +/* PMMU_HBW_STLB_SET_THRESHOLD_HOP5 */ +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP5_MIN_SHIFT 0 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP5_MIN_MASK 0x1FF +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP5_MAX_SHIFT 9 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP5_MAX_MASK 0x3FE00 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP5_MASK_SHIFT 18 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP5_MASK_MASK 0x7FC0000 + +/* PMMU_HBW_STLB_SET_THRESHOLD_HOP4 */ +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP4_MIN_SHIFT 0 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP4_MIN_MASK 0x1FF +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP4_MAX_SHIFT 9 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP4_MAX_MASK 0x3FE00 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP4_MASK_SHIFT 18 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP4_MASK_MASK 0x7FC0000 + +/* PMMU_HBW_STLB_SET_THRESHOLD_HOP3 */ +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP3_MIN_SHIFT 0 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP3_MIN_MASK 0x1FF +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP3_MAX_SHIFT 9 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP3_MAX_MASK 0x3FE00 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP3_MASK_SHIFT 18 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP3_MASK_MASK 0x7FC0000 + +/* PMMU_HBW_STLB_SET_THRESHOLD_HOP2 */ +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP2_MIN_SHIFT 0 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP2_MIN_MASK 0x1FF +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP2_MAX_SHIFT 9 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP2_MAX_MASK 0x3FE00 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP2_MASK_SHIFT 18 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP2_MASK_MASK 0x7FC0000 + +/* PMMU_HBW_STLB_SET_THRESHOLD_HOP1 */ +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP1_MIN_SHIFT 0 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP1_MIN_MASK 0x1FF +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP1_MAX_SHIFT 9 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP1_MAX_MASK 0x3FE00 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP1_MASK_SHIFT 18 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP1_MASK_MASK 0x7FC0000 + +/* PMMU_HBW_STLB_SET_THRESHOLD_HOP0 */ +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP0_MIN_SHIFT 0 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP0_MIN_MASK 0x1FF +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP0_MAX_SHIFT 9 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP0_MAX_MASK 0x3FE00 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP0_MASK_SHIFT 18 +#define PMMU_HBW_STLB_SET_THRESHOLD_HOP0_MASK_MASK 0x7FC0000 + +/* PMMU_HBW_STLB_MULTI_HIT_INTERRUPT_CLR */ + +/* PMMU_HBW_STLB_MULTI_HIT_INTERRUPT_MASK */ +#define PMMU_HBW_STLB_MULTI_HIT_INTERRUPT_MASK_R_SHIFT 0 +#define PMMU_HBW_STLB_MULTI_HIT_INTERRUPT_MASK_R_MASK 0x1 + +/* PMMU_HBW_STLB_MEM_L0_CACHE_CFG */ +#define PMMU_HBW_STLB_MEM_L0_CACHE_CFG_PLRU_EVICTION_SHIFT 0 +#define PMMU_HBW_STLB_MEM_L0_CACHE_CFG_PLRU_EVICTION_MASK 0x1 +#define PMMU_HBW_STLB_MEM_L0_CACHE_CFG_CACHE_STOP_SHIFT 1 +#define PMMU_HBW_STLB_MEM_L0_CACHE_CFG_CACHE_STOP_MASK 0x2 +#define PMMU_HBW_STLB_MEM_L0_CACHE_CFG_INV_WRITEBACK_SHIFT 2 +#define PMMU_HBW_STLB_MEM_L0_CACHE_CFG_INV_WRITEBACK_MASK 0x4 + +/* PMMU_HBW_STLB_MEM_READ_ARPROT */ +#define PMMU_HBW_STLB_MEM_READ_ARPROT_R_SHIFT 0 +#define PMMU_HBW_STLB_MEM_READ_ARPROT_R_MASK 0x7 + +/* PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION */ +#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_SHIFT 0 +#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_MASK \ +0x1 +#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_SHIFT 1 +#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_MASK 0x2 +#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_SHIFT 2 +#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_MASK 0xFFC + +/* PMMU_HBW_STLB_RANGE_INV_START_LSB */ +#define PMMU_HBW_STLB_RANGE_INV_START_LSB_INV_START_LSB_SHIFT 0 +#define PMMU_HBW_STLB_RANGE_INV_START_LSB_INV_START_LSB_MASK 0xFFFFFFFF + +/* PMMU_HBW_STLB_RANGE_INV_START_MSB */ +#define PMMU_HBW_STLB_RANGE_INV_START_MSB_INV_START_MSB_SHIFT 0 +#define PMMU_HBW_STLB_RANGE_INV_START_MSB_INV_START_MSB_MASK 0xFFFFF + +/* PMMU_HBW_STLB_RANGE_INV_END_LSB */ +#define PMMU_HBW_STLB_RANGE_INV_END_LSB_INV_END_LSB_SHIFT 0 +#define PMMU_HBW_STLB_RANGE_INV_END_LSB_INV_END_LSB_MASK 0xFFFFFFFF + +/* PMMU_HBW_STLB_RANGE_INV_END_MSB */ +#define PMMU_HBW_STLB_RANGE_INV_END_MSB_INV_END_MSB_SHIFT 0 +#define PMMU_HBW_STLB_RANGE_INV_END_MSB_INV_END_MSB_MASK 0xFFFFF + +/* PMMU_HBW_STLB_ASID_SCRAMBLER_CTRL */ +#define PMMU_HBW_STLB_ASID_SCRAMBLER_CTRL_SCRAMBLER_SCRAM_EN_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCRAMBLER_CTRL_SCRAMBLER_SCRAM_EN_MASK 0x1 + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_0 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_1 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_2 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_3 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_4 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_5 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_6 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_7 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_8 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_9 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_10 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_11 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_11_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_11_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_12 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_12_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_12_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_13 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_13_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_13_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_14 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_14_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_14_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_15 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_15_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_15_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_16 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_16_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_16_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_17 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_17_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_17_ASID_POLY_MATRIX_H3_MASK 0x1FF + +/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_18 */ +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_18_ASID_POLY_MATRIX_H3_SHIFT 0 +#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_18_ASID_POLY_MATRIX_H3_MASK 0x1FF + +#endif /* ASIC_REG_PMMU_HBW_STLB_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_regs.h new file mode 100644 index 000000000000..87c66c08e24a --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_regs.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PMMU_HBW_STLB_REGS_H_ +#define ASIC_REG_PMMU_HBW_STLB_REGS_H_ + +/* + ***************************************** + * PMMU_HBW_STLB + * (Prototype: STLB) + ***************************************** + */ + +#define mmPMMU_HBW_STLB_BUSY 0x4D01000 + +#define mmPMMU_HBW_STLB_ASID 0x4D01004 + +#define mmPMMU_HBW_STLB_HOP0_PA43_12 0x4D01008 + +#define mmPMMU_HBW_STLB_HOP0_PA63_44 0x4D0100C + +#define mmPMMU_HBW_STLB_CACHE_INV 0x4D01010 + +#define mmPMMU_HBW_STLB_CACHE_INV_BASE_39_8 0x4D01014 + +#define mmPMMU_HBW_STLB_CACHE_INV_BASE_63_40 0x4D01018 + +#define mmPMMU_HBW_STLB_STLB_FEATURE_EN 0x4D0101C + +#define mmPMMU_HBW_STLB_STLB_AXI_CACHE 0x4D01020 + +#define mmPMMU_HBW_STLB_HOP_CONFIGURATION 0x4D01024 + +#define mmPMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_63_32 0x4D01028 + +#define mmPMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_31_0 0x4D0102C + +#define mmPMMU_HBW_STLB_INV_ALL_START 0x4D01034 + +#define mmPMMU_HBW_STLB_INV_ALL_SET 0x4D01038 + +#define mmPMMU_HBW_STLB_INV_PS 0x4D0103C + +#define mmPMMU_HBW_STLB_INV_CONSUMER_INDEX 0x4D01040 + +#define mmPMMU_HBW_STLB_INV_HIT_COUNT 0x4D01044 + +#define mmPMMU_HBW_STLB_INV_SET 0x4D01048 + +#define mmPMMU_HBW_STLB_SRAM_INIT 0x4D0104C + +#define mmPMMU_HBW_STLB_MEM_CACHE_INVALIDATION 0x4D01050 + +#define mmPMMU_HBW_STLB_MEM_CACHE_INV_STATUS 0x4D01054 + +#define mmPMMU_HBW_STLB_MEM_CACHE_BASE_38_7 0x4D01058 + +#define mmPMMU_HBW_STLB_MEM_CACHE_BASE_63_39 0x4D0105C + +#define mmPMMU_HBW_STLB_MEM_CACHE_CONFIG 0x4D01060 + +#define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP5 0x4D01064 + +#define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP4 0x4D01068 + +#define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP3 0x4D0106C + +#define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP2 0x4D01070 + +#define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP1 0x4D01074 + +#define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP0 0x4D01078 + +#define mmPMMU_HBW_STLB_MULTI_HIT_INTERRUPT_CLR 0x4D0107C + +#define mmPMMU_HBW_STLB_MULTI_HIT_INTERRUPT_MASK 0x4D01080 + +#define mmPMMU_HBW_STLB_MEM_L0_CACHE_CFG 0x4D01084 + +#define mmPMMU_HBW_STLB_MEM_READ_ARPROT 0x4D01088 + +#define mmPMMU_HBW_STLB_RANGE_CACHE_INVALIDATION 0x4D0108C + +#define mmPMMU_HBW_STLB_RANGE_INV_START_LSB 0x4D01090 + +#define mmPMMU_HBW_STLB_RANGE_INV_START_MSB 0x4D01094 + +#define mmPMMU_HBW_STLB_RANGE_INV_END_LSB 0x4D01098 + +#define mmPMMU_HBW_STLB_RANGE_INV_END_MSB 0x4D0109C + +#define mmPMMU_HBW_STLB_ASID_SCRAMBLER_CTRL 0x4D01100 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_0 0x4D01104 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_1 0x4D01108 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_2 0x4D0110C + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_3 0x4D01110 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_4 0x4D01114 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_5 0x4D01118 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_6 0x4D0111C + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_7 0x4D01120 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_8 0x4D01124 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_9 0x4D01128 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_10 0x4D0112C + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_11 0x4D01130 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_12 0x4D01134 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_13 0x4D01138 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_14 0x4D0113C + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_15 0x4D01140 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_16 0x4D01144 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_17 0x4D01148 + +#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_18 0x4D0114C + +#endif /* ASIC_REG_PMMU_HBW_STLB_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/pmmu_pif_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pmmu_pif_regs.h new file mode 100644 index 000000000000..dd12793734b4 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/pmmu_pif_regs.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PMMU_PIF_REGS_H_ +#define ASIC_REG_PMMU_PIF_REGS_H_ + +/* + ***************************************** + * PMMU_PIF + * (Prototype: PIF) + ***************************************** + */ + +#define mmPMMU_PIF_WR_CORE_CREDITS_THRESHOLD 0x4D03000 + +#define mmPMMU_PIF_RD_CORE_CREDITS_THRESHOLD 0x4D03004 + +#define mmPMMU_PIF_CORE_CREDITS_THRESHOLD 0x4D03008 + +#define mmPMMU_PIF_CORE_SEPARATION_DISABLE 0x4D0300C + +#define mmPMMU_PIF_DISABLE_E2E_CREDITS 0x4D03010 + +#define mmPMMU_PIF_RATE_LIMITER_ENABLE 0x4D03014 + +#define mmPMMU_PIF_RATE_LIMITER_TOKEN_RESET 0x4D03018 + +#define mmPMMU_PIF_RATE_LIMITER_SATURATION 0x4D0301C + +#define mmPMMU_PIF_RATE_LIMITER_TIMEOUT_LSB 0x4D03020 + +#define mmPMMU_PIF_RATE_LIMITER_TIMEOUT_MSB 0x4D03024 + +#define mmPMMU_PIF_ARB_TYPE 0x4D03028 + +#define mmPMMU_PIF_CLOCK_GATE_CONFIG 0x4D0302C + +#define mmPMMU_PIF_CLOCK_GATE_ACTIVE 0x4D03030 + +#define mmPMMU_PIF_SPI_INTERRUPT_CAUSE 0x4D03034 + +#define mmPMMU_PIF_SPI_INTERRUPT_CAUSE_MASK 0x4D03038 + +#define mmPMMU_PIF_SPI_INTERRUPT_REG 0x4D0303C + +#define mmPMMU_PIF_SPI_INTERRUPT_MASK 0x4D03040 + +#define mmPMMU_PIF_SEI_INTERRUPT_CAUSE 0x4D03044 + +#define mmPMMU_PIF_SEI_INTERRUPT_CAUSE_MASK 0x4D03048 + +#define mmPMMU_PIF_SEI_INTERRUPT_REG 0x4D0304C + +#define mmPMMU_PIF_SEI_INTERRUPT_MASK 0x4D03050 + +#define mmPMMU_PIF_DEBUG_BUFFER_CNT_CTRL 0x4D03054 + +#define mmPMMU_PIF_DEBUG_WR_BUF_CNT 0x4D03058 + +#define mmPMMU_PIF_DEBUG_RD_BUF_CNT 0x4D0305C + +#define mmPMMU_PIF_DEBUG_WR_CORE_BUF_CNT 0x4D03060 + +#define mmPMMU_PIF_DEBUG_RD_CORE_BUF_CNT 0x4D03070 + +#define mmPMMU_PIF_DEBUG_WR_BUF_FULL 0x4D03080 + +#define mmPMMU_PIF_DEBUG_RD_BUF_FULL 0x4D03084 + +#define mmPMMU_PIF_E2E_ROUTING_CFG 0x4D03090 + +#define mmPMMU_PIF_E2E_ROUTING_CFG2 0x4D03094 + +#define mmPMMU_PIF_SPI_INTERRUPT_CLEAR 0x4D03100 + +#define mmPMMU_PIF_SEI_INTERRUPT_CLEAR 0x4D03104 + +#define mmPMMU_PIF_BASE_ADDR_PMMU 0x4D03200 + +#define mmPMMU_PIF_ADDR_MASK_PMMU 0x4D03204 + +#define mmPMMU_PIF_BASE_ADDR_PCI0 0x4D03208 + +#define mmPMMU_PIF_ADDR_MASK_PCI0 0x4D0320C + +#define mmPMMU_PIF_BASE_ADDR_PCI2 0x4D03210 + +#define mmPMMU_PIF_ADDR_MASK_PCI1 0x4D03214 + +#define mmPMMU_PIF_BASE_ADDR_PCI1 0x4D03218 + +#define mmPMMU_PIF_ADDR_MASK_PCI2 0x4D0321C + +#define mmPMMU_PIF_BASE_ADDR_TPC 0x4D03220 + +#define mmPMMU_PIF_ADDR_MASK_TPC 0x4D03224 + +#define mmPMMU_PIF_BASE_ADDR_DEC0 0x4D03228 + +#define mmPMMU_PIF_ADDR_MASK_DEC0 0x4D0322C + +#define mmPMMU_PIF_BASE_ADDR_DEC1 0x4D03230 + +#define mmPMMU_PIF_ADDR_MASK_DEC1 0x4D03234 + +#define mmPMMU_PIF_PMMU_DBG_BASE_ADDR 0x4D03300 + +#define mmPMMU_PIF_PMMU_DBG_ADDR_MASK 0x4D03304 + +#define mmPMMU_PIF_PCI_DBG_BASE_ADDR 0x4D03308 + +#define mmPMMU_PIF_PCI_DBG_ADDR_MASK 0x4D0330C + +#define mmPMMU_PIF_DEC0_DBG_BASE_ADDR 0x4D03310 + +#define mmPMMU_PIF_DEC0_DBG_ADDR_MASK 0x4D03314 + +#define mmPMMU_PIF_DEC1_DBG_BASE_ADDR 0x4D03318 + +#define mmPMMU_PIF_DEC1_DBG_ADDR_MASK 0x4D0331C + +#define mmPMMU_PIF_TPC_DBG_BASE_ADDR 0x4D03320 + +#define mmPMMU_PIF_TPC_DBG_ADDR_MASK 0x4D03324 + +#endif /* ASIC_REG_PMMU_PIF_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_etr_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_etr_masks.h new file mode 100644 index 000000000000..42e67c1059c4 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_etr_masks.h @@ -0,0 +1,311 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_ETR_MASKS_H_ +#define ASIC_REG_PSOC_ETR_MASKS_H_ + +/* + ***************************************** + * PSOC_ETR + * (Prototype: ETR) + ***************************************** + */ + +/* PSOC_ETR_RSZ */ +#define PSOC_ETR_RSZ_RSZ_ETR_SHIFT 0 +#define PSOC_ETR_RSZ_RSZ_ETR_MASK 0x7FFFFFFF + +/* PSOC_ETR_STS */ +#define PSOC_ETR_STS_FULL_SHIFT 0 +#define PSOC_ETR_STS_FULL_MASK 0x1 +#define PSOC_ETR_STS_TRIGGERED_SHIFT 1 +#define PSOC_ETR_STS_TRIGGERED_MASK 0x2 +#define PSOC_ETR_STS_TMCREADY_SHIFT 2 +#define PSOC_ETR_STS_TMCREADY_MASK 0x4 +#define PSOC_ETR_STS_FTEMPTY_SHIFT 3 +#define PSOC_ETR_STS_FTEMPTY_MASK 0x8 +#define PSOC_ETR_STS_EMPTY_SHIFT 4 +#define PSOC_ETR_STS_EMPTY_MASK 0x10 +#define PSOC_ETR_STS_MEMERR_SHIFT 5 +#define PSOC_ETR_STS_MEMERR_MASK 0x20 + +/* PSOC_ETR_RRD */ +#define PSOC_ETR_RRD_RRD_SHIFT 0 +#define PSOC_ETR_RRD_RRD_MASK 0xFFFFFFFF + +/* PSOC_ETR_RRP */ +#define PSOC_ETR_RRP_RRP_SHIFT 0 +#define PSOC_ETR_RRP_RRP_MASK 0xFFFFFFFF + +/* PSOC_ETR_RWP */ +#define PSOC_ETR_RWP_RWP_SHIFT 0 +#define PSOC_ETR_RWP_RWP_MASK 0xFFFFFFFF + +/* PSOC_ETR_TRG */ +#define PSOC_ETR_TRG_TRG_SHIFT 0 +#define PSOC_ETR_TRG_TRG_MASK 0xFFFFFFFF + +/* PSOC_ETR_CTL */ +#define PSOC_ETR_CTL_TRACECAPTEN_SHIFT 0 +#define PSOC_ETR_CTL_TRACECAPTEN_MASK 0x1 + +/* PSOC_ETR_RWD */ +#define PSOC_ETR_RWD_RWD_SHIFT 0 +#define PSOC_ETR_RWD_RWD_MASK 0xFFFFFFFF + +/* PSOC_ETR_MODE */ +#define PSOC_ETR_MODE_MODE_SHIFT 0 +#define PSOC_ETR_MODE_MODE_MASK 0x3 + +/* PSOC_ETR_LBUFLEVEL */ +#define PSOC_ETR_LBUFLEVEL_LBUFLEVEL_SHIFT 0 +#define PSOC_ETR_LBUFLEVEL_LBUFLEVEL_MASK 0x7FFFFFFF + +/* PSOC_ETR_CBUFLEVEL */ +#define PSOC_ETR_CBUFLEVEL_CBUFLEVEL_SHIFT 0 +#define PSOC_ETR_CBUFLEVEL_CBUFLEVEL_MASK 0x7FFFFFFF + +/* PSOC_ETR_BUFWM */ +#define PSOC_ETR_BUFWM_BUFWM_SHIFT 0 +#define PSOC_ETR_BUFWM_BUFWM_MASK 0x3FFFFFFF + +/* PSOC_ETR_RRPHI */ +#define PSOC_ETR_RRPHI_RRPHI_SHIFT 0 +#define PSOC_ETR_RRPHI_RRPHI_MASK 0xFF + +/* PSOC_ETR_RWPHI */ +#define PSOC_ETR_RWPHI_RWPHI_SHIFT 0 +#define PSOC_ETR_RWPHI_RWPHI_MASK 0xFF + +/* PSOC_ETR_AXICTL */ +#define PSOC_ETR_AXICTL_PROTCTRLBIT0_SHIFT 0 +#define PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK 0x1 +#define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT 1 +#define PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK 0x2 +#define PSOC_ETR_AXICTL_CACHECTRLBIT0_SHIFT 2 +#define PSOC_ETR_AXICTL_CACHECTRLBIT0_MASK 0x4 +#define PSOC_ETR_AXICTL_CACHECTRLBIT1_SHIFT 3 +#define PSOC_ETR_AXICTL_CACHECTRLBIT1_MASK 0x8 +#define PSOC_ETR_AXICTL_CACHECTRLBIT2_SHIFT 4 +#define PSOC_ETR_AXICTL_CACHECTRLBIT2_MASK 0x10 +#define PSOC_ETR_AXICTL_CACHECTRLBIT3_SHIFT 5 +#define PSOC_ETR_AXICTL_CACHECTRLBIT3_MASK 0x20 +#define PSOC_ETR_AXICTL_SCATTERGATHERMODE_SHIFT 7 +#define PSOC_ETR_AXICTL_SCATTERGATHERMODE_MASK 0x80 +#define PSOC_ETR_AXICTL_WRBURSTLEN_SHIFT 8 +#define PSOC_ETR_AXICTL_WRBURSTLEN_MASK 0xF00 + +/* PSOC_ETR_DBALO */ +#define PSOC_ETR_DBALO_BUFADDRLO_SHIFT 0 +#define PSOC_ETR_DBALO_BUFADDRLO_MASK 0xFFFFFFFF + +/* PSOC_ETR_DBAHI */ +#define PSOC_ETR_DBAHI_BUFADDRHI_SHIFT 0 +#define PSOC_ETR_DBAHI_BUFADDRHI_MASK 0xFF + +/* PSOC_ETR_FFSR */ +#define PSOC_ETR_FFSR_FLINPROG_SHIFT 0 +#define PSOC_ETR_FFSR_FLINPROG_MASK 0x1 +#define PSOC_ETR_FFSR_FTSTOPPED_SHIFT 1 +#define PSOC_ETR_FFSR_FTSTOPPED_MASK 0x2 + +/* PSOC_ETR_FFCR */ +#define PSOC_ETR_FFCR_ENFT_SHIFT 0 +#define PSOC_ETR_FFCR_ENFT_MASK 0x1 +#define PSOC_ETR_FFCR_ENTI_SHIFT 1 +#define PSOC_ETR_FFCR_ENTI_MASK 0x2 +#define PSOC_ETR_FFCR_FONFLIN_SHIFT 4 +#define PSOC_ETR_FFCR_FONFLIN_MASK 0x10 +#define PSOC_ETR_FFCR_FONTRIGEVT_SHIFT 5 +#define PSOC_ETR_FFCR_FONTRIGEVT_MASK 0x20 +#define PSOC_ETR_FFCR_FLUSHMAN_SHIFT 6 +#define PSOC_ETR_FFCR_FLUSHMAN_MASK 0x40 +#define PSOC_ETR_FFCR_TRIGONTRIGIN_SHIFT 8 +#define PSOC_ETR_FFCR_TRIGONTRIGIN_MASK 0x100 +#define PSOC_ETR_FFCR_TRIGONTRIGEVT_SHIFT 9 +#define PSOC_ETR_FFCR_TRIGONTRIGEVT_MASK 0x200 +#define PSOC_ETR_FFCR_TRIGONFL_SHIFT 10 +#define PSOC_ETR_FFCR_TRIGONFL_MASK 0x400 +#define PSOC_ETR_FFCR_STOPONFL_SHIFT 12 +#define PSOC_ETR_FFCR_STOPONFL_MASK 0x1000 +#define PSOC_ETR_FFCR_STOPONTRIGEVT_SHIFT 13 +#define PSOC_ETR_FFCR_STOPONTRIGEVT_MASK 0x2000 + +/* PSOC_ETR_PSCR */ +#define PSOC_ETR_PSCR_PSCOUNT_SHIFT 0 +#define PSOC_ETR_PSCR_PSCOUNT_MASK 0x1F + +/* PSOC_ETR_ITMISCOP0 */ +#define PSOC_ETR_ITMISCOP0_ACQCOMP_SHIFT 0 +#define PSOC_ETR_ITMISCOP0_ACQCOMP_MASK 0x1 +#define PSOC_ETR_ITMISCOP0_FULL_SHIFT 1 +#define PSOC_ETR_ITMISCOP0_FULL_MASK 0x2 + +/* PSOC_ETR_ITTRFLIN */ +#define PSOC_ETR_ITTRFLIN_TRIGIN_SHIFT 0 +#define PSOC_ETR_ITTRFLIN_TRIGIN_MASK 0x1 +#define PSOC_ETR_ITTRFLIN_FLUSHIN_SHIFT 1 +#define PSOC_ETR_ITTRFLIN_FLUSHIN_MASK 0x2 + +/* PSOC_ETR_ITATBDATA0 */ +#define PSOC_ETR_ITATBDATA0_ATDATASBIT0_SHIFT 0 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT0_MASK 0x1 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT7_SHIFT 1 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT7_MASK 0x2 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT15_SHIFT 2 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT15_MASK 0x4 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT23_SHIFT 3 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT23_MASK 0x8 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT31_SHIFT 4 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT31_MASK 0x10 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT39_SHIFT 5 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT39_MASK 0x20 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT47_SHIFT 6 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT47_MASK 0x40 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT55_SHIFT 7 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT55_MASK 0x80 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT63_SHIFT 8 +#define PSOC_ETR_ITATBDATA0_ATDATASBIT63_MASK 0x100 + +/* PSOC_ETR_ITATBCTR2 */ +#define PSOC_ETR_ITATBCTR2_ATREADYS_SHIFT 0 +#define PSOC_ETR_ITATBCTR2_ATREADYS_MASK 0x1 +#define PSOC_ETR_ITATBCTR2_AFVALIDS_SHIFT 1 +#define PSOC_ETR_ITATBCTR2_AFVALIDS_MASK 0x2 +#define PSOC_ETR_ITATBCTR2_SYNCREQS_SHIFT 2 +#define PSOC_ETR_ITATBCTR2_SYNCREQS_MASK 0x4 + +/* PSOC_ETR_ITATBCTR1 */ +#define PSOC_ETR_ITATBCTR1_ATIDS_SHIFT 0 +#define PSOC_ETR_ITATBCTR1_ATIDS_MASK 0x7F + +/* PSOC_ETR_ITATBCTR0 */ +#define PSOC_ETR_ITATBCTR0_ATVALIDS_SHIFT 0 +#define PSOC_ETR_ITATBCTR0_ATVALIDS_MASK 0x1 +#define PSOC_ETR_ITATBCTR0_AFREADYS_SHIFT 1 +#define PSOC_ETR_ITATBCTR0_AFREADYS_MASK 0x2 +#define PSOC_ETR_ITATBCTR0_ATBYTESS_SHIFT 8 +#define PSOC_ETR_ITATBCTR0_ATBYTESS_MASK 0x700 + +/* PSOC_ETR_ITCTRL */ +#define PSOC_ETR_ITCTRL_INTEGRATION_MODE_SHIFT 0 +#define PSOC_ETR_ITCTRL_INTEGRATION_MODE_MASK 0x1 + +/* PSOC_ETR_CLAIMSET */ +#define PSOC_ETR_CLAIMSET_CLAIMSET_SHIFT 0 +#define PSOC_ETR_CLAIMSET_CLAIMSET_MASK 0xF + +/* PSOC_ETR_CLAIMCLR */ +#define PSOC_ETR_CLAIMCLR_CLAIMCLR_SHIFT 0 +#define PSOC_ETR_CLAIMCLR_CLAIMCLR_MASK 0xF + +/* PSOC_ETR_LAR */ +#define PSOC_ETR_LAR_ACCESS_W_SHIFT 0 +#define PSOC_ETR_LAR_ACCESS_W_MASK 0xFFFFFFFF + +/* PSOC_ETR_LSR */ +#define PSOC_ETR_LSR_LOCKEXIST_SHIFT 0 +#define PSOC_ETR_LSR_LOCKEXIST_MASK 0x1 +#define PSOC_ETR_LSR_LOCKGRANT_SHIFT 1 +#define PSOC_ETR_LSR_LOCKGRANT_MASK 0x2 +#define PSOC_ETR_LSR_LOCKTYPE_SHIFT 2 +#define PSOC_ETR_LSR_LOCKTYPE_MASK 0x4 + +/* PSOC_ETR_AUTHSTATUS */ +#define PSOC_ETR_AUTHSTATUS_NSID_SHIFT 0 +#define PSOC_ETR_AUTHSTATUS_NSID_MASK 0x3 +#define PSOC_ETR_AUTHSTATUS_NSNID_SHIFT 2 +#define PSOC_ETR_AUTHSTATUS_NSNID_MASK 0xC +#define PSOC_ETR_AUTHSTATUS_SID_SHIFT 4 +#define PSOC_ETR_AUTHSTATUS_SID_MASK 0x30 +#define PSOC_ETR_AUTHSTATUS_SNID_SHIFT 6 +#define PSOC_ETR_AUTHSTATUS_SNID_MASK 0xC0 + +/* PSOC_ETR_DEVID */ +#define PSOC_ETR_DEVID_ATBINPORTCOUNT_SHIFT 0 +#define PSOC_ETR_DEVID_ATBINPORTCOUNT_MASK 0x1F +#define PSOC_ETR_DEVID_CLKSCHEME_SHIFT 5 +#define PSOC_ETR_DEVID_CLKSCHEME_MASK 0x20 +#define PSOC_ETR_DEVID_CONFIGTYPE_SHIFT 6 +#define PSOC_ETR_DEVID_CONFIGTYPE_MASK 0xC0 +#define PSOC_ETR_DEVID_MEMWIDTH_SHIFT 8 +#define PSOC_ETR_DEVID_MEMWIDTH_MASK 0x700 +#define PSOC_ETR_DEVID_WBUF_DEPTH_SHIFT 11 +#define PSOC_ETR_DEVID_WBUF_DEPTH_MASK 0x3800 + +/* PSOC_ETR_DEVTYPE */ +#define PSOC_ETR_DEVTYPE_MAJOR_TYPE_SHIFT 0 +#define PSOC_ETR_DEVTYPE_MAJOR_TYPE_MASK 0xF +#define PSOC_ETR_DEVTYPE_SUB_TYPE_SHIFT 4 +#define PSOC_ETR_DEVTYPE_SUB_TYPE_MASK 0xF0 + +/* PSOC_ETR_PERIPHID4 */ +#define PSOC_ETR_PERIPHID4_JEP106_CONT_SHIFT 0 +#define PSOC_ETR_PERIPHID4_JEP106_CONT_MASK 0xF +#define PSOC_ETR_PERIPHID4_FOURKB_COUNT_SHIFT 4 +#define PSOC_ETR_PERIPHID4_FOURKB_COUNT_MASK 0xF0 + +/* PSOC_ETR_PERIPHID5 */ +#define PSOC_ETR_PERIPHID5_PERIPHID5_SHIFT 0 +#define PSOC_ETR_PERIPHID5_PERIPHID5_MASK 0xFFFFFFFF + +/* PSOC_ETR_PERIPHID6 */ +#define PSOC_ETR_PERIPHID6_PERIPHID6_SHIFT 0 +#define PSOC_ETR_PERIPHID6_PERIPHID6_MASK 0xFFFFFFFF + +/* PSOC_ETR_PERIPHID7 */ +#define PSOC_ETR_PERIPHID7_PERIPHID7_SHIFT 0 +#define PSOC_ETR_PERIPHID7_PERIPHID7_MASK 0xFFFFFFFF + +/* PSOC_ETR_PERIPHID0 */ +#define PSOC_ETR_PERIPHID0_PART_NUMBER_BITS7TO0_SHIFT 0 +#define PSOC_ETR_PERIPHID0_PART_NUMBER_BITS7TO0_MASK 0xFF + +/* PSOC_ETR_PERIPHID1 */ +#define PSOC_ETR_PERIPHID1_PART_NUMBER_BITS11TO8_SHIFT 0 +#define PSOC_ETR_PERIPHID1_PART_NUMBER_BITS11TO8_MASK 0xF +#define PSOC_ETR_PERIPHID1_JEP106_BITS3TO0_SHIFT 4 +#define PSOC_ETR_PERIPHID1_JEP106_BITS3TO0_MASK 0xF0 + +/* PSOC_ETR_PERIPHID2 */ +#define PSOC_ETR_PERIPHID2_JEP106_BITS6TO4_SHIFT 0 +#define PSOC_ETR_PERIPHID2_JEP106_BITS6TO4_MASK 0x7 +#define PSOC_ETR_PERIPHID2_JEDEC_SHIFT 3 +#define PSOC_ETR_PERIPHID2_JEDEC_MASK 0x8 +#define PSOC_ETR_PERIPHID2_REVISION_SHIFT 4 +#define PSOC_ETR_PERIPHID2_REVISION_MASK 0xF0 + +/* PSOC_ETR_PERIPHID3 */ +#define PSOC_ETR_PERIPHID3_CUSTOMER_MODIFIED_SHIFT 0 +#define PSOC_ETR_PERIPHID3_CUSTOMER_MODIFIED_MASK 0xF +#define PSOC_ETR_PERIPHID3_REVAND_SHIFT 4 +#define PSOC_ETR_PERIPHID3_REVAND_MASK 0xF0 + +/* PSOC_ETR_COMPID0 */ +#define PSOC_ETR_COMPID0_PREAMBLE_SHIFT 0 +#define PSOC_ETR_COMPID0_PREAMBLE_MASK 0xFF + +/* PSOC_ETR_COMPID1 */ +#define PSOC_ETR_COMPID1_PREAMBLE_SHIFT 0 +#define PSOC_ETR_COMPID1_PREAMBLE_MASK 0xF +#define PSOC_ETR_COMPID1_F_CLASS_SHIFT 4 +#define PSOC_ETR_COMPID1_F_CLASS_MASK 0xF0 + +/* PSOC_ETR_COMPID2 */ +#define PSOC_ETR_COMPID2_PREAMBLE_SHIFT 0 +#define PSOC_ETR_COMPID2_PREAMBLE_MASK 0xFF + +/* PSOC_ETR_COMPID3 */ +#define PSOC_ETR_COMPID3_PREAMBLE_SHIFT 0 +#define PSOC_ETR_COMPID3_PREAMBLE_MASK 0xFF + +#endif /* ASIC_REG_PSOC_ETR_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_etr_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_etr_regs.h new file mode 100644 index 000000000000..980a3e0054c5 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_etr_regs.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_ETR_REGS_H_ +#define ASIC_REG_PSOC_ETR_REGS_H_ + +/* + ***************************************** + * PSOC_ETR + * (Prototype: ETR) + ***************************************** + */ + +#define mmPSOC_ETR_RSZ 0x6C44004 + +#define mmPSOC_ETR_STS 0x6C4400C + +#define mmPSOC_ETR_RRD 0x6C44010 + +#define mmPSOC_ETR_RRP 0x6C44014 + +#define mmPSOC_ETR_RWP 0x6C44018 + +#define mmPSOC_ETR_TRG 0x6C4401C + +#define mmPSOC_ETR_CTL 0x6C44020 + +#define mmPSOC_ETR_RWD 0x6C44024 + +#define mmPSOC_ETR_MODE 0x6C44028 + +#define mmPSOC_ETR_LBUFLEVEL 0x6C4402C + +#define mmPSOC_ETR_CBUFLEVEL 0x6C44030 + +#define mmPSOC_ETR_BUFWM 0x6C44034 + +#define mmPSOC_ETR_RRPHI 0x6C44038 + +#define mmPSOC_ETR_RWPHI 0x6C4403C + +#define mmPSOC_ETR_AXICTL 0x6C44110 + +#define mmPSOC_ETR_DBALO 0x6C44118 + +#define mmPSOC_ETR_DBAHI 0x6C4411C + +#define mmPSOC_ETR_FFSR 0x6C44300 + +#define mmPSOC_ETR_FFCR 0x6C44304 + +#define mmPSOC_ETR_PSCR 0x6C44308 + +#define mmPSOC_ETR_ITMISCOP0 0x6C44EE0 + +#define mmPSOC_ETR_ITTRFLIN 0x6C44EE8 + +#define mmPSOC_ETR_ITATBDATA0 0x6C44EEC + +#define mmPSOC_ETR_ITATBCTR2 0x6C44EF0 + +#define mmPSOC_ETR_ITATBCTR1 0x6C44EF4 + +#define mmPSOC_ETR_ITATBCTR0 0x6C44EF8 + +#define mmPSOC_ETR_ITCTRL 0x6C44F00 + +#define mmPSOC_ETR_CLAIMSET 0x6C44FA0 + +#define mmPSOC_ETR_CLAIMCLR 0x6C44FA4 + +#define mmPSOC_ETR_LAR 0x6C44FB0 + +#define mmPSOC_ETR_LSR 0x6C44FB4 + +#define mmPSOC_ETR_AUTHSTATUS 0x6C44FB8 + +#define mmPSOC_ETR_DEVID 0x6C44FC8 + +#define mmPSOC_ETR_DEVTYPE 0x6C44FCC + +#define mmPSOC_ETR_PERIPHID4 0x6C44FD0 + +#define mmPSOC_ETR_PERIPHID5 0x6C44FD4 + +#define mmPSOC_ETR_PERIPHID6 0x6C44FD8 + +#define mmPSOC_ETR_PERIPHID7 0x6C44FDC + +#define mmPSOC_ETR_PERIPHID0 0x6C44FE0 + +#define mmPSOC_ETR_PERIPHID1 0x6C44FE4 + +#define mmPSOC_ETR_PERIPHID2 0x6C44FE8 + +#define mmPSOC_ETR_PERIPHID3 0x6C44FEC + +#define mmPSOC_ETR_COMPID0 0x6C44FF0 + +#define mmPSOC_ETR_COMPID1 0x6C44FF4 + +#define mmPSOC_ETR_COMPID2 0x6C44FF8 + +#define mmPSOC_ETR_COMPID3 0x6C44FFC + +#endif /* ASIC_REG_PSOC_ETR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_masks.h new file mode 100644 index 000000000000..9be3d656da3a --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_masks.h @@ -0,0 +1,1406 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ +#define ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ + +/* + ***************************************** + * PSOC_GLOBAL_CONF + * (Prototype: GLOBAL_CONF) + ***************************************** + */ + +/* PSOC_GLOBAL_CONF_NON_RST_FLOPS */ +#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_PCI_FW_FSM */ +#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1 + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_MNL_RST_IND_SHIFT 4 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_MNL_RST_IND_MASK 0x10 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_WD_RST_IND_SHIFT 5 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_WD_RST_IND_MASK 0x20 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SW_RST_IND_SHIFT 6 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SW_RST_IND_MASK 0x40 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SOFT_RST_IND_SHIFT 7 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SOFT_RST_IND_MASK 0x80 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_PRST_RST_IND_SHIFT 8 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_PRST_RST_IND_MASK 0x100 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FLR_RST_IND_SHIFT 9 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FLR_RST_IND_MASK 0x200 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FW_RST_IND_SHIFT 10 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FW_RST_IND_MASK 0x400 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_ECC_DERR_RST_IND_SHIFT 11 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_ECC_DERR_RST_IND_MASK 0x800 + +/* PSOC_GLOBAL_CONF_BTM_FSM */ +#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK 0x1F + +/* PSOC_GLOBAL_CONF_BTL_ROM_DELAY */ +#define PSOC_GLOBAL_CONF_BTL_ROM_DELAY_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTL_ROM_DELAY_VAL_MASK 0xFFFF + +/* PSOC_GLOBAL_CONF_SW_BTM_FSM */ +#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK 0x1F + +/* PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM */ +#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_MASK 0x1F + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_QSPI_SPI */ +#define PSOC_GLOBAL_CONF_QSPI_SPI_SEL_SHIFT 0 +#define PSOC_GLOBAL_CONF_QSPI_SPI_SEL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_SPI_MEM_EN */ +#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SPI_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SPI_MASK 0x1 +#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_QSPI_SHIFT 1 +#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_QSPI_MASK 0x2 + +/* PSOC_GLOBAL_CONF_PRSTN */ +#define PSOC_GLOBAL_CONF_PRSTN_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PCIE_EN */ +#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR */ +#define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_SPI_IMG_STS */ +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SPI_PRI_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SPI_PRI_MASK 0x3 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SPI_SEC_SHIFT 2 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SPI_SEC_MASK 0xC +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_PRI_SHIFT 4 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_PRI_MASK 0x30 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SEC_SHIFT 6 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SEC_MASK 0xC0 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCIE_PRI_SHIFT 8 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCIE_PRI_MASK 0x300 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCIE_SEC_SHIFT 10 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCIE_SEC_MASK 0xC00 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_SPI_PRI_SHIFT 12 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_SPI_PRI_MASK 0x3000 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_PRSTN_PRI_SHIFT 14 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_PRSTN_PRI_MASK 0xC000 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_SPI_SEC_SHIFT 16 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_SPI_SEC_MASK 0x30000 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_PRSTN_SEC_SHIFT 18 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_PRSTN_SEC_MASK 0xC0000 + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_FSM */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_MASK 0x1 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_SHIFT 1 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_MASK 0x2 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_SHIFT 2 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_MASK 0x4 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_SHIFT 3 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_MASK 0x8 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_SHIFT 4 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_MASK 0x10 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_SHIFT 5 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_MASK 0x20 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_SHIFT 6 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_MASK 0x40 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_SHIFT 7 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_MASK 0x80 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_SHIFT 8 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_MASK 0x100 + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_MASK 0x1 + +/* PSOC_GLOBAL_CONF_QSPI_SPI_BOOTSEQ_RST */ +#define PSOC_GLOBAL_CONF_QSPI_SPI_BOOTSEQ_RST_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_QSPI_SPI_BOOTSEQ_RST_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PHY_STABLE */ +#define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_SHIFT 0 +#define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PRSTN_OVR */ +#define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_MASK 0x1 +#define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_SHIFT 4 +#define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_MASK 0x10 + +/* PSOC_GLOBAL_CONF_ETR_FLUSH */ +#define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_SHIFT 0 +#define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ANY_RST */ +#define PSOC_GLOBAL_CONF_ANY_RST_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_ANY_RST_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_COLD_RST_FLOPS */ +#define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_DIS_RAZWI_ERR */ +#define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PCIE_PHY_RST_N */ +#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_MASK 0x1 +#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_CLK_DIS_SHIFT 16 +#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_CLK_DIS_MASK 0x10000 + +/* PSOC_GLOBAL_CONF_RAZWI_INTERRUPT */ +#define PSOC_GLOBAL_CONF_RAZWI_INTERRUPT_INTR_SHIFT 0 +#define PSOC_GLOBAL_CONF_RAZWI_INTERRUPT_INTR_MASK 0x1 + +/* PSOC_GLOBAL_CONF_RAZWI_MASK_INFO */ +#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_MASK_SHIFT 0 +#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_MASK_MASK 0x1 +#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AR_SHIFT 1 +#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AR_MASK 0x2 +#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AW_SHIFT 2 +#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AW_MASK 0x4 +#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_L_SHIFT 4 +#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_L_MASK 0x3FF0 +#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_H_SHIFT 16 +#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_H_MASK 0xFFFF0000 + +/* PSOC_GLOBAL_CONF_BTL_PROT */ +#define PSOC_GLOBAL_CONF_BTL_PROT_AR_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTL_PROT_AR_MASK 0x7 +#define PSOC_GLOBAL_CONF_BTL_PROT_AW_SHIFT 4 +#define PSOC_GLOBAL_CONF_BTL_PROT_AW_MASK 0x70 + +/* PSOC_GLOBAL_CONF_BTL_ADDR_EXT */ +#define PSOC_GLOBAL_CONF_BTL_ADDR_EXT_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTL_ADDR_EXT_VAL_MASK 0xFFFFF + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_TO */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_MASK 0x1 + +/* PSOC_GLOBAL_CONF_RESET_DELAYS */ +#define PSOC_GLOBAL_CONF_RESET_DELAYS_PRE_RESET_SHIFT 0 +#define PSOC_GLOBAL_CONF_RESET_DELAYS_PRE_RESET_MASK 0xFFFF +#define PSOC_GLOBAL_CONF_RESET_DELAYS_GRAD_RESET_SHIFT 16 +#define PSOC_GLOBAL_CONF_RESET_DELAYS_GRAD_RESET_MASK 0xFFFF0000 + +/* PSOC_GLOBAL_CONF_SCRATCHPAD */ +#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_SHIFT 0 +#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SEMAPHORE */ +#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_SHIFT 0 +#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_CPU_BOOT_STATUS */ +#define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_SHIFT 0 +#define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU */ +#define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPL_SOURCE */ +#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_MASK 0x7 + +/* PSOC_GLOBAL_CONF_I2C_MSTR1_DBG */ +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_SHIFT 0 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_MASK 0x1 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_SHIFT 1 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_MASK 0x2 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_SHIFT 2 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_MASK 0x4 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_SHIFT 3 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_MASK 0x8 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_SHIFT 4 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_MASK 0x10 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_SHIFT 5 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_MASK 0x20 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_SHIFT 6 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_MASK 0x40 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_SHIFT 7 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_MASK 0x80 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_SHIFT 8 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_MASK 0x100 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_SHIFT 9 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_MASK 0x200 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_SHIFT 10 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_MASK 0x7C00 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_SHIFT 15 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_MASK 0x78000 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_SHIFT 19 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_MASK 0x80000 + +/* PSOC_GLOBAL_CONF_I2C_SLV */ +#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_SHIFT 0 +#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK */ +#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_INTR_SHIFT 0 +#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_INTR_MASK 0x1 + +/* PSOC_GLOBAL_CONF_TRACE_ADDR */ +#define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_SHIFT 0 +#define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK 0xFFFFFF + +/* PSOC_GLOBAL_CONF_SMB_ALERT_CTRL */ +#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_M0_ALERT_MASK_SHIFT 0 +#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_M0_ALERT_MASK_MASK 0xFF +#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_M1_ALERT_MASK_SHIFT 8 +#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_M1_ALERT_MASK_MASK 0xFF00 +#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_SLV_ALERT_MASK_SHIFT 16 +#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_SLV_ALERT_MASK_MASK 0xFF0000 + +/* PSOC_GLOBAL_CONF_SMB_ALERT_INTR_CAUSE */ +#define PSOC_GLOBAL_CONF_SMB_ALERT_INTR_CAUSE_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SMB_ALERT_INTR_CAUSE_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CLEAR */ +#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CLEAR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CLEAR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL */ +#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL_IND_MASK 0x1 +#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL_MASK_SHIFT 4 +#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL_MASK_MASK 0x10 + +/* PSOC_GLOBAL_CONF_TRACE_AXPROT */ +#define PSOC_GLOBAL_CONF_TRACE_AXPROT_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TRACE_AXPROT_VAL_MASK 0x7 + +/* PSOC_GLOBAL_CONF_TRACE_AWUSER */ +#define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_TRACE_ARUSER */ +#define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_BTL_STS */ +#define PSOC_GLOBAL_CONF_BTL_STS_DONE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTL_STS_DONE_MASK 0x1 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_SHIFT 4 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_MASK 0x10 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_SHIFT 8 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_MASK 0xF00 + +/* PSOC_GLOBAL_CONF_TIMEOUT_INTR */ +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_SHIFT 0 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_MASK 0x1 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_SHIFT 1 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_MASK 0x2 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_SHIFT 2 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_MASK 0x4 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_SHIFT 3 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_MASK 0x8 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_SHIFT 4 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_MASK 0x10 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_SHIFT 5 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_MASK 0x20 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_SHIFT 6 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_MASK 0x40 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_SHIFT 7 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_MASK 0x80 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_SHIFT 8 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_MASK 0x100 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_SHIFT 9 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_MASK 0x200 + +/* PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR */ +#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PERIPH_INTR */ +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_SHIFT 0 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_MASK 0x1 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_SHIFT 1 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_MASK 0x2 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_SHIFT 2 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_MASK 0x4 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_SHIFT 3 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_MASK 0x8 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_SHIFT 4 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_MASK 0x10 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_SHIFT 5 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_MASK 0x20 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_SHIFT 6 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_MASK 0x40 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_SHIFT 7 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_MASK 0x80 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_SHIFT 12 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_MASK 0x1000 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_SHIFT 13 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_MASK 0x2000 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_SHIFT 16 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_MASK 0x10000 + +/* PSOC_GLOBAL_CONF_COMB_PERIPH_INTR */ +#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_AXI_ERR_INTR */ +#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ARC_WD_INTR */ +#define PSOC_GLOBAL_CONF_ARC_WD_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_ARC_WD_INTR_IND_MASK 0x3 + +/* PSOC_GLOBAL_CONF_ARC_WD_INTR_MASK */ +#define PSOC_GLOBAL_CONF_ARC_WD_INTR_MASK_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ARC_WD_INTR_MASK_VAL_MASK 0x3 + +/* PSOC_GLOBAL_CONF_DBG_APB_CTRL */ +#define PSOC_GLOBAL_CONF_DBG_APB_CTRL_SEL_SHIFT 0 +#define PSOC_GLOBAL_CONF_DBG_APB_CTRL_SEL_MASK 0x1 +#define PSOC_GLOBAL_CONF_DBG_APB_CTRL_VAL_SHIFT 1 +#define PSOC_GLOBAL_CONF_DBG_APB_CTRL_VAL_MASK 0x2 + +/* PSOC_GLOBAL_CONF_SPI_DMA_BAUDR */ +#define PSOC_GLOBAL_CONF_SPI_DMA_BAUDR_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_DMA_BAUDR_VAL_MASK 0xFFFF + +/* PSOC_GLOBAL_CONF_SPI_DMA_AWPROT */ +#define PSOC_GLOBAL_CONF_SPI_DMA_AWPROT_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_DMA_AWPROT_VAL_MASK 0x7 + +/* PSOC_GLOBAL_CONF_SPI_DMA_AWUSER */ +#define PSOC_GLOBAL_CONF_SPI_DMA_AWUSER_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_DMA_AWUSER_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPI_DMA_CTRL */ +#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_EN_MASK 0x1 +#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_DST_SRAM_SHIFT 1 +#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_DST_SRAM_MASK 0x2 +#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_MEM_SIZE_SHIFT 4 +#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_MEM_SIZE_MASK 0x3FFF0 +#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_ADDR_SHIFT 18 +#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_ADDR_MASK 0xFFFC0000 + +/* PSOC_GLOBAL_CONF_SPI_DMA_STATUS */ +#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_DONE_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_DONE_MASK 0x1 +#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_ERROR_SHIFT 1 +#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_ERROR_MASK 0x2 +#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_COPIED_SHIFT 4 +#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_COPIED_MASK 0x3FFF0 + +/* PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_L */ +#define PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_H */ +#define PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL */ +#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WEN_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WEN_MASK 0x1 +#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_BYTE_SWAP_SHIFT 4 +#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_BYTE_SWAP_MASK 0x10 +#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WRITE_CMD_SHIFT 8 +#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WRITE_CMD_MASK 0xFF00 +#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WREN_CMD_SHIFT 16 +#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WREN_CMD_MASK 0xFF0000 +#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WRDI_CMD_SHIFT 24 +#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WRDI_CMD_MASK 0xFF000000 + +/* PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL */ +#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_EN_MASK 0x1 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_RESP_ERR_SHIFT 1 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_RESP_ERR_MASK 0x2 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_SE_RANGE_SEL_SHIFT 4 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_SE_RANGE_SEL_MASK 0xFF0 + +/* PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_L */ +#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_H */ +#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_H_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_L */ +#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_H */ +#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_H_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_L */ +#define PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_H */ +#define PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_H_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_SPI_WR_WO_SE_STATUS */ +#define PSOC_GLOBAL_CONF_SPI_WR_WO_SE_STATUS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_SE_STATUS_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_QSPI_WR_WO_SE_STATUS */ +#define PSOC_GLOBAL_CONF_QSPI_WR_WO_SE_STATUS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_QSPI_WR_WO_SE_STATUS_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPI_WR_WO_ERR_ADDR */ +#define PSOC_GLOBAL_CONF_SPI_WR_WO_ERR_ADDR_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_ERR_ADDR_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_QSPI_WR_WO_ERR_ADDR */ +#define PSOC_GLOBAL_CONF_QSPI_WR_WO_ERR_ADDR_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_QSPI_WR_WO_ERR_ADDR_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK */ +#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK_QSPI_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK_QSPI_MASK 0x1 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK_SPI_SHIFT 1 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK_SPI_MASK 0x2 + +/* PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE */ +#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE_QSPI_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE_QSPI_IND_MASK 0x1 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE_SPI_IND_SHIFT 1 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE_SPI_IND_MASK 0x2 + +/* PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR */ +#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR_QSPI_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR_QSPI_VAL_MASK 0x1 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR_SPI_VAL_SHIFT 1 +#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR_SPI_VAL_MASK 0x2 + +/* PSOC_GLOBAL_CONF_MSTR_IF */ +#define PSOC_GLOBAL_CONF_MSTR_IF_GRACEFULL_CLEAR_SHIFT 0 +#define PSOC_GLOBAL_CONF_MSTR_IF_GRACEFULL_CLEAR_MASK 0x1 +#define PSOC_GLOBAL_CONF_MSTR_IF_FORCE_BP_SHIFT 1 +#define PSOC_GLOBAL_CONF_MSTR_IF_FORCE_BP_MASK 0x2 + +/* PSOC_GLOBAL_CONF_TARGETID */ +#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_SHIFT 1 +#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_MASK 0xFFE +#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_SHIFT 16 +#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_MASK 0xFFF0000 +#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_SHIFT 28 +#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_MASK 0xF0000000 + +/* PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL */ +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_NUM_OS_RD_SHIFT 0 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_NUM_OS_RD_MASK 0xFF +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_NUM_OS_WR_SHIFT 8 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_NUM_OS_WR_MASK 0xFF00 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_FORCE_WR_BUF_SHIFT 16 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_FORCE_WR_BUF_MASK 0x10000 + +/* PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2 */ +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_AWCACHE_OVRD_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_AWCACHE_OVRD_EN_MASK 0x1 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_AWCACHE_OVRD_VAL_SHIFT 4 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_AWCACHE_OVRD_VAL_MASK 0xF0 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_ARCACHE_OVRD_EN_SHIFT 8 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_ARCACHE_OVRD_EN_MASK 0x100 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_ARCACHE_OVRD_VAL_SHIFT 12 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_ARCACHE_OVRD_VAL_MASK 0xF000 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_NO_WR_INFLIGHT_SHIFT 16 +#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_NO_WR_INFLIGHT_MASK 0x10000 + +/* PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE */ +#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L */ +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_RSVD_0_SHIFT 1 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_RSVD_0_MASK 0x2 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_MEM_REPAIR_CFG_SHIFT 2 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_MEM_REPAIR_CFG_MASK 0xC +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPOL_SHIFT 4 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPOL_MASK 0x10 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPHA_SHIFT 5 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPHA_MASK 0x20 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_BTL_EN_SHIFT 6 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_BTL_EN_MASK 0x40 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_BTL_ROM_EN_SHIFT 7 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_BTL_ROM_EN_MASK 0x80 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_DUMP_SEL_SHIFT 8 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_DUMP_SEL_MASK 0x3FFF00 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_RSVD_1_SHIFT 22 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_RSVD_1_MASK 0x400000 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_DUMP_DIS_SHIFT 23 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_DUMP_DIS_MASK 0x800000 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_I2C_SHIFT 24 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_I2C_MASK 0x1F000000 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_SPI_QSPI_SHIFT 29 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_SPI_QSPI_MASK 0x20000000 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPU_PLL_CFG_SHIFT 30 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPU_PLL_CFG_MASK 0xC0000000 + +/* PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H */ +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_SECURITY_BYPASS_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_SECURITY_BYPASS_MASK 0x1 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_SRIS_MODE_SHIFT 1 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_SRIS_MODE_MASK 0x2 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_I2C_SLV_ADDR_SHIFT 2 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_I2C_SLV_ADDR_MASK 0x7C +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_RERERVED_STRAP_SHIFT 7 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_RERERVED_STRAP_MASK 0x380 + +/* PSOC_GLOBAL_CONF_LEGACY_BOOT_STRAPS */ +#define PSOC_GLOBAL_CONF_LEGACY_BOOT_STRAPS_PCIE_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_LEGACY_BOOT_STRAPS_PCIE_EN_MASK 0x1 + +/* PSOC_GLOBAL_CONF_MEM_REPAIR_DIV */ +#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_MASK 0x1 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_SHIFT 8 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_MASK 0xFF00 + +/* PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL */ +#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_MASK 0x1 + +/* PSOC_GLOBAL_CONF_MEM_REPAIR_STS */ +#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_MASK 0x1 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_SHIFT 4 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_MASK 0x10 + +/* PSOC_GLOBAL_CONF_OUTSTANT_TRANS */ +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_SHIFT 0 +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_MASK 0x1 +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_SHIFT 1 +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_MASK 0x2 + +/* PSOC_GLOBAL_CONF_MASK_REQ */ +#define PSOC_GLOBAL_CONF_MASK_REQ_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_MASK_REQ_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_BSAC_CTRL */ +#define PSOC_GLOBAL_CONF_BSAC_CTRL_ENABLE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_ENABLE_MASK 0x1 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_HOLD_SHIFT 1 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_HOLD_MASK 0x2 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_DONE_SHIFT 4 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_DONE_MASK 0x10 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_STARTED_SHIFT 5 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_STARTED_MASK 0x20 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_APBERROR_SHIFT 6 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_APBERROR_MASK 0x40 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_FRF_SHIFT 8 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_FRF_MASK 0x300 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_TMOD_SHIFT 10 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_TMOD_MASK 0xC00 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_SPI_FRF_SHIFT 12 +#define PSOC_GLOBAL_CONF_BSAC_CTRL_SPI_FRF_MASK 0x3000 + +/* PSOC_GLOBAL_CONF_BSAC_ADDR */ +#define PSOC_GLOBAL_CONF_BSAC_ADDR_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BSAC_ADDR_VAL_MASK 0xFFFFFFF + +/* PSOC_GLOBAL_CONF_BSAC_DATA */ +#define PSOC_GLOBAL_CONF_BSAC_DATA_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BSAC_DATA_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL */ +#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_ADDR_SHIFT 0 +#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_ADDR_MASK 0xFFFFFFF +#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_ENABLE_SHIFT 28 +#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_ENABLE_MASK 0x10000000 +#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_DONE_SHIFT 29 +#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_DONE_MASK 0x20000000 + +/* PSOC_GLOBAL_CONF_BSAC_POLLING_DATA */ +#define PSOC_GLOBAL_CONF_BSAC_POLLING_DATA_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BSAC_POLLING_DATA_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_BSAC_POLLING_MASK */ +#define PSOC_GLOBAL_CONF_BSAC_POLLING_MASK_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BSAC_POLLING_MASK_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_BTL_IMG */ +#define PSOC_GLOBAL_CONF_BTL_IMG_SPI_IMAGE_FLIP_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTL_IMG_SPI_IMAGE_FLIP_MASK 0x1 +#define PSOC_GLOBAL_CONF_BTL_IMG_PRST_IMAGE_FLIP_SHIFT 1 +#define PSOC_GLOBAL_CONF_BTL_IMG_PRST_IMAGE_FLIP_MASK 0x2 +#define PSOC_GLOBAL_CONF_BTL_IMG_PCIE_IMAGE_FLIP_SHIFT 2 +#define PSOC_GLOBAL_CONF_BTL_IMG_PCIE_IMAGE_FLIP_MASK 0x4 +#define PSOC_GLOBAL_CONF_BTL_IMG_SW_RST_RUN_PCIE_IMAGE_SHIFT 4 +#define PSOC_GLOBAL_CONF_BTL_IMG_SW_RST_RUN_PCIE_IMAGE_MASK 0x10 +#define PSOC_GLOBAL_CONF_BTL_IMG_SOFT_RST_RUN_PCIE_IMAGE_SHIFT 5 +#define PSOC_GLOBAL_CONF_BTL_IMG_SOFT_RST_RUN_PCIE_IMAGE_MASK 0x20 +#define PSOC_GLOBAL_CONF_BTL_IMG_WD_RST_RUN_PCIE_IMAGE_SHIFT 6 +#define PSOC_GLOBAL_CONF_BTL_IMG_WD_RST_RUN_PCIE_IMAGE_MASK 0x40 +#define PSOC_GLOBAL_CONF_BTL_IMG_MNL_RST_RUN_PCIE_IMAGE_SHIFT 7 +#define PSOC_GLOBAL_CONF_BTL_IMG_MNL_RST_RUN_PCIE_IMAGE_MASK 0x80 +#define PSOC_GLOBAL_CONF_BTL_IMG_PRST_RUN_PCIE_IMAGE_SHIFT 8 +#define PSOC_GLOBAL_CONF_BTL_IMG_PRST_RUN_PCIE_IMAGE_MASK 0x100 +#define PSOC_GLOBAL_CONF_BTL_IMG_FLR_RST_RUN_PCIE_IMAGE_SHIFT 9 +#define PSOC_GLOBAL_CONF_BTL_IMG_FLR_RST_RUN_PCIE_IMAGE_MASK 0x200 +#define PSOC_GLOBAL_CONF_BTL_IMG_FW_RST_RUN_PCIE_IMAGE_SHIFT 10 +#define PSOC_GLOBAL_CONF_BTL_IMG_FW_RST_RUN_PCIE_IMAGE_MASK 0x400 + +/* PSOC_GLOBAL_CONF_PRSTN_MASK */ +#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_WD_MASK */ +#define PSOC_GLOBAL_CONF_WD_MASK_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_WD_MASK_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_RST_SRC */ +#define PSOC_GLOBAL_CONF_RST_SRC_COLD_RST_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_RST_SRC_COLD_RST_IND_MASK 0x1 +#define PSOC_GLOBAL_CONF_RST_SRC_MNL_RST_IND_SHIFT 1 +#define PSOC_GLOBAL_CONF_RST_SRC_MNL_RST_IND_MASK 0x2 +#define PSOC_GLOBAL_CONF_RST_SRC_PRSTN_RST_IND_SHIFT 2 +#define PSOC_GLOBAL_CONF_RST_SRC_PRSTN_RST_IND_MASK 0x4 +#define PSOC_GLOBAL_CONF_RST_SRC_SOFT_RST_IND_SHIFT 3 +#define PSOC_GLOBAL_CONF_RST_SRC_SOFT_RST_IND_MASK 0x8 +#define PSOC_GLOBAL_CONF_RST_SRC_WD_RST_IND_SHIFT 4 +#define PSOC_GLOBAL_CONF_RST_SRC_WD_RST_IND_MASK 0x10 +#define PSOC_GLOBAL_CONF_RST_SRC_FW_RST_IND_SHIFT 5 +#define PSOC_GLOBAL_CONF_RST_SRC_FW_RST_IND_MASK 0x20 +#define PSOC_GLOBAL_CONF_RST_SRC_SW_RST_IND_SHIFT 6 +#define PSOC_GLOBAL_CONF_RST_SRC_SW_RST_IND_MASK 0x40 +#define PSOC_GLOBAL_CONF_RST_SRC_FLR_RST_IND_SHIFT 7 +#define PSOC_GLOBAL_CONF_RST_SRC_FLR_RST_IND_MASK 0x80 +#define PSOC_GLOBAL_CONF_RST_SRC_ECC_DERR_RST_IND_SHIFT 8 +#define PSOC_GLOBAL_CONF_RST_SRC_ECC_DERR_RST_IND_MASK 0x100 + +/* PSOC_GLOBAL_CONF_BOOT_STATE */ +#define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL */ +#define PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL_SOFT_RST_MASK_SHIFT 0 +#define PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL_SOFT_RST_MASK_MASK 0x1 +#define PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL_SW_RST_MASK_SHIFT 4 +#define PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL_SW_RST_MASK_MASK 0x10 + +/* PSOC_GLOBAL_CONF_PAD_1V8_CFG */ +#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_MASK 0x7F + +/* PSOC_GLOBAL_CONF_PAD_3V3_CFG */ +#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_MASK 0x7F + +/* PSOC_GLOBAL_CONF_BNK3V3_MS */ +#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_MASK 0x3 + +/* PSOC_GLOBAL_CONF_TPC_ISO */ +#define PSOC_GLOBAL_CONF_TPC_ISO_ISO_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_TPC_ISO_ISO_EN_MASK 0x1FFFFFF + +/* PSOC_GLOBAL_CONF_VDEC_ISO */ +#define PSOC_GLOBAL_CONF_VDEC_ISO_ISO_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_VDEC_ISO_ISO_EN_MASK 0x3FF + +/* PSOC_GLOBAL_CONF_NIC_ISO */ +#define PSOC_GLOBAL_CONF_NIC_ISO_ISO_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_NIC_ISO_ISO_EN_MASK 0xFFF + +/* PSOC_GLOBAL_CONF_MME_ISO */ +#define PSOC_GLOBAL_CONF_MME_ISO_MME0_EU_RO_ISO_SHIFT 0 +#define PSOC_GLOBAL_CONF_MME_ISO_MME0_EU_RO_ISO_MASK 0x3F +#define PSOC_GLOBAL_CONF_MME_ISO_MME1_EU_RO_ISO_SHIFT 6 +#define PSOC_GLOBAL_CONF_MME_ISO_MME1_EU_RO_ISO_MASK 0xFC0 +#define PSOC_GLOBAL_CONF_MME_ISO_MME2_EU_RO_ISO_SHIFT 12 +#define PSOC_GLOBAL_CONF_MME_ISO_MME2_EU_RO_ISO_MASK 0x3F000 +#define PSOC_GLOBAL_CONF_MME_ISO_MME3_EU_RO_ISO_SHIFT 18 +#define PSOC_GLOBAL_CONF_MME_ISO_MME3_EU_RO_ISO_MASK 0xFC0000 + +/* PSOC_GLOBAL_CONF_EDMA_ISO */ +#define PSOC_GLOBAL_CONF_EDMA_ISO_ISO_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_EDMA_ISO_ISO_EN_MASK 0xFF + +/* PSOC_GLOBAL_CONF_HBM_ISO */ +#define PSOC_GLOBAL_CONF_HBM_ISO_HBM_TO_XBAR_SHIFT 0 +#define PSOC_GLOBAL_CONF_HBM_ISO_HBM_TO_XBAR_MASK 0xFFF +#define PSOC_GLOBAL_CONF_HBM_ISO_HBM_TO_HCH_SHIFT 16 +#define PSOC_GLOBAL_CONF_HBM_ISO_HBM_TO_HCH_MASK 0x3F0000 + +/* PSOC_GLOBAL_CONF_XBAR_EDGE_ISO */ +#define PSOC_GLOBAL_CONF_XBAR_EDGE_ISO_ISO_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_XBAR_EDGE_ISO_ISO_EN_MASK 0xF + +/* PSOC_GLOBAL_CONF_HIF_HMMU_ISO */ +#define PSOC_GLOBAL_CONF_HIF_HMMU_ISO_ISO_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_HIF_HMMU_ISO_ISO_EN_MASK 0xFFFF + +/* PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS */ +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS_FAILED_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS_FAILED_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH */ +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_LSB_ADDR_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_LSB_ADDR_MASK 0xFFF +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_PPROT_SHIFT 12 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_PPROT_MASK 0x7000 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_PWRITE_SHIFT 16 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_PWRITE_MASK 0x10000 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_FENCE_SHIFT 17 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_FENCE_MASK 0x20000 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_DROP_SHIFT 18 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_DROP_MASK 0x40000 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_DST_ID_SHIFT 20 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_DST_ID_MASK 0x3F00000 + +/* PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR */ +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR_PWDATA_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR_PWDATA_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS */ +#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_RES_READY_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_RES_READY_MASK 0x1 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_PSLVERR_SHIFT 4 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_PSLVERR_MASK 0x10 + +/* PSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP */ +#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP_PRDATA_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP_PRDATA_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR */ +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_REQ_BUFF_FULL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_REQ_BUFF_FULL_MASK 0x1 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_BUFF_FULL_SHIFT 1 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_BUFF_FULL_MASK 0x2 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_REQ_ILLEGAL_SHIFT 2 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_REQ_ILLEGAL_MASK 0x4 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_DATA_OVRN_SHIFT 3 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_DATA_OVRN_MASK 0x8 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_SHIFT 4 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_MASK 0x10 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_QUAL_OVRN_SHIFT 5 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_QUAL_OVRN_MASK 0x20 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_POP_RES_WHILE_EMPTY_SHIFT 6 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_POP_RES_WHILE_EMPTY_MASK 0x40 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PUSH_REQ_WHILE_FULL_SHIFT 7 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PUSH_REQ_WHILE_FULL_MASK 0x80 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RX_TIMEOUT_SHIFT 8 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RX_TIMEOUT_MASK 0x100 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_TX_TIMEOUT_SHIFT 9 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_TX_TIMEOUT_MASK 0x200 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_ADDR_SHIFT 12 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_ADDR_MASK 0xFFF000 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_DST_ID_SHIFT 24 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_DST_ID_MASK 0x3F000000 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_DROP_SHIFT 31 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_DROP_MASK 0x80000000 + +/* PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK */ +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_REQ_BUFF_FULL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_REQ_BUFF_FULL_MASK 0x1 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_BUFF_FULL_SHIFT 1 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_BUFF_FULL_MASK 0x2 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_REQ_ILLEGAL_SHIFT 2 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_REQ_ILLEGAL_MASK 0x4 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_DATA_OVRN_SHIFT 3 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_DATA_OVRN_MASK 0x8 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_PSLVERR_SHIFT 4 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_PSLVERR_MASK 0x10 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_QUAL_OVRN_SHIFT 5 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_QUAL_OVRN_MASK 0x20 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_POP_RES_WHILE_EMPTY_SHIFT 6 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_POP_RES_WHILE_EMPTY_MASK 0x40 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_PUSH_REQ_WHILE_FULL_SHIFT 7 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_PUSH_REQ_WHILE_FULL_MASK 0x80 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RX_TIMEOUT_SHIFT 8 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RX_TIMEOUT_MASK 0x100 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_TX_TIMEOUT_SHIFT 9 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_TX_TIMEOUT_MASK 0x200 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_VALID_SHIFT 16 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_VALID_MASK 0x10000 + +/* PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS */ +#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_REQ_LL_USED_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_REQ_LL_USED_MASK 0x3F +#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_RES_LL_USED_SHIFT 8 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_RES_LL_USED_MASK 0x1F00 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_OTF_FIFO_USED_SHIFT 16 +#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_OTF_FIFO_USED_MASK 0x3F0000 + +/* PSOC_GLOBAL_CONF_ASIF_CORE_CFG */ +#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_RISE_DELAY_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_RISE_DELAY_MASK 0x1F +#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_FALL_DELAY_SHIFT 8 +#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_FALL_DELAY_MASK 0x1F00 +#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_DETECT_DELAY_SHIFT 16 +#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_DETECT_DELAY_MASK 0xF0000 +#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_FLUSH_DESIGN_SHIFT 31 +#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_FLUSH_DESIGN_MASK 0x80000000 + +/* PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT */ +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_DATA_OVRN_CNT_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_DATA_OVRN_CNT_MASK 0xF +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_QUAL_OVRN_CNT_SHIFT 4 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_QUAL_OVRN_CNT_MASK 0xF0 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_DETECT_CYCLES_CNT_SHIFT 8 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_DETECT_CYCLES_CNT_MASK 0xF00 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_CNT_SHIFT 12 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_CNT_MASK 0xF000 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_TX_CNT_SHIFT 16 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_TX_CNT_MASK 0xF0000 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_FSM_SHIFT 20 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_FSM_MASK 0xF00000 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_TX_FSM_SHIFT 24 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_TX_FSM_MASK 0xF000000 + +/* PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR */ +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_GLB_CLEAR_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_GLB_CLEAR_MASK 0x1 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_DATA_OVRN_CLR_SHIFT 1 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_DATA_OVRN_CLR_MASK 0x2 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_QUAL_OVRN_CLR_SHIFT 2 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_QUAL_OVRN_CLR_MASK 0x4 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_CLR_SHIFT 3 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_CLR_MASK 0x8 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_TX_CLR_SHIFT 4 +#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_TX_CLR_MASK 0x10 + +/* PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG */ +#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_EN_MASK 0x1 +#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_EN_SHIFT 1 +#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_EN_MASK 0x2 +#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_RES_SHIFT 2 +#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_RES_MASK 0x4 +#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_RES_SHIFT 3 +#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_RES_MASK 0x8 +#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_VALUE_SHIFT 8 +#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_VALUE_MASK 0x3FF00 +#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_VALUE_SHIFT 20 +#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_VALUE_MASK 0x3FF00000 + +/* PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE */ +#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR */ +#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK */ +#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE */ +#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR */ +#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK */ +#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PAD_DEFAULT */ +#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_MASK 0xF + +/* PSOC_GLOBAL_CONF_PAD_SEL */ +#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_MASK 0x3 + +/* PSOC_GLOBAL_CONF_SMI_ACCESS_EN */ +#define PSOC_GLOBAL_CONF_SMI_ACCESS_EN_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SMI_ACCESS_EN_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_SCRAM_EXTMEM_EN */ +#define PSOC_GLOBAL_CONF_SCRAM_EXTMEM_EN_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SCRAM_EXTMEM_EN_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_SCRAM_PERM_SEL */ +#define PSOC_GLOBAL_CONF_SCRAM_PERM_SEL_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SCRAM_PERM_SEL_VAL_MASK 0xF + +/* PSOC_GLOBAL_CONF_SCRAM_POLY_H3 */ +#define PSOC_GLOBAL_CONF_SCRAM_POLY_H3_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SCRAM_POLY_H3_VAL_MASK 0x1FFFFFFF + +/* PSOC_GLOBAL_CONF_CORE_MODE */ +#define PSOC_GLOBAL_CONF_CORE_MODE_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_CORE_MODE_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_EXTMEM_ID_LOC */ +#define PSOC_GLOBAL_CONF_EXTMEM_ID_LOC_USER_SHRD_IND_LOC_SHIFT 24 +#define PSOC_GLOBAL_CONF_EXTMEM_ID_LOC_USER_SHRD_IND_LOC_MASK 0x3F000000 + +/* PSOC_GLOBAL_CONF_LBW_USER_CTRL */ +#define PSOC_GLOBAL_CONF_LBW_USER_CTRL_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_LBW_USER_CTRL_EN_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ADC_STM_ID */ +#define PSOC_GLOBAL_CONF_ADC_STM_ID_STM_MSTR_ID_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_STM_ID_STM_MSTR_ID_MASK 0x3F + +/* PSOC_GLOBAL_CONF_ADC */ +#define PSOC_GLOBAL_CONF_ADC_INTR_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_INTR_MASK 0xF + +/* PSOC_GLOBAL_CONF_ADC_INT_MASK */ +#define PSOC_GLOBAL_CONF_ADC_INT_MASK_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_INT_MASK_VAL_MASK 0xF + +/* PSOC_GLOBAL_CONF_ADC_CLK_FREQ */ +#define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START */ +#define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_ADC_SAMPLES */ +#define PSOC_GLOBAL_CONF_ADC_SAMPLES_DATA_SAMPLES_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_SAMPLES_DATA_SAMPLES_MASK 0x1F +#define PSOC_GLOBAL_CONF_ADC_SAMPLES_CLK_SAMPLES_SHIFT 8 +#define PSOC_GLOBAL_CONF_ADC_SAMPLES_CLK_SAMPLES_MASK 0x1F00 + +/* PSOC_GLOBAL_CONF_ADC_TPH_CS */ +#define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_ADC_LSB_NMSB */ +#define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES */ +#define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE */ +#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_MASK 0x1 +#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_CH_SEL_SHIFT 4 +#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_CH_SEL_MASK 0x30 + +/* PSOC_GLOBAL_CONF_ADC_TDV_CSDO */ +#define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_ADC_PID_SEL */ +#define PSOC_GLOBAL_CONF_ADC_PID_SEL_ADC_SEL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_PID_SEL_ADC_SEL_MASK 0x3 +#define PSOC_GLOBAL_CONF_ADC_PID_SEL_CHANNEL_SEL_SHIFT 4 +#define PSOC_GLOBAL_CONF_ADC_PID_SEL_CHANNEL_SEL_MASK 0x30 + +/* PSOC_GLOBAL_CONF_ADC_TSU_CSCK */ +#define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_ADC_CH_SEL */ +#define PSOC_GLOBAL_CONF_ADC_CH_SEL_SEL_DELAY_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_CH_SEL_SEL_DELAY_MASK 0xFF +#define PSOC_GLOBAL_CONF_ADC_CH_SEL_SEL_MAX_SHIFT 8 +#define PSOC_GLOBAL_CONF_ADC_CH_SEL_SEL_MAX_MASK 0x300 + +/* PSOC_GLOBAL_CONF_ADC_WRITE_ADDR */ +#define PSOC_GLOBAL_CONF_ADC_WRITE_ADDR_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_WRITE_ADDR_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_ADC_CFG_DATA */ +#define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL */ +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_AUX_WR_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_AUX_WR_EN_MASK 0x1 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_WR_EN_SHIFT 1 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_WR_EN_MASK 0x2 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_GRNT_SHIFT 12 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_GRNT_MASK 0x1000 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_DATA_SHIFT 13 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_DATA_MASK 0x2000 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_TS_SHIFT 14 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_TS_MASK 0x4000 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_MARKED_SHIFT 15 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_MARKED_MASK 0x8000 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_CAUSE_TRIG_SHIFT 16 +#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_CAUSE_TRIG_MASK 0x10000 + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL_RRESP_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL_RRESP_VAL_MASK 0x3 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL_WIN_EN_SHIFT 4 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL_WIN_EN_MASK 0xF0 + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_L */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_L_VAL_SHIFT 12 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_L_VAL_MASK 0xFFFFF000 + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_H */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_L */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_L_VAL_SHIFT 12 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_L_VAL_MASK 0xFFFFF000 + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_H */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_L */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_L_VAL_SHIFT 12 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_L_VAL_MASK 0xFFFFF000 + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_H */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_L */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_L_VAL_SHIFT 12 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_L_VAL_MASK 0xFFFFF000 + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_H */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_L */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_L_VAL_SHIFT 12 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_L_VAL_MASK 0xFFFFF000 + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_H */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_L */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_L_VAL_SHIFT 12 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_L_VAL_MASK 0xFFFFF000 + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_H */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_L */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_L_VAL_SHIFT 12 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_L_VAL_MASK 0xFFFFF000 + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_H */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_L */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_L_VAL_SHIFT 12 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_L_VAL_MASK 0xFFFFF000 + +/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_H */ +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL */ +#define PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL_START_SHIFT 0 +#define PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL_START_MASK 0x1 +#define PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL_DONE_SHIFT 4 +#define PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL_DONE_MASK 0x10 + +/* PSOC_GLOBAL_CONF_RST_OUT_CTRL */ +#define PSOC_GLOBAL_CONF_RST_OUT_CTRL_CLR_SHIFT 0 +#define PSOC_GLOBAL_CONF_RST_OUT_CTRL_CLR_MASK 0x1 + +/* PSOC_GLOBAL_CONF_MEM_CPY_CTRL */ +#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL_EN_MASK 0x1 + +/* PSOC_GLOBAL_CONF_MEM_CPY_STATUS */ +#define PSOC_GLOBAL_CONF_MEM_CPY_STATUS_DONE_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_CPY_STATUS_DONE_MASK 0x1 + +/* PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_H */ +#define PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_L */ +#define PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_H */ +#define PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_L */ +#define PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_MEM_CPY_CTRL2 */ +#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_MEM_SIZE_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_MEM_SIZE_MASK 0xFFFF +#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_WR_OS_SHIFT 16 +#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_WR_OS_MASK 0x3F0000 +#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_RD_OS_SHIFT 24 +#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_RD_OS_MASK 0x3F000000 +#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_USE_CONST_SHIFT 31 +#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_USE_CONST_MASK 0x80000000 + +/* PSOC_GLOBAL_CONF_MEM_CPY_CONST */ +#define PSOC_GLOBAL_CONF_MEM_CPY_CONST_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_CPY_CONST_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_H */ +#define PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_L */ +#define PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_AXI_SPLIT_CFG */ +#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_FORCE_RESP_OK_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_FORCE_RESP_OK_MASK 0x1 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_FORCE_WR_BUF_SHIFT 1 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_FORCE_WR_BUF_MASK 0x2 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_NUM_RD_OS_SHIFT 8 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_NUM_RD_OS_MASK 0xFF00 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_NUM_WR_OS_SHIFT 16 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_NUM_WR_OS_MASK 0xFF0000 + +/* PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1 */ +#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_RD_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_RD_EN_MASK 0x7 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_RD_VAL_SHIFT 8 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_RD_VAL_MASK 0x700 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_WR_EN_SHIFT 16 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_WR_EN_MASK 0x70000 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_WR_VAL_SHIFT 24 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_WR_VAL_MASK 0x7000000 + +/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG0 */ +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG0_OVRD_RD_EN_31_0_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG0_OVRD_RD_EN_31_0_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG1 */ +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG1_OVRD_RD_31_0_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG1_OVRD_RD_31_0_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG2 */ +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG2_OVRD_WR_EN_31_0_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG2_OVRD_WR_EN_31_0_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG3 */ +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG3_OVRD_WR_31_0_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG3_OVRD_WR_31_0_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4 */ +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_RD_EN_39_32_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_RD_EN_39_32_MASK 0xFF +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_RD_39_32_SHIFT 8 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_RD_39_32_MASK 0xFF00 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_WR_EN_39_32_SHIFT 16 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_WR_EN_39_32_MASK 0xFF0000 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_WR_39_32_SHIFT 24 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_WR_39_32_MASK 0xFF000000 + +/* PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD */ +#define PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_EN */ +#define PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_EN_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_EN_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD */ +#define PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_EN */ +#define PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_EN_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_EN_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2 */ +#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_INTR_CAUSE_SHIFT 0 +#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_INTR_CAUSE_MASK 0x1 +#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_INTR_MASK_SHIFT 4 +#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_INTR_MASK_MASK 0x10 +#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_NO_WR_INFLIGHT_SHIFT 5 +#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_NO_WR_INFLIGHT_MASK 0x20 +#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_SEI_INTR_ID_SHIFT 8 +#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_SEI_INTR_ID_MASK 0x7FFFFF00 + +/* PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2 */ +#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_INTR_CAUSE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_INTR_CAUSE_MASK 0x1 +#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_INTR_MASK_SHIFT 4 +#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_INTR_MASK_MASK 0x10 +#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_NO_WR_INFLIGHT_SHIFT 5 +#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_NO_WR_INFLIGHT_MASK 0x20 +#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_SEI_INTR_ID_SHIFT 8 +#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_SEI_INTR_ID_MASK 0xFFFFF00 + +/* PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR */ +#define PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR_MAIN_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR_MAIN_IND_MASK 0x1 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR_BOOTROM_IND_SHIFT 1 +#define PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR_BOOTROM_IND_MASK 0x2 + +/* PSOC_GLOBAL_CONF_MEM_CPY_PROT */ +#define PSOC_GLOBAL_CONF_MEM_CPY_PROT_AR_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_CPY_PROT_AR_MASK 0x7 +#define PSOC_GLOBAL_CONF_MEM_CPY_PROT_AW_SHIFT 4 +#define PSOC_GLOBAL_CONF_MEM_CPY_PROT_AW_MASK 0x70 + +/* PSOC_GLOBAL_CONF_ISOLATE_INPUTS */ +#define PSOC_GLOBAL_CONF_ISOLATE_INPUTS_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_ISOLATE_INPUTS_EN_MASK 0x1 + +/* PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL */ +#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_EN_MASK 0x1 +#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_BRESP_SHIFT 1 +#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_BRESP_MASK 0x6 +#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_RRESP_SHIFT 5 +#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_RRESP_MASK 0x60 + +/* PSOC_GLOBAL_CONF_ARC_JT_SEL */ +#define PSOC_GLOBAL_CONF_ARC_JT_SEL_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ARC_JT_SEL_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PLL_DUMP_CRTL */ +#define PSOC_GLOBAL_CONF_PLL_DUMP_CRTL_PLL_SEL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PLL_DUMP_CRTL_PLL_SEL_MASK 0x3F +#define PSOC_GLOBAL_CONF_PLL_DUMP_CRTL_BIT_SEL_SHIFT 8 +#define PSOC_GLOBAL_CONF_PLL_DUMP_CRTL_BIT_SEL_MASK 0xF00 + +/* PSOC_GLOBAL_CONF_MEM_CPY_AXUSER */ +#define PSOC_GLOBAL_CONF_MEM_CPY_AXUSER_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_CPY_AXUSER_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_BTL_AXUSER */ +#define PSOC_GLOBAL_CONF_BTL_AXUSER_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTL_AXUSER_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0 */ +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC0_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC0_MASK 0x3F +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC1_SHIFT 6 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC1_MASK 0xFC0 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC2_SHIFT 12 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC2_MASK 0x3F000 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC3_SHIFT 18 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC3_MASK \ +0xFC0000 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_HBM_LOC0_SHIFT 24 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_HBM_LOC0_MASK \ +0x3F000000 + +/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1 */ +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_ADDR_EXTMEM_HBM_LOC1_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_ADDR_EXTMEM_HBM_LOC1_MASK 0x3F +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_ADDR_EXTMEM_HBM_LOC2_SHIFT 6 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_ADDR_EXTMEM_HBM_LOC2_MASK 0xFC0 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_PC_EN_SHIFT 12 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_PC_EN_MASK 0x1000 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_CNT_EN_SHIFT 13 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_CNT_EN_MASK 0x2000 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_EN_SHIFT 14 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_EN_MASK \ +0x4000 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_MASK_SHIFT \ +16 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_MASK_MASK \ +0xFF0000 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_HBM_NUM_SHIFT 24 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_HBM_NUM_MASK 0x7000000 + +/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2 */ +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_HBM_CNT_MASK_SHIFT \ +0 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_HBM_CNT_MASK_MASK \ +0xFFFF +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_EXTM_PC_MASK_SHIFT \ +16 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_EXTM_PC_MASK_MASK \ +0xFFFF0000 + +/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3 */ +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP0_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP0_MASK 0x7 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP1_SHIFT 3 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP1_MASK 0x38 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP2_SHIFT 6 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP2_MASK 0x1C0 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP3_SHIFT 9 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP3_MASK 0xE00 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP4_SHIFT 12 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP4_MASK 0x7000 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP5_SHIFT 15 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP5_MASK 0x38000 + +/* PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL */ +#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_EN_MASK 0x1 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_AXI_RESP_SHIFT 4 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_AXI_RESP_MASK 0x30 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_DRAIN_HBW_SHIFT 8 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_DRAIN_HBW_MASK 0x100 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_DRAIN_LBW_SHIFT 9 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_DRAIN_LBW_MASK 0x200 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_INTR_MASK_HBW_SHIFT 12 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_INTR_MASK_HBW_MASK 0x1000 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_INTR_MASK_LBW_SHIFT 13 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_INTR_MASK_LBW_MASK 0x2000 + +/* PSOC_GLOBAL_CONF_AXI_DRAIN_TIMEOUT */ +#define PSOC_GLOBAL_CONF_AXI_DRAIN_TIMEOUT_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_AXI_DRAIN_INTR */ +#define PSOC_GLOBAL_CONF_AXI_DRAIN_INTR_HBW_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_INTR_HBW_IND_MASK 0x1 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_INTR_LBW_IND_SHIFT 1 +#define PSOC_GLOBAL_CONF_AXI_DRAIN_INTR_LBW_IND_MASK 0x2 + +/* PSOC_GLOBAL_CONF_BTL_STOP_SPI_CLK */ +#define PSOC_GLOBAL_CONF_BTL_STOP_SPI_CLK_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTL_STOP_SPI_CLK_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ECO_INTR_CAUSE */ +#define PSOC_GLOBAL_CONF_ECO_INTR_CAUSE_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_ECO_INTR_CAUSE_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ECO_INTR_CLEAR */ +#define PSOC_GLOBAL_CONF_ECO_INTR_CLEAR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_ECO_INTR_CLEAR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ECO_INTR_MASK */ +#define PSOC_GLOBAL_CONF_ECO_INTR_MASK_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ECO_INTR_MASK_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_DFT_APB_CONTROL */ +#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_SPIF_MODE_SHIFT 0 +#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_SPIF_MODE_MASK 0x1 +#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_RESERVED_OUT_SHIFT 1 +#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_RESERVED_OUT_MASK 0xFFFE +#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_RESERVED_IN_SHIFT 16 +#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_RESERVED_IN_MASK 0xFFFF0000 + +#endif /* ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_regs.h new file mode 100644 index 000000000000..48980fa8e37b --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_regs.h @@ -0,0 +1,1337 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ +#define ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ + +/* + ***************************************** + * PSOC_GLOBAL_CONF + * (Prototype: GLOBAL_CONF) + ***************************************** + */ + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_0 0x4C4B000 + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_1 0x4C4B004 + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_2 0x4C4B008 + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_3 0x4C4B00C + +#define mmPSOC_GLOBAL_CONF_PCI_FW_FSM 0x4C4B020 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START 0x4C4B024 + +#define mmPSOC_GLOBAL_CONF_BTM_FSM 0x4C4B028 + +#define mmPSOC_GLOBAL_CONF_BTL_ROM_DELAY 0x4C4B02C + +#define mmPSOC_GLOBAL_CONF_SW_BTM_FSM 0x4C4B030 + +#define mmPSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM 0x4C4B034 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT 0x4C4B038 + +#define mmPSOC_GLOBAL_CONF_QSPI_SPI 0x4C4B03C + +#define mmPSOC_GLOBAL_CONF_SPI_MEM_EN 0x4C4B040 + +#define mmPSOC_GLOBAL_CONF_PRSTN 0x4C4B044 + +#define mmPSOC_GLOBAL_CONF_PCIE_EN 0x4C4B048 + +#define mmPSOC_GLOBAL_CONF_PCIE_PRSTN_INTR 0x4C4B04C + +#define mmPSOC_GLOBAL_CONF_SPI_IMG_STS 0x4C4B050 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_FSM 0x4C4B054 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD 0x4C4B058 + +#define mmPSOC_GLOBAL_CONF_QSPI_SPI_BOOTSEQ_RST 0x4C4B05C + +#define mmPSOC_GLOBAL_CONF_PHY_STABLE 0x4C4B060 + +#define mmPSOC_GLOBAL_CONF_PRSTN_OVR 0x4C4B064 + +#define mmPSOC_GLOBAL_CONF_ETR_FLUSH 0x4C4B068 + +#define mmPSOC_GLOBAL_CONF_ANY_RST 0x4C4B06C + +#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_0 0x4C4B070 + +#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1 0x4C4B074 + +#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2 0x4C4B078 + +#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3 0x4C4B07C + +#define mmPSOC_GLOBAL_CONF_DIS_RAZWI_ERR 0x4C4B080 + +#define mmPSOC_GLOBAL_CONF_PCIE_PHY_RST_N 0x4C4B084 + +#define mmPSOC_GLOBAL_CONF_RAZWI_INTERRUPT 0x4C4B088 + +#define mmPSOC_GLOBAL_CONF_RAZWI_MASK_INFO 0x4C4B08C + +#define mmPSOC_GLOBAL_CONF_BTL_PROT 0x4C4B090 + +#define mmPSOC_GLOBAL_CONF_BTL_ADDR_EXT 0x4C4B094 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TO 0x4C4B098 + +#define mmPSOC_GLOBAL_CONF_RESET_DELAYS 0x4C4B09C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 0x4C4B100 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_1 0x4C4B104 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_2 0x4C4B108 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_3 0x4C4B10C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_4 0x4C4B110 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_5 0x4C4B114 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_6 0x4C4B118 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_7 0x4C4B11C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 0x4C4B120 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_9 0x4C4B124 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_10 0x4C4B128 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_11 0x4C4B12C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_12 0x4C4B130 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_13 0x4C4B134 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_14 0x4C4B138 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_15 0x4C4B13C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_16 0x4C4B140 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_17 0x4C4B144 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_18 0x4C4B148 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_19 0x4C4B14C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_20 0x4C4B150 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_21 0x4C4B154 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_22 0x4C4B158 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 0x4C4B15C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 0x4C4B160 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 0x4C4B164 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 0x4C4B168 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 0x4C4B16C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_28 0x4C4B170 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 0x4C4B174 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 0x4C4B178 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 0x4C4B17C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_0 0x4C4B200 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_1 0x4C4B204 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_2 0x4C4B208 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_3 0x4C4B20C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_4 0x4C4B210 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_5 0x4C4B214 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_6 0x4C4B218 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_7 0x4C4B21C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_8 0x4C4B220 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_9 0x4C4B224 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_10 0x4C4B228 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_11 0x4C4B22C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_12 0x4C4B230 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_13 0x4C4B234 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_14 0x4C4B238 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_15 0x4C4B23C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_16 0x4C4B240 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_17 0x4C4B244 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_18 0x4C4B248 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_19 0x4C4B24C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_20 0x4C4B250 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_21 0x4C4B254 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_22 0x4C4B258 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_23 0x4C4B25C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_24 0x4C4B260 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_25 0x4C4B264 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_26 0x4C4B268 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_27 0x4C4B26C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_28 0x4C4B270 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_29 0x4C4B274 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_30 0x4C4B278 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_31 0x4C4B27C + +#define mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS 0x4C4B300 + +#define mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU 0x4C4B304 + +#define mmPSOC_GLOBAL_CONF_SPL_SOURCE 0x4C4B308 + +#define mmPSOC_GLOBAL_CONF_I2C_MSTR1_DBG 0x4C4B30C + +#define mmPSOC_GLOBAL_CONF_I2C_SLV 0x4C4B310 + +#define mmPSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK 0x4C4B314 + +#define mmPSOC_GLOBAL_CONF_TRACE_ADDR 0x4C4B320 + +#define mmPSOC_GLOBAL_CONF_SMB_ALERT_CTRL 0x4C4B324 + +#define mmPSOC_GLOBAL_CONF_SMB_ALERT_INTR_CAUSE 0x4C4B328 + +#define mmPSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CLEAR 0x4C4B32C + +#define mmPSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL 0x4C4B330 + +#define mmPSOC_GLOBAL_CONF_TRACE_AXPROT 0x4C4B334 + +#define mmPSOC_GLOBAL_CONF_TRACE_AWUSER 0x4C4B338 + +#define mmPSOC_GLOBAL_CONF_TRACE_ARUSER 0x4C4B33C + +#define mmPSOC_GLOBAL_CONF_BTL_STS 0x4C4B340 + +#define mmPSOC_GLOBAL_CONF_TIMEOUT_INTR 0x4C4B350 + +#define mmPSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR 0x4C4B354 + +#define mmPSOC_GLOBAL_CONF_PERIPH_INTR 0x4C4B358 + +#define mmPSOC_GLOBAL_CONF_COMB_PERIPH_INTR 0x4C4B35C + +#define mmPSOC_GLOBAL_CONF_AXI_ERR_INTR 0x4C4B360 + +#define mmPSOC_GLOBAL_CONF_ARC_WD_INTR 0x4C4B368 + +#define mmPSOC_GLOBAL_CONF_ARC_WD_INTR_MASK 0x4C4B36C + +#define mmPSOC_GLOBAL_CONF_DBG_APB_CTRL 0x4C4B370 + +#define mmPSOC_GLOBAL_CONF_SPI_DMA_BAUDR 0x4C4B374 + +#define mmPSOC_GLOBAL_CONF_SPI_DMA_AWPROT 0x4C4B378 + +#define mmPSOC_GLOBAL_CONF_SPI_DMA_AWUSER 0x4C4B37C + +#define mmPSOC_GLOBAL_CONF_SPI_DMA_CTRL 0x4C4B380 + +#define mmPSOC_GLOBAL_CONF_SPI_DMA_STATUS 0x4C4B384 + +#define mmPSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_L 0x4C4B388 + +#define mmPSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_H 0x4C4B38C + +#define mmPSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL 0x4C4B3A0 + +#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_CTRL 0x4C4B3B0 + +#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_L 0x4C4B3B4 + +#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_H 0x4C4B3B8 + +#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_L 0x4C4B3BC + +#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_H 0x4C4B3C0 + +#define mmPSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_L 0x4C4B3C4 + +#define mmPSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_H 0x4C4B3CC + +#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_SE_STATUS 0x4C4B3D0 + +#define mmPSOC_GLOBAL_CONF_QSPI_WR_WO_SE_STATUS 0x4C4B3D4 + +#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_ERR_ADDR 0x4C4B3D8 + +#define mmPSOC_GLOBAL_CONF_QSPI_WR_WO_ERR_ADDR 0x4C4B3DC + +#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK 0x4C4B3E0 + +#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE 0x4C4B3E4 + +#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR 0x4C4B3E8 + +#define mmPSOC_GLOBAL_CONF_MSTR_IF 0x4C4B3F0 + +#define mmPSOC_GLOBAL_CONF_TARGETID 0x4C4B400 + +#define mmPSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_0 0x4C4B404 + +#define mmPSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_1 0x4C4B408 + +#define mmPSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_0 0x4C4B40C + +#define mmPSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_1 0x4C4B410 + +#define mmPSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE 0x4C4B420 + +#define mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L 0x4C4B430 + +#define mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H 0x4C4B434 + +#define mmPSOC_GLOBAL_CONF_LEGACY_BOOT_STRAPS 0x4C4B438 + +#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_DIV 0x4C4B44C + +#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_CTRL 0x4C4B450 + +#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_STS 0x4C4B454 + +#define mmPSOC_GLOBAL_CONF_OUTSTANT_TRANS 0x4C4B458 + +#define mmPSOC_GLOBAL_CONF_MASK_REQ 0x4C4B45C + +#define mmPSOC_GLOBAL_CONF_BSAC_CTRL 0x4C4B4C0 + +#define mmPSOC_GLOBAL_CONF_BSAC_ADDR 0x4C4B4C4 + +#define mmPSOC_GLOBAL_CONF_BSAC_DATA 0x4C4B4C8 + +#define mmPSOC_GLOBAL_CONF_BSAC_POLLING_CTRL 0x4C4B4CC + +#define mmPSOC_GLOBAL_CONF_BSAC_POLLING_DATA 0x4C4B4D0 + +#define mmPSOC_GLOBAL_CONF_BSAC_POLLING_MASK 0x4C4B4D4 + +#define mmPSOC_GLOBAL_CONF_BTL_IMG 0x4C4B4E0 + +#define mmPSOC_GLOBAL_CONF_PRSTN_MASK 0x4C4B4E4 + +#define mmPSOC_GLOBAL_CONF_WD_MASK 0x4C4B4E8 + +#define mmPSOC_GLOBAL_CONF_RST_SRC 0x4C4B4F0 + +#define mmPSOC_GLOBAL_CONF_BOOT_STATE 0x4C4B4F4 + +#define mmPSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL 0x4C4B4F8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_0 0x4C4B500 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_1 0x4C4B504 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_2 0x4C4B508 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_3 0x4C4B50C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_4 0x4C4B510 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_5 0x4C4B514 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_6 0x4C4B518 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_7 0x4C4B51C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_8 0x4C4B520 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_9 0x4C4B524 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_10 0x4C4B528 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_11 0x4C4B52C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_12 0x4C4B530 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_13 0x4C4B534 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_14 0x4C4B538 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_15 0x4C4B53C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_16 0x4C4B540 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_17 0x4C4B544 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_18 0x4C4B548 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_19 0x4C4B54C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_20 0x4C4B550 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_21 0x4C4B554 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_22 0x4C4B558 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_23 0x4C4B55C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_24 0x4C4B560 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_25 0x4C4B564 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_26 0x4C4B568 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_27 0x4C4B56C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_28 0x4C4B570 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_29 0x4C4B574 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_30 0x4C4B578 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_31 0x4C4B57C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_32 0x4C4B580 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_33 0x4C4B584 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_34 0x4C4B588 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_35 0x4C4B58C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_36 0x4C4B590 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_37 0x4C4B594 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_38 0x4C4B598 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_39 0x4C4B59C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_40 0x4C4B5A0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_41 0x4C4B5A4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_42 0x4C4B5A8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_43 0x4C4B5AC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_44 0x4C4B5B0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_45 0x4C4B5B4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_46 0x4C4B5B8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_47 0x4C4B5BC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_48 0x4C4B5C0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_49 0x4C4B5C4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_50 0x4C4B5C8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_51 0x4C4B5CC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_52 0x4C4B5D0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_53 0x4C4B5D4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_54 0x4C4B5D8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_55 0x4C4B5DC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_56 0x4C4B5E0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_57 0x4C4B5E4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_58 0x4C4B5E8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_59 0x4C4B5EC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_60 0x4C4B5F0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_61 0x4C4B5F4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_62 0x4C4B5F8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_63 0x4C4B5FC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_64 0x4C4B600 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_65 0x4C4B604 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_66 0x4C4B608 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_67 0x4C4B60C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_68 0x4C4B610 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_69 0x4C4B614 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_70 0x4C4B618 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_71 0x4C4B61C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_72 0x4C4B620 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_73 0x4C4B624 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_74 0x4C4B628 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_75 0x4C4B62C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_76 0x4C4B630 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_77 0x4C4B634 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_78 0x4C4B638 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_79 0x4C4B63C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_80 0x4C4B640 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_81 0x4C4B644 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_82 0x4C4B648 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_83 0x4C4B64C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_84 0x4C4B650 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_85 0x4C4B654 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_86 0x4C4B658 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_87 0x4C4B65C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_88 0x4C4B660 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_89 0x4C4B664 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_90 0x4C4B668 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_91 0x4C4B66C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_92 0x4C4B670 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_93 0x4C4B674 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_0 0x4C4B690 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_1 0x4C4B694 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_2 0x4C4B698 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_3 0x4C4B69C + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_4 0x4C4B6A0 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_5 0x4C4B6A4 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_6 0x4C4B6A8 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_7 0x4C4B6AC + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_8 0x4C4B6B0 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_9 0x4C4B6B4 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_10 0x4C4B6B8 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_11 0x4C4B6BC + +#define mmPSOC_GLOBAL_CONF_BNK3V3_MS 0x4C4B710 + +#define mmPSOC_GLOBAL_CONF_TPC_ISO 0x4C4B760 + +#define mmPSOC_GLOBAL_CONF_VDEC_ISO 0x4C4B764 + +#define mmPSOC_GLOBAL_CONF_NIC_ISO 0x4C4B768 + +#define mmPSOC_GLOBAL_CONF_MME_ISO 0x4C4B76C + +#define mmPSOC_GLOBAL_CONF_EDMA_ISO 0x4C4B770 + +#define mmPSOC_GLOBAL_CONF_HBM_ISO 0x4C4B774 + +#define mmPSOC_GLOBAL_CONF_XBAR_EDGE_ISO 0x4C4B778 + +#define mmPSOC_GLOBAL_CONF_HIF_HMMU_ISO 0x4C4B77C + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS_0 0x4C4B780 + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS_1 0x4C4B784 + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_0 0x4C4B788 + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_1 0x4C4B78C + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR_0 0x4C4B790 + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR_1 0x4C4B794 + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_0 0x4C4B798 + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_1 0x4C4B79C + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP_0 0x4C4B7A0 + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP_1 0x4C4B7A4 + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_0 0x4C4B7A8 + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_1 0x4C4B7AC + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_0 0x4C4B7B0 + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_1 0x4C4B7B4 + +#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_STATUS 0x4C4B7B8 + +#define mmPSOC_GLOBAL_CONF_ASIF_CORE_CFG 0x4C4B7C0 + +#define mmPSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT 0x4C4B7C4 + +#define mmPSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR 0x4C4B7C8 + +#define mmPSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG 0x4C4B7CC + +#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE_0 0x4C4B7D0 + +#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE_1 0x4C4B7D4 + +#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR_0 0x4C4B7D8 + +#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR_1 0x4C4B7DC + +#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK_0 0x4C4B7E0 + +#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK_1 0x4C4B7E4 + +#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE_0 0x4C4B7E8 + +#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE_1 0x4C4B7EC + +#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR_0 0x4C4B7F0 + +#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR_1 0x4C4B7F4 + +#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK_0 0x4C4B7F8 + +#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK_1 0x4C4B7FC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_0 0x4C4B800 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_1 0x4C4B804 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_2 0x4C4B808 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_3 0x4C4B80C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_4 0x4C4B810 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_5 0x4C4B814 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_6 0x4C4B818 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_7 0x4C4B81C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_8 0x4C4B820 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_9 0x4C4B824 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_10 0x4C4B828 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_11 0x4C4B82C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_12 0x4C4B830 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_13 0x4C4B834 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_14 0x4C4B838 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_15 0x4C4B83C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_16 0x4C4B840 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_17 0x4C4B844 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_18 0x4C4B848 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_19 0x4C4B84C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_20 0x4C4B850 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_21 0x4C4B854 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_22 0x4C4B858 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_23 0x4C4B85C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_24 0x4C4B860 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_25 0x4C4B864 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_26 0x4C4B868 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_27 0x4C4B86C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_28 0x4C4B870 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_29 0x4C4B874 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_30 0x4C4B878 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_31 0x4C4B87C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_32 0x4C4B880 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_33 0x4C4B884 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_34 0x4C4B888 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_35 0x4C4B88C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_36 0x4C4B890 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_37 0x4C4B894 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_38 0x4C4B898 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_39 0x4C4B89C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_40 0x4C4B8A0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_41 0x4C4B8A4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_42 0x4C4B8A8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_43 0x4C4B8AC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_44 0x4C4B8B0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_45 0x4C4B8B4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_46 0x4C4B8B8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_47 0x4C4B8BC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_48 0x4C4B8C0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_49 0x4C4B8C4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_50 0x4C4B8C8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_51 0x4C4B8CC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_52 0x4C4B8D0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_53 0x4C4B8D4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_54 0x4C4B8D8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_55 0x4C4B8DC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_56 0x4C4B8E0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_57 0x4C4B8E4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_58 0x4C4B8E8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_59 0x4C4B8EC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_60 0x4C4B8F0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_61 0x4C4B8F4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_62 0x4C4B8F8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_63 0x4C4B8FC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_64 0x4C4B900 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_65 0x4C4B904 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_66 0x4C4B908 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_67 0x4C4B90C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_68 0x4C4B910 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_69 0x4C4B914 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_70 0x4C4B918 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_71 0x4C4B91C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_72 0x4C4B920 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_73 0x4C4B924 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_74 0x4C4B928 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_75 0x4C4B92C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_76 0x4C4B930 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_77 0x4C4B934 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_78 0x4C4B938 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_79 0x4C4B93C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_80 0x4C4B940 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_81 0x4C4B944 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_82 0x4C4B948 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_83 0x4C4B94C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_84 0x4C4B950 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_85 0x4C4B954 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_86 0x4C4B958 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_87 0x4C4B95C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_88 0x4C4B960 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_89 0x4C4B964 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_90 0x4C4B968 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_91 0x4C4B96C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_92 0x4C4B970 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_93 0x4C4B974 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_94 0x4C4B978 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_95 0x4C4B97C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_0 0x4C4B980 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_1 0x4C4B984 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_2 0x4C4B988 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_3 0x4C4B98C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_4 0x4C4B990 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_5 0x4C4B994 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_6 0x4C4B998 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_7 0x4C4B99C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_8 0x4C4B9A0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_9 0x4C4B9A4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_10 0x4C4B9A8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_11 0x4C4B9AC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_12 0x4C4B9B0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_13 0x4C4B9B4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_14 0x4C4B9B8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_15 0x4C4B9BC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_16 0x4C4B9C0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_17 0x4C4B9C4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_18 0x4C4B9C8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_19 0x4C4B9CC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_20 0x4C4B9D0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_21 0x4C4B9D4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_22 0x4C4B9D8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_23 0x4C4B9DC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_24 0x4C4B9E0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_25 0x4C4B9E4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_26 0x4C4B9E8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_27 0x4C4B9EC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_28 0x4C4B9F0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_29 0x4C4B9F4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_30 0x4C4B9F8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_31 0x4C4B9FC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_32 0x4C4BA00 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_33 0x4C4BA04 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_34 0x4C4BA08 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_35 0x4C4BA0C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_36 0x4C4BA10 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_37 0x4C4BA14 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_38 0x4C4BA18 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_39 0x4C4BA1C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_40 0x4C4BA20 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_41 0x4C4BA24 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_42 0x4C4BA28 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_43 0x4C4BA2C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_44 0x4C4BA30 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_45 0x4C4BA34 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_46 0x4C4BA38 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_47 0x4C4BA3C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_48 0x4C4BA40 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_49 0x4C4BA44 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_50 0x4C4BA48 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_51 0x4C4BA4C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_52 0x4C4BA50 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_53 0x4C4BA54 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_54 0x4C4BA58 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_55 0x4C4BA5C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_56 0x4C4BA60 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_57 0x4C4BA64 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_58 0x4C4BA68 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_59 0x4C4BA6C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_60 0x4C4BA70 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_61 0x4C4BA74 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_62 0x4C4BA78 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_63 0x4C4BA7C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_64 0x4C4BA80 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_65 0x4C4BA84 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_66 0x4C4BA88 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_67 0x4C4BA8C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_68 0x4C4BA90 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_69 0x4C4BA94 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_70 0x4C4BA98 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_71 0x4C4BA9C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_72 0x4C4BAA0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_73 0x4C4BAA4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_74 0x4C4BAA8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_75 0x4C4BAAC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_76 0x4C4BAB0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_77 0x4C4BAB4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_78 0x4C4BAB8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_79 0x4C4BABC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_80 0x4C4BAC0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_81 0x4C4BAC4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_82 0x4C4BAC8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_83 0x4C4BACC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_84 0x4C4BAD0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_85 0x4C4BAD4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_86 0x4C4BAD8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_87 0x4C4BADC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_88 0x4C4BAE0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_89 0x4C4BAE4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_90 0x4C4BAE8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_91 0x4C4BAEC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_92 0x4C4BAF0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_93 0x4C4BAF4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_94 0x4C4BAF8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_95 0x4C4BAFC + +#define mmPSOC_GLOBAL_CONF_SMI_ACCESS_EN 0x4C4BB00 + +#define mmPSOC_GLOBAL_CONF_SCRAM_EXTMEM_EN 0x4C4BB38 + +#define mmPSOC_GLOBAL_CONF_SCRAM_PERM_SEL 0x4C4BB3C + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_0 0x4C4BB40 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_1 0x4C4BB44 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_2 0x4C4BB48 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_3 0x4C4BB4C + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_4 0x4C4BB50 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_5 0x4C4BB54 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_6 0x4C4BB58 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_7 0x4C4BB5C + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_8 0x4C4BB60 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_9 0x4C4BB64 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_10 0x4C4BB68 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_11 0x4C4BB6C + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_12 0x4C4BB70 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_13 0x4C4BB74 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_14 0x4C4BB78 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_15 0x4C4BB7C + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_16 0x4C4BB80 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_17 0x4C4BB84 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_18 0x4C4BB88 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_19 0x4C4BB8C + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_20 0x4C4BB90 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_21 0x4C4BB94 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_22 0x4C4BB98 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_23 0x4C4BB9C + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_24 0x4C4BBA0 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_25 0x4C4BBA4 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_26 0x4C4BBA8 + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_27 0x4C4BBAC + +#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_28 0x4C4BBB0 + +#define mmPSOC_GLOBAL_CONF_CORE_MODE 0x4C4BBB4 + +#define mmPSOC_GLOBAL_CONF_EXTMEM_ID_LOC 0x4C4BBB8 + +#define mmPSOC_GLOBAL_CONF_LBW_USER_CTRL 0x4C4BBC0 + +#define mmPSOC_GLOBAL_CONF_ADC_STM_ID 0x4C4BBFC + +#define mmPSOC_GLOBAL_CONF_ADC_0 0x4C4BC00 + +#define mmPSOC_GLOBAL_CONF_ADC_1 0x4C4BC04 + +#define mmPSOC_GLOBAL_CONF_ADC_INT_MASK_0 0x4C4BC10 + +#define mmPSOC_GLOBAL_CONF_ADC_INT_MASK_1 0x4C4BC14 + +#define mmPSOC_GLOBAL_CONF_ADC_CLK_FREQ_0 0x4C4BC20 + +#define mmPSOC_GLOBAL_CONF_ADC_CLK_FREQ_1 0x4C4BC24 + +#define mmPSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_0 0x4C4BC30 + +#define mmPSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_1 0x4C4BC34 + +#define mmPSOC_GLOBAL_CONF_ADC_SAMPLES_0 0x4C4BC40 + +#define mmPSOC_GLOBAL_CONF_ADC_SAMPLES_1 0x4C4BC44 + +#define mmPSOC_GLOBAL_CONF_ADC_TPH_CS_0 0x4C4BC50 + +#define mmPSOC_GLOBAL_CONF_ADC_TPH_CS_1 0x4C4BC54 + +#define mmPSOC_GLOBAL_CONF_ADC_LSB_NMSB_0 0x4C4BC60 + +#define mmPSOC_GLOBAL_CONF_ADC_LSB_NMSB_1 0x4C4BC64 + +#define mmPSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_0 0x4C4BC70 + +#define mmPSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_1 0x4C4BC74 + +#define mmPSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_0 0x4C4BC80 + +#define mmPSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_1 0x4C4BC84 + +#define mmPSOC_GLOBAL_CONF_ADC_TDV_CSDO_0 0x4C4BC90 + +#define mmPSOC_GLOBAL_CONF_ADC_TDV_CSDO_1 0x4C4BC94 + +#define mmPSOC_GLOBAL_CONF_ADC_PID_SEL 0x4C4BC98 + +#define mmPSOC_GLOBAL_CONF_ADC_TSU_CSCK_0 0x4C4BCA0 + +#define mmPSOC_GLOBAL_CONF_ADC_TSU_CSCK_1 0x4C4BCA4 + +#define mmPSOC_GLOBAL_CONF_ADC_CH_SEL_0 0x4C4BCA8 + +#define mmPSOC_GLOBAL_CONF_ADC_CH_SEL_1 0x4C4BCAC + +#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_0 0x4C4BCC0 + +#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_1 0x4C4BCC4 + +#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_2 0x4C4BCC8 + +#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_3 0x4C4BCCC + +#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_4 0x4C4BCD0 + +#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_5 0x4C4BCD4 + +#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_6 0x4C4BCD8 + +#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_7 0x4C4BCDC + +#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_0 0x4C4BCE0 + +#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_1 0x4C4BCE4 + +#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_2 0x4C4BCE8 + +#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_3 0x4C4BCEC + +#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_4 0x4C4BCF0 + +#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_5 0x4C4BCF4 + +#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_6 0x4C4BCF8 + +#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_7 0x4C4BCFC + +#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_0 0x4C4BD00 + +#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_1 0x4C4BD04 + +#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_2 0x4C4BD08 + +#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_3 0x4C4BD0C + +#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_4 0x4C4BD10 + +#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_5 0x4C4BD14 + +#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_6 0x4C4BD18 + +#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_7 0x4C4BD1C + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_CTRL 0x4C4BD24 + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_L 0x4C4BD28 + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_H 0x4C4BD2C + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_L 0x4C4BD30 + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_H 0x4C4BD34 + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_L 0x4C4BD38 + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_H 0x4C4BD3C + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_L 0x4C4BD40 + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_H 0x4C4BD44 + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_L 0x4C4BD48 + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_H 0x4C4BD4C + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_L 0x4C4BD50 + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_H 0x4C4BD54 + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_L 0x4C4BD58 + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_H 0x4C4BD5C + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_L 0x4C4BD60 + +#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_H 0x4C4BD64 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL 0x4C4BD80 + +#define mmPSOC_GLOBAL_CONF_RST_OUT_CTRL 0x4C4BD84 + +#define mmPSOC_GLOBAL_CONF_MEM_CPY_CTRL 0x4C4BD90 + +#define mmPSOC_GLOBAL_CONF_MEM_CPY_STATUS 0x4C4BD94 + +#define mmPSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_H 0x4C4BD98 + +#define mmPSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_L 0x4C4BD9C + +#define mmPSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_H 0x4C4BDA0 + +#define mmPSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_L 0x4C4BDA4 + +#define mmPSOC_GLOBAL_CONF_MEM_CPY_CTRL2 0x4C4BDA8 + +#define mmPSOC_GLOBAL_CONF_MEM_CPY_CONST 0x4C4BDAC + +#define mmPSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_H 0x4C4BDB0 + +#define mmPSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_L 0x4C4BDB4 + +#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_CFG 0x4C4BDC0 + +#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1 0x4C4BDC4 + +#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG0 0x4C4BDC8 + +#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG1 0x4C4BDCC + +#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG2 0x4C4BDD0 + +#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG3 0x4C4BDD4 + +#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4 0x4C4BDD8 + +#define mmPSOC_GLOBAL_CONF_LBW_ARUSER_OVRD 0x4C4BDE0 + +#define mmPSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_EN 0x4C4BDE4 + +#define mmPSOC_GLOBAL_CONF_LBW_AWUSER_OVRD 0x4C4BDE8 + +#define mmPSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_EN 0x4C4BDEC + +#define mmPSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2 0x4C4BDF0 + +#define mmPSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2 0x4C4BDF4 + +#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR 0x4C4BDF8 + +#define mmPSOC_GLOBAL_CONF_MEM_CPY_PROT 0x4C4BE08 + +#define mmPSOC_GLOBAL_CONF_ISOLATE_INPUTS 0x4C4BE10 + +#define mmPSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL 0x4C4BE14 + +#define mmPSOC_GLOBAL_CONF_ARC_JT_SEL 0x4C4BE28 + +#define mmPSOC_GLOBAL_CONF_PLL_DUMP_CRTL 0x4C4BE2C + +#define mmPSOC_GLOBAL_CONF_MEM_CPY_AXUSER 0x4C4BE30 + +#define mmPSOC_GLOBAL_CONF_BTL_AXUSER 0x4C4BE34 + +#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0 0x4C4BE38 + +#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1 0x4C4BE40 + +#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2 0x4C4BE44 + +#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3 0x4C4BE48 + +#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_CTRL 0x4C4BE4C + +#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_TIMEOUT 0x4C4BE50 + +#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_INTR 0x4C4BE54 + +#define mmPSOC_GLOBAL_CONF_BTL_STOP_SPI_CLK 0x4C4BE58 + +#define mmPSOC_GLOBAL_CONF_ECO_INTR_CAUSE 0x4C4BE60 + +#define mmPSOC_GLOBAL_CONF_ECO_INTR_CLEAR 0x4C4BE64 + +#define mmPSOC_GLOBAL_CONF_ECO_INTR_MASK 0x4C4BE68 + +#define mmPSOC_GLOBAL_CONF_DFT_APB_CONTROL 0x4C4BE70 + +#endif /* ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_masks.h new file mode 100644 index 000000000000..e0cf35226e7f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_masks.h @@ -0,0 +1,2321 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_RESET_CONF_MASKS_H_ +#define ASIC_REG_PSOC_RESET_CONF_MASKS_H_ + +/* + ***************************************** + * PSOC_RESET_CONF + * (Prototype: PSOC_RESET_CONF) + ***************************************** + */ + +/* PSOC_RESET_CONF_PSOC_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_PSOC_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PSOC_PRSTN_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PSOC_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_PSOC_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PSOC_SOFT_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PSOC_FW_RST_CFG */ +#define PSOC_RESET_CONF_PSOC_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PSOC_FW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PSOC_WD_RST_CFG */ +#define PSOC_RESET_CONF_PSOC_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PSOC_WD_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PSOC_MNL_RST_CFG */ +#define PSOC_RESET_CONF_PSOC_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PSOC_MNL_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PSOC_FLR_RST_CFG */ +#define PSOC_RESET_CONF_PSOC_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PSOC_FLR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PSOC_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_PSOC_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PSOC_ECC_DERR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PSOC_SW_RST_CFG */ +#define PSOC_RESET_CONF_PSOC_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PSOC_SW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_CPU_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_CPU_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_CPU_PRSTN_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_CPU_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_CPU_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_CPU_SOFT_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_CPU_FW_RST_CFG */ +#define PSOC_RESET_CONF_CPU_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_CPU_FW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_CPU_WD_RST_CFG */ +#define PSOC_RESET_CONF_CPU_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_CPU_WD_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_CPU_MNL_RST_CFG */ +#define PSOC_RESET_CONF_CPU_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_CPU_MNL_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_CPU_FLR_RST_CFG */ +#define PSOC_RESET_CONF_CPU_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_CPU_FLR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_CPU_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_CPU_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_CPU_ECC_DERR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_CPU_SW_RST_CFG */ +#define PSOC_RESET_CONF_CPU_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_CPU_SW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_ARC_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_ARC_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_PRSTN_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ARC_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_ARC_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SOFT_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ARC_FW_RST_CFG */ +#define PSOC_RESET_CONF_ARC_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_FW_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ARC_WD_RST_CFG */ +#define PSOC_RESET_CONF_ARC_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_WD_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ARC_MNL_RST_CFG */ +#define PSOC_RESET_CONF_ARC_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_MNL_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ARC_FLR_RST_CFG */ +#define PSOC_RESET_CONF_ARC_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_FLR_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ARC_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_ARC_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_ECC_DERR_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ARC_SW_RST_CFG */ +#define PSOC_RESET_CONF_ARC_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SW_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_SIF_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_SIF_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SIF_PRSTN_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SIF_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_SIF_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SIF_SOFT_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SIF_FW_RST_CFG */ +#define PSOC_RESET_CONF_SIF_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SIF_FW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SIF_WD_RST_CFG */ +#define PSOC_RESET_CONF_SIF_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SIF_WD_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SIF_MNL_RST_CFG */ +#define PSOC_RESET_CONF_SIF_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SIF_MNL_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SIF_FLR_RST_CFG */ +#define PSOC_RESET_CONF_SIF_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SIF_FLR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SIF_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_SIF_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SIF_ECC_DERR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SIF_SW_RST_CFG */ +#define PSOC_RESET_CONF_SIF_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SIF_SW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SRAM_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_SRAM_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_PRSTN_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SRAM_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_SRAM_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_SOFT_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SRAM_FW_RST_CFG */ +#define PSOC_RESET_CONF_SRAM_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_FW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SRAM_WD_RST_CFG */ +#define PSOC_RESET_CONF_SRAM_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_WD_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SRAM_MNL_RST_CFG */ +#define PSOC_RESET_CONF_SRAM_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_MNL_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SRAM_FLR_RST_CFG */ +#define PSOC_RESET_CONF_SRAM_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_FLR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SRAM_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_SRAM_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_ECC_DERR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SRAM_SW_RST_CFG */ +#define PSOC_RESET_CONF_SRAM_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_SW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_PCIE_CTRL_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_CTRL_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_CTRL_PRSTN_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_CTRL_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_CTRL_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_CTRL_SOFT_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_CTRL_FW_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_CTRL_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_CTRL_FW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_CTRL_WD_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_CTRL_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_CTRL_WD_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_CTRL_MNL_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_CTRL_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_CTRL_MNL_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_CTRL_FLR_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_CTRL_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_CTRL_FLR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_CTRL_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_CTRL_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_CTRL_ECC_DERR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_CTRL_SW_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_CTRL_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_CTRL_SW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_PHY_CFG_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_PHY_CFG_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_PHY_CFG_PRSTN_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_PHY_CFG_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_PHY_CFG_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_PHY_CFG_SOFT_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_PHY_CFG_FW_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_PHY_CFG_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_PHY_CFG_FW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_PHY_CFG_WD_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_PHY_CFG_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_PHY_CFG_WD_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_PHY_CFG_MNL_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_PHY_CFG_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_PHY_CFG_MNL_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_PHY_CFG_FLR_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_PHY_CFG_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_PHY_CFG_FLR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_PHY_CFG_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_PHY_CFG_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_PHY_CFG_ECC_DERR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_PHY_CFG_SW_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_PHY_CFG_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_PHY_CFG_SW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_IF_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_IF_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_IF_PRSTN_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_IF_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_IF_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_IF_SOFT_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_IF_FW_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_IF_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_IF_FW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_IF_WD_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_IF_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_IF_WD_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_IF_MNL_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_IF_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_IF_MNL_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_IF_FLR_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_IF_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_IF_FLR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_IF_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_IF_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_IF_ECC_DERR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_IF_SW_RST_CFG */ +#define PSOC_RESET_CONF_PCIE_IF_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_IF_SW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_TPC_DIV_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_TPC_DIV_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_PRSTN_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_TPC_DIV_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_TPC_DIV_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_SOFT_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_TPC_DIV_FW_RST_CFG */ +#define PSOC_RESET_CONF_TPC_DIV_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_FW_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_TPC_DIV_WD_RST_CFG */ +#define PSOC_RESET_CONF_TPC_DIV_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_WD_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_TPC_DIV_MNL_RST_CFG */ +#define PSOC_RESET_CONF_TPC_DIV_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_MNL_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_TPC_DIV_FLR_RST_CFG */ +#define PSOC_RESET_CONF_TPC_DIV_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_FLR_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_TPC_DIV_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_TPC_DIV_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_ECC_DERR_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_TPC_DIV_SW_RST_CFG */ +#define PSOC_RESET_CONF_TPC_DIV_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_SW_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_HBM_DIV_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_HBM_DIV_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_PRSTN_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_DIV_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_HBM_DIV_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_SOFT_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_DIV_FW_RST_CFG */ +#define PSOC_RESET_CONF_HBM_DIV_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_FW_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_DIV_WD_RST_CFG */ +#define PSOC_RESET_CONF_HBM_DIV_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_WD_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_DIV_MNL_RST_CFG */ +#define PSOC_RESET_CONF_HBM_DIV_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_MNL_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_DIV_FLR_RST_CFG */ +#define PSOC_RESET_CONF_HBM_DIV_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_FLR_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_DIV_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_HBM_DIV_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_ECC_DERR_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_DIV_SW_RST_CFG */ +#define PSOC_RESET_CONF_HBM_DIV_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_SW_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_PMMU_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_PMMU_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PMMU_PRSTN_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PMMU_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_PMMU_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PMMU_SOFT_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PMMU_FW_RST_CFG */ +#define PSOC_RESET_CONF_PMMU_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PMMU_FW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PMMU_WD_RST_CFG */ +#define PSOC_RESET_CONF_PMMU_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PMMU_WD_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PMMU_MNL_RST_CFG */ +#define PSOC_RESET_CONF_PMMU_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PMMU_MNL_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PMMU_FLR_RST_CFG */ +#define PSOC_RESET_CONF_PMMU_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PMMU_FLR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PMMU_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_PMMU_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PMMU_ECC_DERR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PMMU_SW_RST_CFG */ +#define PSOC_RESET_CONF_PMMU_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PMMU_SW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PM_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_PM_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PM_PRSTN_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_PM_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_PM_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PM_SOFT_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_PM_FW_RST_CFG */ +#define PSOC_RESET_CONF_PM_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PM_FW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_PM_WD_RST_CFG */ +#define PSOC_RESET_CONF_PM_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PM_WD_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_PM_MNL_RST_CFG */ +#define PSOC_RESET_CONF_PM_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PM_MNL_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_PM_FLR_RST_CFG */ +#define PSOC_RESET_CONF_PM_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PM_FLR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_PM_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_PM_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PM_ECC_DERR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_PM_SW_RST_CFG */ +#define PSOC_RESET_CONF_PM_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PM_SW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_TS_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_PRSTN_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_TS_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_SOFT_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_FW_RST_CFG */ +#define PSOC_RESET_CONF_TS_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_FW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_WD_RST_CFG */ +#define PSOC_RESET_CONF_TS_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_WD_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_MNL_RST_CFG */ +#define PSOC_RESET_CONF_TS_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_MNL_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_FLR_RST_CFG */ +#define PSOC_RESET_CONF_TS_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_FLR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_TS_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_ECC_DERR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_SW_RST_CFG */ +#define PSOC_RESET_CONF_TS_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_SW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_IF_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_TS_IF_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_PRSTN_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_IF_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_TS_IF_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_SOFT_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_IF_FW_RST_CFG */ +#define PSOC_RESET_CONF_TS_IF_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_FW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_IF_WD_RST_CFG */ +#define PSOC_RESET_CONF_TS_IF_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_WD_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_IF_MNL_RST_CFG */ +#define PSOC_RESET_CONF_TS_IF_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_MNL_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_IF_FLR_RST_CFG */ +#define PSOC_RESET_CONF_TS_IF_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_FLR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_IF_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_TS_IF_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_ECC_DERR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_IF_SW_RST_CFG */ +#define PSOC_RESET_CONF_TS_IF_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_SW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_PLL_L_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_PLL_L_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_PRSTN_RST_CFG_EN_MASK 0xFFFFFFFF + +/* PSOC_RESET_CONF_PLL_L_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_PLL_L_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_SOFT_RST_CFG_EN_MASK 0xFFFFFFFF + +/* PSOC_RESET_CONF_PLL_L_FW_RST_CFG */ +#define PSOC_RESET_CONF_PLL_L_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_FW_RST_CFG_EN_MASK 0xFFFFFFFF + +/* PSOC_RESET_CONF_PLL_L_WD_RST_CFG */ +#define PSOC_RESET_CONF_PLL_L_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_WD_RST_CFG_EN_MASK 0xFFFFFFFF + +/* PSOC_RESET_CONF_PLL_L_MNL_RST_CFG */ +#define PSOC_RESET_CONF_PLL_L_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_MNL_RST_CFG_EN_MASK 0xFFFFFFFF + +/* PSOC_RESET_CONF_PLL_L_FLR_RST_CFG */ +#define PSOC_RESET_CONF_PLL_L_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_FLR_RST_CFG_EN_MASK 0xFFFFFFFF + +/* PSOC_RESET_CONF_PLL_L_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_PLL_L_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_ECC_DERR_RST_CFG_EN_MASK 0xFFFFFFFF + +/* PSOC_RESET_CONF_PLL_L_SW_RST_CFG */ +#define PSOC_RESET_CONF_PLL_L_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_SW_RST_CFG_EN_MASK 0xFFFFFFFF + +/* PSOC_RESET_CONF_PLL_H_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_PLL_H_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_H_PRSTN_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PLL_H_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_PLL_H_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_H_SOFT_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PLL_H_FW_RST_CFG */ +#define PSOC_RESET_CONF_PLL_H_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_H_FW_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PLL_H_WD_RST_CFG */ +#define PSOC_RESET_CONF_PLL_H_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_H_WD_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PLL_H_MNL_RST_CFG */ +#define PSOC_RESET_CONF_PLL_H_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_H_MNL_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PLL_H_FLR_RST_CFG */ +#define PSOC_RESET_CONF_PLL_H_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_H_FLR_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PLL_H_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_PLL_H_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_H_ECC_DERR_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PLL_H_SW_RST_CFG */ +#define PSOC_RESET_CONF_PLL_H_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_H_SW_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_MME_EUS_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_MME_EUS_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_PRSTN_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MME_EUS_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_MME_EUS_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_SOFT_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MME_EUS_FW_RST_CFG */ +#define PSOC_RESET_CONF_MME_EUS_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_FW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MME_EUS_WD_RST_CFG */ +#define PSOC_RESET_CONF_MME_EUS_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_WD_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MME_EUS_MNL_RST_CFG */ +#define PSOC_RESET_CONF_MME_EUS_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_MNL_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MME_EUS_FLR_RST_CFG */ +#define PSOC_RESET_CONF_MME_EUS_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_FLR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MME_EUS_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_MME_EUS_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_ECC_DERR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MME_EUS_SW_RST_CFG */ +#define PSOC_RESET_CONF_MME_EUS_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_SW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MSS_CLS_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_MSS_CLS_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_PRSTN_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MSS_CLS_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_MSS_CLS_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_SOFT_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MSS_CLS_FW_RST_CFG */ +#define PSOC_RESET_CONF_MSS_CLS_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_FW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MSS_CLS_WD_RST_CFG */ +#define PSOC_RESET_CONF_MSS_CLS_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_WD_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MSS_CLS_MNL_RST_CFG */ +#define PSOC_RESET_CONF_MSS_CLS_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_MNL_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MSS_CLS_FLR_RST_CFG */ +#define PSOC_RESET_CONF_MSS_CLS_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_FLR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MSS_CLS_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_MSS_CLS_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_ECC_DERR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_MSS_CLS_SW_RST_CFG */ +#define PSOC_RESET_CONF_MSS_CLS_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_SW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_TPC_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_TPC_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_PRSTN_RST_CFG_EN_MASK 0x1FFFFFF + +/* PSOC_RESET_CONF_TPC_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_TPC_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_SOFT_RST_CFG_EN_MASK 0x1FFFFFF + +/* PSOC_RESET_CONF_TPC_FW_RST_CFG */ +#define PSOC_RESET_CONF_TPC_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_FW_RST_CFG_EN_MASK 0x1FFFFFF + +/* PSOC_RESET_CONF_TPC_WD_RST_CFG */ +#define PSOC_RESET_CONF_TPC_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_WD_RST_CFG_EN_MASK 0x1FFFFFF + +/* PSOC_RESET_CONF_TPC_MNL_RST_CFG */ +#define PSOC_RESET_CONF_TPC_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_MNL_RST_CFG_EN_MASK 0x1FFFFFF + +/* PSOC_RESET_CONF_TPC_FLR_RST_CFG */ +#define PSOC_RESET_CONF_TPC_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_FLR_RST_CFG_EN_MASK 0x1FFFFFF + +/* PSOC_RESET_CONF_TPC_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_TPC_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_ECC_DERR_RST_CFG_EN_MASK 0x1FFFFFF + +/* PSOC_RESET_CONF_TPC_SW_RST_CFG */ +#define PSOC_RESET_CONF_TPC_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_SW_RST_CFG_EN_MASK 0x1FFFFFF + +/* PSOC_RESET_CONF_HIF_HMMU_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_HIF_HMMU_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_PRSTN_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_HIF_HMMU_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_HIF_HMMU_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_SOFT_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_HIF_HMMU_FW_RST_CFG */ +#define PSOC_RESET_CONF_HIF_HMMU_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_FW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_HIF_HMMU_WD_RST_CFG */ +#define PSOC_RESET_CONF_HIF_HMMU_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_WD_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_HIF_HMMU_MNL_RST_CFG */ +#define PSOC_RESET_CONF_HIF_HMMU_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_MNL_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_HIF_HMMU_FLR_RST_CFG */ +#define PSOC_RESET_CONF_HIF_HMMU_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_FLR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_HIF_HMMU_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_HIF_HMMU_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_ECC_DERR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_HIF_HMMU_SW_RST_CFG */ +#define PSOC_RESET_CONF_HIF_HMMU_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_SW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_XBAR_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_XBAR_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_PRSTN_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_XBAR_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_XBAR_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_SOFT_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_XBAR_FW_RST_CFG */ +#define PSOC_RESET_CONF_XBAR_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_FW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_XBAR_WD_RST_CFG */ +#define PSOC_RESET_CONF_XBAR_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_WD_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_XBAR_MNL_RST_CFG */ +#define PSOC_RESET_CONF_XBAR_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_MNL_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_XBAR_FLR_RST_CFG */ +#define PSOC_RESET_CONF_XBAR_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_FLR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_XBAR_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_XBAR_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_ECC_DERR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_XBAR_SW_RST_CFG */ +#define PSOC_RESET_CONF_XBAR_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_SW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SFT_XFT_TFT_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_PRSTN_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SFT_XFT_TFT_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_SOFT_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SFT_XFT_TFT_FW_RST_CFG */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_FW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SFT_XFT_TFT_WD_RST_CFG */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_WD_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SFT_XFT_TFT_MNL_RST_CFG */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_MNL_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SFT_XFT_TFT_FLR_RST_CFG */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_FLR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SFT_XFT_TFT_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_ECC_DERR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SFT_XFT_TFT_SW_RST_CFG */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_SW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_DDMA_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_DDMA_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_PRSTN_RST_CFG_EN_MASK 0xFF + +/* PSOC_RESET_CONF_DDMA_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_DDMA_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_SOFT_RST_CFG_EN_MASK 0xFF + +/* PSOC_RESET_CONF_DDMA_FW_RST_CFG */ +#define PSOC_RESET_CONF_DDMA_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_FW_RST_CFG_EN_MASK 0xFF + +/* PSOC_RESET_CONF_DDMA_WD_RST_CFG */ +#define PSOC_RESET_CONF_DDMA_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_WD_RST_CFG_EN_MASK 0xFF + +/* PSOC_RESET_CONF_DDMA_MNL_RST_CFG */ +#define PSOC_RESET_CONF_DDMA_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_MNL_RST_CFG_EN_MASK 0xFF + +/* PSOC_RESET_CONF_DDMA_FLR_RST_CFG */ +#define PSOC_RESET_CONF_DDMA_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_FLR_RST_CFG_EN_MASK 0xFF + +/* PSOC_RESET_CONF_DDMA_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_DDMA_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_ECC_DERR_RST_CFG_EN_MASK 0xFF + +/* PSOC_RESET_CONF_DDMA_SW_RST_CFG */ +#define PSOC_RESET_CONF_DDMA_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_SW_RST_CFG_EN_MASK 0xFF + +/* PSOC_RESET_CONF_KDMA_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_KDMA_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_KDMA_PRSTN_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_KDMA_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_KDMA_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_KDMA_SOFT_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_KDMA_FW_RST_CFG */ +#define PSOC_RESET_CONF_KDMA_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_KDMA_FW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_KDMA_WD_RST_CFG */ +#define PSOC_RESET_CONF_KDMA_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_KDMA_WD_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_KDMA_MNL_RST_CFG */ +#define PSOC_RESET_CONF_KDMA_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_KDMA_MNL_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_KDMA_FLR_RST_CFG */ +#define PSOC_RESET_CONF_KDMA_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_KDMA_FLR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_KDMA_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_KDMA_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_KDMA_ECC_DERR_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_KDMA_SW_RST_CFG */ +#define PSOC_RESET_CONF_KDMA_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_KDMA_SW_RST_CFG_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PDMA_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_PDMA_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PDMA_PRSTN_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PDMA_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_PDMA_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PDMA_SOFT_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PDMA_FW_RST_CFG */ +#define PSOC_RESET_CONF_PDMA_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PDMA_FW_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PDMA_WD_RST_CFG */ +#define PSOC_RESET_CONF_PDMA_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PDMA_WD_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PDMA_MNL_RST_CFG */ +#define PSOC_RESET_CONF_PDMA_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PDMA_MNL_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PDMA_FLR_RST_CFG */ +#define PSOC_RESET_CONF_PDMA_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PDMA_FLR_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PDMA_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_PDMA_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PDMA_ECC_DERR_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_PDMA_SW_RST_CFG */ +#define PSOC_RESET_CONF_PDMA_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_PDMA_SW_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ARC_SS_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_ARC_SS_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_PRSTN_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_ARC_SS_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_ARC_SS_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_SOFT_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_ARC_SS_FW_RST_CFG */ +#define PSOC_RESET_CONF_ARC_SS_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_FW_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_ARC_SS_WD_RST_CFG */ +#define PSOC_RESET_CONF_ARC_SS_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_WD_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_ARC_SS_MNL_RST_CFG */ +#define PSOC_RESET_CONF_ARC_SS_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_MNL_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_ARC_SS_FLR_RST_CFG */ +#define PSOC_RESET_CONF_ARC_SS_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_FLR_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_ARC_SS_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_ARC_SS_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_ECC_DERR_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_ARC_SS_SW_RST_CFG */ +#define PSOC_RESET_CONF_ARC_SS_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_SW_RST_CFG_EN_MASK 0x1F + +/* PSOC_RESET_CONF_ROTATOR_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_ROTATOR_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ROTATOR_PRSTN_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ROTATOR_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_ROTATOR_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ROTATOR_SOFT_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ROTATOR_FW_RST_CFG */ +#define PSOC_RESET_CONF_ROTATOR_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ROTATOR_FW_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ROTATOR_WD_RST_CFG */ +#define PSOC_RESET_CONF_ROTATOR_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ROTATOR_WD_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ROTATOR_MNL_RST_CFG */ +#define PSOC_RESET_CONF_ROTATOR_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ROTATOR_MNL_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ROTATOR_FLR_RST_CFG */ +#define PSOC_RESET_CONF_ROTATOR_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ROTATOR_FLR_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ROTATOR_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_ROTATOR_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ROTATOR_ECC_DERR_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ROTATOR_SW_RST_CFG */ +#define PSOC_RESET_CONF_ROTATOR_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_ROTATOR_SW_RST_CFG_EN_MASK 0x3 + +/* PSOC_RESET_CONF_SM_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_SM_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SM_PRSTN_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SM_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_SM_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SM_SOFT_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SM_FW_RST_CFG */ +#define PSOC_RESET_CONF_SM_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SM_FW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SM_WD_RST_CFG */ +#define PSOC_RESET_CONF_SM_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SM_WD_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SM_MNL_RST_CFG */ +#define PSOC_RESET_CONF_SM_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SM_MNL_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SM_FLR_RST_CFG */ +#define PSOC_RESET_CONF_SM_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SM_FLR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SM_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_SM_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SM_ECC_DERR_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_SM_SW_RST_CFG */ +#define PSOC_RESET_CONF_SM_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_SM_SW_RST_CFG_EN_MASK 0xF + +/* PSOC_RESET_CONF_VIDEO_DEC_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_VIDEO_DEC_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_PRSTN_RST_CFG_EN_MASK 0x3FF + +/* PSOC_RESET_CONF_VIDEO_DEC_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_VIDEO_DEC_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_SOFT_RST_CFG_EN_MASK 0x3FF + +/* PSOC_RESET_CONF_VIDEO_DEC_FW_RST_CFG */ +#define PSOC_RESET_CONF_VIDEO_DEC_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_FW_RST_CFG_EN_MASK 0x3FF + +/* PSOC_RESET_CONF_VIDEO_DEC_WD_RST_CFG */ +#define PSOC_RESET_CONF_VIDEO_DEC_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_WD_RST_CFG_EN_MASK 0x3FF + +/* PSOC_RESET_CONF_VIDEO_DEC_MNL_RST_CFG */ +#define PSOC_RESET_CONF_VIDEO_DEC_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_MNL_RST_CFG_EN_MASK 0x3FF + +/* PSOC_RESET_CONF_VIDEO_DEC_FLR_RST_CFG */ +#define PSOC_RESET_CONF_VIDEO_DEC_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_FLR_RST_CFG_EN_MASK 0x3FF + +/* PSOC_RESET_CONF_VIDEO_DEC_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_VIDEO_DEC_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_ECC_DERR_RST_CFG_EN_MASK 0x3FF + +/* PSOC_RESET_CONF_VIDEO_DEC_SW_RST_CFG */ +#define PSOC_RESET_CONF_VIDEO_DEC_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_SW_RST_CFG_EN_MASK 0x3FF + +/* PSOC_RESET_CONF_HBM_MC_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_HBM_MC_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_PRSTN_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_MC_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_HBM_MC_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_SOFT_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_MC_FW_RST_CFG */ +#define PSOC_RESET_CONF_HBM_MC_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_FW_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_MC_WD_RST_CFG */ +#define PSOC_RESET_CONF_HBM_MC_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_WD_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_MC_MNL_RST_CFG */ +#define PSOC_RESET_CONF_HBM_MC_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_MNL_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_MC_FLR_RST_CFG */ +#define PSOC_RESET_CONF_HBM_MC_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_FLR_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_MC_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_HBM_MC_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_ECC_DERR_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_HBM_MC_SW_RST_CFG */ +#define PSOC_RESET_CONF_HBM_MC_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_SW_RST_CFG_EN_MASK 0x3F + +/* PSOC_RESET_CONF_NIC_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_NIC_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRSTN_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_NIC_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_SOFT_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_FW_RST_CFG */ +#define PSOC_RESET_CONF_NIC_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_FW_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_WD_RST_CFG */ +#define PSOC_RESET_CONF_NIC_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_WD_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_MNL_RST_CFG */ +#define PSOC_RESET_CONF_NIC_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_MNL_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_FLR_RST_CFG */ +#define PSOC_RESET_CONF_NIC_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_FLR_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_NIC_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_ECC_DERR_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_SW_RST_CFG */ +#define PSOC_RESET_CONF_NIC_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_SW_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_PRT_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_NIC_PRT_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_PRSTN_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_PRT_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_NIC_PRT_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_SOFT_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_PRT_FW_RST_CFG */ +#define PSOC_RESET_CONF_NIC_PRT_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_FW_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_PRT_WD_RST_CFG */ +#define PSOC_RESET_CONF_NIC_PRT_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_WD_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_PRT_MNL_RST_CFG */ +#define PSOC_RESET_CONF_NIC_PRT_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_MNL_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_PRT_FLR_RST_CFG */ +#define PSOC_RESET_CONF_NIC_PRT_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_FLR_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_PRT_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_NIC_PRT_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_ECC_DERR_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_PRT_SW_RST_CFG */ +#define PSOC_RESET_CONF_NIC_PRT_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_SW_RST_CFG_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_CH_PRSTN_RST_CFG */ +#define PSOC_RESET_CONF_NIC_CH_PRSTN_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_CH_PRSTN_RST_CFG_EN_MASK 0x7 + +/* PSOC_RESET_CONF_NIC_CH_SOFT_RST_CFG */ +#define PSOC_RESET_CONF_NIC_CH_SOFT_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_CH_SOFT_RST_CFG_EN_MASK 0x7 + +/* PSOC_RESET_CONF_NIC_CH_FW_RST_CFG */ +#define PSOC_RESET_CONF_NIC_CH_FW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_CH_FW_RST_CFG_EN_MASK 0x7 + +/* PSOC_RESET_CONF_NIC_CH_WD_RST_CFG */ +#define PSOC_RESET_CONF_NIC_CH_WD_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_CH_WD_RST_CFG_EN_MASK 0x7 + +/* PSOC_RESET_CONF_NIC_CH_MNL_RST_CFG */ +#define PSOC_RESET_CONF_NIC_CH_MNL_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_CH_MNL_RST_CFG_EN_MASK 0x7 + +/* PSOC_RESET_CONF_NIC_CH_FLR_RST_CFG */ +#define PSOC_RESET_CONF_NIC_CH_FLR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_CH_FLR_RST_CFG_EN_MASK 0x7 + +/* PSOC_RESET_CONF_NIC_CH_ECC_DERR_RST_CFG */ +#define PSOC_RESET_CONF_NIC_CH_ECC_DERR_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_CH_ECC_DERR_RST_CFG_EN_MASK 0x7 + +/* PSOC_RESET_CONF_NIC_CH_SW_RST_CFG */ +#define PSOC_RESET_CONF_NIC_CH_SW_RST_CFG_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_CH_SW_RST_CFG_EN_MASK 0x7 + +/* PSOC_RESET_CONF_SOFT_RST */ +#define PSOC_RESET_CONF_SOFT_RST_IND_SHIFT 0 +#define PSOC_RESET_CONF_SOFT_RST_IND_MASK 0x1 + +/* PSOC_RESET_CONF_SW_ALL_RST */ +#define PSOC_RESET_CONF_SW_ALL_RST_IND_SHIFT 0 +#define PSOC_RESET_CONF_SW_ALL_RST_IND_MASK 0x1 + +/* PSOC_RESET_CONF_UNIT_RST_N */ +#define PSOC_RESET_CONF_UNIT_RST_N_IND_SHIFT 0 +#define PSOC_RESET_CONF_UNIT_RST_N_IND_MASK 0x1 + +/* PSOC_RESET_CONF_PSOC_UNIT_RST */ +#define PSOC_RESET_CONF_PSOC_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_PSOC_UNIT_RST_EN_MASK 0x1 + +/* PSOC_RESET_CONF_CPU_UNIT_RST */ +#define PSOC_RESET_CONF_CPU_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_CPU_UNIT_RST_EN_MASK 0x1 + +/* PSOC_RESET_CONF_ARC_UNIT_RST */ +#define PSOC_RESET_CONF_ARC_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_UNIT_RST_EN_MASK 0x3 + +/* PSOC_RESET_CONF_SIF_UNIT_RST */ +#define PSOC_RESET_CONF_SIF_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_SIF_UNIT_RST_EN_MASK 0xF + +/* PSOC_RESET_CONF_SRAM_UNIT_RST */ +#define PSOC_RESET_CONF_SRAM_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_UNIT_RST_EN_MASK 0xF + +/* PSOC_RESET_CONF_PCIE_CTRL_UNIT_RST */ +#define PSOC_RESET_CONF_PCIE_CTRL_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_CTRL_UNIT_RST_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_PHY_CFG_UNIT_RST */ +#define PSOC_RESET_CONF_PCIE_PHY_CFG_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_PHY_CFG_UNIT_RST_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PCIE_IF_UNIT_RST */ +#define PSOC_RESET_CONF_PCIE_IF_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_IF_UNIT_RST_EN_MASK 0x1 + +/* PSOC_RESET_CONF_TPC_DIV_UNIT_RST */ +#define PSOC_RESET_CONF_TPC_DIV_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_UNIT_RST_EN_MASK 0x1F + +/* PSOC_RESET_CONF_HBM_DIV_UNIT_RST */ +#define PSOC_RESET_CONF_HBM_DIV_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_UNIT_RST_EN_MASK 0x3F + +/* PSOC_RESET_CONF_PMMU_UNIT_RST */ +#define PSOC_RESET_CONF_PMMU_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_PMMU_UNIT_RST_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PM_UNIT_RST */ +#define PSOC_RESET_CONF_PM_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_PM_UNIT_RST_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_UNIT_RST */ +#define PSOC_RESET_CONF_TS_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_UNIT_RST_EN_MASK 0xF + +/* PSOC_RESET_CONF_TS_IF_UNIT_RST */ +#define PSOC_RESET_CONF_TS_IF_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_UNIT_RST_EN_MASK 0xF + +/* PSOC_RESET_CONF_PLL_L_UNIT_RST */ +#define PSOC_RESET_CONF_PLL_L_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_UNIT_RST_EN_MASK 0xFFFFFFFF + +/* PSOC_RESET_CONF_PLL_H_UNIT_RST */ +#define PSOC_RESET_CONF_PLL_H_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_PLL_H_UNIT_RST_EN_MASK 0x3 + +/* PSOC_RESET_CONF_MME_EUS_UNIT_RST */ +#define PSOC_RESET_CONF_MME_EUS_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_UNIT_RST_EN_MASK 0xF + +/* PSOC_RESET_CONF_MSS_CLS_UNIT_RST */ +#define PSOC_RESET_CONF_MSS_CLS_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_UNIT_RST_EN_MASK 0xF + +/* PSOC_RESET_CONF_TPC_UNIT_RST */ +#define PSOC_RESET_CONF_TPC_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_TPC_UNIT_RST_EN_MASK 0x1FFFFFF + +/* PSOC_RESET_CONF_HIF_HMMU_UNIT_RST */ +#define PSOC_RESET_CONF_HIF_HMMU_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_UNIT_RST_EN_MASK 0xF + +/* PSOC_RESET_CONF_XBAR_UNIT_RST */ +#define PSOC_RESET_CONF_XBAR_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_UNIT_RST_EN_MASK 0xF + +/* PSOC_RESET_CONF_SFT_XFT_TFT_UNIT_RST */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_UNIT_RST_EN_MASK 0xF + +/* PSOC_RESET_CONF_DDMA_UNIT_RST */ +#define PSOC_RESET_CONF_DDMA_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_UNIT_RST_EN_MASK 0xFF + +/* PSOC_RESET_CONF_KDMA_UNIT_RST */ +#define PSOC_RESET_CONF_KDMA_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_KDMA_UNIT_RST_EN_MASK 0x1 + +/* PSOC_RESET_CONF_PDMA_UNIT_RST */ +#define PSOC_RESET_CONF_PDMA_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_PDMA_UNIT_RST_EN_MASK 0x3 + +/* PSOC_RESET_CONF_ARC_SS_UNIT_RST */ +#define PSOC_RESET_CONF_ARC_SS_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_UNIT_RST_EN_MASK 0x1F + +/* PSOC_RESET_CONF_ROTATOR_UNIT_RST */ +#define PSOC_RESET_CONF_ROTATOR_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_ROTATOR_UNIT_RST_EN_MASK 0x3 + +/* PSOC_RESET_CONF_SM_UNIT_RST */ +#define PSOC_RESET_CONF_SM_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_SM_UNIT_RST_EN_MASK 0xF + +/* PSOC_RESET_CONF_VIDEO_DEC_UNIT_RST */ +#define PSOC_RESET_CONF_VIDEO_DEC_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_UNIT_RST_EN_MASK 0x3FF + +/* PSOC_RESET_CONF_HBM_MC_UNIT_RST */ +#define PSOC_RESET_CONF_HBM_MC_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_UNIT_RST_EN_MASK 0x3F + +/* PSOC_RESET_CONF_NIC_UNIT_RST */ +#define PSOC_RESET_CONF_NIC_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_UNIT_RST_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_PRT_UNIT_RST */ +#define PSOC_RESET_CONF_NIC_PRT_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_UNIT_RST_EN_MASK 0xFFF + +/* PSOC_RESET_CONF_NIC_CH_UNIT_RST */ +#define PSOC_RESET_CONF_NIC_CH_UNIT_RST_EN_SHIFT 0 +#define PSOC_RESET_CONF_NIC_CH_UNIT_RST_EN_MASK 0x7 + +/* PSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_CPU_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_CPU_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_CPU_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_CPU_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_CPU_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_ARC_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_ARC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_ARC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_ARC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_ARC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_ARC_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_ARC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_ARC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_ARC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_ARC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SIF_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SIF_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SIF_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SIF_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SIF_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SIF_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SIF_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SIF_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SIF_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SIF_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SIF_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SIF_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SIF_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SIF_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SIF_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SIF_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SIF_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SIF_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SIF_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SIF_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PM_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PM_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PM_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PM_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PM_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PM_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PM_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PM_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PM_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PM_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PM_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PM_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PM_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PM_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PM_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PM_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PM_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PM_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PM_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PM_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TS_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TS_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TS_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TS_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TS_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TS_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TS_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TS_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TS_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TS_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TS_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TS_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TS_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TS_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TS_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TS_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TS_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TS_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TS_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TS_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_4_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_4_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_5_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_5_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_6_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_6_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_7_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_7_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_8_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_8_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_9_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_9_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_10_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_10_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_10_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_10_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_10_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_11_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_11_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_11_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_11_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_11_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_12_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_12_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_12_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_12_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_12_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_13_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_13_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_13_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_13_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_13_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_14_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_14_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_14_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_14_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_14_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_15_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_15_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_15_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_15_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_15_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_16_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_16_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_16_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_16_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_16_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_17_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_17_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_17_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_17_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_17_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_18_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_18_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_18_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_18_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_18_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_19_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_19_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_19_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_19_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_19_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_20_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_20_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_20_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_20_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_20_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_21_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_21_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_21_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_21_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_21_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_22_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_22_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_22_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_22_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_22_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_23_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_23_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_23_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_23_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_23_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_TPC_24_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_TPC_24_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_TPC_24_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_TPC_24_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_TPC_24_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SM_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SM_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SM_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SM_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SM_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SM_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SM_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SM_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SM_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SM_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SM_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SM_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SM_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SM_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SM_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_SM_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_SM_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_SM_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_SM_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_SM_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_4_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_4_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_5_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_5_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_6_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_6_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_7_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_7_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_8_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_8_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_9_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_9_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_10_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_10_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_10_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_10_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_10_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_11_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_11_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_11_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_11_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_11_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +/* PSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL */ +#define PSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL_RST_SEL_SHIFT 0 +#define PSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF +#define PSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16 +#define PSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000 + +#endif /* ASIC_REG_PSOC_RESET_CONF_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_regs.h new file mode 100644 index 000000000000..6a89624f01d1 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_regs.h @@ -0,0 +1,989 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_RESET_CONF_REGS_H_ +#define ASIC_REG_PSOC_RESET_CONF_REGS_H_ + +/* + ***************************************** + * PSOC_RESET_CONF + * (Prototype: PSOC_RESET_CONF) + ***************************************** + */ + +#define mmPSOC_RESET_CONF_PSOC_PRSTN_RST_CFG 0x4C74000 + +#define mmPSOC_RESET_CONF_PSOC_SOFT_RST_CFG 0x4C74004 + +#define mmPSOC_RESET_CONF_PSOC_FW_RST_CFG 0x4C74008 + +#define mmPSOC_RESET_CONF_PSOC_WD_RST_CFG 0x4C7400C + +#define mmPSOC_RESET_CONF_PSOC_MNL_RST_CFG 0x4C74010 + +#define mmPSOC_RESET_CONF_PSOC_FLR_RST_CFG 0x4C74014 + +#define mmPSOC_RESET_CONF_PSOC_ECC_DERR_RST_CFG 0x4C74018 + +#define mmPSOC_RESET_CONF_PSOC_SW_RST_CFG 0x4C7401C + +#define mmPSOC_RESET_CONF_CPU_PRSTN_RST_CFG 0x4C74020 + +#define mmPSOC_RESET_CONF_CPU_SOFT_RST_CFG 0x4C74024 + +#define mmPSOC_RESET_CONF_CPU_FW_RST_CFG 0x4C74028 + +#define mmPSOC_RESET_CONF_CPU_WD_RST_CFG 0x4C7402C + +#define mmPSOC_RESET_CONF_CPU_MNL_RST_CFG 0x4C74030 + +#define mmPSOC_RESET_CONF_CPU_FLR_RST_CFG 0x4C74034 + +#define mmPSOC_RESET_CONF_CPU_ECC_DERR_RST_CFG 0x4C74038 + +#define mmPSOC_RESET_CONF_CPU_SW_RST_CFG 0x4C7403C + +#define mmPSOC_RESET_CONF_ARC_PRSTN_RST_CFG 0x4C74040 + +#define mmPSOC_RESET_CONF_ARC_SOFT_RST_CFG 0x4C74044 + +#define mmPSOC_RESET_CONF_ARC_FW_RST_CFG 0x4C74048 + +#define mmPSOC_RESET_CONF_ARC_WD_RST_CFG 0x4C7404C + +#define mmPSOC_RESET_CONF_ARC_MNL_RST_CFG 0x4C74050 + +#define mmPSOC_RESET_CONF_ARC_FLR_RST_CFG 0x4C74054 + +#define mmPSOC_RESET_CONF_ARC_ECC_DERR_RST_CFG 0x4C74058 + +#define mmPSOC_RESET_CONF_ARC_SW_RST_CFG 0x4C7405C + +#define mmPSOC_RESET_CONF_SIF_PRSTN_RST_CFG 0x4C74060 + +#define mmPSOC_RESET_CONF_SIF_SOFT_RST_CFG 0x4C74064 + +#define mmPSOC_RESET_CONF_SIF_FW_RST_CFG 0x4C74068 + +#define mmPSOC_RESET_CONF_SIF_WD_RST_CFG 0x4C7406C + +#define mmPSOC_RESET_CONF_SIF_MNL_RST_CFG 0x4C74070 + +#define mmPSOC_RESET_CONF_SIF_FLR_RST_CFG 0x4C74074 + +#define mmPSOC_RESET_CONF_SIF_ECC_DERR_RST_CFG 0x4C74078 + +#define mmPSOC_RESET_CONF_SIF_SW_RST_CFG 0x4C7407C + +#define mmPSOC_RESET_CONF_SRAM_PRSTN_RST_CFG 0x4C74080 + +#define mmPSOC_RESET_CONF_SRAM_SOFT_RST_CFG 0x4C74084 + +#define mmPSOC_RESET_CONF_SRAM_FW_RST_CFG 0x4C74088 + +#define mmPSOC_RESET_CONF_SRAM_WD_RST_CFG 0x4C7408C + +#define mmPSOC_RESET_CONF_SRAM_MNL_RST_CFG 0x4C74090 + +#define mmPSOC_RESET_CONF_SRAM_FLR_RST_CFG 0x4C74094 + +#define mmPSOC_RESET_CONF_SRAM_ECC_DERR_RST_CFG 0x4C74098 + +#define mmPSOC_RESET_CONF_SRAM_SW_RST_CFG 0x4C7409C + +#define mmPSOC_RESET_CONF_PCIE_CTRL_PRSTN_RST_CFG 0x4C740A0 + +#define mmPSOC_RESET_CONF_PCIE_CTRL_SOFT_RST_CFG 0x4C740A4 + +#define mmPSOC_RESET_CONF_PCIE_CTRL_FW_RST_CFG 0x4C740A8 + +#define mmPSOC_RESET_CONF_PCIE_CTRL_WD_RST_CFG 0x4C740AC + +#define mmPSOC_RESET_CONF_PCIE_CTRL_MNL_RST_CFG 0x4C740B0 + +#define mmPSOC_RESET_CONF_PCIE_CTRL_FLR_RST_CFG 0x4C740B4 + +#define mmPSOC_RESET_CONF_PCIE_CTRL_ECC_DERR_RST_CFG 0x4C740B8 + +#define mmPSOC_RESET_CONF_PCIE_CTRL_SW_RST_CFG 0x4C740BC + +#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_PRSTN_RST_CFG 0x4C740C0 + +#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_SOFT_RST_CFG 0x4C740C4 + +#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_FW_RST_CFG 0x4C740C8 + +#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_WD_RST_CFG 0x4C740CC + +#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_MNL_RST_CFG 0x4C740D0 + +#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_FLR_RST_CFG 0x4C740D4 + +#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_ECC_DERR_RST_CFG 0x4C740D8 + +#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_SW_RST_CFG 0x4C740DC + +#define mmPSOC_RESET_CONF_PCIE_IF_PRSTN_RST_CFG 0x4C740E0 + +#define mmPSOC_RESET_CONF_PCIE_IF_SOFT_RST_CFG 0x4C740E4 + +#define mmPSOC_RESET_CONF_PCIE_IF_FW_RST_CFG 0x4C740E8 + +#define mmPSOC_RESET_CONF_PCIE_IF_WD_RST_CFG 0x4C740EC + +#define mmPSOC_RESET_CONF_PCIE_IF_MNL_RST_CFG 0x4C740F0 + +#define mmPSOC_RESET_CONF_PCIE_IF_FLR_RST_CFG 0x4C740F4 + +#define mmPSOC_RESET_CONF_PCIE_IF_ECC_DERR_RST_CFG 0x4C740F8 + +#define mmPSOC_RESET_CONF_PCIE_IF_SW_RST_CFG 0x4C740FC + +#define mmPSOC_RESET_CONF_TPC_DIV_PRSTN_RST_CFG 0x4C74100 + +#define mmPSOC_RESET_CONF_TPC_DIV_SOFT_RST_CFG 0x4C74104 + +#define mmPSOC_RESET_CONF_TPC_DIV_FW_RST_CFG 0x4C74108 + +#define mmPSOC_RESET_CONF_TPC_DIV_WD_RST_CFG 0x4C7410C + +#define mmPSOC_RESET_CONF_TPC_DIV_MNL_RST_CFG 0x4C74110 + +#define mmPSOC_RESET_CONF_TPC_DIV_FLR_RST_CFG 0x4C74114 + +#define mmPSOC_RESET_CONF_TPC_DIV_ECC_DERR_RST_CFG 0x4C74118 + +#define mmPSOC_RESET_CONF_TPC_DIV_SW_RST_CFG 0x4C7411C + +#define mmPSOC_RESET_CONF_HBM_DIV_PRSTN_RST_CFG 0x4C74120 + +#define mmPSOC_RESET_CONF_HBM_DIV_SOFT_RST_CFG 0x4C74124 + +#define mmPSOC_RESET_CONF_HBM_DIV_FW_RST_CFG 0x4C74128 + +#define mmPSOC_RESET_CONF_HBM_DIV_WD_RST_CFG 0x4C7412C + +#define mmPSOC_RESET_CONF_HBM_DIV_MNL_RST_CFG 0x4C74130 + +#define mmPSOC_RESET_CONF_HBM_DIV_FLR_RST_CFG 0x4C74134 + +#define mmPSOC_RESET_CONF_HBM_DIV_ECC_DERR_RST_CFG 0x4C74138 + +#define mmPSOC_RESET_CONF_HBM_DIV_SW_RST_CFG 0x4C7413C + +#define mmPSOC_RESET_CONF_PMMU_PRSTN_RST_CFG 0x4C74140 + +#define mmPSOC_RESET_CONF_PMMU_SOFT_RST_CFG 0x4C74144 + +#define mmPSOC_RESET_CONF_PMMU_FW_RST_CFG 0x4C74148 + +#define mmPSOC_RESET_CONF_PMMU_WD_RST_CFG 0x4C7414C + +#define mmPSOC_RESET_CONF_PMMU_MNL_RST_CFG 0x4C74150 + +#define mmPSOC_RESET_CONF_PMMU_FLR_RST_CFG 0x4C74154 + +#define mmPSOC_RESET_CONF_PMMU_ECC_DERR_RST_CFG 0x4C74158 + +#define mmPSOC_RESET_CONF_PMMU_SW_RST_CFG 0x4C7415C + +#define mmPSOC_RESET_CONF_PM_PRSTN_RST_CFG 0x4C74160 + +#define mmPSOC_RESET_CONF_PM_SOFT_RST_CFG 0x4C74164 + +#define mmPSOC_RESET_CONF_PM_FW_RST_CFG 0x4C74168 + +#define mmPSOC_RESET_CONF_PM_WD_RST_CFG 0x4C7416C + +#define mmPSOC_RESET_CONF_PM_MNL_RST_CFG 0x4C74170 + +#define mmPSOC_RESET_CONF_PM_FLR_RST_CFG 0x4C74174 + +#define mmPSOC_RESET_CONF_PM_ECC_DERR_RST_CFG 0x4C74178 + +#define mmPSOC_RESET_CONF_PM_SW_RST_CFG 0x4C7417C + +#define mmPSOC_RESET_CONF_TS_PRSTN_RST_CFG 0x4C74180 + +#define mmPSOC_RESET_CONF_TS_SOFT_RST_CFG 0x4C74184 + +#define mmPSOC_RESET_CONF_TS_FW_RST_CFG 0x4C74188 + +#define mmPSOC_RESET_CONF_TS_WD_RST_CFG 0x4C7418C + +#define mmPSOC_RESET_CONF_TS_MNL_RST_CFG 0x4C74190 + +#define mmPSOC_RESET_CONF_TS_FLR_RST_CFG 0x4C74194 + +#define mmPSOC_RESET_CONF_TS_ECC_DERR_RST_CFG 0x4C74198 + +#define mmPSOC_RESET_CONF_TS_SW_RST_CFG 0x4C7419C + +#define mmPSOC_RESET_CONF_TS_IF_PRSTN_RST_CFG 0x4C741A0 + +#define mmPSOC_RESET_CONF_TS_IF_SOFT_RST_CFG 0x4C741A4 + +#define mmPSOC_RESET_CONF_TS_IF_FW_RST_CFG 0x4C741A8 + +#define mmPSOC_RESET_CONF_TS_IF_WD_RST_CFG 0x4C741AC + +#define mmPSOC_RESET_CONF_TS_IF_MNL_RST_CFG 0x4C741B0 + +#define mmPSOC_RESET_CONF_TS_IF_FLR_RST_CFG 0x4C741B4 + +#define mmPSOC_RESET_CONF_TS_IF_ECC_DERR_RST_CFG 0x4C741B8 + +#define mmPSOC_RESET_CONF_TS_IF_SW_RST_CFG 0x4C741BC + +#define mmPSOC_RESET_CONF_PLL_L_PRSTN_RST_CFG 0x4C741C0 + +#define mmPSOC_RESET_CONF_PLL_L_SOFT_RST_CFG 0x4C741C4 + +#define mmPSOC_RESET_CONF_PLL_L_FW_RST_CFG 0x4C741C8 + +#define mmPSOC_RESET_CONF_PLL_L_WD_RST_CFG 0x4C741CC + +#define mmPSOC_RESET_CONF_PLL_L_MNL_RST_CFG 0x4C741D0 + +#define mmPSOC_RESET_CONF_PLL_L_FLR_RST_CFG 0x4C741D4 + +#define mmPSOC_RESET_CONF_PLL_L_ECC_DERR_RST_CFG 0x4C741D8 + +#define mmPSOC_RESET_CONF_PLL_L_SW_RST_CFG 0x4C741DC + +#define mmPSOC_RESET_CONF_PLL_H_PRSTN_RST_CFG 0x4C741E0 + +#define mmPSOC_RESET_CONF_PLL_H_SOFT_RST_CFG 0x4C741E4 + +#define mmPSOC_RESET_CONF_PLL_H_FW_RST_CFG 0x4C741E8 + +#define mmPSOC_RESET_CONF_PLL_H_WD_RST_CFG 0x4C741EC + +#define mmPSOC_RESET_CONF_PLL_H_MNL_RST_CFG 0x4C741F0 + +#define mmPSOC_RESET_CONF_PLL_H_FLR_RST_CFG 0x4C741F4 + +#define mmPSOC_RESET_CONF_PLL_H_ECC_DERR_RST_CFG 0x4C741F8 + +#define mmPSOC_RESET_CONF_PLL_H_SW_RST_CFG 0x4C741FC + +#define mmPSOC_RESET_CONF_MME_EUS_PRSTN_RST_CFG 0x4C74200 + +#define mmPSOC_RESET_CONF_MME_EUS_SOFT_RST_CFG 0x4C74204 + +#define mmPSOC_RESET_CONF_MME_EUS_FW_RST_CFG 0x4C74208 + +#define mmPSOC_RESET_CONF_MME_EUS_WD_RST_CFG 0x4C7420C + +#define mmPSOC_RESET_CONF_MME_EUS_MNL_RST_CFG 0x4C74210 + +#define mmPSOC_RESET_CONF_MME_EUS_FLR_RST_CFG 0x4C74214 + +#define mmPSOC_RESET_CONF_MME_EUS_ECC_DERR_RST_CFG 0x4C74218 + +#define mmPSOC_RESET_CONF_MME_EUS_SW_RST_CFG 0x4C7421C + +#define mmPSOC_RESET_CONF_MSS_CLS_PRSTN_RST_CFG 0x4C74220 + +#define mmPSOC_RESET_CONF_MSS_CLS_SOFT_RST_CFG 0x4C74224 + +#define mmPSOC_RESET_CONF_MSS_CLS_FW_RST_CFG 0x4C74228 + +#define mmPSOC_RESET_CONF_MSS_CLS_WD_RST_CFG 0x4C7422C + +#define mmPSOC_RESET_CONF_MSS_CLS_MNL_RST_CFG 0x4C74230 + +#define mmPSOC_RESET_CONF_MSS_CLS_FLR_RST_CFG 0x4C74234 + +#define mmPSOC_RESET_CONF_MSS_CLS_ECC_DERR_RST_CFG 0x4C74238 + +#define mmPSOC_RESET_CONF_MSS_CLS_SW_RST_CFG 0x4C7423C + +#define mmPSOC_RESET_CONF_TPC_PRSTN_RST_CFG 0x4C74240 + +#define mmPSOC_RESET_CONF_TPC_SOFT_RST_CFG 0x4C74244 + +#define mmPSOC_RESET_CONF_TPC_FW_RST_CFG 0x4C74248 + +#define mmPSOC_RESET_CONF_TPC_WD_RST_CFG 0x4C7424C + +#define mmPSOC_RESET_CONF_TPC_MNL_RST_CFG 0x4C74250 + +#define mmPSOC_RESET_CONF_TPC_FLR_RST_CFG 0x4C74254 + +#define mmPSOC_RESET_CONF_TPC_ECC_DERR_RST_CFG 0x4C74258 + +#define mmPSOC_RESET_CONF_TPC_SW_RST_CFG 0x4C7425C + +#define mmPSOC_RESET_CONF_HIF_HMMU_PRSTN_RST_CFG 0x4C74260 + +#define mmPSOC_RESET_CONF_HIF_HMMU_SOFT_RST_CFG 0x4C74264 + +#define mmPSOC_RESET_CONF_HIF_HMMU_FW_RST_CFG 0x4C74268 + +#define mmPSOC_RESET_CONF_HIF_HMMU_WD_RST_CFG 0x4C7426C + +#define mmPSOC_RESET_CONF_HIF_HMMU_MNL_RST_CFG 0x4C74270 + +#define mmPSOC_RESET_CONF_HIF_HMMU_FLR_RST_CFG 0x4C74274 + +#define mmPSOC_RESET_CONF_HIF_HMMU_ECC_DERR_RST_CFG 0x4C74278 + +#define mmPSOC_RESET_CONF_HIF_HMMU_SW_RST_CFG 0x4C7427C + +#define mmPSOC_RESET_CONF_XBAR_PRSTN_RST_CFG 0x4C74280 + +#define mmPSOC_RESET_CONF_XBAR_SOFT_RST_CFG 0x4C74284 + +#define mmPSOC_RESET_CONF_XBAR_FW_RST_CFG 0x4C74288 + +#define mmPSOC_RESET_CONF_XBAR_WD_RST_CFG 0x4C7428C + +#define mmPSOC_RESET_CONF_XBAR_MNL_RST_CFG 0x4C74290 + +#define mmPSOC_RESET_CONF_XBAR_FLR_RST_CFG 0x4C74294 + +#define mmPSOC_RESET_CONF_XBAR_ECC_DERR_RST_CFG 0x4C74298 + +#define mmPSOC_RESET_CONF_XBAR_SW_RST_CFG 0x4C7429C + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_PRSTN_RST_CFG 0x4C742A0 + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_SOFT_RST_CFG 0x4C742A4 + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_FW_RST_CFG 0x4C742A8 + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_WD_RST_CFG 0x4C742AC + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_MNL_RST_CFG 0x4C742B0 + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_FLR_RST_CFG 0x4C742B4 + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_ECC_DERR_RST_CFG 0x4C742B8 + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_SW_RST_CFG 0x4C742BC + +#define mmPSOC_RESET_CONF_DDMA_PRSTN_RST_CFG 0x4C742C0 + +#define mmPSOC_RESET_CONF_DDMA_SOFT_RST_CFG 0x4C742C4 + +#define mmPSOC_RESET_CONF_DDMA_FW_RST_CFG 0x4C742C8 + +#define mmPSOC_RESET_CONF_DDMA_WD_RST_CFG 0x4C742CC + +#define mmPSOC_RESET_CONF_DDMA_MNL_RST_CFG 0x4C742D0 + +#define mmPSOC_RESET_CONF_DDMA_FLR_RST_CFG 0x4C742D4 + +#define mmPSOC_RESET_CONF_DDMA_ECC_DERR_RST_CFG 0x4C742D8 + +#define mmPSOC_RESET_CONF_DDMA_SW_RST_CFG 0x4C742DC + +#define mmPSOC_RESET_CONF_KDMA_PRSTN_RST_CFG 0x4C742E0 + +#define mmPSOC_RESET_CONF_KDMA_SOFT_RST_CFG 0x4C742E4 + +#define mmPSOC_RESET_CONF_KDMA_FW_RST_CFG 0x4C742E8 + +#define mmPSOC_RESET_CONF_KDMA_WD_RST_CFG 0x4C742EC + +#define mmPSOC_RESET_CONF_KDMA_MNL_RST_CFG 0x4C742F0 + +#define mmPSOC_RESET_CONF_KDMA_FLR_RST_CFG 0x4C742F4 + +#define mmPSOC_RESET_CONF_KDMA_ECC_DERR_RST_CFG 0x4C742F8 + +#define mmPSOC_RESET_CONF_KDMA_SW_RST_CFG 0x4C742FC + +#define mmPSOC_RESET_CONF_PDMA_PRSTN_RST_CFG 0x4C74300 + +#define mmPSOC_RESET_CONF_PDMA_SOFT_RST_CFG 0x4C74304 + +#define mmPSOC_RESET_CONF_PDMA_FW_RST_CFG 0x4C74308 + +#define mmPSOC_RESET_CONF_PDMA_WD_RST_CFG 0x4C7430C + +#define mmPSOC_RESET_CONF_PDMA_MNL_RST_CFG 0x4C74310 + +#define mmPSOC_RESET_CONF_PDMA_FLR_RST_CFG 0x4C74314 + +#define mmPSOC_RESET_CONF_PDMA_ECC_DERR_RST_CFG 0x4C74318 + +#define mmPSOC_RESET_CONF_PDMA_SW_RST_CFG 0x4C7431C + +#define mmPSOC_RESET_CONF_ARC_SS_PRSTN_RST_CFG 0x4C74320 + +#define mmPSOC_RESET_CONF_ARC_SS_SOFT_RST_CFG 0x4C74324 + +#define mmPSOC_RESET_CONF_ARC_SS_FW_RST_CFG 0x4C74328 + +#define mmPSOC_RESET_CONF_ARC_SS_WD_RST_CFG 0x4C7432C + +#define mmPSOC_RESET_CONF_ARC_SS_MNL_RST_CFG 0x4C74330 + +#define mmPSOC_RESET_CONF_ARC_SS_FLR_RST_CFG 0x4C74334 + +#define mmPSOC_RESET_CONF_ARC_SS_ECC_DERR_RST_CFG 0x4C74338 + +#define mmPSOC_RESET_CONF_ARC_SS_SW_RST_CFG 0x4C7433C + +#define mmPSOC_RESET_CONF_ROTATOR_PRSTN_RST_CFG 0x4C74340 + +#define mmPSOC_RESET_CONF_ROTATOR_SOFT_RST_CFG 0x4C74344 + +#define mmPSOC_RESET_CONF_ROTATOR_FW_RST_CFG 0x4C74348 + +#define mmPSOC_RESET_CONF_ROTATOR_WD_RST_CFG 0x4C7434C + +#define mmPSOC_RESET_CONF_ROTATOR_MNL_RST_CFG 0x4C74350 + +#define mmPSOC_RESET_CONF_ROTATOR_FLR_RST_CFG 0x4C74354 + +#define mmPSOC_RESET_CONF_ROTATOR_ECC_DERR_RST_CFG 0x4C74358 + +#define mmPSOC_RESET_CONF_ROTATOR_SW_RST_CFG 0x4C7435C + +#define mmPSOC_RESET_CONF_SM_PRSTN_RST_CFG 0x4C74360 + +#define mmPSOC_RESET_CONF_SM_SOFT_RST_CFG 0x4C74364 + +#define mmPSOC_RESET_CONF_SM_FW_RST_CFG 0x4C74368 + +#define mmPSOC_RESET_CONF_SM_WD_RST_CFG 0x4C7436C + +#define mmPSOC_RESET_CONF_SM_MNL_RST_CFG 0x4C74370 + +#define mmPSOC_RESET_CONF_SM_FLR_RST_CFG 0x4C74374 + +#define mmPSOC_RESET_CONF_SM_ECC_DERR_RST_CFG 0x4C74378 + +#define mmPSOC_RESET_CONF_SM_SW_RST_CFG 0x4C7437C + +#define mmPSOC_RESET_CONF_VIDEO_DEC_PRSTN_RST_CFG 0x4C74380 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_SOFT_RST_CFG 0x4C74384 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_FW_RST_CFG 0x4C74388 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_WD_RST_CFG 0x4C7438C + +#define mmPSOC_RESET_CONF_VIDEO_DEC_MNL_RST_CFG 0x4C74390 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_FLR_RST_CFG 0x4C74394 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_ECC_DERR_RST_CFG 0x4C74398 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_SW_RST_CFG 0x4C7439C + +#define mmPSOC_RESET_CONF_HBM_MC_PRSTN_RST_CFG 0x4C743A0 + +#define mmPSOC_RESET_CONF_HBM_MC_SOFT_RST_CFG 0x4C743A4 + +#define mmPSOC_RESET_CONF_HBM_MC_FW_RST_CFG 0x4C743A8 + +#define mmPSOC_RESET_CONF_HBM_MC_WD_RST_CFG 0x4C743AC + +#define mmPSOC_RESET_CONF_HBM_MC_MNL_RST_CFG 0x4C743B0 + +#define mmPSOC_RESET_CONF_HBM_MC_FLR_RST_CFG 0x4C743B4 + +#define mmPSOC_RESET_CONF_HBM_MC_ECC_DERR_RST_CFG 0x4C743B8 + +#define mmPSOC_RESET_CONF_HBM_MC_SW_RST_CFG 0x4C743BC + +#define mmPSOC_RESET_CONF_NIC_PRSTN_RST_CFG 0x4C743C0 + +#define mmPSOC_RESET_CONF_NIC_SOFT_RST_CFG 0x4C743C4 + +#define mmPSOC_RESET_CONF_NIC_FW_RST_CFG 0x4C743C8 + +#define mmPSOC_RESET_CONF_NIC_WD_RST_CFG 0x4C743CC + +#define mmPSOC_RESET_CONF_NIC_MNL_RST_CFG 0x4C743D0 + +#define mmPSOC_RESET_CONF_NIC_FLR_RST_CFG 0x4C743D4 + +#define mmPSOC_RESET_CONF_NIC_ECC_DERR_RST_CFG 0x4C743D8 + +#define mmPSOC_RESET_CONF_NIC_SW_RST_CFG 0x4C743DC + +#define mmPSOC_RESET_CONF_NIC_PRT_PRSTN_RST_CFG 0x4C743E0 + +#define mmPSOC_RESET_CONF_NIC_PRT_SOFT_RST_CFG 0x4C743E4 + +#define mmPSOC_RESET_CONF_NIC_PRT_FW_RST_CFG 0x4C743E8 + +#define mmPSOC_RESET_CONF_NIC_PRT_WD_RST_CFG 0x4C743EC + +#define mmPSOC_RESET_CONF_NIC_PRT_MNL_RST_CFG 0x4C743F0 + +#define mmPSOC_RESET_CONF_NIC_PRT_FLR_RST_CFG 0x4C743F4 + +#define mmPSOC_RESET_CONF_NIC_PRT_ECC_DERR_RST_CFG 0x4C743F8 + +#define mmPSOC_RESET_CONF_NIC_PRT_SW_RST_CFG 0x4C743FC + +#define mmPSOC_RESET_CONF_NIC_CH_PRSTN_RST_CFG 0x4C74400 + +#define mmPSOC_RESET_CONF_NIC_CH_SOFT_RST_CFG 0x4C74404 + +#define mmPSOC_RESET_CONF_NIC_CH_FW_RST_CFG 0x4C74408 + +#define mmPSOC_RESET_CONF_NIC_CH_WD_RST_CFG 0x4C7440C + +#define mmPSOC_RESET_CONF_NIC_CH_MNL_RST_CFG 0x4C74410 + +#define mmPSOC_RESET_CONF_NIC_CH_FLR_RST_CFG 0x4C74414 + +#define mmPSOC_RESET_CONF_NIC_CH_ECC_DERR_RST_CFG 0x4C74418 + +#define mmPSOC_RESET_CONF_NIC_CH_SW_RST_CFG 0x4C7441C + +#define mmPSOC_RESET_CONF_SOFT_RST 0x4C74800 + +#define mmPSOC_RESET_CONF_SW_ALL_RST 0x4C74804 + +#define mmPSOC_RESET_CONF_UNIT_RST_N 0x4C74808 + +#define mmPSOC_RESET_CONF_PSOC_UNIT_RST 0x4C7480C + +#define mmPSOC_RESET_CONF_CPU_UNIT_RST 0x4C74810 + +#define mmPSOC_RESET_CONF_ARC_UNIT_RST 0x4C74814 + +#define mmPSOC_RESET_CONF_SIF_UNIT_RST 0x4C74818 + +#define mmPSOC_RESET_CONF_SRAM_UNIT_RST 0x4C7481C + +#define mmPSOC_RESET_CONF_PCIE_CTRL_UNIT_RST 0x4C74820 + +#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_UNIT_RST 0x4C74824 + +#define mmPSOC_RESET_CONF_PCIE_IF_UNIT_RST 0x4C74828 + +#define mmPSOC_RESET_CONF_TPC_DIV_UNIT_RST 0x4C7482C + +#define mmPSOC_RESET_CONF_HBM_DIV_UNIT_RST 0x4C74830 + +#define mmPSOC_RESET_CONF_PMMU_UNIT_RST 0x4C74834 + +#define mmPSOC_RESET_CONF_PM_UNIT_RST 0x4C74838 + +#define mmPSOC_RESET_CONF_TS_UNIT_RST 0x4C7483C + +#define mmPSOC_RESET_CONF_TS_IF_UNIT_RST 0x4C74840 + +#define mmPSOC_RESET_CONF_PLL_L_UNIT_RST 0x4C74844 + +#define mmPSOC_RESET_CONF_PLL_H_UNIT_RST 0x4C74848 + +#define mmPSOC_RESET_CONF_MME_EUS_UNIT_RST 0x4C7484C + +#define mmPSOC_RESET_CONF_MSS_CLS_UNIT_RST 0x4C74850 + +#define mmPSOC_RESET_CONF_TPC_UNIT_RST 0x4C74854 + +#define mmPSOC_RESET_CONF_HIF_HMMU_UNIT_RST 0x4C74858 + +#define mmPSOC_RESET_CONF_XBAR_UNIT_RST 0x4C7485C + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_UNIT_RST 0x4C74860 + +#define mmPSOC_RESET_CONF_DDMA_UNIT_RST 0x4C74864 + +#define mmPSOC_RESET_CONF_KDMA_UNIT_RST 0x4C74868 + +#define mmPSOC_RESET_CONF_PDMA_UNIT_RST 0x4C7486C + +#define mmPSOC_RESET_CONF_ARC_SS_UNIT_RST 0x4C74870 + +#define mmPSOC_RESET_CONF_ROTATOR_UNIT_RST 0x4C74874 + +#define mmPSOC_RESET_CONF_SM_UNIT_RST 0x4C74878 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_UNIT_RST 0x4C7487C + +#define mmPSOC_RESET_CONF_HBM_MC_UNIT_RST 0x4C74880 + +#define mmPSOC_RESET_CONF_NIC_UNIT_RST 0x4C74884 + +#define mmPSOC_RESET_CONF_NIC_PRT_UNIT_RST 0x4C74888 + +#define mmPSOC_RESET_CONF_NIC_CH_UNIT_RST 0x4C7488C + +#define mmPSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL 0x4C74B00 + +#define mmPSOC_RESET_CONF_CPU_0_CLK_RST_CTRL 0x4C74B04 + +#define mmPSOC_RESET_CONF_ARC_0_CLK_RST_CTRL 0x4C74B08 + +#define mmPSOC_RESET_CONF_ARC_1_CLK_RST_CTRL 0x4C74B0C + +#define mmPSOC_RESET_CONF_SIF_0_CLK_RST_CTRL 0x4C74B10 + +#define mmPSOC_RESET_CONF_SIF_1_CLK_RST_CTRL 0x4C74B14 + +#define mmPSOC_RESET_CONF_SIF_2_CLK_RST_CTRL 0x4C74B18 + +#define mmPSOC_RESET_CONF_SIF_3_CLK_RST_CTRL 0x4C74B1C + +#define mmPSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL 0x4C74B20 + +#define mmPSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL 0x4C74B24 + +#define mmPSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL 0x4C74B28 + +#define mmPSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL 0x4C74B2C + +#define mmPSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL 0x4C74B30 + +#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL 0x4C74B34 + +#define mmPSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL 0x4C74B38 + +#define mmPSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL 0x4C74B3C + +#define mmPSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL 0x4C74B40 + +#define mmPSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL 0x4C74B44 + +#define mmPSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL 0x4C74B48 + +#define mmPSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL 0x4C74B4C + +#define mmPSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL 0x4C74B50 + +#define mmPSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL 0x4C74B54 + +#define mmPSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL 0x4C74B58 + +#define mmPSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL 0x4C74B5C + +#define mmPSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL 0x4C74B60 + +#define mmPSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL 0x4C74B64 + +#define mmPSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL 0x4C74B68 + +#define mmPSOC_RESET_CONF_PM_0_CLK_RST_CTRL 0x4C74B6C + +#define mmPSOC_RESET_CONF_PM_1_CLK_RST_CTRL 0x4C74B70 + +#define mmPSOC_RESET_CONF_PM_2_CLK_RST_CTRL 0x4C74B74 + +#define mmPSOC_RESET_CONF_PM_3_CLK_RST_CTRL 0x4C74B78 + +#define mmPSOC_RESET_CONF_TS_0_CLK_RST_CTRL 0x4C74B7C + +#define mmPSOC_RESET_CONF_TS_1_CLK_RST_CTRL 0x4C74B80 + +#define mmPSOC_RESET_CONF_TS_2_CLK_RST_CTRL 0x4C74B84 + +#define mmPSOC_RESET_CONF_TS_3_CLK_RST_CTRL 0x4C74B88 + +#define mmPSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL 0x4C74B8C + +#define mmPSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL 0x4C74B90 + +#define mmPSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL 0x4C74B94 + +#define mmPSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL 0x4C74B98 + +#define mmPSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL 0x4C74B9C + +#define mmPSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL 0x4C74BA0 + +#define mmPSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL 0x4C74BA4 + +#define mmPSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL 0x4C74BA8 + +#define mmPSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL 0x4C74BAC + +#define mmPSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL 0x4C74BB0 + +#define mmPSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL 0x4C74BB4 + +#define mmPSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL 0x4C74BB8 + +#define mmPSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL 0x4C74BBC + +#define mmPSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL 0x4C74BC0 + +#define mmPSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL 0x4C74BC4 + +#define mmPSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL 0x4C74BC8 + +#define mmPSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL 0x4C74BCC + +#define mmPSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL 0x4C74BD0 + +#define mmPSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL 0x4C74BD4 + +#define mmPSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL 0x4C74BD8 + +#define mmPSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL 0x4C74BDC + +#define mmPSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL 0x4C74BE0 + +#define mmPSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL 0x4C74BE4 + +#define mmPSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL 0x4C74BE8 + +#define mmPSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL 0x4C74BEC + +#define mmPSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL 0x4C74BF0 + +#define mmPSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL 0x4C74BF4 + +#define mmPSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL 0x4C74BF8 + +#define mmPSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL 0x4C74BFC + +#define mmPSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL 0x4C74C00 + +#define mmPSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL 0x4C74C04 + +#define mmPSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL 0x4C74C08 + +#define mmPSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL 0x4C74C0C + +#define mmPSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL 0x4C74C10 + +#define mmPSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL 0x4C74C14 + +#define mmPSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL 0x4C74C18 + +#define mmPSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL 0x4C74C1C + +#define mmPSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL 0x4C74C20 + +#define mmPSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL 0x4C74C24 + +#define mmPSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL 0x4C74C28 + +#define mmPSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL 0x4C74C2C + +#define mmPSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL 0x4C74C30 + +#define mmPSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL 0x4C74C34 + +#define mmPSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL 0x4C74C38 + +#define mmPSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL 0x4C74C3C + +#define mmPSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL 0x4C74C40 + +#define mmPSOC_RESET_CONF_TPC_0_CLK_RST_CTRL 0x4C74C44 + +#define mmPSOC_RESET_CONF_TPC_1_CLK_RST_CTRL 0x4C74C48 + +#define mmPSOC_RESET_CONF_TPC_2_CLK_RST_CTRL 0x4C74C4C + +#define mmPSOC_RESET_CONF_TPC_3_CLK_RST_CTRL 0x4C74C50 + +#define mmPSOC_RESET_CONF_TPC_4_CLK_RST_CTRL 0x4C74C54 + +#define mmPSOC_RESET_CONF_TPC_5_CLK_RST_CTRL 0x4C74C58 + +#define mmPSOC_RESET_CONF_TPC_6_CLK_RST_CTRL 0x4C74C5C + +#define mmPSOC_RESET_CONF_TPC_7_CLK_RST_CTRL 0x4C74C60 + +#define mmPSOC_RESET_CONF_TPC_8_CLK_RST_CTRL 0x4C74C64 + +#define mmPSOC_RESET_CONF_TPC_9_CLK_RST_CTRL 0x4C74C68 + +#define mmPSOC_RESET_CONF_TPC_10_CLK_RST_CTRL 0x4C74C6C + +#define mmPSOC_RESET_CONF_TPC_11_CLK_RST_CTRL 0x4C74C70 + +#define mmPSOC_RESET_CONF_TPC_12_CLK_RST_CTRL 0x4C74C74 + +#define mmPSOC_RESET_CONF_TPC_13_CLK_RST_CTRL 0x4C74C78 + +#define mmPSOC_RESET_CONF_TPC_14_CLK_RST_CTRL 0x4C74C7C + +#define mmPSOC_RESET_CONF_TPC_15_CLK_RST_CTRL 0x4C74C80 + +#define mmPSOC_RESET_CONF_TPC_16_CLK_RST_CTRL 0x4C74C84 + +#define mmPSOC_RESET_CONF_TPC_17_CLK_RST_CTRL 0x4C74C88 + +#define mmPSOC_RESET_CONF_TPC_18_CLK_RST_CTRL 0x4C74C8C + +#define mmPSOC_RESET_CONF_TPC_19_CLK_RST_CTRL 0x4C74C90 + +#define mmPSOC_RESET_CONF_TPC_20_CLK_RST_CTRL 0x4C74C94 + +#define mmPSOC_RESET_CONF_TPC_21_CLK_RST_CTRL 0x4C74C98 + +#define mmPSOC_RESET_CONF_TPC_22_CLK_RST_CTRL 0x4C74C9C + +#define mmPSOC_RESET_CONF_TPC_23_CLK_RST_CTRL 0x4C74CA0 + +#define mmPSOC_RESET_CONF_TPC_24_CLK_RST_CTRL 0x4C74CA4 + +#define mmPSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL 0x4C74CA8 + +#define mmPSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL 0x4C74CAC + +#define mmPSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL 0x4C74CB0 + +#define mmPSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL 0x4C74CB4 + +#define mmPSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL 0x4C74CB8 + +#define mmPSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL 0x4C74CBC + +#define mmPSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL 0x4C74CC0 + +#define mmPSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL 0x4C74CC4 + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL 0x4C74CC8 + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL 0x4C74CCC + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL 0x4C74CD0 + +#define mmPSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL 0x4C74CD4 + +#define mmPSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL 0x4C74CD8 + +#define mmPSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL 0x4C74CDC + +#define mmPSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL 0x4C74CE0 + +#define mmPSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL 0x4C74CE4 + +#define mmPSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL 0x4C74CE8 + +#define mmPSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL 0x4C74CEC + +#define mmPSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL 0x4C74CF0 + +#define mmPSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL 0x4C74CF4 + +#define mmPSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL 0x4C74CF8 + +#define mmPSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL 0x4C74CFC + +#define mmPSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL 0x4C74D00 + +#define mmPSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL 0x4C74D04 + +#define mmPSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL 0x4C74D08 + +#define mmPSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL 0x4C74D0C + +#define mmPSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL 0x4C74D10 + +#define mmPSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL 0x4C74D14 + +#define mmPSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL 0x4C74D18 + +#define mmPSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL 0x4C74D1C + +#define mmPSOC_RESET_CONF_SM_0_CLK_RST_CTRL 0x4C74D20 + +#define mmPSOC_RESET_CONF_SM_1_CLK_RST_CTRL 0x4C74D24 + +#define mmPSOC_RESET_CONF_SM_2_CLK_RST_CTRL 0x4C74D28 + +#define mmPSOC_RESET_CONF_SM_3_CLK_RST_CTRL 0x4C74D2C + +#define mmPSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL 0x4C74D30 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL 0x4C74D34 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL 0x4C74D38 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL 0x4C74D3C + +#define mmPSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL 0x4C74D40 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL 0x4C74D44 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL 0x4C74D48 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL 0x4C74D4C + +#define mmPSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL 0x4C74D50 + +#define mmPSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL 0x4C74D54 + +#define mmPSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL 0x4C74D58 + +#define mmPSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL 0x4C74D5C + +#define mmPSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL 0x4C74D60 + +#define mmPSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL 0x4C74D64 + +#define mmPSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL 0x4C74D68 + +#define mmPSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL 0x4C74D6C + +#define mmPSOC_RESET_CONF_NIC_0_CLK_RST_CTRL 0x4C74D70 + +#define mmPSOC_RESET_CONF_NIC_1_CLK_RST_CTRL 0x4C74D74 + +#define mmPSOC_RESET_CONF_NIC_2_CLK_RST_CTRL 0x4C74D78 + +#define mmPSOC_RESET_CONF_NIC_3_CLK_RST_CTRL 0x4C74D7C + +#define mmPSOC_RESET_CONF_NIC_4_CLK_RST_CTRL 0x4C74D80 + +#define mmPSOC_RESET_CONF_NIC_5_CLK_RST_CTRL 0x4C74D84 + +#define mmPSOC_RESET_CONF_NIC_6_CLK_RST_CTRL 0x4C74D88 + +#define mmPSOC_RESET_CONF_NIC_7_CLK_RST_CTRL 0x4C74D8C + +#define mmPSOC_RESET_CONF_NIC_8_CLK_RST_CTRL 0x4C74D90 + +#define mmPSOC_RESET_CONF_NIC_9_CLK_RST_CTRL 0x4C74D94 + +#define mmPSOC_RESET_CONF_NIC_10_CLK_RST_CTRL 0x4C74D98 + +#define mmPSOC_RESET_CONF_NIC_11_CLK_RST_CTRL 0x4C74D9C + +#define mmPSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL 0x4C74DA0 + +#define mmPSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL 0x4C74DA4 + +#define mmPSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL 0x4C74DA8 + +#define mmPSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL 0x4C74DAC + +#define mmPSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL 0x4C74DB0 + +#define mmPSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL 0x4C74DB4 + +#define mmPSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL 0x4C74DB8 + +#define mmPSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL 0x4C74DBC + +#define mmPSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL 0x4C74DC0 + +#define mmPSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL 0x4C74DC4 + +#define mmPSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL 0x4C74DC8 + +#define mmPSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL 0x4C74DCC + +#define mmPSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL 0x4C74DD0 + +#define mmPSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL 0x4C74DD4 + +#define mmPSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL 0x4C74DD8 + +#endif /* ASIC_REG_PSOC_RESET_CONF_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_timestamp_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_timestamp_regs.h new file mode 100644 index 000000000000..699becc28887 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/psoc_timestamp_regs.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_TIMESTAMP_REGS_H_ +#define ASIC_REG_PSOC_TIMESTAMP_REGS_H_ + +/* + ***************************************** + * PSOC_TIMESTAMP + * (Prototype: TIMESTAMP) + ***************************************** + */ + +#define mmPSOC_TIMESTAMP_CNTCR 0x4C49000 + +#define mmPSOC_TIMESTAMP_CNTSR 0x4C49004 + +#define mmPSOC_TIMESTAMP_CNTCVL 0x4C49008 + +#define mmPSOC_TIMESTAMP_CNTCVU 0x4C4900C + +#define mmPSOC_TIMESTAMP_CNTFID0 0x4C49020 + +#define mmPSOC_TIMESTAMP_PIDR4 0x4C49FD0 + +#define mmPSOC_TIMESTAMP_PIDR5 0x4C49FD4 + +#define mmPSOC_TIMESTAMP_PIDR6 0x4C49FD8 + +#define mmPSOC_TIMESTAMP_PIDR7 0x4C49FDC + +#define mmPSOC_TIMESTAMP_PIDR0 0x4C49FE0 + +#define mmPSOC_TIMESTAMP_PIDR1 0x4C49FE4 + +#define mmPSOC_TIMESTAMP_PIDR2 0x4C49FE8 + +#define mmPSOC_TIMESTAMP_PIDR3 0x4C49FEC + +#define mmPSOC_TIMESTAMP_CIDR0 0x4C49FF0 + +#define mmPSOC_TIMESTAMP_CIDR1 0x4C49FF4 + +#define mmPSOC_TIMESTAMP_CIDR2 0x4C49FF8 + +#define mmPSOC_TIMESTAMP_CIDR3 0x4C49FFC + +#endif /* ASIC_REG_PSOC_TIMESTAMP_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_desc_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_desc_regs.h new file mode 100644 index 000000000000..79320320ebcb --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_desc_regs.h @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ROT0_DESC_REGS_H_ +#define ASIC_REG_ROT0_DESC_REGS_H_ + +/* + ***************************************** + * ROT0_DESC + * (Prototype: ROT_DESC) + ***************************************** + */ + +#define mmROT0_DESC_CONTEXT_ID 0x4E0B100 + +#define mmROT0_DESC_IN_IMG_START_ADDR_L 0x4E0B104 + +#define mmROT0_DESC_IN_IMG_START_ADDR_H 0x4E0B108 + +#define mmROT0_DESC_OUT_IMG_START_ADDR_L 0x4E0B10C + +#define mmROT0_DESC_OUT_IMG_START_ADDR_H 0x4E0B110 + +#define mmROT0_DESC_CFG 0x4E0B114 + +#define mmROT0_DESC_IM_READ_SLOPE 0x4E0B118 + +#define mmROT0_DESC_SIN_D 0x4E0B11C + +#define mmROT0_DESC_COS_D 0x4E0B120 + +#define mmROT0_DESC_IN_IMG 0x4E0B124 + +#define mmROT0_DESC_IN_STRIDE 0x4E0B128 + +#define mmROT0_DESC_IN_STRIPE 0x4E0B12C + +#define mmROT0_DESC_IN_CENTER 0x4E0B130 + +#define mmROT0_DESC_OUT_IMG 0x4E0B134 + +#define mmROT0_DESC_OUT_STRIDE 0x4E0B138 + +#define mmROT0_DESC_OUT_STRIPE 0x4E0B13C + +#define mmROT0_DESC_OUT_CENTER 0x4E0B140 + +#define mmROT0_DESC_BACKGROUND 0x4E0B144 + +#define mmROT0_DESC_CPL_MSG_EN 0x4E0B148 + +#define mmROT0_DESC_IDLE_STATE 0x4E0B14C + +#define mmROT0_DESC_CPL_MSG_ADDR 0x4E0B150 + +#define mmROT0_DESC_CPL_MSG_DATA 0x4E0B154 + +#define mmROT0_DESC_CPL_MSG_AWUSER 0x4E0B158 + +#define mmROT0_DESC_X_I_START_OFFSET 0x4E0B15C + +#define mmROT0_DESC_X_I_START_OFFSET_FLIP 0x4E0B160 + +#define mmROT0_DESC_X_I_FIRST 0x4E0B164 + +#define mmROT0_DESC_Y_I_FIRST 0x4E0B168 + +#define mmROT0_DESC_Y_I 0x4E0B16C + +#define mmROT0_DESC_OUT_STRIPE_SIZE 0x4E0B170 + +#define mmROT0_DESC_RSB_CFG_0 0x4E0B174 + +#define mmROT0_DESC_RSB_PAD_VAL 0x4E0B178 + +#define mmROT0_DESC_HBW_ARUSER_HI 0x4E0B17C + +#define mmROT0_DESC_HBW_ARUSER_LO 0x4E0B180 + +#define mmROT0_DESC_HBW_AWUSER_HI 0x4E0B184 + +#define mmROT0_DESC_HBW_AWUSER_LO 0x4E0B188 + +#define mmROT0_DESC_OWM_CFG 0x4E0B18C + +#define mmROT0_DESC_CTRL_CFG 0x4E0B190 + +#define mmROT0_DESC_PIXEL_PAD 0x4E0B194 + +#define mmROT0_DESC_PREC_SHIFT 0x4E0B198 + +#define mmROT0_DESC_MAX_VAL 0x4E0B19C + +#define mmROT0_DESC_A0_M11 0x4E0B1A0 + +#define mmROT0_DESC_A1_M12 0x4E0B1A4 + +#define mmROT0_DESC_A2 0x4E0B1A8 + +#define mmROT0_DESC_B0_M21 0x4E0B1AC + +#define mmROT0_DESC_B1_M22 0x4E0B1B0 + +#define mmROT0_DESC_B2 0x4E0B1B4 + +#define mmROT0_DESC_C0 0x4E0B1B8 + +#define mmROT0_DESC_C1 0x4E0B1BC + +#define mmROT0_DESC_C2 0x4E0B1C0 + +#define mmROT0_DESC_D0 0x4E0B1C4 + +#define mmROT0_DESC_D1 0x4E0B1C8 + +#define mmROT0_DESC_D2 0x4E0B1CC + +#define mmROT0_DESC_INV_PROC_SIZE_M_1 0x4E0B1D0 + +#define mmROT0_DESC_MESH_IMG_START_ADDR_L 0x4E0B1D4 + +#define mmROT0_DESC_MESH_IMG_START_ADDR_H 0x4E0B1D8 + +#define mmROT0_DESC_MESH_IMG 0x4E0B1DC + +#define mmROT0_DESC_MESH_STRIDE 0x4E0B1E0 + +#define mmROT0_DESC_MESH_STRIPE 0x4E0B1E4 + +#define mmROT0_DESC_MESH_CTRL 0x4E0B1E8 + +#define mmROT0_DESC_MESH_GH 0x4E0B1EC + +#define mmROT0_DESC_MESH_GV 0x4E0B1F0 + +#define mmROT0_DESC_MRSB_CFG_0 0x4E0B1F4 + +#define mmROT0_DESC_MRSB_PAD_VAL 0x4E0B1F8 + +#define mmROT0_DESC_BUF_CFG 0x4E0B1FC + +#define mmROT0_DESC_CID_OFFSET 0x4E0B200 + +#define mmROT0_DESC_PUSH_DESC 0x4E0B204 + +#endif /* ASIC_REG_ROT0_DESC_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_masks.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_masks.h new file mode 100644 index 000000000000..f2e739ede3d9 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_masks.h @@ -0,0 +1,313 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ROT0_MASKS_H_ +#define ASIC_REG_ROT0_MASKS_H_ + +/* + ***************************************** + * ROT0 + * (Prototype: ROTATOR) + ***************************************** + */ + +/* ROT0_KMD_MODE */ +#define ROT0_KMD_MODE_EN_SHIFT 0 +#define ROT0_KMD_MODE_EN_MASK 0x1 + +/* ROT0_CPL_QUEUE_EN */ +#define ROT0_CPL_QUEUE_EN_Q_EN_SHIFT 0 +#define ROT0_CPL_QUEUE_EN_Q_EN_MASK 0x1 + +/* ROT0_CPL_QUEUE_ADDR_L */ +#define ROT0_CPL_QUEUE_ADDR_L_VAL_SHIFT 0 +#define ROT0_CPL_QUEUE_ADDR_L_VAL_MASK 0xFFFFFFFF + +/* ROT0_CPL_QUEUE_ADDR_H */ +#define ROT0_CPL_QUEUE_ADDR_H_VAL_SHIFT 0 +#define ROT0_CPL_QUEUE_ADDR_H_VAL_MASK 0xFFFFFFFF + +/* ROT0_CPL_QUEUE_DATA */ +#define ROT0_CPL_QUEUE_DATA_VAL_SHIFT 0 +#define ROT0_CPL_QUEUE_DATA_VAL_MASK 0xFFFFFFFF + +/* ROT0_CPL_QUEUE_AWUSER */ +#define ROT0_CPL_QUEUE_AWUSER_VAL_SHIFT 0 +#define ROT0_CPL_QUEUE_AWUSER_VAL_MASK 0xFFFFFFFF + +/* ROT0_CPL_QUEUE_AXI */ +#define ROT0_CPL_QUEUE_AXI_CACHE_SHIFT 0 +#define ROT0_CPL_QUEUE_AXI_CACHE_MASK 0xF +#define ROT0_CPL_QUEUE_AXI_PROT_SHIFT 4 +#define ROT0_CPL_QUEUE_AXI_PROT_MASK 0x70 + +/* ROT0_CPL_MSG_THRESHOLD */ +#define ROT0_CPL_MSG_THRESHOLD_VAL_SHIFT 0 +#define ROT0_CPL_MSG_THRESHOLD_VAL_MASK 0x3F + +/* ROT0_CPL_MSG_AXI */ +#define ROT0_CPL_MSG_AXI_CACHE_SHIFT 0 +#define ROT0_CPL_MSG_AXI_CACHE_MASK 0xF +#define ROT0_CPL_MSG_AXI_PROT_SHIFT 4 +#define ROT0_CPL_MSG_AXI_PROT_MASK 0x70 + +/* ROT0_AXI_WB */ +#define ROT0_AXI_WB_CACHE_SHIFT 0 +#define ROT0_AXI_WB_CACHE_MASK 0xF +#define ROT0_AXI_WB_PROT_SHIFT 4 +#define ROT0_AXI_WB_PROT_MASK 0x70 + +/* ROT0_ERR_CFG */ +#define ROT0_ERR_CFG_STOP_ON_ERR_SHIFT 0 +#define ROT0_ERR_CFG_STOP_ON_ERR_MASK 0x1 + +/* ROT0_ERR_STATUS */ +#define ROT0_ERR_STATUS_ROT_HBW_RD_SHIFT 0 +#define ROT0_ERR_STATUS_ROT_HBW_RD_MASK 0x1 +#define ROT0_ERR_STATUS_ROT_HBW_WR_SHIFT 1 +#define ROT0_ERR_STATUS_ROT_HBW_WR_MASK 0x2 +#define ROT0_ERR_STATUS_QMAN_HBW_RD_SHIFT 2 +#define ROT0_ERR_STATUS_QMAN_HBW_RD_MASK 0x4 +#define ROT0_ERR_STATUS_QMAN_HBW_WR_SHIFT 3 +#define ROT0_ERR_STATUS_QMAN_HBW_WR_MASK 0x8 +#define ROT0_ERR_STATUS_ROT_LBW_WR_SHIFT 4 +#define ROT0_ERR_STATUS_ROT_LBW_WR_MASK 0x10 + +/* ROT0_WBC_MAX_OUTSTANDING */ +#define ROT0_WBC_MAX_OUTSTANDING_VAL_SHIFT 0 +#define ROT0_WBC_MAX_OUTSTANDING_VAL_MASK 0xFFFF + +/* ROT0_WBC_RL */ +#define ROT0_WBC_RL_SATURATION_SHIFT 0 +#define ROT0_WBC_RL_SATURATION_MASK 0xFF +#define ROT0_WBC_RL_TIMEOUT_SHIFT 8 +#define ROT0_WBC_RL_TIMEOUT_MASK 0xFF00 +#define ROT0_WBC_RL_RST_TOKEN_SHIFT 16 +#define ROT0_WBC_RL_RST_TOKEN_MASK 0xFF0000 +#define ROT0_WBC_RL_RATE_LIMITER_EN_SHIFT 24 +#define ROT0_WBC_RL_RATE_LIMITER_EN_MASK 0x1000000 + +/* ROT0_WBC_INFLIGHTS */ +#define ROT0_WBC_INFLIGHTS_VAL_SHIFT 0 +#define ROT0_WBC_INFLIGHTS_VAL_MASK 0xFFFF + +/* ROT0_WBC_INFO */ +#define ROT0_WBC_INFO_EMPTY_SHIFT 0 +#define ROT0_WBC_INFO_EMPTY_MASK 0x1 +#define ROT0_WBC_INFO_AXI_IDLE_SHIFT 1 +#define ROT0_WBC_INFO_AXI_IDLE_MASK 0x2 + +/* ROT0_WBC_MON */ +#define ROT0_WBC_MON_CNT_SHIFT 0 +#define ROT0_WBC_MON_CNT_MASK 0x1 +#define ROT0_WBC_MON_TS_SHIFT 8 +#define ROT0_WBC_MON_TS_MASK 0x300 +#define ROT0_WBC_MON_CONTEXT_ID_SHIFT 16 +#define ROT0_WBC_MON_CONTEXT_ID_MASK 0xFFFF0000 + +/* ROT0_RSB_CAM_MAX_SIZE */ +#define ROT0_RSB_CAM_MAX_SIZE_DATA_SHIFT 0 +#define ROT0_RSB_CAM_MAX_SIZE_DATA_MASK 0xFFFF +#define ROT0_RSB_CAM_MAX_SIZE_MD_SHIFT 16 +#define ROT0_RSB_CAM_MAX_SIZE_MD_MASK 0xFFFF0000 + +/* ROT0_RSB_CFG */ +#define ROT0_RSB_CFG_CACHE_DISABLE_SHIFT 0 +#define ROT0_RSB_CFG_CACHE_DISABLE_MASK 0x1 +#define ROT0_RSB_CFG_ENABLE_CGATE_SHIFT 1 +#define ROT0_RSB_CFG_ENABLE_CGATE_MASK 0x2 + +/* ROT0_RSB_MAX_OS */ +#define ROT0_RSB_MAX_OS_VAL_SHIFT 0 +#define ROT0_RSB_MAX_OS_VAL_MASK 0xFFFF + +/* ROT0_RSB_RL */ +#define ROT0_RSB_RL_SATURATION_SHIFT 0 +#define ROT0_RSB_RL_SATURATION_MASK 0xFF +#define ROT0_RSB_RL_TIMEOUT_SHIFT 8 +#define ROT0_RSB_RL_TIMEOUT_MASK 0xFF00 +#define ROT0_RSB_RL_RST_TOKEN_SHIFT 16 +#define ROT0_RSB_RL_RST_TOKEN_MASK 0xFF0000 +#define ROT0_RSB_RL_RATE_LIMITER_EN_SHIFT 24 +#define ROT0_RSB_RL_RATE_LIMITER_EN_MASK 0x1000000 + +/* ROT0_RSB_INFLIGHTS */ +#define ROT0_RSB_INFLIGHTS_VAL_SHIFT 0 +#define ROT0_RSB_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* ROT0_RSB_OCCUPANCY */ +#define ROT0_RSB_OCCUPANCY_VAL_SHIFT 0 +#define ROT0_RSB_OCCUPANCY_VAL_MASK 0xFFFFFFFF + +/* ROT0_RSB_INFO */ +#define ROT0_RSB_INFO_EMPTY_SHIFT 0 +#define ROT0_RSB_INFO_EMPTY_MASK 0x1 +#define ROT0_RSB_INFO_AXI_IDLE_SHIFT 1 +#define ROT0_RSB_INFO_AXI_IDLE_MASK 0x2 + +/* ROT0_RSB_MON */ +#define ROT0_RSB_MON_CNT_SHIFT 0 +#define ROT0_RSB_MON_CNT_MASK 0x1FFF +#define ROT0_RSB_MON_TS_SHIFT 16 +#define ROT0_RSB_MON_TS_MASK 0x30000 + +/* ROT0_RSB_MON_CONTEXT_ID */ +#define ROT0_RSB_MON_CONTEXT_ID_VAL_SHIFT 0 +#define ROT0_RSB_MON_CONTEXT_ID_VAL_MASK 0xFFFFFFFF + +/* ROT0_MSS_HALT */ +#define ROT0_MSS_HALT_VAL_SHIFT 0 +#define ROT0_MSS_HALT_VAL_MASK 0x7 + +/* ROT0_MSS_SEI_STATUS */ +#define ROT0_MSS_SEI_STATUS_I0_SHIFT 0 +#define ROT0_MSS_SEI_STATUS_I0_MASK 0x1 +#define ROT0_MSS_SEI_STATUS_I1_SHIFT 1 +#define ROT0_MSS_SEI_STATUS_I1_MASK 0x2 +#define ROT0_MSS_SEI_STATUS_I2_SHIFT 2 +#define ROT0_MSS_SEI_STATUS_I2_MASK 0x4 +#define ROT0_MSS_SEI_STATUS_I3_SHIFT 3 +#define ROT0_MSS_SEI_STATUS_I3_MASK 0x8 +#define ROT0_MSS_SEI_STATUS_I4_SHIFT 4 +#define ROT0_MSS_SEI_STATUS_I4_MASK 0x10 +#define ROT0_MSS_SEI_STATUS_I5_SHIFT 5 +#define ROT0_MSS_SEI_STATUS_I5_MASK 0x20 +#define ROT0_MSS_SEI_STATUS_I6_SHIFT 6 +#define ROT0_MSS_SEI_STATUS_I6_MASK 0x40 +#define ROT0_MSS_SEI_STATUS_I7_SHIFT 7 +#define ROT0_MSS_SEI_STATUS_I7_MASK 0x80 +#define ROT0_MSS_SEI_STATUS_I8_SHIFT 8 +#define ROT0_MSS_SEI_STATUS_I8_MASK 0x100 +#define ROT0_MSS_SEI_STATUS_I9_SHIFT 9 +#define ROT0_MSS_SEI_STATUS_I9_MASK 0x200 +#define ROT0_MSS_SEI_STATUS_I10_SHIFT 10 +#define ROT0_MSS_SEI_STATUS_I10_MASK 0x400 +#define ROT0_MSS_SEI_STATUS_I11_SHIFT 11 +#define ROT0_MSS_SEI_STATUS_I11_MASK 0x800 +#define ROT0_MSS_SEI_STATUS_I12_SHIFT 12 +#define ROT0_MSS_SEI_STATUS_I12_MASK 0x1000 +#define ROT0_MSS_SEI_STATUS_I13_SHIFT 13 +#define ROT0_MSS_SEI_STATUS_I13_MASK 0x2000 +#define ROT0_MSS_SEI_STATUS_I14_SHIFT 14 +#define ROT0_MSS_SEI_STATUS_I14_MASK 0x4000 +#define ROT0_MSS_SEI_STATUS_I15_SHIFT 15 +#define ROT0_MSS_SEI_STATUS_I15_MASK 0x8000 +#define ROT0_MSS_SEI_STATUS_I16_SHIFT 16 +#define ROT0_MSS_SEI_STATUS_I16_MASK 0x10000 +#define ROT0_MSS_SEI_STATUS_I17_SHIFT 17 +#define ROT0_MSS_SEI_STATUS_I17_MASK 0x20000 +#define ROT0_MSS_SEI_STATUS_I18_SHIFT 18 +#define ROT0_MSS_SEI_STATUS_I18_MASK 0x40000 +#define ROT0_MSS_SEI_STATUS_I19_SHIFT 19 +#define ROT0_MSS_SEI_STATUS_I19_MASK 0x80000 +#define ROT0_MSS_SEI_STATUS_I20_SHIFT 20 +#define ROT0_MSS_SEI_STATUS_I20_MASK 0x100000 +#define ROT0_MSS_SEI_STATUS_I21_SHIFT 21 +#define ROT0_MSS_SEI_STATUS_I21_MASK 0x200000 + +/* ROT0_MSS_SEI_MASK */ +#define ROT0_MSS_SEI_MASK_VAL_SHIFT 0 +#define ROT0_MSS_SEI_MASK_VAL_MASK 0x3FFFFF + +/* ROT0_MSS_SPI_STATUS */ +#define ROT0_MSS_SPI_STATUS_I0_SHIFT 0 +#define ROT0_MSS_SPI_STATUS_I0_MASK 0x1 +#define ROT0_MSS_SPI_STATUS_I1_SHIFT 1 +#define ROT0_MSS_SPI_STATUS_I1_MASK 0x2 +#define ROT0_MSS_SPI_STATUS_I2_SHIFT 2 +#define ROT0_MSS_SPI_STATUS_I2_MASK 0x4 +#define ROT0_MSS_SPI_STATUS_I3_SHIFT 3 +#define ROT0_MSS_SPI_STATUS_I3_MASK 0x8 +#define ROT0_MSS_SPI_STATUS_I4_SHIFT 4 +#define ROT0_MSS_SPI_STATUS_I4_MASK 0x10 +#define ROT0_MSS_SPI_STATUS_I5_SHIFT 5 +#define ROT0_MSS_SPI_STATUS_I5_MASK 0x20 +#define ROT0_MSS_SPI_STATUS_I6_SHIFT 6 +#define ROT0_MSS_SPI_STATUS_I6_MASK 0x40 +#define ROT0_MSS_SPI_STATUS_I7_SHIFT 7 +#define ROT0_MSS_SPI_STATUS_I7_MASK 0x80 + +/* ROT0_MSS_SPI_MASK */ +#define ROT0_MSS_SPI_MASK_VAL_SHIFT 0 +#define ROT0_MSS_SPI_MASK_VAL_MASK 0xFF + +/* ROT0_DISABLE_PAD_CALC */ +#define ROT0_DISABLE_PAD_CALC_VAL_SHIFT 0 +#define ROT0_DISABLE_PAD_CALC_VAL_MASK 0x3 + +/* ROT0_QMAN_CFG */ +#define ROT0_QMAN_CFG_FORCE_STOP_SHIFT 0 +#define ROT0_QMAN_CFG_FORCE_STOP_MASK 0x1 + +/* ROT0_CLK_EN */ +#define ROT0_CLK_EN_LBW_CFG_DIS_SHIFT 0 +#define ROT0_CLK_EN_LBW_CFG_DIS_MASK 0x1 +#define ROT0_CLK_EN_DBG_CFG_DIS_SHIFT 4 +#define ROT0_CLK_EN_DBG_CFG_DIS_MASK 0x10 +#define ROT0_CLK_EN_SB_EMPTY_MASK_SHIFT 5 +#define ROT0_CLK_EN_SB_EMPTY_MASK_MASK 0x20 + +/* ROT0_MRSB_CAM_MAX_SIZE */ +#define ROT0_MRSB_CAM_MAX_SIZE_DATA_SHIFT 0 +#define ROT0_MRSB_CAM_MAX_SIZE_DATA_MASK 0xFFFF +#define ROT0_MRSB_CAM_MAX_SIZE_MD_SHIFT 16 +#define ROT0_MRSB_CAM_MAX_SIZE_MD_MASK 0xFFFF0000 + +/* ROT0_MRSB_CFG */ +#define ROT0_MRSB_CFG_CACHE_DISABLE_SHIFT 0 +#define ROT0_MRSB_CFG_CACHE_DISABLE_MASK 0x1 +#define ROT0_MRSB_CFG_ENABLE_CGATE_SHIFT 1 +#define ROT0_MRSB_CFG_ENABLE_CGATE_MASK 0x2 + +/* ROT0_MRSB_MAX_OS */ +#define ROT0_MRSB_MAX_OS_VAL_SHIFT 0 +#define ROT0_MRSB_MAX_OS_VAL_MASK 0xFFFF + +/* ROT0_MRSB_RL */ +#define ROT0_MRSB_RL_SATURATION_SHIFT 0 +#define ROT0_MRSB_RL_SATURATION_MASK 0xFF +#define ROT0_MRSB_RL_TIMEOUT_SHIFT 8 +#define ROT0_MRSB_RL_TIMEOUT_MASK 0xFF00 +#define ROT0_MRSB_RL_RST_TOKEN_SHIFT 16 +#define ROT0_MRSB_RL_RST_TOKEN_MASK 0xFF0000 +#define ROT0_MRSB_RL_RATE_LIMITER_EN_SHIFT 24 +#define ROT0_MRSB_RL_RATE_LIMITER_EN_MASK 0x1000000 + +/* ROT0_MRSB_INFLIGHTS */ +#define ROT0_MRSB_INFLIGHTS_VAL_SHIFT 0 +#define ROT0_MRSB_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* ROT0_MRSB_OCCUPANCY */ +#define ROT0_MRSB_OCCUPANCY_VAL_SHIFT 0 +#define ROT0_MRSB_OCCUPANCY_VAL_MASK 0xFFFFFFFF + +/* ROT0_MRSB_INFO */ +#define ROT0_MRSB_INFO_EMPTY_SHIFT 0 +#define ROT0_MRSB_INFO_EMPTY_MASK 0x1 +#define ROT0_MRSB_INFO_AXI_IDLE_SHIFT 1 +#define ROT0_MRSB_INFO_AXI_IDLE_MASK 0x2 + +/* ROT0_MRSB_MON */ +#define ROT0_MRSB_MON_CNT_SHIFT 0 +#define ROT0_MRSB_MON_CNT_MASK 0x1FFF +#define ROT0_MRSB_MON_TS_SHIFT 16 +#define ROT0_MRSB_MON_TS_MASK 0x30000 + +/* ROT0_MRSB_MON_CONTEXT_ID */ +#define ROT0_MRSB_MON_CONTEXT_ID_VAL_SHIFT 0 +#define ROT0_MRSB_MON_CONTEXT_ID_VAL_MASK 0xFFFFFFFF + +/* ROT0_MSS_STS */ +#define ROT0_MSS_STS_IS_HALT_SHIFT 0 +#define ROT0_MSS_STS_IS_HALT_MASK 0x1 + +#endif /* ASIC_REG_ROT0_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_arc_aux_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_arc_aux_regs.h new file mode 100644 index 000000000000..e83daa33d737 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_arc_aux_regs.h @@ -0,0 +1,591 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ROT0_QM_ARC_AUX_REGS_H_ +#define ASIC_REG_ROT0_QM_ARC_AUX_REGS_H_ + +/* + ***************************************** + * ROT0_QM_ARC_AUX + * (Prototype: QMAN_ARC_AUX) + ***************************************** + */ + +#define mmROT0_QM_ARC_AUX_RUN_HALT_REQ 0x4E08100 + +#define mmROT0_QM_ARC_AUX_RUN_HALT_ACK 0x4E08104 + +#define mmROT0_QM_ARC_AUX_RST_VEC_ADDR 0x4E08108 + +#define mmROT0_QM_ARC_AUX_DBG_MODE 0x4E0810C + +#define mmROT0_QM_ARC_AUX_CLUSTER_NUM 0x4E08110 + +#define mmROT0_QM_ARC_AUX_ARC_NUM 0x4E08114 + +#define mmROT0_QM_ARC_AUX_WAKE_UP_EVENT 0x4E08118 + +#define mmROT0_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x4E0811C + +#define mmROT0_QM_ARC_AUX_CTI_AP_STS 0x4E08120 + +#define mmROT0_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x4E08124 + +#define mmROT0_QM_ARC_AUX_ARC_RST 0x4E08128 + +#define mmROT0_QM_ARC_AUX_ARC_RST_REQ 0x4E0812C + +#define mmROT0_QM_ARC_AUX_SRAM_LSB_ADDR 0x4E08130 + +#define mmROT0_QM_ARC_AUX_SRAM_MSB_ADDR 0x4E08134 + +#define mmROT0_QM_ARC_AUX_PCIE_LSB_ADDR 0x4E08138 + +#define mmROT0_QM_ARC_AUX_PCIE_MSB_ADDR 0x4E0813C + +#define mmROT0_QM_ARC_AUX_CFG_LSB_ADDR 0x4E08140 + +#define mmROT0_QM_ARC_AUX_CFG_MSB_ADDR 0x4E08144 + +#define mmROT0_QM_ARC_AUX_HBM0_LSB_ADDR 0x4E08150 + +#define mmROT0_QM_ARC_AUX_HBM0_MSB_ADDR 0x4E08154 + +#define mmROT0_QM_ARC_AUX_HBM1_LSB_ADDR 0x4E08158 + +#define mmROT0_QM_ARC_AUX_HBM1_MSB_ADDR 0x4E0815C + +#define mmROT0_QM_ARC_AUX_HBM2_LSB_ADDR 0x4E08160 + +#define mmROT0_QM_ARC_AUX_HBM2_MSB_ADDR 0x4E08164 + +#define mmROT0_QM_ARC_AUX_HBM3_LSB_ADDR 0x4E08168 + +#define mmROT0_QM_ARC_AUX_HBM3_MSB_ADDR 0x4E0816C + +#define mmROT0_QM_ARC_AUX_HBM0_OFFSET 0x4E08170 + +#define mmROT0_QM_ARC_AUX_HBM1_OFFSET 0x4E08174 + +#define mmROT0_QM_ARC_AUX_HBM2_OFFSET 0x4E08178 + +#define mmROT0_QM_ARC_AUX_HBM3_OFFSET 0x4E0817C + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x4E08180 + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x4E08184 + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x4E08188 + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x4E0818C + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x4E08190 + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x4E08194 + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x4E08198 + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x4E0819C + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x4E081A0 + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x4E081A4 + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x4E081A8 + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x4E081AC + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x4E081B0 + +#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x4E081B4 + +#define mmROT0_QM_ARC_AUX_ARC_CBU_AWCACHE_OVR 0x4E081B8 + +#define mmROT0_QM_ARC_AUX_ARC_LBU_AWCACHE_OVR 0x4E081BC + +#define mmROT0_QM_ARC_AUX_CONTEXT_ID_0 0x4E081C0 + +#define mmROT0_QM_ARC_AUX_CONTEXT_ID_1 0x4E081C4 + +#define mmROT0_QM_ARC_AUX_CONTEXT_ID_2 0x4E081C8 + +#define mmROT0_QM_ARC_AUX_CONTEXT_ID_3 0x4E081CC + +#define mmROT0_QM_ARC_AUX_CONTEXT_ID_4 0x4E081D0 + +#define mmROT0_QM_ARC_AUX_CONTEXT_ID_5 0x4E081D4 + +#define mmROT0_QM_ARC_AUX_CONTEXT_ID_6 0x4E081D8 + +#define mmROT0_QM_ARC_AUX_CONTEXT_ID_7 0x4E081DC + +#define mmROT0_QM_ARC_AUX_CID_OFFSET_0 0x4E081E0 + +#define mmROT0_QM_ARC_AUX_CID_OFFSET_1 0x4E081E4 + +#define mmROT0_QM_ARC_AUX_CID_OFFSET_2 0x4E081E8 + +#define mmROT0_QM_ARC_AUX_CID_OFFSET_3 0x4E081EC + +#define mmROT0_QM_ARC_AUX_CID_OFFSET_4 0x4E081F0 + +#define mmROT0_QM_ARC_AUX_CID_OFFSET_5 0x4E081F4 + +#define mmROT0_QM_ARC_AUX_CID_OFFSET_6 0x4E081F8 + +#define mmROT0_QM_ARC_AUX_CID_OFFSET_7 0x4E081FC + +#define mmROT0_QM_ARC_AUX_SW_INTR_0 0x4E08200 + +#define mmROT0_QM_ARC_AUX_SW_INTR_1 0x4E08204 + +#define mmROT0_QM_ARC_AUX_SW_INTR_2 0x4E08208 + +#define mmROT0_QM_ARC_AUX_SW_INTR_3 0x4E0820C + +#define mmROT0_QM_ARC_AUX_SW_INTR_4 0x4E08210 + +#define mmROT0_QM_ARC_AUX_SW_INTR_5 0x4E08214 + +#define mmROT0_QM_ARC_AUX_SW_INTR_6 0x4E08218 + +#define mmROT0_QM_ARC_AUX_SW_INTR_7 0x4E0821C + +#define mmROT0_QM_ARC_AUX_SW_INTR_8 0x4E08220 + +#define mmROT0_QM_ARC_AUX_SW_INTR_9 0x4E08224 + +#define mmROT0_QM_ARC_AUX_SW_INTR_10 0x4E08228 + +#define mmROT0_QM_ARC_AUX_SW_INTR_11 0x4E0822C + +#define mmROT0_QM_ARC_AUX_SW_INTR_12 0x4E08230 + +#define mmROT0_QM_ARC_AUX_SW_INTR_13 0x4E08234 + +#define mmROT0_QM_ARC_AUX_SW_INTR_14 0x4E08238 + +#define mmROT0_QM_ARC_AUX_SW_INTR_15 0x4E0823C + +#define mmROT0_QM_ARC_AUX_IRQ_INTR_MASK_0 0x4E08280 + +#define mmROT0_QM_ARC_AUX_IRQ_INTR_MASK_1 0x4E08284 + +#define mmROT0_QM_ARC_AUX_ARC_SEI_INTR_STS 0x4E08290 + +#define mmROT0_QM_ARC_AUX_ARC_SEI_INTR_CLR 0x4E08294 + +#define mmROT0_QM_ARC_AUX_ARC_SEI_INTR_MASK 0x4E08298 + +#define mmROT0_QM_ARC_AUX_ARC_EXCPTN_CAUSE 0x4E0829C + +#define mmROT0_QM_ARC_AUX_SEI_INTR_HALT_EN 0x4E082A0 + +#define mmROT0_QM_ARC_AUX_ARC_SEI_INTR_HALT_MASK 0x4E082A4 + +#define mmROT0_QM_ARC_AUX_QMAN_SEI_INTR_HALT_MASK 0x4E082A8 + +#define mmROT0_QM_ARC_AUX_ARC_REI_INTR_STS 0x4E082B0 + +#define mmROT0_QM_ARC_AUX_ARC_REI_INTR_CLR 0x4E082B4 + +#define mmROT0_QM_ARC_AUX_ARC_REI_INTR_MASK 0x4E082B8 + +#define mmROT0_QM_ARC_AUX_DCCM_ECC_ERR_ADDR 0x4E082BC + +#define mmROT0_QM_ARC_AUX_DCCM_ECC_SYNDROME 0x4E082C0 + +#define mmROT0_QM_ARC_AUX_I_CACHE_ECC_ERR_ADDR 0x4E082C4 + +#define mmROT0_QM_ARC_AUX_I_CACHE_ECC_SYNDROME 0x4E082C8 + +#define mmROT0_QM_ARC_AUX_D_CACHE_ECC_ERR_ADDR 0x4E082CC + +#define mmROT0_QM_ARC_AUX_D_CACHE_ECC_SYNDROME 0x4E082D0 + +#define mmROT0_QM_ARC_AUX_LBW_TRMINATE_AWADDR_ERR 0x4E082E0 + +#define mmROT0_QM_ARC_AUX_LBW_TRMINATE_ARADDR_ERR 0x4E082E4 + +#define mmROT0_QM_ARC_AUX_CFG_LBW_TERMINATE_BRESP 0x4E082E8 + +#define mmROT0_QM_ARC_AUX_CFG_LBW_TERMINATE_RRESP 0x4E082EC + +#define mmROT0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXLEN 0x4E082F0 + +#define mmROT0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXSIZE 0x4E082F4 + +#define mmROT0_QM_ARC_AUX_SCRATCHPAD_0 0x4E08300 + +#define mmROT0_QM_ARC_AUX_SCRATCHPAD_1 0x4E08304 + +#define mmROT0_QM_ARC_AUX_SCRATCHPAD_2 0x4E08308 + +#define mmROT0_QM_ARC_AUX_SCRATCHPAD_3 0x4E0830C + +#define mmROT0_QM_ARC_AUX_SCRATCHPAD_4 0x4E08310 + +#define mmROT0_QM_ARC_AUX_SCRATCHPAD_5 0x4E08314 + +#define mmROT0_QM_ARC_AUX_SCRATCHPAD_6 0x4E08318 + +#define mmROT0_QM_ARC_AUX_SCRATCHPAD_7 0x4E0831C + +#define mmROT0_QM_ARC_AUX_TOTAL_CBU_WR_CNT 0x4E08320 + +#define mmROT0_QM_ARC_AUX_INFLIGHT_CBU_WR_CNT 0x4E08324 + +#define mmROT0_QM_ARC_AUX_TOTAL_CBU_RD_CNT 0x4E08328 + +#define mmROT0_QM_ARC_AUX_INFLIGHT_CBU_RD_CNT 0x4E0832C + +#define mmROT0_QM_ARC_AUX_TOTAL_LBU_WR_CNT 0x4E08330 + +#define mmROT0_QM_ARC_AUX_INFLIGHT_LBU_WR_CNT 0x4E08334 + +#define mmROT0_QM_ARC_AUX_TOTAL_LBU_RD_CNT 0x4E08338 + +#define mmROT0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT 0x4E0833C + +#define mmROT0_QM_ARC_AUX_CBU_ARUSER_OVR 0x4E08350 + +#define mmROT0_QM_ARC_AUX_CBU_ARUSER_OVR_EN 0x4E08354 + +#define mmROT0_QM_ARC_AUX_CBU_AWUSER_OVR 0x4E08358 + +#define mmROT0_QM_ARC_AUX_CBU_AWUSER_OVR_EN 0x4E0835C + +#define mmROT0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR 0x4E08360 + +#define mmROT0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR_EN 0x4E08364 + +#define mmROT0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR 0x4E08368 + +#define mmROT0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR_EN 0x4E0836C + +#define mmROT0_QM_ARC_AUX_CBU_AXCACHE_OVR 0x4E08370 + +#define mmROT0_QM_ARC_AUX_CBU_LOCK_OVR 0x4E08374 + +#define mmROT0_QM_ARC_AUX_CBU_PROT_OVR 0x4E08378 + +#define mmROT0_QM_ARC_AUX_CBU_MAX_OUTSTANDING 0x4E0837C + +#define mmROT0_QM_ARC_AUX_CBU_EARLY_BRESP_EN 0x4E08380 + +#define mmROT0_QM_ARC_AUX_CBU_FORCE_RSP_OK 0x4E08384 + +#define mmROT0_QM_ARC_AUX_CBU_NO_WR_INFLIGHT 0x4E0838C + +#define mmROT0_QM_ARC_AUX_CBU_SEI_INTR_ID 0x4E08390 + +#define mmROT0_QM_ARC_AUX_LBU_ARUSER_OVR 0x4E08400 + +#define mmROT0_QM_ARC_AUX_LBU_ARUSER_OVR_EN 0x4E08404 + +#define mmROT0_QM_ARC_AUX_LBU_AWUSER_OVR 0x4E08408 + +#define mmROT0_QM_ARC_AUX_LBU_AWUSER_OVR_EN 0x4E0840C + +#define mmROT0_QM_ARC_AUX_LBU_AXCACHE_OVR 0x4E08420 + +#define mmROT0_QM_ARC_AUX_LBU_LOCK_OVR 0x4E08424 + +#define mmROT0_QM_ARC_AUX_LBU_PROT_OVR 0x4E08428 + +#define mmROT0_QM_ARC_AUX_LBU_MAX_OUTSTANDING 0x4E0842C + +#define mmROT0_QM_ARC_AUX_LBU_EARLY_BRESP_EN 0x4E08430 + +#define mmROT0_QM_ARC_AUX_LBU_FORCE_RSP_OK 0x4E08434 + +#define mmROT0_QM_ARC_AUX_LBU_NO_WR_INFLIGHT 0x4E0843C + +#define mmROT0_QM_ARC_AUX_LBU_SEI_INTR_ID 0x4E08440 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0 0x4E08500 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_1 0x4E08504 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_2 0x4E08508 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_3 0x4E0850C + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_4 0x4E08510 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_5 0x4E08514 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_6 0x4E08518 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_7 0x4E0851C + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_0 0x4E08520 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_1 0x4E08524 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_2 0x4E08528 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_3 0x4E0852C + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_4 0x4E08530 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_5 0x4E08534 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_6 0x4E08538 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_7 0x4E0853C + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_0 0x4E08540 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_1 0x4E08544 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_2 0x4E08548 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_3 0x4E0854C + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_4 0x4E08550 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_5 0x4E08554 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_6 0x4E08558 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_7 0x4E0855C + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_0 0x4E08560 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_1 0x4E08564 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_2 0x4E08568 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_3 0x4E0856C + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_4 0x4E08570 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_5 0x4E08574 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_6 0x4E08578 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_7 0x4E0857C + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_0 0x4E08580 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_1 0x4E08584 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_2 0x4E08588 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_3 0x4E0858C + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_4 0x4E08590 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_5 0x4E08594 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_6 0x4E08598 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_7 0x4E0859C + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x4E085A0 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x4E085A4 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x4E085A8 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x4E085AC + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x4E085B0 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x4E085B4 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x4E085B8 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x4E085BC + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x4E085C0 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x4E085C4 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x4E085C8 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x4E085CC + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x4E085D0 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x4E085D4 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x4E085D8 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x4E085DC + +#define mmROT0_QM_ARC_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x4E085E0 + +#define mmROT0_QM_ARC_AUX_NIC_Q_VLD_ENTRY_MASK 0x4E085E4 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_DROP_EN 0x4E08620 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_WARN_MSG 0x4E08624 + +#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG 0x4E08628 + +#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWPROT 0x4E08630 + +#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWUSER 0x4E08634 + +#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWBURST 0x4E08638 + +#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWLOCK 0x4E0863C + +#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWCACHE 0x4E08640 + +#define mmROT0_QM_ARC_AUX_DCCM_WRR_ARB_WEIGHT 0x4E08644 + +#define mmROT0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x4E08648 + +#define mmROT0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT 0x4E0864C + +#define mmROT0_QM_ARC_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x4E08650 + +#define mmROT0_QM_ARC_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x4E08654 + +#define mmROT0_QM_ARC_AUX_QMAN_CQ_SHADOW_CI 0x4E08658 + +#define mmROT0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI 0x4E0865C + +#define mmROT0_QM_ARC_AUX_AUX2APB_PROT 0x4E08700 + +#define mmROT0_QM_ARC_AUX_LBW_FORK_WIN_EN 0x4E08704 + +#define mmROT0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x4E08708 + +#define mmROT0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x4E0870C + +#define mmROT0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x4E08710 + +#define mmROT0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x4E08714 + +#define mmROT0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR0 0x4E08718 + +#define mmROT0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK0 0x4E0871C + +#define mmROT0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR1 0x4E08720 + +#define mmROT0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK1 0x4E08724 + +#define mmROT0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR0 0x4E08728 + +#define mmROT0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR1 0x4E0872C + +#define mmROT0_QM_ARC_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x4E08730 + +#define mmROT0_QM_ARC_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x4E08734 + +#define mmROT0_QM_ARC_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x4E08738 + +#define mmROT0_QM_ARC_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x4E0873C + +#define mmROT0_QM_ARC_AUX_CBU_FORK_WIN_EN 0x4E08740 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_LSB 0x4E08750 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_MSB 0x4E08754 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_LSB 0x4E08758 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_MSB 0x4E0875C + +#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_LSB 0x4E08760 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_MSB 0x4E08764 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_LSB 0x4E08768 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_MSB 0x4E0876C + +#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_LSB 0x4E08770 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_MSB 0x4E08774 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_LSB 0x4E08778 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_MSB 0x4E0877C + +#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_LSB 0x4E08780 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_MSB 0x4E08784 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_LSB 0x4E08788 + +#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_MSB 0x4E0878C + +#define mmROT0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_LSB 0x4E08790 + +#define mmROT0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_MSB 0x4E08794 + +#define mmROT0_QM_ARC_AUX_CFG_CBU_TERMINATE_BRESP 0x4E08798 + +#define mmROT0_QM_ARC_AUX_CFG_CBU_TERMINATE_RRESP 0x4E0879C + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_0 0x4E08800 + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_1 0x4E08804 + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_2 0x4E08808 + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_3 0x4E0880C + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_4 0x4E08810 + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_5 0x4E08814 + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_6 0x4E08818 + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_7 0x4E0881C + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_8 0x4E08820 + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_9 0x4E08824 + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_10 0x4E08828 + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_11 0x4E0882C + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_12 0x4E08830 + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_13 0x4E08834 + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_14 0x4E08838 + +#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_15 0x4E0883C + +#define mmROT0_QM_ARC_AUX_DCCM_TRMINATE_AWADDR_ERR 0x4E08840 + +#define mmROT0_QM_ARC_AUX_DCCM_TRMINATE_ARADDR_ERR 0x4E08844 + +#define mmROT0_QM_ARC_AUX_CFG_DCCM_TERMINATE_BRESP 0x4E08848 + +#define mmROT0_QM_ARC_AUX_CFG_DCCM_TERMINATE_RRESP 0x4E0884C + +#define mmROT0_QM_ARC_AUX_CFG_DCCM_TERMINATE_EN 0x4E08850 + +#define mmROT0_QM_ARC_AUX_CFG_DCCM_SECURE_REGION 0x4E08854 + +#define mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x4E08900 + +#define mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_CTL 0x4E08904 + +#define mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x4E08908 + +#define mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR 0x4E0890C + +#define mmROT0_QM_ARC_AUX_ARC_ACC_ENGS_BUSER 0x4E08910 + +#define mmROT0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN 0x4E08920 + +#endif /* ASIC_REG_ROT0_QM_ARC_AUX_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_axuser_nonsecured_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_axuser_nonsecured_regs.h new file mode 100644 index 000000000000..8e040a2ef1c1 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_axuser_nonsecured_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ROT0_QM_AXUSER_NONSECURED_REGS_H_ +#define ASIC_REG_ROT0_QM_AXUSER_NONSECURED_REGS_H_ + +/* + ***************************************** + * ROT0_QM_AXUSER_NONSECURED + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmROT0_QM_AXUSER_NONSECURED_HB_ASID 0x4E0AB80 + +#define mmROT0_QM_AXUSER_NONSECURED_HB_MMU_BP 0x4E0AB84 + +#define mmROT0_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x4E0AB88 + +#define mmROT0_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x4E0AB8C + +#define mmROT0_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x4E0AB90 + +#define mmROT0_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x4E0AB94 + +#define mmROT0_QM_AXUSER_NONSECURED_HB_QOS 0x4E0AB98 + +#define mmROT0_QM_AXUSER_NONSECURED_HB_RSVD 0x4E0AB9C + +#define mmROT0_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x4E0ABA0 + +#define mmROT0_QM_AXUSER_NONSECURED_HB_CORE 0x4E0ABA4 + +#define mmROT0_QM_AXUSER_NONSECURED_E2E_COORD 0x4E0ABA8 + +#define mmROT0_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x4E0ABB0 + +#define mmROT0_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x4E0ABB4 + +#define mmROT0_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x4E0ABB8 + +#define mmROT0_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x4E0ABBC + +#define mmROT0_QM_AXUSER_NONSECURED_LB_COORD 0x4E0ABC0 + +#define mmROT0_QM_AXUSER_NONSECURED_LB_LOCK 0x4E0ABC4 + +#define mmROT0_QM_AXUSER_NONSECURED_LB_RSVD 0x4E0ABC8 + +#define mmROT0_QM_AXUSER_NONSECURED_LB_OVRD 0x4E0ABCC + +#endif /* ASIC_REG_ROT0_QM_AXUSER_NONSECURED_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_cgm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_cgm_regs.h new file mode 100644 index 000000000000..077ae2347a3d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_cgm_regs.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ROT0_QM_CGM_REGS_H_ +#define ASIC_REG_ROT0_QM_CGM_REGS_H_ + +/* + ***************************************** + * ROT0_QM_CGM + * (Prototype: QMAN_CGM) + ***************************************** + */ + +#define mmROT0_QM_CGM_CFG 0x4E0AD80 + +#define mmROT0_QM_CGM_STS 0x4E0AD84 + +#define mmROT0_QM_CGM_CFG1 0x4E0AD88 + +#endif /* ASIC_REG_ROT0_QM_CGM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_regs.h new file mode 100644 index 000000000000..de3c85510af2 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_qm_regs.h @@ -0,0 +1,1057 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ROT0_QM_REGS_H_ +#define ASIC_REG_ROT0_QM_REGS_H_ + +/* + ***************************************** + * ROT0_QM + * (Prototype: QMAN) + ***************************************** + */ + +#define mmROT0_QM_GLBL_CFG0 0x4E0A000 + +#define mmROT0_QM_GLBL_CFG1 0x4E0A004 + +#define mmROT0_QM_GLBL_CFG2 0x4E0A008 + +#define mmROT0_QM_GLBL_ERR_CFG 0x4E0A00C + +#define mmROT0_QM_GLBL_ERR_CFG1 0x4E0A010 + +#define mmROT0_QM_GLBL_ERR_ARC_HALT_EN 0x4E0A014 + +#define mmROT0_QM_GLBL_AXCACHE 0x4E0A018 + +#define mmROT0_QM_GLBL_STS0 0x4E0A01C + +#define mmROT0_QM_GLBL_STS1 0x4E0A020 + +#define mmROT0_QM_GLBL_ERR_STS_0 0x4E0A024 + +#define mmROT0_QM_GLBL_ERR_STS_1 0x4E0A028 + +#define mmROT0_QM_GLBL_ERR_STS_2 0x4E0A02C + +#define mmROT0_QM_GLBL_ERR_STS_3 0x4E0A030 + +#define mmROT0_QM_GLBL_ERR_STS_4 0x4E0A034 + +#define mmROT0_QM_GLBL_ERR_MSG_EN_0 0x4E0A038 + +#define mmROT0_QM_GLBL_ERR_MSG_EN_1 0x4E0A03C + +#define mmROT0_QM_GLBL_ERR_MSG_EN_2 0x4E0A040 + +#define mmROT0_QM_GLBL_ERR_MSG_EN_3 0x4E0A044 + +#define mmROT0_QM_GLBL_ERR_MSG_EN_4 0x4E0A048 + +#define mmROT0_QM_GLBL_PROT 0x4E0A04C + +#define mmROT0_QM_PQ_BASE_LO_0 0x4E0A050 + +#define mmROT0_QM_PQ_BASE_LO_1 0x4E0A054 + +#define mmROT0_QM_PQ_BASE_LO_2 0x4E0A058 + +#define mmROT0_QM_PQ_BASE_LO_3 0x4E0A05C + +#define mmROT0_QM_PQ_BASE_HI_0 0x4E0A060 + +#define mmROT0_QM_PQ_BASE_HI_1 0x4E0A064 + +#define mmROT0_QM_PQ_BASE_HI_2 0x4E0A068 + +#define mmROT0_QM_PQ_BASE_HI_3 0x4E0A06C + +#define mmROT0_QM_PQ_SIZE_0 0x4E0A070 + +#define mmROT0_QM_PQ_SIZE_1 0x4E0A074 + +#define mmROT0_QM_PQ_SIZE_2 0x4E0A078 + +#define mmROT0_QM_PQ_SIZE_3 0x4E0A07C + +#define mmROT0_QM_PQ_PI_0 0x4E0A080 + +#define mmROT0_QM_PQ_PI_1 0x4E0A084 + +#define mmROT0_QM_PQ_PI_2 0x4E0A088 + +#define mmROT0_QM_PQ_PI_3 0x4E0A08C + +#define mmROT0_QM_PQ_CI_0 0x4E0A090 + +#define mmROT0_QM_PQ_CI_1 0x4E0A094 + +#define mmROT0_QM_PQ_CI_2 0x4E0A098 + +#define mmROT0_QM_PQ_CI_3 0x4E0A09C + +#define mmROT0_QM_PQ_CFG0_0 0x4E0A0A0 + +#define mmROT0_QM_PQ_CFG0_1 0x4E0A0A4 + +#define mmROT0_QM_PQ_CFG0_2 0x4E0A0A8 + +#define mmROT0_QM_PQ_CFG0_3 0x4E0A0AC + +#define mmROT0_QM_PQ_CFG1_0 0x4E0A0B0 + +#define mmROT0_QM_PQ_CFG1_1 0x4E0A0B4 + +#define mmROT0_QM_PQ_CFG1_2 0x4E0A0B8 + +#define mmROT0_QM_PQ_CFG1_3 0x4E0A0BC + +#define mmROT0_QM_PQ_STS0_0 0x4E0A0C0 + +#define mmROT0_QM_PQ_STS0_1 0x4E0A0C4 + +#define mmROT0_QM_PQ_STS0_2 0x4E0A0C8 + +#define mmROT0_QM_PQ_STS0_3 0x4E0A0CC + +#define mmROT0_QM_PQ_STS1_0 0x4E0A0D0 + +#define mmROT0_QM_PQ_STS1_1 0x4E0A0D4 + +#define mmROT0_QM_PQ_STS1_2 0x4E0A0D8 + +#define mmROT0_QM_PQ_STS1_3 0x4E0A0DC + +#define mmROT0_QM_CQ_CFG0_0 0x4E0A0E0 + +#define mmROT0_QM_CQ_CFG0_1 0x4E0A0E4 + +#define mmROT0_QM_CQ_CFG0_2 0x4E0A0E8 + +#define mmROT0_QM_CQ_CFG0_3 0x4E0A0EC + +#define mmROT0_QM_CQ_CFG0_4 0x4E0A0F0 + +#define mmROT0_QM_CQ_STS0_0 0x4E0A0F4 + +#define mmROT0_QM_CQ_STS0_1 0x4E0A0F8 + +#define mmROT0_QM_CQ_STS0_2 0x4E0A0FC + +#define mmROT0_QM_CQ_STS0_3 0x4E0A100 + +#define mmROT0_QM_CQ_STS0_4 0x4E0A104 + +#define mmROT0_QM_CQ_CFG1_0 0x4E0A108 + +#define mmROT0_QM_CQ_CFG1_1 0x4E0A10C + +#define mmROT0_QM_CQ_CFG1_2 0x4E0A110 + +#define mmROT0_QM_CQ_CFG1_3 0x4E0A114 + +#define mmROT0_QM_CQ_CFG1_4 0x4E0A118 + +#define mmROT0_QM_CQ_STS1_0 0x4E0A11C + +#define mmROT0_QM_CQ_STS1_1 0x4E0A120 + +#define mmROT0_QM_CQ_STS1_2 0x4E0A124 + +#define mmROT0_QM_CQ_STS1_3 0x4E0A128 + +#define mmROT0_QM_CQ_STS1_4 0x4E0A12C + +#define mmROT0_QM_CQ_PTR_LO_0 0x4E0A150 + +#define mmROT0_QM_CQ_PTR_HI_0 0x4E0A154 + +#define mmROT0_QM_CQ_TSIZE_0 0x4E0A158 + +#define mmROT0_QM_CQ_CTL_0 0x4E0A15C + +#define mmROT0_QM_CQ_PTR_LO_1 0x4E0A160 + +#define mmROT0_QM_CQ_PTR_HI_1 0x4E0A164 + +#define mmROT0_QM_CQ_TSIZE_1 0x4E0A168 + +#define mmROT0_QM_CQ_CTL_1 0x4E0A16C + +#define mmROT0_QM_CQ_PTR_LO_2 0x4E0A170 + +#define mmROT0_QM_CQ_PTR_HI_2 0x4E0A174 + +#define mmROT0_QM_CQ_TSIZE_2 0x4E0A178 + +#define mmROT0_QM_CQ_CTL_2 0x4E0A17C + +#define mmROT0_QM_CQ_PTR_LO_3 0x4E0A180 + +#define mmROT0_QM_CQ_PTR_HI_3 0x4E0A184 + +#define mmROT0_QM_CQ_TSIZE_3 0x4E0A188 + +#define mmROT0_QM_CQ_CTL_3 0x4E0A18C + +#define mmROT0_QM_CQ_PTR_LO_4 0x4E0A190 + +#define mmROT0_QM_CQ_PTR_HI_4 0x4E0A194 + +#define mmROT0_QM_CQ_TSIZE_4 0x4E0A198 + +#define mmROT0_QM_CQ_CTL_4 0x4E0A19C + +#define mmROT0_QM_CQ_TSIZE_STS_0 0x4E0A1A0 + +#define mmROT0_QM_CQ_TSIZE_STS_1 0x4E0A1A4 + +#define mmROT0_QM_CQ_TSIZE_STS_2 0x4E0A1A8 + +#define mmROT0_QM_CQ_TSIZE_STS_3 0x4E0A1AC + +#define mmROT0_QM_CQ_TSIZE_STS_4 0x4E0A1B0 + +#define mmROT0_QM_CQ_PTR_LO_STS_0 0x4E0A1B4 + +#define mmROT0_QM_CQ_PTR_LO_STS_1 0x4E0A1B8 + +#define mmROT0_QM_CQ_PTR_LO_STS_2 0x4E0A1BC + +#define mmROT0_QM_CQ_PTR_LO_STS_3 0x4E0A1C0 + +#define mmROT0_QM_CQ_PTR_LO_STS_4 0x4E0A1C4 + +#define mmROT0_QM_CQ_PTR_HI_STS_0 0x4E0A1C8 + +#define mmROT0_QM_CQ_PTR_HI_STS_1 0x4E0A1CC + +#define mmROT0_QM_CQ_PTR_HI_STS_2 0x4E0A1D0 + +#define mmROT0_QM_CQ_PTR_HI_STS_3 0x4E0A1D4 + +#define mmROT0_QM_CQ_PTR_HI_STS_4 0x4E0A1D8 + +#define mmROT0_QM_CQ_IFIFO_STS_0 0x4E0A1DC + +#define mmROT0_QM_CQ_IFIFO_STS_1 0x4E0A1E0 + +#define mmROT0_QM_CQ_IFIFO_STS_2 0x4E0A1E4 + +#define mmROT0_QM_CQ_IFIFO_STS_3 0x4E0A1E8 + +#define mmROT0_QM_CQ_IFIFO_STS_4 0x4E0A1EC + +#define mmROT0_QM_CP_MSG_BASE0_ADDR_LO_0 0x4E0A1F0 + +#define mmROT0_QM_CP_MSG_BASE0_ADDR_LO_1 0x4E0A1F4 + +#define mmROT0_QM_CP_MSG_BASE0_ADDR_LO_2 0x4E0A1F8 + +#define mmROT0_QM_CP_MSG_BASE0_ADDR_LO_3 0x4E0A1FC + +#define mmROT0_QM_CP_MSG_BASE0_ADDR_LO_4 0x4E0A200 + +#define mmROT0_QM_CP_MSG_BASE0_ADDR_HI_0 0x4E0A204 + +#define mmROT0_QM_CP_MSG_BASE0_ADDR_HI_1 0x4E0A208 + +#define mmROT0_QM_CP_MSG_BASE0_ADDR_HI_2 0x4E0A20C + +#define mmROT0_QM_CP_MSG_BASE0_ADDR_HI_3 0x4E0A210 + +#define mmROT0_QM_CP_MSG_BASE0_ADDR_HI_4 0x4E0A214 + +#define mmROT0_QM_CP_MSG_BASE1_ADDR_LO_0 0x4E0A218 + +#define mmROT0_QM_CP_MSG_BASE1_ADDR_LO_1 0x4E0A21C + +#define mmROT0_QM_CP_MSG_BASE1_ADDR_LO_2 0x4E0A220 + +#define mmROT0_QM_CP_MSG_BASE1_ADDR_LO_3 0x4E0A224 + +#define mmROT0_QM_CP_MSG_BASE1_ADDR_LO_4 0x4E0A228 + +#define mmROT0_QM_CP_MSG_BASE1_ADDR_HI_0 0x4E0A22C + +#define mmROT0_QM_CP_MSG_BASE1_ADDR_HI_1 0x4E0A230 + +#define mmROT0_QM_CP_MSG_BASE1_ADDR_HI_2 0x4E0A234 + +#define mmROT0_QM_CP_MSG_BASE1_ADDR_HI_3 0x4E0A238 + +#define mmROT0_QM_CP_MSG_BASE1_ADDR_HI_4 0x4E0A23C + +#define mmROT0_QM_CP_MSG_BASE2_ADDR_LO_0 0x4E0A240 + +#define mmROT0_QM_CP_MSG_BASE2_ADDR_LO_1 0x4E0A244 + +#define mmROT0_QM_CP_MSG_BASE2_ADDR_LO_2 0x4E0A248 + +#define mmROT0_QM_CP_MSG_BASE2_ADDR_LO_3 0x4E0A24C + +#define mmROT0_QM_CP_MSG_BASE2_ADDR_LO_4 0x4E0A250 + +#define mmROT0_QM_CP_MSG_BASE2_ADDR_HI_0 0x4E0A254 + +#define mmROT0_QM_CP_MSG_BASE2_ADDR_HI_1 0x4E0A258 + +#define mmROT0_QM_CP_MSG_BASE2_ADDR_HI_2 0x4E0A25C + +#define mmROT0_QM_CP_MSG_BASE2_ADDR_HI_3 0x4E0A260 + +#define mmROT0_QM_CP_MSG_BASE2_ADDR_HI_4 0x4E0A264 + +#define mmROT0_QM_CP_MSG_BASE3_ADDR_LO_0 0x4E0A268 + +#define mmROT0_QM_CP_MSG_BASE3_ADDR_LO_1 0x4E0A26C + +#define mmROT0_QM_CP_MSG_BASE3_ADDR_LO_2 0x4E0A270 + +#define mmROT0_QM_CP_MSG_BASE3_ADDR_LO_3 0x4E0A274 + +#define mmROT0_QM_CP_MSG_BASE3_ADDR_LO_4 0x4E0A278 + +#define mmROT0_QM_CP_MSG_BASE3_ADDR_HI_0 0x4E0A27C + +#define mmROT0_QM_CP_MSG_BASE3_ADDR_HI_1 0x4E0A280 + +#define mmROT0_QM_CP_MSG_BASE3_ADDR_HI_2 0x4E0A284 + +#define mmROT0_QM_CP_MSG_BASE3_ADDR_HI_3 0x4E0A288 + +#define mmROT0_QM_CP_MSG_BASE3_ADDR_HI_4 0x4E0A28C + +#define mmROT0_QM_CP_FENCE0_RDATA_0 0x4E0A290 + +#define mmROT0_QM_CP_FENCE0_RDATA_1 0x4E0A294 + +#define mmROT0_QM_CP_FENCE0_RDATA_2 0x4E0A298 + +#define mmROT0_QM_CP_FENCE0_RDATA_3 0x4E0A29C + +#define mmROT0_QM_CP_FENCE0_RDATA_4 0x4E0A2A0 + +#define mmROT0_QM_CP_FENCE1_RDATA_0 0x4E0A2A4 + +#define mmROT0_QM_CP_FENCE1_RDATA_1 0x4E0A2A8 + +#define mmROT0_QM_CP_FENCE1_RDATA_2 0x4E0A2AC + +#define mmROT0_QM_CP_FENCE1_RDATA_3 0x4E0A2B0 + +#define mmROT0_QM_CP_FENCE1_RDATA_4 0x4E0A2B4 + +#define mmROT0_QM_CP_FENCE2_RDATA_0 0x4E0A2B8 + +#define mmROT0_QM_CP_FENCE2_RDATA_1 0x4E0A2BC + +#define mmROT0_QM_CP_FENCE2_RDATA_2 0x4E0A2C0 + +#define mmROT0_QM_CP_FENCE2_RDATA_3 0x4E0A2C4 + +#define mmROT0_QM_CP_FENCE2_RDATA_4 0x4E0A2C8 + +#define mmROT0_QM_CP_FENCE3_RDATA_0 0x4E0A2CC + +#define mmROT0_QM_CP_FENCE3_RDATA_1 0x4E0A2D0 + +#define mmROT0_QM_CP_FENCE3_RDATA_2 0x4E0A2D4 + +#define mmROT0_QM_CP_FENCE3_RDATA_3 0x4E0A2D8 + +#define mmROT0_QM_CP_FENCE3_RDATA_4 0x4E0A2DC + +#define mmROT0_QM_CP_FENCE0_CNT_0 0x4E0A2E0 + +#define mmROT0_QM_CP_FENCE0_CNT_1 0x4E0A2E4 + +#define mmROT0_QM_CP_FENCE0_CNT_2 0x4E0A2E8 + +#define mmROT0_QM_CP_FENCE0_CNT_3 0x4E0A2EC + +#define mmROT0_QM_CP_FENCE0_CNT_4 0x4E0A2F0 + +#define mmROT0_QM_CP_FENCE1_CNT_0 0x4E0A2F4 + +#define mmROT0_QM_CP_FENCE1_CNT_1 0x4E0A2F8 + +#define mmROT0_QM_CP_FENCE1_CNT_2 0x4E0A2FC + +#define mmROT0_QM_CP_FENCE1_CNT_3 0x4E0A300 + +#define mmROT0_QM_CP_FENCE1_CNT_4 0x4E0A304 + +#define mmROT0_QM_CP_FENCE2_CNT_0 0x4E0A308 + +#define mmROT0_QM_CP_FENCE2_CNT_1 0x4E0A30C + +#define mmROT0_QM_CP_FENCE2_CNT_2 0x4E0A310 + +#define mmROT0_QM_CP_FENCE2_CNT_3 0x4E0A314 + +#define mmROT0_QM_CP_FENCE2_CNT_4 0x4E0A318 + +#define mmROT0_QM_CP_FENCE3_CNT_0 0x4E0A31C + +#define mmROT0_QM_CP_FENCE3_CNT_1 0x4E0A320 + +#define mmROT0_QM_CP_FENCE3_CNT_2 0x4E0A324 + +#define mmROT0_QM_CP_FENCE3_CNT_3 0x4E0A328 + +#define mmROT0_QM_CP_FENCE3_CNT_4 0x4E0A32C + +#define mmROT0_QM_CP_BARRIER_CFG 0x4E0A330 + +#define mmROT0_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0x4E0A334 + +#define mmROT0_QM_CP_LDMA_DST_BASE_LO_OFFSET 0x4E0A338 + +#define mmROT0_QM_CP_LDMA_TSIZE_OFFSET 0x4E0A33C + +#define mmROT0_QM_CP_CQ_PTR_LO_OFFSET_0 0x4E0A340 + +#define mmROT0_QM_CP_CQ_PTR_LO_OFFSET_1 0x4E0A344 + +#define mmROT0_QM_CP_CQ_PTR_LO_OFFSET_2 0x4E0A348 + +#define mmROT0_QM_CP_CQ_PTR_LO_OFFSET_3 0x4E0A34C + +#define mmROT0_QM_CP_CQ_PTR_LO_OFFSET_4 0x4E0A350 + +#define mmROT0_QM_CP_STS_0 0x4E0A368 + +#define mmROT0_QM_CP_STS_1 0x4E0A36C + +#define mmROT0_QM_CP_STS_2 0x4E0A370 + +#define mmROT0_QM_CP_STS_3 0x4E0A374 + +#define mmROT0_QM_CP_STS_4 0x4E0A378 + +#define mmROT0_QM_CP_CURRENT_INST_LO_0 0x4E0A37C + +#define mmROT0_QM_CP_CURRENT_INST_LO_1 0x4E0A380 + +#define mmROT0_QM_CP_CURRENT_INST_LO_2 0x4E0A384 + +#define mmROT0_QM_CP_CURRENT_INST_LO_3 0x4E0A388 + +#define mmROT0_QM_CP_CURRENT_INST_LO_4 0x4E0A38C + +#define mmROT0_QM_CP_CURRENT_INST_HI_0 0x4E0A390 + +#define mmROT0_QM_CP_CURRENT_INST_HI_1 0x4E0A394 + +#define mmROT0_QM_CP_CURRENT_INST_HI_2 0x4E0A398 + +#define mmROT0_QM_CP_CURRENT_INST_HI_3 0x4E0A39C + +#define mmROT0_QM_CP_CURRENT_INST_HI_4 0x4E0A3A0 + +#define mmROT0_QM_CP_PRED_0 0x4E0A3A4 + +#define mmROT0_QM_CP_PRED_1 0x4E0A3A8 + +#define mmROT0_QM_CP_PRED_2 0x4E0A3AC + +#define mmROT0_QM_CP_PRED_3 0x4E0A3B0 + +#define mmROT0_QM_CP_PRED_4 0x4E0A3B4 + +#define mmROT0_QM_CP_PRED_UPEN_0 0x4E0A3B8 + +#define mmROT0_QM_CP_PRED_UPEN_1 0x4E0A3BC + +#define mmROT0_QM_CP_PRED_UPEN_2 0x4E0A3C0 + +#define mmROT0_QM_CP_PRED_UPEN_3 0x4E0A3C4 + +#define mmROT0_QM_CP_PRED_UPEN_4 0x4E0A3C8 + +#define mmROT0_QM_CP_DBG_0_0 0x4E0A3CC + +#define mmROT0_QM_CP_DBG_0_1 0x4E0A3D0 + +#define mmROT0_QM_CP_DBG_0_2 0x4E0A3D4 + +#define mmROT0_QM_CP_DBG_0_3 0x4E0A3D8 + +#define mmROT0_QM_CP_DBG_0_4 0x4E0A3DC + +#define mmROT0_QM_CP_CPDMA_UP_CRED_0 0x4E0A3E0 + +#define mmROT0_QM_CP_CPDMA_UP_CRED_1 0x4E0A3E4 + +#define mmROT0_QM_CP_CPDMA_UP_CRED_2 0x4E0A3E8 + +#define mmROT0_QM_CP_CPDMA_UP_CRED_3 0x4E0A3EC + +#define mmROT0_QM_CP_CPDMA_UP_CRED_4 0x4E0A3F0 + +#define mmROT0_QM_CP_IN_DATA_LO_0 0x4E0A3F4 + +#define mmROT0_QM_CP_IN_DATA_LO_1 0x4E0A3F8 + +#define mmROT0_QM_CP_IN_DATA_LO_2 0x4E0A3FC + +#define mmROT0_QM_CP_IN_DATA_LO_3 0x4E0A400 + +#define mmROT0_QM_CP_IN_DATA_LO_4 0x4E0A404 + +#define mmROT0_QM_CP_IN_DATA_HI_0 0x4E0A408 + +#define mmROT0_QM_CP_IN_DATA_HI_1 0x4E0A40C + +#define mmROT0_QM_CP_IN_DATA_HI_2 0x4E0A410 + +#define mmROT0_QM_CP_IN_DATA_HI_3 0x4E0A414 + +#define mmROT0_QM_CP_IN_DATA_HI_4 0x4E0A418 + +#define mmROT0_QM_PQC_HBW_BASE_LO_0 0x4E0A41C + +#define mmROT0_QM_PQC_HBW_BASE_LO_1 0x4E0A420 + +#define mmROT0_QM_PQC_HBW_BASE_LO_2 0x4E0A424 + +#define mmROT0_QM_PQC_HBW_BASE_LO_3 0x4E0A428 + +#define mmROT0_QM_PQC_HBW_BASE_HI_0 0x4E0A42C + +#define mmROT0_QM_PQC_HBW_BASE_HI_1 0x4E0A430 + +#define mmROT0_QM_PQC_HBW_BASE_HI_2 0x4E0A434 + +#define mmROT0_QM_PQC_HBW_BASE_HI_3 0x4E0A438 + +#define mmROT0_QM_PQC_SIZE_0 0x4E0A43C + +#define mmROT0_QM_PQC_SIZE_1 0x4E0A440 + +#define mmROT0_QM_PQC_SIZE_2 0x4E0A444 + +#define mmROT0_QM_PQC_SIZE_3 0x4E0A448 + +#define mmROT0_QM_PQC_PI_0 0x4E0A44C + +#define mmROT0_QM_PQC_PI_1 0x4E0A450 + +#define mmROT0_QM_PQC_PI_2 0x4E0A454 + +#define mmROT0_QM_PQC_PI_3 0x4E0A458 + +#define mmROT0_QM_PQC_LBW_WDATA_0 0x4E0A45C + +#define mmROT0_QM_PQC_LBW_WDATA_1 0x4E0A460 + +#define mmROT0_QM_PQC_LBW_WDATA_2 0x4E0A464 + +#define mmROT0_QM_PQC_LBW_WDATA_3 0x4E0A468 + +#define mmROT0_QM_PQC_LBW_BASE_LO_0 0x4E0A46C + +#define mmROT0_QM_PQC_LBW_BASE_LO_1 0x4E0A470 + +#define mmROT0_QM_PQC_LBW_BASE_LO_2 0x4E0A474 + +#define mmROT0_QM_PQC_LBW_BASE_LO_3 0x4E0A478 + +#define mmROT0_QM_PQC_LBW_BASE_HI_0 0x4E0A47C + +#define mmROT0_QM_PQC_LBW_BASE_HI_1 0x4E0A480 + +#define mmROT0_QM_PQC_LBW_BASE_HI_2 0x4E0A484 + +#define mmROT0_QM_PQC_LBW_BASE_HI_3 0x4E0A488 + +#define mmROT0_QM_PQC_CFG 0x4E0A48C + +#define mmROT0_QM_PQC_SECURE_PUSH_IND 0x4E0A490 + +#define mmROT0_QM_ARB_MASK 0x4E0A4A0 + +#define mmROT0_QM_ARB_CFG_0 0x4E0A4A4 + +#define mmROT0_QM_ARB_CHOICE_Q_PUSH 0x4E0A4A8 + +#define mmROT0_QM_ARB_WRR_WEIGHT_0 0x4E0A4AC + +#define mmROT0_QM_ARB_WRR_WEIGHT_1 0x4E0A4B0 + +#define mmROT0_QM_ARB_WRR_WEIGHT_2 0x4E0A4B4 + +#define mmROT0_QM_ARB_WRR_WEIGHT_3 0x4E0A4B8 + +#define mmROT0_QM_ARB_CFG_1 0x4E0A4BC + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_0 0x4E0A4C0 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_1 0x4E0A4C4 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_2 0x4E0A4C8 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_3 0x4E0A4CC + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_4 0x4E0A4D0 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_5 0x4E0A4D4 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_6 0x4E0A4D8 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_7 0x4E0A4DC + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_8 0x4E0A4E0 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_9 0x4E0A4E4 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_10 0x4E0A4E8 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_11 0x4E0A4EC + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_12 0x4E0A4F0 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_13 0x4E0A4F4 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_14 0x4E0A4F8 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_15 0x4E0A4FC + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_16 0x4E0A500 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_17 0x4E0A504 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_18 0x4E0A508 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_19 0x4E0A50C + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_20 0x4E0A510 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_21 0x4E0A514 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_22 0x4E0A518 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_23 0x4E0A51C + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_24 0x4E0A520 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_25 0x4E0A524 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_26 0x4E0A528 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_27 0x4E0A52C + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_28 0x4E0A530 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_29 0x4E0A534 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_30 0x4E0A538 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_31 0x4E0A53C + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_32 0x4E0A540 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_33 0x4E0A544 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_34 0x4E0A548 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_35 0x4E0A54C + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_36 0x4E0A550 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_37 0x4E0A554 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_38 0x4E0A558 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_39 0x4E0A55C + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_40 0x4E0A560 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_41 0x4E0A564 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_42 0x4E0A568 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_43 0x4E0A56C + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_44 0x4E0A570 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_45 0x4E0A574 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_46 0x4E0A578 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_47 0x4E0A57C + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_48 0x4E0A580 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_49 0x4E0A584 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_50 0x4E0A588 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_51 0x4E0A58C + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_52 0x4E0A590 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_53 0x4E0A594 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_54 0x4E0A598 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_55 0x4E0A59C + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_56 0x4E0A5A0 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_57 0x4E0A5A4 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_58 0x4E0A5A8 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_59 0x4E0A5AC + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_60 0x4E0A5B0 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_61 0x4E0A5B4 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_62 0x4E0A5B8 + +#define mmROT0_QM_ARB_MST_AVAIL_CRED_63 0x4E0A5BC + +#define mmROT0_QM_ARB_MST_CRED_INC 0x4E0A5E0 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_0 0x4E0A5E4 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_1 0x4E0A5E8 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_2 0x4E0A5EC + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_3 0x4E0A5F0 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_4 0x4E0A5F4 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_5 0x4E0A5F8 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_6 0x4E0A5FC + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_7 0x4E0A600 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_8 0x4E0A604 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_9 0x4E0A608 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_10 0x4E0A60C + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_11 0x4E0A610 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_12 0x4E0A614 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_13 0x4E0A618 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_14 0x4E0A61C + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_15 0x4E0A620 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_16 0x4E0A624 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_17 0x4E0A628 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_18 0x4E0A62C + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_19 0x4E0A630 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_20 0x4E0A634 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_21 0x4E0A638 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_22 0x4E0A63C + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_23 0x4E0A640 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_24 0x4E0A644 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_25 0x4E0A648 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_26 0x4E0A64C + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_27 0x4E0A650 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_28 0x4E0A654 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_29 0x4E0A658 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_30 0x4E0A65C + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_31 0x4E0A660 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_32 0x4E0A664 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_33 0x4E0A668 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_34 0x4E0A66C + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_35 0x4E0A670 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_36 0x4E0A674 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_37 0x4E0A678 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_38 0x4E0A67C + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_39 0x4E0A680 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_40 0x4E0A684 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_41 0x4E0A688 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_42 0x4E0A68C + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_43 0x4E0A690 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_44 0x4E0A694 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_45 0x4E0A698 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_46 0x4E0A69C + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_47 0x4E0A6A0 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_48 0x4E0A6A4 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_49 0x4E0A6A8 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_50 0x4E0A6AC + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_51 0x4E0A6B0 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_52 0x4E0A6B4 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_53 0x4E0A6B8 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_54 0x4E0A6BC + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_55 0x4E0A6C0 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_56 0x4E0A6C4 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_57 0x4E0A6C8 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_58 0x4E0A6CC + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_59 0x4E0A6D0 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_60 0x4E0A6D4 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_61 0x4E0A6D8 + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_62 0x4E0A6DC + +#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_63 0x4E0A6E0 + +#define mmROT0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x4E0A704 + +#define mmROT0_QM_ARB_MST_SLAVE_EN 0x4E0A708 + +#define mmROT0_QM_ARB_MST_SLAVE_EN_1 0x4E0A70C + +#define mmROT0_QM_ARB_SLV_CHOICE_WDT 0x4E0A710 + +#define mmROT0_QM_ARB_SLV_ID 0x4E0A714 + +#define mmROT0_QM_ARB_MST_QUIET_PER 0x4E0A718 + +#define mmROT0_QM_ARB_MSG_MAX_INFLIGHT 0x4E0A744 + +#define mmROT0_QM_ARB_BASE_LO 0x4E0A754 + +#define mmROT0_QM_ARB_BASE_HI 0x4E0A758 + +#define mmROT0_QM_ARB_STATE_STS 0x4E0A780 + +#define mmROT0_QM_ARB_CHOICE_FULLNESS_STS 0x4E0A784 + +#define mmROT0_QM_ARB_MSG_STS 0x4E0A788 + +#define mmROT0_QM_ARB_SLV_CHOICE_Q_HEAD 0x4E0A78C + +#define mmROT0_QM_ARB_ERR_CAUSE 0x4E0A79C + +#define mmROT0_QM_ARB_ERR_MSG_EN 0x4E0A7A0 + +#define mmROT0_QM_ARB_ERR_STS_DRP 0x4E0A7A8 + +#define mmROT0_QM_ARB_MST_CRED_STS 0x4E0A7B0 + +#define mmROT0_QM_ARB_MST_CRED_STS_1 0x4E0A7B4 + +#define mmROT0_QM_CSMR_STRICT_PRIO_CFG 0x4E0A7FC + +#define mmROT0_QM_ARC_CQ_CFG0 0x4E0A800 + +#define mmROT0_QM_ARC_CQ_CFG1 0x4E0A804 + +#define mmROT0_QM_ARC_CQ_PTR_LO 0x4E0A808 + +#define mmROT0_QM_ARC_CQ_PTR_HI 0x4E0A80C + +#define mmROT0_QM_ARC_CQ_TSIZE 0x4E0A810 + +#define mmROT0_QM_ARC_CQ_CTL 0x4E0A814 + +#define mmROT0_QM_ARC_CQ_IFIFO_STS 0x4E0A81C + +#define mmROT0_QM_ARC_CQ_STS0 0x4E0A820 + +#define mmROT0_QM_ARC_CQ_STS1 0x4E0A824 + +#define mmROT0_QM_ARC_CQ_TSIZE_STS 0x4E0A828 + +#define mmROT0_QM_ARC_CQ_PTR_LO_STS 0x4E0A82C + +#define mmROT0_QM_ARC_CQ_PTR_HI_STS 0x4E0A830 + +#define mmROT0_QM_CP_WR_ARC_ADDR_HI 0x4E0A834 + +#define mmROT0_QM_CP_WR_ARC_ADDR_LO 0x4E0A838 + +#define mmROT0_QM_ARC_CQ_IFIFO_MSG_BASE_HI 0x4E0A83C + +#define mmROT0_QM_ARC_CQ_IFIFO_MSG_BASE_LO 0x4E0A840 + +#define mmROT0_QM_ARC_CQ_CTL_MSG_BASE_HI 0x4E0A844 + +#define mmROT0_QM_ARC_CQ_CTL_MSG_BASE_LO 0x4E0A848 + +#define mmROT0_QM_CQ_IFIFO_MSG_BASE_HI 0x4E0A84C + +#define mmROT0_QM_CQ_IFIFO_MSG_BASE_LO 0x4E0A850 + +#define mmROT0_QM_CQ_CTL_MSG_BASE_HI 0x4E0A854 + +#define mmROT0_QM_CQ_CTL_MSG_BASE_LO 0x4E0A858 + +#define mmROT0_QM_ADDR_OVRD 0x4E0A85C + +#define mmROT0_QM_CQ_IFIFO_CI_0 0x4E0A860 + +#define mmROT0_QM_CQ_IFIFO_CI_1 0x4E0A864 + +#define mmROT0_QM_CQ_IFIFO_CI_2 0x4E0A868 + +#define mmROT0_QM_CQ_IFIFO_CI_3 0x4E0A86C + +#define mmROT0_QM_CQ_IFIFO_CI_4 0x4E0A870 + +#define mmROT0_QM_ARC_CQ_IFIFO_CI 0x4E0A874 + +#define mmROT0_QM_CQ_CTL_CI_0 0x4E0A878 + +#define mmROT0_QM_CQ_CTL_CI_1 0x4E0A87C + +#define mmROT0_QM_CQ_CTL_CI_2 0x4E0A880 + +#define mmROT0_QM_CQ_CTL_CI_3 0x4E0A884 + +#define mmROT0_QM_CQ_CTL_CI_4 0x4E0A888 + +#define mmROT0_QM_ARC_CQ_CTL_CI 0x4E0A88C + +#define mmROT0_QM_CP_CFG 0x4E0A890 + +#define mmROT0_QM_CP_EXT_SWITCH 0x4E0A894 + +#define mmROT0_QM_CP_SWITCH_WD_SET 0x4E0A898 + +#define mmROT0_QM_CP_SWITCH_WD 0x4E0A89C + +#define mmROT0_QM_ARC_LB_ADDR_BASE_LO 0x4E0A8A4 + +#define mmROT0_QM_ARC_LB_ADDR_BASE_HI 0x4E0A8A8 + +#define mmROT0_QM_ENGINE_BASE_ADDR_HI 0x4E0A8AC + +#define mmROT0_QM_ENGINE_BASE_ADDR_LO 0x4E0A8B0 + +#define mmROT0_QM_ENGINE_ADDR_RANGE_SIZE 0x4E0A8B4 + +#define mmROT0_QM_QM_ARC_AUX_BASE_ADDR_HI 0x4E0A8B8 + +#define mmROT0_QM_QM_ARC_AUX_BASE_ADDR_LO 0x4E0A8BC + +#define mmROT0_QM_QM_BASE_ADDR_HI 0x4E0A8C0 + +#define mmROT0_QM_QM_BASE_ADDR_LO 0x4E0A8C4 + +#define mmROT0_QM_ARC_PQC_SECURE_PUSH_IND 0x4E0A8C8 + +#define mmROT0_QM_PQC_STS_0_0 0x4E0A8D0 + +#define mmROT0_QM_PQC_STS_0_1 0x4E0A8D4 + +#define mmROT0_QM_PQC_STS_0_2 0x4E0A8D8 + +#define mmROT0_QM_PQC_STS_0_3 0x4E0A8DC + +#define mmROT0_QM_PQC_STS_1_0 0x4E0A8E0 + +#define mmROT0_QM_PQC_STS_1_1 0x4E0A8E4 + +#define mmROT0_QM_PQC_STS_1_2 0x4E0A8E8 + +#define mmROT0_QM_PQC_STS_1_3 0x4E0A8EC + +#define mmROT0_QM_SEI_STATUS 0x4E0A8F0 + +#define mmROT0_QM_SEI_MASK 0x4E0A8F4 + +#define mmROT0_QM_GLBL_ERR_ADDR_LO 0x4E0AD00 + +#define mmROT0_QM_GLBL_ERR_ADDR_HI 0x4E0AD04 + +#define mmROT0_QM_GLBL_ERR_WDATA 0x4E0AD08 + +#define mmROT0_QM_L2H_MASK_LO 0x4E0AD14 + +#define mmROT0_QM_L2H_MASK_HI 0x4E0AD18 + +#define mmROT0_QM_L2H_CMPR_LO 0x4E0AD1C + +#define mmROT0_QM_L2H_CMPR_HI 0x4E0AD20 + +#define mmROT0_QM_LOCAL_RANGE_BASE 0x4E0AD24 + +#define mmROT0_QM_LOCAL_RANGE_SIZE 0x4E0AD28 + +#define mmROT0_QM_HBW_RD_RATE_LIM_CFG_1 0x4E0AD30 + +#define mmROT0_QM_LBW_WR_RATE_LIM_CFG_0 0x4E0AD34 + +#define mmROT0_QM_LBW_WR_RATE_LIM_CFG_1 0x4E0AD38 + +#define mmROT0_QM_HBW_RD_RATE_LIM_CFG_0 0x4E0AD3C + +#define mmROT0_QM_IND_GW_APB_CFG 0x4E0AD40 + +#define mmROT0_QM_IND_GW_APB_WDATA 0x4E0AD44 + +#define mmROT0_QM_IND_GW_APB_RDATA 0x4E0AD48 + +#define mmROT0_QM_IND_GW_APB_STATUS 0x4E0AD4C + +#define mmROT0_QM_PERF_CNT_FREE_LO 0x4E0AD60 + +#define mmROT0_QM_PERF_CNT_FREE_HI 0x4E0AD64 + +#define mmROT0_QM_PERF_CNT_IDLE_LO 0x4E0AD68 + +#define mmROT0_QM_PERF_CNT_IDLE_HI 0x4E0AD6C + +#define mmROT0_QM_PERF_CNT_CFG 0x4E0AD70 + +#endif /* ASIC_REG_ROT0_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_regs.h new file mode 100644 index 000000000000..7d85dc5559da --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/rot0_regs.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_ROT0_REGS_H_ +#define ASIC_REG_ROT0_REGS_H_ + +/* + ***************************************** + * ROT0 + * (Prototype: ROTATOR) + ***************************************** + */ + +#define mmROT0_KMD_MODE 0x4E0B000 + +#define mmROT0_CPL_QUEUE_EN 0x4E0B004 + +#define mmROT0_CPL_QUEUE_ADDR_L 0x4E0B008 + +#define mmROT0_CPL_QUEUE_ADDR_H 0x4E0B00C + +#define mmROT0_CPL_QUEUE_DATA 0x4E0B010 + +#define mmROT0_CPL_QUEUE_AWUSER 0x4E0B014 + +#define mmROT0_CPL_QUEUE_AXI 0x4E0B018 + +#define mmROT0_CPL_MSG_THRESHOLD 0x4E0B020 + +#define mmROT0_CPL_MSG_AXI 0x4E0B024 + +#define mmROT0_AXI_WB 0x4E0B028 + +#define mmROT0_ERR_CFG 0x4E0B02C + +#define mmROT0_ERR_STATUS 0x4E0B030 + +#define mmROT0_WBC_MAX_OUTSTANDING 0x4E0B038 + +#define mmROT0_WBC_RL 0x4E0B03C + +#define mmROT0_WBC_INFLIGHTS 0x4E0B040 + +#define mmROT0_WBC_INFO 0x4E0B044 + +#define mmROT0_WBC_MON 0x4E0B048 + +#define mmROT0_RSB_CAM_MAX_SIZE 0x4E0B04C + +#define mmROT0_RSB_CFG 0x4E0B050 + +#define mmROT0_RSB_MAX_OS 0x4E0B054 + +#define mmROT0_RSB_RL 0x4E0B058 + +#define mmROT0_RSB_INFLIGHTS 0x4E0B05C + +#define mmROT0_RSB_OCCUPANCY 0x4E0B060 + +#define mmROT0_RSB_INFO 0x4E0B064 + +#define mmROT0_RSB_MON 0x4E0B068 + +#define mmROT0_RSB_MON_CONTEXT_ID 0x4E0B06C + +#define mmROT0_MSS_HALT 0x4E0B070 + +#define mmROT0_MSS_SEI_STATUS 0x4E0B074 + +#define mmROT0_MSS_SEI_MASK 0x4E0B078 + +#define mmROT0_MSS_SPI_STATUS 0x4E0B07C + +#define mmROT0_MSS_SPI_MASK 0x4E0B080 + +#define mmROT0_DISABLE_PAD_CALC 0x4E0B084 + +#define mmROT0_QMAN_CFG 0x4E0B088 + +#define mmROT0_CLK_EN 0x4E0B08C + +#define mmROT0_MRSB_CAM_MAX_SIZE 0x4E0B090 + +#define mmROT0_MRSB_CFG 0x4E0B094 + +#define mmROT0_MRSB_MAX_OS 0x4E0B098 + +#define mmROT0_MRSB_RL 0x4E0B09C + +#define mmROT0_MRSB_INFLIGHTS 0x4E0B0A0 + +#define mmROT0_MRSB_OCCUPANCY 0x4E0B0A4 + +#define mmROT0_MRSB_INFO 0x4E0B0A8 + +#define mmROT0_MRSB_MON 0x4E0B0AC + +#define mmROT0_MRSB_MON_CONTEXT_ID 0x4E0B0B0 + +#define mmROT0_MSS_STS 0x4E0B0B4 + +#endif /* ASIC_REG_ROT0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/xbar_edge_0_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/xbar_edge_0_regs.h new file mode 100644 index 000000000000..e8aebd7f5f85 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/xbar_edge_0_regs.h @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_XBAR_EDGE_0_REGS_H_ +#define ASIC_REG_XBAR_EDGE_0_REGS_H_ + +/* + ***************************************** + * XBAR_EDGE_0 + * (Prototype: XBAR) + ***************************************** + */ + +#define mmXBAR_EDGE_0_LBW_HIF0_BASE_ADDR 0x4D48000 + +#define mmXBAR_EDGE_0_LBW_HIF0_ADDR_MASK 0x4D48004 + +#define mmXBAR_EDGE_0_LBW_HIF1_BASE_ADDR 0x4D48008 + +#define mmXBAR_EDGE_0_LBW_HIF1_ADDR_MASK 0x4D4800C + +#define mmXBAR_EDGE_0_LBW_HMMU0_BASE_ADDR 0x4D48010 + +#define mmXBAR_EDGE_0_LBW_HMMU0_ADDR_MASK 0x4D48014 + +#define mmXBAR_EDGE_0_LBW_HMMU1_BASE_ADDR 0x4D48018 + +#define mmXBAR_EDGE_0_LBW_HMMU1_ADDR_MASK 0x4D4801C + +#define mmXBAR_EDGE_0_LBW_EDMA_BASE_ADDR0 0x4D48020 + +#define mmXBAR_EDGE_0_LBW_EDMA_ADDR_MASK0 0x4D48024 + +#define mmXBAR_EDGE_0_LBW_EDMA_BASE_ADDR1 0x4D48028 + +#define mmXBAR_EDGE_0_LBW_EDMA_ADDR_MASK1 0x4D4802C + +#define mmXBAR_EDGE_0_LBW_HBM_BASE_ADDR0 0x4D48030 + +#define mmXBAR_EDGE_0_LBW_HBM_ADDR_MASK0 0x4D48034 + +#define mmXBAR_EDGE_0_LBW_HBM_BASE_ADDR1 0x4D48038 + +#define mmXBAR_EDGE_0_LBW_HBM_ADDR_MASK1 0x4D4803C + +#define mmXBAR_EDGE_0_LBW_XBAR_BASE_ADDR0 0x4D48040 + +#define mmXBAR_EDGE_0_LBW_XBAR_ADDR_MASK0 0x4D48044 + +#define mmXBAR_EDGE_0_LBW_XBAR_BASE_ADDR1 0x4D48048 + +#define mmXBAR_EDGE_0_LBW_XBAR_ADDR_MASK1 0x4D4804C + +#define mmXBAR_EDGE_0_DBG_HIF0_BASE_ADDR 0x4D48080 + +#define mmXBAR_EDGE_0_DBG_HIF0_ADDR_MASK 0x4D48084 + +#define mmXBAR_EDGE_0_DBG_HIF1_BASE_ADDR 0x4D48088 + +#define mmXBAR_EDGE_0_DBG_HIF1_ADDR_MASK 0x4D4808C + +#define mmXBAR_EDGE_0_DBG_HMMU0_BASE_ADDR 0x4D48090 + +#define mmXBAR_EDGE_0_DBG_HMMU0_ADDR_MASK 0x4D48094 + +#define mmXBAR_EDGE_0_DBG_HMMU1_BASE_ADDR 0x4D48098 + +#define mmXBAR_EDGE_0_DBG_HMMU1_ADDR_MASK 0x4D4809C + +#define mmXBAR_EDGE_0_DBG_EDMA_BASE_ADDR0 0x4D480A0 + +#define mmXBAR_EDGE_0_DBG_EDMA_ADDR_MASK0 0x4D480A4 + +#define mmXBAR_EDGE_0_DBG_EDMA_BASE_ADDR1 0x4D480A8 + +#define mmXBAR_EDGE_0_DBG_EDMA_ADDR_MASK1 0x4D480AC + +#define mmXBAR_EDGE_0_DBG_HBM_BASE_ADDR0 0x4D480B0 + +#define mmXBAR_EDGE_0_DBG_HBM_ADDR_MASK0 0x4D480B4 + +#define mmXBAR_EDGE_0_DBG_HBM_BASE_ADDR1 0x4D480B8 + +#define mmXBAR_EDGE_0_DBG_HBM_ADDR_MASK1 0x4D480BC + +#define mmXBAR_EDGE_0_DBG_XBAR_BASE_ADDR0 0x4D480C0 + +#define mmXBAR_EDGE_0_DBG_XBAR_ADDR_MASK0 0x4D480C4 + +#define mmXBAR_EDGE_0_DBG_XBAR_BASE_ADDR1 0x4D480C8 + +#define mmXBAR_EDGE_0_DBG_XBAR_ADDR_MASK1 0x4D480CC + +#define mmXBAR_EDGE_0_LBW_INTERNAL_ADDR_RGF 0x4D480D0 + +#define mmXBAR_EDGE_0_DBG_INTERNAL_ADDR_FUN 0x4D480D4 + +#define mmXBAR_EDGE_0_EMEM_HBM_BIT_LOCATION 0x4D48100 + +#define mmXBAR_EDGE_0_EMEM_PC_BIT_LOCATION 0x4D48104 + +#define mmXBAR_EDGE_0_HIF_WR_RS_CH_LOCATION 0x4D48108 + +#define mmXBAR_EDGE_0_HBW_MST_ARB_WEIGHT 0x4D4810C + +#define mmXBAR_EDGE_0_MMU_PC_IDX_MAP_0 0x4D48110 + +#define mmXBAR_EDGE_0_MMU_PC_IDX_MAP_1 0x4D48114 + +#define mmXBAR_EDGE_0_MMU_RD_LL_ARB_0 0x4D48120 + +#define mmXBAR_EDGE_0_MMU_RD_LL_ARB_1 0x4D48124 + +#define mmXBAR_EDGE_0_MMU_WR_LL_ARB_0 0x4D48128 + +#define mmXBAR_EDGE_0_MMU_WR_LL_ARB_1 0x4D4812C + +#define mmXBAR_EDGE_0_HBM_USER_RESP_OVR_0 0x4D48130 + +#define mmXBAR_EDGE_0_HBM_USER_RESP_OVR_1 0x4D48134 + +#define mmXBAR_EDGE_0_RL_RD_0 0x4D48140 + +#define mmXBAR_EDGE_0_RL_RD_1 0x4D48144 + +#define mmXBAR_EDGE_0_RL_RD_2 0x4D48148 + +#define mmXBAR_EDGE_0_RL_RD_3 0x4D4814C + +#define mmXBAR_EDGE_0_RL_RD_4 0x4D48150 + +#define mmXBAR_EDGE_0_RL_RD_5 0x4D48154 + +#define mmXBAR_EDGE_0_RL_RD_6 0x4D48158 + +#define mmXBAR_EDGE_0_RL_RD_7 0x4D4815C + +#define mmXBAR_EDGE_0_RL_RD_8 0x4D48160 + +#define mmXBAR_EDGE_0_RL_RD_9 0x4D48164 + +#define mmXBAR_EDGE_0_RL_RD_10 0x4D48168 + +#define mmXBAR_EDGE_0_RL_RD_11 0x4D4816C + +#define mmXBAR_EDGE_0_RL_WR_0 0x4D48180 + +#define mmXBAR_EDGE_0_RL_WR_1 0x4D48184 + +#define mmXBAR_EDGE_0_RL_WR_2 0x4D48188 + +#define mmXBAR_EDGE_0_RL_WR_3 0x4D4818C + +#define mmXBAR_EDGE_0_RL_WR_4 0x4D48190 + +#define mmXBAR_EDGE_0_RL_WR_5 0x4D48194 + +#define mmXBAR_EDGE_0_RL_WR_6 0x4D48198 + +#define mmXBAR_EDGE_0_RL_WR_7 0x4D4819C + +#define mmXBAR_EDGE_0_RL_WR_8 0x4D481A0 + +#define mmXBAR_EDGE_0_RL_WR_9 0x4D481A4 + +#define mmXBAR_EDGE_0_RL_WR_10 0x4D481A8 + +#define mmXBAR_EDGE_0_RL_WR_11 0x4D481AC + +#define mmXBAR_EDGE_0_E2E_CRDT_SLV_0 0x4D481B0 + +#define mmXBAR_EDGE_0_E2E_CRDT_SLV_1 0x4D481B4 + +#define mmXBAR_EDGE_0_E2E_CRDT_SLV_2 0x4D481B8 + +#define mmXBAR_EDGE_0_E2E_CRDT_DEBUG 0x4D481BC + +#define mmXBAR_EDGE_0_UPSCALE 0x4D481C0 + +#define mmXBAR_EDGE_0_DOWN_CONV 0x4D481C4 + +#define mmXBAR_EDGE_0_DOWN_CONV_LFSR_EN 0x4D481D0 + +#define mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VLD 0x4D481D4 + +#define mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VALUE 0x4D481D8 + +#define mmXBAR_EDGE_0_DOWN_CONV_LFSR_CFG_POLY 0x4D481DC + +#endif /* ASIC_REG_XBAR_EDGE_0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/xbar_mid_0_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/xbar_mid_0_regs.h new file mode 100644 index 000000000000..3d39d1a94851 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/xbar_mid_0_regs.h @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_XBAR_MID_0_REGS_H_ +#define ASIC_REG_XBAR_MID_0_REGS_H_ + +/* + ***************************************** + * XBAR_MID_0 + * (Prototype: XBAR) + ***************************************** + */ + +#define mmXBAR_MID_0_LBW_HIF0_BASE_ADDR 0x4D40000 + +#define mmXBAR_MID_0_LBW_HIF0_ADDR_MASK 0x4D40004 + +#define mmXBAR_MID_0_LBW_HIF1_BASE_ADDR 0x4D40008 + +#define mmXBAR_MID_0_LBW_HIF1_ADDR_MASK 0x4D4000C + +#define mmXBAR_MID_0_LBW_HMMU0_BASE_ADDR 0x4D40010 + +#define mmXBAR_MID_0_LBW_HMMU0_ADDR_MASK 0x4D40014 + +#define mmXBAR_MID_0_LBW_HMMU1_BASE_ADDR 0x4D40018 + +#define mmXBAR_MID_0_LBW_HMMU1_ADDR_MASK 0x4D4001C + +#define mmXBAR_MID_0_LBW_EDMA_BASE_ADDR0 0x4D40020 + +#define mmXBAR_MID_0_LBW_EDMA_ADDR_MASK0 0x4D40024 + +#define mmXBAR_MID_0_LBW_EDMA_BASE_ADDR1 0x4D40028 + +#define mmXBAR_MID_0_LBW_EDMA_ADDR_MASK1 0x4D4002C + +#define mmXBAR_MID_0_LBW_HBM_BASE_ADDR0 0x4D40030 + +#define mmXBAR_MID_0_LBW_HBM_ADDR_MASK0 0x4D40034 + +#define mmXBAR_MID_0_LBW_HBM_BASE_ADDR1 0x4D40038 + +#define mmXBAR_MID_0_LBW_HBM_ADDR_MASK1 0x4D4003C + +#define mmXBAR_MID_0_LBW_XBAR_BASE_ADDR0 0x4D40040 + +#define mmXBAR_MID_0_LBW_XBAR_ADDR_MASK0 0x4D40044 + +#define mmXBAR_MID_0_LBW_XBAR_BASE_ADDR1 0x4D40048 + +#define mmXBAR_MID_0_LBW_XBAR_ADDR_MASK1 0x4D4004C + +#define mmXBAR_MID_0_DBG_HIF0_BASE_ADDR 0x4D40080 + +#define mmXBAR_MID_0_DBG_HIF0_ADDR_MASK 0x4D40084 + +#define mmXBAR_MID_0_DBG_HIF1_BASE_ADDR 0x4D40088 + +#define mmXBAR_MID_0_DBG_HIF1_ADDR_MASK 0x4D4008C + +#define mmXBAR_MID_0_DBG_HMMU0_BASE_ADDR 0x4D40090 + +#define mmXBAR_MID_0_DBG_HMMU0_ADDR_MASK 0x4D40094 + +#define mmXBAR_MID_0_DBG_HMMU1_BASE_ADDR 0x4D40098 + +#define mmXBAR_MID_0_DBG_HMMU1_ADDR_MASK 0x4D4009C + +#define mmXBAR_MID_0_DBG_EDMA_BASE_ADDR0 0x4D400A0 + +#define mmXBAR_MID_0_DBG_EDMA_ADDR_MASK0 0x4D400A4 + +#define mmXBAR_MID_0_DBG_EDMA_BASE_ADDR1 0x4D400A8 + +#define mmXBAR_MID_0_DBG_EDMA_ADDR_MASK1 0x4D400AC + +#define mmXBAR_MID_0_DBG_HBM_BASE_ADDR0 0x4D400B0 + +#define mmXBAR_MID_0_DBG_HBM_ADDR_MASK0 0x4D400B4 + +#define mmXBAR_MID_0_DBG_HBM_BASE_ADDR1 0x4D400B8 + +#define mmXBAR_MID_0_DBG_HBM_ADDR_MASK1 0x4D400BC + +#define mmXBAR_MID_0_DBG_XBAR_BASE_ADDR0 0x4D400C0 + +#define mmXBAR_MID_0_DBG_XBAR_ADDR_MASK0 0x4D400C4 + +#define mmXBAR_MID_0_DBG_XBAR_BASE_ADDR1 0x4D400C8 + +#define mmXBAR_MID_0_DBG_XBAR_ADDR_MASK1 0x4D400CC + +#define mmXBAR_MID_0_LBW_INTERNAL_ADDR_RGF 0x4D400D0 + +#define mmXBAR_MID_0_DBG_INTERNAL_ADDR_FUN 0x4D400D4 + +#define mmXBAR_MID_0_EMEM_HBM_BIT_LOCATION 0x4D40100 + +#define mmXBAR_MID_0_EMEM_PC_BIT_LOCATION 0x4D40104 + +#define mmXBAR_MID_0_HIF_WR_RS_CH_LOCATION 0x4D40108 + +#define mmXBAR_MID_0_HBW_MST_ARB_WEIGHT 0x4D4010C + +#define mmXBAR_MID_0_MMU_PC_IDX_MAP_0 0x4D40110 + +#define mmXBAR_MID_0_MMU_PC_IDX_MAP_1 0x4D40114 + +#define mmXBAR_MID_0_MMU_RD_LL_ARB_0 0x4D40120 + +#define mmXBAR_MID_0_MMU_RD_LL_ARB_1 0x4D40124 + +#define mmXBAR_MID_0_MMU_WR_LL_ARB_0 0x4D40128 + +#define mmXBAR_MID_0_MMU_WR_LL_ARB_1 0x4D4012C + +#define mmXBAR_MID_0_HBM_USER_RESP_OVR_0 0x4D40130 + +#define mmXBAR_MID_0_HBM_USER_RESP_OVR_1 0x4D40134 + +#define mmXBAR_MID_0_RL_RD_0 0x4D40140 + +#define mmXBAR_MID_0_RL_RD_1 0x4D40144 + +#define mmXBAR_MID_0_RL_RD_2 0x4D40148 + +#define mmXBAR_MID_0_RL_RD_3 0x4D4014C + +#define mmXBAR_MID_0_RL_RD_4 0x4D40150 + +#define mmXBAR_MID_0_RL_RD_5 0x4D40154 + +#define mmXBAR_MID_0_RL_RD_6 0x4D40158 + +#define mmXBAR_MID_0_RL_RD_7 0x4D4015C + +#define mmXBAR_MID_0_RL_RD_8 0x4D40160 + +#define mmXBAR_MID_0_RL_RD_9 0x4D40164 + +#define mmXBAR_MID_0_RL_RD_10 0x4D40168 + +#define mmXBAR_MID_0_RL_RD_11 0x4D4016C + +#define mmXBAR_MID_0_RL_WR_0 0x4D40180 + +#define mmXBAR_MID_0_RL_WR_1 0x4D40184 + +#define mmXBAR_MID_0_RL_WR_2 0x4D40188 + +#define mmXBAR_MID_0_RL_WR_3 0x4D4018C + +#define mmXBAR_MID_0_RL_WR_4 0x4D40190 + +#define mmXBAR_MID_0_RL_WR_5 0x4D40194 + +#define mmXBAR_MID_0_RL_WR_6 0x4D40198 + +#define mmXBAR_MID_0_RL_WR_7 0x4D4019C + +#define mmXBAR_MID_0_RL_WR_8 0x4D401A0 + +#define mmXBAR_MID_0_RL_WR_9 0x4D401A4 + +#define mmXBAR_MID_0_RL_WR_10 0x4D401A8 + +#define mmXBAR_MID_0_RL_WR_11 0x4D401AC + +#define mmXBAR_MID_0_E2E_CRDT_SLV_0 0x4D401B0 + +#define mmXBAR_MID_0_E2E_CRDT_SLV_1 0x4D401B4 + +#define mmXBAR_MID_0_E2E_CRDT_SLV_2 0x4D401B8 + +#define mmXBAR_MID_0_E2E_CRDT_DEBUG 0x4D401BC + +#define mmXBAR_MID_0_UPSCALE 0x4D401C0 + +#define mmXBAR_MID_0_DOWN_CONV 0x4D401C4 + +#define mmXBAR_MID_0_DOWN_CONV_LFSR_EN 0x4D401D0 + +#define mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VLD 0x4D401D4 + +#define mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VALUE 0x4D401D8 + +#define mmXBAR_MID_0_DOWN_CONV_LFSR_CFG_POLY 0x4D401DC + +#endif /* ASIC_REG_XBAR_MID_0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/gaudi2.h b/drivers/misc/habanalabs/include/gaudi2/gaudi2.h new file mode 100644 index 000000000000..5b4f9e108798 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/gaudi2.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2020-2022 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI2_H +#define GAUDI2_H + +#define SRAM_CFG_BAR_ID 0 +#define MSIX_BAR_ID 2 +#define DRAM_BAR_ID 4 + +/* Refers to CFG_REGION_SIZE, BAR0_RSRVD_SIZE and SRAM_SIZE */ +#define CFG_BAR_SIZE 0x10000000ull /* 256MB */ + +#define MSIX_BAR_SIZE 0x4000ull /* 16KB */ + +#define CFG_BASE 0x1000007FF8000000ull +#define CFG_SIZE 0x8000000ull /* 96MB CFG + 32MB DBG*/ +#define CFG_REGION_SIZE 0xC000000ull /* 192MB */ + +#define STM_FLASH_BASE_ADDR 0x1000007FF4000000ull /* Not 256MB aligned */ +#define STM_FLASH_ALIGNED_OFF 0x4000000ull /* 256 MB alignment */ +#define STM_FLASH_SIZE 0x2000000ull /* 32MB */ + +#define SPI_FLASH_BASE_ADDR 0x1000007FF6000000ull +#define SPI_FLASH_SIZE 0x1000000ull /* 16MB */ + +#define SCRATCHPAD_SRAM_ADDR 0x1000007FF7FE0000ull +#define SCRATCHPAD_SRAM_SIZE 0x10000ull /* 64KB */ + +#define PCIE_FW_SRAM_ADDR 0x1000007FF7FF0000ull +#define PCIE_FW_SRAM_SIZE 0x8000 /* 32KB */ + +#define BAR0_RSRVD_BASE_ADDR 0x1000FFFFFC000000ull +#define BAR0_RSRVD_SIZE 0x1000000ull /* 16MB */ + +#define SRAM_BASE_ADDR 0x1000FFFFFD000000ull +#define SRAM_SIZE 0x3000000ull /* 48MB */ + +#define DRAM_PHYS_BASE 0x1001000000000000ull + +/* every hint address is masked accordingly */ +#define DRAM_VA_HINT_MASK 0xFFFFFFFFFFFFull /* 48bit mask */ + +#define HOST_PHYS_BASE_0 0x0000000000000000ull +#define HOST_PHYS_SIZE_0 0x0100000000000000ull /* 64PB (56 bits) */ + +#define HOST_PHYS_BASE_1 0xFF00000000000000ull +#define HOST_PHYS_SIZE_1 0x0100000000000000ull /* 64PB (56 bits) */ + +#define RESERVED_VA_RANGE_FOR_ARC_ON_HBM_START 0x1001500000000000ull +#define RESERVED_VA_RANGE_FOR_ARC_ON_HBM_END 0x10016FFFFFFFFFFFull + +#define RESERVED_VA_FOR_VIRTUAL_MSIX_DOORBELL_START 0xFFF077FFFFFF0000ull +#define RESERVED_VA_FOR_VIRTUAL_MSIX_DOORBELL_END 0xFFF077FFFFFFFFFFull + +#define RESERVED_VA_RANGE_FOR_ARC_ON_HOST_START 0xFFF0780000000000ull +#define RESERVED_VA_RANGE_FOR_ARC_ON_HOST_END 0xFFF07FFFFFFFFFFFull + +#define RESERVED_VA_RANGE_FOR_ARC_ON_HOST_HPAGE_START 0xFFF0F80000000000ull +#define RESERVED_VA_RANGE_FOR_ARC_ON_HOST_HPAGE_END 0xFFF0FFFFFFFFFFFFull + +#define GAUDI2_MSIX_ENTRIES 512 + +#define QMAN_PQ_ENTRY_SIZE 16 /* Bytes */ + +#define MAX_ASID 2 + +#define NUM_ARC_CPUS 69 + +/* Every ARC cpu in the system contains a single DCCM block + * except MME and Scheduler ARCs which contain 2 DCCM blocks + */ +#define ARC_DCCM_BLOCK_SIZE 0x8000 + +#define NUM_OF_DCORES 4 +#define NUM_OF_SFT 4 +#define NUM_OF_PSOC_ARC 2 +#define NUM_OF_SCHEDULER_ARC 6 + +#define NUM_OF_PQ_PER_QMAN 4 +#define NUM_OF_CQ_PER_QMAN 5 +#define NUM_OF_CP_PER_QMAN 5 +#define NUM_OF_EDMA_PER_DCORE 2 +#define NUM_OF_HIF_PER_DCORE 4 +#define NUM_OF_PDMA 2 +#define NUM_OF_TPC_PER_DCORE 6 +#define NUM_DCORE0_TPC 7 +#define NUM_DCORE1_TPC NUM_OF_TPC_PER_DCORE +#define NUM_DCORE2_TPC NUM_OF_TPC_PER_DCORE +#define NUM_DCORE3_TPC NUM_OF_TPC_PER_DCORE +#define NUM_OF_DEC_PER_DCORE 2 +#define NUM_OF_ROT 2 +#define NUM_OF_HMMU_PER_DCORE 4 +#define NUM_OF_MME_PER_DCORE 1 +#define NUM_OF_MME_SBTE_PER_DCORE 5 +#define NUM_OF_MME_WB_PER_DCORE 2 +#define NUM_OF_RTR_PER_DCORE 8 +#define NUM_OF_VDEC_PER_DCORE 2 +#define NUM_OF_IF_RTR_PER_SFT 3 +#define NUM_OF_PCIE_VDEC 2 +#define NUM_OF_ARC_FARMS_ARC 4 +#define NUM_OF_XBAR 4 + +#define TPC_NUM_OF_KERNEL_TENSORS 16 +#define TPC_NUM_OF_QM_TENSORS 16 + +#define MME_NUM_OF_LFSR_SEEDS 256 + +#define NIC_NUMBER_OF_MACROS 12 + +#define NIC_NUMBER_OF_QM_PER_MACRO 2 + +#define NIC_NUMBER_OF_ENGINES (NIC_NUMBER_OF_MACROS * 2) + +#define NIC_MAX_NUMBER_OF_PORTS (NIC_NUMBER_OF_ENGINES * 2) + +#define DEVICE_CACHE_LINE_SIZE 128 + +#endif /* GAUDI2_H */ diff --git a/drivers/misc/habanalabs/include/gaudi2/gaudi2_async_events.h b/drivers/misc/habanalabs/include/gaudi2/gaudi2_async_events.h new file mode 100644 index 000000000000..34406770a76a --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/gaudi2_async_events.h @@ -0,0 +1,963 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2018-2021 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef __GAUDI2_ASYNC_EVENTS_H_ +#define __GAUDI2_ASYNC_EVENTS_H_ + +enum gaudi2_async_event_id { + GAUDI2_EVENT_PCIE_CORE_SERR = 32, + GAUDI2_EVENT_PCIE_CORE_DERR = 33, + GAUDI2_EVENT_PCIE_IF_SERR = 34, + GAUDI2_EVENT_PCIE_IF_DERR = 35, + GAUDI2_EVENT_PCIE_PHY_SERR = 36, + GAUDI2_EVENT_PCIE_PHY_DERR = 37, + GAUDI2_EVENT_TPC0_ECC_SERR = 38, + GAUDI2_EVENT_TPC1_ECC_SERR = 39, + GAUDI2_EVENT_TPC2_ECC_SERR = 40, + GAUDI2_EVENT_TPC3_ECC_SERR = 41, + GAUDI2_EVENT_TPC4_ECC_SERR = 42, + GAUDI2_EVENT_TPC5_ECC_SERR = 43, + GAUDI2_EVENT_TPC6_ECC_SERR = 44, + GAUDI2_EVENT_TPC7_ECC_SERR = 45, + GAUDI2_EVENT_TPC8_ECC_SERR = 46, + GAUDI2_EVENT_TPC9_ECC_SERR = 47, + GAUDI2_EVENT_TPC10_ECC_SERR = 48, + GAUDI2_EVENT_TPC11_ECC_SERR = 49, + GAUDI2_EVENT_TPC12_ECC_SERR = 50, + GAUDI2_EVENT_TPC13_ECC_SERR = 51, + GAUDI2_EVENT_TPC14_ECC_SERR = 52, + GAUDI2_EVENT_TPC15_ECC_SERR = 53, + GAUDI2_EVENT_TPC16_ECC_SERR = 54, + GAUDI2_EVENT_TPC17_ECC_SERR = 55, + GAUDI2_EVENT_TPC18_ECC_SERR = 56, + GAUDI2_EVENT_TPC19_ECC_SERR = 57, + GAUDI2_EVENT_TPC20_ECC_SERR = 58, + GAUDI2_EVENT_TPC21_ECC_SERR = 59, + GAUDI2_EVENT_TPC22_ECC_SERR = 60, + GAUDI2_EVENT_TPC23_ECC_SERR = 61, + GAUDI2_EVENT_TPC24_ECC_SERR = 62, + GAUDI2_EVENT_TPC0_ECC_DERR = 63, + GAUDI2_EVENT_TPC1_ECC_DERR = 64, + GAUDI2_EVENT_TPC2_ECC_DERR = 65, + GAUDI2_EVENT_TPC3_ECC_DERR = 66, + GAUDI2_EVENT_TPC4_ECC_DERR = 67, + GAUDI2_EVENT_TPC5_ECC_DERR = 68, + GAUDI2_EVENT_TPC6_ECC_DERR = 69, + GAUDI2_EVENT_TPC7_ECC_DERR = 70, + GAUDI2_EVENT_TPC8_ECC_DERR = 71, + GAUDI2_EVENT_TPC9_ECC_DERR = 72, + GAUDI2_EVENT_TPC10_ECC_DERR = 73, + GAUDI2_EVENT_TPC11_ECC_DERR = 74, + GAUDI2_EVENT_TPC12_ECC_DERR = 75, + GAUDI2_EVENT_TPC13_ECC_DERR = 76, + GAUDI2_EVENT_TPC14_ECC_DERR = 77, + GAUDI2_EVENT_TPC15_ECC_DERR = 78, + GAUDI2_EVENT_TPC16_ECC_DERR = 79, + GAUDI2_EVENT_TPC17_ECC_DERR = 80, + GAUDI2_EVENT_TPC18_ECC_DERR = 81, + GAUDI2_EVENT_TPC19_ECC_DERR = 82, + GAUDI2_EVENT_TPC20_ECC_DERR = 83, + GAUDI2_EVENT_TPC21_ECC_DERR = 84, + GAUDI2_EVENT_TPC22_ECC_DERR = 85, + GAUDI2_EVENT_TPC23_ECC_DERR = 86, + GAUDI2_EVENT_TPC24_ECC_DERR = 87, + GAUDI2_EVENT_MME0_SBTE0_ECC_SERR = 88, + GAUDI2_EVENT_MME0_SBTE1_ECC_SERR = 89, + GAUDI2_EVENT_MME0_SBTE2_ECC_SERR = 90, + GAUDI2_EVENT_MME0_SBTE3_ECC_SERR = 91, + GAUDI2_EVENT_MME0_SBTE4_ECC_SERR = 92, + GAUDI2_EVENT_MME0_CTRL_ECC_SERR = 93, + GAUDI2_EVENT_MME0_WAP_ECC_SERR = 94, + GAUDI2_EVENT_MME1_SBTE0_ECC_SERR = 95, + GAUDI2_EVENT_MME1_SBTE1_ECC_SERR = 96, + GAUDI2_EVENT_MME1_SBTE2_ECC_SERR = 97, + GAUDI2_EVENT_MME1_SBTE3_ECC_SERR = 98, + GAUDI2_EVENT_MME1_SBTE4_ECC_SERR = 99, + GAUDI2_EVENT_MME1_CTRL_ECC_SERR = 100, + GAUDI2_EVENT_MME1_WAP_ECC_SERR = 101, + GAUDI2_EVENT_MME2_SBTE0_ECC_SERR = 102, + GAUDI2_EVENT_MME2_SBTE1_ECC_SERR = 103, + GAUDI2_EVENT_MME2_SBTE2_ECC_SERR = 104, + GAUDI2_EVENT_MME2_SBTE3_ECC_SERR = 105, + GAUDI2_EVENT_MME2_SBTE4_ECC_SERR = 106, + GAUDI2_EVENT_MME2_CTRL_ECC_SERR = 107, + GAUDI2_EVENT_MME2_WAP_ECC_SERR = 108, + GAUDI2_EVENT_MME3_SBTE0_ECC_SERR = 109, + GAUDI2_EVENT_MME3_SBTE1_ECC_SERR = 110, + GAUDI2_EVENT_MME3_SBTE2_ECC_SERR = 111, + GAUDI2_EVENT_MME3_SBTE3_ECC_SERR = 112, + GAUDI2_EVENT_MME3_SBTE4_ECC_SERR = 113, + GAUDI2_EVENT_MME3_CTRL_ECC_SERR = 114, + GAUDI2_EVENT_MME3_WAP_ECC_SERR = 115, + GAUDI2_EVENT_MME0_SBTE0_ECC_DERR = 116, + GAUDI2_EVENT_MME0_SBTE1_ECC_DERR = 117, + GAUDI2_EVENT_MME0_SBTE2_ECC_DERR = 118, + GAUDI2_EVENT_MME0_SBTE3_ECC_DERR = 119, + GAUDI2_EVENT_MME0_SBTE4_ECC_DERR = 120, + GAUDI2_EVENT_MME0_CTRL_ECC_DERR = 121, + GAUDI2_EVENT_MME0_WAP_ECC_DERR = 122, + GAUDI2_EVENT_MME1_SBTE0_ECC_DERR = 123, + GAUDI2_EVENT_MME1_SBTE1_ECC_DERR = 124, + GAUDI2_EVENT_MME1_SBTE2_ECC_DERR = 125, + GAUDI2_EVENT_MME1_SBTE3_ECC_DERR = 126, + GAUDI2_EVENT_MME1_SBTE4_ECC_DERR = 127, + GAUDI2_EVENT_MME1_CTRL_ECC_DERR = 128, + GAUDI2_EVENT_MME1_WAP_ECC_DERR = 129, + GAUDI2_EVENT_MME2_SBTE0_ECC_DERR = 130, + GAUDI2_EVENT_MME2_SBTE1_ECC_DERR = 131, + GAUDI2_EVENT_MME2_SBTE2_ECC_DERR = 132, + GAUDI2_EVENT_MME2_SBTE3_ECC_DERR = 133, + GAUDI2_EVENT_MME2_SBTE4_ECC_DERR = 134, + GAUDI2_EVENT_MME2_CTRL_ECC_DERR = 135, + GAUDI2_EVENT_MME2_WAP_ECC_DERR = 136, + GAUDI2_EVENT_MME3_SBTE0_ECC_DERR = 137, + GAUDI2_EVENT_MME3_SBTE1_ECC_DERR = 138, + GAUDI2_EVENT_MME3_SBTE2_ECC_DERR = 139, + GAUDI2_EVENT_MME3_SBTE3_ECC_DERR = 140, + GAUDI2_EVENT_MME3_SBTE4_ECC_DERR = 141, + GAUDI2_EVENT_MME3_CTRL_ECC_DERR = 142, + GAUDI2_EVENT_MME3_WAP_ECC_DERR = 143, + GAUDI2_EVENT_HDMA2_ECC_SERR = 144, + GAUDI2_EVENT_HDMA3_ECC_SERR = 145, + GAUDI2_EVENT_HDMA0_ECC_SERR = 146, + GAUDI2_EVENT_HDMA1_ECC_SERR = 147, + GAUDI2_EVENT_HDMA6_ECC_SERR = 148, + GAUDI2_EVENT_HDMA7_ECC_SERR = 149, + GAUDI2_EVENT_HDMA4_ECC_SERR = 150, + GAUDI2_EVENT_HDMA5_ECC_SERR = 151, + GAUDI2_EVENT_HDMA2_ECC_DERR = 152, + GAUDI2_EVENT_HDMA3_ECC_DERR = 153, + GAUDI2_EVENT_HDMA0_ECC_DERR = 154, + GAUDI2_EVENT_HDMA1_ECC_DERR = 155, + GAUDI2_EVENT_HDMA6_ECC_DERR = 156, + GAUDI2_EVENT_HDMA7_ECC_DERR = 157, + GAUDI2_EVENT_HDMA4_ECC_DERR = 158, + GAUDI2_EVENT_HDMA5_ECC_DERR = 159, + GAUDI2_EVENT_KDMA0_ECC_SERR = 160, + GAUDI2_EVENT_PDMA0_ECC_SERR = 161, + GAUDI2_EVENT_PDMA1_ECC_SERR = 162, + GAUDI2_EVENT_KDMA0_ECC_DERR = 163, + GAUDI2_EVENT_PDMA0_ECC_DERR = 164, + GAUDI2_EVENT_PDMA1_ECC_DERR = 165, + GAUDI2_EVENT_CPU_IF_ECC_SERR = 166, + GAUDI2_EVENT_CPU_IF_ECC_DERR = 167, + GAUDI2_EVENT_PSOC_MEM_SERR = 168, + GAUDI2_EVENT_PSOC_MEM_DERR = 169, + GAUDI2_EVENT_SRAM0_ECC_SERR = 170, + GAUDI2_EVENT_SRAM1_ECC_SERR = 171, + GAUDI2_EVENT_SRAM2_ECC_SERR = 172, + GAUDI2_EVENT_SRAM3_ECC_SERR = 173, + GAUDI2_EVENT_SRAM4_ECC_SERR = 174, + GAUDI2_EVENT_SRAM5_ECC_SERR = 175, + GAUDI2_EVENT_SRAM6_ECC_SERR = 176, + GAUDI2_EVENT_SRAM7_ECC_SERR = 177, + GAUDI2_EVENT_SRAM8_ECC_SERR = 178, + GAUDI2_EVENT_SRAM9_ECC_SERR = 179, + GAUDI2_EVENT_SRAM10_ECC_SERR = 180, + GAUDI2_EVENT_SRAM11_ECC_SERR = 181, + GAUDI2_EVENT_SRAM12_ECC_SERR = 182, + GAUDI2_EVENT_SRAM13_ECC_SERR = 183, + GAUDI2_EVENT_SRAM14_ECC_SERR = 184, + GAUDI2_EVENT_SRAM15_ECC_SERR = 185, + GAUDI2_EVENT_SRAM16_ECC_SERR = 186, + GAUDI2_EVENT_SRAM17_ECC_SERR = 187, + GAUDI2_EVENT_SRAM18_ECC_SERR = 188, + GAUDI2_EVENT_SRAM19_ECC_SERR = 189, + GAUDI2_EVENT_SRAM20_ECC_SERR = 190, + GAUDI2_EVENT_SRAM21_ECC_SERR = 191, + GAUDI2_EVENT_SRAM22_ECC_SERR = 192, + GAUDI2_EVENT_SRAM23_ECC_SERR = 193, + GAUDI2_EVENT_SRAM24_ECC_SERR = 194, + GAUDI2_EVENT_SRAM25_ECC_SERR = 195, + GAUDI2_EVENT_SRAM26_ECC_SERR = 196, + GAUDI2_EVENT_SRAM27_ECC_SERR = 197, + GAUDI2_EVENT_SRAM28_ECC_SERR = 198, + GAUDI2_EVENT_SRAM29_ECC_SERR = 199, + GAUDI2_EVENT_SRAM30_ECC_SERR = 200, + GAUDI2_EVENT_SRAM31_ECC_SERR = 201, + GAUDI2_EVENT_SRAM0_ECC_DERR = 202, + GAUDI2_EVENT_SRAM1_ECC_DERR = 203, + GAUDI2_EVENT_SRAM2_ECC_DERR = 204, + GAUDI2_EVENT_SRAM3_ECC_DERR = 205, + GAUDI2_EVENT_SRAM4_ECC_DERR = 206, + GAUDI2_EVENT_SRAM5_ECC_DERR = 207, + GAUDI2_EVENT_SRAM6_ECC_DERR = 208, + GAUDI2_EVENT_SRAM7_ECC_DERR = 209, + GAUDI2_EVENT_SRAM8_ECC_DERR = 210, + GAUDI2_EVENT_SRAM9_ECC_DERR = 211, + GAUDI2_EVENT_SRAM10_ECC_DERR = 212, + GAUDI2_EVENT_SRAM11_ECC_DERR = 213, + GAUDI2_EVENT_SRAM12_ECC_DERR = 214, + GAUDI2_EVENT_SRAM13_ECC_DERR = 215, + GAUDI2_EVENT_SRAM14_ECC_DERR = 216, + GAUDI2_EVENT_SRAM15_ECC_DERR = 217, + GAUDI2_EVENT_SRAM16_ECC_DERR = 218, + GAUDI2_EVENT_SRAM17_ECC_DERR = 219, + GAUDI2_EVENT_SRAM18_ECC_DERR = 220, + GAUDI2_EVENT_SRAM19_ECC_DERR = 221, + GAUDI2_EVENT_SRAM20_ECC_DERR = 222, + GAUDI2_EVENT_SRAM21_ECC_DERR = 223, + GAUDI2_EVENT_SRAM22_ECC_DERR = 224, + GAUDI2_EVENT_SRAM23_ECC_DERR = 225, + GAUDI2_EVENT_SRAM24_ECC_DERR = 226, + GAUDI2_EVENT_SRAM25_ECC_DERR = 227, + GAUDI2_EVENT_SRAM26_ECC_DERR = 228, + GAUDI2_EVENT_SRAM27_ECC_DERR = 229, + GAUDI2_EVENT_SRAM28_ECC_DERR = 230, + GAUDI2_EVENT_SRAM29_ECC_DERR = 231, + GAUDI2_EVENT_SRAM30_ECC_DERR = 232, + GAUDI2_EVENT_SRAM31_ECC_DERR = 233, + GAUDI2_EVENT_CPU_GIC500 = 234, + GAUDI2_EVENT_HBM_0_MC0_ECC_SERR = 235, + GAUDI2_EVENT_HBM_1_MC0_ECC_SERR = 236, + GAUDI2_EVENT_HBM_2_MC0_ECC_SERR = 237, + GAUDI2_EVENT_HBM_3_MC0_ECC_SERR = 238, + GAUDI2_EVENT_HBM_4_MC0_ECC_SERR = 239, + GAUDI2_EVENT_HBM_5_MC0_ECC_SERR = 240, + GAUDI2_EVENT_HBM_0_MC1_ECC_SERR = 241, + GAUDI2_EVENT_HBM_1_MC1_ECC_SERR = 242, + GAUDI2_EVENT_HBM_2_MC1_ECC_SERR = 243, + GAUDI2_EVENT_HBM_3_MC1_ECC_SERR = 244, + GAUDI2_EVENT_HBM_4_MC1_ECC_SERR = 245, + GAUDI2_EVENT_HBM_5_MC1_ECC_SERR = 246, + GAUDI2_EVENT_HBM_0_MC0_ECC_DERR = 247, + GAUDI2_EVENT_HBM_1_MC0_ECC_DERR = 248, + GAUDI2_EVENT_HBM_2_MC0_ECC_DERR = 249, + GAUDI2_EVENT_HBM_3_MC0_ECC_DERR = 250, + GAUDI2_EVENT_HBM_4_MC0_ECC_DERR = 251, + GAUDI2_EVENT_HBM_5_MC0_ECC_DERR = 252, + GAUDI2_EVENT_HBM_0_MC1_ECC_DERR = 253, + GAUDI2_EVENT_HBM_1_MC1_ECC_DERR = 254, + GAUDI2_EVENT_HBM_2_MC1_ECC_DERR = 255, + GAUDI2_EVENT_HBM_3_MC1_ECC_DERR = 256, + GAUDI2_EVENT_HBM_4_MC1_ECC_DERR = 257, + GAUDI2_EVENT_HBM_5_MC1_ECC_DERR = 258, + GAUDI2_EVENT_HMMU_0_ECC_SERR = 259, + GAUDI2_EVENT_HMMU_1_ECC_SERR = 260, + GAUDI2_EVENT_HMMU_2_ECC_SERR = 261, + GAUDI2_EVENT_HMMU_3_ECC_SERR = 262, + GAUDI2_EVENT_HMMU_8_ECC_SERR = 263, + GAUDI2_EVENT_HMMU_9_ECC_SERR = 264, + GAUDI2_EVENT_HMMU_10_ECC_SERR = 265, + GAUDI2_EVENT_HMMU_11_ECC_SERR = 266, + GAUDI2_EVENT_HMMU_7_ECC_SERR = 267, + GAUDI2_EVENT_HMMU_6_ECC_SERR = 268, + GAUDI2_EVENT_HMMU_5_ECC_SERR = 269, + GAUDI2_EVENT_HMMU_4_ECC_SERR = 270, + GAUDI2_EVENT_HMMU_15_ECC_SERR = 271, + GAUDI2_EVENT_HMMU_14_ECC_SERR = 272, + GAUDI2_EVENT_HMMU_13_ECC_SERR = 273, + GAUDI2_EVENT_HMMU_12_ECC_SERR = 274, + GAUDI2_EVENT_HMMU_0_ECC_DERR = 275, + GAUDI2_EVENT_HMMU_1_ECC_DERR = 276, + GAUDI2_EVENT_HMMU_2_ECC_DERR = 277, + GAUDI2_EVENT_HMMU_3_ECC_DERR = 278, + GAUDI2_EVENT_HMMU_8_ECC_DERR = 279, + GAUDI2_EVENT_HMMU_9_ECC_DERR = 280, + GAUDI2_EVENT_HMMU_10_ECC_DERR = 281, + GAUDI2_EVENT_HMMU_11_ECC_DERR = 282, + GAUDI2_EVENT_HMMU_7_ECC_DERR = 283, + GAUDI2_EVENT_HMMU_6_ECC_DERR = 284, + GAUDI2_EVENT_HMMU_5_ECC_DERR = 285, + GAUDI2_EVENT_HMMU_4_ECC_DERR = 286, + GAUDI2_EVENT_HMMU_15_ECC_DERR = 287, + GAUDI2_EVENT_HMMU_14_ECC_DERR = 288, + GAUDI2_EVENT_HMMU_13_ECC_DERR = 289, + GAUDI2_EVENT_HMMU_12_ECC_DERR = 290, + GAUDI2_EVENT_PMMU_ECC_SERR_0 = 291, + GAUDI2_EVENT_PMMU_ECC_DERR_0 = 292, + GAUDI2_EVENT_DEC0_VCD_ECC_SERR = 295, + GAUDI2_EVENT_DEC1_VCD_ECC_SERR = 296, + GAUDI2_EVENT_DEC2_VCD_ECC_SERR = 297, + GAUDI2_EVENT_DEC3_VCD_ECC_SERR = 298, + GAUDI2_EVENT_DEC4_VCD_ECC_SERR = 299, + GAUDI2_EVENT_DEC5_VCD_ECC_SERR = 300, + GAUDI2_EVENT_DEC6_VCD_ECC_SERR = 301, + GAUDI2_EVENT_DEC7_VCD_ECC_SERR = 302, + GAUDI2_EVENT_DEC8_VCD_ECC_SERR = 303, + GAUDI2_EVENT_DEC9_VCD_ECC_SERR = 304, + GAUDI2_EVENT_DEC0_L2C_ECC_SERR = 305, + GAUDI2_EVENT_DEC1_L2C_ECC_SERR = 306, + GAUDI2_EVENT_DEC2_L2C_ECC_SERR = 307, + GAUDI2_EVENT_DEC3_L2C_ECC_SERR = 308, + GAUDI2_EVENT_DEC4_L2C_ECC_SERR = 309, + GAUDI2_EVENT_DEC5_L2C_ECC_SERR = 310, + GAUDI2_EVENT_DEC6_L2C_ECC_SERR = 311, + GAUDI2_EVENT_DEC7_L2C_ECC_SERR = 312, + GAUDI2_EVENT_DEC8_L2C_ECC_SERR = 313, + GAUDI2_EVENT_DEC9_L2C_ECC_SERR = 314, + GAUDI2_EVENT_DEC0_VCD_ECC_DERR = 315, + GAUDI2_EVENT_DEC1_VCD_ECC_DERR = 316, + GAUDI2_EVENT_DEC2_VCD_ECC_DERR = 317, + GAUDI2_EVENT_DEC3_VCD_ECC_DERR = 318, + GAUDI2_EVENT_DEC4_VCD_ECC_DERR = 319, + GAUDI2_EVENT_DEC5_VCD_ECC_DERR = 320, + GAUDI2_EVENT_DEC6_VCD_ECC_DERR = 321, + GAUDI2_EVENT_DEC7_VCD_ECC_DERR = 322, + GAUDI2_EVENT_DEC8_VCD_ECC_DERR = 323, + GAUDI2_EVENT_DEC9_VCD_ECC_DERR = 324, + GAUDI2_EVENT_DEC0_L2C_ECC_DERR = 325, + GAUDI2_EVENT_DEC1_L2C_ECC_DERR = 326, + GAUDI2_EVENT_DEC2_L2C_ECC_DERR = 327, + GAUDI2_EVENT_DEC3_L2C_ECC_DERR = 328, + GAUDI2_EVENT_DEC4_L2C_ECC_DERR = 329, + GAUDI2_EVENT_DEC5_L2C_ECC_DERR = 330, + GAUDI2_EVENT_DEC6_L2C_ECC_DERR = 331, + GAUDI2_EVENT_DEC7_L2C_ECC_DERR = 332, + GAUDI2_EVENT_DEC8_L2C_ECC_DERR = 333, + GAUDI2_EVENT_DEC9_L2C_ECC_DERR = 334, + GAUDI2_EVENT_HIF0_ECC_SERR = 337, + GAUDI2_EVENT_HIF1_ECC_SERR = 338, + GAUDI2_EVENT_HIF2_ECC_SERR = 339, + GAUDI2_EVENT_HIF3_ECC_SERR = 340, + GAUDI2_EVENT_HIF8_ECC_SERR = 341, + GAUDI2_EVENT_HIF9_ECC_SERR = 342, + GAUDI2_EVENT_HIF10_ECC_SERR = 343, + GAUDI2_EVENT_HIF11_ECC_SERR = 344, + GAUDI2_EVENT_HIF7_ECC_SERR = 345, + GAUDI2_EVENT_HIF6_ECC_SERR = 346, + GAUDI2_EVENT_HIF5_ECC_SERR = 347, + GAUDI2_EVENT_HIF4_ECC_SERR = 348, + GAUDI2_EVENT_HIF15_ECC_SERR = 349, + GAUDI2_EVENT_HIF14_ECC_SERR = 350, + GAUDI2_EVENT_HIF13_ECC_SERR = 351, + GAUDI2_EVENT_HIF12_ECC_SERR = 352, + GAUDI2_EVENT_HIF0_ECC_DERR = 353, + GAUDI2_EVENT_HIF1_ECC_DERR = 354, + GAUDI2_EVENT_HIF2_ECC_DERR = 355, + GAUDI2_EVENT_HIF3_ECC_DERR = 356, + GAUDI2_EVENT_HIF8_ECC_DERR = 357, + GAUDI2_EVENT_HIF9_ECC_DERR = 358, + GAUDI2_EVENT_HIF10_ECC_DERR = 359, + GAUDI2_EVENT_HIF11_ECC_DERR = 360, + GAUDI2_EVENT_HIF7_ECC_DERR = 361, + GAUDI2_EVENT_HIF6_ECC_DERR = 362, + GAUDI2_EVENT_HIF5_ECC_DERR = 363, + GAUDI2_EVENT_HIF4_ECC_DERR = 364, + GAUDI2_EVENT_HIF15_ECC_DERR = 365, + GAUDI2_EVENT_HIF14_ECC_DERR = 366, + GAUDI2_EVENT_HIF13_ECC_DERR = 367, + GAUDI2_EVENT_HIF12_ECC_DERR = 368, + GAUDI2_EVENT_NIC0_ECC_SERR = 369, + GAUDI2_EVENT_NIC1_ECC_SERR = 370, + GAUDI2_EVENT_NIC2_ECC_SERR = 371, + GAUDI2_EVENT_NIC3_ECC_SERR = 372, + GAUDI2_EVENT_NIC4_ECC_SERR = 373, + GAUDI2_EVENT_NIC5_ECC_SERR = 374, + GAUDI2_EVENT_NIC6_ECC_SERR = 375, + GAUDI2_EVENT_NIC7_ECC_SERR = 376, + GAUDI2_EVENT_NIC8_ECC_SERR = 377, + GAUDI2_EVENT_NIC9_ECC_SERR = 378, + GAUDI2_EVENT_NIC10_ECC_SERR = 379, + GAUDI2_EVENT_NIC11_ECC_SERR = 380, + GAUDI2_EVENT_NIC0_ECC_DERR = 381, + GAUDI2_EVENT_NIC1_ECC_DERR = 382, + GAUDI2_EVENT_NIC2_ECC_DERR = 383, + GAUDI2_EVENT_NIC3_ECC_DERR = 384, + GAUDI2_EVENT_NIC4_ECC_DERR = 385, + GAUDI2_EVENT_NIC5_ECC_DERR = 386, + GAUDI2_EVENT_NIC6_ECC_DERR = 387, + GAUDI2_EVENT_NIC7_ECC_DERR = 388, + GAUDI2_EVENT_NIC8_ECC_DERR = 389, + GAUDI2_EVENT_NIC9_ECC_DERR = 390, + GAUDI2_EVENT_NIC10_ECC_DERR = 391, + GAUDI2_EVENT_NIC11_ECC_DERR = 392, + GAUDI2_EVENT_SM0_ECC_DERR = 393, + GAUDI2_EVENT_SM1_ECC_DERR = 394, + GAUDI2_EVENT_SM2_ECC_DERR = 395, + GAUDI2_EVENT_SM3_ECC_DERR = 396, + GAUDI2_EVENT_SM0_ECC_SERR = 397, + GAUDI2_EVENT_SM1_ECC_SERR = 398, + GAUDI2_EVENT_SM2_ECC_SERR = 399, + GAUDI2_EVENT_SM3_ECC_SERR = 400, + GAUDI2_EVENT_XBAR0_ECC_SERR = 401, + GAUDI2_EVENT_XBAR1_ECC_SERR = 402, + GAUDI2_EVENT_XBAR2_ECC_SERR = 403, + GAUDI2_EVENT_XBAR3_ECC_SERR = 404, + GAUDI2_EVENT_XBAR0_ECC_DERR = 405, + GAUDI2_EVENT_XBAR1_ECC_DERR = 406, + GAUDI2_EVENT_XBAR2_ECC_DERR = 407, + GAUDI2_EVENT_XBAR3_ECC_DERR = 408, + GAUDI2_EVENT_ARC0_ECC_SERR = 409, + GAUDI2_EVENT_ARC0_ECC_DERR = 410, + GAUDI2_EVENT_PCIE_BME_CLEARD = 411, + GAUDI2_EVENT_PCIE_ADDR_DEC_ERR = 412, + GAUDI2_EVENT_TPC0_AXI_ERR_RSP = 413, + GAUDI2_EVENT_TPC1_AXI_ERR_RSP = 414, + GAUDI2_EVENT_TPC2_AXI_ERR_RSP = 415, + GAUDI2_EVENT_TPC3_AXI_ERR_RSP = 416, + GAUDI2_EVENT_TPC4_AXI_ERR_RSP = 417, + GAUDI2_EVENT_TPC5_AXI_ERR_RSP = 418, + GAUDI2_EVENT_TPC6_AXI_ERR_RSP = 419, + GAUDI2_EVENT_TPC7_AXI_ERR_RSP = 420, + GAUDI2_EVENT_TPC8_AXI_ERR_RSP = 421, + GAUDI2_EVENT_TPC9_AXI_ERR_RSP = 422, + GAUDI2_EVENT_TPC10_AXI_ERR_RSP = 423, + GAUDI2_EVENT_TPC11_AXI_ERR_RSP = 424, + GAUDI2_EVENT_TPC12_AXI_ERR_RSP = 425, + GAUDI2_EVENT_TPC13_AXI_ERR_RSP = 426, + GAUDI2_EVENT_TPC14_AXI_ERR_RSP = 427, + GAUDI2_EVENT_TPC15_AXI_ERR_RSP = 428, + GAUDI2_EVENT_TPC16_AXI_ERR_RSP = 429, + GAUDI2_EVENT_TPC17_AXI_ERR_RSP = 430, + GAUDI2_EVENT_TPC18_AXI_ERR_RSP = 431, + GAUDI2_EVENT_TPC19_AXI_ERR_RSP = 432, + GAUDI2_EVENT_TPC20_AXI_ERR_RSP = 433, + GAUDI2_EVENT_TPC21_AXI_ERR_RSP = 434, + GAUDI2_EVENT_TPC22_AXI_ERR_RSP = 435, + GAUDI2_EVENT_TPC23_AXI_ERR_RSP = 436, + GAUDI2_EVENT_TPC24_AXI_ERR_RSP = 437, + GAUDI2_EVENT_CPU_AXI_ECC = 438, + GAUDI2_EVENT_CPU_L2_RAM_ECC = 439, + GAUDI2_EVENT_MME0_SBTE0_AXI_ERR_RSP = 440, + GAUDI2_EVENT_MME0_SBTE1_AXI_ERR_RSP = 441, + GAUDI2_EVENT_MME0_SBTE2_AXI_ERR_RSP = 442, + GAUDI2_EVENT_MME0_SBTE3_AXI_ERR_RSP = 443, + GAUDI2_EVENT_MME0_SBTE4_AXI_ERR_RSP = 444, + GAUDI2_EVENT_MME0_CTRL_AXI_ERROR_RESPONSE = 445, + GAUDI2_EVENT_MME0_QMAN_SW_ERROR = 446, + GAUDI2_EVENT_MME1_SBTE0_AXI_ERR_RSP = 447, + GAUDI2_EVENT_MME1_SBTE1_AXI_ERR_RSP = 448, + GAUDI2_EVENT_MME1_SBTE2_AXI_ERR_RSP = 449, + GAUDI2_EVENT_MME1_SBTE3_AXI_ERR_RSP = 450, + GAUDI2_EVENT_MME1_SBTE4_AXI_ERR_RSP = 451, + GAUDI2_EVENT_MME1_CTRL_AXI_ERROR_RESPONSE = 452, + GAUDI2_EVENT_MME1_QMAN_SW_ERROR = 453, + GAUDI2_EVENT_MME2_SBTE0_AXI_ERR_RSP = 454, + GAUDI2_EVENT_MME2_SBTE1_AXI_ERR_RSP = 455, + GAUDI2_EVENT_MME2_SBTE2_AXI_ERR_RSP = 456, + GAUDI2_EVENT_MME2_SBTE3_AXI_ERR_RSP = 457, + GAUDI2_EVENT_MME2_SBTE4_AXI_ERR_RSP = 458, + GAUDI2_EVENT_MME2_CTRL_AXI_ERROR_RESPONSE = 459, + GAUDI2_EVENT_MME2_QMAN_SW_ERROR = 460, + GAUDI2_EVENT_MME3_SBTE0_AXI_ERR_RSP = 461, + GAUDI2_EVENT_MME3_SBTE1_AXI_ERR_RSP = 462, + GAUDI2_EVENT_MME3_SBTE2_AXI_ERR_RSP = 463, + GAUDI2_EVENT_MME3_SBTE3_AXI_ERR_RSP = 464, + GAUDI2_EVENT_MME3_SBTE4_AXI_ERR_RSP = 465, + GAUDI2_EVENT_MME3_CTRL_AXI_ERROR_RESPONSE = 466, + GAUDI2_EVENT_MME3_QMAN_SW_ERROR = 467, + GAUDI2_EVENT_PSOC_MME_PLL_LOCK_ERR = 468, + GAUDI2_EVENT_PSOC_CPU_PLL_LOCK_ERR = 469, + GAUDI2_EVENT_DCORE3_TPC_PLL_LOCK_ERR = 470, + GAUDI2_EVENT_DCORE3_NIC_PLL_LOCK_ERR = 471, + GAUDI2_EVENT_DCORE3_XBAR_MMU_PLL_LOCK_ERR = 472, + GAUDI2_EVENT_DCORE3_XBAR_DMA_PLL_LOCK_ERR = 473, + GAUDI2_EVENT_DCORE3_XBAR_IF_PLL_LOCK_ERR = 474, + GAUDI2_EVENT_DCORE3_XBAR_BANK_PLL_LOCK_ERR = 475, + GAUDI2_EVENT_DCORE1_XBAR_MMU_PLL_LOCK_ERR = 476, + GAUDI2_EVENT_DCORE1_XBAR_DMA_PLL_LOCK_ERR = 477, + GAUDI2_EVENT_DCORE1_XBAR_IF_PLL_LOCK_ERR = 478, + GAUDI2_EVENT_DCORE1_XBAR_MESH_PLL_LOCK_ERR = 479, + GAUDI2_EVENT_DCORE1_TPC_PLL_LOCK_ERR = 480, + GAUDI2_EVENT_DCORE1_NIC_PLL_LOCK_ERR = 481, + GAUDI2_EVENT_PMMU_MME_PLL_LOCK_ERR = 482, + GAUDI2_EVENT_DCORE0_TPC_PLL_LOCK_ERR = 483, + GAUDI2_EVENT_DCORE0_PCI_PLL_LOCK_ERR = 484, + GAUDI2_EVENT_DCORE0_XBAR_MMU_PLL_LOCK_ERR = 485, + GAUDI2_EVENT_DCORE0_XBAR_DMA_PLL_LOCK_ERR = 486, + GAUDI2_EVENT_DCORE0_XBAR_IF_PLL_LOCK_ERR = 487, + GAUDI2_EVENT_DCORE0_XBAR_MESH_PLL_LOCK_ERR = 488, + GAUDI2_EVENT_DCORE2_XBAR_MMU_PLL_LOCK_ERR = 489, + GAUDI2_EVENT_DCORE2_XBAR_DMA_PLL_LOCK_ERR = 490, + GAUDI2_EVENT_DCORE2_XBAR_IF_PLL_LOCK_ERR = 491, + GAUDI2_EVENT_DCORE2_XBAR_BANK_PLL_LOCK_ERR = 492, + GAUDI2_EVENT_DCORE2_TPC_PLL_LOCK_ERR = 493, + GAUDI2_EVENT_PSOC_VID_PLL_LOCK_ERR = 494, + GAUDI2_EVENT_PMMU_VID_PLL_LOCK_ERR = 495, + GAUDI2_EVENT_DCORE3_HBM_PLL_LOCK_ERR = 496, + GAUDI2_EVENT_DCORE1_XBAR_HBM_PLL_LOCK_ERR = 497, + GAUDI2_EVENT_DCORE1_HBM_PLL_LOCK_ERR = 498, + GAUDI2_EVENT_DCORE0_HBM_PLL_LOCK_ERR = 499, + GAUDI2_EVENT_DCORE2_XBAR_HBM_PLL_LOCK_ERR = 500, + GAUDI2_EVENT_DCORE2_HBM_PLL_LOCK_ERR = 501, + GAUDI2_EVENT_CPU_AXI_ERR_RSP = 502, + GAUDI2_EVENT_HMMU_0_AXI_ERR_RSP = 503, + GAUDI2_EVENT_HMMU_1_AXI_ERR_RSP = 504, + GAUDI2_EVENT_HMMU_2_AXI_ERR_RSP = 505, + GAUDI2_EVENT_HMMU_3_AXI_ERR_RSP = 506, + GAUDI2_EVENT_HMMU_8_AXI_ERR_RSP = 507, + GAUDI2_EVENT_HMMU_9_AXI_ERR_RSP = 508, + GAUDI2_EVENT_HMMU_10_AXI_ERR_RSP = 509, + GAUDI2_EVENT_HMMU_11_AXI_ERR_RSP = 510, + GAUDI2_EVENT_HMMU_7_AXI_ERR_RSP = 511, + GAUDI2_EVENT_HMMU_6_AXI_ERR_RSP = 512, + GAUDI2_EVENT_HMMU_5_AXI_ERR_RSP = 513, + GAUDI2_EVENT_HMMU_4_AXI_ERR_RSP = 514, + GAUDI2_EVENT_HMMU_15_AXI_ERR_RSP = 515, + GAUDI2_EVENT_HMMU_14_AXI_ERR_RSP = 516, + GAUDI2_EVENT_HMMU_13_AXI_ERR_RSP = 517, + GAUDI2_EVENT_HMMU_12_AXI_ERR_RSP = 518, + GAUDI2_EVENT_PMMU_FATAL_0 = 519, + GAUDI2_EVENT_PMMU_AXI_ERR_RSP_0 = 520, + GAUDI2_EVENT_VM0_ALARM_A = 521, + GAUDI2_EVENT_VM0_ALARM_B = 522, + GAUDI2_EVENT_VM1_ALARM_A = 523, + GAUDI2_EVENT_VM1_ALARM_B = 524, + GAUDI2_EVENT_VM2_ALARM_A = 525, + GAUDI2_EVENT_VM2_ALARM_B = 526, + GAUDI2_EVENT_VM3_ALARM_A = 527, + GAUDI2_EVENT_VM3_ALARM_B = 528, + GAUDI2_EVENT_PSOC_AXI_ERR_RSP = 529, + GAUDI2_EVENT_PSOC_PRSTN_FALL = 530, + GAUDI2_EVENT_KDMA_CH0_AXI_ERR_RSP = 539, + GAUDI2_EVENT_PDMA_CH0_AXI_ERR_RSP = 540, + GAUDI2_EVENT_PDMA_CH1_AXI_ERR_RSP = 541, + GAUDI2_EVENT_HBM_CATTRIP_0 = 542, + GAUDI2_EVENT_HBM_CATTRIP_1 = 543, + GAUDI2_EVENT_HBM_CATTRIP_2 = 544, + GAUDI2_EVENT_HBM_CATTRIP_3 = 545, + GAUDI2_EVENT_HBM_CATTRIP_4 = 546, + GAUDI2_EVENT_HBM_CATTRIP_5 = 547, + GAUDI2_EVENT_HBM0_MC0_SEI_SEVERE = 548, + GAUDI2_EVENT_HBM0_MC0_SEI_NON_SEVERE = 549, + GAUDI2_EVENT_HBM0_MC1_SEI_SEVERE = 550, + GAUDI2_EVENT_HBM0_MC1_SEI_NON_SEVERE = 551, + GAUDI2_EVENT_HBM1_MC0_SEI_SEVERE = 552, + GAUDI2_EVENT_HBM1_MC0_SEI_NON_SEVERE = 553, + GAUDI2_EVENT_HBM1_MC1_SEI_SEVERE = 554, + GAUDI2_EVENT_HBM1_MC1_SEI_NON_SEVERE = 555, + GAUDI2_EVENT_HBM2_MC0_SEI_SEVERE = 556, + GAUDI2_EVENT_HBM2_MC0_SEI_NON_SEVERE = 557, + GAUDI2_EVENT_HBM2_MC1_SEI_SEVERE = 558, + GAUDI2_EVENT_HBM2_MC1_SEI_NON_SEVERE = 559, + GAUDI2_EVENT_HBM3_MC0_SEI_SEVERE = 560, + GAUDI2_EVENT_HBM3_MC0_SEI_NON_SEVERE = 561, + GAUDI2_EVENT_HBM3_MC1_SEI_SEVERE = 562, + GAUDI2_EVENT_HBM3_MC1_SEI_NON_SEVERE = 563, + GAUDI2_EVENT_HBM4_MC0_SEI_SEVERE = 564, + GAUDI2_EVENT_HBM4_MC0_SEI_NON_SEVERE = 565, + GAUDI2_EVENT_HBM4_MC1_SEI_SEVERE = 566, + GAUDI2_EVENT_HBM4_MC1_SEI_NON_SEVERE = 567, + GAUDI2_EVENT_HBM5_MC0_SEI_SEVERE = 568, + GAUDI2_EVENT_HBM5_MC0_SEI_NON_SEVERE = 569, + GAUDI2_EVENT_HBM5_MC1_SEI_SEVERE = 570, + GAUDI2_EVENT_HBM5_MC1_SEI_NON_SEVERE = 571, + GAUDI2_EVENT_DEC0_AXI_ERR_RSPONSE = 572, + GAUDI2_EVENT_DEC1_AXI_ERR_RSPONSE = 573, + GAUDI2_EVENT_DEC2_AXI_ERR_RSPONSE = 574, + GAUDI2_EVENT_DEC3_AXI_ERR_RSPONSE = 575, + GAUDI2_EVENT_DEC4_AXI_ERR_RSPONSE = 576, + GAUDI2_EVENT_DEC5_AXI_ERR_RSPONSE = 577, + GAUDI2_EVENT_DEC6_AXI_ERR_RSPONSE = 578, + GAUDI2_EVENT_DEC7_AXI_ERR_RSPONSE = 579, + GAUDI2_EVENT_DEC8_AXI_ERR_RSPONSE = 580, + GAUDI2_EVENT_DEC9_AXI_ERR_RSPONSE = 581, + GAUDI2_EVENT_HIF0_FATAL = 584, + GAUDI2_EVENT_HIF1_FATAL = 585, + GAUDI2_EVENT_HIF2_FATAL = 586, + GAUDI2_EVENT_HIF3_FATAL = 587, + GAUDI2_EVENT_HIF8_FATAL = 588, + GAUDI2_EVENT_HIF9_FATAL = 589, + GAUDI2_EVENT_HIF10_FATAL = 590, + GAUDI2_EVENT_HIF11_FATAL = 591, + GAUDI2_EVENT_HIF7_FATAL = 592, + GAUDI2_EVENT_HIF6_FATAL = 593, + GAUDI2_EVENT_HIF5_FATAL = 594, + GAUDI2_EVENT_HIF4_FATAL = 595, + GAUDI2_EVENT_HIF15_FATAL = 596, + GAUDI2_EVENT_HIF14_FATAL = 597, + GAUDI2_EVENT_HIF13_FATAL = 598, + GAUDI2_EVENT_HIF12_FATAL = 599, + GAUDI2_EVENT_NIC0_AXI_ERROR_RESPONSE = 600, + GAUDI2_EVENT_NIC1_AXI_ERROR_RESPONSE = 601, + GAUDI2_EVENT_NIC2_AXI_ERROR_RESPONSE = 602, + GAUDI2_EVENT_NIC3_AXI_ERROR_RESPONSE = 603, + GAUDI2_EVENT_NIC4_AXI_ERROR_RESPONSE = 604, + GAUDI2_EVENT_NIC5_AXI_ERROR_RESPONSE = 605, + GAUDI2_EVENT_NIC6_AXI_ERROR_RESPONSE = 606, + GAUDI2_EVENT_NIC7_AXI_ERROR_RESPONSE = 607, + GAUDI2_EVENT_NIC8_AXI_ERROR_RESPONSE = 608, + GAUDI2_EVENT_NIC9_AXI_ERROR_RESPONSE = 609, + GAUDI2_EVENT_NIC10_AXI_ERROR_RESPONSE = 610, + GAUDI2_EVENT_NIC11_AXI_ERROR_RESPONSE = 611, + GAUDI2_EVENT_SM0_AXI_ERROR_RESPONSE = 612, + GAUDI2_EVENT_SM1_AXI_ERROR_RESPONSE = 613, + GAUDI2_EVENT_SM2_AXI_ERROR_RESPONSE = 614, + GAUDI2_EVENT_SM3_AXI_ERROR_RESPONSE = 615, + GAUDI2_EVENT_ARC_AXI_ERROR_RESPONSE_0 = 616, + GAUDI2_EVENT_PCIE_PME_MSG_RECEIVED = 618, + GAUDI2_EVENT_PCIE_FLR_REQUESTED = 619, + GAUDI2_EVENT_PCIE_HOT_RESET_REQ = 620, + GAUDI2_EVENT_PCIE_PERST = 621, + GAUDI2_EVENT_PCIE_APB_TIMEOUT = 622, + GAUDI2_EVENT_PCIE_BM_D_P_WR = 623, + GAUDI2_EVENT_PCIE_BM_D_RD = 624, + GAUDI2_EVENT_PCIE_BM_U_P_WR = 625, + GAUDI2_EVENT_PCIE_BM_U_RD = 626, + GAUDI2_EVENT_PCIE_FATAL_ERR = 627, + GAUDI2_EVENT_PCIE_PERST_FAL = 628, + GAUDI2_EVENT_PCIE_VDM_READY = 629, + GAUDI2_EVENT_PCIE_VDM_ERROR = 630, + GAUDI2_EVENT_PCIE_P2P_MSIX = 631, + GAUDI2_EVENT_PCIE_DRAIN_COMPLETE = 632, + GAUDI2_EVENT_TPC0_BMON_SPMU = 633, + GAUDI2_EVENT_TPC0_KERNEL_ERR = 634, + GAUDI2_EVENT_TPC1_BMON_SPMU = 635, + GAUDI2_EVENT_TPC1_KERNEL_ERR = 636, + GAUDI2_EVENT_TPC2_BMON_SPMU = 637, + GAUDI2_EVENT_TPC2_KERNEL_ERR = 638, + GAUDI2_EVENT_TPC3_BMON_SPMU = 639, + GAUDI2_EVENT_TPC3_KERNEL_ERR = 640, + GAUDI2_EVENT_TPC4_BMON_SPMU = 641, + GAUDI2_EVENT_TPC4_KERNEL_ERR = 642, + GAUDI2_EVENT_TPC5_BMON_SPMU = 643, + GAUDI2_EVENT_TPC5_KERNEL_ERR = 644, + GAUDI2_EVENT_TPC6_BMON_SPMU = 645, + GAUDI2_EVENT_TPC6_KERNEL_ERR = 646, + GAUDI2_EVENT_TPC7_BMON_SPMU = 647, + GAUDI2_EVENT_TPC7_KERNEL_ERR = 648, + GAUDI2_EVENT_TPC8_BMON_SPMU = 649, + GAUDI2_EVENT_TPC8_KERNEL_ERR = 650, + GAUDI2_EVENT_TPC9_BMON_SPMU = 651, + GAUDI2_EVENT_TPC9_KERNEL_ERR = 652, + GAUDI2_EVENT_TPC10_BMON_SPMU = 653, + GAUDI2_EVENT_TPC10_KERNEL_ERR = 654, + GAUDI2_EVENT_TPC11_BMON_SPMU = 655, + GAUDI2_EVENT_TPC11_KERNEL_ERR = 656, + GAUDI2_EVENT_TPC12_BMON_SPMU = 657, + GAUDI2_EVENT_TPC12_KERNEL_ERR = 658, + GAUDI2_EVENT_TPC13_BMON_SPMU = 659, + GAUDI2_EVENT_TPC13_KERNEL_ERR = 660, + GAUDI2_EVENT_TPC14_BMON_SPMU = 661, + GAUDI2_EVENT_TPC14_KERNEL_ERR = 662, + GAUDI2_EVENT_TPC15_BMON_SPMU = 663, + GAUDI2_EVENT_TPC15_KERNEL_ERR = 664, + GAUDI2_EVENT_TPC16_BMON_SPMU = 665, + GAUDI2_EVENT_TPC16_KERNEL_ERR = 666, + GAUDI2_EVENT_TPC17_BMON_SPMU = 667, + GAUDI2_EVENT_TPC17_KERNEL_ERR = 668, + GAUDI2_EVENT_TPC18_BMON_SPMU = 669, + GAUDI2_EVENT_TPC18_KERNEL_ERR = 670, + GAUDI2_EVENT_TPC19_BMON_SPMU = 671, + GAUDI2_EVENT_TPC19_KERNEL_ERR = 672, + GAUDI2_EVENT_TPC20_BMON_SPMU = 673, + GAUDI2_EVENT_TPC20_KERNEL_ERR = 674, + GAUDI2_EVENT_TPC21_BMON_SPMU = 675, + GAUDI2_EVENT_TPC21_KERNEL_ERR = 676, + GAUDI2_EVENT_TPC22_BMON_SPMU = 677, + GAUDI2_EVENT_TPC22_KERNEL_ERR = 678, + GAUDI2_EVENT_TPC23_BMON_SPMU = 679, + GAUDI2_EVENT_TPC23_KERNEL_ERR = 680, + GAUDI2_EVENT_TPC24_BMON_SPMU = 681, + GAUDI2_EVENT_TPC24_KERNEL_ERR = 682, + GAUDI2_EVENT_MME0_SPI_BASE = 683, + GAUDI2_EVENT_MME0_CTRL_BMON_SPMU = 688, + GAUDI2_EVENT_MME0_SBTE_BMON_SPMU = 689, + GAUDI2_EVENT_MME0_WAP_BMON_SPMU = 690, + GAUDI2_EVENT_MME0_WAP_SOURCE_RESULT_INVALID = 691, + GAUDI2_EVENT_MME1_SPI_BASE = 692, + GAUDI2_EVENT_MME1_CTRL_BMON_SPMU = 697, + GAUDI2_EVENT_MME1_SBTE_BMON_SPMU = 698, + GAUDI2_EVENT_MME1_WAP_BMON_SPMU = 699, + GAUDI2_EVENT_MME1_WAP_SOURCE_RESULT_INVALID = 700, + GAUDI2_EVENT_MME2_SPI_BASE = 701, + GAUDI2_EVENT_MME2_CTRL_BMON_SPMU = 706, + GAUDI2_EVENT_MME2_SBTE_BMON_SPMU = 707, + GAUDI2_EVENT_MME2_WAP_BMON_SPMU = 708, + GAUDI2_EVENT_MME2_WAP_SOURCE_RESULT_INVALID = 709, + GAUDI2_EVENT_MME3_SPI_BASE = 710, + GAUDI2_EVENT_MME3_CTRL_BMON_SPMU = 715, + GAUDI2_EVENT_MME3_SBTE_BMON_SPMU = 716, + GAUDI2_EVENT_MME3_WAP_BMON_SPMU = 717, + GAUDI2_EVENT_MME3_WAP_SOURCE_RESULT_INVALID = 718, + GAUDI2_EVENT_HMMU0_SPI_BASE = 719, + GAUDI2_EVENT_HMMU0_PAGE_FAULT_OR_WR_PERM = 720, + GAUDI2_EVENT_HMMU0_SECURITY_ERROR = 721, + GAUDI2_EVENT_HMMU1_SPI_BASE = 722, + GAUDI2_EVENT_HMMU1_PAGE_FAULT_WR_PERM = 723, + GAUDI2_EVENT_HMMU1_SECURITY_ERROR = 724, + GAUDI2_EVENT_HMMU2_SPI_BASE = 725, + GAUDI2_EVENT_HMMU2_PAGE_FAULT_WR_PERM = 726, + GAUDI2_EVENT_HMMU2_SECURITY_ERROR = 727, + GAUDI2_EVENT_HMMU3_SPI_BASE = 728, + GAUDI2_EVENT_HMMU3_PAGE_FAULT_WR_PERM = 729, + GAUDI2_EVENT_HMMU3_SECURITY_ERROR = 730, + GAUDI2_EVENT_HMMU8_SPI_BASE = 731, + GAUDI2_EVENT_HMMU8_PAGE_FAULT_WR_PERM = 732, + GAUDI2_EVENT_HMMU8_SECURITY_ERROR = 733, + GAUDI2_EVENT_HMMU9_SPI_BASE = 734, + GAUDI2_EVENT_HMMU9_PAGE_FAULT_WR_PERM = 735, + GAUDI2_EVENT_HMMU9_SECURITY_ERROR = 736, + GAUDI2_EVENT_HMMU10_SPI_BASE = 737, + GAUDI2_EVENT_HMMU10_PAGE_FAULT_WR_PERM = 738, + GAUDI2_EVENT_HMMU10_SECURITY_ERROR = 739, + GAUDI2_EVENT_HMMU11_SPI_BASE = 740, + GAUDI2_EVENT_HMMU11_PAGE_FAULT_WR_PERM = 741, + GAUDI2_EVENT_HMMU11_SECURITY_ERROR = 742, + GAUDI2_EVENT_HMMU7_SPI_BASE = 743, + GAUDI2_EVENT_HMMU7_PAGE_FAULT_WR_PERM = 744, + GAUDI2_EVENT_HMMU7_SECURITY_ERROR = 745, + GAUDI2_EVENT_HMMU6_SPI_BASE = 746, + GAUDI2_EVENT_HMMU6_PAGE_FAULT_WR_PERM = 747, + GAUDI2_EVENT_HMMU6_SECURITY_ERROR = 748, + GAUDI2_EVENT_HMMU5_SPI_BASE = 749, + GAUDI2_EVENT_HMMU5_PAGE_FAULT_WR_PERM = 750, + GAUDI2_EVENT_HMMU5_SECURITY_ERROR = 751, + GAUDI2_EVENT_HMMU4_SPI_BASE = 752, + GAUDI2_EVENT_HMMU4_PAGE_FAULT_WR_PERM = 753, + GAUDI2_EVENT_HMMU4_SECURITY_ERROR = 754, + GAUDI2_EVENT_HMMU15_SPI_BASE = 755, + GAUDI2_EVENT_HMMU15_PAGE_FAULT_WR_PERM = 756, + GAUDI2_EVENT_HMMU15_SECURITY_ERROR = 757, + GAUDI2_EVENT_HMMU14_SPI_BASE = 758, + GAUDI2_EVENT_HMMU14_PAGE_FAULT_WR_PERM = 759, + GAUDI2_EVENT_HMMU14_SECURITY_ERROR = 760, + GAUDI2_EVENT_HMMU13_SPI_BASE = 761, + GAUDI2_EVENT_HMMU13_PAGE_FAULT_WR_PERM = 762, + GAUDI2_EVENT_HMMU13_SECURITY_ERROR = 763, + GAUDI2_EVENT_HMMU12_SPI_BASE = 764, + GAUDI2_EVENT_HMMU12_PAGE_FAULT_WR_PERM = 765, + GAUDI2_EVENT_HMMU12_SECURITY_ERROR = 766, + GAUDI2_EVENT_PMMU0_PAGE_FAULT_WR_PERM = 768, + GAUDI2_EVENT_PMMU0_SECURITY_ERROR = 769, + GAUDI2_EVENT_HDMA2_BM_SPMU = 770, + GAUDI2_EVENT_HDMA3_BM_SPMU = 772, + GAUDI2_EVENT_HDMA0_BM_SPMU = 774, + GAUDI2_EVENT_HDMA1_BM_SPMU = 776, + GAUDI2_EVENT_HDMA6_BM_SPMU = 778, + GAUDI2_EVENT_HDMA7_BM_SPMU = 780, + GAUDI2_EVENT_HDMA4_BM_SPMU = 782, + GAUDI2_EVENT_HDMA5_BM_SPMU = 784, + GAUDI2_EVENT_KDMA_BM_SPMU = 786, + GAUDI2_EVENT_PDMA0_BM_SPMU = 788, + GAUDI2_EVENT_PDMA1_BM_SPMU = 789, + GAUDI2_EVENT_HBM0_MC0_SPI = 790, + GAUDI2_EVENT_HBM0_MC1_SPI = 791, + GAUDI2_EVENT_HBM1_MC0_SPI = 792, + GAUDI2_EVENT_HBM1_MC1_SPI = 793, + GAUDI2_EVENT_HBM2_MC0_SPI = 794, + GAUDI2_EVENT_HBM2_MC1_SPI = 795, + GAUDI2_EVENT_HBM3_MC0_SPI = 796, + GAUDI2_EVENT_HBM3_MC1_SPI = 797, + GAUDI2_EVENT_HBM4_MC0_SPI = 798, + GAUDI2_EVENT_HBM4_MC1_SPI = 799, + GAUDI2_EVENT_HBM5_MC0_SPI = 800, + GAUDI2_EVENT_HBM5_MC1_SPI = 801, + GAUDI2_EVENT_CPU_BMON = 802, + GAUDI2_EVENT_CPU_BMON_1 = 803, + GAUDI2_EVENT_TS_A_SOUTH_0 = 804, + GAUDI2_EVENT_TS_A_NORTH_1 = 805, + GAUDI2_EVENT_TS_A_EAST_2 = 806, + GAUDI2_EVENT_TS_A_WEST_3 = 807, + GAUDI2_EVENT_PSOC0_GPIO_79_64 = 812, + GAUDI2_EVENT_PSOC1_GPIO_63_48 = 813, + GAUDI2_EVENT_PSOC2_GPIO_47_32 = 814, + GAUDI2_EVENT_PSOC3_GPIO_31_16 = 815, + GAUDI2_EVENT_PSOC4_GPIO_15_0 = 816, + GAUDI2_EVENT_PSOC58_RPM_READY = 870, + GAUDI2_EVENT_PSOC59_RPM_ERROR_OR_DRAIN = 871, + GAUDI2_EVENT_PSOC60_GPIO_95_80 = 872, + GAUDI2_EVENT_PSOC62_QSPI_INTERRUPT = 874, + GAUDI2_EVENT_PSOC63_RAZWI_OR_PID_MIN_MAX_INTERRUPT = 875, + GAUDI2_EVENT_PSOC64_ADC0_INTERRUPT = 876, + GAUDI2_EVENT_PSOC65_PID = 877, + GAUDI2_EVENT_PSOC66_IC_SLV_SMBALERT_DET_INTR = 878, + GAUDI2_EVENT_PSOC75_SVID0_PARITY_ERROR_INTERRUPT = 887, + GAUDI2_EVENT_PSOC76_SVID1_PARITY_ERROR_INTERRUPT = 888, + GAUDI2_EVENT_PSOC77_SVID_PARITY_ERROR_INTERRUPT = 889, + GAUDI2_EVENT_PSOC78_SVID0_READY_INTERRUPT = 890, + GAUDI2_EVENT_PSOC79_SVID1_READY_INTERRUPT = 891, + GAUDI2_EVENT_PSOC80_SVID2_READY_INTERRUPT = 892, + GAUDI2_EVENT_PSOC81_ADC1_INTERRUPT = 893, + GAUDI2_EVENT_PSOC82_SVID_COMBINED_ALERT_INTERRUPT = 894, + GAUDI2_EVENT_PSOC83_SPI_WARE_OUT_ATTACK_OR_ARP = 895, + GAUDI2_EVENT_DEC0_SPI = 896, + GAUDI2_EVENT_DEC0_BMON_SPMU = 897, + GAUDI2_EVENT_DEC1_SPI = 898, + GAUDI2_EVENT_DEC1_BMON_SPMU = 899, + GAUDI2_EVENT_DEC2_SPI = 900, + GAUDI2_EVENT_DEC2_BMON_SPMU = 901, + GAUDI2_EVENT_DEC3_SPI = 902, + GAUDI2_EVENT_DEC3_BMON_SPMU = 903, + GAUDI2_EVENT_DEC4_SPI = 904, + GAUDI2_EVENT_DEC4_BMON_SPMU = 905, + GAUDI2_EVENT_DEC5_SPI = 906, + GAUDI2_EVENT_DEC5_BMON_SPMU = 907, + GAUDI2_EVENT_DEC6_SPI = 908, + GAUDI2_EVENT_DEC6_BMON_SPMU = 909, + GAUDI2_EVENT_DEC7_SPI = 910, + GAUDI2_EVENT_DEC7_BMON_SPMU = 911, + GAUDI2_EVENT_DEC8_SPI = 912, + GAUDI2_EVENT_DEC8_BMON_SPMU = 913, + GAUDI2_EVENT_DEC9_SPI = 914, + GAUDI2_EVENT_DEC9_BMON_SPMU = 915, + GAUDI2_EVENT_HIF0_SPI_WARN = 918, + GAUDI2_EVENT_HIF1_SPI_WARN = 920, + GAUDI2_EVENT_HIF2_SPI_WARN = 922, + GAUDI2_EVENT_HIF3_SPI_WARN = 924, + GAUDI2_EVENT_HIF8_SPI_WARN = 926, + GAUDI2_EVENT_HIF9_SPI_WARN = 928, + GAUDI2_EVENT_HIF10_SPI_WARN = 930, + GAUDI2_EVENT_HIF11_SPI_WARN = 932, + GAUDI2_EVENT_HIF7_SPI_WARN = 934, + GAUDI2_EVENT_HIF6_SPI_WARN = 936, + GAUDI2_EVENT_HIF5_SPI_WARN = 938, + GAUDI2_EVENT_HIF4_SPI_WARN = 940, + GAUDI2_EVENT_HIF15_SPI_WARN = 942, + GAUDI2_EVENT_HIF14_SPI_WARN = 944, + GAUDI2_EVENT_HIF13_SPI_WARN = 946, + GAUDI2_EVENT_HIF12_SPI_WARN = 948, + GAUDI2_EVENT_NIC0_BMON_SPMU = 951, + GAUDI2_EVENT_NIC0_SW_ERROR = 952, + GAUDI2_EVENT_NIC1_BMON_SPMU = 955, + GAUDI2_EVENT_NIC1_SW_ERROR = 956, + GAUDI2_EVENT_NIC2_BMON_SPMU = 959, + GAUDI2_EVENT_NIC2_SW_ERROR = 960, + GAUDI2_EVENT_NIC3_BMON_SPMU = 963, + GAUDI2_EVENT_NIC3_SW_ERROR = 964, + GAUDI2_EVENT_NIC4_BMON_SPMU = 967, + GAUDI2_EVENT_NIC4_SW_ERROR = 968, + GAUDI2_EVENT_NIC5_BMON_SPMU = 971, + GAUDI2_EVENT_NIC5_SW_ERROR = 972, + GAUDI2_EVENT_NIC6_BMON_SPMU = 975, + GAUDI2_EVENT_NIC6_SW_ERROR = 976, + GAUDI2_EVENT_NIC7_BMON_SPMU = 979, + GAUDI2_EVENT_NIC7_SW_ERROR = 980, + GAUDI2_EVENT_NIC8_BMON_SPMU = 983, + GAUDI2_EVENT_NIC8_SW_ERROR = 984, + GAUDI2_EVENT_NIC9_BMON_SPMU = 987, + GAUDI2_EVENT_NIC9_SW_ERROR = 988, + GAUDI2_EVENT_NIC10_BMON_SPMU = 991, + GAUDI2_EVENT_NIC10_SW_ERROR = 992, + GAUDI2_EVENT_NIC11_BMON_SPMU = 995, + GAUDI2_EVENT_NIC11_SW_ERROR = 996, + GAUDI2_EVENT_ROTATOR0_SERR = 1118, + GAUDI2_EVENT_ROTATOR1_SERR = 1119, + GAUDI2_EVENT_ROTATOR0_DERR = 1120, + GAUDI2_EVENT_ROTATOR1_DERR = 1121, + GAUDI2_EVENT_ROTATOR0_AXI_ERROR_RESPONSE = 1122, + GAUDI2_EVENT_ROTATOR1_AXI_ERROR_RESPONSE = 1123, + GAUDI2_EVENT_ROTATOR0_BMON_SPMU = 1126, + GAUDI2_EVENT_ROTATOR1_BMON_SPMU = 1128, + GAUDI2_EVENT_SM0_BMON_SPMU = 1130, + GAUDI2_EVENT_SM1_BMON_SPMU = 1131, + GAUDI2_EVENT_SM2_BMON_SPMU = 1132, + GAUDI2_EVENT_SM3_BMON_SPMU = 1133, + GAUDI2_EVENT_PSOC_DMA_QM = 1174, + GAUDI2_EVENT_TPC0_QM = 1206, + GAUDI2_EVENT_TPC1_QM = 1207, + GAUDI2_EVENT_TPC2_QM = 1208, + GAUDI2_EVENT_TPC3_QM = 1209, + GAUDI2_EVENT_TPC4_QM = 1210, + GAUDI2_EVENT_TPC5_QM = 1211, + GAUDI2_EVENT_TPC6_QM = 1212, + GAUDI2_EVENT_TPC7_QM = 1213, + GAUDI2_EVENT_TPC8_QM = 1214, + GAUDI2_EVENT_TPC9_QM = 1215, + GAUDI2_EVENT_TPC10_QM = 1216, + GAUDI2_EVENT_TPC11_QM = 1217, + GAUDI2_EVENT_TPC12_QM = 1218, + GAUDI2_EVENT_TPC13_QM = 1219, + GAUDI2_EVENT_TPC14_QM = 1220, + GAUDI2_EVENT_TPC15_QM = 1221, + GAUDI2_EVENT_TPC16_QM = 1222, + GAUDI2_EVENT_TPC17_QM = 1223, + GAUDI2_EVENT_TPC18_QM = 1224, + GAUDI2_EVENT_TPC19_QM = 1225, + GAUDI2_EVENT_TPC20_QM = 1226, + GAUDI2_EVENT_TPC21_QM = 1227, + GAUDI2_EVENT_TPC22_QM = 1228, + GAUDI2_EVENT_TPC23_QM = 1229, + GAUDI2_EVENT_TPC24_QM = 1230, + GAUDI2_EVENT_MME0_QM = 1232, + GAUDI2_EVENT_MME1_QM = 1233, + GAUDI2_EVENT_MME2_QM = 1234, + GAUDI2_EVENT_MME3_QM = 1235, + GAUDI2_EVENT_HDMA2_QM = 1236, + GAUDI2_EVENT_HDMA3_QM = 1237, + GAUDI2_EVENT_HDMA0_QM = 1238, + GAUDI2_EVENT_HDMA1_QM = 1239, + GAUDI2_EVENT_HDMA6_QM = 1240, + GAUDI2_EVENT_HDMA7_QM = 1241, + GAUDI2_EVENT_HDMA4_QM = 1242, + GAUDI2_EVENT_HDMA5_QM = 1243, + GAUDI2_EVENT_PDMA0_QM = 1244, + GAUDI2_EVENT_PDMA1_QM = 1245, + GAUDI2_EVENT_CPU_PI_UPDATE = 1246, + GAUDI2_EVENT_CPU_HALT_MACHINE = 1247, + GAUDI2_EVENT_CPU_INTS_REGISTER = 1248, + GAUDI2_EVENT_ROTATOR0_ROT0_QM = 1249, + GAUDI2_EVENT_ROTATOR1_ROT1_QM = 1250, + GAUDI2_EVENT_CPU_SOFT_RESET = 1251, + GAUDI2_EVENT_CPU_CPLD_SHUTDOWN_CAUSE = 1252, + GAUDI2_EVENT_CPU_FIX_POWER_ENV_S = 1253, + GAUDI2_EVENT_CPU_FIX_POWER_ENV_E = 1254, + GAUDI2_EVENT_CPU_FIX_THERMAL_ENV_S = 1255, + GAUDI2_EVENT_CPU_FIX_THERMAL_ENV_E = 1256, + GAUDI2_EVENT_CPU_CPLD_SHUTDOWN_EVENT = 1257, + GAUDI2_EVENT_CPU_PKT_QUEUE_OUT_SYNC = 1258, + GAUDI2_EVENT_HDMA2_CORE = 1259, + GAUDI2_EVENT_HDMA3_CORE = 1260, + GAUDI2_EVENT_HDMA0_CORE = 1261, + GAUDI2_EVENT_HDMA1_CORE = 1262, + GAUDI2_EVENT_HDMA6_CORE = 1263, + GAUDI2_EVENT_HDMA7_CORE = 1264, + GAUDI2_EVENT_HDMA4_CORE = 1265, + GAUDI2_EVENT_HDMA5_CORE = 1266, + GAUDI2_EVENT_PDMA0_CORE = 1267, + GAUDI2_EVENT_PDMA1_CORE = 1268, + GAUDI2_EVENT_KDMA0_CORE = 1269, + GAUDI2_EVENT_NIC0_QM0 = 1270, + GAUDI2_EVENT_NIC0_QM1 = 1271, + GAUDI2_EVENT_NIC1_QM0 = 1272, + GAUDI2_EVENT_NIC1_QM1 = 1273, + GAUDI2_EVENT_NIC2_QM0 = 1274, + GAUDI2_EVENT_NIC2_QM1 = 1275, + GAUDI2_EVENT_NIC3_QM0 = 1276, + GAUDI2_EVENT_NIC3_QM1 = 1277, + GAUDI2_EVENT_NIC4_QM0 = 1278, + GAUDI2_EVENT_NIC4_QM1 = 1279, + GAUDI2_EVENT_NIC5_QM0 = 1280, + GAUDI2_EVENT_NIC5_QM1 = 1281, + GAUDI2_EVENT_NIC6_QM0 = 1282, + GAUDI2_EVENT_NIC6_QM1 = 1283, + GAUDI2_EVENT_NIC7_QM0 = 1284, + GAUDI2_EVENT_NIC7_QM1 = 1285, + GAUDI2_EVENT_NIC8_QM0 = 1286, + GAUDI2_EVENT_NIC8_QM1 = 1287, + GAUDI2_EVENT_NIC9_QM0 = 1288, + GAUDI2_EVENT_NIC9_QM1 = 1289, + GAUDI2_EVENT_NIC10_QM0 = 1290, + GAUDI2_EVENT_NIC10_QM1 = 1291, + GAUDI2_EVENT_NIC11_QM0 = 1292, + GAUDI2_EVENT_NIC11_QM1 = 1293, + GAUDI2_EVENT_CPU_PKT_SANITY_FAILED = 1294, + GAUDI2_EVENT_CPU0_STATUS_NIC0_ENG0 = 1295, + GAUDI2_EVENT_CPU0_STATUS_NIC0_ENG1 = 1296, + GAUDI2_EVENT_CPU1_STATUS_NIC1_ENG0 = 1297, + GAUDI2_EVENT_CPU1_STATUS_NIC1_ENG1 = 1298, + GAUDI2_EVENT_CPU2_STATUS_NIC2_ENG0 = 1299, + GAUDI2_EVENT_CPU2_STATUS_NIC2_ENG1 = 1300, + GAUDI2_EVENT_CPU3_STATUS_NIC3_ENG0 = 1301, + GAUDI2_EVENT_CPU3_STATUS_NIC3_ENG1 = 1302, + GAUDI2_EVENT_CPU4_STATUS_NIC4_ENG0 = 1303, + GAUDI2_EVENT_CPU4_STATUS_NIC4_ENG1 = 1304, + GAUDI2_EVENT_CPU5_STATUS_NIC5_ENG0 = 1305, + GAUDI2_EVENT_CPU5_STATUS_NIC5_ENG1 = 1306, + GAUDI2_EVENT_CPU6_STATUS_NIC6_ENG0 = 1307, + GAUDI2_EVENT_CPU6_STATUS_NIC6_ENG1 = 1308, + GAUDI2_EVENT_CPU7_STATUS_NIC7_ENG0 = 1309, + GAUDI2_EVENT_CPU7_STATUS_NIC7_ENG1 = 1310, + GAUDI2_EVENT_CPU8_STATUS_NIC8_ENG0 = 1311, + GAUDI2_EVENT_CPU8_STATUS_NIC8_ENG1 = 1312, + GAUDI2_EVENT_CPU9_STATUS_NIC9_ENG0 = 1313, + GAUDI2_EVENT_CPU9_STATUS_NIC9_ENG1 = 1314, + GAUDI2_EVENT_CPU10_STATUS_NIC10_ENG0 = 1315, + GAUDI2_EVENT_CPU10_STATUS_NIC10_ENG1 = 1316, + GAUDI2_EVENT_CPU11_STATUS_NIC11_ENG0 = 1317, + GAUDI2_EVENT_CPU11_STATUS_NIC11_ENG1 = 1318, + GAUDI2_EVENT_ARC_DCCM_FULL = 1319, + GAUDI2_EVENT_SIZE, +}; + +#endif /* __GAUDI2_ASYNC_EVENTS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/gaudi2_async_ids_map_extended.h b/drivers/misc/habanalabs/include/gaudi2/gaudi2_async_ids_map_extended.h new file mode 100644 index 000000000000..5bd4383c9f2c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/gaudi2_async_ids_map_extended.h @@ -0,0 +1,2668 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2018-2021 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef __GAUDI2_ASYNC_IDS_MAP_EVENTS_EXT_H_ +#define __GAUDI2_ASYNC_IDS_MAP_EVENTS_EXT_H_ + +struct gaudi2_async_events_ids_map { + int fc_id; + int cpu_id; + int valid; + int msg; + int reset; + char name[64]; +}; + +static struct gaudi2_async_events_ids_map gaudi2_irq_map_table[] = { + { .fc_id = 0, .cpu_id = 0, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1, .cpu_id = 1, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 2, .cpu_id = 2, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 3, .cpu_id = 3, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 4, .cpu_id = 4, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 5, .cpu_id = 5, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 6, .cpu_id = 6, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 7, .cpu_id = 7, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 8, .cpu_id = 8, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 9, .cpu_id = 9, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 10, .cpu_id = 10, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 11, .cpu_id = 11, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 12, .cpu_id = 12, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 13, .cpu_id = 13, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 14, .cpu_id = 14, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 15, .cpu_id = 15, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 16, .cpu_id = 16, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 17, .cpu_id = 17, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 18, .cpu_id = 18, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 19, .cpu_id = 19, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 20, .cpu_id = 20, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 21, .cpu_id = 21, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 22, .cpu_id = 22, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 23, .cpu_id = 23, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 24, .cpu_id = 24, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 25, .cpu_id = 25, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 26, .cpu_id = 26, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 27, .cpu_id = 27, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 28, .cpu_id = 28, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 29, .cpu_id = 29, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 30, .cpu_id = 30, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 31, .cpu_id = 31, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 32, .cpu_id = 32, .valid = 1, + .msg = 0, .reset = 0, .name = "PCIE_CORE_SERR" }, + { .fc_id = 33, .cpu_id = 33, .valid = 1, + .msg = 0, .reset = 1, .name = "PCIE_CORE_DERR" }, + { .fc_id = 34, .cpu_id = 34, .valid = 1, + .msg = 0, .reset = 0, .name = "PCIE_IF_SERR" }, + { .fc_id = 35, .cpu_id = 35, .valid = 1, + .msg = 0, .reset = 1, .name = "PCIE_IF_DERR" }, + { .fc_id = 36, .cpu_id = 36, .valid = 1, + .msg = 0, .reset = 0, .name = "PCIE_PHY_SERR" }, + { .fc_id = 37, .cpu_id = 37, .valid = 1, + .msg = 0, .reset = 1, .name = "PCIE_PHY_DERR" }, + { .fc_id = 38, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC0_ECC_SERR" }, + { .fc_id = 39, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC1_ECC_SERR" }, + { .fc_id = 40, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC2_ECC_SERR" }, + { .fc_id = 41, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC3_ECC_SERR" }, + { .fc_id = 42, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC4_ECC_SERR" }, + { .fc_id = 43, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC5_ECC_SERR" }, + { .fc_id = 44, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC6_ECC_SERR" }, + { .fc_id = 45, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC7_ECC_SERR" }, + { .fc_id = 46, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC8_ECC_SERR" }, + { .fc_id = 47, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC9_ECC_SERR" }, + { .fc_id = 48, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC10_ECC_SERR" }, + { .fc_id = 49, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC11_ECC_SERR" }, + { .fc_id = 50, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC12_ECC_SERR" }, + { .fc_id = 51, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC13_ECC_SERR" }, + { .fc_id = 52, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC14_ECC_SERR" }, + { .fc_id = 53, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC15_ECC_SERR" }, + { .fc_id = 54, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC16_ECC_SERR" }, + { .fc_id = 55, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC17_ECC_SERR" }, + { .fc_id = 56, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC18_ECC_SERR" }, + { .fc_id = 57, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC19_ECC_SERR" }, + { .fc_id = 58, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC20_ECC_SERR" }, + { .fc_id = 59, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC21_ECC_SERR" }, + { .fc_id = 60, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC22_ECC_SERR" }, + { .fc_id = 61, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC23_ECC_SERR" }, + { .fc_id = 62, .cpu_id = 38, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC24_ECC_SERR" }, + { .fc_id = 63, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC0_ECC_DERR" }, + { .fc_id = 64, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC1_ECC_DERR" }, + { .fc_id = 65, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC2_ECC_DERR" }, + { .fc_id = 66, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC3_ECC_DERR" }, + { .fc_id = 67, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC4_ECC_DERR" }, + { .fc_id = 68, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC5_ECC_DERR" }, + { .fc_id = 69, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC6_ECC_DERR" }, + { .fc_id = 70, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC7_ECC_DERR" }, + { .fc_id = 71, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC8_ECC_DERR" }, + { .fc_id = 72, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC9_ECC_DERR" }, + { .fc_id = 73, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC10_ECC_DERR" }, + { .fc_id = 74, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC11_ECC_DERR" }, + { .fc_id = 75, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC12_ECC_DERR" }, + { .fc_id = 76, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC13_ECC_DERR" }, + { .fc_id = 77, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC14_ECC_DERR" }, + { .fc_id = 78, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC15_ECC_DERR" }, + { .fc_id = 79, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC16_ECC_DERR" }, + { .fc_id = 80, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC17_ECC_DERR" }, + { .fc_id = 81, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC18_ECC_DERR" }, + { .fc_id = 82, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC19_ECC_DERR" }, + { .fc_id = 83, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC20_ECC_DERR" }, + { .fc_id = 84, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC21_ECC_DERR" }, + { .fc_id = 85, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC22_ECC_DERR" }, + { .fc_id = 86, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC23_ECC_DERR" }, + { .fc_id = 87, .cpu_id = 39, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC24_ECC_DERR" }, + { .fc_id = 88, .cpu_id = 40, .valid = 1, + .msg = 0, .reset = 0, .name = "MME0_SBTE0_ECC_SERR" }, + { .fc_id = 89, .cpu_id = 40, .valid = 1, + .msg = 0, .reset = 0, .name = "MME0_SBTE1_ECC_SERR" }, + { .fc_id = 90, .cpu_id = 40, .valid = 1, + .msg = 0, .reset = 0, .name = "MME0_SBTE2_ECC_SERR" }, + { .fc_id = 91, .cpu_id = 40, .valid = 1, + .msg = 0, .reset = 0, .name = "MME0_SBTE3_ECC_SERR" }, + { .fc_id = 92, .cpu_id = 40, .valid = 1, + .msg = 0, .reset = 0, .name = "MME0_SBTE4_ECC_SERR" }, + { .fc_id = 93, .cpu_id = 40, .valid = 1, + .msg = 0, .reset = 0, .name = "MME0_CTRL_ECC_SERR" }, + { .fc_id = 94, .cpu_id = 40, .valid = 1, + .msg = 0, .reset = 0, .name = "MME0_WAP_ECC_SERR" }, + { .fc_id = 95, .cpu_id = 41, .valid = 1, + .msg = 0, .reset = 0, .name = "MME1_SBTE0_ECC_SERR" }, + { .fc_id = 96, .cpu_id = 41, .valid = 1, + .msg = 0, .reset = 0, .name = "MME1_SBTE1_ECC_SERR" }, + { .fc_id = 97, .cpu_id = 41, .valid = 1, + .msg = 0, .reset = 0, .name = "MME1_SBTE2_ECC_SERR" }, + { .fc_id = 98, .cpu_id = 41, .valid = 1, + .msg = 0, .reset = 0, .name = "MME1_SBTE3_ECC_SERR" }, + { .fc_id = 99, .cpu_id = 41, .valid = 1, + .msg = 0, .reset = 0, .name = "MME1_SBTE4_ECC_SERR" }, + { .fc_id = 100, .cpu_id = 41, .valid = 1, + .msg = 0, .reset = 0, .name = "MME1_CTRL_ECC_SERR" }, + { .fc_id = 101, .cpu_id = 41, .valid = 1, + .msg = 0, .reset = 0, .name = "MME1_WAP_ECC_SERR" }, + { .fc_id = 102, .cpu_id = 42, .valid = 1, + .msg = 0, .reset = 0, .name = "MME2_SBTE0_ECC_SERR" }, + { .fc_id = 103, .cpu_id = 42, .valid = 1, + .msg = 0, .reset = 0, .name = "MME2_SBTE1_ECC_SERR" }, + { .fc_id = 104, .cpu_id = 42, .valid = 1, + .msg = 0, .reset = 0, .name = "MME2_SBTE2_ECC_SERR" }, + { .fc_id = 105, .cpu_id = 42, .valid = 1, + .msg = 0, .reset = 0, .name = "MME2_SBTE3_ECC_SERR" }, + { .fc_id = 106, .cpu_id = 42, .valid = 1, + .msg = 0, .reset = 0, .name = "MME2_SBTE4_ECC_SERR" }, + { .fc_id = 107, .cpu_id = 42, .valid = 1, + .msg = 0, .reset = 0, .name = "MME2_CTRL_ECC_SERR" }, + { .fc_id = 108, .cpu_id = 42, .valid = 1, + .msg = 0, .reset = 0, .name = "MME2_WAP_ECC_SERR" }, + { .fc_id = 109, .cpu_id = 43, .valid = 1, + .msg = 0, .reset = 0, .name = "MME3_SBTE0_ECC_SERR" }, + { .fc_id = 110, .cpu_id = 43, .valid = 1, + .msg = 0, .reset = 0, .name = "MME3_SBTE1_ECC_SERR" }, + { .fc_id = 111, .cpu_id = 43, .valid = 1, + .msg = 0, .reset = 0, .name = "MME3_SBTE2_ECC_SERR" }, + { .fc_id = 112, .cpu_id = 43, .valid = 1, + .msg = 0, .reset = 0, .name = "MME3_SBTE3_ECC_SERR" }, + { .fc_id = 113, .cpu_id = 43, .valid = 1, + .msg = 0, .reset = 0, .name = "MME3_SBTE4_ECC_SERR" }, + { .fc_id = 114, .cpu_id = 43, .valid = 1, + .msg = 0, .reset = 0, .name = "MME3_CTRL_ECC_SERR" }, + { .fc_id = 115, .cpu_id = 43, .valid = 1, + .msg = 0, .reset = 0, .name = "MME3_WAP_ECC_SERR" }, + { .fc_id = 116, .cpu_id = 44, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_SBTE0_ECC_DERR" }, + { .fc_id = 117, .cpu_id = 44, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_SBTE1_ECC_DERR" }, + { .fc_id = 118, .cpu_id = 44, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_SBTE2_ECC_DERR" }, + { .fc_id = 119, .cpu_id = 44, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_SBTE3_ECC_DERR" }, + { .fc_id = 120, .cpu_id = 44, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_SBTE4_ECC_DERR" }, + { .fc_id = 121, .cpu_id = 44, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_CTRL_ECC_DERR" }, + { .fc_id = 122, .cpu_id = 44, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_WAP_ECC_DERR" }, + { .fc_id = 123, .cpu_id = 45, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_SBTE0_ECC_DERR" }, + { .fc_id = 124, .cpu_id = 45, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_SBTE1_ECC_DERR" }, + { .fc_id = 125, .cpu_id = 45, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_SBTE2_ECC_DERR" }, + { .fc_id = 126, .cpu_id = 45, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_SBTE3_ECC_DERR" }, + { .fc_id = 127, .cpu_id = 45, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_SBTE4_ECC_DERR" }, + { .fc_id = 128, .cpu_id = 45, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_CTRL_ECC_DERR" }, + { .fc_id = 129, .cpu_id = 45, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_WAP_ECC_DERR" }, + { .fc_id = 130, .cpu_id = 46, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_SBTE0_ECC_DERR" }, + { .fc_id = 131, .cpu_id = 46, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_SBTE1_ECC_DERR" }, + { .fc_id = 132, .cpu_id = 46, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_SBTE2_ECC_DERR" }, + { .fc_id = 133, .cpu_id = 46, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_SBTE3_ECC_DERR" }, + { .fc_id = 134, .cpu_id = 46, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_SBTE4_ECC_DERR" }, + { .fc_id = 135, .cpu_id = 46, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_CTRL_ECC_DERR" }, + { .fc_id = 136, .cpu_id = 46, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_WAP_ECC_DERR" }, + { .fc_id = 137, .cpu_id = 47, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_SBTE0_ECC_DERR" }, + { .fc_id = 138, .cpu_id = 47, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_SBTE1_ECC_DERR" }, + { .fc_id = 139, .cpu_id = 47, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_SBTE2_ECC_DERR" }, + { .fc_id = 140, .cpu_id = 47, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_SBTE3_ECC_DERR" }, + { .fc_id = 141, .cpu_id = 47, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_SBTE4_ECC_DERR" }, + { .fc_id = 142, .cpu_id = 47, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_CTRL_ECC_DERR" }, + { .fc_id = 143, .cpu_id = 47, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_WAP_ECC_DERR" }, + { .fc_id = 144, .cpu_id = 48, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA2_ECC_SERR" }, + { .fc_id = 145, .cpu_id = 48, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA3_ECC_SERR" }, + { .fc_id = 146, .cpu_id = 48, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA0_ECC_SERR" }, + { .fc_id = 147, .cpu_id = 48, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA1_ECC_SERR" }, + { .fc_id = 148, .cpu_id = 48, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA6_ECC_SERR" }, + { .fc_id = 149, .cpu_id = 48, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA7_ECC_SERR" }, + { .fc_id = 150, .cpu_id = 48, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA4_ECC_SERR" }, + { .fc_id = 151, .cpu_id = 48, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA5_ECC_SERR" }, + { .fc_id = 152, .cpu_id = 49, .valid = 1, + .msg = 0, .reset = 1, .name = "HDMA2_ECC_DERR" }, + { .fc_id = 153, .cpu_id = 49, .valid = 1, + .msg = 0, .reset = 1, .name = "HDMA3_ECC_DERR" }, + { .fc_id = 154, .cpu_id = 49, .valid = 1, + .msg = 0, .reset = 1, .name = "HDMA0_ECC_DERR" }, + { .fc_id = 155, .cpu_id = 49, .valid = 1, + .msg = 0, .reset = 1, .name = "HDMA1_ECC_DERR" }, + { .fc_id = 156, .cpu_id = 49, .valid = 1, + .msg = 0, .reset = 1, .name = "HDMA6_ECC_DERR" }, + { .fc_id = 157, .cpu_id = 49, .valid = 1, + .msg = 0, .reset = 1, .name = "HDMA7_ECC_DERR" }, + { .fc_id = 158, .cpu_id = 49, .valid = 1, + .msg = 0, .reset = 1, .name = "HDMA4_ECC_DERR" }, + { .fc_id = 159, .cpu_id = 49, .valid = 1, + .msg = 0, .reset = 1, .name = "HDMA5_ECC_DERR" }, + { .fc_id = 160, .cpu_id = 50, .valid = 1, + .msg = 0, .reset = 0, .name = "KDMA0_ECC_SERR" }, + { .fc_id = 161, .cpu_id = 51, .valid = 1, + .msg = 0, .reset = 0, .name = "PDMA0_ECC_SERR" }, + { .fc_id = 162, .cpu_id = 51, .valid = 1, + .msg = 0, .reset = 0, .name = "PDMA1_ECC_SERR" }, + { .fc_id = 163, .cpu_id = 52, .valid = 1, + .msg = 0, .reset = 1, .name = "KDMA0_ECC_DERR" }, + { .fc_id = 164, .cpu_id = 53, .valid = 1, + .msg = 0, .reset = 1, .name = "PDMA0_ECC_DERR" }, + { .fc_id = 165, .cpu_id = 53, .valid = 1, + .msg = 0, .reset = 1, .name = "PDMA1_ECC_DERR" }, + { .fc_id = 166, .cpu_id = 54, .valid = 1, + .msg = 0, .reset = 0, .name = "CPU_IF_ECC_SERR" }, + { .fc_id = 167, .cpu_id = 55, .valid = 1, + .msg = 0, .reset = 1, .name = "CPU_IF_ECC_DERR" }, + { .fc_id = 168, .cpu_id = 56, .valid = 1, + .msg = 0, .reset = 0, .name = "PSOC_MEM_SERR" }, + { .fc_id = 169, .cpu_id = 57, .valid = 1, + .msg = 0, .reset = 1, .name = "PSOC_MEM_DERR" }, + { .fc_id = 170, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM0_ECC_SERR" }, + { .fc_id = 171, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM1_ECC_SERR" }, + { .fc_id = 172, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM2_ECC_SERR" }, + { .fc_id = 173, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM3_ECC_SERR" }, + { .fc_id = 174, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM4_ECC_SERR" }, + { .fc_id = 175, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM5_ECC_SERR" }, + { .fc_id = 176, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM6_ECC_SERR" }, + { .fc_id = 177, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM7_ECC_SERR" }, + { .fc_id = 178, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM8_ECC_SERR" }, + { .fc_id = 179, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM9_ECC_SERR" }, + { .fc_id = 180, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM10_ECC_SERR" }, + { .fc_id = 181, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM11_ECC_SERR" }, + { .fc_id = 182, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM12_ECC_SERR" }, + { .fc_id = 183, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM13_ECC_SERR" }, + { .fc_id = 184, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM14_ECC_SERR" }, + { .fc_id = 185, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM15_ECC_SERR" }, + { .fc_id = 186, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM16_ECC_SERR" }, + { .fc_id = 187, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM17_ECC_SERR" }, + { .fc_id = 188, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM18_ECC_SERR" }, + { .fc_id = 189, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM19_ECC_SERR" }, + { .fc_id = 190, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM20_ECC_SERR" }, + { .fc_id = 191, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM21_ECC_SERR" }, + { .fc_id = 192, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM22_ECC_SERR" }, + { .fc_id = 193, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM23_ECC_SERR" }, + { .fc_id = 194, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM24_ECC_SERR" }, + { .fc_id = 195, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM25_ECC_SERR" }, + { .fc_id = 196, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM26_ECC_SERR" }, + { .fc_id = 197, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM27_ECC_SERR" }, + { .fc_id = 198, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM28_ECC_SERR" }, + { .fc_id = 199, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM29_ECC_SERR" }, + { .fc_id = 200, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM30_ECC_SERR" }, + { .fc_id = 201, .cpu_id = 58, .valid = 1, + .msg = 0, .reset = 0, .name = "SRAM31_ECC_SERR" }, + { .fc_id = 202, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM0_ECC_DERR" }, + { .fc_id = 203, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM1_ECC_DERR" }, + { .fc_id = 204, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM2_ECC_DERR" }, + { .fc_id = 205, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM3_ECC_DERR" }, + { .fc_id = 206, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM4_ECC_DERR" }, + { .fc_id = 207, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM5_ECC_DERR" }, + { .fc_id = 208, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM6_ECC_DERR" }, + { .fc_id = 209, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM7_ECC_DERR" }, + { .fc_id = 210, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM8_ECC_DERR" }, + { .fc_id = 211, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM9_ECC_DERR" }, + { .fc_id = 212, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM10_ECC_DERR" }, + { .fc_id = 213, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM11_ECC_DERR" }, + { .fc_id = 214, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM12_ECC_DERR" }, + { .fc_id = 215, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM13_ECC_DERR" }, + { .fc_id = 216, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM14_ECC_DERR" }, + { .fc_id = 217, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM15_ECC_DERR" }, + { .fc_id = 218, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM16_ECC_DERR" }, + { .fc_id = 219, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM17_ECC_DERR" }, + { .fc_id = 220, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM18_ECC_DERR" }, + { .fc_id = 221, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM19_ECC_DERR" }, + { .fc_id = 222, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM20_ECC_DERR" }, + { .fc_id = 223, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM21_ECC_DERR" }, + { .fc_id = 224, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM22_ECC_DERR" }, + { .fc_id = 225, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM23_ECC_DERR" }, + { .fc_id = 226, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM24_ECC_DERR" }, + { .fc_id = 227, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM25_ECC_DERR" }, + { .fc_id = 228, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM26_ECC_DERR" }, + { .fc_id = 229, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM27_ECC_DERR" }, + { .fc_id = 230, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM28_ECC_DERR" }, + { .fc_id = 231, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM29_ECC_DERR" }, + { .fc_id = 232, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM30_ECC_DERR" }, + { .fc_id = 233, .cpu_id = 59, .valid = 1, + .msg = 0, .reset = 1, .name = "SRAM31_ECC_DERR" }, + { .fc_id = 234, .cpu_id = 60, .valid = 1, + .msg = 0, .reset = 1, .name = "GIC500" }, + { .fc_id = 235, .cpu_id = 61, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM_0_MC0_ECC_SERR" }, + { .fc_id = 236, .cpu_id = 61, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM_1_MC0_ECC_SERR" }, + { .fc_id = 237, .cpu_id = 61, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM_2_MC0_ECC_SERR" }, + { .fc_id = 238, .cpu_id = 61, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM_3_MC0_ECC_SERR" }, + { .fc_id = 239, .cpu_id = 61, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM_4_MC0_ECC_SERR" }, + { .fc_id = 240, .cpu_id = 61, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM_5_MC0_ECC_SERR" }, + { .fc_id = 241, .cpu_id = 61, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM_0_MC1_ECC_SERR" }, + { .fc_id = 242, .cpu_id = 61, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM_1_MC1_ECC_SERR" }, + { .fc_id = 243, .cpu_id = 61, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM_2_MC1_ECC_SERR" }, + { .fc_id = 244, .cpu_id = 61, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM_3_MC1_ECC_SERR" }, + { .fc_id = 245, .cpu_id = 61, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM_4_MC1_ECC_SERR" }, + { .fc_id = 246, .cpu_id = 61, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM_5_MC1_ECC_SERR" }, + { .fc_id = 247, .cpu_id = 62, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_0_MC0_ECC_DERR" }, + { .fc_id = 248, .cpu_id = 62, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_1_MC0_ECC_DERR" }, + { .fc_id = 249, .cpu_id = 62, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_2_MC0_ECC_DERR" }, + { .fc_id = 250, .cpu_id = 62, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_3_MC0_ECC_DERR" }, + { .fc_id = 251, .cpu_id = 62, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_4_MC0_ECC_DERR" }, + { .fc_id = 252, .cpu_id = 62, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_5_MC0_ECC_DERR" }, + { .fc_id = 253, .cpu_id = 62, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_0_MC1_ECC_DERR" }, + { .fc_id = 254, .cpu_id = 62, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_1_MC1_ECC_DERR" }, + { .fc_id = 255, .cpu_id = 62, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_2_MC1_ECC_DERR" }, + { .fc_id = 256, .cpu_id = 62, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_3_MC1_ECC_DERR" }, + { .fc_id = 257, .cpu_id = 62, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_4_MC1_ECC_DERR" }, + { .fc_id = 258, .cpu_id = 62, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_5_MC1_ECC_DERR" }, + { .fc_id = 259, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_0_ECC_SERR" }, + { .fc_id = 260, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_1_ECC_SERR" }, + { .fc_id = 261, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_2_ECC_SERR" }, + { .fc_id = 262, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_3_ECC_SERR" }, + { .fc_id = 263, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_8_ECC_SERR" }, + { .fc_id = 264, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_9_ECC_SERR" }, + { .fc_id = 265, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_10_ECC_SERR" }, + { .fc_id = 266, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_11_ECC_SERR" }, + { .fc_id = 267, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_7_ECC_SERR" }, + { .fc_id = 268, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_6_ECC_SERR" }, + { .fc_id = 269, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_5_ECC_SERR" }, + { .fc_id = 270, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_4_ECC_SERR" }, + { .fc_id = 271, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_15_ECC_SERR" }, + { .fc_id = 272, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_14_ECC_SERR" }, + { .fc_id = 273, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_13_ECC_SERR" }, + { .fc_id = 274, .cpu_id = 63, .valid = 1, + .msg = 0, .reset = 0, .name = "HMMU_12_ECC_SERR" }, + { .fc_id = 275, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_0_ECC_DERR" }, + { .fc_id = 276, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_1_ECC_DERR" }, + { .fc_id = 277, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_2_ECC_DERR" }, + { .fc_id = 278, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_3_ECC_DERR" }, + { .fc_id = 279, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_8_ECC_DERR" }, + { .fc_id = 280, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_9_ECC_DERR" }, + { .fc_id = 281, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_10_ECC_DERR" }, + { .fc_id = 282, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_11_ECC_DERR" }, + { .fc_id = 283, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_7_ECC_DERR" }, + { .fc_id = 284, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_6_ECC_DERR" }, + { .fc_id = 285, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_5_ECC_DERR" }, + { .fc_id = 286, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_4_ECC_DERR" }, + { .fc_id = 287, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_15_ECC_DERR" }, + { .fc_id = 288, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_14_ECC_DERR" }, + { .fc_id = 289, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_13_ECC_DERR" }, + { .fc_id = 290, .cpu_id = 64, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_12_ECC_DERR" }, + { .fc_id = 291, .cpu_id = 65, .valid = 1, + .msg = 0, .reset = 0, .name = "PMMU_ECC_SERR" }, + { .fc_id = 292, .cpu_id = 66, .valid = 1, + .msg = 0, .reset = 1, .name = "PMMU_ECC_DERR" }, + { .fc_id = 293, .cpu_id = 67, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 294, .cpu_id = 68, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 295, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC0_VCD_ECC_SERR" }, + { .fc_id = 296, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC1_VCD_ECC_SERR" }, + { .fc_id = 297, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC2_VCD_ECC_SERR" }, + { .fc_id = 298, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC3_VCD_ECC_SERR" }, + { .fc_id = 299, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC4_VCD_ECC_SERR" }, + { .fc_id = 300, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC5_VCD_ECC_SERR" }, + { .fc_id = 301, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC6_VCD_ECC_SERR" }, + { .fc_id = 302, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC7_VCD_ECC_SERR" }, + { .fc_id = 303, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC8_VCD_ECC_SERR" }, + { .fc_id = 304, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC9_VCD_ECC_SERR" }, + { .fc_id = 305, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC0_L2C_ECC_SERR" }, + { .fc_id = 306, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC1_L2C_ECC_SERR" }, + { .fc_id = 307, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC2_L2C_ECC_SERR" }, + { .fc_id = 308, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC3_L2C_ECC_SERR" }, + { .fc_id = 309, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC4_L2C_ECC_SERR" }, + { .fc_id = 310, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC5_L2C_ECC_SERR" }, + { .fc_id = 311, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC6_L2C_ECC_SERR" }, + { .fc_id = 312, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC7_L2C_ECC_SERR" }, + { .fc_id = 313, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC8_L2C_ECC_SERR" }, + { .fc_id = 314, .cpu_id = 69, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC9_L2C_ECC_SERR" }, + { .fc_id = 315, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC0_VCD_ECC_DERR" }, + { .fc_id = 316, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC1_VCD_ECC_DERR" }, + { .fc_id = 317, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC2_VCD_ECC_DERR" }, + { .fc_id = 318, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC3_VCD_ECC_DERR" }, + { .fc_id = 319, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC4_VCD_ECC_DERR" }, + { .fc_id = 320, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC5_VCD_ECC_DERR" }, + { .fc_id = 321, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC6_VCD_ECC_DERR" }, + { .fc_id = 322, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC7_VCD_ECC_DERR" }, + { .fc_id = 323, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC8_VCD_ECC_DERR" }, + { .fc_id = 324, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC9_VCD_ECC_DERR" }, + { .fc_id = 325, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC0_L2C_ECC_DERR" }, + { .fc_id = 326, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC1_L2C_ECC_DERR" }, + { .fc_id = 327, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC2_L2C_ECC_DERR" }, + { .fc_id = 328, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC3_L2C_ECC_DERR" }, + { .fc_id = 329, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC4_L2C_ECC_DERR" }, + { .fc_id = 330, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC5_L2C_ECC_DERR" }, + { .fc_id = 331, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC6_L2C_ECC_DERR" }, + { .fc_id = 332, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC7_L2C_ECC_DERR" }, + { .fc_id = 333, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC8_L2C_ECC_DERR" }, + { .fc_id = 334, .cpu_id = 70, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC9_L2C_ECC_DERR" }, + { .fc_id = 335, .cpu_id = 71, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 336, .cpu_id = 72, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 337, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF0_ECC_SERR" }, + { .fc_id = 338, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF1_ECC_SERR" }, + { .fc_id = 339, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF2_ECC_SERR" }, + { .fc_id = 340, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF3_ECC_SERR" }, + { .fc_id = 341, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF8_ECC_SERR" }, + { .fc_id = 342, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF9_ECC_SERR" }, + { .fc_id = 343, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF10_ECC_SERR" }, + { .fc_id = 344, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF11_ECC_SERR" }, + { .fc_id = 345, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF7_ECC_SERR" }, + { .fc_id = 346, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF6_ECC_SERR" }, + { .fc_id = 347, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF5_ECC_SERR" }, + { .fc_id = 348, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF4_ECC_SERR" }, + { .fc_id = 349, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF15_ECC_SERR" }, + { .fc_id = 350, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF14_ECC_SERR" }, + { .fc_id = 351, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF13_ECC_SERR" }, + { .fc_id = 352, .cpu_id = 73, .valid = 1, + .msg = 0, .reset = 0, .name = "HIF12_ECC_SERR" }, + { .fc_id = 353, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF0_ECC_DERR" }, + { .fc_id = 354, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF1_ECC_DERR" }, + { .fc_id = 355, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF2_ECC_DERR" }, + { .fc_id = 356, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF3_ECC_DERR" }, + { .fc_id = 357, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF8_ECC_DERR" }, + { .fc_id = 358, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF9_ECC_DERR" }, + { .fc_id = 359, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF10_ECC_DERR" }, + { .fc_id = 360, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF11_ECC_DERR" }, + { .fc_id = 361, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF7_ECC_DERR" }, + { .fc_id = 362, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF6_ECC_DERR" }, + { .fc_id = 363, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF5_ECC_DERR" }, + { .fc_id = 364, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF4_ECC_DERR" }, + { .fc_id = 365, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF15_ECC_DERR" }, + { .fc_id = 366, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF14_ECC_DERR" }, + { .fc_id = 367, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF13_ECC_DERR" }, + { .fc_id = 368, .cpu_id = 74, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF12_ECC_DERR" }, + { .fc_id = 369, .cpu_id = 75, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC0_ECC_SERR" }, + { .fc_id = 370, .cpu_id = 75, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC1_ECC_SERR" }, + { .fc_id = 371, .cpu_id = 75, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC2_ECC_SERR" }, + { .fc_id = 372, .cpu_id = 75, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC3_ECC_SERR" }, + { .fc_id = 373, .cpu_id = 75, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC4_ECC_SERR" }, + { .fc_id = 374, .cpu_id = 75, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC5_ECC_SERR" }, + { .fc_id = 375, .cpu_id = 75, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC6_ECC_SERR" }, + { .fc_id = 376, .cpu_id = 75, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC7_ECC_SERR" }, + { .fc_id = 377, .cpu_id = 75, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC8_ECC_SERR" }, + { .fc_id = 378, .cpu_id = 75, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC9_ECC_SERR" }, + { .fc_id = 379, .cpu_id = 75, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC10_ECC_SERR" }, + { .fc_id = 380, .cpu_id = 75, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC11_ECC_SERR" }, + { .fc_id = 381, .cpu_id = 76, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC0_ECC_DERR" }, + { .fc_id = 382, .cpu_id = 76, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC1_ECC_DERR" }, + { .fc_id = 383, .cpu_id = 76, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC2_ECC_DERR" }, + { .fc_id = 384, .cpu_id = 76, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC3_ECC_DERR" }, + { .fc_id = 385, .cpu_id = 76, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC4_ECC_DERR" }, + { .fc_id = 386, .cpu_id = 76, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC5_ECC_DERR" }, + { .fc_id = 387, .cpu_id = 76, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC6_ECC_DERR" }, + { .fc_id = 388, .cpu_id = 76, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC7_ECC_DERR" }, + { .fc_id = 389, .cpu_id = 76, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC8_ECC_DERR" }, + { .fc_id = 390, .cpu_id = 76, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC9_ECC_DERR" }, + { .fc_id = 391, .cpu_id = 76, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC10_ECC_DERR" }, + { .fc_id = 392, .cpu_id = 76, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC11_ECC_DERR" }, + { .fc_id = 393, .cpu_id = 77, .valid = 1, + .msg = 0, .reset = 1, .name = "SM0_ECC_DERR" }, + { .fc_id = 394, .cpu_id = 77, .valid = 1, + .msg = 0, .reset = 1, .name = "SM1_ECC_DERR" }, + { .fc_id = 395, .cpu_id = 77, .valid = 1, + .msg = 0, .reset = 1, .name = "SM2_ECC_DERR" }, + { .fc_id = 396, .cpu_id = 77, .valid = 1, + .msg = 0, .reset = 1, .name = "SM3_ECC_DERR" }, + { .fc_id = 397, .cpu_id = 78, .valid = 1, + .msg = 0, .reset = 0, .name = "SM0_ECC_SERR" }, + { .fc_id = 398, .cpu_id = 78, .valid = 1, + .msg = 0, .reset = 0, .name = "SM1_ECC_SERR" }, + { .fc_id = 399, .cpu_id = 78, .valid = 1, + .msg = 0, .reset = 0, .name = "SM2_ECC_SERR" }, + { .fc_id = 400, .cpu_id = 78, .valid = 1, + .msg = 0, .reset = 0, .name = "SM3_ECC_SERR" }, + { .fc_id = 401, .cpu_id = 79, .valid = 1, + .msg = 0, .reset = 0, .name = "XBAR0_ECC_SERR" }, + { .fc_id = 402, .cpu_id = 79, .valid = 1, + .msg = 0, .reset = 0, .name = "XBAR1_ECC_SERR" }, + { .fc_id = 403, .cpu_id = 79, .valid = 1, + .msg = 0, .reset = 0, .name = "XBAR2_ECC_SERR" }, + { .fc_id = 404, .cpu_id = 79, .valid = 1, + .msg = 0, .reset = 0, .name = "XBAR3_ECC_SERR" }, + { .fc_id = 405, .cpu_id = 80, .valid = 1, + .msg = 0, .reset = 1, .name = "XBAR0_ECC_DERR" }, + { .fc_id = 406, .cpu_id = 80, .valid = 1, + .msg = 0, .reset = 1, .name = "XBAR1_ECC_DERR" }, + { .fc_id = 407, .cpu_id = 80, .valid = 1, + .msg = 0, .reset = 1, .name = "XBAR2_ECC_DERR" }, + { .fc_id = 408, .cpu_id = 80, .valid = 1, + .msg = 0, .reset = 1, .name = "XBAR3_ECC_DERR" }, + { .fc_id = 409, .cpu_id = 81, .valid = 1, + .msg = 0, .reset = 0, .name = "ARC0_ECC_SERR" }, + { .fc_id = 410, .cpu_id = 82, .valid = 1, + .msg = 0, .reset = 1, .name = "ARC0_ECC_DERR" }, + { .fc_id = 411, .cpu_id = 83, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 412, .cpu_id = 84, .valid = 1, + .msg = 0, .reset = 1, .name = "PCIE_ADDR_DEC_ERR" }, + { .fc_id = 413, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC0_AXI_ERR_RSP" }, + { .fc_id = 414, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC1_AXI_ERR_RSP" }, + { .fc_id = 415, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC2_AXI_ERR_RSP" }, + { .fc_id = 416, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC3_AXI_ERR_RSP" }, + { .fc_id = 417, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC4_AXI_ERR_RSP" }, + { .fc_id = 418, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC5_AXI_ERR_RSP" }, + { .fc_id = 419, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC6_AXI_ERR_RSP" }, + { .fc_id = 420, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC7_AXI_ERR_RSP" }, + { .fc_id = 421, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC8_AXI_ERR_RSP" }, + { .fc_id = 422, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC9_AXI_ERR_RSP" }, + { .fc_id = 423, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC10_AXI_ERR_RSP" }, + { .fc_id = 424, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC11_AXI_ERR_RSP" }, + { .fc_id = 425, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC12_AXI_ERR_RSP" }, + { .fc_id = 426, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC13_AXI_ERR_RSP" }, + { .fc_id = 427, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC14_AXI_ERR_RSP" }, + { .fc_id = 428, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC15_AXI_ERR_RSP" }, + { .fc_id = 429, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC16_AXI_ERR_RSP" }, + { .fc_id = 430, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC17_AXI_ERR_RSP" }, + { .fc_id = 431, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC18_AXI_ERR_RSP" }, + { .fc_id = 432, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC19_AXI_ERR_RSP" }, + { .fc_id = 433, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC20_AXI_ERR_RSP" }, + { .fc_id = 434, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC21_AXI_ERR_RSP" }, + { .fc_id = 435, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC22_AXI_ERR_RSP" }, + { .fc_id = 436, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC23_AXI_ERR_RSP" }, + { .fc_id = 437, .cpu_id = 85, .valid = 1, + .msg = 0, .reset = 1, .name = "TPC24_AXI_ERR_RSP" }, + { .fc_id = 438, .cpu_id = 86, .valid = 1, + .msg = 0, .reset = 1, .name = "AXI_ECC" }, + { .fc_id = 439, .cpu_id = 87, .valid = 1, + .msg = 0, .reset = 1, .name = "L2_RAM_ECC" }, + { .fc_id = 440, .cpu_id = 88, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_SBTE0_AXI_ERR_RSP" }, + { .fc_id = 441, .cpu_id = 88, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_SBTE1_AXI_ERR_RSP" }, + { .fc_id = 442, .cpu_id = 88, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_SBTE2_AXI_ERR_RSP" }, + { .fc_id = 443, .cpu_id = 88, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_SBTE3_AXI_ERR_RSP" }, + { .fc_id = 444, .cpu_id = 88, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_SBTE4_AXI_ERR_RSP" }, + { .fc_id = 445, .cpu_id = 88, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_CTRL_AXI_ERROR_RESPONSE" }, + { .fc_id = 446, .cpu_id = 88, .valid = 1, + .msg = 0, .reset = 1, .name = "MME0_QMAN_SW_ERROR" }, + { .fc_id = 447, .cpu_id = 89, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_SBTE0_AXI_ERR_RSP" }, + { .fc_id = 448, .cpu_id = 89, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_SBTE1_AXI_ERR_RSP" }, + { .fc_id = 449, .cpu_id = 89, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_SBTE2_AXI_ERR_RSP" }, + { .fc_id = 450, .cpu_id = 89, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_SBTE3_AXI_ERR_RSP" }, + { .fc_id = 451, .cpu_id = 89, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_SBTE4_AXI_ERR_RSP" }, + { .fc_id = 452, .cpu_id = 89, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_CTRL_AXI_ERROR_RESPONSE" }, + { .fc_id = 453, .cpu_id = 89, .valid = 1, + .msg = 0, .reset = 1, .name = "MME1_QMAN_SW_ERROR" }, + { .fc_id = 454, .cpu_id = 90, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_SBTE0_AXI_ERR_RSP" }, + { .fc_id = 455, .cpu_id = 90, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_SBTE1_AXI_ERR_RSP" }, + { .fc_id = 456, .cpu_id = 90, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_SBTE2_AXI_ERR_RSP" }, + { .fc_id = 457, .cpu_id = 90, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_SBTE3_AXI_ERR_RSP" }, + { .fc_id = 458, .cpu_id = 90, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_SBTE4_AXI_ERR_RSP" }, + { .fc_id = 459, .cpu_id = 90, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_CTRL_AXI_ERROR_RESPONSE" }, + { .fc_id = 460, .cpu_id = 90, .valid = 1, + .msg = 0, .reset = 1, .name = "MME2_QMAN_SW_ERROR" }, + { .fc_id = 461, .cpu_id = 91, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_SBTE0_AXI_ERR_RSP" }, + { .fc_id = 462, .cpu_id = 91, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_SBTE1_AXI_ERR_RSP" }, + { .fc_id = 463, .cpu_id = 91, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_SBTE2_AXI_ERR_RSP" }, + { .fc_id = 464, .cpu_id = 91, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_SBTE3_AXI_ERR_RSP" }, + { .fc_id = 465, .cpu_id = 91, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_SBTE4_AXI_ERR_RSP" }, + { .fc_id = 466, .cpu_id = 91, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_CTRL_AXI_ERROR_RESPONSE" }, + { .fc_id = 467, .cpu_id = 91, .valid = 1, + .msg = 0, .reset = 1, .name = "MME3_QMAN_SW_ERROR" }, + { .fc_id = 468, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "PSOC_MME_PLL_LOCK_ERR" }, + { .fc_id = 469, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "PSOC_CPU_PLL_LOCK_ERR" }, + { .fc_id = 470, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE3_TPC_PLL_LOCK_ERR" }, + { .fc_id = 471, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE3_NIC_PLL_LOCK_ERR" }, + { .fc_id = 472, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE3_XBAR_MMU_PLL_LOCK_ERR" }, + { .fc_id = 473, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE3_XBAR_DMA_PLL_LOCK_ERR" }, + { .fc_id = 474, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE3_XBAR_IF_PLL_LOCK_ERR" }, + { .fc_id = 475, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE3_XBAR_BANK_PLL_LOCK_ERR" }, + { .fc_id = 476, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE1_XBAR_MMU_PLL_LOCK_ERR" }, + { .fc_id = 477, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE1_XBAR_DMA_PLL_LOCK_ERR" }, + { .fc_id = 478, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE1_XBAR_IF_PLL_LOCK_ERR" }, + { .fc_id = 479, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE1_XBAR_MESH_PLL_LOCK_ERR" }, + { .fc_id = 480, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE1_TPC_PLL_LOCK_ERR" }, + { .fc_id = 481, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE1_NIC_PLL_LOCK_ERR" }, + { .fc_id = 482, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "PMMU_MME_PLL_LOCK_ERR" }, + { .fc_id = 483, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE0_TPC_PLL_LOCK_ERR" }, + { .fc_id = 484, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE0_PCI_PLL_LOCK_ERR" }, + { .fc_id = 485, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE0_XBAR_MMU_PLL_LOCK_ERR" }, + { .fc_id = 486, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE0_XBAR_DMA_PLL_LOCK_ERR" }, + { .fc_id = 487, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE0_XBAR_IF_PLL_LOCK_ERR" }, + { .fc_id = 488, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE0_XBAR_MESH_PLL_LOCK_ERR" }, + { .fc_id = 489, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE2_XBAR_MMU_PLL_LOCK_ERR" }, + { .fc_id = 490, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE2_XBAR_DMA_PLL_LOCK_ERR" }, + { .fc_id = 491, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE2_XBAR_IF_PLL_LOCK_ERR" }, + { .fc_id = 492, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE2_XBAR_BANK_PLL_LOCK_ERR" }, + { .fc_id = 493, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE2_TPC_PLL_LOCK_ERR" }, + { .fc_id = 494, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "PSOC_VID_PLL_LOCK_ERR" }, + { .fc_id = 495, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "PMMU_VID_PLL_LOCK_ERR" }, + { .fc_id = 496, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE3_HBM_PLL_LOCK_ERR" }, + { .fc_id = 497, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE1_XBAR_HBM_PLL_LOCK_ERR" }, + { .fc_id = 498, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE1_HBM_PLL_LOCK_ERR" }, + { .fc_id = 499, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE0_HBM_PLL_LOCK_ERR" }, + { .fc_id = 500, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE2_XBAR_HBM_PLL_LOCK_ERR" }, + { .fc_id = 501, .cpu_id = 92, .valid = 1, + .msg = 0, .reset = 1, .name = "DCORE2_HBM_PLL_LOCK_ERR" }, + { .fc_id = 502, .cpu_id = 93, .valid = 1, + .msg = 0, .reset = 1, .name = "CPU_AXI_ERR_RSP" }, + { .fc_id = 503, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_0_AXI_ERR_RSP" }, + { .fc_id = 504, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_1_AXI_ERR_RSP" }, + { .fc_id = 505, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_2_AXI_ERR_RSP" }, + { .fc_id = 506, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_3_AXI_ERR_RSP" }, + { .fc_id = 507, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_8_AXI_ERR_RSP" }, + { .fc_id = 508, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_9_AXI_ERR_RSP" }, + { .fc_id = 509, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_10_AXI_ERR_RSP" }, + { .fc_id = 510, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_11_AXI_ERR_RSP" }, + { .fc_id = 511, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_7_AXI_ERR_RSP" }, + { .fc_id = 512, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_6_AXI_ERR_RSP" }, + { .fc_id = 513, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_5_AXI_ERR_RSP" }, + { .fc_id = 514, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_4_AXI_ERR_RSP" }, + { .fc_id = 515, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_15_AXI_ERR_RSP" }, + { .fc_id = 516, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_14_AXI_ERR_RSP" }, + { .fc_id = 517, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_13_AXI_ERR_RSP" }, + { .fc_id = 518, .cpu_id = 94, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU_12_AXI_ERR_RSP" }, + { .fc_id = 519, .cpu_id = 95, .valid = 1, + .msg = 0, .reset = 1, .name = "PMMU_FATAL" }, + { .fc_id = 520, .cpu_id = 96, .valid = 1, + .msg = 0, .reset = 1, .name = "PMMU_AXI_ERR_RSP" }, + { .fc_id = 521, .cpu_id = 97, .valid = 1, + .msg = 0, .reset = 0, .name = "VM0_ALARM_A" }, + { .fc_id = 522, .cpu_id = 98, .valid = 1, + .msg = 0, .reset = 0, .name = "VM0_ALARM_B" }, + { .fc_id = 523, .cpu_id = 99, .valid = 1, + .msg = 0, .reset = 0, .name = "VM1_ALARM_A" }, + { .fc_id = 524, .cpu_id = 100, .valid = 1, + .msg = 0, .reset = 0, .name = "VM1_ALARM_B" }, + { .fc_id = 525, .cpu_id = 101, .valid = 1, + .msg = 0, .reset = 0, .name = "VM2_ALARM_A" }, + { .fc_id = 526, .cpu_id = 102, .valid = 1, + .msg = 0, .reset = 0, .name = "VM2_ALARM_B" }, + { .fc_id = 527, .cpu_id = 103, .valid = 1, + .msg = 0, .reset = 0, .name = "VM3_ALARM_A" }, + { .fc_id = 528, .cpu_id = 104, .valid = 1, + .msg = 0, .reset = 0, .name = "VM3_ALARM_B" }, + { .fc_id = 529, .cpu_id = 105, .valid = 1, + .msg = 0, .reset = 1, .name = "PSOC_AXI_ERR_RSP" }, + { .fc_id = 530, .cpu_id = 106, .valid = 1, + .msg = 0, .reset = 0, .name = "PSOC_PRSTN_FALL" }, + { .fc_id = 531, .cpu_id = 107, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 532, .cpu_id = 107, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 533, .cpu_id = 107, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 534, .cpu_id = 107, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 535, .cpu_id = 107, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 536, .cpu_id = 107, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 537, .cpu_id = 107, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 538, .cpu_id = 107, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 539, .cpu_id = 108, .valid = 1, + .msg = 0, .reset = 1, .name = "KDMA_CH0_AXI_ERR_RSP" }, + { .fc_id = 540, .cpu_id = 109, .valid = 1, + .msg = 0, .reset = 1, .name = "PDMA_CH0_AXI_ERR_RSP" }, + { .fc_id = 541, .cpu_id = 109, .valid = 1, + .msg = 0, .reset = 1, .name = "PDMA_CH1_AXI_ERR_RSP" }, + { .fc_id = 542, .cpu_id = 110, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_CATTRIP_0" }, + { .fc_id = 543, .cpu_id = 111, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_CATTRIP_1" }, + { .fc_id = 544, .cpu_id = 112, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_CATTRIP_2" }, + { .fc_id = 545, .cpu_id = 113, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_CATTRIP_3" }, + { .fc_id = 546, .cpu_id = 114, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_CATTRIP_4" }, + { .fc_id = 547, .cpu_id = 115, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM_CATTRIP_5" }, + { .fc_id = 548, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM0_MC0_SEI_SEVERE" }, + { .fc_id = 549, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM0_MC0_SEI_NON_SEVERE" }, + { .fc_id = 550, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM0_MC1_SEI_SEVERE" }, + { .fc_id = 551, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM0_MC1_SEI_NON_SEVERE" }, + { .fc_id = 552, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM1_MC0_SEI_SEVERE" }, + { .fc_id = 553, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM1_MC0_SEI_NON_SEVERE" }, + { .fc_id = 554, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM1_MC1_SEI_SEVERE" }, + { .fc_id = 555, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM1_MC1_SEI_NON_SEVERE" }, + { .fc_id = 556, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM2_MC0_SEI_SEVERE" }, + { .fc_id = 557, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM2_MC0_SEI_NON_SEVERE" }, + { .fc_id = 558, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM2_MC1_SEI_SEVERE" }, + { .fc_id = 559, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM2_MC1_SEI_NON_SEVERE" }, + { .fc_id = 560, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM3_MC0_SEI_SEVERE" }, + { .fc_id = 561, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM3_MC0_SEI_NON_SEVERE" }, + { .fc_id = 562, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM3_MC1_SEI_SEVERE" }, + { .fc_id = 563, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM3_MC1_SEI_NON_SEVERE" }, + { .fc_id = 564, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM4_MC0_SEI_SEVERE" }, + { .fc_id = 565, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM4_MC0_SEI_NON_SEVERE" }, + { .fc_id = 566, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM4_MC1_SEI_SEVERE" }, + { .fc_id = 567, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM4_MC1_SEI_NON_SEVERE" }, + { .fc_id = 568, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM5_MC0_SEI_SEVERE" }, + { .fc_id = 569, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM5_MC0_SEI_NON_SEVERE" }, + { .fc_id = 570, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 1, .name = "HBM5_MC1_SEI_SEVERE" }, + { .fc_id = 571, .cpu_id = 116, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM5_MC1_SEI_NON_SEVERE" }, + { .fc_id = 572, .cpu_id = 117, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC0_AXI_ERR_RSPONSE" }, + { .fc_id = 573, .cpu_id = 117, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC1_AXI_ERR_RSPONSE" }, + { .fc_id = 574, .cpu_id = 117, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC2_AXI_ERR_RSPONSE" }, + { .fc_id = 575, .cpu_id = 117, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC3_AXI_ERR_RSPONSE" }, + { .fc_id = 576, .cpu_id = 117, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC4_AXI_ERR_RSPONSE" }, + { .fc_id = 577, .cpu_id = 117, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC5_AXI_ERR_RSPONSE" }, + { .fc_id = 578, .cpu_id = 117, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC6_AXI_ERR_RSPONSE" }, + { .fc_id = 579, .cpu_id = 117, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC7_AXI_ERR_RSPONSE" }, + { .fc_id = 580, .cpu_id = 117, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC8_AXI_ERR_RSPONSE" }, + { .fc_id = 581, .cpu_id = 117, .valid = 1, + .msg = 0, .reset = 1, .name = "DEC9_AXI_ERR_RSPONSE" }, + { .fc_id = 582, .cpu_id = 118, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 583, .cpu_id = 119, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 584, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF0_FATAL" }, + { .fc_id = 585, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF1_FATAL" }, + { .fc_id = 586, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF2_FATAL" }, + { .fc_id = 587, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF3_FATAL" }, + { .fc_id = 588, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF8_FATAL" }, + { .fc_id = 589, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF9_FATAL" }, + { .fc_id = 590, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF10_FATAL" }, + { .fc_id = 591, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF11_FATAL" }, + { .fc_id = 592, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF7_FATAL" }, + { .fc_id = 593, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF6_FATAL" }, + { .fc_id = 594, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF5_FATAL" }, + { .fc_id = 595, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF4_FATAL" }, + { .fc_id = 596, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF15_FATAL" }, + { .fc_id = 597, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF14_FATAL" }, + { .fc_id = 598, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF13_FATAL" }, + { .fc_id = 599, .cpu_id = 120, .valid = 1, + .msg = 0, .reset = 1, .name = "HIF12_FATAL" }, + { .fc_id = 600, .cpu_id = 121, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC0_AXI_ERROR_RESPONSE" }, + { .fc_id = 601, .cpu_id = 121, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC1_AXI_ERROR_RESPONSE" }, + { .fc_id = 602, .cpu_id = 121, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC2_AXI_ERROR_RESPONSE" }, + { .fc_id = 603, .cpu_id = 121, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC3_AXI_ERROR_RESPONSE" }, + { .fc_id = 604, .cpu_id = 121, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC4_AXI_ERROR_RESPONSE" }, + { .fc_id = 605, .cpu_id = 121, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC5_AXI_ERROR_RESPONSE" }, + { .fc_id = 606, .cpu_id = 121, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC6_AXI_ERROR_RESPONSE" }, + { .fc_id = 607, .cpu_id = 121, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC7_AXI_ERROR_RESPONSE" }, + { .fc_id = 608, .cpu_id = 121, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC8_AXI_ERROR_RESPONSE" }, + { .fc_id = 609, .cpu_id = 121, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC9_AXI_ERROR_RESPONSE" }, + { .fc_id = 610, .cpu_id = 121, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC10_AXI_ERROR_RESPONSE" }, + { .fc_id = 611, .cpu_id = 121, .valid = 1, + .msg = 0, .reset = 1, .name = "NIC11_AXI_ERROR_RESPONSE" }, + { .fc_id = 612, .cpu_id = 122, .valid = 1, + .msg = 0, .reset = 1, .name = "SM0_AXI_ERROR_RESPONSE" }, + { .fc_id = 613, .cpu_id = 122, .valid = 1, + .msg = 0, .reset = 1, .name = "SM1_AXI_ERROR_RESPONSE" }, + { .fc_id = 614, .cpu_id = 122, .valid = 1, + .msg = 0, .reset = 1, .name = "SM2_AXI_ERROR_RESPONSE" }, + { .fc_id = 615, .cpu_id = 122, .valid = 1, + .msg = 0, .reset = 1, .name = "SM3_AXI_ERROR_RESPONSE" }, + { .fc_id = 616, .cpu_id = 123, .valid = 1, + .msg = 0, .reset = 1, .name = "ARC_AXI_ERROR_RESPONSE" }, + { .fc_id = 617, .cpu_id = 124, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 618, .cpu_id = 125, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 619, .cpu_id = 125, .valid = 1, + .msg = 0, .reset = 0, .name = "PCIE_FLR_REQUESTED" }, + { .fc_id = 620, .cpu_id = 125, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 621, .cpu_id = 125, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 622, .cpu_id = 125, .valid = 1, + .msg = 0, .reset = 1, .name = "PCIE_APB_TIMEOUT" }, + { .fc_id = 623, .cpu_id = 125, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 624, .cpu_id = 125, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 625, .cpu_id = 125, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 626, .cpu_id = 125, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 627, .cpu_id = 125, .valid = 1, + .msg = 0, .reset = 0, .name = "PCIE_FATAL_ERR" }, + { .fc_id = 628, .cpu_id = 125, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 629, .cpu_id = 126, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 630, .cpu_id = 127, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 631, .cpu_id = 128, .valid = 1, + .msg = 0, .reset = 0, .name = "PCIE_P2P_MSIX" }, + { .fc_id = 632, .cpu_id = 129, .valid = 1, + .msg = 0, .reset = 0, .name = "PCIE_DRAIN_COMPLETE" }, + { .fc_id = 633, .cpu_id = 130, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC0_BMON_SPMU" }, + { .fc_id = 634, .cpu_id = 131, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC0_KERNEL_ERR" }, + { .fc_id = 635, .cpu_id = 132, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC1_BMON_SPMU" }, + { .fc_id = 636, .cpu_id = 133, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC1_KERNEL_ERR" }, + { .fc_id = 637, .cpu_id = 134, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC2_BMON_SPMU" }, + { .fc_id = 638, .cpu_id = 135, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC2_KERNEL_ERR" }, + { .fc_id = 639, .cpu_id = 136, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC3_BMON_SPMU" }, + { .fc_id = 640, .cpu_id = 137, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC3_KERNEL_ERR" }, + { .fc_id = 641, .cpu_id = 138, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC4_BMON_SPMU" }, + { .fc_id = 642, .cpu_id = 139, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC4_KERNEL_ERR" }, + { .fc_id = 643, .cpu_id = 140, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC5_BMON_SPMU" }, + { .fc_id = 644, .cpu_id = 141, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC5_KERNEL_ERR" }, + { .fc_id = 645, .cpu_id = 150, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC6_BMON_SPMU" }, + { .fc_id = 646, .cpu_id = 151, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC6_KERNEL_ERR" }, + { .fc_id = 647, .cpu_id = 152, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC7_BMON_SPMU" }, + { .fc_id = 648, .cpu_id = 153, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC7_KERNEL_ERR" }, + { .fc_id = 649, .cpu_id = 146, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC8_BMON_SPMU" }, + { .fc_id = 650, .cpu_id = 147, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC8_KERNEL_ERR" }, + { .fc_id = 651, .cpu_id = 148, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC9_BMON_SPMU" }, + { .fc_id = 652, .cpu_id = 149, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC9_KERNEL_ERR" }, + { .fc_id = 653, .cpu_id = 142, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC10_BMON_SPMU" }, + { .fc_id = 654, .cpu_id = 143, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC10_KERNEL_ERR" }, + { .fc_id = 655, .cpu_id = 144, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC11_BMON_SPMU" }, + { .fc_id = 656, .cpu_id = 145, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC11_KERNEL_ERR" }, + { .fc_id = 657, .cpu_id = 162, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC12_BMON_SPMU" }, + { .fc_id = 658, .cpu_id = 163, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC12_KERNEL_ERR" }, + { .fc_id = 659, .cpu_id = 164, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC13_BMON_SPMU" }, + { .fc_id = 660, .cpu_id = 165, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC13_KERNEL_ERR" }, + { .fc_id = 661, .cpu_id = 158, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC14_BMON_SPMU" }, + { .fc_id = 662, .cpu_id = 159, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC14_KERNEL_ERR" }, + { .fc_id = 663, .cpu_id = 160, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC15_BMON_SPMU" }, + { .fc_id = 664, .cpu_id = 161, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC15_KERNEL_ERR" }, + { .fc_id = 665, .cpu_id = 154, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC16_BMON_SPMU" }, + { .fc_id = 666, .cpu_id = 155, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC16_KERNEL_ERR" }, + { .fc_id = 667, .cpu_id = 156, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC17_BMON_SPMU" }, + { .fc_id = 668, .cpu_id = 157, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC17_KERNEL_ERR" }, + { .fc_id = 669, .cpu_id = 166, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC18_BMON_SPMU" }, + { .fc_id = 670, .cpu_id = 167, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC18_KERNEL_ERR" }, + { .fc_id = 671, .cpu_id = 168, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC19_BMON_SPMU" }, + { .fc_id = 672, .cpu_id = 169, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC19_KERNEL_ERR" }, + { .fc_id = 673, .cpu_id = 170, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC20_BMON_SPMU" }, + { .fc_id = 674, .cpu_id = 171, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC20_KERNEL_ERR" }, + { .fc_id = 675, .cpu_id = 172, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC21_BMON_SPMU" }, + { .fc_id = 676, .cpu_id = 173, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC21_KERNEL_ERR" }, + { .fc_id = 677, .cpu_id = 174, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC22_BMON_SPMU" }, + { .fc_id = 678, .cpu_id = 175, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC22_KERNEL_ERR" }, + { .fc_id = 679, .cpu_id = 176, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC23_BMON_SPMU" }, + { .fc_id = 680, .cpu_id = 177, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC23_KERNEL_ERR" }, + { .fc_id = 681, .cpu_id = 178, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC24_BMON_SPMU" }, + { .fc_id = 682, .cpu_id = 179, .valid = 1, + .msg = 0, .reset = 0, .name = "TPC24_KERNEL_ERR" }, + { .fc_id = 683, .cpu_id = 180, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 684, .cpu_id = 180, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 685, .cpu_id = 180, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 686, .cpu_id = 180, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 687, .cpu_id = 180, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 688, .cpu_id = 180, .valid = 1, + .msg = 0, .reset = 0, .name = "MME0_CTRL_BMON_SPMU" }, + { .fc_id = 689, .cpu_id = 180, .valid = 1, + .msg = 0, .reset = 0, .name = "MME0_SBTE_BMON_SPMU" }, + { .fc_id = 690, .cpu_id = 180, .valid = 1, + .msg = 0, .reset = 0, .name = "MME0_WAP_BMON_SPMU" }, + { .fc_id = 691, .cpu_id = 180, .valid = 1, + .msg = 0, .reset = 0, .name = "MME0_WAP_SOURCE_RESULT_INVALID" }, + { .fc_id = 692, .cpu_id = 181, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 693, .cpu_id = 181, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 694, .cpu_id = 181, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 695, .cpu_id = 181, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 696, .cpu_id = 181, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 697, .cpu_id = 181, .valid = 1, + .msg = 0, .reset = 0, .name = "MME1_CTRL_BMON_SPMU" }, + { .fc_id = 698, .cpu_id = 181, .valid = 1, + .msg = 0, .reset = 0, .name = "MME1_SBTE_BMON_SPMU" }, + { .fc_id = 699, .cpu_id = 181, .valid = 1, + .msg = 0, .reset = 0, .name = "MME1_WAP_BMON_SPMU" }, + { .fc_id = 700, .cpu_id = 181, .valid = 1, + .msg = 0, .reset = 0, .name = "MME1_WAP_SOURCE_RESULT_INVALID" }, + { .fc_id = 701, .cpu_id = 182, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 702, .cpu_id = 182, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 703, .cpu_id = 182, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 704, .cpu_id = 182, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 705, .cpu_id = 182, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 706, .cpu_id = 182, .valid = 1, + .msg = 0, .reset = 0, .name = "MME2_CTRL_BMON_SPMU" }, + { .fc_id = 707, .cpu_id = 182, .valid = 1, + .msg = 0, .reset = 0, .name = "MME2_SBTE_BMON_SPMU" }, + { .fc_id = 708, .cpu_id = 182, .valid = 1, + .msg = 0, .reset = 0, .name = "MME2_WAP_BMON_SPMU" }, + { .fc_id = 709, .cpu_id = 182, .valid = 1, + .msg = 0, .reset = 0, .name = "MME2_WAP_SOURCE_RESULT_INVALID" }, + { .fc_id = 710, .cpu_id = 183, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 711, .cpu_id = 183, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 712, .cpu_id = 183, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 713, .cpu_id = 183, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 714, .cpu_id = 183, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 715, .cpu_id = 183, .valid = 1, + .msg = 0, .reset = 0, .name = "MME3_CTRL_BMON_SPMU" }, + { .fc_id = 716, .cpu_id = 183, .valid = 1, + .msg = 0, .reset = 0, .name = "MME3_SBTE_BMON_SPMU" }, + { .fc_id = 717, .cpu_id = 183, .valid = 1, + .msg = 0, .reset = 0, .name = "MME3_WAP_BMON_SPMU" }, + { .fc_id = 718, .cpu_id = 183, .valid = 1, + .msg = 0, .reset = 0, .name = "MME3_WAP_SOURCE_RESULT_INVALID" }, + { .fc_id = 719, .cpu_id = 184, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 720, .cpu_id = 184, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU0_PAGE_FAULT_OR_WR_PERM" }, + { .fc_id = 721, .cpu_id = 184, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU0_SECURITY_ERROR" }, + { .fc_id = 722, .cpu_id = 185, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 723, .cpu_id = 185, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU1_PAGE_FAULT_WR_PERM" }, + { .fc_id = 724, .cpu_id = 185, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU1_SECURITY_ERROR" }, + { .fc_id = 725, .cpu_id = 186, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 726, .cpu_id = 186, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU2_PAGE_FAULT_WR_PERM" }, + { .fc_id = 727, .cpu_id = 186, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU2_SECURITY_ERROR" }, + { .fc_id = 728, .cpu_id = 187, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 729, .cpu_id = 187, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU3_PAGE_FAULT_WR_PERM" }, + { .fc_id = 730, .cpu_id = 187, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU3_SECURITY_ERROR" }, + { .fc_id = 731, .cpu_id = 188, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 732, .cpu_id = 188, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU8_PAGE_FAULT_WR_PERM" }, + { .fc_id = 733, .cpu_id = 188, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU8_SECURITY_ERROR" }, + { .fc_id = 734, .cpu_id = 189, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 735, .cpu_id = 189, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU9_PAGE_FAULT_WR_PERM" }, + { .fc_id = 736, .cpu_id = 189, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU9_SECURITY_ERROR" }, + { .fc_id = 737, .cpu_id = 190, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 738, .cpu_id = 190, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU10_PAGE_FAULT_WR_PERM" }, + { .fc_id = 739, .cpu_id = 190, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU10_SECURITY_ERROR" }, + { .fc_id = 740, .cpu_id = 191, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 741, .cpu_id = 191, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU11_PAGE_FAULT_WR_PERM" }, + { .fc_id = 742, .cpu_id = 191, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU11_SECURITY_ERROR" }, + { .fc_id = 743, .cpu_id = 192, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 744, .cpu_id = 192, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU7_PAGE_FAULT_WR_PERM" }, + { .fc_id = 745, .cpu_id = 192, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU7_SECURITY_ERROR" }, + { .fc_id = 746, .cpu_id = 193, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 747, .cpu_id = 193, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU6_PAGE_FAULT_WR_PERM" }, + { .fc_id = 748, .cpu_id = 193, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU6_SECURITY_ERROR" }, + { .fc_id = 749, .cpu_id = 194, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 750, .cpu_id = 194, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU5_PAGE_FAULT_WR_PERM" }, + { .fc_id = 751, .cpu_id = 194, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU5_SECURITY_ERROR" }, + { .fc_id = 752, .cpu_id = 195, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 753, .cpu_id = 195, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU4_PAGE_FAULT_WR_PERM" }, + { .fc_id = 754, .cpu_id = 195, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU4_SECURITY_ERROR" }, + { .fc_id = 755, .cpu_id = 196, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 756, .cpu_id = 196, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU15_PAGE_FAULT_WR_PERM" }, + { .fc_id = 757, .cpu_id = 196, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU15_SECURITY_ERROR" }, + { .fc_id = 758, .cpu_id = 197, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 759, .cpu_id = 197, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU14_PAGE_FAULT_WR_PERM" }, + { .fc_id = 760, .cpu_id = 197, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU14_SECURITY_ERROR" }, + { .fc_id = 761, .cpu_id = 198, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 762, .cpu_id = 198, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU13_PAGE_FAULT_WR_PERM" }, + { .fc_id = 763, .cpu_id = 198, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU13_SECURITY_ERROR" }, + { .fc_id = 764, .cpu_id = 199, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 765, .cpu_id = 199, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU12_PAGE_FAULT_WR_PERM" }, + { .fc_id = 766, .cpu_id = 199, .valid = 1, + .msg = 0, .reset = 1, .name = "HMMU12_SECURITY_ERROR" }, + { .fc_id = 767, .cpu_id = 200, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 768, .cpu_id = 201, .valid = 1, + .msg = 0, .reset = 1, .name = "PMMU0_PAGE_FAULT_WR_PERM" }, + { .fc_id = 769, .cpu_id = 202, .valid = 1, + .msg = 0, .reset = 1, .name = "PMMU0_SECURITY_ERROR" }, + { .fc_id = 770, .cpu_id = 203, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA2_BM_SPMU" }, + { .fc_id = 771, .cpu_id = 204, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 772, .cpu_id = 205, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA3_BM_SPMU" }, + { .fc_id = 773, .cpu_id = 206, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 774, .cpu_id = 207, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA0_BM_SPMU" }, + { .fc_id = 775, .cpu_id = 208, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 776, .cpu_id = 209, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA1_BM_SPMU" }, + { .fc_id = 777, .cpu_id = 210, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 778, .cpu_id = 211, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA6_BM_SPMU" }, + { .fc_id = 779, .cpu_id = 212, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 780, .cpu_id = 213, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA7_BM_SPMU" }, + { .fc_id = 781, .cpu_id = 214, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 782, .cpu_id = 215, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA4_BM_SPMU" }, + { .fc_id = 783, .cpu_id = 216, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 784, .cpu_id = 217, .valid = 1, + .msg = 0, .reset = 0, .name = "HDMA5_BM_SPMU" }, + { .fc_id = 785, .cpu_id = 218, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 786, .cpu_id = 219, .valid = 1, + .msg = 0, .reset = 0, .name = "KDMA_BM_SPMU" }, + { .fc_id = 787, .cpu_id = 220, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 788, .cpu_id = 221, .valid = 1, + .msg = 0, .reset = 0, .name = "PDMA0_BM_SPMU" }, + { .fc_id = 789, .cpu_id = 222, .valid = 1, + .msg = 0, .reset = 0, .name = "PDMA1_BM_SPMU" }, + { .fc_id = 790, .cpu_id = 223, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM0_MC0_SPI" }, + { .fc_id = 791, .cpu_id = 224, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM0_MC1_SPI" }, + { .fc_id = 792, .cpu_id = 225, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM1_MC0_SPI" }, + { .fc_id = 793, .cpu_id = 226, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM1_MC1_SPI" }, + { .fc_id = 794, .cpu_id = 227, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM2_MC0_SPI" }, + { .fc_id = 795, .cpu_id = 228, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM2_MC1_SPI" }, + { .fc_id = 796, .cpu_id = 229, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM3_MC0_SPI" }, + { .fc_id = 797, .cpu_id = 230, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM3_MC1_SPI" }, + { .fc_id = 798, .cpu_id = 231, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM4_MC0_SPI" }, + { .fc_id = 799, .cpu_id = 232, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM4_MC1_SPI" }, + { .fc_id = 800, .cpu_id = 233, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM5_MC0_SPI" }, + { .fc_id = 801, .cpu_id = 234, .valid = 1, + .msg = 0, .reset = 0, .name = "HBM5_MC1_SPI" }, + { .fc_id = 802, .cpu_id = 235, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 803, .cpu_id = 236, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 804, .cpu_id = 237, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 805, .cpu_id = 238, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 806, .cpu_id = 239, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 807, .cpu_id = 240, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 808, .cpu_id = 241, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 809, .cpu_id = 242, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 810, .cpu_id = 243, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 811, .cpu_id = 244, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 812, .cpu_id = 245, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 813, .cpu_id = 246, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 814, .cpu_id = 247, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 815, .cpu_id = 248, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 816, .cpu_id = 249, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 817, .cpu_id = 250, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 818, .cpu_id = 251, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 819, .cpu_id = 252, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 820, .cpu_id = 253, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 821, .cpu_id = 254, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 822, .cpu_id = 255, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 823, .cpu_id = 256, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 824, .cpu_id = 257, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 825, .cpu_id = 258, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 826, .cpu_id = 259, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 827, .cpu_id = 260, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 828, .cpu_id = 261, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 829, .cpu_id = 262, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 830, .cpu_id = 263, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 831, .cpu_id = 264, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 832, .cpu_id = 265, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 833, .cpu_id = 266, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 834, .cpu_id = 267, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 835, .cpu_id = 268, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 836, .cpu_id = 269, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 837, .cpu_id = 270, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 838, .cpu_id = 271, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 839, .cpu_id = 272, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 840, .cpu_id = 273, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 841, .cpu_id = 274, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 842, .cpu_id = 275, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 843, .cpu_id = 276, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 844, .cpu_id = 277, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 845, .cpu_id = 278, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 846, .cpu_id = 279, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 847, .cpu_id = 280, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 848, .cpu_id = 281, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 849, .cpu_id = 282, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 850, .cpu_id = 283, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 851, .cpu_id = 284, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 852, .cpu_id = 285, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 853, .cpu_id = 286, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 854, .cpu_id = 287, .valid = 0, + .msg = 0, .reset = 1, .name = "" }, + { .fc_id = 855, .cpu_id = 288, .valid = 0, + .msg = 0, .reset = 1, .name = "" }, + { .fc_id = 856, .cpu_id = 289, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 857, .cpu_id = 290, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 858, .cpu_id = 291, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 859, .cpu_id = 292, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 860, .cpu_id = 293, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 861, .cpu_id = 294, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 862, .cpu_id = 295, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 863, .cpu_id = 296, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 864, .cpu_id = 297, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 865, .cpu_id = 298, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 866, .cpu_id = 299, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 867, .cpu_id = 300, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 868, .cpu_id = 301, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 869, .cpu_id = 302, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 870, .cpu_id = 303, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 871, .cpu_id = 304, .valid = 1, + .msg = 0, .reset = 1, .name = "RPM_ERROR_OR_DRAIN" }, + { .fc_id = 872, .cpu_id = 305, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 873, .cpu_id = 306, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 874, .cpu_id = 307, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 875, .cpu_id = 308, .valid = 1, + .msg = 0, .reset = 0, .name = "RAZWI_OR_PID_MIN_MAX_INTERRUPT" }, + { .fc_id = 876, .cpu_id = 309, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 877, .cpu_id = 310, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 878, .cpu_id = 311, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 879, .cpu_id = 312, .valid = 0, + .msg = 0, .reset = 1, .name = "" }, + { .fc_id = 880, .cpu_id = 313, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 881, .cpu_id = 314, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 882, .cpu_id = 315, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 883, .cpu_id = 316, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 884, .cpu_id = 317, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 885, .cpu_id = 318, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 886, .cpu_id = 319, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 887, .cpu_id = 320, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 888, .cpu_id = 321, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 889, .cpu_id = 322, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 890, .cpu_id = 323, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 891, .cpu_id = 324, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 892, .cpu_id = 325, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 893, .cpu_id = 326, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 894, .cpu_id = 327, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 895, .cpu_id = 328, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 896, .cpu_id = 329, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC0_SPI" }, + { .fc_id = 897, .cpu_id = 329, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC0_BMON_SPMU" }, + { .fc_id = 898, .cpu_id = 330, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC1_SPI" }, + { .fc_id = 899, .cpu_id = 330, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC1_BMON_SPMU" }, + { .fc_id = 900, .cpu_id = 331, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC2_SPI" }, + { .fc_id = 901, .cpu_id = 331, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC2_BMON_SPMU" }, + { .fc_id = 902, .cpu_id = 332, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC3_SPI" }, + { .fc_id = 903, .cpu_id = 332, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC3_BMON_SPMU" }, + { .fc_id = 904, .cpu_id = 333, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC4_SPI" }, + { .fc_id = 905, .cpu_id = 333, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC4_BMON_SPMU" }, + { .fc_id = 906, .cpu_id = 334, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC5_SPI" }, + { .fc_id = 907, .cpu_id = 334, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC5_BMON_SPMU" }, + { .fc_id = 908, .cpu_id = 335, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC6_SPI" }, + { .fc_id = 909, .cpu_id = 335, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC6_BMON_SPMU" }, + { .fc_id = 910, .cpu_id = 336, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC7_SPI" }, + { .fc_id = 911, .cpu_id = 336, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC7_BMON_SPMU" }, + { .fc_id = 912, .cpu_id = 337, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC8_SPI" }, + { .fc_id = 913, .cpu_id = 337, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC8_BMON_SPMU" }, + { .fc_id = 914, .cpu_id = 338, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC9_SPI" }, + { .fc_id = 915, .cpu_id = 338, .valid = 1, + .msg = 0, .reset = 0, .name = "DEC9_BMON_SPMU" }, + { .fc_id = 916, .cpu_id = 339, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 917, .cpu_id = 340, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 918, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 919, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 920, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 921, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 922, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 923, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 924, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 925, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 926, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 927, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 928, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 929, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 930, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 931, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 932, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 933, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 934, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 935, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 936, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 937, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 938, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 939, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 940, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 941, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 942, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 943, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 944, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 945, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 946, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 947, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 948, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 949, .cpu_id = 341, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 950, .cpu_id = 342, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 951, .cpu_id = 343, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC0_BMON_SPMU" }, + { .fc_id = 952, .cpu_id = 343, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC0_SW_ERROR" }, + { .fc_id = 953, .cpu_id = 343, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 954, .cpu_id = 343, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 955, .cpu_id = 344, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC1_BMON_SPMU" }, + { .fc_id = 956, .cpu_id = 344, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC1_SW_ERROR" }, + { .fc_id = 957, .cpu_id = 344, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 958, .cpu_id = 344, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 959, .cpu_id = 345, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC2_BMON_SPMU" }, + { .fc_id = 960, .cpu_id = 345, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC2_SW_ERROR" }, + { .fc_id = 961, .cpu_id = 345, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 962, .cpu_id = 345, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 963, .cpu_id = 346, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC3_BMON_SPMU" }, + { .fc_id = 964, .cpu_id = 346, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC3_SW_ERROR" }, + { .fc_id = 965, .cpu_id = 346, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 966, .cpu_id = 346, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 967, .cpu_id = 347, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC4_BMON_SPMU" }, + { .fc_id = 968, .cpu_id = 347, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC4_SW_ERROR" }, + { .fc_id = 969, .cpu_id = 347, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 970, .cpu_id = 347, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 971, .cpu_id = 348, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC5_BMON_SPMU" }, + { .fc_id = 972, .cpu_id = 348, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC5_SW_ERROR" }, + { .fc_id = 973, .cpu_id = 348, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 974, .cpu_id = 348, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 975, .cpu_id = 349, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC6_BMON_SPMU" }, + { .fc_id = 976, .cpu_id = 349, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC6_SW_ERROR" }, + { .fc_id = 977, .cpu_id = 349, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 978, .cpu_id = 349, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 979, .cpu_id = 350, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC7_BMON_SPMU" }, + { .fc_id = 980, .cpu_id = 350, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC7_SW_ERROR" }, + { .fc_id = 981, .cpu_id = 350, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 982, .cpu_id = 350, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 983, .cpu_id = 351, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC8_BMON_SPMU" }, + { .fc_id = 984, .cpu_id = 351, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC8_SW_ERROR" }, + { .fc_id = 985, .cpu_id = 351, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 986, .cpu_id = 351, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 987, .cpu_id = 352, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC9_BMON_SPMU" }, + { .fc_id = 988, .cpu_id = 352, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC9_SW_ERROR" }, + { .fc_id = 989, .cpu_id = 352, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 990, .cpu_id = 352, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 991, .cpu_id = 353, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC10_BMON_SPMU" }, + { .fc_id = 992, .cpu_id = 353, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC10_SW_ERROR" }, + { .fc_id = 993, .cpu_id = 353, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 994, .cpu_id = 353, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 995, .cpu_id = 354, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC11_BMON_SPMU" }, + { .fc_id = 996, .cpu_id = 354, .valid = 1, + .msg = 0, .reset = 0, .name = "NIC11_SW_ERROR" }, + { .fc_id = 997, .cpu_id = 354, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 998, .cpu_id = 354, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 999, .cpu_id = 355, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1000, .cpu_id = 356, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1001, .cpu_id = 357, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1002, .cpu_id = 358, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1003, .cpu_id = 359, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1004, .cpu_id = 360, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1005, .cpu_id = 361, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1006, .cpu_id = 362, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1007, .cpu_id = 363, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1008, .cpu_id = 368, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1009, .cpu_id = 369, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1010, .cpu_id = 366, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1011, .cpu_id = 367, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1012, .cpu_id = 364, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1013, .cpu_id = 365, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1014, .cpu_id = 374, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1015, .cpu_id = 375, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1016, .cpu_id = 372, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1017, .cpu_id = 373, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1018, .cpu_id = 370, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1019, .cpu_id = 371, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1020, .cpu_id = 376, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1021, .cpu_id = 377, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1022, .cpu_id = 378, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1023, .cpu_id = 379, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1024, .cpu_id = 380, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1025, .cpu_id = 381, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1026, .cpu_id = 382, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1027, .cpu_id = 383, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1028, .cpu_id = 384, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1029, .cpu_id = 385, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1030, .cpu_id = 386, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1031, .cpu_id = 387, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1032, .cpu_id = 388, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1033, .cpu_id = 389, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1034, .cpu_id = 390, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1035, .cpu_id = 391, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1036, .cpu_id = 392, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1037, .cpu_id = 393, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1038, .cpu_id = 394, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1039, .cpu_id = 395, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1040, .cpu_id = 396, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1041, .cpu_id = 397, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1042, .cpu_id = 398, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1043, .cpu_id = 399, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1044, .cpu_id = 400, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1045, .cpu_id = 401, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1046, .cpu_id = 402, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1047, .cpu_id = 403, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1048, .cpu_id = 404, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1049, .cpu_id = 405, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1050, .cpu_id = 406, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1051, .cpu_id = 407, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1052, .cpu_id = 408, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1053, .cpu_id = 409, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1054, .cpu_id = 410, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1055, .cpu_id = 411, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1056, .cpu_id = 412, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1057, .cpu_id = 413, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1058, .cpu_id = 414, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1059, .cpu_id = 414, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1060, .cpu_id = 414, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1061, .cpu_id = 414, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1062, .cpu_id = 414, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1063, .cpu_id = 414, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1064, .cpu_id = 414, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1065, .cpu_id = 414, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1066, .cpu_id = 414, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1067, .cpu_id = 414, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1068, .cpu_id = 415, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1069, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1070, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1071, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1072, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1073, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1074, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1075, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1076, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1077, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1078, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1079, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1080, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1081, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1082, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1083, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1084, .cpu_id = 416, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1085, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1086, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1087, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1088, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1089, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1090, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1091, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1092, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1093, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1094, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1095, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1096, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1097, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1098, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1099, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1100, .cpu_id = 417, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1101, .cpu_id = 418, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1102, .cpu_id = 419, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1103, .cpu_id = 420, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1104, .cpu_id = 421, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1105, .cpu_id = 422, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1106, .cpu_id = 422, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1107, .cpu_id = 422, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1108, .cpu_id = 422, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1109, .cpu_id = 422, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1110, .cpu_id = 422, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1111, .cpu_id = 422, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1112, .cpu_id = 422, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1113, .cpu_id = 422, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1114, .cpu_id = 422, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1115, .cpu_id = 422, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1116, .cpu_id = 422, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1117, .cpu_id = 423, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1118, .cpu_id = 424, .valid = 1, + .msg = 0, .reset = 0, .name = "ROTATOR0_SERR" }, + { .fc_id = 1119, .cpu_id = 425, .valid = 1, + .msg = 0, .reset = 0, .name = "ROTATOR1_SERR" }, + { .fc_id = 1120, .cpu_id = 426, .valid = 1, + .msg = 0, .reset = 1, .name = "ROTATOR0_DERR" }, + { .fc_id = 1121, .cpu_id = 427, .valid = 1, + .msg = 0, .reset = 1, .name = "ROTATOR1_DERR" }, + { .fc_id = 1122, .cpu_id = 428, .valid = 1, + .msg = 0, .reset = 1, .name = "ROTATOR0_AXI_ERROR_RESPONSE" }, + { .fc_id = 1123, .cpu_id = 429, .valid = 1, + .msg = 0, .reset = 1, .name = "ROTATOR1_AXI_ERROR_RESPONSE" }, + { .fc_id = 1124, .cpu_id = 430, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1125, .cpu_id = 431, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1126, .cpu_id = 432, .valid = 1, + .msg = 0, .reset = 0, .name = "ROTATOR0_BMON_SPMU" }, + { .fc_id = 1127, .cpu_id = 433, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1128, .cpu_id = 434, .valid = 1, + .msg = 0, .reset = 0, .name = "ROTATOR1_BMON_SPMU" }, + { .fc_id = 1129, .cpu_id = 435, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1130, .cpu_id = 436, .valid = 1, + .msg = 0, .reset = 0, .name = "SM0_BMON_SPMU" }, + { .fc_id = 1131, .cpu_id = 437, .valid = 1, + .msg = 0, .reset = 0, .name = "SM1_BMON_SPMU" }, + { .fc_id = 1132, .cpu_id = 438, .valid = 1, + .msg = 0, .reset = 0, .name = "SM2_BMON_SPMU" }, + { .fc_id = 1133, .cpu_id = 439, .valid = 1, + .msg = 0, .reset = 0, .name = "SM3_BMON_SPMU" }, + { .fc_id = 1134, .cpu_id = 440, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1135, .cpu_id = 441, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1136, .cpu_id = 442, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1137, .cpu_id = 443, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1138, .cpu_id = 444, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1139, .cpu_id = 445, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1140, .cpu_id = 446, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1141, .cpu_id = 447, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1142, .cpu_id = 448, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1143, .cpu_id = 449, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1144, .cpu_id = 450, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1145, .cpu_id = 451, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1146, .cpu_id = 452, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1147, .cpu_id = 453, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1148, .cpu_id = 454, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1149, .cpu_id = 455, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1150, .cpu_id = 456, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1151, .cpu_id = 457, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1152, .cpu_id = 458, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1153, .cpu_id = 459, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1154, .cpu_id = 460, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1155, .cpu_id = 461, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1156, .cpu_id = 462, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1157, .cpu_id = 463, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1158, .cpu_id = 464, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1159, .cpu_id = 465, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1160, .cpu_id = 466, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1161, .cpu_id = 467, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1162, .cpu_id = 468, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1163, .cpu_id = 469, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1164, .cpu_id = 470, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1165, .cpu_id = 471, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1166, .cpu_id = 472, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1167, .cpu_id = 473, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1168, .cpu_id = 474, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1169, .cpu_id = 475, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1170, .cpu_id = 476, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1171, .cpu_id = 477, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1172, .cpu_id = 478, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1173, .cpu_id = 479, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1174, .cpu_id = 480, .valid = 1, + .msg = 1, .reset = 0, .name = "PSOC_DMA_QM" }, + { .fc_id = 1175, .cpu_id = 481, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1176, .cpu_id = 482, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1177, .cpu_id = 483, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1178, .cpu_id = 484, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1179, .cpu_id = 485, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1180, .cpu_id = 486, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1181, .cpu_id = 487, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1182, .cpu_id = 488, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1183, .cpu_id = 489, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1184, .cpu_id = 490, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1185, .cpu_id = 491, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1186, .cpu_id = 492, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1187, .cpu_id = 493, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1188, .cpu_id = 494, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1189, .cpu_id = 495, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1190, .cpu_id = 496, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1191, .cpu_id = 497, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1192, .cpu_id = 498, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1193, .cpu_id = 499, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1194, .cpu_id = 500, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1195, .cpu_id = 501, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1196, .cpu_id = 502, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1197, .cpu_id = 503, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1198, .cpu_id = 504, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1199, .cpu_id = 505, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1200, .cpu_id = 506, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1201, .cpu_id = 507, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1202, .cpu_id = 508, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1203, .cpu_id = 509, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1204, .cpu_id = 510, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1205, .cpu_id = 511, .valid = 0, + .msg = 0, .reset = 0, .name = "" }, + { .fc_id = 1206, .cpu_id = 512, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC0_QM" }, + { .fc_id = 1207, .cpu_id = 513, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC1_QM" }, + { .fc_id = 1208, .cpu_id = 514, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC2_QM" }, + { .fc_id = 1209, .cpu_id = 515, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC3_QM" }, + { .fc_id = 1210, .cpu_id = 516, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC4_QM" }, + { .fc_id = 1211, .cpu_id = 517, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC5_QM" }, + { .fc_id = 1212, .cpu_id = 518, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC6_QM" }, + { .fc_id = 1213, .cpu_id = 519, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC7_QM" }, + { .fc_id = 1214, .cpu_id = 520, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC8_QM" }, + { .fc_id = 1215, .cpu_id = 521, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC9_QM" }, + { .fc_id = 1216, .cpu_id = 522, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC10_QM" }, + { .fc_id = 1217, .cpu_id = 523, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC11_QM" }, + { .fc_id = 1218, .cpu_id = 524, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC12_QM" }, + { .fc_id = 1219, .cpu_id = 525, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC13_QM" }, + { .fc_id = 1220, .cpu_id = 526, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC14_QM" }, + { .fc_id = 1221, .cpu_id = 527, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC15_QM" }, + { .fc_id = 1222, .cpu_id = 528, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC16_QM" }, + { .fc_id = 1223, .cpu_id = 529, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC17_QM" }, + { .fc_id = 1224, .cpu_id = 530, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC18_QM" }, + { .fc_id = 1225, .cpu_id = 531, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC19_QM" }, + { .fc_id = 1226, .cpu_id = 532, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC20_QM" }, + { .fc_id = 1227, .cpu_id = 533, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC21_QM" }, + { .fc_id = 1228, .cpu_id = 534, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC22_QM" }, + { .fc_id = 1229, .cpu_id = 535, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC23_QM" }, + { .fc_id = 1230, .cpu_id = 536, .valid = 1, + .msg = 1, .reset = 0, .name = "TPC24_QM" }, + { .fc_id = 1231, .cpu_id = 537, .valid = 0, + .msg = 1, .reset = 0, .name = "" }, + { .fc_id = 1232, .cpu_id = 538, .valid = 1, + .msg = 1, .reset = 0, .name = "MME0_QM" }, + { .fc_id = 1233, .cpu_id = 539, .valid = 1, + .msg = 1, .reset = 0, .name = "MME1_QM" }, + { .fc_id = 1234, .cpu_id = 540, .valid = 1, + .msg = 1, .reset = 0, .name = "MME2_QM" }, + { .fc_id = 1235, .cpu_id = 541, .valid = 1, + .msg = 1, .reset = 0, .name = "MME3_QM" }, + { .fc_id = 1236, .cpu_id = 542, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA2_QM" }, + { .fc_id = 1237, .cpu_id = 543, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA3_QM" }, + { .fc_id = 1238, .cpu_id = 544, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA0_QM" }, + { .fc_id = 1239, .cpu_id = 545, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA1_QM" }, + { .fc_id = 1240, .cpu_id = 546, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA6_QM" }, + { .fc_id = 1241, .cpu_id = 547, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA7_QM" }, + { .fc_id = 1242, .cpu_id = 548, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA4_QM" }, + { .fc_id = 1243, .cpu_id = 549, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA5_QM" }, + { .fc_id = 1244, .cpu_id = 550, .valid = 1, + .msg = 1, .reset = 0, .name = "PDMA0_QM" }, + { .fc_id = 1245, .cpu_id = 551, .valid = 1, + .msg = 1, .reset = 0, .name = "PDMA1_QM" }, + { .fc_id = 1246, .cpu_id = 552, .valid = 1, + .msg = 1, .reset = 0, .name = "PI_UPDATE" }, + { .fc_id = 1247, .cpu_id = 553, .valid = 1, + .msg = 1, .reset = 0, .name = "HALT_MACHINE" }, + { .fc_id = 1248, .cpu_id = 554, .valid = 1, + .msg = 1, .reset = 0, .name = "INTS_REGISTER" }, + { .fc_id = 1249, .cpu_id = 555, .valid = 1, + .msg = 1, .reset = 0, .name = "ROT0_QM" }, + { .fc_id = 1250, .cpu_id = 556, .valid = 1, + .msg = 1, .reset = 0, .name = "ROT1_QM" }, + { .fc_id = 1251, .cpu_id = 557, .valid = 1, + .msg = 1, .reset = 0, .name = "SOFT_RESET" }, + { .fc_id = 1252, .cpu_id = 558, .valid = 1, + .msg = 1, .reset = 0, .name = "CPLD_SHUTDOWN_CAUSE" }, + { .fc_id = 1253, .cpu_id = 559, .valid = 1, + .msg = 1, .reset = 0, .name = "FIX_POWER_ENV_S" }, + { .fc_id = 1254, .cpu_id = 560, .valid = 1, + .msg = 1, .reset = 0, .name = "FIX_POWER_ENV_E" }, + { .fc_id = 1255, .cpu_id = 561, .valid = 1, + .msg = 1, .reset = 0, .name = "FIX_THERMAL_ENV_S" }, + { .fc_id = 1256, .cpu_id = 562, .valid = 1, + .msg = 1, .reset = 0, .name = "FIX_THERMAL_ENV_E" }, + { .fc_id = 1257, .cpu_id = 563, .valid = 1, + .msg = 1, .reset = 0, .name = "CPLD_SHUTDOWN_EVENT" }, + { .fc_id = 1258, .cpu_id = 564, .valid = 1, + .msg = 1, .reset = 0, .name = "PKT_QUEUE_OUT_SYNC" }, + { .fc_id = 1259, .cpu_id = 565, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA2_CORE" }, + { .fc_id = 1260, .cpu_id = 566, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA3_CORE" }, + { .fc_id = 1261, .cpu_id = 567, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA0_CORE" }, + { .fc_id = 1262, .cpu_id = 568, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA1_CORE" }, + { .fc_id = 1263, .cpu_id = 569, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA6_CORE" }, + { .fc_id = 1264, .cpu_id = 570, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA7_CORE" }, + { .fc_id = 1265, .cpu_id = 571, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA4_CORE" }, + { .fc_id = 1266, .cpu_id = 572, .valid = 1, + .msg = 1, .reset = 0, .name = "HDMA5_CORE" }, + { .fc_id = 1267, .cpu_id = 573, .valid = 1, + .msg = 1, .reset = 0, .name = "PDMA0_CORE" }, + { .fc_id = 1268, .cpu_id = 574, .valid = 1, + .msg = 1, .reset = 0, .name = "PDMA1_CORE" }, + { .fc_id = 1269, .cpu_id = 575, .valid = 1, + .msg = 1, .reset = 0, .name = "KDMA0_CORE" }, + { .fc_id = 1270, .cpu_id = 576, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC0_QM0" }, + { .fc_id = 1271, .cpu_id = 577, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC0_QM1" }, + { .fc_id = 1272, .cpu_id = 578, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC1_QM0" }, + { .fc_id = 1273, .cpu_id = 579, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC1_QM1" }, + { .fc_id = 1274, .cpu_id = 580, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC2_QM0" }, + { .fc_id = 1275, .cpu_id = 581, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC2_QM1" }, + { .fc_id = 1276, .cpu_id = 582, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC3_QM0" }, + { .fc_id = 1277, .cpu_id = 583, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC3_QM1" }, + { .fc_id = 1278, .cpu_id = 584, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC4_QM0" }, + { .fc_id = 1279, .cpu_id = 585, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC4_QM1" }, + { .fc_id = 1280, .cpu_id = 586, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC5_QM0" }, + { .fc_id = 1281, .cpu_id = 587, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC5_QM1" }, + { .fc_id = 1282, .cpu_id = 588, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC6_QM0" }, + { .fc_id = 1283, .cpu_id = 589, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC6_QM1" }, + { .fc_id = 1284, .cpu_id = 590, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC7_QM0" }, + { .fc_id = 1285, .cpu_id = 591, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC7_QM1" }, + { .fc_id = 1286, .cpu_id = 592, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC8_QM0" }, + { .fc_id = 1287, .cpu_id = 593, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC8_QM1" }, + { .fc_id = 1288, .cpu_id = 594, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC9_QM0" }, + { .fc_id = 1289, .cpu_id = 595, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC9_QM1" }, + { .fc_id = 1290, .cpu_id = 596, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC10_QM0" }, + { .fc_id = 1291, .cpu_id = 597, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC10_QM1" }, + { .fc_id = 1292, .cpu_id = 598, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC11_QM0" }, + { .fc_id = 1293, .cpu_id = 599, .valid = 1, + .msg = 1, .reset = 0, .name = "NIC11_QM1" }, + { .fc_id = 1294, .cpu_id = 600, .valid = 1, + .msg = 1, .reset = 0, .name = "CPU_PKT_SANITY_FAILED" }, + { .fc_id = 1295, .cpu_id = 601, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC0_ENG0" }, + { .fc_id = 1296, .cpu_id = 602, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC0_ENG1" }, + { .fc_id = 1297, .cpu_id = 603, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC1_ENG0" }, + { .fc_id = 1298, .cpu_id = 604, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC1_ENG1" }, + { .fc_id = 1299, .cpu_id = 605, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC2_ENG0" }, + { .fc_id = 1300, .cpu_id = 606, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC2_ENG1" }, + { .fc_id = 1301, .cpu_id = 607, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC3_ENG0" }, + { .fc_id = 1302, .cpu_id = 608, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC3_ENG1" }, + { .fc_id = 1303, .cpu_id = 609, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC4_ENG0" }, + { .fc_id = 1304, .cpu_id = 610, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC4_ENG1" }, + { .fc_id = 1305, .cpu_id = 611, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC5_ENG0" }, + { .fc_id = 1306, .cpu_id = 612, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC5_ENG1" }, + { .fc_id = 1307, .cpu_id = 613, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC6_ENG0" }, + { .fc_id = 1308, .cpu_id = 614, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC6_ENG1" }, + { .fc_id = 1309, .cpu_id = 615, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC7_ENG0" }, + { .fc_id = 1310, .cpu_id = 616, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC7_ENG1" }, + { .fc_id = 1311, .cpu_id = 617, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC8_ENG0" }, + { .fc_id = 1312, .cpu_id = 618, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC8_ENG1" }, + { .fc_id = 1313, .cpu_id = 619, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC9_ENG0" }, + { .fc_id = 1314, .cpu_id = 620, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC9_ENG1" }, + { .fc_id = 1315, .cpu_id = 621, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC10_ENG0" }, + { .fc_id = 1316, .cpu_id = 622, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC10_ENG1" }, + { .fc_id = 1317, .cpu_id = 623, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC11_ENG0" }, + { .fc_id = 1318, .cpu_id = 624, .valid = 1, + .msg = 1, .reset = 0, .name = "STATUS_NIC11_ENG1" }, + { .fc_id = 1319, .cpu_id = 625, .valid = 1, + .msg = 1, .reset = 0, .name = "ARC_DCCM_FULL" }, +}; + +#endif /* __GAUDI2_ASYNC_IDS_MAP_EVENTS_EXT_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/gaudi2_async_virt_events.h b/drivers/misc/habanalabs/include/gaudi2/gaudi2_async_virt_events.h new file mode 100644 index 000000000000..6d6ed7838a64 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/gaudi2_async_virt_events.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2022 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef __GAUDI2_ASYNC_VIRT_EVENTS_H_ +#define __GAUDI2_ASYNC_VIRT_EVENTS_H_ + +enum gaudi2_async_virt_event_id { + GAUDI2_EVENT_NIC3_QM1_OLD = 1206, + GAUDI2_EVENT_NIC4_QM0_OLD = 1207, + GAUDI2_EVENT_NIC4_QM1_OLD = 1208, + GAUDI2_EVENT_NIC5_QM0_OLD = 1209, + GAUDI2_EVENT_NIC5_QM1_OLD = 1210, + GAUDI2_EVENT_NIC6_QM0_OLD = 1211, + GAUDI2_EVENT_NIC6_QM1_OLD = 1212, + GAUDI2_EVENT_NIC7_QM0_OLD = 1213, + GAUDI2_EVENT_NIC7_QM1_OLD = 1214, + GAUDI2_EVENT_NIC8_QM0_OLD = 1215, + GAUDI2_EVENT_NIC8_QM1_OLD = 1216, + GAUDI2_EVENT_NIC9_QM0_OLD = 1217, + GAUDI2_EVENT_NIC9_QM1_OLD = 1218, + GAUDI2_EVENT_NIC10_QM0_OLD = 1219, + GAUDI2_EVENT_NIC10_QM1_OLD = 1220, + GAUDI2_EVENT_NIC11_QM0_OLD = 1221, + GAUDI2_EVENT_NIC11_QM1_OLD = 1222, + GAUDI2_EVENT_CPU_PKT_SANITY_FAILED_OLD = 1223, + GAUDI2_EVENT_CPU0_STATUS_NIC0_ENG0_OLD = 1224, + GAUDI2_EVENT_CPU0_STATUS_NIC0_ENG1_OLD = 1225, + GAUDI2_EVENT_CPU1_STATUS_NIC1_ENG0_OLD = 1226, + GAUDI2_EVENT_CPU1_STATUS_NIC1_ENG1_OLD = 1227, + GAUDI2_EVENT_CPU2_STATUS_NIC2_ENG0_OLD = 1228, + GAUDI2_EVENT_CPU2_STATUS_NIC2_ENG1_OLD = 1229, + GAUDI2_EVENT_CPU3_STATUS_NIC3_ENG0_OLD = 1230, + GAUDI2_EVENT_CPU3_STATUS_NIC3_ENG1_OLD = 1231, + GAUDI2_EVENT_CPU4_STATUS_NIC4_ENG0_OLD = 1232, + GAUDI2_EVENT_CPU4_STATUS_NIC4_ENG1_OLD = 1233, + GAUDI2_EVENT_CPU5_STATUS_NIC5_ENG0_OLD = 1234, + GAUDI2_EVENT_CPU5_STATUS_NIC5_ENG1_OLD = 1235, + GAUDI2_EVENT_CPU6_STATUS_NIC6_ENG0_OLD = 1236, + GAUDI2_EVENT_CPU6_STATUS_NIC6_ENG1_OLD = 1237, + GAUDI2_EVENT_CPU7_STATUS_NIC7_ENG0_OLD = 1238, + GAUDI2_EVENT_CPU7_STATUS_NIC7_ENG1_OLD = 1239, + GAUDI2_EVENT_CPU8_STATUS_NIC8_ENG0_OLD = 1240, + GAUDI2_EVENT_CPU8_STATUS_NIC8_ENG1_OLD = 1241, + GAUDI2_EVENT_CPU9_STATUS_NIC9_ENG0_OLD = 1242, + GAUDI2_EVENT_CPU9_STATUS_NIC9_ENG1_OLD = 1243, + GAUDI2_EVENT_CPU10_STATUS_NIC10_ENG0_OLD = 1244, + GAUDI2_EVENT_CPU10_STATUS_NIC10_ENG1_OLD = 1245, + GAUDI2_EVENT_CPU11_STATUS_NIC11_ENG0_OLD = 1246, + GAUDI2_EVENT_CPU11_STATUS_NIC11_ENG1_OLD = 1247, + GAUDI2_EVENT_ARC_DCCM_FULL_OLD = 1248, +}; + +#endif /* __GAUDI2_ASYNC_VIRT_EVENTS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi2/gaudi2_coresight.h b/drivers/misc/habanalabs/include/gaudi2/gaudi2_coresight.h new file mode 100644 index 000000000000..14f09d7758c7 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/gaudi2_coresight.h @@ -0,0 +1,984 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef GAUDI2_CORESIGHT_H +#define GAUDI2_CORESIGHT_H + +enum gaudi2_debug_stm_regs_index { + GAUDI2_STM_FIRST = 0, + GAUDI2_STM_DCORE0_TPC0_EML = GAUDI2_STM_FIRST, + GAUDI2_STM_DCORE0_TPC1_EML, + GAUDI2_STM_DCORE0_TPC2_EML, + GAUDI2_STM_DCORE0_TPC3_EML, + GAUDI2_STM_DCORE0_TPC4_EML, + GAUDI2_STM_DCORE0_TPC5_EML, + GAUDI2_STM_DCORE0_TPC6_EML, + GAUDI2_STM_DCORE1_TPC0_EML, + GAUDI2_STM_DCORE1_TPC1_EML, + GAUDI2_STM_DCORE1_TPC2_EML, + GAUDI2_STM_DCORE1_TPC3_EML, + GAUDI2_STM_DCORE1_TPC4_EML, + GAUDI2_STM_DCORE1_TPC5_EML, + GAUDI2_STM_DCORE2_TPC0_EML, + GAUDI2_STM_DCORE2_TPC1_EML, + GAUDI2_STM_DCORE2_TPC2_EML, + GAUDI2_STM_DCORE2_TPC3_EML, + GAUDI2_STM_DCORE2_TPC4_EML, + GAUDI2_STM_DCORE2_TPC5_EML, + GAUDI2_STM_DCORE3_TPC0_EML, + GAUDI2_STM_DCORE3_TPC1_EML, + GAUDI2_STM_DCORE3_TPC2_EML, + GAUDI2_STM_DCORE3_TPC3_EML, + GAUDI2_STM_DCORE3_TPC4_EML, + GAUDI2_STM_DCORE3_TPC5_EML, + GAUDI2_STM_DCORE0_HMMU0_CS, + GAUDI2_STM_DCORE0_HMMU1_CS, + GAUDI2_STM_DCORE0_HMMU2_CS, + GAUDI2_STM_DCORE0_HMMU3_CS, + GAUDI2_STM_DCORE0_MME_CTRL, + GAUDI2_STM_DCORE0_MME_SBTE0, + GAUDI2_STM_DCORE0_MME_SBTE1, + GAUDI2_STM_DCORE0_MME_SBTE2, + GAUDI2_STM_DCORE0_MME_SBTE3, + GAUDI2_STM_DCORE0_MME_SBTE4, + GAUDI2_STM_DCORE0_MME_ACC, + GAUDI2_STM_DCORE0_SM, + GAUDI2_STM_DCORE0_EDMA0_CS, + GAUDI2_STM_DCORE0_EDMA1_CS, + GAUDI2_STM_DCORE0_VDEC0_CS, + GAUDI2_STM_DCORE0_VDEC1_CS, + GAUDI2_STM_DCORE1_HMMU0_CS, + GAUDI2_STM_DCORE1_HMMU1_CS, + GAUDI2_STM_DCORE1_HMMU2_CS, + GAUDI2_STM_DCORE1_HMMU3_CS, + GAUDI2_STM_DCORE1_MME_CTRL, + GAUDI2_STM_DCORE1_MME_SBTE0, + GAUDI2_STM_DCORE1_MME_SBTE1, + GAUDI2_STM_DCORE1_MME_SBTE2, + GAUDI2_STM_DCORE1_MME_SBTE3, + GAUDI2_STM_DCORE1_MME_SBTE4, + GAUDI2_STM_DCORE1_MME_ACC, + GAUDI2_STM_DCORE1_SM, + GAUDI2_STM_DCORE1_EDMA0_CS, + GAUDI2_STM_DCORE1_EDMA1_CS, + GAUDI2_STM_DCORE1_VDEC0_CS, + GAUDI2_STM_DCORE1_VDEC1_CS, + GAUDI2_STM_DCORE2_HMMU0_CS, + GAUDI2_STM_DCORE2_HMMU1_CS, + GAUDI2_STM_DCORE2_HMMU2_CS, + GAUDI2_STM_DCORE2_HMMU3_CS, + GAUDI2_STM_DCORE2_MME_CTRL, + GAUDI2_STM_DCORE2_MME_SBTE0, + GAUDI2_STM_DCORE2_MME_SBTE1, + GAUDI2_STM_DCORE2_MME_SBTE2, + GAUDI2_STM_DCORE2_MME_SBTE3, + GAUDI2_STM_DCORE2_MME_SBTE4, + GAUDI2_STM_DCORE2_MME_ACC, + GAUDI2_STM_DCORE2_SM, + GAUDI2_STM_DCORE2_EDMA0_CS, + GAUDI2_STM_DCORE2_EDMA1_CS, + GAUDI2_STM_DCORE2_VDEC0_CS, + GAUDI2_STM_DCORE2_VDEC1_CS, + GAUDI2_STM_DCORE3_HMMU0_CS, + GAUDI2_STM_DCORE3_HMMU1_CS, + GAUDI2_STM_DCORE3_HMMU2_CS, + GAUDI2_STM_DCORE3_HMMU3_CS, + GAUDI2_STM_DCORE3_MME_CTRL, + GAUDI2_STM_DCORE3_MME_SBTE0, + GAUDI2_STM_DCORE3_MME_SBTE1, + GAUDI2_STM_DCORE3_MME_SBTE2, + GAUDI2_STM_DCORE3_MME_SBTE3, + GAUDI2_STM_DCORE3_MME_SBTE4, + GAUDI2_STM_DCORE3_MME_ACC, + GAUDI2_STM_DCORE3_SM, + GAUDI2_STM_DCORE3_EDMA0_CS, + GAUDI2_STM_DCORE3_EDMA1_CS, + GAUDI2_STM_DCORE3_VDEC0_CS, + GAUDI2_STM_DCORE3_VDEC1_CS, + GAUDI2_STM_PCIE, + GAUDI2_STM_PSOC, + GAUDI2_STM_PSOC_ARC0_CS, + GAUDI2_STM_PSOC_ARC1_CS, + GAUDI2_STM_PDMA0_CS, + GAUDI2_STM_PDMA1_CS, + GAUDI2_STM_CPU, + GAUDI2_STM_PMMU_CS, + GAUDI2_STM_ROT0_CS, + GAUDI2_STM_ROT1_CS, + GAUDI2_STM_ARC_FARM_CS, + GAUDI2_STM_KDMA_CS, + GAUDI2_STM_PCIE_VDEC0_CS, + GAUDI2_STM_PCIE_VDEC1_CS, + GAUDI2_STM_HBM0_MC0_CS, + GAUDI2_STM_HBM0_MC1_CS, + GAUDI2_STM_HBM1_MC0_CS, + GAUDI2_STM_HBM1_MC1_CS, + GAUDI2_STM_HBM2_MC0_CS, + GAUDI2_STM_HBM2_MC1_CS, + GAUDI2_STM_HBM3_MC0_CS, + GAUDI2_STM_HBM3_MC1_CS, + GAUDI2_STM_HBM4_MC0_CS, + GAUDI2_STM_HBM4_MC1_CS, + GAUDI2_STM_HBM5_MC0_CS, + GAUDI2_STM_HBM5_MC1_CS, + GAUDI2_STM_NIC0_DBG_0, + GAUDI2_STM_NIC0_DBG_1, + GAUDI2_STM_NIC1_DBG_0, + GAUDI2_STM_NIC1_DBG_1, + GAUDI2_STM_NIC2_DBG_0, + GAUDI2_STM_NIC2_DBG_1, + GAUDI2_STM_NIC3_DBG_0, + GAUDI2_STM_NIC3_DBG_1, + GAUDI2_STM_NIC4_DBG_0, + GAUDI2_STM_NIC4_DBG_1, + GAUDI2_STM_NIC5_DBG_0, + GAUDI2_STM_NIC5_DBG_1, + GAUDI2_STM_NIC6_DBG_0, + GAUDI2_STM_NIC6_DBG_1, + GAUDI2_STM_NIC7_DBG_0, + GAUDI2_STM_NIC7_DBG_1, + GAUDI2_STM_NIC8_DBG_0, + GAUDI2_STM_NIC8_DBG_1, + GAUDI2_STM_NIC9_DBG_0, + GAUDI2_STM_NIC9_DBG_1, + GAUDI2_STM_NIC10_DBG_0, + GAUDI2_STM_NIC10_DBG_1, + GAUDI2_STM_NIC11_DBG_0, + GAUDI2_STM_NIC11_DBG_1, + GAUDI2_STM_LAST = GAUDI2_STM_NIC11_DBG_1 +}; + +enum gaudi2_debug_etf_regs_index { + GAUDI2_ETF_FIRST = 0, + GAUDI2_ETF_DCORE0_TPC0_EML = GAUDI2_ETF_FIRST, + GAUDI2_ETF_DCORE0_TPC1_EML, + GAUDI2_ETF_DCORE0_TPC2_EML, + GAUDI2_ETF_DCORE0_TPC3_EML, + GAUDI2_ETF_DCORE0_TPC4_EML, + GAUDI2_ETF_DCORE0_TPC5_EML, + GAUDI2_ETF_DCORE0_TPC6_EML, + GAUDI2_ETF_DCORE1_TPC0_EML, + GAUDI2_ETF_DCORE1_TPC1_EML, + GAUDI2_ETF_DCORE1_TPC2_EML, + GAUDI2_ETF_DCORE1_TPC3_EML, + GAUDI2_ETF_DCORE1_TPC4_EML, + GAUDI2_ETF_DCORE1_TPC5_EML, + GAUDI2_ETF_DCORE2_TPC0_EML, + GAUDI2_ETF_DCORE2_TPC1_EML, + GAUDI2_ETF_DCORE2_TPC2_EML, + GAUDI2_ETF_DCORE2_TPC3_EML, + GAUDI2_ETF_DCORE2_TPC4_EML, + GAUDI2_ETF_DCORE2_TPC5_EML, + GAUDI2_ETF_DCORE3_TPC0_EML, + GAUDI2_ETF_DCORE3_TPC1_EML, + GAUDI2_ETF_DCORE3_TPC2_EML, + GAUDI2_ETF_DCORE3_TPC3_EML, + GAUDI2_ETF_DCORE3_TPC4_EML, + GAUDI2_ETF_DCORE3_TPC5_EML, + GAUDI2_ETF_DCORE0_HMMU0_CS, + GAUDI2_ETF_DCORE0_HMMU1_CS, + GAUDI2_ETF_DCORE0_HMMU2_CS, + GAUDI2_ETF_DCORE0_HMMU3_CS, + GAUDI2_ETF_DCORE0_MME_CTRL, + GAUDI2_ETF_DCORE0_MME_SBTE0, + GAUDI2_ETF_DCORE0_MME_SBTE1, + GAUDI2_ETF_DCORE0_MME_SBTE2, + GAUDI2_ETF_DCORE0_MME_SBTE3, + GAUDI2_ETF_DCORE0_MME_SBTE4, + GAUDI2_ETF_DCORE0_MME_ACC, + GAUDI2_ETF_DCORE0_SM, + GAUDI2_ETF_DCORE0_EDMA0_CS, + GAUDI2_ETF_DCORE0_EDMA1_CS, + GAUDI2_ETF_DCORE0_VDEC0_CS, + GAUDI2_ETF_DCORE0_VDEC1_CS, + GAUDI2_ETF_DCORE1_HMMU0_CS, + GAUDI2_ETF_DCORE1_HMMU1_CS, + GAUDI2_ETF_DCORE1_HMMU2_CS, + GAUDI2_ETF_DCORE1_HMMU3_CS, + GAUDI2_ETF_DCORE1_MME_CTRL, + GAUDI2_ETF_DCORE1_MME_SBTE0, + GAUDI2_ETF_DCORE1_MME_SBTE1, + GAUDI2_ETF_DCORE1_MME_SBTE2, + GAUDI2_ETF_DCORE1_MME_SBTE3, + GAUDI2_ETF_DCORE1_MME_SBTE4, + GAUDI2_ETF_DCORE1_MME_ACC, + GAUDI2_ETF_DCORE1_SM, + GAUDI2_ETF_DCORE1_EDMA0_CS, + GAUDI2_ETF_DCORE1_EDMA1_CS, + GAUDI2_ETF_DCORE1_VDEC0_CS, + GAUDI2_ETF_DCORE1_VDEC1_CS, + GAUDI2_ETF_DCORE2_HMMU0_CS, + GAUDI2_ETF_DCORE2_HMMU1_CS, + GAUDI2_ETF_DCORE2_HMMU2_CS, + GAUDI2_ETF_DCORE2_HMMU3_CS, + GAUDI2_ETF_DCORE2_MME_CTRL, + GAUDI2_ETF_DCORE2_MME_SBTE0, + GAUDI2_ETF_DCORE2_MME_SBTE1, + GAUDI2_ETF_DCORE2_MME_SBTE2, + GAUDI2_ETF_DCORE2_MME_SBTE3, + GAUDI2_ETF_DCORE2_MME_SBTE4, + GAUDI2_ETF_DCORE2_MME_ACC, + GAUDI2_ETF_DCORE2_SM, + GAUDI2_ETF_DCORE2_EDMA0_CS, + GAUDI2_ETF_DCORE2_EDMA1_CS, + GAUDI2_ETF_DCORE2_VDEC0_CS, + GAUDI2_ETF_DCORE2_VDEC1_CS, + GAUDI2_ETF_DCORE3_HMMU0_CS, + GAUDI2_ETF_DCORE3_HMMU1_CS, + GAUDI2_ETF_DCORE3_HMMU2_CS, + GAUDI2_ETF_DCORE3_HMMU3_CS, + GAUDI2_ETF_DCORE3_MME_CTRL, + GAUDI2_ETF_DCORE3_MME_SBTE0, + GAUDI2_ETF_DCORE3_MME_SBTE1, + GAUDI2_ETF_DCORE3_MME_SBTE2, + GAUDI2_ETF_DCORE3_MME_SBTE3, + GAUDI2_ETF_DCORE3_MME_SBTE4, + GAUDI2_ETF_DCORE3_MME_ACC, + GAUDI2_ETF_DCORE3_SM, + GAUDI2_ETF_DCORE3_EDMA0_CS, + GAUDI2_ETF_DCORE3_EDMA1_CS, + GAUDI2_ETF_DCORE3_VDEC0_CS, + GAUDI2_ETF_DCORE3_VDEC1_CS, + GAUDI2_ETF_PCIE, + GAUDI2_ETF_PSOC, + GAUDI2_ETF_PSOC_ARC0_CS, + GAUDI2_ETF_PSOC_ARC1_CS, + GAUDI2_ETF_PDMA0_CS, + GAUDI2_ETF_PDMA1_CS, + GAUDI2_ETF_CPU_0, + GAUDI2_ETF_CPU_1, + GAUDI2_ETF_CPU_TRACE, + GAUDI2_ETF_PMMU_CS, + GAUDI2_ETF_ROT0_CS, + GAUDI2_ETF_ROT1_CS, + GAUDI2_ETF_ARC_FARM_CS, + GAUDI2_ETF_KDMA_CS, + GAUDI2_ETF_PCIE_VDEC0_CS, + GAUDI2_ETF_PCIE_VDEC1_CS, + GAUDI2_ETF_HBM0_MC0_CS, + GAUDI2_ETF_HBM0_MC1_CS, + GAUDI2_ETF_HBM1_MC0_CS, + GAUDI2_ETF_HBM1_MC1_CS, + GAUDI2_ETF_HBM2_MC0_CS, + GAUDI2_ETF_HBM2_MC1_CS, + GAUDI2_ETF_HBM3_MC0_CS, + GAUDI2_ETF_HBM3_MC1_CS, + GAUDI2_ETF_HBM4_MC0_CS, + GAUDI2_ETF_HBM4_MC1_CS, + GAUDI2_ETF_HBM5_MC0_CS, + GAUDI2_ETF_HBM5_MC1_CS, + GAUDI2_ETF_NIC0_DBG_0, + GAUDI2_ETF_NIC0_DBG_1, + GAUDI2_ETF_NIC1_DBG_0, + GAUDI2_ETF_NIC1_DBG_1, + GAUDI2_ETF_NIC2_DBG_0, + GAUDI2_ETF_NIC2_DBG_1, + GAUDI2_ETF_NIC3_DBG_0, + GAUDI2_ETF_NIC3_DBG_1, + GAUDI2_ETF_NIC4_DBG_0, + GAUDI2_ETF_NIC4_DBG_1, + GAUDI2_ETF_NIC5_DBG_0, + GAUDI2_ETF_NIC5_DBG_1, + GAUDI2_ETF_NIC6_DBG_0, + GAUDI2_ETF_NIC6_DBG_1, + GAUDI2_ETF_NIC7_DBG_0, + GAUDI2_ETF_NIC7_DBG_1, + GAUDI2_ETF_NIC8_DBG_0, + GAUDI2_ETF_NIC8_DBG_1, + GAUDI2_ETF_NIC9_DBG_0, + GAUDI2_ETF_NIC9_DBG_1, + GAUDI2_ETF_NIC10_DBG_0, + GAUDI2_ETF_NIC10_DBG_1, + GAUDI2_ETF_NIC11_DBG_0, + GAUDI2_ETF_NIC11_DBG_1, + GAUDI2_ETF_LAST = GAUDI2_ETF_NIC11_DBG_1 +}; + +enum gaudi2_debug_funnel_regs_index { + GAUDI2_FUNNEL_FIRST = 0, + GAUDI2_FUNNEL_DCORE0_TPC0_EML = GAUDI2_FUNNEL_FIRST, + GAUDI2_FUNNEL_DCORE0_TPC1_EML, + GAUDI2_FUNNEL_DCORE0_TPC2_EML, + GAUDI2_FUNNEL_DCORE0_TPC3_EML, + GAUDI2_FUNNEL_DCORE0_TPC4_EML, + GAUDI2_FUNNEL_DCORE0_TPC5_EML, + GAUDI2_FUNNEL_DCORE0_TPC6_EML, + GAUDI2_FUNNEL_DCORE1_TPC0_EML, + GAUDI2_FUNNEL_DCORE1_TPC1_EML, + GAUDI2_FUNNEL_DCORE1_TPC2_EML, + GAUDI2_FUNNEL_DCORE1_TPC3_EML, + GAUDI2_FUNNEL_DCORE1_TPC4_EML, + GAUDI2_FUNNEL_DCORE1_TPC5_EML, + GAUDI2_FUNNEL_DCORE2_TPC0_EML, + GAUDI2_FUNNEL_DCORE2_TPC1_EML, + GAUDI2_FUNNEL_DCORE2_TPC2_EML, + GAUDI2_FUNNEL_DCORE2_TPC3_EML, + GAUDI2_FUNNEL_DCORE2_TPC4_EML, + GAUDI2_FUNNEL_DCORE2_TPC5_EML, + GAUDI2_FUNNEL_DCORE3_TPC0_EML, + GAUDI2_FUNNEL_DCORE3_TPC1_EML, + GAUDI2_FUNNEL_DCORE3_TPC2_EML, + GAUDI2_FUNNEL_DCORE3_TPC3_EML, + GAUDI2_FUNNEL_DCORE3_TPC4_EML, + GAUDI2_FUNNEL_DCORE3_TPC5_EML, + GAUDI2_FUNNEL_DCORE0_XFT, + GAUDI2_FUNNEL_DCORE0_TFT0, + GAUDI2_FUNNEL_DCORE0_TFT1, + GAUDI2_FUNNEL_DCORE0_TFT2, + GAUDI2_FUNNEL_DCORE0_RTR0, + GAUDI2_FUNNEL_DCORE0_RTR1, + GAUDI2_FUNNEL_DCORE0_RTR2, + GAUDI2_FUNNEL_DCORE0_RTR3, + GAUDI2_FUNNEL_DCORE0_RTR4, + GAUDI2_FUNNEL_DCORE0_MIF0, + GAUDI2_FUNNEL_DCORE0_RTR5, + GAUDI2_FUNNEL_DCORE0_MIF1, + GAUDI2_FUNNEL_DCORE0_RTR6, + GAUDI2_FUNNEL_DCORE0_MIF2, + GAUDI2_FUNNEL_DCORE0_RTR7, + GAUDI2_FUNNEL_DCORE0_MIF3, + GAUDI2_FUNNEL_DCORE1_XFT, + GAUDI2_FUNNEL_DCORE1_TFT0, + GAUDI2_FUNNEL_DCORE1_TFT1, + GAUDI2_FUNNEL_DCORE1_TFT2, + GAUDI2_FUNNEL_DCORE1_RTR0, + GAUDI2_FUNNEL_DCORE1_MIF0, + GAUDI2_FUNNEL_DCORE1_RTR1, + GAUDI2_FUNNEL_DCORE1_MIF1, + GAUDI2_FUNNEL_DCORE1_RTR2, + GAUDI2_FUNNEL_DCORE1_MIF2, + GAUDI2_FUNNEL_DCORE1_RTR3, + GAUDI2_FUNNEL_DCORE1_MIF3, + GAUDI2_FUNNEL_DCORE1_RTR4, + GAUDI2_FUNNEL_DCORE1_RTR5, + GAUDI2_FUNNEL_DCORE1_RTR6, + GAUDI2_FUNNEL_DCORE1_RTR7, + GAUDI2_FUNNEL_DCORE2_XFT, + GAUDI2_FUNNEL_DCORE2_TFT0, + GAUDI2_FUNNEL_DCORE2_TFT1, + GAUDI2_FUNNEL_DCORE2_TFT2, + GAUDI2_FUNNEL_DCORE2_RTR0, + GAUDI2_FUNNEL_DCORE2_RTR1, + GAUDI2_FUNNEL_DCORE2_RTR2, + GAUDI2_FUNNEL_DCORE2_RTR3, + GAUDI2_FUNNEL_DCORE2_RTR4, + GAUDI2_FUNNEL_DCORE2_MIF0, + GAUDI2_FUNNEL_DCORE2_RTR5, + GAUDI2_FUNNEL_DCORE2_MIF1, + GAUDI2_FUNNEL_DCORE2_RTR6, + GAUDI2_FUNNEL_DCORE2_MIF2, + GAUDI2_FUNNEL_DCORE2_RTR7, + GAUDI2_FUNNEL_DCORE2_MIF3, + GAUDI2_FUNNEL_DCORE3_XFT, + GAUDI2_FUNNEL_DCORE3_TFT0, + GAUDI2_FUNNEL_DCORE3_TFT1, + GAUDI2_FUNNEL_DCORE3_TFT2, + GAUDI2_FUNNEL_DCORE3_RTR0, + GAUDI2_FUNNEL_DCORE3_MIF0, + GAUDI2_FUNNEL_DCORE3_RTR1, + GAUDI2_FUNNEL_DCORE3_MIF1, + GAUDI2_FUNNEL_DCORE3_RTR2, + GAUDI2_FUNNEL_DCORE3_MIF2, + GAUDI2_FUNNEL_DCORE3_RTR3, + GAUDI2_FUNNEL_DCORE3_MIF3, + GAUDI2_FUNNEL_DCORE3_RTR4, + GAUDI2_FUNNEL_DCORE3_RTR5, + GAUDI2_FUNNEL_DCORE3_RTR6, + GAUDI2_FUNNEL_DCORE3_RTR7, + GAUDI2_FUNNEL_PSOC, + GAUDI2_FUNNEL_PSOC_ARC0, + GAUDI2_FUNNEL_PSOC_ARC1, + GAUDI2_FUNNEL_XDMA, + GAUDI2_FUNNEL_CPU, + GAUDI2_FUNNEL_PMMU, + GAUDI2_FUNNEL_PMMU_DEC, + GAUDI2_FUNNEL_DCORE0_XBAR_MID, + GAUDI2_FUNNEL_DCORE0_XBAR_EDGE, + GAUDI2_FUNNEL_DCORE1_XBAR_MID, + GAUDI2_FUNNEL_DCORE1_XBAR_EDGE, + GAUDI2_FUNNEL_DCORE2_XBAR_MID, + GAUDI2_FUNNEL_DCORE2_XBAR_EDGE, + GAUDI2_FUNNEL_DCORE3_XBAR_MID, + GAUDI2_FUNNEL_DCORE3_XBAR_EDGE, + GAUDI2_FUNNEL_ARC_FARM, + GAUDI2_FUNNEL_HBM0_MC0, + GAUDI2_FUNNEL_HBM0_MC1, + GAUDI2_FUNNEL_HBM1_MC0, + GAUDI2_FUNNEL_HBM1_MC1, + GAUDI2_FUNNEL_HBM2_MC0, + GAUDI2_FUNNEL_HBM2_MC1, + GAUDI2_FUNNEL_HBM3_MC0, + GAUDI2_FUNNEL_HBM3_MC1, + GAUDI2_FUNNEL_HBM4_MC0, + GAUDI2_FUNNEL_HBM4_MC1, + GAUDI2_FUNNEL_HBM5_MC0, + GAUDI2_FUNNEL_HBM5_MC1, + GAUDI2_FUNNEL_NIC0_DBG_TX, + GAUDI2_FUNNEL_NIC0_DBG_NCH, + GAUDI2_FUNNEL_NIC1_DBG_TX, + GAUDI2_FUNNEL_NIC1_DBG_NCH, + GAUDI2_FUNNEL_NIC2_DBG_TX, + GAUDI2_FUNNEL_NIC2_DBG_NCH, + GAUDI2_FUNNEL_NIC3_DBG_TX, + GAUDI2_FUNNEL_NIC3_DBG_NCH, + GAUDI2_FUNNEL_NIC4_DBG_TX, + GAUDI2_FUNNEL_NIC4_DBG_NCH, + GAUDI2_FUNNEL_NIC5_DBG_TX, + GAUDI2_FUNNEL_NIC5_DBG_NCH, + GAUDI2_FUNNEL_NIC6_DBG_TX, + GAUDI2_FUNNEL_NIC6_DBG_NCH, + GAUDI2_FUNNEL_NIC7_DBG_TX, + GAUDI2_FUNNEL_NIC7_DBG_NCH, + GAUDI2_FUNNEL_NIC8_DBG_TX, + GAUDI2_FUNNEL_NIC8_DBG_NCH, + GAUDI2_FUNNEL_NIC9_DBG_TX, + GAUDI2_FUNNEL_NIC9_DBG_NCH, + GAUDI2_FUNNEL_NIC10_DBG_TX, + GAUDI2_FUNNEL_NIC10_DBG_NCH, + GAUDI2_FUNNEL_NIC11_DBG_TX, + GAUDI2_FUNNEL_NIC11_DBG_NCH, + GAUDI2_FUNNEL_LAST = GAUDI2_FUNNEL_NIC11_DBG_NCH +}; + +enum gaudi2_debug_bmon_regs_index { + GAUDI2_BMON_FIRST = 0, + GAUDI2_BMON_DCORE0_TPC0_EML_0 = GAUDI2_BMON_FIRST, + GAUDI2_BMON_DCORE0_TPC0_EML_1, + GAUDI2_BMON_DCORE0_TPC0_EML_2, + GAUDI2_BMON_DCORE0_TPC0_EML_3, + GAUDI2_BMON_DCORE0_TPC1_EML_0, + GAUDI2_BMON_DCORE0_TPC1_EML_1, + GAUDI2_BMON_DCORE0_TPC1_EML_2, + GAUDI2_BMON_DCORE0_TPC1_EML_3, + GAUDI2_BMON_DCORE0_TPC2_EML_0, + GAUDI2_BMON_DCORE0_TPC2_EML_1, + GAUDI2_BMON_DCORE0_TPC2_EML_2, + GAUDI2_BMON_DCORE0_TPC2_EML_3, + GAUDI2_BMON_DCORE0_TPC3_EML_0, + GAUDI2_BMON_DCORE0_TPC3_EML_1, + GAUDI2_BMON_DCORE0_TPC3_EML_2, + GAUDI2_BMON_DCORE0_TPC3_EML_3, + GAUDI2_BMON_DCORE0_TPC4_EML_0, + GAUDI2_BMON_DCORE0_TPC4_EML_1, + GAUDI2_BMON_DCORE0_TPC4_EML_2, + GAUDI2_BMON_DCORE0_TPC4_EML_3, + GAUDI2_BMON_DCORE0_TPC5_EML_0, + GAUDI2_BMON_DCORE0_TPC5_EML_1, + GAUDI2_BMON_DCORE0_TPC5_EML_2, + GAUDI2_BMON_DCORE0_TPC5_EML_3, + GAUDI2_BMON_DCORE0_TPC6_EML_0, + GAUDI2_BMON_DCORE0_TPC6_EML_1, + GAUDI2_BMON_DCORE0_TPC6_EML_2, + GAUDI2_BMON_DCORE0_TPC6_EML_3, + GAUDI2_BMON_DCORE1_TPC0_EML_0, + GAUDI2_BMON_DCORE1_TPC0_EML_1, + GAUDI2_BMON_DCORE1_TPC0_EML_2, + GAUDI2_BMON_DCORE1_TPC0_EML_3, + GAUDI2_BMON_DCORE1_TPC1_EML_0, + GAUDI2_BMON_DCORE1_TPC1_EML_1, + GAUDI2_BMON_DCORE1_TPC1_EML_2, + GAUDI2_BMON_DCORE1_TPC1_EML_3, + GAUDI2_BMON_DCORE1_TPC2_EML_0, + GAUDI2_BMON_DCORE1_TPC2_EML_1, + GAUDI2_BMON_DCORE1_TPC2_EML_2, + GAUDI2_BMON_DCORE1_TPC2_EML_3, + GAUDI2_BMON_DCORE1_TPC3_EML_0, + GAUDI2_BMON_DCORE1_TPC3_EML_1, + GAUDI2_BMON_DCORE1_TPC3_EML_2, + GAUDI2_BMON_DCORE1_TPC3_EML_3, + GAUDI2_BMON_DCORE1_TPC4_EML_0, + GAUDI2_BMON_DCORE1_TPC4_EML_1, + GAUDI2_BMON_DCORE1_TPC4_EML_2, + GAUDI2_BMON_DCORE1_TPC4_EML_3, + GAUDI2_BMON_DCORE1_TPC5_EML_0, + GAUDI2_BMON_DCORE1_TPC5_EML_1, + GAUDI2_BMON_DCORE1_TPC5_EML_2, + GAUDI2_BMON_DCORE1_TPC5_EML_3, + GAUDI2_BMON_DCORE2_TPC0_EML_0, + GAUDI2_BMON_DCORE2_TPC0_EML_1, + GAUDI2_BMON_DCORE2_TPC0_EML_2, + GAUDI2_BMON_DCORE2_TPC0_EML_3, + GAUDI2_BMON_DCORE2_TPC1_EML_0, + GAUDI2_BMON_DCORE2_TPC1_EML_1, + GAUDI2_BMON_DCORE2_TPC1_EML_2, + GAUDI2_BMON_DCORE2_TPC1_EML_3, + GAUDI2_BMON_DCORE2_TPC2_EML_0, + GAUDI2_BMON_DCORE2_TPC2_EML_1, + GAUDI2_BMON_DCORE2_TPC2_EML_2, + GAUDI2_BMON_DCORE2_TPC2_EML_3, + GAUDI2_BMON_DCORE2_TPC3_EML_0, + GAUDI2_BMON_DCORE2_TPC3_EML_1, + GAUDI2_BMON_DCORE2_TPC3_EML_2, + GAUDI2_BMON_DCORE2_TPC3_EML_3, + GAUDI2_BMON_DCORE2_TPC4_EML_0, + GAUDI2_BMON_DCORE2_TPC4_EML_1, + GAUDI2_BMON_DCORE2_TPC4_EML_2, + GAUDI2_BMON_DCORE2_TPC4_EML_3, + GAUDI2_BMON_DCORE2_TPC5_EML_0, + GAUDI2_BMON_DCORE2_TPC5_EML_1, + GAUDI2_BMON_DCORE2_TPC5_EML_2, + GAUDI2_BMON_DCORE2_TPC5_EML_3, + GAUDI2_BMON_DCORE3_TPC0_EML_0, + GAUDI2_BMON_DCORE3_TPC0_EML_1, + GAUDI2_BMON_DCORE3_TPC0_EML_2, + GAUDI2_BMON_DCORE3_TPC0_EML_3, + GAUDI2_BMON_DCORE3_TPC1_EML_0, + GAUDI2_BMON_DCORE3_TPC1_EML_1, + GAUDI2_BMON_DCORE3_TPC1_EML_2, + GAUDI2_BMON_DCORE3_TPC1_EML_3, + GAUDI2_BMON_DCORE3_TPC2_EML_0, + GAUDI2_BMON_DCORE3_TPC2_EML_1, + GAUDI2_BMON_DCORE3_TPC2_EML_2, + GAUDI2_BMON_DCORE3_TPC2_EML_3, + GAUDI2_BMON_DCORE3_TPC3_EML_0, + GAUDI2_BMON_DCORE3_TPC3_EML_1, + GAUDI2_BMON_DCORE3_TPC3_EML_2, + GAUDI2_BMON_DCORE3_TPC3_EML_3, + GAUDI2_BMON_DCORE3_TPC4_EML_0, + GAUDI2_BMON_DCORE3_TPC4_EML_1, + GAUDI2_BMON_DCORE3_TPC4_EML_2, + GAUDI2_BMON_DCORE3_TPC4_EML_3, + GAUDI2_BMON_DCORE3_TPC5_EML_0, + GAUDI2_BMON_DCORE3_TPC5_EML_1, + GAUDI2_BMON_DCORE3_TPC5_EML_2, + GAUDI2_BMON_DCORE3_TPC5_EML_3, + GAUDI2_BMON_DCORE0_HMMU0_0, + GAUDI2_BMON_DCORE0_HMMU0_1, + GAUDI2_BMON_DCORE0_HMMU0_3, + GAUDI2_BMON_DCORE0_HMMU0_2, + GAUDI2_BMON_DCORE0_HMMU0_4, + GAUDI2_BMON_DCORE0_HMMU1_0, + GAUDI2_BMON_DCORE0_HMMU1_1, + GAUDI2_BMON_DCORE0_HMMU1_3, + GAUDI2_BMON_DCORE0_HMMU1_2, + GAUDI2_BMON_DCORE0_HMMU1_4, + GAUDI2_BMON_DCORE0_HMMU2_0, + GAUDI2_BMON_DCORE0_HMMU2_1, + GAUDI2_BMON_DCORE0_HMMU2_3, + GAUDI2_BMON_DCORE0_HMMU2_2, + GAUDI2_BMON_DCORE0_HMMU2_4, + GAUDI2_BMON_DCORE0_HMMU3_0, + GAUDI2_BMON_DCORE0_HMMU3_1, + GAUDI2_BMON_DCORE0_HMMU3_3, + GAUDI2_BMON_DCORE0_HMMU3_2, + GAUDI2_BMON_DCORE0_HMMU3_4, + GAUDI2_BMON_DCORE0_MME_CTRL_0, + GAUDI2_BMON_DCORE0_MME_CTRL_1, + GAUDI2_BMON_DCORE0_MME_CTRL_2, + GAUDI2_BMON_DCORE0_MME_CTRL_3, + GAUDI2_BMON_DCORE0_MME_SBTE0_0, + GAUDI2_BMON_DCORE0_MME_SBTE1_0, + GAUDI2_BMON_DCORE0_MME_SBTE2_0, + GAUDI2_BMON_DCORE0_MME_SBTE3_0, + GAUDI2_BMON_DCORE0_MME_SBTE4_0, + GAUDI2_BMON_DCORE0_MME_ACC_0, + GAUDI2_BMON_DCORE0_MME_ACC_1, + GAUDI2_BMON_DCORE0_SM, + GAUDI2_BMON_DCORE0_SM_1, + GAUDI2_BMON_DCORE0_EDMA0_0, + GAUDI2_BMON_DCORE0_EDMA0_1, + GAUDI2_BMON_DCORE0_EDMA1_0, + GAUDI2_BMON_DCORE0_EDMA1_1, + GAUDI2_BMON_DCORE0_VDEC0_0, + GAUDI2_BMON_DCORE0_VDEC0_1, + GAUDI2_BMON_DCORE0_VDEC0_2, + GAUDI2_BMON_DCORE0_VDEC1_0, + GAUDI2_BMON_DCORE0_VDEC1_1, + GAUDI2_BMON_DCORE0_VDEC1_2, + GAUDI2_BMON_DCORE1_HMMU0_0, + GAUDI2_BMON_DCORE1_HMMU0_1, + GAUDI2_BMON_DCORE1_HMMU0_3, + GAUDI2_BMON_DCORE1_HMMU0_2, + GAUDI2_BMON_DCORE1_HMMU0_4, + GAUDI2_BMON_DCORE1_HMMU1_0, + GAUDI2_BMON_DCORE1_HMMU1_1, + GAUDI2_BMON_DCORE1_HMMU1_3, + GAUDI2_BMON_DCORE1_HMMU1_2, + GAUDI2_BMON_DCORE1_HMMU1_4, + GAUDI2_BMON_DCORE1_HMMU2_0, + GAUDI2_BMON_DCORE1_HMMU2_1, + GAUDI2_BMON_DCORE1_HMMU2_3, + GAUDI2_BMON_DCORE1_HMMU2_2, + GAUDI2_BMON_DCORE1_HMMU2_4, + GAUDI2_BMON_DCORE1_HMMU3_0, + GAUDI2_BMON_DCORE1_HMMU3_1, + GAUDI2_BMON_DCORE1_HMMU3_3, + GAUDI2_BMON_DCORE1_HMMU3_2, + GAUDI2_BMON_DCORE1_HMMU3_4, + GAUDI2_BMON_DCORE1_MME_CTRL_0, + GAUDI2_BMON_DCORE1_MME_CTRL_1, + GAUDI2_BMON_DCORE1_MME_CTRL_2, + GAUDI2_BMON_DCORE1_MME_CTRL_3, + GAUDI2_BMON_DCORE1_MME_SBTE0_0, + GAUDI2_BMON_DCORE1_MME_SBTE1_0, + GAUDI2_BMON_DCORE1_MME_SBTE2_0, + GAUDI2_BMON_DCORE1_MME_SBTE3_0, + GAUDI2_BMON_DCORE1_MME_SBTE4_0, + GAUDI2_BMON_DCORE1_MME_ACC_0, + GAUDI2_BMON_DCORE1_MME_ACC_1, + GAUDI2_BMON_DCORE1_SM, + GAUDI2_BMON_DCORE1_SM_1, + GAUDI2_BMON_DCORE1_EDMA0_0, + GAUDI2_BMON_DCORE1_EDMA0_1, + GAUDI2_BMON_DCORE1_EDMA1_0, + GAUDI2_BMON_DCORE1_EDMA1_1, + GAUDI2_BMON_DCORE1_VDEC0_0, + GAUDI2_BMON_DCORE1_VDEC0_1, + GAUDI2_BMON_DCORE1_VDEC0_2, + GAUDI2_BMON_DCORE1_VDEC1_0, + GAUDI2_BMON_DCORE1_VDEC1_1, + GAUDI2_BMON_DCORE1_VDEC1_2, + GAUDI2_BMON_DCORE2_HMMU0_0, + GAUDI2_BMON_DCORE2_HMMU0_1, + GAUDI2_BMON_DCORE2_HMMU0_3, + GAUDI2_BMON_DCORE2_HMMU0_2, + GAUDI2_BMON_DCORE2_HMMU0_4, + GAUDI2_BMON_DCORE2_HMMU1_0, + GAUDI2_BMON_DCORE2_HMMU1_1, + GAUDI2_BMON_DCORE2_HMMU1_3, + GAUDI2_BMON_DCORE2_HMMU1_2, + GAUDI2_BMON_DCORE2_HMMU1_4, + GAUDI2_BMON_DCORE2_HMMU2_0, + GAUDI2_BMON_DCORE2_HMMU2_1, + GAUDI2_BMON_DCORE2_HMMU2_3, + GAUDI2_BMON_DCORE2_HMMU2_2, + GAUDI2_BMON_DCORE2_HMMU2_4, + GAUDI2_BMON_DCORE2_HMMU3_0, + GAUDI2_BMON_DCORE2_HMMU3_1, + GAUDI2_BMON_DCORE2_HMMU3_3, + GAUDI2_BMON_DCORE2_HMMU3_2, + GAUDI2_BMON_DCORE2_HMMU3_4, + GAUDI2_BMON_DCORE2_MME_CTRL_0, + GAUDI2_BMON_DCORE2_MME_CTRL_1, + GAUDI2_BMON_DCORE2_MME_CTRL_2, + GAUDI2_BMON_DCORE2_MME_CTRL_3, + GAUDI2_BMON_DCORE2_MME_SBTE0_0, + GAUDI2_BMON_DCORE2_MME_SBTE1_0, + GAUDI2_BMON_DCORE2_MME_SBTE2_0, + GAUDI2_BMON_DCORE2_MME_SBTE3_0, + GAUDI2_BMON_DCORE2_MME_SBTE4_0, + GAUDI2_BMON_DCORE2_MME_ACC_0, + GAUDI2_BMON_DCORE2_MME_ACC_1, + GAUDI2_BMON_DCORE2_SM, + GAUDI2_BMON_DCORE2_SM_1, + GAUDI2_BMON_DCORE2_EDMA0_0, + GAUDI2_BMON_DCORE2_EDMA0_1, + GAUDI2_BMON_DCORE2_EDMA1_0, + GAUDI2_BMON_DCORE2_EDMA1_1, + GAUDI2_BMON_DCORE2_VDEC0_0, + GAUDI2_BMON_DCORE2_VDEC0_1, + GAUDI2_BMON_DCORE2_VDEC0_2, + GAUDI2_BMON_DCORE2_VDEC1_0, + GAUDI2_BMON_DCORE2_VDEC1_1, + GAUDI2_BMON_DCORE2_VDEC1_2, + GAUDI2_BMON_DCORE3_HMMU0_0, + GAUDI2_BMON_DCORE3_HMMU0_1, + GAUDI2_BMON_DCORE3_HMMU0_3, + GAUDI2_BMON_DCORE3_HMMU0_2, + GAUDI2_BMON_DCORE3_HMMU0_4, + GAUDI2_BMON_DCORE3_HMMU1_0, + GAUDI2_BMON_DCORE3_HMMU1_1, + GAUDI2_BMON_DCORE3_HMMU1_3, + GAUDI2_BMON_DCORE3_HMMU1_2, + GAUDI2_BMON_DCORE3_HMMU1_4, + GAUDI2_BMON_DCORE3_HMMU2_0, + GAUDI2_BMON_DCORE3_HMMU2_1, + GAUDI2_BMON_DCORE3_HMMU2_3, + GAUDI2_BMON_DCORE3_HMMU2_2, + GAUDI2_BMON_DCORE3_HMMU2_4, + GAUDI2_BMON_DCORE3_HMMU3_0, + GAUDI2_BMON_DCORE3_HMMU3_1, + GAUDI2_BMON_DCORE3_HMMU3_3, + GAUDI2_BMON_DCORE3_HMMU3_2, + GAUDI2_BMON_DCORE3_HMMU3_4, + GAUDI2_BMON_DCORE3_MME_CTRL_0, + GAUDI2_BMON_DCORE3_MME_CTRL_1, + GAUDI2_BMON_DCORE3_MME_CTRL_2, + GAUDI2_BMON_DCORE3_MME_CTRL_3, + GAUDI2_BMON_DCORE3_MME_SBTE0_0, + GAUDI2_BMON_DCORE3_MME_SBTE1_0, + GAUDI2_BMON_DCORE3_MME_SBTE2_0, + GAUDI2_BMON_DCORE3_MME_SBTE3_0, + GAUDI2_BMON_DCORE3_MME_SBTE4_0, + GAUDI2_BMON_DCORE3_MME_ACC_0, + GAUDI2_BMON_DCORE3_MME_ACC_1, + GAUDI2_BMON_DCORE3_SM, + GAUDI2_BMON_DCORE3_SM_1, + GAUDI2_BMON_DCORE3_EDMA0_0, + GAUDI2_BMON_DCORE3_EDMA0_1, + GAUDI2_BMON_DCORE3_EDMA1_0, + GAUDI2_BMON_DCORE3_EDMA1_1, + GAUDI2_BMON_DCORE3_VDEC0_0, + GAUDI2_BMON_DCORE3_VDEC0_1, + GAUDI2_BMON_DCORE3_VDEC0_2, + GAUDI2_BMON_DCORE3_VDEC1_0, + GAUDI2_BMON_DCORE3_VDEC1_1, + GAUDI2_BMON_DCORE3_VDEC1_2, + GAUDI2_BMON_PCIE_MSTR_WR, + GAUDI2_BMON_PCIE_MSTR_RD, + GAUDI2_BMON_PCIE_SLV_WR, + GAUDI2_BMON_PCIE_SLV_RD, + GAUDI2_BMON_PSOC_ARC0_0, + GAUDI2_BMON_PSOC_ARC0_1, + GAUDI2_BMON_PSOC_ARC1_0, + GAUDI2_BMON_PSOC_ARC1_1, + GAUDI2_BMON_PDMA0_0, + GAUDI2_BMON_PDMA0_1, + GAUDI2_BMON_PDMA1_0, + GAUDI2_BMON_PDMA1_1, + GAUDI2_BMON_CPU_WR, + GAUDI2_BMON_CPU_RD, + GAUDI2_BMON_PMMU_0, + GAUDI2_BMON_PMMU_1, + GAUDI2_BMON_PMMU_2, + GAUDI2_BMON_PMMU_3, + GAUDI2_BMON_PMMU_4, + GAUDI2_BMON_ROT0_0, + GAUDI2_BMON_ROT0_1, + GAUDI2_BMON_ROT0_2, + GAUDI2_BMON_ROT0_3, + GAUDI2_BMON_ROT1_0, + GAUDI2_BMON_ROT1_1, + GAUDI2_BMON_ROT1_2, + GAUDI2_BMON_ROT1_3, + GAUDI2_BMON_ARC_FARM_0, + GAUDI2_BMON_ARC_FARM_1, + GAUDI2_BMON_ARC_FARM_2, + GAUDI2_BMON_ARC_FARM_3, + GAUDI2_BMON_KDMA_0, + GAUDI2_BMON_KDMA_1, + GAUDI2_BMON_KDMA_2, + GAUDI2_BMON_KDMA_3, + GAUDI2_BMON_PCIE_VDEC0_0, + GAUDI2_BMON_PCIE_VDEC0_1, + GAUDI2_BMON_PCIE_VDEC0_2, + GAUDI2_BMON_PCIE_VDEC1_0, + GAUDI2_BMON_PCIE_VDEC1_1, + GAUDI2_BMON_PCIE_VDEC1_2, + GAUDI2_BMON_NIC0_DBG_0_0, + GAUDI2_BMON_NIC0_DBG_1_0, + GAUDI2_BMON_NIC0_DBG_2_0, + GAUDI2_BMON_NIC0_DBG_0_1, + GAUDI2_BMON_NIC0_DBG_1_1, + GAUDI2_BMON_NIC0_DBG_2_1, + GAUDI2_BMON_NIC1_DBG_0_0, + GAUDI2_BMON_NIC1_DBG_1_0, + GAUDI2_BMON_NIC1_DBG_2_0, + GAUDI2_BMON_NIC1_DBG_0_1, + GAUDI2_BMON_NIC1_DBG_1_1, + GAUDI2_BMON_NIC1_DBG_2_1, + GAUDI2_BMON_NIC2_DBG_0_0, + GAUDI2_BMON_NIC2_DBG_1_0, + GAUDI2_BMON_NIC2_DBG_2_0, + GAUDI2_BMON_NIC2_DBG_0_1, + GAUDI2_BMON_NIC2_DBG_1_1, + GAUDI2_BMON_NIC2_DBG_2_1, + GAUDI2_BMON_NIC3_DBG_0_0, + GAUDI2_BMON_NIC3_DBG_1_0, + GAUDI2_BMON_NIC3_DBG_2_0, + GAUDI2_BMON_NIC3_DBG_0_1, + GAUDI2_BMON_NIC3_DBG_1_1, + GAUDI2_BMON_NIC3_DBG_2_1, + GAUDI2_BMON_NIC4_DBG_0_0, + GAUDI2_BMON_NIC4_DBG_1_0, + GAUDI2_BMON_NIC4_DBG_2_0, + GAUDI2_BMON_NIC4_DBG_0_1, + GAUDI2_BMON_NIC4_DBG_1_1, + GAUDI2_BMON_NIC4_DBG_2_1, + GAUDI2_BMON_NIC5_DBG_0_0, + GAUDI2_BMON_NIC5_DBG_1_0, + GAUDI2_BMON_NIC5_DBG_2_0, + GAUDI2_BMON_NIC5_DBG_0_1, + GAUDI2_BMON_NIC5_DBG_1_1, + GAUDI2_BMON_NIC5_DBG_2_1, + GAUDI2_BMON_NIC6_DBG_0_0, + GAUDI2_BMON_NIC6_DBG_1_0, + GAUDI2_BMON_NIC6_DBG_2_0, + GAUDI2_BMON_NIC6_DBG_0_1, + GAUDI2_BMON_NIC6_DBG_1_1, + GAUDI2_BMON_NIC6_DBG_2_1, + GAUDI2_BMON_NIC7_DBG_0_0, + GAUDI2_BMON_NIC7_DBG_1_0, + GAUDI2_BMON_NIC7_DBG_2_0, + GAUDI2_BMON_NIC7_DBG_0_1, + GAUDI2_BMON_NIC7_DBG_1_1, + GAUDI2_BMON_NIC7_DBG_2_1, + GAUDI2_BMON_NIC8_DBG_0_0, + GAUDI2_BMON_NIC8_DBG_1_0, + GAUDI2_BMON_NIC8_DBG_2_0, + GAUDI2_BMON_NIC8_DBG_0_1, + GAUDI2_BMON_NIC8_DBG_1_1, + GAUDI2_BMON_NIC8_DBG_2_1, + GAUDI2_BMON_NIC9_DBG_0_0, + GAUDI2_BMON_NIC9_DBG_1_0, + GAUDI2_BMON_NIC9_DBG_2_0, + GAUDI2_BMON_NIC9_DBG_0_1, + GAUDI2_BMON_NIC9_DBG_1_1, + GAUDI2_BMON_NIC9_DBG_2_1, + GAUDI2_BMON_NIC10_DBG_0_0, + GAUDI2_BMON_NIC10_DBG_1_0, + GAUDI2_BMON_NIC10_DBG_2_0, + GAUDI2_BMON_NIC10_DBG_0_1, + GAUDI2_BMON_NIC10_DBG_1_1, + GAUDI2_BMON_NIC10_DBG_2_1, + GAUDI2_BMON_NIC11_DBG_0_0, + GAUDI2_BMON_NIC11_DBG_1_0, + GAUDI2_BMON_NIC11_DBG_2_0, + GAUDI2_BMON_NIC11_DBG_0_1, + GAUDI2_BMON_NIC11_DBG_1_1, + GAUDI2_BMON_NIC11_DBG_2_1, + GAUDI2_BMON_LAST = GAUDI2_BMON_NIC11_DBG_2_1 +}; + +enum gaudi2_debug_spmu_regs_index { + GAUDI2_SPMU_FIRST = 0, + GAUDI2_SPMU_DCORE0_TPC0_EML = GAUDI2_SPMU_FIRST, + GAUDI2_SPMU_DCORE0_TPC1_EML, + GAUDI2_SPMU_DCORE0_TPC2_EML, + GAUDI2_SPMU_DCORE0_TPC3_EML, + GAUDI2_SPMU_DCORE0_TPC4_EML, + GAUDI2_SPMU_DCORE0_TPC5_EML, + GAUDI2_SPMU_DCORE0_TPC6_EML, + GAUDI2_SPMU_DCORE1_TPC0_EML, + GAUDI2_SPMU_DCORE1_TPC1_EML, + GAUDI2_SPMU_DCORE1_TPC2_EML, + GAUDI2_SPMU_DCORE1_TPC3_EML, + GAUDI2_SPMU_DCORE1_TPC4_EML, + GAUDI2_SPMU_DCORE1_TPC5_EML, + GAUDI2_SPMU_DCORE2_TPC0_EML, + GAUDI2_SPMU_DCORE2_TPC1_EML, + GAUDI2_SPMU_DCORE2_TPC2_EML, + GAUDI2_SPMU_DCORE2_TPC3_EML, + GAUDI2_SPMU_DCORE2_TPC4_EML, + GAUDI2_SPMU_DCORE2_TPC5_EML, + GAUDI2_SPMU_DCORE3_TPC0_EML, + GAUDI2_SPMU_DCORE3_TPC1_EML, + GAUDI2_SPMU_DCORE3_TPC2_EML, + GAUDI2_SPMU_DCORE3_TPC3_EML, + GAUDI2_SPMU_DCORE3_TPC4_EML, + GAUDI2_SPMU_DCORE3_TPC5_EML, + GAUDI2_SPMU_DCORE0_HMMU0_CS, + GAUDI2_SPMU_DCORE0_HMMU1_CS, + GAUDI2_SPMU_DCORE0_HMMU2_CS, + GAUDI2_SPMU_DCORE0_HMMU3_CS, + GAUDI2_SPMU_DCORE0_MME_CTRL, + GAUDI2_SPMU_DCORE0_MME_SBTE0, + GAUDI2_SPMU_DCORE0_MME_SBTE1, + GAUDI2_SPMU_DCORE0_MME_SBTE2, + GAUDI2_SPMU_DCORE0_MME_SBTE3, + GAUDI2_SPMU_DCORE0_MME_SBTE4, + GAUDI2_SPMU_DCORE0_MME_ACC, + GAUDI2_SPMU_DCORE0_SM, + GAUDI2_SPMU_DCORE0_EDMA0_CS, + GAUDI2_SPMU_DCORE0_EDMA1_CS, + GAUDI2_SPMU_DCORE0_VDEC0_CS, + GAUDI2_SPMU_DCORE0_VDEC1_CS, + GAUDI2_SPMU_DCORE1_HMMU0_CS, + GAUDI2_SPMU_DCORE1_HMMU1_CS, + GAUDI2_SPMU_DCORE1_HMMU2_CS, + GAUDI2_SPMU_DCORE1_HMMU3_CS, + GAUDI2_SPMU_DCORE1_MME_CTRL, + GAUDI2_SPMU_DCORE1_MME_SBTE0, + GAUDI2_SPMU_DCORE1_MME_SBTE1, + GAUDI2_SPMU_DCORE1_MME_SBTE2, + GAUDI2_SPMU_DCORE1_MME_SBTE3, + GAUDI2_SPMU_DCORE1_MME_SBTE4, + GAUDI2_SPMU_DCORE1_MME_ACC, + GAUDI2_SPMU_DCORE1_SM, + GAUDI2_SPMU_DCORE1_EDMA0_CS, + GAUDI2_SPMU_DCORE1_EDMA1_CS, + GAUDI2_SPMU_DCORE1_VDEC0_CS, + GAUDI2_SPMU_DCORE1_VDEC1_CS, + GAUDI2_SPMU_DCORE2_HMMU0_CS, + GAUDI2_SPMU_DCORE2_HMMU1_CS, + GAUDI2_SPMU_DCORE2_HMMU2_CS, + GAUDI2_SPMU_DCORE2_HMMU3_CS, + GAUDI2_SPMU_DCORE2_MME_CTRL, + GAUDI2_SPMU_DCORE2_MME_SBTE0, + GAUDI2_SPMU_DCORE2_MME_SBTE1, + GAUDI2_SPMU_DCORE2_MME_SBTE2, + GAUDI2_SPMU_DCORE2_MME_SBTE3, + GAUDI2_SPMU_DCORE2_MME_SBTE4, + GAUDI2_SPMU_DCORE2_MME_ACC, + GAUDI2_SPMU_DCORE2_SM, + GAUDI2_SPMU_DCORE2_EDMA0_CS, + GAUDI2_SPMU_DCORE2_EDMA1_CS, + GAUDI2_SPMU_DCORE2_VDEC0_CS, + GAUDI2_SPMU_DCORE2_VDEC1_CS, + GAUDI2_SPMU_DCORE3_HMMU0_CS, + GAUDI2_SPMU_DCORE3_HMMU1_CS, + GAUDI2_SPMU_DCORE3_HMMU2_CS, + GAUDI2_SPMU_DCORE3_HMMU3_CS, + GAUDI2_SPMU_DCORE3_MME_CTRL, + GAUDI2_SPMU_DCORE3_MME_SBTE0, + GAUDI2_SPMU_DCORE3_MME_SBTE1, + GAUDI2_SPMU_DCORE3_MME_SBTE2, + GAUDI2_SPMU_DCORE3_MME_SBTE3, + GAUDI2_SPMU_DCORE3_MME_SBTE4, + GAUDI2_SPMU_DCORE3_MME_ACC, + GAUDI2_SPMU_DCORE3_SM, + GAUDI2_SPMU_DCORE3_EDMA0_CS, + GAUDI2_SPMU_DCORE3_EDMA1_CS, + GAUDI2_SPMU_DCORE3_VDEC0_CS, + GAUDI2_SPMU_DCORE3_VDEC1_CS, + GAUDI2_SPMU_PCIE, + GAUDI2_SPMU_PSOC_ARC0_CS, + GAUDI2_SPMU_PSOC_ARC1_CS, + GAUDI2_SPMU_PDMA0_CS, + GAUDI2_SPMU_PDMA1_CS, + GAUDI2_SPMU_PMMU_CS, + GAUDI2_SPMU_ROT0_CS, + GAUDI2_SPMU_ROT1_CS, + GAUDI2_SPMU_ARC_FARM_CS, + GAUDI2_SPMU_KDMA_CS, + GAUDI2_SPMU_PCIE_VDEC0_CS, + GAUDI2_SPMU_PCIE_VDEC1_CS, + GAUDI2_SPMU_HBM0_MC0_CS, + GAUDI2_SPMU_HBM0_MC1_CS, + GAUDI2_SPMU_HBM1_MC0_CS, + GAUDI2_SPMU_HBM1_MC1_CS, + GAUDI2_SPMU_HBM2_MC0_CS, + GAUDI2_SPMU_HBM2_MC1_CS, + GAUDI2_SPMU_HBM3_MC0_CS, + GAUDI2_SPMU_HBM3_MC1_CS, + GAUDI2_SPMU_HBM4_MC0_CS, + GAUDI2_SPMU_HBM4_MC1_CS, + GAUDI2_SPMU_HBM5_MC0_CS, + GAUDI2_SPMU_HBM5_MC1_CS, + GAUDI2_SPMU_NIC0_DBG_0, + GAUDI2_SPMU_NIC0_DBG_1, + GAUDI2_SPMU_NIC1_DBG_0, + GAUDI2_SPMU_NIC1_DBG_1, + GAUDI2_SPMU_NIC2_DBG_0, + GAUDI2_SPMU_NIC2_DBG_1, + GAUDI2_SPMU_NIC3_DBG_0, + GAUDI2_SPMU_NIC3_DBG_1, + GAUDI2_SPMU_NIC4_DBG_0, + GAUDI2_SPMU_NIC4_DBG_1, + GAUDI2_SPMU_NIC5_DBG_0, + GAUDI2_SPMU_NIC5_DBG_1, + GAUDI2_SPMU_NIC6_DBG_0, + GAUDI2_SPMU_NIC6_DBG_1, + GAUDI2_SPMU_NIC7_DBG_0, + GAUDI2_SPMU_NIC7_DBG_1, + GAUDI2_SPMU_NIC8_DBG_0, + GAUDI2_SPMU_NIC8_DBG_1, + GAUDI2_SPMU_NIC9_DBG_0, + GAUDI2_SPMU_NIC9_DBG_1, + GAUDI2_SPMU_NIC10_DBG_0, + GAUDI2_SPMU_NIC10_DBG_1, + GAUDI2_SPMU_NIC11_DBG_0, + GAUDI2_SPMU_NIC11_DBG_1, + GAUDI2_SPMU_LAST = GAUDI2_SPMU_NIC11_DBG_1 +}; + +#endif /* GAUDI2_CORESIGHT_H */ diff --git a/drivers/misc/habanalabs/include/gaudi2/gaudi2_fw_if.h b/drivers/misc/habanalabs/include/gaudi2/gaudi2_fw_if.h new file mode 100644 index 000000000000..e4a7d5725096 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/gaudi2_fw_if.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2019-2021 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI2_FW_IF_H +#define GAUDI2_FW_IF_H + +#define GAUDI2_EVENT_QUEUE_MSIX_IDX 0 + +#define UBOOT_FW_OFFSET 0x100000 /* 1MB in SRAM */ +#define LINUX_FW_OFFSET 0x800000 /* 8BM in DDR */ + +#define GAUDI2_PLL_FREQ_LOW 200000000 /* 200 MHz */ + +#define GAUDI2_SP_SRAM_BASE_ADDR 0x27FE0000 +#define GAUDI2_MAILBOX_BASE_ADDR 0x27FE1800 + +#define GAUDI2_NUM_MME 4 + +#define GAUDI2_ARCPID_TX_MB_SIZE 0x1000 +#define GAUDI2_ARCPID_RX_MB_SIZE 0x400 +#define GAUDI2_ARM_TX_MB_SIZE 0x400 +#define GAUDI2_ARM_RX_MB_SIZE 0x1800 + +#define GAUDI2_DCCM_BASE_ADDR 0x27020000 +#define GAUDI2_ARCPID_TX_MB_ADDR GAUDI2_DCCM_BASE_ADDR + +#define GAUDI2_ARCPID_RX_MB_ADDR (GAUDI2_ARCPID_TX_MB_ADDR + \ + GAUDI2_ARCPID_TX_MB_SIZE) + +#define GAUDI2_ARM_TX_MB_ADDR GAUDI2_MAILBOX_BASE_ADDR + +#define GAUDI2_ARM_RX_MB_ADDR (GAUDI2_ARM_TX_MB_ADDR + \ + GAUDI2_ARM_TX_MB_SIZE) + +#define GAUDI2_ARM_TX_MB_OFFSET (GAUDI2_ARM_TX_MB_ADDR - \ + GAUDI2_SP_SRAM_BASE_ADDR) + +#define GAUDI2_ARM_RX_MB_OFFSET (GAUDI2_ARM_RX_MB_ADDR - \ + GAUDI2_SP_SRAM_BASE_ADDR) + +enum gaudi2_fw_status { + GAUDI2_PID_STATUS_UP = 0x1, /* PID on ARC0 is up */ + GAUDI2_ARM_STATUS_UP = 0x2, /* ARM Linux Boot complete */ + GAUDI2_MGMT_STATUS_UP = 0x3, /* ARC1 Mgmt is up */ + GAUDI2_STATUS_LAST = 0xFF +}; + +struct gaudi2_cold_rst_data { + union { + struct { + u32 recovery_flag: 1; + u32 validation_flag: 1; + u32 efuse_read_flag: 1; + u32 spsram_init_done : 1; + u32 fake_security_enable : 1; + u32 fake_sig_validation_en : 1; + u32 reserved : 26; + }; + __le32 data; + }; +}; + +enum gaudi2_rst_src { + HL_COLD_RST = 1, + HL_MANUAL_RST = 2, + HL_PRSTN_RST = 4, + HL_SOFT_RST = 8, + HL_WD_RST = 16, + HL_FW_ALL_RST = 32, + HL_SW_ALL_RST = 64, + HL_FLR_RST = 128, + HL_ECC_DERR_RST = 256 +}; + +struct gaudi2_redundancy_ctx { + int redundant_hbm; + int redundant_edma; + int redundant_tpc; + int redundant_vdec; + __le64 hbm_mask; + __le64 edma_mask; + __le64 tpc_mask; + __le64 vdec_mask; + __le64 mme_mask; + __le64 nic_mask; + __le64 rtr_mask; + __le64 hmmu_hif_iso; + __le64 xbar_edge_iso; + __le64 hmmu_hif_mask; + __le64 xbar_edge_mask; + __u8 mme_pe_iso[GAUDI2_NUM_MME]; + __le32 full_hbm_mode; /* true on full (non binning hbm)*/ +} __packed; + +#endif /* GAUDI2_FW_IF_H */ diff --git a/drivers/misc/habanalabs/include/gaudi2/gaudi2_packets.h b/drivers/misc/habanalabs/include/gaudi2/gaudi2_packets.h new file mode 100644 index 000000000000..8bf90fc18bf5 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/gaudi2_packets.h @@ -0,0 +1,197 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI2_PACKETS_H +#define GAUDI2_PACKETS_H + +#include + +#define PACKET_HEADER_PACKET_ID_SHIFT 56 +#define PACKET_HEADER_PACKET_ID_MASK 0x1F00000000000000ull + +enum packet_id { + PACKET_WREG_32 = 0x1, + PACKET_WREG_BULK = 0x2, + PACKET_MSG_LONG = 0x3, + PACKET_MSG_SHORT = 0x4, + PACKET_CP_DMA = 0x5, + PACKET_REPEAT = 0x6, + PACKET_MSG_PROT = 0x7, + PACKET_FENCE = 0x8, + PACKET_LIN_DMA = 0x9, + PACKET_NOP = 0xA, + PACKET_STOP = 0xB, + PACKET_ARB_POINT = 0xC, + PACKET_WAIT = 0xD, + PACKET_CB_LIST = 0xE, + PACKET_LOAD_AND_EXE = 0xF, + PACKET_WRITE_ARC_STREAM = 0x10, + PACKET_LAST_READ_FROM_ARC = 0x11, + PACKET_WREG_64_SHORT = 0x12, + PACKET_WREG_64_LONG = 0x13, + MAX_PACKET_ID = (PACKET_HEADER_PACKET_ID_MASK >> + PACKET_HEADER_PACKET_ID_SHIFT) + 1 +}; + +#define GAUDI2_PKT_CTL_OPCODE_SHIFT 24 +#define GAUDI2_PKT_CTL_OPCODE_MASK 0x1F000000 + +#define GAUDI2_PKT_CTL_EB_SHIFT 29 +#define GAUDI2_PKT_CTL_EB_MASK 0x20000000 + +#define GAUDI2_PKT_CTL_RB_SHIFT 30 +#define GAUDI2_PKT_CTL_RB_MASK 0x40000000 + +#define GAUDI2_PKT_CTL_MB_SHIFT 31 +#define GAUDI2_PKT_CTL_MB_MASK 0x80000000 + +/* All packets have, at least, an 8-byte header, which contains + * the packet type. The kernel driver uses the packet header for packet + * validation and to perform any necessary required preparation before + * sending them off to the hardware. + */ +struct gaudi2_packet { + __le64 header; + /* The rest of the packet data follows. Use the corresponding + * packet_XXX struct to deference the data, based on packet type + */ + u8 contents[0]; +}; + +struct packet_nop { + __le32 reserved; + __le32 ctl; +}; + +struct packet_stop { + __le32 reserved; + __le32 ctl; +}; + +struct packet_wreg32 { + __le32 value; + __le32 ctl; +}; + +struct packet_wreg_bulk { + __le32 size64; + __le32 ctl; + __le64 values[0]; /* data starts here */ +}; + +struct packet_msg_long { + __le32 value; + __le32 ctl; + __le64 addr; +}; + +#define GAUDI2_PKT_SHORT_VAL_SOB_SYNC_VAL_SHIFT 0 +#define GAUDI2_PKT_SHORT_VAL_SOB_SYNC_VAL_MASK 0x00007FFF + +#define GAUDI2_PKT_SHORT_VAL_SOB_MOD_SHIFT 31 +#define GAUDI2_PKT_SHORT_VAL_SOB_MOD_MASK 0x80000000 + +#define GAUDI2_PKT_SHORT_VAL_MON_SYNC_GID_SHIFT 0 +#define GAUDI2_PKT_SHORT_VAL_MON_SYNC_GID_MASK 0x000000FF + +#define GAUDI2_PKT_SHORT_VAL_MON_MASK_SHIFT 8 +#define GAUDI2_PKT_SHORT_VAL_MON_MASK_MASK 0x0000FF00 + +#define GAUDI2_PKT_SHORT_VAL_MON_MODE_SHIFT 16 +#define GAUDI2_PKT_SHORT_VAL_MON_MODE_MASK 0x00010000 + +#define GAUDI2_PKT_SHORT_VAL_MON_SYNC_VAL_SHIFT 17 +#define GAUDI2_PKT_SHORT_VAL_MON_SYNC_VAL_MASK 0xFFFE0000 + +#define GAUDI2_PKT_SHORT_CTL_ADDR_SHIFT 0 +#define GAUDI2_PKT_SHORT_CTL_ADDR_MASK 0x0000FFFF + +#define GAUDI2_PKT_SHORT_CTL_BASE_SHIFT 22 +#define GAUDI2_PKT_SHORT_CTL_BASE_MASK 0x00C00000 + +struct packet_msg_short { + __le32 value; + __le32 ctl; +}; + +struct packet_msg_prot { + __le32 value; + __le32 ctl; + __le64 addr; +}; + +#define GAUDI2_PKT_FENCE_CFG_DEC_VAL_SHIFT 0 +#define GAUDI2_PKT_FENCE_CFG_DEC_VAL_MASK 0x0000000F + +#define GAUDI2_PKT_FENCE_CFG_TARGET_VAL_SHIFT 16 +#define GAUDI2_PKT_FENCE_CFG_TARGET_VAL_MASK 0x00FF0000 + +#define GAUDI2_PKT_FENCE_CFG_ID_SHIFT 30 +#define GAUDI2_PKT_FENCE_CFG_ID_MASK 0xC0000000 + +#define GAUDI2_PKT_FENCE_CTL_PRED_SHIFT 0 +#define GAUDI2_PKT_FENCE_CTL_PRED_MASK 0x0000001F + +struct packet_fence { + __le32 cfg; + __le32 ctl; +}; + +#define GAUDI2_PKT_LIN_DMA_CTL_WRCOMP_SHIFT 0 +#define GAUDI2_PKT_LIN_DMA_CTL_WRCOMP_MASK 0x00000001 + +#define GAUDI2_PKT_LIN_DMA_CTL_ENDIAN_SHIFT 1 +#define GAUDI2_PKT_LIN_DMA_CTL_ENDIAN_MASK 0x00000006 + +#define GAUDI2_PKT_LIN_DMA_CTL_MEMSET_SHIFT 4 +#define GAUDI2_PKT_LIN_DMA_CTL_MEMSET_MASK 0x00000010 + +#define GAUDI2_PKT_LIN_DMA_CTL_CONTEXT_ID_SHIFT 8 +#define GAUDI2_PKT_LIN_DMA_CTL_CONTEXT_ID_MASK 0x00FFFF00 + +struct packet_lin_dma { + __le32 tsize; + __le32 ctl; + __le64 src_addr; + __le64 dst_addr; +}; + +struct packet_arb_point { + __le32 cfg; + __le32 ctl; +}; + +struct packet_repeat { + __le32 cfg; + __le32 ctl; +}; + +struct packet_wait { + __le32 cfg; + __le32 ctl; +}; + +struct packet_cb_list { + __le32 reserved; + __le32 ctl; + __le64 index_addr; + __le64 table_addr; +}; + +struct packet_load_and_exe { + __le32 cfg; + __le32 ctl; + __le64 src_addr; +}; + +struct packet_cp_dma { + __le32 tsize; + __le32 ctl; + __le64 src_addr; +}; + +#endif /* GAUDI2_PACKETS_H */ diff --git a/drivers/misc/habanalabs/include/gaudi2/gaudi2_reg_map.h b/drivers/misc/habanalabs/include/gaudi2/gaudi2_reg_map.h new file mode 100644 index 000000000000..ae7feb388f63 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/gaudi2_reg_map.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI2_REG_MAP_H_ +#define GAUDI2_REG_MAP_H_ + +/* + * PSOC scratch-pad registers + */ +#define mmHW_STATE mmCPU_IF_KMD_HW_DIRTY_STATUS +#define mmPID_STATUS_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_1 +#define mmARM_STATUS_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_2 +#define mmGIC_TPC_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_3 +#define mmGIC_MME_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_4 +#define mmGIC_DMA_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_5 +#define mmGIC_ROT_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_6 +#define mmGIC_NIC_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_7 +#define mmGIC_DMA_CR_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 +#define mmGIC_HOST_PI_UPD_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_9 +#define mmGIC_HOST_HALT_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_10 +#define mmGIC_HOST_INTS_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_11 +#define mmGIC_HOST_SOFT_RST_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_12 +#define mmEEPROM_COPY_LOCATION_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_13 +#define mmCPU_RST_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_14 +#define mmENGINE_ARC_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_15 +#define mmPID_CFG_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_18 +/* + * TODO: mmGIC_RAZWI_STATUS_REG is temporary + * macro and to be removed after GAUDI2 PO + */ +#define mmGIC_RAZWI_STATUS_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_19 +#define mmCPU_BOOT_DEV_STS0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_20 +#define mmCPU_BOOT_DEV_STS1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_21 +#define mmCPU_CMD_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 +#define mmCPU_BOOT_ERR0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 +#define mmCPU_BOOT_ERR1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 +#define mmUPD_STS mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 +#define mmUPD_CMD mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 +#define mmUBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 +#define mmRDWR_TEST mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 +#define mmBTL_ID mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 +#define mmRST_SRC mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_0 +#define mmPREBOOT_PCIE_EN mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1 +#define mmCOLD_RST_DATA mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2 +#define mmUPD_PENDING_STS mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3 +#define mmPID_CMD_REQ_REG mmPSOC_PID_PID_CMD_0 +#define mmPID_CMD_REQ_REG_HI mmPSOC_PID_PID_CMD_1 +#define mmPID_CMD_RSP_REG mmPSOC_PID_PID_CMD_2 +#define mmPID_CMD_RSP_REG_HI mmPSOC_PID_PID_CMD_3 +#define mmPID_CMD_TELEMETRY_REG_0 mmPSOC_PID_PID_CMD_4 +#define mmPID_CMD_TELEMETRY_REG_0_HI mmPSOC_PID_PID_CMD_5 +#define mmPID_CMD_TELEMETRY_REG_1 mmPSOC_PID_PID_CMD_6 +#define mmPID_CMD_TELEMETRY_REG_1_HI mmPSOC_PID_PID_CMD_7 + +#endif /* GAUDI2_REG_MAP_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/goya_packets.h b/drivers/misc/habanalabs/include/goya/goya_packets.h index 50ce5175b63a..896799204fb0 100644 --- a/drivers/misc/habanalabs/include/goya/goya_packets.h +++ b/drivers/misc/habanalabs/include/goya/goya_packets.h @@ -28,18 +28,6 @@ enum packet_id { PACKET_HEADER_PACKET_ID_SHIFT) + 1 }; -enum goya_dma_direction { - DMA_HOST_TO_DRAM, - DMA_HOST_TO_SRAM, - DMA_DRAM_TO_SRAM, - DMA_SRAM_TO_DRAM, - DMA_SRAM_TO_HOST, - DMA_DRAM_TO_HOST, - DMA_DRAM_TO_DRAM, - DMA_SRAM_TO_SRAM, - DMA_ENUM_MAX -}; - #define GOYA_PKT_CTL_OPCODE_SHIFT 24 #define GOYA_PKT_CTL_OPCODE_MASK 0x1F000000 diff --git a/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h index cae8ac8bc5b1..d408feecd483 100644 --- a/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h +++ b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h @@ -9,9 +9,17 @@ #define INCLUDE_MMU_GENERAL_H_ #define PAGE_SHIFT_4KB 12 +#define PAGE_SHIFT_64KB 16 #define PAGE_SHIFT_2MB 21 -#define PAGE_SIZE_2MB (_AC(1, UL) << PAGE_SHIFT_2MB) -#define PAGE_SIZE_4KB (_AC(1, UL) << PAGE_SHIFT_4KB) +#define PAGE_SHIFT_16MB 24 +#define PAGE_SHIFT_64MB 26 +#define PAGE_SHIFT_1GB 30 +#define PAGE_SIZE_4KB _BITUL(PAGE_SHIFT_4KB) +#define PAGE_SIZE_64KB _BITUL(PAGE_SHIFT_64KB) +#define PAGE_SIZE_2MB _BITUL(PAGE_SHIFT_2MB) +#define PAGE_SIZE_16MB _BITUL(PAGE_SHIFT_16MB) +#define PAGE_SIZE_64MB _BITUL(PAGE_SHIFT_64MB) +#define PAGE_SIZE_1GB _BITUL(PAGE_SHIFT_1GB) #define PAGE_PRESENT_MASK 0x0000000000001ull #define SWAP_OUT_MASK 0x0000000000004ull @@ -19,6 +27,7 @@ #define FLAGS_MASK 0x0000000000FFFull #define MMU_ARCH_5_HOPS 5 +#define MMU_ARCH_6_HOPS 6 #define HOP_PHYS_ADDR_MASK (~FLAGS_MASK) @@ -31,6 +40,7 @@ #define MMU_HOP0_PA43_12_SHIFT 12 #define MMU_HOP0_PA49_44_SHIFT (12 + 32) +#define MMU_HOP0_PA63_44_SHIFT (12 + 32) #define MMU_CONFIG_TIMEOUT_USEC 2000 /* 2 ms */ diff --git a/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v2_0.h b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v2_0.h new file mode 100644 index 000000000000..cd7bf25d2da9 --- /dev/null +++ b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v2_0.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2019 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef INCLUDE_MMU_V2_0_H_ +#define INCLUDE_MMU_V2_0_H_ + +#define HOP0_MASK_4K 0xFE00000000000000ull +#define HOP1_MASK_4K 0x01FF000000000000ull +#define HOP2_MASK_4K 0x0000FF8000000000ull +#define HOP3_MASK_4K 0x0000007FC0000000ull +#define HOP4_MASK_4K 0x000000003FE00000ull +#define HOP5_MASK_4K 0x00000000001FF000ull + +#define HOP0_MASK_64K 0xFF00000000000000ull +#define HOP1_MASK_64K 0x00FF000000000000ull +#define HOP2_MASK_64K 0x0000FF0000000000ull +#define HOP3_MASK_64K 0x000000FF00000000ull +#define HOP4_MASK_64K 0x00000000FF000000ull +#define HOP5_MASK_64K 0x0000000000FF0000ull + +#define HOP0_SHIFT_4K 57 +#define HOP1_SHIFT_4K 48 +#define HOP2_SHIFT_4K 39 +#define HOP3_SHIFT_4K 30 +#define HOP4_SHIFT_4K 21 +#define HOP5_SHIFT_4K 12 + +#define HOP0_SHIFT_64K 56 +#define HOP1_SHIFT_64K 48 +#define HOP2_SHIFT_64K 40 +#define HOP3_SHIFT_64K 32 +#define HOP4_SHIFT_64K 24 +#define HOP5_SHIFT_64K 16 + +#define DHOP0_MASK HOP0_MASK_4K +#define DHOP1_MASK HOP1_MASK_4K +#define DHOP2_MASK HOP2_MASK_4K +#define DHOP3_MASK HOP3_MASK_4K +#define DHOP4_MASK 0x000003C000000ull + +#define DHOP0_SHIFT HOP0_SHIFT_4K +#define DHOP1_SHIFT HOP1_SHIFT_4K +#define DHOP2_SHIFT HOP2_SHIFT_4K +#define DHOP3_SHIFT HOP3_SHIFT_4K +#define DHOP4_SHIFT 26 + +#endif /* INCLUDE_MMU_V2_0_H_ */ diff --git a/drivers/misc/lkdtm/cfi.c b/drivers/misc/lkdtm/cfi.c index 666a7f4bc137..71483cb1e422 100644 --- a/drivers/misc/lkdtm/cfi.c +++ b/drivers/misc/lkdtm/cfi.c @@ -97,7 +97,7 @@ static volatile int force_check; static void lkdtm_CFI_BACKWARD(void) { /* Use calculated gotos to keep labels addressable. */ - void *labels[] = {0, &&normal, &&redirected, &&check_normal, &&check_redirected}; + void *labels[] = { NULL, &&normal, &&redirected, &&check_normal, &&check_redirected }; pr_info("Attempting unchecked stack return address redirection ...\n"); diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c index befa491e3344..3a95fe7d4e33 100644 --- a/drivers/misc/mei/hw-me.c +++ b/drivers/misc/mei/hw-me.c @@ -561,7 +561,7 @@ static int mei_me_hbuf_write(struct mei_device *dev, dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM((struct mei_msg_hdr *)hdr)); empty_slots = mei_hbuf_empty_slots(dev); - dev_dbg(dev->dev, "empty slots = %hu.\n", empty_slots); + dev_dbg(dev->dev, "empty slots = %d.\n", empty_slots); if (empty_slots < 0) return -EOVERFLOW; diff --git a/drivers/misc/sgi-gru/grukservices.c b/drivers/misc/sgi-gru/grukservices.c index 19dbdad8ad8a..fa1f5a632e7f 100644 --- a/drivers/misc/sgi-gru/grukservices.c +++ b/drivers/misc/sgi-gru/grukservices.c @@ -36,7 +36,7 @@ * kernel/user requirements. * * Blade percpu resources reserved for kernel use. These resources are - * reserved whenever the the kernel context for the blade is loaded. Note + * reserved whenever the kernel context for the blade is loaded. Note * that the kernel context is not guaranteed to be always available. It is * loaded on demand & can be stolen by a user if the user demand exceeds the * kernel demand. The kernel can always reload the kernel context but diff --git a/drivers/misc/sgi-xp/xpc_uv.c b/drivers/misc/sgi-xp/xpc_uv.c index ba9ae0e2df0f..fff522d347e3 100644 --- a/drivers/misc/sgi-xp/xpc_uv.c +++ b/drivers/misc/sgi-xp/xpc_uv.c @@ -1598,7 +1598,7 @@ out_2: * by xpc_notify_senders_of_disconnect_uv(), and to also get an * error returned here will confuse them. Additionally, since * in this case the channel is being disconnected we don't need - * to put the the msg_slot back on the free list. + * to put the msg_slot back on the free list. */ if (cmpxchg(&msg_slot->func, func, NULL) != func) { ret = xpSuccess; diff --git a/drivers/misc/sgi-xp/xpnet.c b/drivers/misc/sgi-xp/xpnet.c index 50644f83e78c..2396ba3b03bd 100644 --- a/drivers/misc/sgi-xp/xpnet.c +++ b/drivers/misc/sgi-xp/xpnet.c @@ -285,7 +285,7 @@ xpnet_connection_activity(enum xp_retval reason, short partid, int channel, __clear_bit(partid, xpnet_broadcast_partitions); spin_unlock_bh(&xpnet_broadcast_lock); - if (bitmap_empty((unsigned long *)xpnet_broadcast_partitions, + if (bitmap_empty(xpnet_broadcast_partitions, xp_max_npartitions)) { netif_carrier_off(xpnet_device); } @@ -522,9 +522,8 @@ xpnet_init(void) dev_info(xpnet, "registering network device %s\n", XPNET_DEVICE_NAME); - xpnet_broadcast_partitions = kcalloc(BITS_TO_LONGS(xp_max_npartitions), - sizeof(long), - GFP_KERNEL); + xpnet_broadcast_partitions = bitmap_zalloc(xp_max_npartitions, + GFP_KERNEL); if (xpnet_broadcast_partitions == NULL) return -ENOMEM; @@ -535,7 +534,7 @@ xpnet_init(void) xpnet_device = alloc_netdev(0, XPNET_DEVICE_NAME, NET_NAME_UNKNOWN, ether_setup); if (xpnet_device == NULL) { - kfree(xpnet_broadcast_partitions); + bitmap_free(xpnet_broadcast_partitions); return -ENOMEM; } @@ -574,7 +573,7 @@ xpnet_init(void) result = register_netdev(xpnet_device); if (result != 0) { free_netdev(xpnet_device); - kfree(xpnet_broadcast_partitions); + bitmap_free(xpnet_broadcast_partitions); } return result; @@ -590,7 +589,7 @@ xpnet_exit(void) unregister_netdev(xpnet_device); free_netdev(xpnet_device); - kfree(xpnet_broadcast_partitions); + bitmap_free(xpnet_broadcast_partitions); } module_exit(xpnet_exit); diff --git a/drivers/misc/uacce/uacce.c b/drivers/misc/uacce/uacce.c index 281c54003edc..b70a013139c7 100644 --- a/drivers/misc/uacce/uacce.c +++ b/drivers/misc/uacce/uacce.c @@ -9,43 +9,38 @@ static struct class *uacce_class; static dev_t uacce_devt; -static DEFINE_MUTEX(uacce_mutex); static DEFINE_XARRAY_ALLOC(uacce_xa); +/* + * If the parent driver or the device disappears, the queue state is invalid and + * ops are not usable anymore. + */ +static bool uacce_queue_is_valid(struct uacce_queue *q) +{ + return q->state == UACCE_Q_INIT || q->state == UACCE_Q_STARTED; +} + static int uacce_start_queue(struct uacce_queue *q) { - int ret = 0; + int ret; - mutex_lock(&uacce_mutex); - - if (q->state != UACCE_Q_INIT) { - ret = -EINVAL; - goto out_with_lock; - } + if (q->state != UACCE_Q_INIT) + return -EINVAL; if (q->uacce->ops->start_queue) { ret = q->uacce->ops->start_queue(q); if (ret < 0) - goto out_with_lock; + return ret; } q->state = UACCE_Q_STARTED; - -out_with_lock: - mutex_unlock(&uacce_mutex); - - return ret; + return 0; } static int uacce_put_queue(struct uacce_queue *q) { struct uacce_device *uacce = q->uacce; - mutex_lock(&uacce_mutex); - - if (q->state == UACCE_Q_ZOMBIE) - goto out; - if ((q->state == UACCE_Q_STARTED) && uacce->ops->stop_queue) uacce->ops->stop_queue(q); @@ -54,8 +49,6 @@ static int uacce_put_queue(struct uacce_queue *q) uacce->ops->put_queue(q); q->state = UACCE_Q_ZOMBIE; -out: - mutex_unlock(&uacce_mutex); return 0; } @@ -65,20 +58,36 @@ static long uacce_fops_unl_ioctl(struct file *filep, { struct uacce_queue *q = filep->private_data; struct uacce_device *uacce = q->uacce; + long ret = -ENXIO; + + /* + * uacce->ops->ioctl() may take the mmap_lock when copying arg to/from + * user. Avoid a circular lock dependency with uacce_fops_mmap(), which + * gets called with mmap_lock held, by taking uacce->mutex instead of + * q->mutex. Doing this in uacce_fops_mmap() is not possible because + * uacce_fops_open() calls iommu_sva_bind_device(), which takes + * mmap_lock, while holding uacce->mutex. + */ + mutex_lock(&uacce->mutex); + if (!uacce_queue_is_valid(q)) + goto out_unlock; switch (cmd) { case UACCE_CMD_START_Q: - return uacce_start_queue(q); - + ret = uacce_start_queue(q); + break; case UACCE_CMD_PUT_Q: - return uacce_put_queue(q); - + ret = uacce_put_queue(q); + break; default: - if (!uacce->ops->ioctl) - return -EINVAL; - - return uacce->ops->ioctl(q, cmd, arg); + if (uacce->ops->ioctl) + ret = uacce->ops->ioctl(q, cmd, arg); + else + ret = -EINVAL; } +out_unlock: + mutex_unlock(&uacce->mutex); + return ret; } #ifdef CONFIG_COMPAT @@ -136,6 +145,13 @@ static int uacce_fops_open(struct inode *inode, struct file *filep) if (!q) return -ENOMEM; + mutex_lock(&uacce->mutex); + + if (!uacce->parent) { + ret = -EINVAL; + goto out_with_mem; + } + ret = uacce_bind_queue(uacce, q); if (ret) goto out_with_mem; @@ -152,10 +168,9 @@ static int uacce_fops_open(struct inode *inode, struct file *filep) filep->private_data = q; uacce->inode = inode; q->state = UACCE_Q_INIT; - - mutex_lock(&uacce->queues_lock); + mutex_init(&q->mutex); list_add(&q->list, &uacce->queues); - mutex_unlock(&uacce->queues_lock); + mutex_unlock(&uacce->mutex); return 0; @@ -163,18 +178,20 @@ out_with_bond: uacce_unbind_queue(q); out_with_mem: kfree(q); + mutex_unlock(&uacce->mutex); return ret; } static int uacce_fops_release(struct inode *inode, struct file *filep) { struct uacce_queue *q = filep->private_data; + struct uacce_device *uacce = q->uacce; - mutex_lock(&q->uacce->queues_lock); - list_del(&q->list); - mutex_unlock(&q->uacce->queues_lock); + mutex_lock(&uacce->mutex); uacce_put_queue(q); uacce_unbind_queue(q); + list_del(&q->list); + mutex_unlock(&uacce->mutex); kfree(q); return 0; @@ -217,10 +234,9 @@ static int uacce_fops_mmap(struct file *filep, struct vm_area_struct *vma) vma->vm_private_data = q; qfr->type = type; - mutex_lock(&uacce_mutex); - - if (q->state != UACCE_Q_INIT && q->state != UACCE_Q_STARTED) { - ret = -EINVAL; + mutex_lock(&q->mutex); + if (!uacce_queue_is_valid(q)) { + ret = -ENXIO; goto out_with_lock; } @@ -248,12 +264,12 @@ static int uacce_fops_mmap(struct file *filep, struct vm_area_struct *vma) } q->qfrs[type] = qfr; - mutex_unlock(&uacce_mutex); + mutex_unlock(&q->mutex); return ret; out_with_lock: - mutex_unlock(&uacce_mutex); + mutex_unlock(&q->mutex); kfree(qfr); return ret; } @@ -262,12 +278,20 @@ static __poll_t uacce_fops_poll(struct file *file, poll_table *wait) { struct uacce_queue *q = file->private_data; struct uacce_device *uacce = q->uacce; + __poll_t ret = 0; + + mutex_lock(&q->mutex); + if (!uacce_queue_is_valid(q)) + goto out_unlock; poll_wait(file, &q->wait, wait); - if (uacce->ops->is_q_updated && uacce->ops->is_q_updated(q)) - return EPOLLIN | EPOLLRDNORM; - return 0; + if (uacce->ops->is_q_updated && uacce->ops->is_q_updated(q)) + ret = EPOLLIN | EPOLLRDNORM; + +out_unlock: + mutex_unlock(&q->mutex); + return ret; } static const struct file_operations uacce_fops = { @@ -450,7 +474,7 @@ struct uacce_device *uacce_alloc(struct device *parent, goto err_with_uacce; INIT_LIST_HEAD(&uacce->queues); - mutex_init(&uacce->queues_lock); + mutex_init(&uacce->mutex); device_initialize(&uacce->dev); uacce->dev.devt = MKDEV(MAJOR(uacce_devt), uacce->dev_id); uacce->dev.class = uacce_class; @@ -507,13 +531,23 @@ void uacce_remove(struct uacce_device *uacce) if (uacce->inode) unmap_mapping_range(uacce->inode->i_mapping, 0, 0, 1); + /* + * uacce_fops_open() may be running concurrently, even after we remove + * the cdev. Holding uacce->mutex ensures that open() does not obtain a + * removed uacce device. + */ + mutex_lock(&uacce->mutex); /* ensure no open queue remains */ - mutex_lock(&uacce->queues_lock); list_for_each_entry_safe(q, next_q, &uacce->queues, list) { + /* + * Taking q->mutex ensures that fops do not use the defunct + * uacce->ops after the queue is disabled. + */ + mutex_lock(&q->mutex); uacce_put_queue(q); + mutex_unlock(&q->mutex); uacce_unbind_queue(q); } - mutex_unlock(&uacce->queues_lock); /* disable sva now since no opened queues */ uacce_disable_sva(uacce); @@ -521,6 +555,13 @@ void uacce_remove(struct uacce_device *uacce) if (uacce->cdev) cdev_device_del(uacce->cdev, &uacce->dev); xa_erase(&uacce_xa, uacce->dev_id); + /* + * uacce exists as long as there are open fds, but ops will be freed + * now. Ensure that bugs cause NULL deref rather than use-after-free. + */ + uacce->ops = NULL; + uacce->parent = NULL; + mutex_unlock(&uacce->mutex); put_device(&uacce->dev); } EXPORT_SYMBOL_GPL(uacce_remove); diff --git a/drivers/misc/vcpu_stall_detector.c b/drivers/misc/vcpu_stall_detector.c new file mode 100644 index 000000000000..53b5506080e1 --- /dev/null +++ b/drivers/misc/vcpu_stall_detector.c @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// VCPU stall detector. +// Copyright (C) Google, 2022 + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define VCPU_STALL_REG_STATUS (0x00) +#define VCPU_STALL_REG_LOAD_CNT (0x04) +#define VCPU_STALL_REG_CURRENT_CNT (0x08) +#define VCPU_STALL_REG_CLOCK_FREQ_HZ (0x0C) +#define VCPU_STALL_REG_LEN (0x10) + +#define VCPU_STALL_DEFAULT_CLOCK_HZ (10) +#define VCPU_STALL_MAX_CLOCK_HZ (100) +#define VCPU_STALL_DEFAULT_TIMEOUT_SEC (8) +#define VCPU_STALL_MAX_TIMEOUT_SEC (600) + +struct vcpu_stall_detect_config { + u32 clock_freq_hz; + u32 stall_timeout_sec; + + void __iomem *membase; + struct platform_device *dev; + enum cpuhp_state hp_online; +}; + +struct vcpu_stall_priv { + struct hrtimer vcpu_hrtimer; + bool is_initialized; +}; + +/* The vcpu stall configuration structure which applies to all the CPUs */ +static struct vcpu_stall_detect_config vcpu_stall_config; + +#define vcpu_stall_reg_write(vcpu, reg, value) \ + writel_relaxed((value), \ + (void __iomem *)(vcpu_stall_config.membase + \ + (vcpu) * VCPU_STALL_REG_LEN + (reg))) + + +static struct vcpu_stall_priv __percpu *vcpu_stall_detectors; + +static enum hrtimer_restart +vcpu_stall_detect_timer_fn(struct hrtimer *hrtimer) +{ + u32 ticks, ping_timeout_ms; + + /* Reload the stall detector counter register every + * `ping_timeout_ms` to prevent the virtual device + * from decrementing it to 0. The virtual device decrements this + * register at 'clock_freq_hz' frequency. + */ + ticks = vcpu_stall_config.clock_freq_hz * + vcpu_stall_config.stall_timeout_sec; + vcpu_stall_reg_write(smp_processor_id(), + VCPU_STALL_REG_LOAD_CNT, ticks); + + ping_timeout_ms = vcpu_stall_config.stall_timeout_sec * + MSEC_PER_SEC / 2; + hrtimer_forward_now(hrtimer, + ms_to_ktime(ping_timeout_ms)); + + return HRTIMER_RESTART; +} + +static int start_stall_detector_cpu(unsigned int cpu) +{ + u32 ticks, ping_timeout_ms; + struct vcpu_stall_priv *vcpu_stall_detector = + this_cpu_ptr(vcpu_stall_detectors); + struct hrtimer *vcpu_hrtimer = &vcpu_stall_detector->vcpu_hrtimer; + + vcpu_stall_reg_write(cpu, VCPU_STALL_REG_CLOCK_FREQ_HZ, + vcpu_stall_config.clock_freq_hz); + + /* Compute the number of ticks required for the stall detector + * counter register based on the internal clock frequency and the + * timeout value given from the device tree. + */ + ticks = vcpu_stall_config.clock_freq_hz * + vcpu_stall_config.stall_timeout_sec; + vcpu_stall_reg_write(cpu, VCPU_STALL_REG_LOAD_CNT, ticks); + + /* Enable the internal clock and start the stall detector */ + vcpu_stall_reg_write(cpu, VCPU_STALL_REG_STATUS, 1); + + /* Pet the stall detector at half of its expiration timeout + * to prevent spurious resets. + */ + ping_timeout_ms = vcpu_stall_config.stall_timeout_sec * + MSEC_PER_SEC / 2; + + hrtimer_init(vcpu_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + vcpu_hrtimer->function = vcpu_stall_detect_timer_fn; + vcpu_stall_detector->is_initialized = true; + + hrtimer_start(vcpu_hrtimer, ms_to_ktime(ping_timeout_ms), + HRTIMER_MODE_REL_PINNED); + + return 0; +} + +static int stop_stall_detector_cpu(unsigned int cpu) +{ + struct vcpu_stall_priv *vcpu_stall_detector = + per_cpu_ptr(vcpu_stall_detectors, cpu); + + if (!vcpu_stall_detector->is_initialized) + return 0; + + /* Disable the stall detector for the current CPU */ + hrtimer_cancel(&vcpu_stall_detector->vcpu_hrtimer); + vcpu_stall_reg_write(cpu, VCPU_STALL_REG_STATUS, 0); + vcpu_stall_detector->is_initialized = false; + + return 0; +} + +static int vcpu_stall_detect_probe(struct platform_device *pdev) +{ + int ret; + struct resource *r; + void __iomem *membase; + u32 clock_freq_hz = VCPU_STALL_DEFAULT_CLOCK_HZ; + u32 stall_timeout_sec = VCPU_STALL_DEFAULT_TIMEOUT_SEC; + struct device_node *np = pdev->dev.of_node; + + vcpu_stall_detectors = devm_alloc_percpu(&pdev->dev, + typeof(struct vcpu_stall_priv)); + if (!vcpu_stall_detectors) + return -ENOMEM; + + membase = devm_platform_get_and_ioremap_resource(pdev, 0, &r); + if (IS_ERR(membase)) { + dev_err(&pdev->dev, "Failed to get memory resource\n"); + return PTR_ERR(membase); + } + + if (!of_property_read_u32(np, "clock-frequency", &clock_freq_hz)) { + if (!(clock_freq_hz > 0 && + clock_freq_hz < VCPU_STALL_MAX_CLOCK_HZ)) { + dev_warn(&pdev->dev, "clk out of range\n"); + clock_freq_hz = VCPU_STALL_DEFAULT_CLOCK_HZ; + } + } + + if (!of_property_read_u32(np, "timeout-sec", &stall_timeout_sec)) { + if (!(stall_timeout_sec > 0 && + stall_timeout_sec < VCPU_STALL_MAX_TIMEOUT_SEC)) { + dev_warn(&pdev->dev, "stall timeout out of range\n"); + stall_timeout_sec = VCPU_STALL_DEFAULT_TIMEOUT_SEC; + } + } + + vcpu_stall_config = (struct vcpu_stall_detect_config) { + .membase = membase, + .clock_freq_hz = clock_freq_hz, + .stall_timeout_sec = stall_timeout_sec + }; + + ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, + "virt/vcpu_stall_detector:online", + start_stall_detector_cpu, + stop_stall_detector_cpu); + if (ret < 0) { + dev_err(&pdev->dev, "failed to install cpu hotplug"); + goto err; + } + + vcpu_stall_config.hp_online = ret; + return 0; +err: + return ret; +} + +static int vcpu_stall_detect_remove(struct platform_device *pdev) +{ + int cpu; + + cpuhp_remove_state(vcpu_stall_config.hp_online); + + for_each_possible_cpu(cpu) + stop_stall_detector_cpu(cpu); + + return 0; +} + +static const struct of_device_id vcpu_stall_detect_of_match[] = { + { .compatible = "qemu,vcpu-stall-detector", }, + {} +}; + +MODULE_DEVICE_TABLE(of, vcpu_stall_detect_of_match); + +static struct platform_driver vcpu_stall_detect_driver = { + .probe = vcpu_stall_detect_probe, + .remove = vcpu_stall_detect_remove, + .driver = { + .name = KBUILD_MODNAME, + .of_match_table = vcpu_stall_detect_of_match, + }, +}; + +module_platform_driver(vcpu_stall_detect_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Sebastian Ene "); +MODULE_DESCRIPTION("VCPU stall detector"); diff --git a/drivers/net/wireguard/device.c b/drivers/net/wireguard/device.c index aa9a7a5970fd..d58e9f818d3b 100644 --- a/drivers/net/wireguard/device.c +++ b/drivers/net/wireguard/device.c @@ -69,7 +69,8 @@ static int wg_pm_notification(struct notifier_block *nb, unsigned long action, v * its normal operation rather than as a somewhat rare event, then we * don't actually want to clear keys. */ - if (IS_ENABLED(CONFIG_PM_AUTOSLEEP) || IS_ENABLED(CONFIG_ANDROID)) + if (IS_ENABLED(CONFIG_PM_AUTOSLEEP) || + IS_ENABLED(CONFIG_PM_USERSPACE_AUTOSLEEP)) return 0; if (action != PM_HIBERNATION_PREPARE && action != PM_SUSPEND_PREPARE) diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 967d0084800e..d72d879a6d34 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -107,6 +107,13 @@ config MTK_EFUSE This driver can also be built as a module. If so, the module will be called efuse-mtk. +config MICROCHIP_OTPC + tristate "Microchip OTPC support" + depends on ARCH_AT91 || COMPILE_TEST + help + This driver enable the OTP controller available on Microchip SAMA7G5 + SoCs. It controlls the access to the OTP memory connected to it. + config NVMEM_NINTENDO_OTP tristate "Nintendo Wii and Wii U OTP Support" depends on WII || COMPILE_TEST diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 00e136a0a123..c710b64f9fe4 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -67,3 +67,5 @@ obj-$(CONFIG_NVMEM_SUNPLUS_OCOTP) += nvmem_sunplus_ocotp.o nvmem_sunplus_ocotp-y := sunplus-ocotp.o obj-$(CONFIG_NVMEM_APPLE_EFUSES) += nvmem-apple-efuses.o nvmem-apple-efuses-y := apple-efuses.o +obj-$(CONFIG_MICROCHIP_OTPC) += nvmem-microchip-otpc.o +nvmem-microchip-otpc-y := microchip-otpc.o diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c new file mode 100644 index 000000000000..436e0dc4f337 --- /dev/null +++ b/drivers/nvmem/microchip-otpc.c @@ -0,0 +1,288 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * OTP Memory controller + * + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries + * + * Author: Claudiu Beznea + */ + +#include +#include +#include +#include +#include +#include + +#define MCHP_OTPC_CR (0x0) +#define MCHP_OTPC_CR_READ BIT(6) +#define MCHP_OTPC_MR (0x4) +#define MCHP_OTPC_MR_ADDR GENMASK(31, 16) +#define MCHP_OTPC_AR (0x8) +#define MCHP_OTPC_SR (0xc) +#define MCHP_OTPC_SR_READ BIT(6) +#define MCHP_OTPC_HR (0x20) +#define MCHP_OTPC_HR_SIZE GENMASK(15, 8) +#define MCHP_OTPC_DR (0x24) + +#define MCHP_OTPC_NAME "mchp-otpc" +#define MCHP_OTPC_SIZE (11 * 1024) + +/** + * struct mchp_otpc - OTPC private data structure + * @base: base address + * @dev: struct device pointer + * @packets: list of packets in OTP memory + * @npackets: number of packets in OTP memory + */ +struct mchp_otpc { + void __iomem *base; + struct device *dev; + struct list_head packets; + u32 npackets; +}; + +/** + * struct mchp_otpc_packet - OTPC packet data structure + * @list: list head + * @id: packet ID + * @offset: packet offset (in words) in OTP memory + */ +struct mchp_otpc_packet { + struct list_head list; + u32 id; + u32 offset; +}; + +static struct mchp_otpc_packet *mchp_otpc_id_to_packet(struct mchp_otpc *otpc, + u32 id) +{ + struct mchp_otpc_packet *packet; + + if (id >= otpc->npackets) + return NULL; + + list_for_each_entry(packet, &otpc->packets, list) { + if (packet->id == id) + return packet; + } + + return NULL; +} + +static int mchp_otpc_prepare_read(struct mchp_otpc *otpc, + unsigned int offset) +{ + u32 tmp; + + /* Set address. */ + tmp = readl_relaxed(otpc->base + MCHP_OTPC_MR); + tmp &= ~MCHP_OTPC_MR_ADDR; + tmp |= FIELD_PREP(MCHP_OTPC_MR_ADDR, offset); + writel_relaxed(tmp, otpc->base + MCHP_OTPC_MR); + + /* Set read. */ + tmp = readl_relaxed(otpc->base + MCHP_OTPC_CR); + tmp |= MCHP_OTPC_CR_READ; + writel_relaxed(tmp, otpc->base + MCHP_OTPC_CR); + + /* Wait for packet to be transferred into temporary buffers. */ + return read_poll_timeout(readl_relaxed, tmp, !(tmp & MCHP_OTPC_SR_READ), + 10000, 2000, false, otpc->base + MCHP_OTPC_SR); +} + +/* + * OTPC memory is organized into packets. Each packets contains a header and + * a payload. Header is 4 bytes long and contains the size of the payload. + * Payload size varies. The memory footprint is something as follows: + * + * Memory offset Memory footprint Packet ID + * ------------- ---------------- --------- + * + * 0x0 +------------+ <-- packet 0 + * | header 0 | + * 0x4 +------------+ + * | payload 0 | + * . . + * . ... . + * . . + * offset1 +------------+ <-- packet 1 + * | header 1 | + * offset1 + 0x4 +------------+ + * | payload 1 | + * . . + * . ... . + * . . + * offset2 +------------+ <-- packet 2 + * . . + * . ... . + * . . + * offsetN +------------+ <-- packet N + * | header N | + * offsetN + 0x4 +------------+ + * | payload N | + * . . + * . ... . + * . . + * +------------+ + * + * where offset1, offset2, offsetN depends on the size of payload 0, payload 1, + * payload N-1. + * + * The access to memory is done on a per packet basis: the control registers + * need to be updated with an offset address (within a packet range) and the + * data registers will be update by controller with information contained by + * that packet. E.g. if control registers are updated with any address within + * the range [offset1, offset2) the data registers are updated by controller + * with packet 1. Header data is accessible though MCHP_OTPC_HR register. + * Payload data is accessible though MCHP_OTPC_DR and MCHP_OTPC_AR registers. + * There is no direct mapping b/w the offset requested by software and the + * offset returned by hardware. + * + * For this, the read function will return the first requested bytes in the + * packet. The user will have to be aware of the memory footprint before doing + * the read request. + */ +static int mchp_otpc_read(void *priv, unsigned int off, void *val, + size_t bytes) +{ + struct mchp_otpc *otpc = priv; + struct mchp_otpc_packet *packet; + u32 *buf = val; + u32 offset; + size_t len = 0; + int ret, payload_size; + + /* + * We reach this point with off being multiple of stride = 4 to + * be able to cross the subsystem. Inside the driver we use continuous + * unsigned integer numbers for packet id, thus devide off by 4 + * before passing it to mchp_otpc_id_to_packet(). + */ + packet = mchp_otpc_id_to_packet(otpc, off / 4); + if (!packet) + return -EINVAL; + offset = packet->offset; + + while (len < bytes) { + ret = mchp_otpc_prepare_read(otpc, offset); + if (ret) + return ret; + + /* Read and save header content. */ + *buf++ = readl_relaxed(otpc->base + MCHP_OTPC_HR); + len += sizeof(*buf); + offset++; + if (len >= bytes) + break; + + /* Read and save payload content. */ + payload_size = FIELD_GET(MCHP_OTPC_HR_SIZE, *(buf - 1)); + writel_relaxed(0UL, otpc->base + MCHP_OTPC_AR); + do { + *buf++ = readl_relaxed(otpc->base + MCHP_OTPC_DR); + len += sizeof(*buf); + offset++; + payload_size--; + } while (payload_size >= 0 && len < bytes); + } + + return 0; +} + +static int mchp_otpc_init_packets_list(struct mchp_otpc *otpc, u32 *size) +{ + struct mchp_otpc_packet *packet; + u32 word, word_pos = 0, id = 0, npackets = 0, payload_size; + int ret; + + INIT_LIST_HEAD(&otpc->packets); + *size = 0; + + while (*size < MCHP_OTPC_SIZE) { + ret = mchp_otpc_prepare_read(otpc, word_pos); + if (ret) + return ret; + + word = readl_relaxed(otpc->base + MCHP_OTPC_HR); + payload_size = FIELD_GET(MCHP_OTPC_HR_SIZE, word); + if (!payload_size) + break; + + packet = devm_kzalloc(otpc->dev, sizeof(*packet), GFP_KERNEL); + if (!packet) + return -ENOMEM; + + packet->id = id++; + packet->offset = word_pos; + INIT_LIST_HEAD(&packet->list); + list_add_tail(&packet->list, &otpc->packets); + + /* Count size by adding header and paload sizes. */ + *size += 4 * (payload_size + 1); + /* Next word: this packet (header, payload) position + 1. */ + word_pos += payload_size + 2; + + npackets++; + } + + otpc->npackets = npackets; + + return 0; +} + +static struct nvmem_config mchp_nvmem_config = { + .name = MCHP_OTPC_NAME, + .type = NVMEM_TYPE_OTP, + .read_only = true, + .word_size = 4, + .stride = 4, + .reg_read = mchp_otpc_read, +}; + +static int mchp_otpc_probe(struct platform_device *pdev) +{ + struct nvmem_device *nvmem; + struct mchp_otpc *otpc; + u32 size; + int ret; + + otpc = devm_kzalloc(&pdev->dev, sizeof(*otpc), GFP_KERNEL); + if (!otpc) + return -ENOMEM; + + otpc->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(otpc->base)) + return PTR_ERR(otpc->base); + + otpc->dev = &pdev->dev; + ret = mchp_otpc_init_packets_list(otpc, &size); + if (ret) + return ret; + + mchp_nvmem_config.dev = otpc->dev; + mchp_nvmem_config.size = size; + mchp_nvmem_config.priv = otpc; + nvmem = devm_nvmem_register(&pdev->dev, &mchp_nvmem_config); + + return PTR_ERR_OR_ZERO(nvmem); +} + +static const struct of_device_id __maybe_unused mchp_otpc_ids[] = { + { .compatible = "microchip,sama7g5-otpc", }, + { }, +}; +MODULE_DEVICE_TABLE(of, mchp_otpc_ids); + +static struct platform_driver mchp_otpc_driver = { + .probe = mchp_otpc_probe, + .driver = { + .name = MCHP_OTPC_NAME, + .of_match_table = of_match_ptr(mchp_otpc_ids), + }, +}; +module_platform_driver(mchp_otpc_driver); + +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_DESCRIPTION("Microchip SAMA7G5 OTPC driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/nvmem/mtk-efuse.c b/drivers/nvmem/mtk-efuse.c index e9a375dd84af..a08e0aedd21c 100644 --- a/drivers/nvmem/mtk-efuse.c +++ b/drivers/nvmem/mtk-efuse.c @@ -41,8 +41,7 @@ static int mtk_efuse_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->base = devm_ioremap_resource(dev, res); + priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(priv->base)) return PTR_ERR(priv->base); diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig index 486ca23aba32..ce7ba3eb2a8e 100644 --- a/drivers/phy/amlogic/Kconfig +++ b/drivers/phy/amlogic/Kconfig @@ -37,6 +37,18 @@ config PHY_MESON_GXL_USB2 GXL and GXM SoCs. If unsure, say N. +config PHY_MESON_G12A_MIPI_DPHY_ANALOG + tristate "Meson G12A MIPI Analog DPHY driver" + default ARCH_MESON + depends on OF && (ARCH_MESON || COMPILE_TEST) + select GENERIC_PHY + select MFD_SYSCON + select GENERIC_PHY_MIPI_DPHY + help + Enable this to support the Meson MIPI Analog DPHY found in Meson G12A + SoCs. + If unsure, say N. + config PHY_MESON_G12A_USB2 tristate "Meson G12A USB2 PHY driver" default ARCH_MESON diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile index c0886c850bb0..91e3b9790c03 100644 --- a/drivers/phy/amlogic/Makefile +++ b/drivers/phy/amlogic/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o obj-$(CONFIG_PHY_MESON_G12A_USB2) += phy-meson-g12a-usb2.o obj-$(CONFIG_PHY_MESON_G12A_USB3_PCIE) += phy-meson-g12a-usb3-pcie.o +obj-$(CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG) += phy-meson-g12a-mipi-dphy-analog.o obj-$(CONFIG_PHY_MESON_AXG_PCIE) += phy-meson-axg-pcie.o obj-$(CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG) += phy-meson-axg-mipi-pcie-analog.o obj-$(CONFIG_PHY_MESON_AXG_MIPI_DPHY) += phy-meson-axg-mipi-dphy.o diff --git a/drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c b/drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c index fdbd64c03e12..32d1ff09befb 100644 --- a/drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c +++ b/drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c @@ -136,7 +136,7 @@ /* TWAKEUP. */ #define MIPI_DSI_WAKEUP_TIM 0x20 -/* when in RxULPS check state, after the the logic enable the analog, +/* when in RxULPS check state, after the logic enable the analog, * how long we should wait to check the lP state . */ #define MIPI_DSI_LPOK_TIM 0x24 diff --git a/drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c b/drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c new file mode 100644 index 000000000000..c14089fa7db4 --- /dev/null +++ b/drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Meson G12A MIPI DSI Analog PHY + * + * Copyright (C) 2018 Amlogic, Inc. All rights reserved + * Copyright (C) 2022 BayLibre, SAS + * Author: Neil Armstrong + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define HHI_MIPI_CNTL0 0x00 +#define HHI_MIPI_CNTL0_DIF_REF_CTL1 GENMASK(31, 16) +#define HHI_MIPI_CNTL0_DIF_REF_CTL0 GENMASK(15, 0) + +#define HHI_MIPI_CNTL1 0x04 +#define HHI_MIPI_CNTL1_BANDGAP BIT(16) +#define HHI_MIPI_CNTL2_DIF_REF_CTL2 GENMASK(15, 0) + +#define HHI_MIPI_CNTL2 0x08 +#define HHI_MIPI_CNTL2_DIF_TX_CTL1 GENMASK(31, 16) +#define HHI_MIPI_CNTL2_CH_EN GENMASK(15, 11) +#define HHI_MIPI_CNTL2_DIF_TX_CTL0 GENMASK(10, 0) + +#define DSI_LANE_0 BIT(4) +#define DSI_LANE_1 BIT(3) +#define DSI_LANE_CLK BIT(2) +#define DSI_LANE_2 BIT(1) +#define DSI_LANE_3 BIT(0) + +struct phy_g12a_mipi_dphy_analog_priv { + struct phy *phy; + struct regmap *regmap; + struct phy_configure_opts_mipi_dphy config; +}; + +static int phy_g12a_mipi_dphy_analog_configure(struct phy *phy, + union phy_configure_opts *opts) +{ + struct phy_g12a_mipi_dphy_analog_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy); + if (ret) + return ret; + + memcpy(&priv->config, opts, sizeof(priv->config)); + + return 0; +} + +static int phy_g12a_mipi_dphy_analog_power_on(struct phy *phy) +{ + struct phy_g12a_mipi_dphy_analog_priv *priv = phy_get_drvdata(phy); + unsigned int reg; + + regmap_write(priv->regmap, HHI_MIPI_CNTL0, + FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL0, 0x8) | + FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL1, 0xa487)); + + regmap_write(priv->regmap, HHI_MIPI_CNTL1, + FIELD_PREP(HHI_MIPI_CNTL2_DIF_REF_CTL2, 0x2e) | + HHI_MIPI_CNTL1_BANDGAP); + + regmap_write(priv->regmap, HHI_MIPI_CNTL2, + FIELD_PREP(HHI_MIPI_CNTL2_DIF_TX_CTL0, 0x459) | + FIELD_PREP(HHI_MIPI_CNTL2_DIF_TX_CTL1, 0x2680)); + + reg = DSI_LANE_CLK; + switch (priv->config.lanes) { + case 4: + reg |= DSI_LANE_3; + fallthrough; + case 3: + reg |= DSI_LANE_2; + fallthrough; + case 2: + reg |= DSI_LANE_1; + fallthrough; + case 1: + reg |= DSI_LANE_0; + break; + default: + reg = 0; + } + + regmap_update_bits(priv->regmap, HHI_MIPI_CNTL2, + HHI_MIPI_CNTL2_CH_EN, + FIELD_PREP(HHI_MIPI_CNTL2_CH_EN, reg)); + + return 0; +} + +static int phy_g12a_mipi_dphy_analog_power_off(struct phy *phy) +{ + struct phy_g12a_mipi_dphy_analog_priv *priv = phy_get_drvdata(phy); + + regmap_write(priv->regmap, HHI_MIPI_CNTL0, 0); + regmap_write(priv->regmap, HHI_MIPI_CNTL1, 0); + regmap_write(priv->regmap, HHI_MIPI_CNTL2, 0); + + return 0; +} + +static const struct phy_ops phy_g12a_mipi_dphy_analog_ops = { + .configure = phy_g12a_mipi_dphy_analog_configure, + .power_on = phy_g12a_mipi_dphy_analog_power_on, + .power_off = phy_g12a_mipi_dphy_analog_power_off, + .owner = THIS_MODULE, +}; + +static int phy_g12a_mipi_dphy_analog_probe(struct platform_device *pdev) +{ + struct phy_provider *phy; + struct device *dev = &pdev->dev; + struct phy_g12a_mipi_dphy_analog_priv *priv; + struct device_node *np = dev->of_node, *parent_np; + struct regmap *map; + + priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + /* Get the hhi system controller node */ + parent_np = of_get_parent(np); + map = syscon_node_to_regmap(parent_np); + of_node_put(parent_np); + if (IS_ERR(map)) + return dev_err_probe(dev, PTR_ERR(map), "failed to get HHI regmap\n"); + + priv->regmap = map; + + priv->phy = devm_phy_create(dev, np, &phy_g12a_mipi_dphy_analog_ops); + if (IS_ERR(priv->phy)) + return dev_err_probe(dev, PTR_ERR(priv->phy), "failed to create PHY\n"); + + phy_set_drvdata(priv->phy, priv); + dev_set_drvdata(dev, priv); + + phy = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy); +} + +static const struct of_device_id phy_g12a_mipi_dphy_analog_of_match[] = { + { + .compatible = "amlogic,g12a-mipi-dphy-analog", + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, phy_g12a_mipi_dphy_analog_of_match); + +static struct platform_driver phy_g12a_mipi_dphy_analog_driver = { + .probe = phy_g12a_mipi_dphy_analog_probe, + .driver = { + .name = "phy-meson-g12a-mipi-dphy-analog", + .of_match_table = phy_g12a_mipi_dphy_analog_of_match, + }, +}; +module_platform_driver(phy_g12a_mipi_dphy_analog_driver); + +MODULE_AUTHOR("Neil Armstrong "); +MODULE_DESCRIPTION("Meson G12A MIPI Analog D-PHY driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/phy/broadcom/phy-brcm-usb-init.c b/drivers/phy/broadcom/phy-brcm-usb-init.c index dd0f66288fbd..dddcbd3cd5f3 100644 --- a/drivers/phy/broadcom/phy-brcm-usb-init.c +++ b/drivers/phy/broadcom/phy-brcm-usb-init.c @@ -861,7 +861,7 @@ static void usb_init_common(struct brcm_usb_init_params *params) brcmusb_usb2_eye_fix(ctrl); /* - * Make sure the the second and third memory controller + * Make sure the second and third memory controller * interfaces are enabled if they exist. */ if (USB_CTRL_MASK_FAMILY(params, SETUP, SCB1_EN)) diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c index ba042e39cfaf..3dfdfb33cd0a 100644 --- a/drivers/phy/cadence/cdns-dphy.c +++ b/drivers/phy/cadence/cdns-dphy.c @@ -3,9 +3,11 @@ * Copyright: 2017-2018 Cadence Design Systems, Inc. */ +#include #include #include #include +#include #include #include #include @@ -17,6 +19,7 @@ #define REG_WAKEUP_TIME_NS 800 #define DPHY_PLL_RATE_HZ 108000000 +#define POLL_TIMEOUT_US 1000 /* DPHY registers */ #define DPHY_PMA_CMN(reg) (reg) @@ -45,6 +48,10 @@ #define DPHY_CMN_OPDIV_FROM_REG BIT(6) #define DPHY_CMN_OPDIV(x) ((x) << 7) +#define DPHY_BAND_CFG DPHY_PCS(0x0) +#define DPHY_BAND_CFG_LEFT_BAND GENMASK(4, 0) +#define DPHY_BAND_CFG_RIGHT_BAND GENMASK(9, 5) + #define DPHY_PSM_CFG DPHY_PCS(0x4) #define DPHY_PSM_CFG_FROM_REG BIT(0) #define DPHY_PSM_CLK_DIV(x) ((x) << 1) @@ -57,6 +64,18 @@ #define DSI_NULL_FRAME_OVERHEAD 6 #define DSI_EOT_PKT_SIZE 4 +#define DPHY_TX_J721E_WIZ_PLL_CTRL 0xF04 +#define DPHY_TX_J721E_WIZ_STATUS 0xF08 +#define DPHY_TX_J721E_WIZ_RST_CTRL 0xF0C +#define DPHY_TX_J721E_WIZ_PSM_FREQ 0xF10 + +#define DPHY_TX_J721E_WIZ_IPDIV GENMASK(4, 0) +#define DPHY_TX_J721E_WIZ_OPDIV GENMASK(13, 8) +#define DPHY_TX_J721E_WIZ_FBDIV GENMASK(25, 16) +#define DPHY_TX_J721E_WIZ_LANE_RSTB BIT(31) +#define DPHY_TX_WIZ_PLL_LOCK BIT(31) +#define DPHY_TX_WIZ_O_CMN_READY BIT(31) + struct cdns_dphy_cfg { u8 pll_ipdiv; u8 pll_opdiv; @@ -92,6 +111,12 @@ struct cdns_dphy { struct phy *phy; }; +/* Order of bands is important since the index is the band number. */ +static const unsigned int tx_bands[] = { + 80, 100, 120, 160, 200, 240, 320, 390, 450, 510, 560, 640, 690, 770, + 870, 950, 1000, 1200, 1400, 1600, 1800, 2000, 2200, 2500 +}; + static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy, struct cdns_dphy_cfg *cfg, struct phy_configure_opts_mipi_dphy *opts, @@ -199,6 +224,46 @@ static void cdns_dphy_ref_set_psm_div(struct cdns_dphy *dphy, u8 div) dphy->regs + DPHY_PSM_CFG); } +static unsigned long cdns_dphy_j721e_get_wakeup_time_ns(struct cdns_dphy *dphy) +{ + /* Minimum wakeup time as per MIPI D-PHY spec v1.2 */ + return 1000000; +} + +static void cdns_dphy_j721e_set_pll_cfg(struct cdns_dphy *dphy, + const struct cdns_dphy_cfg *cfg) +{ + u32 status; + + /* + * set the PWM and PLL Byteclk divider settings to recommended values + * which is same as that of in ref ops + */ + writel(DPHY_CMN_PWM_HIGH(6) | DPHY_CMN_PWM_LOW(0x101) | + DPHY_CMN_PWM_DIV(0x8), + dphy->regs + DPHY_CMN_PWM); + + writel((FIELD_PREP(DPHY_TX_J721E_WIZ_IPDIV, cfg->pll_ipdiv) | + FIELD_PREP(DPHY_TX_J721E_WIZ_OPDIV, cfg->pll_opdiv) | + FIELD_PREP(DPHY_TX_J721E_WIZ_FBDIV, cfg->pll_fbdiv)), + dphy->regs + DPHY_TX_J721E_WIZ_PLL_CTRL); + + writel(DPHY_TX_J721E_WIZ_LANE_RSTB, + dphy->regs + DPHY_TX_J721E_WIZ_RST_CTRL); + + readl_poll_timeout(dphy->regs + DPHY_TX_J721E_WIZ_PLL_CTRL, status, + (status & DPHY_TX_WIZ_PLL_LOCK), 0, POLL_TIMEOUT_US); + + readl_poll_timeout(dphy->regs + DPHY_TX_J721E_WIZ_STATUS, status, + (status & DPHY_TX_WIZ_O_CMN_READY), 0, + POLL_TIMEOUT_US); +} + +static void cdns_dphy_j721e_set_psm_div(struct cdns_dphy *dphy, u8 div) +{ + writel(div, dphy->regs + DPHY_TX_J721E_WIZ_PSM_FREQ); +} + /* * This is the reference implementation of DPHY hooks. Specific integration of * this IP may have to re-implement some of them depending on how they decided @@ -210,6 +275,12 @@ static const struct cdns_dphy_ops ref_dphy_ops = { .set_psm_div = cdns_dphy_ref_set_psm_div, }; +static const struct cdns_dphy_ops j721e_dphy_ops = { + .get_wakeup_time_ns = cdns_dphy_j721e_get_wakeup_time_ns, + .set_pll_cfg = cdns_dphy_j721e_set_pll_cfg, + .set_psm_div = cdns_dphy_j721e_set_psm_div, +}; + static int cdns_dphy_config_from_opts(struct phy *phy, struct phy_configure_opts_mipi_dphy *opts, struct cdns_dphy_cfg *cfg) @@ -232,6 +303,24 @@ static int cdns_dphy_config_from_opts(struct phy *phy, return 0; } +static int cdns_dphy_tx_get_band_ctrl(unsigned long hs_clk_rate) +{ + unsigned int rate; + int i; + + rate = hs_clk_rate / 1000000UL; + + if (rate < tx_bands[0]) + return -EOPNOTSUPP; + + for (i = 0; i < ARRAY_SIZE(tx_bands) - 1; i++) { + if (rate >= tx_bands[i] && rate < tx_bands[i + 1]) + return i; + } + + return -EOPNOTSUPP; +} + static int cdns_dphy_validate(struct phy *phy, enum phy_mode mode, int submode, union phy_configure_opts *opts) { @@ -247,7 +336,8 @@ static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts) { struct cdns_dphy *dphy = phy_get_drvdata(phy); struct cdns_dphy_cfg cfg = { 0 }; - int ret; + int ret, band_ctrl; + unsigned int reg; ret = cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg); if (ret) @@ -276,6 +366,14 @@ static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts) */ cdns_dphy_set_pll_cfg(dphy, &cfg); + band_ctrl = cdns_dphy_tx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate); + if (band_ctrl < 0) + return band_ctrl; + + reg = FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND, band_ctrl) | + FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND, band_ctrl); + writel(reg, dphy->regs + DPHY_BAND_CFG); + return 0; } @@ -370,6 +468,7 @@ static int cdns_dphy_remove(struct platform_device *pdev) static const struct of_device_id cdns_dphy_of_match[] = { { .compatible = "cdns,dphy", .data = &ref_dphy_ops }, + { .compatible = "ti,j721e-dphy", .data = &j721e_dphy_ops }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, cdns_dphy_of_match); diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 73fb99ccd525..6e86a6517f37 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -348,7 +348,6 @@ struct cdns_regmap_cdb_context { struct cdns_sierra_phy { struct device *dev; - struct regmap *regmap; const struct cdns_sierra_data *init_data; struct cdns_sierra_inst phys[SIERRA_MAX_LANES]; struct reset_control *phy_rst; diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c index 7c4b8050485f..f099053c583c 100644 --- a/drivers/phy/cadence/phy-cadence-torrent.c +++ b/drivers/phy/cadence/phy-cadence-torrent.c @@ -331,7 +331,6 @@ struct cdns_torrent_phy { struct cdns_torrent_inst phys[MAX_NUM_LANES]; int nsubnodes; const struct cdns_torrent_data *init_data; - struct regmap *regmap; struct regmap *regmap_common_cdb; struct regmap *regmap_phy_pcs_common_cdb; struct regmap *regmap_phy_pma_common_cdb; diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig index f9c54cd02036..853958fb2c06 100644 --- a/drivers/phy/freescale/Kconfig +++ b/drivers/phy/freescale/Kconfig @@ -8,6 +8,15 @@ config PHY_FSL_IMX8MQ_USB select GENERIC_PHY default ARCH_MXC && ARM64 +config PHY_MIXEL_LVDS_PHY + tristate "Mixel LVDS PHY support" + depends on OF + select GENERIC_PHY + select REGMAP_MMIO + help + Enable this to add support for the Mixel LVDS PHY as found + on NXP's i.MX8qm SoC. + config PHY_MIXEL_MIPI_DPHY tristate "Mixel MIPI DSI PHY support" depends on OF && HAS_IOMEM diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile index 3518d5dbe8a7..cedb328bc4d2 100644 --- a/drivers/phy/freescale/Makefile +++ b/drivers/phy/freescale/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o +obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o obj-$(CONFIG_PHY_FSL_LYNX_28G) += phy-fsl-lynx-28g.o diff --git a/drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c b/drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c new file mode 100644 index 000000000000..e514b64bfdab --- /dev/null +++ b/drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c @@ -0,0 +1,450 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2020,2022 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define REG_SET 0x4 +#define REG_CLR 0x8 + +#define PHY_CTRL 0x0 +#define M_MASK GENMASK(18, 17) +#define M(n) FIELD_PREP(M_MASK, (n)) +#define CCM_MASK GENMASK(16, 14) +#define CCM(n) FIELD_PREP(CCM_MASK, (n)) +#define CA_MASK GENMASK(13, 11) +#define CA(n) FIELD_PREP(CA_MASK, (n)) +#define TST_MASK GENMASK(10, 5) +#define TST(n) FIELD_PREP(TST_MASK, (n)) +#define CH_EN(id) BIT(3 + (id)) +#define NB BIT(2) +#define RFB BIT(1) +#define PD BIT(0) + +/* Power On Reset(POR) value */ +#define CTRL_RESET_VAL (M(0x0) | CCM(0x4) | CA(0x4) | TST(0x25)) + +/* PHY initialization value and mask */ +#define CTRL_INIT_MASK (M_MASK | CCM_MASK | CA_MASK | TST_MASK | NB | RFB) +#define CTRL_INIT_VAL (M(0x0) | CCM(0x5) | CA(0x4) | TST(0x25) | RFB) + +#define PHY_STATUS 0x10 +#define LOCK BIT(0) + +#define PHY_NUM 2 + +#define MIN_CLKIN_FREQ (25 * MEGA) +#define MAX_CLKIN_FREQ (165 * MEGA) + +#define PLL_LOCK_SLEEP 10 +#define PLL_LOCK_TIMEOUT 1000 + +struct mixel_lvds_phy { + struct phy *phy; + struct phy_configure_opts_lvds cfg; + unsigned int id; +}; + +struct mixel_lvds_phy_priv { + struct regmap *regmap; + struct mutex lock; /* protect remap access and cfg of our own */ + struct clk *phy_ref_clk; + struct mixel_lvds_phy *phys[PHY_NUM]; +}; + +static int mixel_lvds_phy_init(struct phy *phy) +{ + struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent); + + mutex_lock(&priv->lock); + regmap_update_bits(priv->regmap, + PHY_CTRL, CTRL_INIT_MASK, CTRL_INIT_VAL); + mutex_unlock(&priv->lock); + + return 0; +} + +static int mixel_lvds_phy_power_on(struct phy *phy) +{ + struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent); + struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy); + struct mixel_lvds_phy *companion = priv->phys[lvds_phy->id ^ 1]; + struct phy_configure_opts_lvds *cfg = &lvds_phy->cfg; + u32 val = 0; + u32 locked; + int ret; + + /* The master PHY would power on the slave PHY. */ + if (cfg->is_slave) + return 0; + + ret = clk_prepare_enable(priv->phy_ref_clk); + if (ret < 0) { + dev_err(&phy->dev, + "failed to enable PHY reference clock: %d\n", ret); + return ret; + } + + mutex_lock(&priv->lock); + if (cfg->bits_per_lane_and_dclk_cycle == 7) { + if (cfg->differential_clk_rate < 44000000) + val |= M(0x2); + else if (cfg->differential_clk_rate < 90000000) + val |= M(0x1); + else + val |= M(0x0); + } else { + val = NB; + + if (cfg->differential_clk_rate < 32000000) + val |= M(0x2); + else if (cfg->differential_clk_rate < 63000000) + val |= M(0x1); + else + val |= M(0x0); + } + regmap_update_bits(priv->regmap, PHY_CTRL, M_MASK | NB, val); + + /* + * Enable two channels synchronously, + * if the companion PHY is a slave PHY. + */ + if (companion->cfg.is_slave) + val = CH_EN(0) | CH_EN(1); + else + val = CH_EN(lvds_phy->id); + regmap_write(priv->regmap, PHY_CTRL + REG_SET, val); + + ret = regmap_read_poll_timeout(priv->regmap, PHY_STATUS, locked, + locked, PLL_LOCK_SLEEP, + PLL_LOCK_TIMEOUT); + if (ret < 0) { + dev_err(&phy->dev, "failed to get PHY lock: %d\n", ret); + clk_disable_unprepare(priv->phy_ref_clk); + } + mutex_unlock(&priv->lock); + + return ret; +} + +static int mixel_lvds_phy_power_off(struct phy *phy) +{ + struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent); + struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy); + struct mixel_lvds_phy *companion = priv->phys[lvds_phy->id ^ 1]; + struct phy_configure_opts_lvds *cfg = &lvds_phy->cfg; + + /* The master PHY would power off the slave PHY. */ + if (cfg->is_slave) + return 0; + + mutex_lock(&priv->lock); + if (companion->cfg.is_slave) + regmap_write(priv->regmap, PHY_CTRL + REG_CLR, + CH_EN(0) | CH_EN(1)); + else + regmap_write(priv->regmap, PHY_CTRL + REG_CLR, + CH_EN(lvds_phy->id)); + mutex_unlock(&priv->lock); + + clk_disable_unprepare(priv->phy_ref_clk); + + return 0; +} + +static int mixel_lvds_phy_configure(struct phy *phy, + union phy_configure_opts *opts) +{ + struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent); + struct phy_configure_opts_lvds *cfg = &opts->lvds; + int ret; + + ret = clk_set_rate(priv->phy_ref_clk, cfg->differential_clk_rate); + if (ret) + dev_err(&phy->dev, "failed to set PHY reference clock rate(%lu): %d\n", + cfg->differential_clk_rate, ret); + + return ret; +} + +/* Assume the master PHY's configuration set is cached first. */ +static int mixel_lvds_phy_check_slave(struct phy *slave_phy) +{ + struct device *dev = &slave_phy->dev; + struct mixel_lvds_phy_priv *priv = dev_get_drvdata(dev->parent); + struct mixel_lvds_phy *slv = phy_get_drvdata(slave_phy); + struct mixel_lvds_phy *mst = priv->phys[slv->id ^ 1]; + struct phy_configure_opts_lvds *mst_cfg = &mst->cfg; + struct phy_configure_opts_lvds *slv_cfg = &slv->cfg; + + if (mst_cfg->bits_per_lane_and_dclk_cycle != + slv_cfg->bits_per_lane_and_dclk_cycle) { + dev_err(dev, "number bits mismatch(mst: %u vs slv: %u)\n", + mst_cfg->bits_per_lane_and_dclk_cycle, + slv_cfg->bits_per_lane_and_dclk_cycle); + return -EINVAL; + } + + if (mst_cfg->differential_clk_rate != + slv_cfg->differential_clk_rate) { + dev_err(dev, "dclk rate mismatch(mst: %lu vs slv: %lu)\n", + mst_cfg->differential_clk_rate, + slv_cfg->differential_clk_rate); + return -EINVAL; + } + + if (mst_cfg->lanes != slv_cfg->lanes) { + dev_err(dev, "lanes mismatch(mst: %u vs slv: %u)\n", + mst_cfg->lanes, slv_cfg->lanes); + return -EINVAL; + } + + if (mst_cfg->is_slave == slv_cfg->is_slave) { + dev_err(dev, "master PHY is not found\n"); + return -EINVAL; + } + + return 0; +} + +static int mixel_lvds_phy_validate(struct phy *phy, enum phy_mode mode, + int submode, union phy_configure_opts *opts) +{ + struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent); + struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy); + struct phy_configure_opts_lvds *cfg = &opts->lvds; + int ret = 0; + + if (mode != PHY_MODE_LVDS) { + dev_err(&phy->dev, "invalid PHY mode(%d)\n", mode); + return -EINVAL; + } + + if (cfg->bits_per_lane_and_dclk_cycle != 7 && + cfg->bits_per_lane_and_dclk_cycle != 10) { + dev_err(&phy->dev, "invalid bits per data lane(%u)\n", + cfg->bits_per_lane_and_dclk_cycle); + return -EINVAL; + } + + if (cfg->lanes != 4 && cfg->lanes != 3) { + dev_err(&phy->dev, "invalid data lanes(%u)\n", cfg->lanes); + return -EINVAL; + } + + if (cfg->differential_clk_rate < MIN_CLKIN_FREQ || + cfg->differential_clk_rate > MAX_CLKIN_FREQ) { + dev_err(&phy->dev, "invalid differential clock rate(%lu)\n", + cfg->differential_clk_rate); + return -EINVAL; + } + + mutex_lock(&priv->lock); + /* cache configuration set of our own for check */ + memcpy(&lvds_phy->cfg, cfg, sizeof(*cfg)); + + if (cfg->is_slave) { + ret = mixel_lvds_phy_check_slave(phy); + if (ret) + dev_err(&phy->dev, "failed to check slave PHY: %d\n", ret); + } + mutex_unlock(&priv->lock); + + return ret; +} + +static const struct phy_ops mixel_lvds_phy_ops = { + .init = mixel_lvds_phy_init, + .power_on = mixel_lvds_phy_power_on, + .power_off = mixel_lvds_phy_power_off, + .configure = mixel_lvds_phy_configure, + .validate = mixel_lvds_phy_validate, + .owner = THIS_MODULE, +}; + +static int mixel_lvds_phy_reset(struct device *dev) +{ + struct mixel_lvds_phy_priv *priv = dev_get_drvdata(dev); + int ret; + + ret = pm_runtime_resume_and_get(dev); + if (ret < 0) { + dev_err(dev, "failed to get PM runtime: %d\n", ret); + return ret; + } + + regmap_write(priv->regmap, PHY_CTRL, CTRL_RESET_VAL); + + ret = pm_runtime_put(dev); + if (ret < 0) + dev_err(dev, "failed to put PM runtime: %d\n", ret); + + return ret; +} + +static struct phy *mixel_lvds_phy_xlate(struct device *dev, + struct of_phandle_args *args) +{ + struct mixel_lvds_phy_priv *priv = dev_get_drvdata(dev); + unsigned int phy_id; + + if (args->args_count != 1) { + dev_err(dev, + "invalid argument number(%d) for 'phys' property\n", + args->args_count); + return ERR_PTR(-EINVAL); + } + + phy_id = args->args[0]; + + if (phy_id >= PHY_NUM) { + dev_err(dev, "invalid PHY index(%d)\n", phy_id); + return ERR_PTR(-ENODEV); + } + + return priv->phys[phy_id]->phy; +} + +static int mixel_lvds_phy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct phy_provider *phy_provider; + struct mixel_lvds_phy_priv *priv; + struct mixel_lvds_phy *lvds_phy; + struct phy *phy; + int i; + int ret; + + if (!dev->of_node) + return -ENODEV; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->regmap = syscon_node_to_regmap(dev->of_node->parent); + if (IS_ERR(priv->regmap)) + return dev_err_probe(dev, PTR_ERR(priv->regmap), + "failed to get regmap\n"); + + priv->phy_ref_clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->phy_ref_clk)) + return dev_err_probe(dev, PTR_ERR(priv->phy_ref_clk), + "failed to get PHY reference clock\n"); + + mutex_init(&priv->lock); + + dev_set_drvdata(dev, priv); + + pm_runtime_enable(dev); + + ret = mixel_lvds_phy_reset(dev); + if (ret) { + dev_err(dev, "failed to do POR reset: %d\n", ret); + return ret; + } + + for (i = 0; i < PHY_NUM; i++) { + lvds_phy = devm_kzalloc(dev, sizeof(*lvds_phy), GFP_KERNEL); + if (!lvds_phy) { + ret = -ENOMEM; + goto err; + } + + phy = devm_phy_create(dev, NULL, &mixel_lvds_phy_ops); + if (IS_ERR(phy)) { + ret = PTR_ERR(phy); + dev_err(dev, "failed to create PHY for channel%d: %d\n", + i, ret); + goto err; + } + + lvds_phy->phy = phy; + lvds_phy->id = i; + priv->phys[i] = lvds_phy; + + phy_set_drvdata(phy, lvds_phy); + } + + phy_provider = devm_of_phy_provider_register(dev, mixel_lvds_phy_xlate); + if (IS_ERR(phy_provider)) { + ret = PTR_ERR(phy_provider); + dev_err(dev, "failed to register PHY provider: %d\n", ret); + goto err; + } + + return 0; +err: + pm_runtime_disable(dev); + + return ret; +} + +static int mixel_lvds_phy_remove(struct platform_device *pdev) +{ + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static int __maybe_unused mixel_lvds_phy_runtime_suspend(struct device *dev) +{ + struct mixel_lvds_phy_priv *priv = dev_get_drvdata(dev); + + /* power down */ + mutex_lock(&priv->lock); + regmap_write(priv->regmap, PHY_CTRL + REG_SET, PD); + mutex_unlock(&priv->lock); + + return 0; +} + +static int __maybe_unused mixel_lvds_phy_runtime_resume(struct device *dev) +{ + struct mixel_lvds_phy_priv *priv = dev_get_drvdata(dev); + + /* power up + control initialization */ + mutex_lock(&priv->lock); + regmap_update_bits(priv->regmap, PHY_CTRL, + CTRL_INIT_MASK | PD, CTRL_INIT_VAL); + mutex_unlock(&priv->lock); + + return 0; +} + +static const struct dev_pm_ops mixel_lvds_phy_pm_ops = { + SET_RUNTIME_PM_OPS(mixel_lvds_phy_runtime_suspend, + mixel_lvds_phy_runtime_resume, NULL) +}; + +static const struct of_device_id mixel_lvds_phy_of_match[] = { + { .compatible = "fsl,imx8qm-lvds-phy" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mixel_lvds_phy_of_match); + +static struct platform_driver mixel_lvds_phy_driver = { + .probe = mixel_lvds_phy_probe, + .remove = mixel_lvds_phy_remove, + .driver = { + .pm = &mixel_lvds_phy_pm_ops, + .name = "mixel-lvds-phy", + .of_match_table = mixel_lvds_phy_of_match, + } +}; +module_platform_driver(mixel_lvds_phy_driver); + +MODULE_DESCRIPTION("Mixel LVDS PHY driver"); +MODULE_AUTHOR("Liu Ying "); +MODULE_LICENSE("GPL"); diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig index 55f8e6c048ab..3125ecb5d119 100644 --- a/drivers/phy/mediatek/Kconfig +++ b/drivers/phy/mediatek/Kconfig @@ -2,6 +2,17 @@ # # Phy drivers for Mediatek devices # +config PHY_MTK_PCIE + tristate "MediaTek PCIe-PHY Driver" + depends on ARCH_MEDIATEK || COMPILE_TEST + depends on OF + select GENERIC_PHY + help + Say 'Y' here to add support for MediaTek PCIe PHY driver. + This driver create the basic PHY instance and provides initialize + callback for PCIe GEN3 port, it supports software efuse + initialization. + config PHY_MTK_TPHY tristate "MediaTek T-PHY Driver" depends on ARCH_MEDIATEK || COMPILE_TEST @@ -55,3 +66,11 @@ config PHY_MTK_MIPI_DSI select GENERIC_PHY help Support MIPI DSI for Mediatek SoCs. + +config PHY_MTK_DP + tristate "MediaTek DP-PHY Driver" + depends on ARCH_MEDIATEK || COMPILE_TEST + depends on OF + select GENERIC_PHY + help + Support DisplayPort PHY for MediaTek SoCs. diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile index ace660fbed3a..fb1f8edaffa7 100644 --- a/drivers/phy/mediatek/Makefile +++ b/drivers/phy/mediatek/Makefile @@ -3,6 +3,8 @@ # Makefile for the phy drivers. # +obj-$(CONFIG_PHY_MTK_DP) += phy-mtk-dp.o +obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-mtk-dp.c new file mode 100644 index 000000000000..31266e7ca324 --- /dev/null +++ b/drivers/phy/mediatek/phy-mtk-dp.c @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek DisplayPort PHY driver + * + * Copyright (c) 2022, BayLibre Inc. + * Copyright (c) 2022, MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define PHY_OFFSET 0x1000 + +#define MTK_DP_PHY_DIG_PLL_CTL_1 (PHY_OFFSET + 0x14) +#define TPLL_SSC_EN BIT(3) + +#define MTK_DP_PHY_DIG_BIT_RATE (PHY_OFFSET + 0x3C) +#define BIT_RATE_RBR 0 +#define BIT_RATE_HBR 1 +#define BIT_RATE_HBR2 2 +#define BIT_RATE_HBR3 3 + +#define MTK_DP_PHY_DIG_SW_RST (PHY_OFFSET + 0x38) +#define DP_GLB_SW_RST_PHYD BIT(0) + +#define MTK_DP_LANE0_DRIVING_PARAM_3 (PHY_OFFSET + 0x138) +#define MTK_DP_LANE1_DRIVING_PARAM_3 (PHY_OFFSET + 0x238) +#define MTK_DP_LANE2_DRIVING_PARAM_3 (PHY_OFFSET + 0x338) +#define MTK_DP_LANE3_DRIVING_PARAM_3 (PHY_OFFSET + 0x438) +#define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT BIT(4) +#define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT (BIT(10) | BIT(12)) +#define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT GENMASK(20, 19) +#define XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT GENMASK(29, 29) +#define DRIVING_PARAM_3_DEFAULT (XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT) + +#define XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT GENMASK(4, 3) +#define XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT GENMASK(12, 9) +#define XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT (BIT(18) | BIT(21)) +#define XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT GENMASK(29, 29) +#define DRIVING_PARAM_4_DEFAULT (XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT) + +#define XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT (BIT(3) | BIT(5)) +#define XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT GENMASK(13, 12) +#define DRIVING_PARAM_5_DEFAULT (XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT) + +#define XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT 0 +#define XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT GENMASK(10, 10) +#define XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT GENMASK(19, 19) +#define XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT GENMASK(28, 28) +#define DRIVING_PARAM_6_DEFAULT (XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT) + +#define XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT 0 +#define XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT GENMASK(10, 9) +#define XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT GENMASK(19, 18) +#define XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT 0 +#define DRIVING_PARAM_7_DEFAULT (XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT) + +#define XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT GENMASK(3, 3) +#define XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT 0 +#define DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT) + +struct mtk_dp_phy { + struct regmap *regs; +}; + +static int mtk_dp_phy_init(struct phy *phy) +{ + struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); + u32 driving_params[] = { + DRIVING_PARAM_3_DEFAULT, + DRIVING_PARAM_4_DEFAULT, + DRIVING_PARAM_5_DEFAULT, + DRIVING_PARAM_6_DEFAULT, + DRIVING_PARAM_7_DEFAULT, + DRIVING_PARAM_8_DEFAULT + }; + + regmap_bulk_write(dp_phy->regs, MTK_DP_LANE0_DRIVING_PARAM_3, + driving_params, ARRAY_SIZE(driving_params)); + regmap_bulk_write(dp_phy->regs, MTK_DP_LANE1_DRIVING_PARAM_3, + driving_params, ARRAY_SIZE(driving_params)); + regmap_bulk_write(dp_phy->regs, MTK_DP_LANE2_DRIVING_PARAM_3, + driving_params, ARRAY_SIZE(driving_params)); + regmap_bulk_write(dp_phy->regs, MTK_DP_LANE3_DRIVING_PARAM_3, + driving_params, ARRAY_SIZE(driving_params)); + + return 0; +} + +static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) +{ + struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); + u32 val; + + if (opts->dp.set_rate) { + switch (opts->dp.link_rate) { + default: + dev_err(&phy->dev, + "Implementation error, unknown linkrate %x\n", + opts->dp.link_rate); + return -EINVAL; + case 1620: + val = BIT_RATE_RBR; + break; + case 2700: + val = BIT_RATE_HBR; + break; + case 5400: + val = BIT_RATE_HBR2; + break; + case 8100: + val = BIT_RATE_HBR3; + break; + } + regmap_write(dp_phy->regs, MTK_DP_PHY_DIG_BIT_RATE, val); + } + + regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_PLL_CTL_1, + TPLL_SSC_EN, opts->dp.ssc ? TPLL_SSC_EN : 0); + + return 0; +} + +static int mtk_dp_phy_reset(struct phy *phy) +{ + struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); + + regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST, + DP_GLB_SW_RST_PHYD, 0); + usleep_range(50, 200); + regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST, + DP_GLB_SW_RST_PHYD, 1); + + return 0; +} + +static const struct phy_ops mtk_dp_phy_dev_ops = { + .init = mtk_dp_phy_init, + .configure = mtk_dp_phy_configure, + .reset = mtk_dp_phy_reset, + .owner = THIS_MODULE, +}; + +static int mtk_dp_phy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mtk_dp_phy *dp_phy; + struct phy *phy; + struct regmap *regs; + + regs = *(struct regmap **)dev->platform_data; + if (!regs) + return dev_err_probe(dev, EINVAL, + "No data passed, requires struct regmap**\n"); + + dp_phy = devm_kzalloc(dev, sizeof(*dp_phy), GFP_KERNEL); + if (!dp_phy) + return -ENOMEM; + + dp_phy->regs = regs; + phy = devm_phy_create(dev, NULL, &mtk_dp_phy_dev_ops); + if (IS_ERR(phy)) + return dev_err_probe(dev, PTR_ERR(phy), + "Failed to create DP PHY\n"); + + phy_set_drvdata(phy, dp_phy); + if (!dev->of_node) + phy_create_lookup(phy, "dp", dev_name(dev)); + + return 0; +} + +static struct platform_driver mtk_dp_phy_driver = { + .probe = mtk_dp_phy_probe, + .driver = { + .name = "mediatek-dp-phy", + }, +}; +module_platform_driver(mtk_dp_phy_driver); + +MODULE_AUTHOR("Markus Schneider-Pargmann "); +MODULE_DESCRIPTION("MediaTek DP PHY Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/phy/mediatek/phy-mtk-pcie.c b/drivers/phy/mediatek/phy-mtk-pcie.c new file mode 100644 index 000000000000..7f29d43442bf --- /dev/null +++ b/drivers/phy/mediatek/phy-mtk-pcie.c @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Jianjun Wang + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "phy-mtk-io.h" + +#define PEXTP_ANA_GLB_00_REG 0x9000 +/* Internal Resistor Selection of TX Bias Current */ +#define EFUSE_GLB_INTR_SEL GENMASK(28, 24) + +#define PEXTP_ANA_LN0_TRX_REG 0xa000 + +#define PEXTP_ANA_TX_REG 0x04 +/* TX PMOS impedance selection */ +#define EFUSE_LN_TX_PMOS_SEL GENMASK(5, 2) +/* TX NMOS impedance selection */ +#define EFUSE_LN_TX_NMOS_SEL GENMASK(11, 8) + +#define PEXTP_ANA_RX_REG 0x3c +/* RX impedance selection */ +#define EFUSE_LN_RX_SEL GENMASK(3, 0) + +#define PEXTP_ANA_LANE_OFFSET 0x100 + +/** + * struct mtk_pcie_lane_efuse - eFuse data for each lane + * @tx_pmos: TX PMOS impedance selection data + * @tx_nmos: TX NMOS impedance selection data + * @rx_data: RX impedance selection data + * @lane_efuse_supported: software eFuse data is supported for this lane + */ +struct mtk_pcie_lane_efuse { + u32 tx_pmos; + u32 tx_nmos; + u32 rx_data; + bool lane_efuse_supported; +}; + +/** + * struct mtk_pcie_phy_data - phy data for each SoC + * @num_lanes: supported lane numbers + * @sw_efuse_supported: support software to load eFuse data + */ +struct mtk_pcie_phy_data { + int num_lanes; + bool sw_efuse_supported; +}; + +/** + * struct mtk_pcie_phy - PCIe phy driver main structure + * @dev: pointer to device + * @phy: pointer to generic phy + * @sif_base: IO mapped register base address of system interface + * @data: pointer to SoC dependent data + * @sw_efuse_en: software eFuse enable status + * @efuse_glb_intr: internal resistor selection of TX bias current data + * @efuse: pointer to eFuse data for each lane + */ +struct mtk_pcie_phy { + struct device *dev; + struct phy *phy; + void __iomem *sif_base; + const struct mtk_pcie_phy_data *data; + + bool sw_efuse_en; + u32 efuse_glb_intr; + struct mtk_pcie_lane_efuse *efuse; +}; + +static void mtk_pcie_efuse_set_lane(struct mtk_pcie_phy *pcie_phy, + unsigned int lane) +{ + struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane]; + void __iomem *addr; + + if (!data->lane_efuse_supported) + return; + + addr = pcie_phy->sif_base + PEXTP_ANA_LN0_TRX_REG + + lane * PEXTP_ANA_LANE_OFFSET; + + mtk_phy_update_bits(addr + PEXTP_ANA_TX_REG, EFUSE_LN_TX_PMOS_SEL, + FIELD_PREP(EFUSE_LN_TX_PMOS_SEL, data->tx_pmos)); + + mtk_phy_update_bits(addr + PEXTP_ANA_TX_REG, EFUSE_LN_TX_NMOS_SEL, + FIELD_PREP(EFUSE_LN_TX_NMOS_SEL, data->tx_nmos)); + + mtk_phy_update_bits(addr + PEXTP_ANA_RX_REG, EFUSE_LN_RX_SEL, + FIELD_PREP(EFUSE_LN_RX_SEL, data->rx_data)); +} + +/** + * mtk_pcie_phy_init() - Initialize the phy + * @phy: the phy to be initialized + * + * Initialize the phy by setting the efuse data. + * The hardware settings will be reset during suspend, it should be + * reinitialized when the consumer calls phy_init() again on resume. + */ +static int mtk_pcie_phy_init(struct phy *phy) +{ + struct mtk_pcie_phy *pcie_phy = phy_get_drvdata(phy); + int i; + + if (!pcie_phy->sw_efuse_en) + return 0; + + /* Set global data */ + mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG, + EFUSE_GLB_INTR_SEL, + FIELD_PREP(EFUSE_GLB_INTR_SEL, pcie_phy->efuse_glb_intr)); + + for (i = 0; i < pcie_phy->data->num_lanes; i++) + mtk_pcie_efuse_set_lane(pcie_phy, i); + + return 0; +} + +static const struct phy_ops mtk_pcie_phy_ops = { + .init = mtk_pcie_phy_init, + .owner = THIS_MODULE, +}; + +static int mtk_pcie_efuse_read_for_lane(struct mtk_pcie_phy *pcie_phy, + unsigned int lane) +{ + struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane]; + struct device *dev = pcie_phy->dev; + char efuse_id[16]; + int ret; + + snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_pmos", lane); + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_pmos); + if (ret) + return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id); + + snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_nmos", lane); + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_nmos); + if (ret) + return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id); + + snprintf(efuse_id, sizeof(efuse_id), "rx_ln%d", lane); + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->rx_data); + if (ret) + return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id); + + if (!(efuse->tx_pmos || efuse->tx_nmos || efuse->rx_data)) + return dev_err_probe(dev, -EINVAL, + "No eFuse data found for lane%d, but dts enable it\n", + lane); + + efuse->lane_efuse_supported = true; + + return 0; +} + +static int mtk_pcie_read_efuse(struct mtk_pcie_phy *pcie_phy) +{ + struct device *dev = pcie_phy->dev; + bool nvmem_enabled; + int ret, i; + + /* nvmem data is optional */ + nvmem_enabled = device_property_present(dev, "nvmem-cells"); + if (!nvmem_enabled) + return 0; + + ret = nvmem_cell_read_variable_le_u32(dev, "glb_intr", + &pcie_phy->efuse_glb_intr); + if (ret) + return dev_err_probe(dev, ret, "Failed to read glb_intr\n"); + + pcie_phy->sw_efuse_en = true; + + pcie_phy->efuse = devm_kzalloc(dev, pcie_phy->data->num_lanes * + sizeof(*pcie_phy->efuse), GFP_KERNEL); + if (!pcie_phy->efuse) + return -ENOMEM; + + for (i = 0; i < pcie_phy->data->num_lanes; i++) { + ret = mtk_pcie_efuse_read_for_lane(pcie_phy, i); + if (ret) + return ret; + } + + return 0; +} + +static int mtk_pcie_phy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct phy_provider *provider; + struct mtk_pcie_phy *pcie_phy; + int ret; + + pcie_phy = devm_kzalloc(dev, sizeof(*pcie_phy), GFP_KERNEL); + if (!pcie_phy) + return -ENOMEM; + + pcie_phy->sif_base = devm_platform_ioremap_resource_byname(pdev, "sif"); + if (IS_ERR(pcie_phy->sif_base)) + return dev_err_probe(dev, PTR_ERR(pcie_phy->sif_base), + "Failed to map phy-sif base\n"); + + pcie_phy->phy = devm_phy_create(dev, dev->of_node, &mtk_pcie_phy_ops); + if (IS_ERR(pcie_phy->phy)) + return dev_err_probe(dev, PTR_ERR(pcie_phy->phy), + "Failed to create PCIe phy\n"); + + pcie_phy->dev = dev; + pcie_phy->data = of_device_get_match_data(dev); + if (!pcie_phy->data) + return dev_err_probe(dev, -EINVAL, "Failed to get phy data\n"); + + if (pcie_phy->data->sw_efuse_supported) { + /* + * Failed to read the efuse data is not a fatal problem, + * ignore the failure and keep going. + */ + ret = mtk_pcie_read_efuse(pcie_phy); + if (ret == -EPROBE_DEFER || ret == -ENOMEM) + return ret; + } + + phy_set_drvdata(pcie_phy->phy, pcie_phy); + + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (IS_ERR(provider)) + return dev_err_probe(dev, PTR_ERR(provider), + "PCIe phy probe failed\n"); + + return 0; +} + +static const struct mtk_pcie_phy_data mt8195_data = { + .num_lanes = 2, + .sw_efuse_supported = true, +}; + +static const struct of_device_id mtk_pcie_phy_of_match[] = { + { .compatible = "mediatek,mt8195-pcie-phy", .data = &mt8195_data }, + { }, +}; +MODULE_DEVICE_TABLE(of, mtk_pcie_phy_of_match); + +static struct platform_driver mtk_pcie_phy_driver = { + .probe = mtk_pcie_phy_probe, + .driver = { + .name = "mtk-pcie-phy", + .of_match_table = mtk_pcie_phy_of_match, + }, +}; +module_platform_driver(mtk_pcie_phy_driver); + +MODULE_DESCRIPTION("MediaTek PCIe PHY driver"); +MODULE_AUTHOR("Jianjun Wang "); +MODULE_LICENSE("GPL"); diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index e9e3b1a4dbb0..65f6c30a3e93 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -5,7 +5,13 @@ obj-$(CONFIG_PHY_QCOM_EDP) += phy-qcom-edp.o obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o -obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o +obj-$(CONFIG_PHY_QCOM_QMP) += \ + phy-qcom-qmp-combo.o \ + phy-qcom-qmp-pcie.o \ + phy-qcom-qmp-pcie-msm8996.o \ + phy-qcom-qmp-ufs.o \ + phy-qcom-qmp-usb.o + obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c index cacd32f6e0cc..7e3570789845 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -639,6 +639,18 @@ static int qcom_edp_phy_probe(struct platform_device *pdev) if (ret) return ret; + ret = regulator_set_load(edp->supplies[0].consumer, 21800); /* 1.2 V vdda-phy */ + if (ret) { + dev_err(dev, "failed to set load at %s\n", edp->supplies[0].supply); + return ret; + } + + ret = regulator_set_load(edp->supplies[1].consumer, 36000); /* 0.9 V vdda-pll */ + if (ret) { + dev_err(dev, "failed to set load at %s\n", edp->supplies[1].supply); + return ret; + } + ret = qcom_edp_clks_register(edp, pdev->dev.of_node); if (ret) return ret; diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c new file mode 100644 index 000000000000..4b1828976104 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -0,0 +1,2621 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "phy-qcom-qmp.h" + +/* QPHY_SW_RESET bit */ +#define SW_RESET BIT(0) +/* QPHY_POWER_DOWN_CONTROL */ +#define SW_PWRDN BIT(0) +#define REFCLK_DRV_DSBL BIT(1) +/* QPHY_START_CONTROL bits */ +#define SERDES_START BIT(0) +#define PCS_START BIT(1) +#define PLL_READY_GATE_EN BIT(3) +/* QPHY_PCS_STATUS bit */ +#define PHYSTATUS BIT(6) +#define PHYSTATUS_4_20 BIT(7) +/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ +#define PCS_READY BIT(0) + +/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ +/* DP PHY soft reset */ +#define SW_DPPHY_RESET BIT(0) +/* mux to select DP PHY reset control, 0:HW control, 1: software reset */ +#define SW_DPPHY_RESET_MUX BIT(1) +/* USB3 PHY soft reset */ +#define SW_USB3PHY_RESET BIT(2) +/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ +#define SW_USB3PHY_RESET_MUX BIT(3) + +/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ +#define USB3_MODE BIT(0) /* enables USB3 mode */ +#define DP_MODE BIT(1) /* enables DP mode */ + +/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ +#define ARCVR_DTCT_EN BIT(0) +#define ALFPS_DTCT_EN BIT(1) +#define ARCVR_DTCT_EVENT_SEL BIT(4) + +/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ +#define IRQ_CLEAR BIT(0) + +/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ +#define RCVR_DETECT BIT(0) + +/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ +#define CLAMP_EN BIT(0) /* enables i/o clamp_n */ + +#define PHY_INIT_COMPLETE_TIMEOUT 10000 +#define POWER_DOWN_DELAY_US_MIN 10 +#define POWER_DOWN_DELAY_US_MAX 11 + +#define MAX_PROP_NAME 32 + +/* Define the assumed distance between lanes for underspecified device trees. */ +#define QMP_PHY_LEGACY_LANE_STRIDE 0x400 + +struct qmp_phy_init_tbl { + unsigned int offset; + unsigned int val; + /* + * register part of layout ? + * if yes, then offset gives index in the reg-layout + */ + bool in_layout; + /* + * mask of lanes for which this register is written + * for cases when second lane needs different values + */ + u8 lane_mask; +}; + +#define QMP_PHY_INIT_CFG(o, v) \ + { \ + .offset = o, \ + .val = v, \ + .lane_mask = 0xff, \ + } + +#define QMP_PHY_INIT_CFG_L(o, v) \ + { \ + .offset = o, \ + .val = v, \ + .in_layout = true, \ + .lane_mask = 0xff, \ + } + +#define QMP_PHY_INIT_CFG_LANE(o, v, l) \ + { \ + .offset = o, \ + .val = v, \ + .lane_mask = l, \ + } + +/* set of registers with offsets different per-PHY */ +enum qphy_reg_layout { + /* Common block control registers */ + QPHY_COM_SW_RESET, + QPHY_COM_POWER_DOWN_CONTROL, + QPHY_COM_START_CONTROL, + QPHY_COM_PCS_READY_STATUS, + /* PCS registers */ + QPHY_SW_RESET, + QPHY_START_CTRL, + QPHY_PCS_READY_STATUS, + QPHY_PCS_STATUS, + QPHY_PCS_AUTONOMOUS_MODE_CTRL, + QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, + QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, + QPHY_PCS_POWER_DOWN_CONTROL, + /* PCS_MISC registers */ + QPHY_PCS_MISC_TYPEC_CTRL, + /* Keep last to ensure regs_layout arrays are properly initialized */ + QPHY_LAYOUT_SIZE +}; + +static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = 0x00, + [QPHY_START_CTRL] = 0x08, + [QPHY_PCS_STATUS] = 0x174, + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8, + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc, + [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170, +}; + +static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = 0x00, + [QPHY_START_CTRL] = 0x44, + [QPHY_PCS_STATUS] = 0x14, + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, + + /* In PCS_USB */ + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x008, + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x014, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), +}; + +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), +}; + +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), +}; + +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), +}; + +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), +}; + +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), +}; + +static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { + /* FLL settings */ + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), + + /* Lock Det settings */ + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), + + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), + + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), +}; + +static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), +}; + +static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), +}; + +static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), +}; + +static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { + /* Lock Det settings */ + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), + + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), +}; + +static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), +}; + +static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), +}; + +static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), +}; + +static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), +}; + +static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), +}; + +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), +}; + +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), +}; + +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), +}; + +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), +}; + +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), +}; + +static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), +}; + + +/* list of regulators */ +struct qmp_regulator_data { + const char *name; + unsigned int enable_load; +}; + +static struct qmp_regulator_data qmp_phy_vreg_l[] = { + { .name = "vdda-phy", .enable_load = 21800 }, + { .name = "vdda-pll", .enable_load = 36000 }, +}; + +struct qmp_phy; + +/* struct qmp_phy_cfg - per-PHY initialization config */ +struct qmp_phy_cfg { + /* phy-type - PCIE/UFS/USB */ + unsigned int type; + /* number of lanes provided by phy */ + int nlanes; + + /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_init_tbl *serdes_tbl; + int serdes_tbl_num; + const struct qmp_phy_init_tbl *tx_tbl; + int tx_tbl_num; + const struct qmp_phy_init_tbl *rx_tbl; + int rx_tbl_num; + const struct qmp_phy_init_tbl *pcs_tbl; + int pcs_tbl_num; + const struct qmp_phy_init_tbl *pcs_usb_tbl; + int pcs_usb_tbl_num; + + /* Init sequence for DP PHY block link rates */ + const struct qmp_phy_init_tbl *serdes_tbl_rbr; + int serdes_tbl_rbr_num; + const struct qmp_phy_init_tbl *serdes_tbl_hbr; + int serdes_tbl_hbr_num; + const struct qmp_phy_init_tbl *serdes_tbl_hbr2; + int serdes_tbl_hbr2_num; + const struct qmp_phy_init_tbl *serdes_tbl_hbr3; + int serdes_tbl_hbr3_num; + + /* DP PHY callbacks */ + int (*configure_dp_phy)(struct qmp_phy *qphy); + void (*configure_dp_tx)(struct qmp_phy *qphy); + int (*calibrate_dp_phy)(struct qmp_phy *qphy); + void (*dp_aux_init)(struct qmp_phy *qphy); + + /* clock ids to be requested */ + const char * const *clk_list; + int num_clks; + /* resets to be requested */ + const char * const *reset_list; + int num_resets; + /* regulators to be requested */ + const struct qmp_regulator_data *vreg_list; + int num_vregs; + + /* array of registers with different offsets */ + const unsigned int *regs; + + unsigned int start_ctrl; + unsigned int pwrdn_ctrl; + /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ + unsigned int phy_status; + + /* true, if PHY needs delay after POWER_DOWN */ + bool has_pwrdn_delay; + /* power_down delay in usec */ + int pwrdn_delay_min; + int pwrdn_delay_max; + + /* true, if PHY has a separate DP_COM control block */ + bool has_phy_dp_com_ctrl; + /* true, if PHY has secondary tx/rx lanes to be configured */ + bool is_dual_lane_phy; + + /* Offset from PCS to PCS_USB region */ + unsigned int pcs_usb_offset; + +}; + +struct qmp_phy_combo_cfg { + const struct qmp_phy_cfg *usb_cfg; + const struct qmp_phy_cfg *dp_cfg; +}; + +/** + * struct qmp_phy - per-lane phy descriptor + * + * @phy: generic phy + * @cfg: phy specific configuration + * @serdes: iomapped memory space for phy's serdes (i.e. PLL) + * @tx: iomapped memory space for lane's tx + * @rx: iomapped memory space for lane's rx + * @pcs: iomapped memory space for lane's pcs + * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) + * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) + * @pcs_misc: iomapped memory space for lane's pcs_misc + * @pcs_usb: iomapped memory space for lane's pcs_usb + * @pipe_clk: pipe clock + * @index: lane index + * @qmp: QMP phy to which this lane belongs + * @lane_rst: lane's reset controller + * @mode: current PHY mode + * @dp_aux_cfg: Display port aux config + * @dp_opts: Display port optional config + * @dp_clks: Display port clocks + */ +struct qmp_phy { + struct phy *phy; + const struct qmp_phy_cfg *cfg; + void __iomem *serdes; + void __iomem *tx; + void __iomem *rx; + void __iomem *pcs; + void __iomem *tx2; + void __iomem *rx2; + void __iomem *pcs_misc; + void __iomem *pcs_usb; + struct clk *pipe_clk; + unsigned int index; + struct qcom_qmp *qmp; + struct reset_control *lane_rst; + enum phy_mode mode; + unsigned int dp_aux_cfg; + struct phy_configure_opts_dp dp_opts; + struct qmp_phy_dp_clks *dp_clks; +}; + +struct qmp_phy_dp_clks { + struct qmp_phy *qphy; + struct clk_hw dp_link_hw; + struct clk_hw dp_pixel_hw; +}; + +/** + * struct qcom_qmp - structure holding QMP phy block attributes + * + * @dev: device + * @dp_com: iomapped memory space for phy's dp_com control block + * + * @clks: array of clocks required by phy + * @resets: array of resets required by phy + * @vregs: regulator supplies bulk data + * + * @phys: array of per-lane phy descriptors + * @phy_mutex: mutex lock for PHY common block initialization + * @init_count: phy common block initialization count + * @ufs_reset: optional UFS PHY reset handle + */ +struct qcom_qmp { + struct device *dev; + void __iomem *dp_com; + + struct clk_bulk_data *clks; + struct reset_control_bulk_data *resets; + struct regulator_bulk_data *vregs; + + struct qmp_phy **phys; + + struct mutex phy_mutex; + int init_count; + + struct reset_control *ufs_reset; +}; + +static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy); +static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy); +static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy); +static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy); + +static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy); +static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy); +static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy); +static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy); + +static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) +{ + u32 reg; + + reg = readl(base + offset); + reg |= val; + writel(reg, base + offset); + + /* ensure that above write is through */ + readl(base + offset); +} + +static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) +{ + u32 reg; + + reg = readl(base + offset); + reg &= ~val; + writel(reg, base + offset); + + /* ensure that above write is through */ + readl(base + offset); +} + +/* list of clocks required by phy */ +static const char * const qmp_v3_phy_clk_l[] = { + "aux", "cfg_ahb", "ref", "com_aux", +}; + +static const char * const qmp_v4_phy_clk_l[] = { + "aux", "ref_clk_src", "ref", "com_aux", +}; + +/* the primary usb3 phy on sm8250 doesn't have a ref clock */ +static const char * const qmp_v4_sm8250_usbphy_clk_l[] = { + "aux", "ref_clk_src", "com_aux" +}; + +/* list of resets */ +static const char * const msm8996_usb3phy_reset_l[] = { + "phy", "common", +}; + +static const char * const sc7180_usb3phy_reset_l[] = { + "phy", +}; + +static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = qmp_v3_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), + .tx_tbl = qmp_v3_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), + .rx_tbl = qmp_v3_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), + .pcs_tbl = qmp_v3_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), + .clk_list = qmp_v3_phy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), + .reset_list = sc7180_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v3_usb3phy_regs_layout, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, + + .has_phy_dp_com_ctrl = true, + .is_dual_lane_phy = true, +}; + +static const struct qmp_phy_cfg sc7180_dpphy_cfg = { + .type = PHY_TYPE_DP, + .nlanes = 1, + + .serdes_tbl = qmp_v3_dp_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), + .tx_tbl = qmp_v3_dp_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), + + .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), + .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), + .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), + .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), + + .clk_list = qmp_v3_phy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), + .reset_list = sc7180_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v3_usb3phy_regs_layout, + + .has_phy_dp_com_ctrl = true, + .is_dual_lane_phy = true, + + .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init, + .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx, + .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy, + .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate, +}; + +static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = { + .usb_cfg = &sc7180_usb3phy_cfg, + .dp_cfg = &sc7180_dpphy_cfg, +}; + +static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = sm8150_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), + .tx_tbl = sm8150_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), + .rx_tbl = sm8150_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), + .pcs_tbl = sm8150_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), + .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl, + .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl), + .clk_list = qmp_v4_phy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v4_usb3phy_regs_layout, + .pcs_usb_offset = 0x300, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + + .has_pwrdn_delay = true, + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, + + .has_phy_dp_com_ctrl = true, + .is_dual_lane_phy = true, +}; + +static const struct qmp_phy_cfg sc8180x_dpphy_cfg = { + .type = PHY_TYPE_DP, + .nlanes = 1, + + .serdes_tbl = qmp_v4_dp_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), + .tx_tbl = qmp_v4_dp_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), + + .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), + .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), + .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), + .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), + + .clk_list = qmp_v3_phy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), + .reset_list = sc7180_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v3_usb3phy_regs_layout, + + .has_phy_dp_com_ctrl = true, + .is_dual_lane_phy = true, + + .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, + .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, + .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, + .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, +}; + +static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = { + .usb_cfg = &sm8150_usb3phy_cfg, + .dp_cfg = &sc8180x_dpphy_cfg, +}; + +static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = sm8150_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), + .tx_tbl = sm8250_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), + .rx_tbl = sm8250_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), + .pcs_tbl = sm8250_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), + .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl, + .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl), + .clk_list = qmp_v4_sm8250_usbphy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v4_usb3phy_regs_layout, + .pcs_usb_offset = 0x300, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, + + .has_phy_dp_com_ctrl = true, + .is_dual_lane_phy = true, +}; + +static const struct qmp_phy_cfg sm8250_dpphy_cfg = { + .type = PHY_TYPE_DP, + .nlanes = 1, + + .serdes_tbl = qmp_v4_dp_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), + .tx_tbl = qmp_v4_dp_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), + + .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), + .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), + .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), + .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), + + .clk_list = qmp_v4_phy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v4_usb3phy_regs_layout, + + .has_phy_dp_com_ctrl = true, + .is_dual_lane_phy = true, + + .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, + .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, + .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, + .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, +}; + +static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = { + .usb_cfg = &sm8250_usb3phy_cfg, + .dp_cfg = &sm8250_dpphy_cfg, +}; + +static void qcom_qmp_phy_combo_configure_lane(void __iomem *base, + const unsigned int *regs, + const struct qmp_phy_init_tbl tbl[], + int num, + u8 lane_mask) +{ + int i; + const struct qmp_phy_init_tbl *t = tbl; + + if (!t) + return; + + for (i = 0; i < num; i++, t++) { + if (!(t->lane_mask & lane_mask)) + continue; + + if (t->in_layout) + writel(t->val, base + regs[t->offset]); + else + writel(t->val, base + t->offset); + } +} + +static void qcom_qmp_phy_combo_configure(void __iomem *base, + const unsigned int *regs, + const struct qmp_phy_init_tbl tbl[], + int num) +{ + qcom_qmp_phy_combo_configure_lane(base, regs, tbl, num, 0xff); +} + +static int qcom_qmp_phy_combo_serdes_init(struct qmp_phy *qphy) +{ + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *serdes = qphy->serdes; + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; + const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; + int serdes_tbl_num = cfg->serdes_tbl_num; + + qcom_qmp_phy_combo_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); + + if (cfg->type == PHY_TYPE_DP) { + switch (dp_opts->link_rate) { + case 1620: + qcom_qmp_phy_combo_configure(serdes, cfg->regs, + cfg->serdes_tbl_rbr, + cfg->serdes_tbl_rbr_num); + break; + case 2700: + qcom_qmp_phy_combo_configure(serdes, cfg->regs, + cfg->serdes_tbl_hbr, + cfg->serdes_tbl_hbr_num); + break; + case 5400: + qcom_qmp_phy_combo_configure(serdes, cfg->regs, + cfg->serdes_tbl_hbr2, + cfg->serdes_tbl_hbr2_num); + break; + case 8100: + qcom_qmp_phy_combo_configure(serdes, cfg->regs, + cfg->serdes_tbl_hbr3, + cfg->serdes_tbl_hbr3_num); + break; + default: + /* Other link rates aren't supported */ + return -EINVAL; + } + } + + return 0; +} + +static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy) +{ + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, + qphy->pcs + QSERDES_DP_PHY_PD_CTL); + + /* Turn on BIAS current for PHY/PLL */ + writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | + QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, + qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); + + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); + + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_LANE_0_1_PWRDN | + DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | + DP_PHY_PD_CTL_DP_CLAMP_EN, + qphy->pcs + QSERDES_DP_PHY_PD_CTL); + + writel(QSERDES_V3_COM_BIAS_EN | + QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | + QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | + QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, + qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); + + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); + writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); + writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); + writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); + writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); + qphy->dp_aux_cfg = 0; + + writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | + PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | + PHY_AUX_REQ_ERR_MASK, + qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); +} + +static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { + { 0x00, 0x0c, 0x15, 0x1a }, + { 0x02, 0x0e, 0x16, 0xff }, + { 0x02, 0x11, 0xff, 0xff }, + { 0x04, 0xff, 0xff, 0xff } +}; + +static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { + { 0x02, 0x12, 0x16, 0x1a }, + { 0x09, 0x19, 0x1f, 0xff }, + { 0x10, 0x1f, 0xff, 0xff }, + { 0x1f, 0xff, 0xff, 0xff } +}; + +static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { + { 0x00, 0x0c, 0x14, 0x19 }, + { 0x00, 0x0b, 0x12, 0xff }, + { 0x00, 0x0b, 0xff, 0xff }, + { 0x04, 0xff, 0xff, 0xff } +}; + +static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { + { 0x08, 0x0f, 0x16, 0x1f }, + { 0x11, 0x1e, 0x1f, 0xff }, + { 0x19, 0x1f, 0xff, 0xff }, + { 0x1f, 0xff, 0xff, 0xff } +}; + +static int qcom_qmp_phy_combo_configure_dp_swing(struct qmp_phy *qphy, + unsigned int drv_lvl_reg, unsigned int emp_post_reg) +{ + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; + unsigned int v_level = 0, p_level = 0; + u8 voltage_swing_cfg, pre_emphasis_cfg; + int i; + + for (i = 0; i < dp_opts->lanes; i++) { + v_level = max(v_level, dp_opts->voltage[i]); + p_level = max(p_level, dp_opts->pre[i]); + } + + if (dp_opts->link_rate <= 2700) { + voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level]; + pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level]; + } else { + voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level]; + pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level]; + } + + /* TODO: Move check to config check */ + if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) + return -EINVAL; + + /* Enable MUX to use Cursor values from these registers */ + voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; + pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; + + writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg); + writel(pre_emphasis_cfg, qphy->tx + emp_post_reg); + writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg); + writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg); + + return 0; +} + +static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy) +{ + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; + u32 bias_en, drvr_en; + + if (qcom_qmp_phy_combo_configure_dp_swing(qphy, + QSERDES_V3_TX_TX_DRV_LVL, + QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0) + return; + + if (dp_opts->lanes == 1) { + bias_en = 0x3e; + drvr_en = 0x13; + } else { + bias_en = 0x3f; + drvr_en = 0x10; + } + + writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); + writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); + writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); + writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); +} + +static bool qcom_qmp_phy_combo_configure_dp_mode(struct qmp_phy *qphy) +{ + u32 val; + bool reverse = false; + + val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; + + /* + * TODO: Assume orientation is CC1 for now and two lanes, need to + * use type-c connector to understand orientation and lanes. + * + * Otherwise val changes to be like below if this code understood + * the orientation of the type-c cable. + * + * if (lane_cnt == 4 || orientation == ORIENTATION_CC2) + * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; + * if (lane_cnt == 4 || orientation == ORIENTATION_CC1) + * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; + * if (orientation == ORIENTATION_CC2) + * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); + */ + val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; + writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL); + + writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE); + + return reverse; +} + +static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) +{ + const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; + u32 phy_vco_div, status; + unsigned long pixel_freq; + + qcom_qmp_phy_combo_configure_dp_mode(qphy); + + writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); + writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); + + switch (dp_opts->link_rate) { + case 1620: + phy_vco_div = 0x1; + pixel_freq = 1620000000UL / 2; + break; + case 2700: + phy_vco_div = 0x1; + pixel_freq = 2700000000UL / 2; + break; + case 5400: + phy_vco_div = 0x2; + pixel_freq = 5400000000UL / 4; + break; + case 8100: + phy_vco_div = 0x0; + pixel_freq = 8100000000UL / 6; + break; + default: + /* Other link rates aren't supported */ + return -EINVAL; + } + writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV); + + clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); + clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); + + writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); + writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); + writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); + + writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL); + + if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS, + status, + ((status & BIT(0)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); + + if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, + status, + ((status & BIT(1)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); + udelay(2000); + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); + + return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, + status, + ((status & BIT(1)) > 0), + 500, + 10000); +} + +/* + * We need to calibrate the aux setting here as many times + * as the caller tries + */ +static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy) +{ + static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; + u8 val; + + qphy->dp_aux_cfg++; + qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); + val = cfg1_settings[qphy->dp_aux_cfg]; + + writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); + + return 0; +} + +static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy) +{ + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, + qphy->pcs + QSERDES_DP_PHY_PD_CTL); + + /* Turn on BIAS current for PHY/PLL */ + writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); + + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); + writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); + writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); + writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); + writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); + qphy->dp_aux_cfg = 0; + + writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | + PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | + PHY_AUX_REQ_ERR_MASK, + qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); +} + +static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy) +{ + /* Program default values before writing proper values */ + writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); + writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); + + writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); + writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); + + qcom_qmp_phy_combo_configure_dp_swing(qphy, + QSERDES_V4_TX_TX_DRV_LVL, + QSERDES_V4_TX_TX_EMP_POST1_LVL); +} + +static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy) +{ + const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; + u32 phy_vco_div, status; + unsigned long pixel_freq; + u32 bias0_en, drvr0_en, bias1_en, drvr1_en; + bool reverse; + + writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1); + + reverse = qcom_qmp_phy_combo_configure_dp_mode(qphy); + + writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); + writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); + + writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); + writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); + + switch (dp_opts->link_rate) { + case 1620: + phy_vco_div = 0x1; + pixel_freq = 1620000000UL / 2; + break; + case 2700: + phy_vco_div = 0x1; + pixel_freq = 2700000000UL / 2; + break; + case 5400: + phy_vco_div = 0x2; + pixel_freq = 5400000000UL / 4; + break; + case 8100: + phy_vco_div = 0x0; + pixel_freq = 8100000000UL / 6; + break; + default: + /* Other link rates aren't supported */ + return -EINVAL; + } + writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV); + + clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); + clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); + + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); + writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); + writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); + + writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL); + + if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS, + status, + ((status & BIT(0)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, + status, + ((status & BIT(0)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, + status, + ((status & BIT(1)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); + + if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, + status, + ((status & BIT(0)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, + status, + ((status & BIT(1)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + /* + * At least for 7nm DP PHY this has to be done after enabling link + * clock. + */ + + if (dp_opts->lanes == 1) { + bias0_en = reverse ? 0x3e : 0x15; + bias1_en = reverse ? 0x15 : 0x3e; + drvr0_en = reverse ? 0x13 : 0x10; + drvr1_en = reverse ? 0x10 : 0x13; + } else if (dp_opts->lanes == 2) { + bias0_en = reverse ? 0x3f : 0x15; + bias1_en = reverse ? 0x15 : 0x3f; + drvr0_en = 0x10; + drvr1_en = 0x10; + } else { + bias0_en = 0x3f; + bias1_en = 0x3f; + drvr0_en = 0x10; + drvr1_en = 0x10; + } + + writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); + writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); + writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); + writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); + + writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); + udelay(2000); + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); + + if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, + status, + ((status & BIT(1)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV); + writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV); + + writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); + writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); + + writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); + writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); + + return 0; +} + +/* + * We need to calibrate the aux setting here as many times + * as the caller tries + */ +static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy) +{ + static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; + u8 val; + + qphy->dp_aux_cfg++; + qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); + val = cfg1_settings[qphy->dp_aux_cfg]; + + writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); + + return 0; +} + +static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) +{ + const struct phy_configure_opts_dp *dp_opts = &opts->dp; + struct qmp_phy *qphy = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qphy->cfg; + + memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); + if (qphy->dp_opts.set_voltages) { + cfg->configure_dp_tx(qphy); + qphy->dp_opts.set_voltages = 0; + } + + return 0; +} + +static int qcom_qmp_dp_phy_calibrate(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qphy->cfg; + + if (cfg->calibrate_dp_phy) + return cfg->calibrate_dp_phy(qphy); + + return 0; +} + +static int qcom_qmp_phy_combo_com_init(struct qmp_phy *qphy) +{ + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *pcs = qphy->pcs; + void __iomem *dp_com = qmp->dp_com; + int ret; + + mutex_lock(&qmp->phy_mutex); + if (qmp->init_count++) { + mutex_unlock(&qmp->phy_mutex); + return 0; + } + + /* turn on regulator supplies */ + ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); + if (ret) { + dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); + goto err_unlock; + } + + ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); + if (ret) { + dev_err(qmp->dev, "reset assert failed\n"); + goto err_disable_regulators; + } + + ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); + if (ret) { + dev_err(qmp->dev, "reset deassert failed\n"); + goto err_disable_regulators; + } + + ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); + if (ret) + goto err_assert_reset; + + if (cfg->has_phy_dp_com_ctrl) { + qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, + SW_PWRDN); + /* override hardware control for reset of qmp phy */ + qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, + SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | + SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); + + /* Default type-c orientation, i.e CC1 */ + qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); + + qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, + USB3_MODE | DP_MODE); + + /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ + qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, + SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | + SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); + + qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); + qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); + } + + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) + qphy_setbits(pcs, + cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + cfg->pwrdn_ctrl); + else + qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, + cfg->pwrdn_ctrl); + + mutex_unlock(&qmp->phy_mutex); + + return 0; + +err_assert_reset: + reset_control_bulk_assert(cfg->num_resets, qmp->resets); +err_disable_regulators: + regulator_bulk_disable(cfg->num_vregs, qmp->vregs); +err_unlock: + mutex_unlock(&qmp->phy_mutex); + + return ret; +} + +static int qcom_qmp_phy_combo_com_exit(struct qmp_phy *qphy) +{ + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + + mutex_lock(&qmp->phy_mutex); + if (--qmp->init_count) { + mutex_unlock(&qmp->phy_mutex); + return 0; + } + + reset_control_assert(qmp->ufs_reset); + + reset_control_bulk_assert(cfg->num_resets, qmp->resets); + + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); + + regulator_bulk_disable(cfg->num_vregs, qmp->vregs); + + mutex_unlock(&qmp->phy_mutex); + + return 0; +} + +static int qcom_qmp_phy_combo_init(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + int ret; + dev_vdbg(qmp->dev, "Initializing QMP phy\n"); + + ret = qcom_qmp_phy_combo_com_init(qphy); + if (ret) + return ret; + + if (cfg->type == PHY_TYPE_DP) + cfg->dp_aux_init(qphy); + + return 0; +} + +static int qcom_qmp_phy_combo_power_on(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *tx = qphy->tx; + void __iomem *rx = qphy->rx; + void __iomem *pcs = qphy->pcs; + void __iomem *status; + unsigned int mask, val, ready; + int ret; + + qcom_qmp_phy_combo_serdes_init(qphy); + + ret = clk_prepare_enable(qphy->pipe_clk); + if (ret) { + dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); + return ret; + } + + /* Tx, Rx, and PCS configurations */ + qcom_qmp_phy_combo_configure_lane(tx, cfg->regs, + cfg->tx_tbl, cfg->tx_tbl_num, 1); + + /* Configuration for other LANE for USB-DP combo PHY */ + if (cfg->is_dual_lane_phy) { + qcom_qmp_phy_combo_configure_lane(qphy->tx2, cfg->regs, + cfg->tx_tbl, cfg->tx_tbl_num, 2); + } + + /* Configure special DP tx tunings */ + if (cfg->type == PHY_TYPE_DP) + cfg->configure_dp_tx(qphy); + + qcom_qmp_phy_combo_configure_lane(rx, cfg->regs, + cfg->rx_tbl, cfg->rx_tbl_num, 1); + + if (cfg->is_dual_lane_phy) { + qcom_qmp_phy_combo_configure_lane(qphy->rx2, cfg->regs, + cfg->rx_tbl, cfg->rx_tbl_num, 2); + } + + /* Configure link rate, swing, etc. */ + if (cfg->type == PHY_TYPE_DP) { + cfg->configure_dp_phy(qphy); + } else { + qcom_qmp_phy_combo_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); + } + + ret = reset_control_deassert(qmp->ufs_reset); + if (ret) + goto err_disable_pipe_clk; + + if (cfg->has_pwrdn_delay) + usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); + + if (cfg->type != PHY_TYPE_DP) { + /* Pull PHY out of reset state */ + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + /* start SerDes and Phy-Coding-Sublayer */ + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + + status = pcs + cfg->regs[QPHY_PCS_STATUS]; + mask = cfg->phy_status; + ready = 0; + + ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, + PHY_INIT_COMPLETE_TIMEOUT); + if (ret) { + dev_err(qmp->dev, "phy initialization timed-out\n"); + goto err_disable_pipe_clk; + } + } + return 0; + +err_disable_pipe_clk: + clk_disable_unprepare(qphy->pipe_clk); + + return ret; +} + +static int qcom_qmp_phy_combo_power_off(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qphy->cfg; + + clk_disable_unprepare(qphy->pipe_clk); + + if (cfg->type == PHY_TYPE_DP) { + /* Assert DP PHY power down */ + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); + } else { + /* PHY reset */ + qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + + /* stop SerDes and Phy-Coding-Sublayer */ + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + + /* Put PHY into POWER DOWN state: active low */ + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + cfg->pwrdn_ctrl); + } else { + qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, + cfg->pwrdn_ctrl); + } + } + + return 0; +} + +static int qcom_qmp_phy_combo_exit(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + + qcom_qmp_phy_combo_com_exit(qphy); + + return 0; +} + +static int qcom_qmp_phy_combo_enable(struct phy *phy) +{ + int ret; + + ret = qcom_qmp_phy_combo_init(phy); + if (ret) + return ret; + + ret = qcom_qmp_phy_combo_power_on(phy); + if (ret) + qcom_qmp_phy_combo_exit(phy); + + return ret; +} + +static int qcom_qmp_phy_combo_disable(struct phy *phy) +{ + int ret; + + ret = qcom_qmp_phy_combo_power_off(phy); + if (ret) + return ret; + return qcom_qmp_phy_combo_exit(phy); +} + +static int qcom_qmp_phy_combo_set_mode(struct phy *phy, + enum phy_mode mode, int submode) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + + qphy->mode = mode; + + return 0; +} + +static void qcom_qmp_phy_combo_enable_autonomous_mode(struct qmp_phy *qphy) +{ + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs; + void __iomem *pcs_misc = qphy->pcs_misc; + u32 intr_mask; + + if (qphy->mode == PHY_MODE_USB_HOST_SS || + qphy->mode == PHY_MODE_USB_DEVICE_SS) + intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; + else + intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; + + /* Clear any pending interrupts status */ + qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); + /* Writing 1 followed by 0 clears the interrupt */ + qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); + + qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], + ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); + + /* Enable required PHY autonomous mode interrupts */ + qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); + + /* Enable i/o clamp_n for autonomous mode */ + if (pcs_misc) + qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); +} + +static void qcom_qmp_phy_combo_disable_autonomous_mode(struct qmp_phy *qphy) +{ + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs_usb; + void __iomem *pcs_misc = qphy->pcs_misc; + + /* Disable i/o clamp_n on resume for normal mode */ + if (pcs_misc) + qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); + + qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], + ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); + + qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); + /* Writing 1 followed by 0 clears the interrupt */ + qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); +} + +static int __maybe_unused qcom_qmp_phy_combo_runtime_suspend(struct device *dev) +{ + struct qcom_qmp *qmp = dev_get_drvdata(dev); + struct qmp_phy *qphy = qmp->phys[0]; + const struct qmp_phy_cfg *cfg = qphy->cfg; + + dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); + + /* Supported only for USB3 PHY and luckily USB3 is the first phy */ + if (cfg->type != PHY_TYPE_USB3) + return 0; + + if (!qmp->init_count) { + dev_vdbg(dev, "PHY not initialized, bailing out\n"); + return 0; + } + + qcom_qmp_phy_combo_enable_autonomous_mode(qphy); + + clk_disable_unprepare(qphy->pipe_clk); + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); + + return 0; +} + +static int __maybe_unused qcom_qmp_phy_combo_runtime_resume(struct device *dev) +{ + struct qcom_qmp *qmp = dev_get_drvdata(dev); + struct qmp_phy *qphy = qmp->phys[0]; + const struct qmp_phy_cfg *cfg = qphy->cfg; + int ret = 0; + + dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); + + /* Supported only for USB3 PHY and luckily USB3 is the first phy */ + if (cfg->type != PHY_TYPE_USB3) + return 0; + + if (!qmp->init_count) { + dev_vdbg(dev, "PHY not initialized, bailing out\n"); + return 0; + } + + ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); + if (ret) + return ret; + + ret = clk_prepare_enable(qphy->pipe_clk); + if (ret) { + dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); + return ret; + } + + qcom_qmp_phy_combo_disable_autonomous_mode(qphy); + + return 0; +} + +static int qcom_qmp_phy_combo_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) +{ + struct qcom_qmp *qmp = dev_get_drvdata(dev); + int num = cfg->num_vregs; + int ret, i; + + qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); + if (!qmp->vregs) + return -ENOMEM; + + for (i = 0; i < num; i++) + qmp->vregs[i].supply = cfg->vreg_list[i].name; + + ret = devm_regulator_bulk_get(dev, num, qmp->vregs); + if (ret) { + dev_err(dev, "failed at devm_regulator_bulk_get\n"); + return ret; + } + + for (i = 0; i < num; i++) { + ret = regulator_set_load(qmp->vregs[i].consumer, + cfg->vreg_list[i].enable_load); + if (ret) { + dev_err(dev, "failed to set load at %s\n", + qmp->vregs[i].supply); + return ret; + } + } + + return 0; +} + +static int qcom_qmp_phy_combo_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) +{ + struct qcom_qmp *qmp = dev_get_drvdata(dev); + int i; + int ret; + + qmp->resets = devm_kcalloc(dev, cfg->num_resets, + sizeof(*qmp->resets), GFP_KERNEL); + if (!qmp->resets) + return -ENOMEM; + + for (i = 0; i < cfg->num_resets; i++) + qmp->resets[i].id = cfg->reset_list[i]; + + ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); + if (ret) + return dev_err_probe(dev, ret, "failed to get resets\n"); + + return 0; +} + +static int qcom_qmp_phy_combo_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) +{ + struct qcom_qmp *qmp = dev_get_drvdata(dev); + int num = cfg->num_clks; + int i; + + qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); + if (!qmp->clks) + return -ENOMEM; + + for (i = 0; i < num; i++) + qmp->clks[i].id = cfg->clk_list[i]; + + return devm_clk_bulk_get(dev, num, qmp->clks); +} + +static void phy_clk_release_provider(void *res) +{ + of_clk_del_provider(res); +} + +/* + * Register a fixed rate pipe clock. + * + * The _pipe_clksrc generated by PHY goes to the GCC that gate + * controls it. The _pipe_clk coming out of the GCC is requested + * by the PHY driver for its operations. + * We register the _pipe_clksrc here. The gcc driver takes care + * of assigning this _pipe_clksrc as parent to _pipe_clk. + * Below picture shows this relationship. + * + * +---------------+ + * | PHY block |<<---------------------------------------+ + * | | | + * | +-------+ | +-----+ | + * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ + * clk | +-------+ | +-----+ + * +---------------+ + */ +static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) +{ + struct clk_fixed_rate *fixed; + struct clk_init_data init = { }; + int ret; + + ret = of_property_read_string(np, "clock-output-names", &init.name); + if (ret) { + dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); + return ret; + } + + fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); + if (!fixed) + return -ENOMEM; + + init.ops = &clk_fixed_rate_ops; + + /* controllers using QMP phys use 125MHz pipe clock interface */ + fixed->fixed_rate = 125000000; + fixed->hw.init = &init; + + ret = devm_clk_hw_register(qmp->dev, &fixed->hw); + if (ret) + return ret; + + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); + if (ret) + return ret; + + /* + * Roll a devm action because the clock provider is the child node, but + * the child node is not actually a device. + */ + return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); +} + +/* + * Display Port PLL driver block diagram for branch clocks + * + * +------------------------------+ + * | DP_VCO_CLK | + * | | + * | +-------------------+ | + * | | (DP PLL/VCO) | | + * | +---------+---------+ | + * | v | + * | +----------+-----------+ | + * | | hsclk_divsel_clk_src | | + * | +----------+-----------+ | + * +------------------------------+ + * | + * +---------<---------v------------>----------+ + * | | + * +--------v----------------+ | + * | dp_phy_pll_link_clk | | + * | link_clk | | + * +--------+----------------+ | + * | | + * | | + * v v + * Input to DISPCC block | + * for link clk, crypto clk | + * and interface clock | + * | + * | + * +--------<------------+-----------------+---<---+ + * | | | + * +----v---------+ +--------v-----+ +--------v------+ + * | vco_divided | | vco_divided | | vco_divided | + * | _clk_src | | _clk_src | | _clk_src | + * | | | | | | + * |divsel_six | | divsel_two | | divsel_four | + * +-------+------+ +-----+--------+ +--------+------+ + * | | | + * v---->----------v-------------<------v + * | + * +----------+-----------------+ + * | dp_phy_pll_vco_div_clk | + * +---------+------------------+ + * | + * v + * Input to DISPCC block + * for DP pixel clock + * + */ +static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + switch (req->rate) { + case 1620000000UL / 2: + case 2700000000UL / 2: + /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ + return 0; + default: + return -EINVAL; + } +} + +static unsigned long +qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + const struct qmp_phy_dp_clks *dp_clks; + const struct qmp_phy *qphy; + const struct phy_configure_opts_dp *dp_opts; + + dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw); + qphy = dp_clks->qphy; + dp_opts = &qphy->dp_opts; + + switch (dp_opts->link_rate) { + case 1620: + return 1620000000UL / 2; + case 2700: + return 2700000000UL / 2; + case 5400: + return 5400000000UL / 4; + case 8100: + return 8100000000UL / 6; + default: + return 0; + } +} + +static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = { + .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate, + .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate, +}; + +static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + switch (req->rate) { + case 162000000: + case 270000000: + case 540000000: + case 810000000: + return 0; + default: + return -EINVAL; + } +} + +static unsigned long +qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + const struct qmp_phy_dp_clks *dp_clks; + const struct qmp_phy *qphy; + const struct phy_configure_opts_dp *dp_opts; + + dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw); + qphy = dp_clks->qphy; + dp_opts = &qphy->dp_opts; + + switch (dp_opts->link_rate) { + case 1620: + case 2700: + case 5400: + case 8100: + return dp_opts->link_rate * 100000; + default: + return 0; + } +} + +static const struct clk_ops qcom_qmp_dp_link_clk_ops = { + .determine_rate = qcom_qmp_dp_link_clk_determine_rate, + .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate, +}; + +static struct clk_hw * +qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) +{ + struct qmp_phy_dp_clks *dp_clks = data; + unsigned int idx = clkspec->args[0]; + + if (idx >= 2) { + pr_err("%s: invalid index %u\n", __func__, idx); + return ERR_PTR(-EINVAL); + } + + if (idx == 0) + return &dp_clks->dp_link_hw; + + return &dp_clks->dp_pixel_hw; +} + +static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, + struct device_node *np) +{ + struct clk_init_data init = { }; + struct qmp_phy_dp_clks *dp_clks; + char name[64]; + int ret; + + dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL); + if (!dp_clks) + return -ENOMEM; + + dp_clks->qphy = qphy; + qphy->dp_clks = dp_clks; + + snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); + init.ops = &qcom_qmp_dp_link_clk_ops; + init.name = name; + dp_clks->dp_link_hw.init = &init; + ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw); + if (ret) + return ret; + + snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); + init.ops = &qcom_qmp_dp_pixel_clk_ops; + init.name = name; + dp_clks->dp_pixel_hw.init = &init; + ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw); + if (ret) + return ret; + + ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks); + if (ret) + return ret; + + /* + * Roll a devm action because the clock provider is the child node, but + * the child node is not actually a device. + */ + return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); +} + +static const struct phy_ops qcom_qmp_phy_combo_usb_ops = { + .init = qcom_qmp_phy_combo_enable, + .exit = qcom_qmp_phy_combo_disable, + .set_mode = qcom_qmp_phy_combo_set_mode, + .owner = THIS_MODULE, +}; + +static const struct phy_ops qcom_qmp_phy_combo_dp_ops = { + .init = qcom_qmp_phy_combo_init, + .configure = qcom_qmp_dp_phy_configure, + .power_on = qcom_qmp_phy_combo_power_on, + .calibrate = qcom_qmp_dp_phy_calibrate, + .power_off = qcom_qmp_phy_combo_power_off, + .exit = qcom_qmp_phy_combo_exit, + .set_mode = qcom_qmp_phy_combo_set_mode, + .owner = THIS_MODULE, +}; + +static +int qcom_qmp_phy_combo_create(struct device *dev, struct device_node *np, int id, + void __iomem *serdes, const struct qmp_phy_cfg *cfg) +{ + struct qcom_qmp *qmp = dev_get_drvdata(dev); + struct phy *generic_phy; + struct qmp_phy *qphy; + const struct phy_ops *ops; + char prop_name[MAX_PROP_NAME]; + int ret; + + qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); + if (!qphy) + return -ENOMEM; + + qphy->cfg = cfg; + qphy->serdes = serdes; + /* + * Get memory resources for each phy lane: + * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. + * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 + * For single lane PHYs: pcs_misc (optional) -> 3. + */ + qphy->tx = of_iomap(np, 0); + if (!qphy->tx) + return -ENOMEM; + + qphy->rx = of_iomap(np, 1); + if (!qphy->rx) + return -ENOMEM; + + qphy->pcs = of_iomap(np, 2); + if (!qphy->pcs) + return -ENOMEM; + + if (cfg->pcs_usb_offset) + qphy->pcs_usb = qphy->pcs + cfg->pcs_usb_offset; + + /* + * If this is a dual-lane PHY, then there should be registers for the + * second lane. Some old device trees did not specify this, so fall + * back to old legacy behavior of assuming they can be reached at an + * offset from the first lane. + */ + if (cfg->is_dual_lane_phy) { + qphy->tx2 = of_iomap(np, 3); + qphy->rx2 = of_iomap(np, 4); + if (!qphy->tx2 || !qphy->rx2) { + dev_warn(dev, + "Underspecified device tree, falling back to legacy register regions\n"); + + /* In the old version, pcs_misc is at index 3. */ + qphy->pcs_misc = qphy->tx2; + qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; + qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; + + } else { + qphy->pcs_misc = of_iomap(np, 5); + } + + } else { + qphy->pcs_misc = of_iomap(np, 3); + } + + if (!qphy->pcs_misc) + dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); + + /* + * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3 + * based phys, so they essentially have pipe clock. So, + * we return error in case phy is USB3 or PIPE type. + * Otherwise, we initialize pipe clock to NULL for + * all phys that don't need this. + */ + snprintf(prop_name, sizeof(prop_name), "pipe%d", id); + qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); + if (IS_ERR(qphy->pipe_clk)) { + if (cfg->type == PHY_TYPE_USB3) { + ret = PTR_ERR(qphy->pipe_clk); + if (ret != -EPROBE_DEFER) + dev_err(dev, + "failed to get lane%d pipe_clk, %d\n", + id, ret); + return ret; + } + qphy->pipe_clk = NULL; + } + + if (cfg->type == PHY_TYPE_DP) + ops = &qcom_qmp_phy_combo_dp_ops; + else + ops = &qcom_qmp_phy_combo_usb_ops; + + generic_phy = devm_phy_create(dev, np, ops); + if (IS_ERR(generic_phy)) { + ret = PTR_ERR(generic_phy); + dev_err(dev, "failed to create qphy %d\n", ret); + return ret; + } + + qphy->phy = generic_phy; + qphy->index = id; + qphy->qmp = qmp; + qmp->phys[id] = qphy; + phy_set_drvdata(generic_phy, qphy); + + return 0; +} + +static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = { + { + .compatible = "qcom,sc7180-qmp-usb3-dp-phy", + .data = &sc7180_usb3dpphy_cfg, + }, + { + .compatible = "qcom,sm8250-qmp-usb3-dp-phy", + .data = &sm8250_usb3dpphy_cfg, + }, + { + .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", + .data = &sc8180x_usb3dpphy_cfg, + }, + { } +}; +MODULE_DEVICE_TABLE(of, qcom_qmp_combo_phy_of_match_table); + +static const struct dev_pm_ops qcom_qmp_phy_combo_pm_ops = { + SET_RUNTIME_PM_OPS(qcom_qmp_phy_combo_runtime_suspend, + qcom_qmp_phy_combo_runtime_resume, NULL) +}; + +static int qcom_qmp_phy_combo_probe(struct platform_device *pdev) +{ + struct qcom_qmp *qmp; + struct device *dev = &pdev->dev; + struct device_node *child; + struct phy_provider *phy_provider; + void __iomem *serdes; + void __iomem *usb_serdes; + void __iomem *dp_serdes = NULL; + const struct qmp_phy_combo_cfg *combo_cfg = NULL; + const struct qmp_phy_cfg *cfg = NULL; + const struct qmp_phy_cfg *usb_cfg = NULL; + const struct qmp_phy_cfg *dp_cfg = NULL; + int num, id, expected_phys; + int ret; + + qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); + if (!qmp) + return -ENOMEM; + + qmp->dev = dev; + dev_set_drvdata(dev, qmp); + + /* Get the specific init parameters of QMP phy */ + combo_cfg = of_device_get_match_data(dev); + if (!combo_cfg) + return -EINVAL; + + usb_cfg = combo_cfg->usb_cfg; + cfg = usb_cfg; /* Setup clks and regulators */ + + /* per PHY serdes; usually located at base address */ + usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(serdes)) + return PTR_ERR(serdes); + + /* per PHY dp_com; if PHY has dp_com control block */ + if (cfg->has_phy_dp_com_ctrl) { + qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(qmp->dp_com)) + return PTR_ERR(qmp->dp_com); + } + + /* Only two serdes for combo PHY */ + dp_serdes = devm_platform_ioremap_resource(pdev, 2); + if (IS_ERR(dp_serdes)) + return PTR_ERR(dp_serdes); + + dp_cfg = combo_cfg->dp_cfg; + expected_phys = 2; + + mutex_init(&qmp->phy_mutex); + + ret = qcom_qmp_phy_combo_clk_init(dev, cfg); + if (ret) + return ret; + + ret = qcom_qmp_phy_combo_reset_init(dev, cfg); + if (ret) + return ret; + + ret = qcom_qmp_phy_combo_vreg_init(dev, cfg); + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(dev, "failed to get regulator supplies: %d\n", + ret); + return ret; + } + + num = of_get_available_child_count(dev->of_node); + /* do we have a rogue child node ? */ + if (num > expected_phys) + return -EINVAL; + + qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); + if (!qmp->phys) + return -ENOMEM; + + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + /* + * Prevent runtime pm from being ON by default. Users can enable + * it using power/control in sysfs. + */ + pm_runtime_forbid(dev); + + id = 0; + for_each_available_child_of_node(dev->of_node, child) { + if (of_node_name_eq(child, "dp-phy")) { + cfg = dp_cfg; + serdes = dp_serdes; + + /* Create per-lane phy */ + ret = qcom_qmp_phy_combo_create(dev, child, id, serdes, cfg); + if (ret) { + dev_err(dev, "failed to create lane%d phy, %d\n", + id, ret); + goto err_node_put; + } + + ret = phy_dp_clks_register(qmp, qmp->phys[id], child); + if (ret) { + dev_err(qmp->dev, + "failed to register DP clock source\n"); + goto err_node_put; + } + } else if (of_node_name_eq(child, "usb3-phy")) { + cfg = usb_cfg; + serdes = usb_serdes; + + /* Create per-lane phy */ + ret = qcom_qmp_phy_combo_create(dev, child, id, serdes, cfg); + if (ret) { + dev_err(dev, "failed to create lane%d phy, %d\n", + id, ret); + goto err_node_put; + } + + /* + * Register the pipe clock provided by phy. + * See function description to see details of this pipe clock. + */ + ret = phy_pipe_clk_register(qmp, child); + if (ret) { + dev_err(qmp->dev, + "failed to register pipe clock source\n"); + goto err_node_put; + } + } + + id++; + } + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (!IS_ERR(phy_provider)) + dev_info(dev, "Registered Qcom-QMP phy\n"); + else + pm_runtime_disable(dev); + + return PTR_ERR_OR_ZERO(phy_provider); + +err_node_put: + pm_runtime_disable(dev); + of_node_put(child); + return ret; +} + +static struct platform_driver qcom_qmp_phy_combo_driver = { + .probe = qcom_qmp_phy_combo_probe, + .driver = { + .name = "qcom-qmp-combo-phy", + .pm = &qcom_qmp_phy_combo_pm_ops, + .of_match_table = qcom_qmp_combo_phy_of_match_table, + }, +}; + +module_platform_driver(qcom_qmp_phy_combo_driver); + +MODULE_AUTHOR("Vivek Gautam "); +MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c new file mode 100644 index 000000000000..be6a94439b6c --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -0,0 +1,1054 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "phy-qcom-qmp.h" + +/* QPHY_SW_RESET bit */ +#define SW_RESET BIT(0) +/* QPHY_POWER_DOWN_CONTROL */ +#define SW_PWRDN BIT(0) +#define REFCLK_DRV_DSBL BIT(1) +/* QPHY_START_CONTROL bits */ +#define SERDES_START BIT(0) +#define PCS_START BIT(1) +#define PLL_READY_GATE_EN BIT(3) +/* QPHY_PCS_STATUS bit */ +#define PHYSTATUS BIT(6) +#define PHYSTATUS_4_20 BIT(7) +/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ +#define PCS_READY BIT(0) + +/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ +/* DP PHY soft reset */ +#define SW_DPPHY_RESET BIT(0) +/* mux to select DP PHY reset control, 0:HW control, 1: software reset */ +#define SW_DPPHY_RESET_MUX BIT(1) +/* USB3 PHY soft reset */ +#define SW_USB3PHY_RESET BIT(2) +/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ +#define SW_USB3PHY_RESET_MUX BIT(3) + +/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ +#define USB3_MODE BIT(0) /* enables USB3 mode */ +#define DP_MODE BIT(1) /* enables DP mode */ + +/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ +#define ARCVR_DTCT_EN BIT(0) +#define ALFPS_DTCT_EN BIT(1) +#define ARCVR_DTCT_EVENT_SEL BIT(4) + +/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ +#define IRQ_CLEAR BIT(0) + +/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ +#define RCVR_DETECT BIT(0) + +/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ +#define CLAMP_EN BIT(0) /* enables i/o clamp_n */ + +#define PHY_INIT_COMPLETE_TIMEOUT 10000 +#define POWER_DOWN_DELAY_US_MIN 10 +#define POWER_DOWN_DELAY_US_MAX 11 + +#define MAX_PROP_NAME 32 + +/* Define the assumed distance between lanes for underspecified device trees. */ +#define QMP_PHY_LEGACY_LANE_STRIDE 0x400 + +struct qmp_phy_init_tbl { + unsigned int offset; + unsigned int val; + /* + * register part of layout ? + * if yes, then offset gives index in the reg-layout + */ + bool in_layout; + /* + * mask of lanes for which this register is written + * for cases when second lane needs different values + */ + u8 lane_mask; +}; + +#define QMP_PHY_INIT_CFG(o, v) \ + { \ + .offset = o, \ + .val = v, \ + .lane_mask = 0xff, \ + } + +#define QMP_PHY_INIT_CFG_L(o, v) \ + { \ + .offset = o, \ + .val = v, \ + .in_layout = true, \ + .lane_mask = 0xff, \ + } + +#define QMP_PHY_INIT_CFG_LANE(o, v, l) \ + { \ + .offset = o, \ + .val = v, \ + .lane_mask = l, \ + } + +/* set of registers with offsets different per-PHY */ +enum qphy_reg_layout { + /* Common block control registers */ + QPHY_COM_SW_RESET, + QPHY_COM_POWER_DOWN_CONTROL, + QPHY_COM_START_CONTROL, + QPHY_COM_PCS_READY_STATUS, + /* PCS registers */ + QPHY_SW_RESET, + QPHY_START_CTRL, + QPHY_PCS_READY_STATUS, + QPHY_PCS_STATUS, + QPHY_PCS_AUTONOMOUS_MODE_CTRL, + QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, + QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, + QPHY_PCS_POWER_DOWN_CONTROL, + /* PCS_MISC registers */ + QPHY_PCS_MISC_TYPEC_CTRL, + /* Keep last to ensure regs_layout arrays are properly initialized */ + QPHY_LAYOUT_SIZE +}; + +static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_COM_SW_RESET] = 0x400, + [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, + [QPHY_COM_START_CONTROL] = 0x408, + [QPHY_COM_PCS_READY_STATUS] = 0x448, + [QPHY_SW_RESET] = 0x00, + [QPHY_START_CTRL] = 0x08, + [QPHY_PCS_STATUS] = 0x174, +}; + +static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), + QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40), +}; + +static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), +}; + +static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19), +}; + +static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL, 0x4c), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), + + QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x05), + + QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x05), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_DOWN_CONTROL, 0x02), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG4, 0x00), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG1, 0xa3), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), +}; + +struct qmp_phy; + +/* struct qmp_phy_cfg - per-PHY initialization config */ +struct qmp_phy_cfg { + /* phy-type - PCIE/UFS/USB */ + unsigned int type; + /* number of lanes provided by phy */ + int nlanes; + + /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_init_tbl *serdes_tbl; + int serdes_tbl_num; + const struct qmp_phy_init_tbl *serdes_tbl_sec; + int serdes_tbl_num_sec; + const struct qmp_phy_init_tbl *tx_tbl; + int tx_tbl_num; + const struct qmp_phy_init_tbl *tx_tbl_sec; + int tx_tbl_num_sec; + const struct qmp_phy_init_tbl *rx_tbl; + int rx_tbl_num; + const struct qmp_phy_init_tbl *rx_tbl_sec; + int rx_tbl_num_sec; + const struct qmp_phy_init_tbl *pcs_tbl; + int pcs_tbl_num; + const struct qmp_phy_init_tbl *pcs_tbl_sec; + int pcs_tbl_num_sec; + const struct qmp_phy_init_tbl *pcs_misc_tbl; + int pcs_misc_tbl_num; + const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; + int pcs_misc_tbl_num_sec; + + /* clock ids to be requested */ + const char * const *clk_list; + int num_clks; + /* resets to be requested */ + const char * const *reset_list; + int num_resets; + /* regulators to be requested */ + const char * const *vreg_list; + int num_vregs; + + /* array of registers with different offsets */ + const unsigned int *regs; + + unsigned int start_ctrl; + unsigned int pwrdn_ctrl; + unsigned int mask_com_pcs_ready; + /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ + unsigned int phy_status; + + /* true, if PHY needs delay after POWER_DOWN */ + bool has_pwrdn_delay; + /* power_down delay in usec */ + int pwrdn_delay_min; + int pwrdn_delay_max; +}; + +/** + * struct qmp_phy - per-lane phy descriptor + * + * @phy: generic phy + * @cfg: phy specific configuration + * @serdes: iomapped memory space for phy's serdes (i.e. PLL) + * @tx: iomapped memory space for lane's tx + * @rx: iomapped memory space for lane's rx + * @pcs: iomapped memory space for lane's pcs + * @pcs_misc: iomapped memory space for lane's pcs_misc + * @pipe_clk: pipe clock + * @index: lane index + * @qmp: QMP phy to which this lane belongs + * @lane_rst: lane's reset controller + * @mode: current PHY mode + */ +struct qmp_phy { + struct phy *phy; + const struct qmp_phy_cfg *cfg; + void __iomem *serdes; + void __iomem *tx; + void __iomem *rx; + void __iomem *pcs; + void __iomem *pcs_misc; + struct clk *pipe_clk; + unsigned int index; + struct qcom_qmp *qmp; + struct reset_control *lane_rst; + enum phy_mode mode; +}; + +/** + * struct qcom_qmp - structure holding QMP phy block attributes + * + * @dev: device + * + * @clks: array of clocks required by phy + * @resets: array of resets required by phy + * @vregs: regulator supplies bulk data + * + * @phys: array of per-lane phy descriptors + * @phy_mutex: mutex lock for PHY common block initialization + * @init_count: phy common block initialization count + */ +struct qcom_qmp { + struct device *dev; + + struct clk_bulk_data *clks; + struct reset_control_bulk_data *resets; + struct regulator_bulk_data *vregs; + + struct qmp_phy **phys; + + struct mutex phy_mutex; + int init_count; +}; + +static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) +{ + u32 reg; + + reg = readl(base + offset); + reg |= val; + writel(reg, base + offset); + + /* ensure that above write is through */ + readl(base + offset); +} + +static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) +{ + u32 reg; + + reg = readl(base + offset); + reg &= ~val; + writel(reg, base + offset); + + /* ensure that above write is through */ + readl(base + offset); +} + +/* list of clocks required by phy */ +static const char * const msm8996_phy_clk_l[] = { + "aux", "cfg_ahb", "ref", +}; + +/* list of resets */ +static const char * const msm8996_pciephy_reset_l[] = { + "phy", "common", "cfg", +}; + +/* list of regulators */ +static const char * const qmp_phy_vreg_l[] = { + "vdda-phy", "vdda-pll", +}; + +static const struct qmp_phy_cfg msm8996_pciephy_cfg = { + .type = PHY_TYPE_PCIE, + .nlanes = 3, + + .serdes_tbl = msm8996_pcie_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl), + .tx_tbl = msm8996_pcie_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl), + .rx_tbl = msm8996_pcie_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl), + .pcs_tbl = msm8996_pcie_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl), + .clk_list = msm8996_phy_clk_l, + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), + .reset_list = msm8996_pciephy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = pciephy_regs_layout, + + .start_ctrl = PCS_START | PLL_READY_GATE_EN, + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .mask_com_pcs_ready = PCS_READY, + .phy_status = PHYSTATUS, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, +}; + +static void qcom_qmp_phy_pcie_msm8996_configure_lane(void __iomem *base, + const unsigned int *regs, + const struct qmp_phy_init_tbl tbl[], + int num, + u8 lane_mask) +{ + int i; + const struct qmp_phy_init_tbl *t = tbl; + + if (!t) + return; + + for (i = 0; i < num; i++, t++) { + if (!(t->lane_mask & lane_mask)) + continue; + + if (t->in_layout) + writel(t->val, base + regs[t->offset]); + else + writel(t->val, base + t->offset); + } +} + +static void qcom_qmp_phy_pcie_msm8996_configure(void __iomem *base, + const unsigned int *regs, + const struct qmp_phy_init_tbl tbl[], + int num) +{ + qcom_qmp_phy_pcie_msm8996_configure_lane(base, regs, tbl, num, 0xff); +} + +static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy) +{ + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *serdes = qphy->serdes; + const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; + int serdes_tbl_num = cfg->serdes_tbl_num; + void __iomem *status; + unsigned int mask, val; + int ret; + + qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); + if (cfg->serdes_tbl_sec) + qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, + cfg->serdes_tbl_num_sec); + + + qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); + qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], + SERDES_START | PCS_START); + + status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; + mask = cfg->mask_com_pcs_ready; + + ret = readl_poll_timeout(status, val, (val & mask), 10, + PHY_INIT_COMPLETE_TIMEOUT); + if (ret) { + dev_err(qmp->dev, + "phy common block init timed-out\n"); + return ret; + } + + return 0; +} + +static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy) +{ + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *serdes = qphy->serdes; + int ret; + + mutex_lock(&qmp->phy_mutex); + if (qmp->init_count++) { + mutex_unlock(&qmp->phy_mutex); + return 0; + } + + /* turn on regulator supplies */ + ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); + if (ret) { + dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); + goto err_unlock; + } + + ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); + if (ret) { + dev_err(qmp->dev, "reset assert failed\n"); + goto err_disable_regulators; + } + + ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); + if (ret) { + dev_err(qmp->dev, "reset deassert failed\n"); + goto err_disable_regulators; + } + + ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); + if (ret) + goto err_assert_reset; + + qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], + SW_PWRDN); + + mutex_unlock(&qmp->phy_mutex); + + return 0; + +err_assert_reset: + reset_control_bulk_assert(cfg->num_resets, qmp->resets); +err_disable_regulators: + regulator_bulk_disable(cfg->num_vregs, qmp->vregs); +err_unlock: + mutex_unlock(&qmp->phy_mutex); + + return ret; +} + +static int qcom_qmp_phy_pcie_msm8996_com_exit(struct qmp_phy *qphy) +{ + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *serdes = qphy->serdes; + + mutex_lock(&qmp->phy_mutex); + if (--qmp->init_count) { + mutex_unlock(&qmp->phy_mutex); + return 0; + } + + qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], + SERDES_START | PCS_START); + qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], + SW_RESET); + qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], + SW_PWRDN); + + reset_control_bulk_assert(cfg->num_resets, qmp->resets); + + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); + + regulator_bulk_disable(cfg->num_vregs, qmp->vregs); + + mutex_unlock(&qmp->phy_mutex); + + return 0; +} + +static int qcom_qmp_phy_pcie_msm8996_init(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + struct qcom_qmp *qmp = qphy->qmp; + int ret; + dev_vdbg(qmp->dev, "Initializing QMP phy\n"); + + ret = qcom_qmp_phy_pcie_msm8996_com_init(qphy); + if (ret) + return ret; + + return 0; +} + +static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *tx = qphy->tx; + void __iomem *rx = qphy->rx; + void __iomem *pcs = qphy->pcs; + void __iomem *pcs_misc = qphy->pcs_misc; + void __iomem *status; + unsigned int mask, val, ready; + int ret; + + qcom_qmp_phy_pcie_msm8996_serdes_init(qphy); + + ret = reset_control_deassert(qphy->lane_rst); + if (ret) { + dev_err(qmp->dev, "lane%d reset deassert failed\n", + qphy->index); + return ret; + } + + ret = clk_prepare_enable(qphy->pipe_clk); + if (ret) { + dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); + goto err_reset_lane; + } + + /* Tx, Rx, and PCS configurations */ + qcom_qmp_phy_pcie_msm8996_configure_lane(tx, cfg->regs, + cfg->tx_tbl, cfg->tx_tbl_num, 1); + if (cfg->tx_tbl_sec) + qcom_qmp_phy_pcie_msm8996_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, + cfg->tx_tbl_num_sec, 1); + + qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs, + cfg->rx_tbl, cfg->rx_tbl_num, 1); + if (cfg->rx_tbl_sec) + qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs, + cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); + + qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); + if (cfg->pcs_tbl_sec) + qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, + cfg->pcs_tbl_num_sec); + + qcom_qmp_phy_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, + cfg->pcs_misc_tbl_num); + if (cfg->pcs_misc_tbl_sec) + qcom_qmp_phy_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, + cfg->pcs_misc_tbl_num_sec); + + /* + * Pull out PHY from POWER DOWN state. + * This is active low enable signal to power-down PHY. + */ + qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); + + if (cfg->has_pwrdn_delay) + usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); + + /* Pull PHY out of reset state */ + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + + /* start SerDes and Phy-Coding-Sublayer */ + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + + status = pcs + cfg->regs[QPHY_PCS_STATUS]; + mask = cfg->phy_status; + ready = 0; + + ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, + PHY_INIT_COMPLETE_TIMEOUT); + if (ret) { + dev_err(qmp->dev, "phy initialization timed-out\n"); + goto err_disable_pipe_clk; + } + + return 0; + +err_disable_pipe_clk: + clk_disable_unprepare(qphy->pipe_clk); +err_reset_lane: + reset_control_assert(qphy->lane_rst); + + return ret; +} + +static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qphy->cfg; + + clk_disable_unprepare(qphy->pipe_clk); + + /* PHY reset */ + qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + + /* stop SerDes and Phy-Coding-Sublayer */ + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + + /* Put PHY into POWER DOWN state: active low */ + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + cfg->pwrdn_ctrl); + } else { + qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, + cfg->pwrdn_ctrl); + } + + return 0; +} + +static int qcom_qmp_phy_pcie_msm8996_exit(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + + reset_control_assert(qphy->lane_rst); + + qcom_qmp_phy_pcie_msm8996_com_exit(qphy); + + return 0; +} + +static int qcom_qmp_phy_pcie_msm8996_enable(struct phy *phy) +{ + int ret; + + ret = qcom_qmp_phy_pcie_msm8996_init(phy); + if (ret) + return ret; + + ret = qcom_qmp_phy_pcie_msm8996_power_on(phy); + if (ret) + qcom_qmp_phy_pcie_msm8996_exit(phy); + + return ret; +} + +static int qcom_qmp_phy_pcie_msm8996_disable(struct phy *phy) +{ + int ret; + + ret = qcom_qmp_phy_pcie_msm8996_power_off(phy); + if (ret) + return ret; + return qcom_qmp_phy_pcie_msm8996_exit(phy); +} + +static int qcom_qmp_phy_pcie_msm8996_set_mode(struct phy *phy, + enum phy_mode mode, int submode) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + + qphy->mode = mode; + + return 0; +} + +static int qcom_qmp_phy_pcie_msm8996_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) +{ + struct qcom_qmp *qmp = dev_get_drvdata(dev); + int num = cfg->num_vregs; + int i; + + qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); + if (!qmp->vregs) + return -ENOMEM; + + for (i = 0; i < num; i++) + qmp->vregs[i].supply = cfg->vreg_list[i]; + + return devm_regulator_bulk_get(dev, num, qmp->vregs); +} + +static int qcom_qmp_phy_pcie_msm8996_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) +{ + struct qcom_qmp *qmp = dev_get_drvdata(dev); + int i; + int ret; + + qmp->resets = devm_kcalloc(dev, cfg->num_resets, + sizeof(*qmp->resets), GFP_KERNEL); + if (!qmp->resets) + return -ENOMEM; + + for (i = 0; i < cfg->num_resets; i++) + qmp->resets[i].id = cfg->reset_list[i]; + + ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); + if (ret) + return dev_err_probe(dev, ret, "failed to get resets\n"); + + return 0; +} + +static int qcom_qmp_phy_pcie_msm8996_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) +{ + struct qcom_qmp *qmp = dev_get_drvdata(dev); + int num = cfg->num_clks; + int i; + + qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); + if (!qmp->clks) + return -ENOMEM; + + for (i = 0; i < num; i++) + qmp->clks[i].id = cfg->clk_list[i]; + + return devm_clk_bulk_get(dev, num, qmp->clks); +} + +static void phy_clk_release_provider(void *res) +{ + of_clk_del_provider(res); +} + +/* + * Register a fixed rate pipe clock. + * + * The _pipe_clksrc generated by PHY goes to the GCC that gate + * controls it. The _pipe_clk coming out of the GCC is requested + * by the PHY driver for its operations. + * We register the _pipe_clksrc here. The gcc driver takes care + * of assigning this _pipe_clksrc as parent to _pipe_clk. + * Below picture shows this relationship. + * + * +---------------+ + * | PHY block |<<---------------------------------------+ + * | | | + * | +-------+ | +-----+ | + * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ + * clk | +-------+ | +-----+ + * +---------------+ + */ +static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) +{ + struct clk_fixed_rate *fixed; + struct clk_init_data init = { }; + int ret; + + ret = of_property_read_string(np, "clock-output-names", &init.name); + if (ret) { + dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); + return ret; + } + + fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); + if (!fixed) + return -ENOMEM; + + init.ops = &clk_fixed_rate_ops; + + /* controllers using QMP phys use 125MHz pipe clock interface */ + fixed->fixed_rate = 125000000; + fixed->hw.init = &init; + + ret = devm_clk_hw_register(qmp->dev, &fixed->hw); + if (ret) + return ret; + + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); + if (ret) + return ret; + + /* + * Roll a devm action because the clock provider is the child node, but + * the child node is not actually a device. + */ + return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); +} + +static const struct phy_ops qcom_qmp_phy_pcie_msm8996_ops = { + .power_on = qcom_qmp_phy_pcie_msm8996_enable, + .power_off = qcom_qmp_phy_pcie_msm8996_disable, + .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode, + .owner = THIS_MODULE, +}; + +static void qcom_qmp_reset_control_put(void *data) +{ + reset_control_put(data); +} + +static +int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np, int id, + void __iomem *serdes, const struct qmp_phy_cfg *cfg) +{ + struct qcom_qmp *qmp = dev_get_drvdata(dev); + struct phy *generic_phy; + struct qmp_phy *qphy; + char prop_name[MAX_PROP_NAME]; + int ret; + + qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); + if (!qphy) + return -ENOMEM; + + qphy->cfg = cfg; + qphy->serdes = serdes; + /* + * Get memory resources for each phy lane: + * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. + * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 + * For single lane PHYs: pcs_misc (optional) -> 3. + */ + qphy->tx = of_iomap(np, 0); + if (!qphy->tx) + return -ENOMEM; + + qphy->rx = of_iomap(np, 1); + if (!qphy->rx) + return -ENOMEM; + + qphy->pcs = of_iomap(np, 2); + if (!qphy->pcs) + return -ENOMEM; + + qphy->pcs_misc = of_iomap(np, 3); + + if (!qphy->pcs_misc) + dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); + + snprintf(prop_name, sizeof(prop_name), "pipe%d", id); + qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); + if (IS_ERR(qphy->pipe_clk)) { + return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), + "failed to get lane%d pipe clock\n", id); + } + + /* Get lane reset, if any */ + snprintf(prop_name, sizeof(prop_name), "lane%d", id); + qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name); + if (IS_ERR(qphy->lane_rst)) { + dev_err(dev, "failed to get lane%d reset\n", id); + return PTR_ERR(qphy->lane_rst); + } + ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put, + qphy->lane_rst); + if (ret) + return ret; + + generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_msm8996_ops); + if (IS_ERR(generic_phy)) { + ret = PTR_ERR(generic_phy); + dev_err(dev, "failed to create qphy %d\n", ret); + return ret; + } + + qphy->phy = generic_phy; + qphy->index = id; + qphy->qmp = qmp; + qmp->phys[id] = qphy; + phy_set_drvdata(generic_phy, qphy); + + return 0; +} + +static const struct of_device_id qcom_qmp_phy_pcie_msm8996_of_match_table[] = { + { + .compatible = "qcom,msm8996-qmp-pcie-phy", + .data = &msm8996_pciephy_cfg, + }, + { }, +}; +MODULE_DEVICE_TABLE(of, qcom_qmp_phy_pcie_msm8996_of_match_table); + +static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev) +{ + struct qcom_qmp *qmp; + struct device *dev = &pdev->dev; + struct device_node *child; + struct phy_provider *phy_provider; + void __iomem *serdes; + const struct qmp_phy_cfg *cfg = NULL; + int num, id, expected_phys; + int ret; + + qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); + if (!qmp) + return -ENOMEM; + + qmp->dev = dev; + dev_set_drvdata(dev, qmp); + + /* Get the specific init parameters of QMP phy */ + cfg = of_device_get_match_data(dev); + if (!cfg) + return -EINVAL; + + /* per PHY serdes; usually located at base address */ + serdes = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(serdes)) + return PTR_ERR(serdes); + + expected_phys = cfg->nlanes; + + mutex_init(&qmp->phy_mutex); + + ret = qcom_qmp_phy_pcie_msm8996_clk_init(dev, cfg); + if (ret) + return ret; + + ret = qcom_qmp_phy_pcie_msm8996_reset_init(dev, cfg); + if (ret) + return ret; + + ret = qcom_qmp_phy_pcie_msm8996_vreg_init(dev, cfg); + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(dev, "failed to get regulator supplies: %d\n", + ret); + return ret; + } + + num = of_get_available_child_count(dev->of_node); + /* do we have a rogue child node ? */ + if (num > expected_phys) + return -EINVAL; + + qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); + if (!qmp->phys) + return -ENOMEM; + + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + /* + * Prevent runtime pm from being ON by default. Users can enable + * it using power/control in sysfs. + */ + pm_runtime_forbid(dev); + + id = 0; + for_each_available_child_of_node(dev->of_node, child) { + /* Create per-lane phy */ + ret = qcom_qmp_phy_pcie_msm8996_create(dev, child, id, serdes, cfg); + if (ret) { + dev_err(dev, "failed to create lane%d phy, %d\n", + id, ret); + goto err_node_put; + } + + /* + * Register the pipe clock provided by phy. + * See function description to see details of this pipe clock. + */ + ret = phy_pipe_clk_register(qmp, child); + if (ret) { + dev_err(qmp->dev, + "failed to register pipe clock source\n"); + goto err_node_put; + } + + id++; + } + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (!IS_ERR(phy_provider)) + dev_info(dev, "Registered Qcom-QMP phy\n"); + else + pm_runtime_disable(dev); + + return PTR_ERR_OR_ZERO(phy_provider); + +err_node_put: + pm_runtime_disable(dev); + of_node_put(child); + return ret; +} + +static struct platform_driver qcom_qmp_phy_pcie_msm8996_driver = { + .probe = qcom_qmp_phy_pcie_msm8996_probe, + .driver = { + .name = "qcom-qmp-msm8996-pcie-phy", + .of_match_table = qcom_qmp_phy_pcie_msm8996_of_match_table, + }, +}; + +module_platform_driver(qcom_qmp_phy_pcie_msm8996_driver); + +MODULE_AUTHOR("Vivek Gautam "); +MODULE_DESCRIPTION("Qualcomm QMP MSM8996 PCIe PHY driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-qhp.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-qhp.h new file mode 100644 index 000000000000..e4a4d2cd85eb --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-qhp.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCIE_QHP_H_ +#define QCOM_PHY_QMP_PCIE_QHP_H_ + +/* PCIE GEN3 COM registers */ +#define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 +#define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 +#define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 +#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 +#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c +#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 +#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 +#define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 +#define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 +#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c +#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70 +#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78 +#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c +#define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98 +#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4 +#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8 +#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0 +#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4 +#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc +#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0 +#define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc +#define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0 +#define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8 +#define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100 +#define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108 +#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c +#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120 +#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124 +#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128 +#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c +#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130 +#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150 +#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158 +#define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178 +#define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8 +#define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc +#define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0 +#define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0 +#define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8 +#define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0 +#define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc +#define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c +#define PCIE_GEN3_QHP_COM_CMN_MODE 0x224 +#define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228 +#define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c + +/* PCIE GEN3 QHP Lane registers */ +#define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc +#define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10 +#define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14 +#define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18 +#define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60 +#define PCIE_GEN3_QHP_L0_LANE_MODE 0x64 +#define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c +#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0 +#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4 +#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8 +#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0 +#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4 +#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8 +#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc +#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0 +#define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc +#define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100 +#define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108 +#define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114 +#define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118 +#define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c +#define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120 +#define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124 +#define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128 +#define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130 +#define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134 +#define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138 +#define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c +#define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154 +#define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160 +#define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168 +#define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c +#define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178 +#define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180 +#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184 +#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188 +#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c +#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190 +#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194 +#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198 +#define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c +#define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4 +#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0 +#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4 +#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8 +#define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230 +#define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234 +#define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238 +#define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4 +#define PCIE_GEN3_QHP_L0_RSM_START 0x2a8 +#define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac +#define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0 +#define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8 +#define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0 +#define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4 +#define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc + +/* PCIE GEN3 PCS registers */ +#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c +#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40 +#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54 +#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68 +#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c +#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c +#define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c new file mode 100644 index 000000000000..2d65e1f56bfc --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -0,0 +1,2556 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "phy-qcom-qmp.h" + +/* QPHY_SW_RESET bit */ +#define SW_RESET BIT(0) +/* QPHY_POWER_DOWN_CONTROL */ +#define SW_PWRDN BIT(0) +#define REFCLK_DRV_DSBL BIT(1) +/* QPHY_START_CONTROL bits */ +#define SERDES_START BIT(0) +#define PCS_START BIT(1) +#define PLL_READY_GATE_EN BIT(3) +/* QPHY_PCS_STATUS bit */ +#define PHYSTATUS BIT(6) +#define PHYSTATUS_4_20 BIT(7) +/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ +#define PCS_READY BIT(0) + +/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ +/* DP PHY soft reset */ +#define SW_DPPHY_RESET BIT(0) +/* mux to select DP PHY reset control, 0:HW control, 1: software reset */ +#define SW_DPPHY_RESET_MUX BIT(1) +/* USB3 PHY soft reset */ +#define SW_USB3PHY_RESET BIT(2) +/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ +#define SW_USB3PHY_RESET_MUX BIT(3) + +/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ +#define USB3_MODE BIT(0) /* enables USB3 mode */ +#define DP_MODE BIT(1) /* enables DP mode */ + +/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ +#define ARCVR_DTCT_EN BIT(0) +#define ALFPS_DTCT_EN BIT(1) +#define ARCVR_DTCT_EVENT_SEL BIT(4) + +/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ +#define IRQ_CLEAR BIT(0) + +/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ +#define RCVR_DETECT BIT(0) + +/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ +#define CLAMP_EN BIT(0) /* enables i/o clamp_n */ + +#define PHY_INIT_COMPLETE_TIMEOUT 10000 +#define POWER_DOWN_DELAY_US_MIN 10 +#define POWER_DOWN_DELAY_US_MAX 11 + +#define MAX_PROP_NAME 32 + +/* Define the assumed distance between lanes for underspecified device trees. */ +#define QMP_PHY_LEGACY_LANE_STRIDE 0x400 + +struct qmp_phy_init_tbl { + unsigned int offset; + unsigned int val; + /* + * register part of layout ? + * if yes, then offset gives index in the reg-layout + */ + bool in_layout; + /* + * mask of lanes for which this register is written + * for cases when second lane needs different values + */ + u8 lane_mask; +}; + +#define QMP_PHY_INIT_CFG(o, v) \ + { \ + .offset = o, \ + .val = v, \ + .lane_mask = 0xff, \ + } + +#define QMP_PHY_INIT_CFG_L(o, v) \ + { \ + .offset = o, \ + .val = v, \ + .in_layout = true, \ + .lane_mask = 0xff, \ + } + +#define QMP_PHY_INIT_CFG_LANE(o, v, l) \ + { \ + .offset = o, \ + .val = v, \ + .lane_mask = l, \ + } + +/* set of registers with offsets different per-PHY */ +enum qphy_reg_layout { + /* Common block control registers */ + QPHY_COM_SW_RESET, + QPHY_COM_POWER_DOWN_CONTROL, + QPHY_COM_START_CONTROL, + QPHY_COM_PCS_READY_STATUS, + /* PCS registers */ + QPHY_SW_RESET, + QPHY_START_CTRL, + QPHY_PCS_READY_STATUS, + QPHY_PCS_STATUS, + QPHY_PCS_AUTONOMOUS_MODE_CTRL, + QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, + QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, + QPHY_PCS_POWER_DOWN_CONTROL, + /* PCS_MISC registers */ + QPHY_PCS_MISC_TYPEC_CTRL, + /* Keep last to ensure regs_layout arrays are properly initialized */ + QPHY_LAYOUT_SIZE +}; + +static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = 0x00, + [QPHY_START_CTRL] = 0x44, + [QPHY_PCS_STATUS] = 0x14, + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, +}; + +static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_COM_SW_RESET] = 0x400, + [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, + [QPHY_COM_START_CONTROL] = 0x408, + [QPHY_COM_PCS_READY_STATUS] = 0x448, + [QPHY_SW_RESET] = 0x00, + [QPHY_START_CTRL] = 0x08, + [QPHY_PCS_STATUS] = 0x174, +}; + +static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = 0x00, + [QPHY_START_CTRL] = 0x08, + [QPHY_PCS_STATUS] = 0x174, +}; + +static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = 0x00, + [QPHY_START_CTRL] = 0x08, + [QPHY_PCS_STATUS] = 0x2ac, +}; + +static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = 0x00, + [QPHY_START_CTRL] = 0x44, + [QPHY_PCS_STATUS] = 0x14, + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, +}; + +static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), +}; + +static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), +}; + +static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), +}; + +static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), +}; + +static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), +}; + +static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), +}; + +static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), +}; + +static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), +}; + +static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), +}; + +static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), +}; + +static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), + QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36), + QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), +}; + +static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), +}; + +static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), + QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0), + QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), +}; + +static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355), + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a), + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa), + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), + QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa), + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1), + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68), + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2), + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa), + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab), + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414), + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0), + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), +}; + +static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), +}; + +static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), +}; + +static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), +}; + +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), +}; + +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), +}; + +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), +}; + +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), + + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), + + QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), + + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), + + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), +}; + +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), +}; + +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), +}; + +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), +}; + +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = { +}; + +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), +}; + +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), +}; + +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), +}; + +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), +}; + +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), +}; + +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), +}; + +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), +}; + +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), +}; + +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), +}; + +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), +}; + +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), +}; + +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), +}; + +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), +}; + +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), +}; + +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), +}; + +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), +}; + +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), +}; + +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), +}; + +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), + + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), + + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), + + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), + + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), +}; + +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99), +}; + +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), +}; + +struct qmp_phy; + +/* struct qmp_phy_cfg - per-PHY initialization config */ +struct qmp_phy_cfg { + /* phy-type - PCIE/UFS/USB */ + unsigned int type; + /* number of lanes provided by phy */ + int nlanes; + + /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_init_tbl *serdes_tbl; + int serdes_tbl_num; + const struct qmp_phy_init_tbl *serdes_tbl_sec; + int serdes_tbl_num_sec; + const struct qmp_phy_init_tbl *tx_tbl; + int tx_tbl_num; + const struct qmp_phy_init_tbl *tx_tbl_sec; + int tx_tbl_num_sec; + const struct qmp_phy_init_tbl *rx_tbl; + int rx_tbl_num; + const struct qmp_phy_init_tbl *rx_tbl_sec; + int rx_tbl_num_sec; + const struct qmp_phy_init_tbl *pcs_tbl; + int pcs_tbl_num; + const struct qmp_phy_init_tbl *pcs_tbl_sec; + int pcs_tbl_num_sec; + const struct qmp_phy_init_tbl *pcs_misc_tbl; + int pcs_misc_tbl_num; + const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; + int pcs_misc_tbl_num_sec; + + /* clock ids to be requested */ + const char * const *clk_list; + int num_clks; + /* resets to be requested */ + const char * const *reset_list; + int num_resets; + /* regulators to be requested */ + const char * const *vreg_list; + int num_vregs; + + /* array of registers with different offsets */ + const unsigned int *regs; + + unsigned int start_ctrl; + unsigned int pwrdn_ctrl; + unsigned int mask_com_pcs_ready; + /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ + unsigned int phy_status; + + /* true, if PHY needs delay after POWER_DOWN */ + bool has_pwrdn_delay; + /* power_down delay in usec */ + int pwrdn_delay_min; + int pwrdn_delay_max; + + /* true, if PHY has secondary tx/rx lanes to be configured */ + bool is_dual_lane_phy; + + /* QMP PHY pipe clock interface rate */ + unsigned long pipe_clock_rate; +}; + +/** + * struct qmp_phy - per-lane phy descriptor + * + * @phy: generic phy + * @cfg: phy specific configuration + * @serdes: iomapped memory space for phy's serdes (i.e. PLL) + * @tx: iomapped memory space for lane's tx + * @rx: iomapped memory space for lane's rx + * @pcs: iomapped memory space for lane's pcs + * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) + * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) + * @pcs_misc: iomapped memory space for lane's pcs_misc + * @pipe_clk: pipe clock + * @index: lane index + * @qmp: QMP phy to which this lane belongs + * @mode: current PHY mode + */ +struct qmp_phy { + struct phy *phy; + const struct qmp_phy_cfg *cfg; + void __iomem *serdes; + void __iomem *tx; + void __iomem *rx; + void __iomem *pcs; + void __iomem *tx2; + void __iomem *rx2; + void __iomem *pcs_misc; + struct clk *pipe_clk; + unsigned int index; + struct qcom_qmp *qmp; + enum phy_mode mode; +}; + +/** + * struct qcom_qmp - structure holding QMP phy block attributes + * + * @dev: device + * + * @clks: array of clocks required by phy + * @resets: array of resets required by phy + * @vregs: regulator supplies bulk data + * + * @phys: array of per-lane phy descriptors + */ +struct qcom_qmp { + struct device *dev; + + struct clk_bulk_data *clks; + struct reset_control_bulk_data *resets; + struct regulator_bulk_data *vregs; + + struct qmp_phy **phys; +}; + +static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) +{ + u32 reg; + + reg = readl(base + offset); + reg |= val; + writel(reg, base + offset); + + /* ensure that above write is through */ + readl(base + offset); +} + +static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) +{ + u32 reg; + + reg = readl(base + offset); + reg &= ~val; + writel(reg, base + offset); + + /* ensure that above write is through */ + readl(base + offset); +} + +/* list of clocks required by phy */ +static const char * const msm8996_phy_clk_l[] = { + "aux", "cfg_ahb", "ref", +}; + + +static const char * const sdm845_pciephy_clk_l[] = { + "aux", "cfg_ahb", "ref", "refgen", +}; + +/* list of regulators */ +static const char * const qmp_phy_vreg_l[] = { + "vdda-phy", "vdda-pll", +}; + +static const char * const ipq8074_pciephy_clk_l[] = { + "aux", "cfg_ahb", +}; + +/* list of resets */ +static const char * const ipq8074_pciephy_reset_l[] = { + "phy", "common", +}; + +static const char * const sdm845_pciephy_reset_l[] = { + "phy", +}; + +static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { + .type = PHY_TYPE_PCIE, + .nlanes = 1, + + .serdes_tbl = ipq8074_pcie_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), + .tx_tbl = ipq8074_pcie_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), + .rx_tbl = ipq8074_pcie_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), + .pcs_tbl = ipq8074_pcie_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), + .clk_list = ipq8074_pciephy_clk_l, + .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), + .reset_list = ipq8074_pciephy_reset_l, + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), + .vreg_list = NULL, + .num_vregs = 0, + .regs = pciephy_regs_layout, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = 995, /* us */ + .pwrdn_delay_max = 1005, /* us */ +}; + +static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { + .type = PHY_TYPE_PCIE, + .nlanes = 1, + + .serdes_tbl = ipq8074_pcie_gen3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), + .tx_tbl = ipq8074_pcie_gen3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), + .rx_tbl = ipq8074_pcie_gen3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), + .pcs_tbl = ipq8074_pcie_gen3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), + .clk_list = ipq8074_pciephy_clk_l, + .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), + .reset_list = ipq8074_pciephy_reset_l, + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), + .vreg_list = NULL, + .num_vregs = 0, + .regs = ipq_pciephy_gen3_regs_layout, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = 995, /* us */ + .pwrdn_delay_max = 1005, /* us */ + + .pipe_clock_rate = 250000000, +}; + +static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { + .type = PHY_TYPE_PCIE, + .nlanes = 1, + + .serdes_tbl = ipq6018_pcie_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), + .tx_tbl = ipq6018_pcie_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), + .rx_tbl = ipq6018_pcie_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), + .pcs_tbl = ipq6018_pcie_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), + .pcs_misc_tbl = ipq6018_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl), + .clk_list = ipq8074_pciephy_clk_l, + .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), + .reset_list = ipq8074_pciephy_reset_l, + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), + .vreg_list = NULL, + .num_vregs = 0, + .regs = ipq_pciephy_gen3_regs_layout, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = 995, /* us */ + .pwrdn_delay_max = 1005, /* us */ +}; + +static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { + .type = PHY_TYPE_PCIE, + .nlanes = 1, + + .serdes_tbl = sdm845_qmp_pcie_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), + .tx_tbl = sdm845_qmp_pcie_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), + .rx_tbl = sdm845_qmp_pcie_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), + .pcs_tbl = sdm845_qmp_pcie_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), + .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), + .clk_list = sdm845_pciephy_clk_l, + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sdm845_qmp_pciephy_regs_layout, + + .start_ctrl = PCS_START | SERDES_START, + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = 995, /* us */ + .pwrdn_delay_max = 1005, /* us */ +}; + +static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { + .type = PHY_TYPE_PCIE, + .nlanes = 1, + + .serdes_tbl = sdm845_qhp_pcie_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), + .tx_tbl = sdm845_qhp_pcie_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), + .rx_tbl = sdm845_qhp_pcie_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), + .pcs_tbl = sdm845_qhp_pcie_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), + .clk_list = sdm845_pciephy_clk_l, + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sdm845_qhp_pciephy_regs_layout, + + .start_ctrl = PCS_START | SERDES_START, + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = 995, /* us */ + .pwrdn_delay_max = 1005, /* us */ +}; + +static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { + .type = PHY_TYPE_PCIE, + .nlanes = 1, + + .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), + .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl, + .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), + .tx_tbl = sm8250_qmp_pcie_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), + .rx_tbl = sm8250_qmp_pcie_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), + .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl, + .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), + .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), + .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl, + .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), + .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), + .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), + .clk_list = sdm845_pciephy_clk_l, + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8250_pcie_regs_layout, + + .start_ctrl = PCS_START | SERDES_START, + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = 995, /* us */ + .pwrdn_delay_max = 1005, /* us */ +}; + +static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { + .type = PHY_TYPE_PCIE, + .nlanes = 2, + + .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), + .tx_tbl = sm8250_qmp_pcie_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), + .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl, + .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), + .rx_tbl = sm8250_qmp_pcie_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), + .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl, + .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), + .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), + .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl, + .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), + .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), + .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), + .clk_list = sdm845_pciephy_clk_l, + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8250_pcie_regs_layout, + + .start_ctrl = PCS_START | SERDES_START, + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, + + .is_dual_lane_phy = true, + .has_pwrdn_delay = true, + .pwrdn_delay_min = 995, /* us */ + .pwrdn_delay_max = 1005, /* us */ +}; + +static const struct qmp_phy_cfg msm8998_pciephy_cfg = { + .type = PHY_TYPE_PCIE, + .nlanes = 1, + + .serdes_tbl = msm8998_pcie_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), + .tx_tbl = msm8998_pcie_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), + .rx_tbl = msm8998_pcie_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), + .pcs_tbl = msm8998_pcie_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), + .clk_list = msm8996_phy_clk_l, + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), + .reset_list = ipq8074_pciephy_reset_l, + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = pciephy_regs_layout, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, +}; + +static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { + .type = PHY_TYPE_PCIE, + .nlanes = 1, + + .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), + .tx_tbl = sc8180x_qmp_pcie_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), + .rx_tbl = sc8180x_qmp_pcie_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), + .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), + .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), + .clk_list = sdm845_pciephy_clk_l, + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8250_pcie_regs_layout, + + .start_ctrl = PCS_START | SERDES_START, + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = 995, /* us */ + .pwrdn_delay_max = 1005, /* us */ +}; + +static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { + .type = PHY_TYPE_PCIE, + .nlanes = 2, + + .serdes_tbl = sdx55_qmp_pcie_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), + .tx_tbl = sdx55_qmp_pcie_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), + .rx_tbl = sdx55_qmp_pcie_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), + .pcs_tbl = sdx55_qmp_pcie_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), + .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), + .clk_list = sdm845_pciephy_clk_l, + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8250_pcie_regs_layout, + + .start_ctrl = PCS_START | SERDES_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS_4_20, + + .is_dual_lane_phy = true, + .has_pwrdn_delay = true, + .pwrdn_delay_min = 995, /* us */ + .pwrdn_delay_max = 1005, /* us */ +}; + +static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { + .type = PHY_TYPE_PCIE, + .nlanes = 1, + + .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), + .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), + .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), + .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), + .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), + .clk_list = sdm845_pciephy_clk_l, + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8250_pcie_regs_layout, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = 995, /* us */ + .pwrdn_delay_max = 1005, /* us */ +}; + +static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { + .type = PHY_TYPE_PCIE, + .nlanes = 2, + + .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), + .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), + .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), + .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), + .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), + .clk_list = sdm845_pciephy_clk_l, + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8250_pcie_regs_layout, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS_4_20, + + .is_dual_lane_phy = true, + .has_pwrdn_delay = true, + .pwrdn_delay_min = 995, /* us */ + .pwrdn_delay_max = 1005, /* us */ +}; + +static void qcom_qmp_phy_pcie_configure_lane(void __iomem *base, + const unsigned int *regs, + const struct qmp_phy_init_tbl tbl[], + int num, + u8 lane_mask) +{ + int i; + const struct qmp_phy_init_tbl *t = tbl; + + if (!t) + return; + + for (i = 0; i < num; i++, t++) { + if (!(t->lane_mask & lane_mask)) + continue; + + if (t->in_layout) + writel(t->val, base + regs[t->offset]); + else + writel(t->val, base + t->offset); + } +} + +static void qcom_qmp_phy_pcie_configure(void __iomem *base, + const unsigned int *regs, + const struct qmp_phy_init_tbl tbl[], + int num) +{ + qcom_qmp_phy_pcie_configure_lane(base, regs, tbl, num, 0xff); +} + +static int qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy) +{ + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *serdes = qphy->serdes; + const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; + int serdes_tbl_num = cfg->serdes_tbl_num; + + qcom_qmp_phy_pcie_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); + if (cfg->serdes_tbl_sec) + qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, + cfg->serdes_tbl_num_sec); + + return 0; +} + +static int qcom_qmp_phy_pcie_com_init(struct qmp_phy *qphy) +{ + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *pcs = qphy->pcs; + int ret; + + /* turn on regulator supplies */ + ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); + if (ret) { + dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); + return ret; + } + + ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); + if (ret) { + dev_err(qmp->dev, "reset assert failed\n"); + goto err_disable_regulators; + } + + ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); + if (ret) { + dev_err(qmp->dev, "reset deassert failed\n"); + goto err_disable_regulators; + } + + ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); + if (ret) + goto err_assert_reset; + + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) + qphy_setbits(pcs, + cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + cfg->pwrdn_ctrl); + else + qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, + cfg->pwrdn_ctrl); + + return 0; + +err_assert_reset: + reset_control_bulk_assert(cfg->num_resets, qmp->resets); +err_disable_regulators: + regulator_bulk_disable(cfg->num_vregs, qmp->vregs); + + return ret; +} + +static int qcom_qmp_phy_pcie_com_exit(struct qmp_phy *qphy) +{ + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + + reset_control_bulk_assert(cfg->num_resets, qmp->resets); + + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); + + regulator_bulk_disable(cfg->num_vregs, qmp->vregs); + + return 0; +} + +static int qcom_qmp_phy_pcie_init(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + struct qcom_qmp *qmp = qphy->qmp; + int ret; + dev_vdbg(qmp->dev, "Initializing QMP phy\n"); + + ret = qcom_qmp_phy_pcie_com_init(qphy); + if (ret) + return ret; + + return 0; +} + +static int qcom_qmp_phy_pcie_power_on(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *tx = qphy->tx; + void __iomem *rx = qphy->rx; + void __iomem *pcs = qphy->pcs; + void __iomem *pcs_misc = qphy->pcs_misc; + void __iomem *status; + unsigned int mask, val, ready; + int ret; + + qcom_qmp_phy_pcie_serdes_init(qphy); + + ret = clk_prepare_enable(qphy->pipe_clk); + if (ret) { + dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); + return ret; + } + + /* Tx, Rx, and PCS configurations */ + qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs, + cfg->tx_tbl, cfg->tx_tbl_num, 1); + if (cfg->tx_tbl_sec) + qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, + cfg->tx_tbl_num_sec, 1); + + /* Configuration for other LANE for USB-DP combo PHY */ + if (cfg->is_dual_lane_phy) { + qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs, + cfg->tx_tbl, cfg->tx_tbl_num, 2); + if (cfg->tx_tbl_sec) + qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs, + cfg->tx_tbl_sec, + cfg->tx_tbl_num_sec, 2); + } + + qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs, + cfg->rx_tbl, cfg->rx_tbl_num, 1); + if (cfg->rx_tbl_sec) + qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs, + cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); + + if (cfg->is_dual_lane_phy) { + qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs, + cfg->rx_tbl, cfg->rx_tbl_num, 2); + if (cfg->rx_tbl_sec) + qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs, + cfg->rx_tbl_sec, + cfg->rx_tbl_num_sec, 2); + } + + qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); + if (cfg->pcs_tbl_sec) + qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, + cfg->pcs_tbl_num_sec); + + qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, + cfg->pcs_misc_tbl_num); + if (cfg->pcs_misc_tbl_sec) + qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, + cfg->pcs_misc_tbl_num_sec); + + /* + * Pull out PHY from POWER DOWN state. + * This is active low enable signal to power-down PHY. + */ + qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); + + if (cfg->has_pwrdn_delay) + usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); + + /* Pull PHY out of reset state */ + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + + /* start SerDes and Phy-Coding-Sublayer */ + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + + status = pcs + cfg->regs[QPHY_PCS_STATUS]; + mask = cfg->phy_status; + ready = 0; + + ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, + PHY_INIT_COMPLETE_TIMEOUT); + if (ret) { + dev_err(qmp->dev, "phy initialization timed-out\n"); + goto err_disable_pipe_clk; + } + + return 0; + +err_disable_pipe_clk: + clk_disable_unprepare(qphy->pipe_clk); + + return ret; +} + +static int qcom_qmp_phy_pcie_power_off(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qphy->cfg; + + clk_disable_unprepare(qphy->pipe_clk); + + /* PHY reset */ + qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + + /* stop SerDes and Phy-Coding-Sublayer */ + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + + /* Put PHY into POWER DOWN state: active low */ + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + cfg->pwrdn_ctrl); + } else { + qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, + cfg->pwrdn_ctrl); + } + + return 0; +} + +static int qcom_qmp_phy_pcie_exit(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + + qcom_qmp_phy_pcie_com_exit(qphy); + + return 0; +} + +static int qcom_qmp_phy_pcie_enable(struct phy *phy) +{ + int ret; + + ret = qcom_qmp_phy_pcie_init(phy); + if (ret) + return ret; + + ret = qcom_qmp_phy_pcie_power_on(phy); + if (ret) + qcom_qmp_phy_pcie_exit(phy); + + return ret; +} + +static int qcom_qmp_phy_pcie_disable(struct phy *phy) +{ + int ret; + + ret = qcom_qmp_phy_pcie_power_off(phy); + if (ret) + return ret; + return qcom_qmp_phy_pcie_exit(phy); +} + +static int qcom_qmp_phy_pcie_set_mode(struct phy *phy, + enum phy_mode mode, int submode) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + + qphy->mode = mode; + + return 0; +} + +static int qcom_qmp_phy_pcie_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) +{ + struct qcom_qmp *qmp = dev_get_drvdata(dev); + int num = cfg->num_vregs; + int i; + + qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); + if (!qmp->vregs) + return -ENOMEM; + + for (i = 0; i < num; i++) + qmp->vregs[i].supply = cfg->vreg_list[i]; + + return devm_regulator_bulk_get(dev, num, qmp->vregs); +} + +static int qcom_qmp_phy_pcie_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) +{ + struct qcom_qmp *qmp = dev_get_drvdata(dev); + int i; + int ret; + + qmp->resets = devm_kcalloc(dev, cfg->num_resets, + sizeof(*qmp->resets), GFP_KERNEL); + if (!qmp->resets) + return -ENOMEM; + + for (i = 0; i < cfg->num_resets; i++) + qmp->resets[i].id = cfg->reset_list[i]; + + ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); + if (ret) + return dev_err_probe(dev, ret, "failed to get resets\n"); + + return 0; +} + +static int qcom_qmp_phy_pcie_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) +{ + struct qcom_qmp *qmp = dev_get_drvdata(dev); + int num = cfg->num_clks; + int i; + + qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); + if (!qmp->clks) + return -ENOMEM; + + for (i = 0; i < num; i++) + qmp->clks[i].id = cfg->clk_list[i]; + + return devm_clk_bulk_get(dev, num, qmp->clks); +} + +static void phy_clk_release_provider(void *res) +{ + of_clk_del_provider(res); +} + +/* + * Register a fixed rate pipe clock. + * + * The _pipe_clksrc generated by PHY goes to the GCC that gate + * controls it. The _pipe_clk coming out of the GCC is requested + * by the PHY driver for its operations. + * We register the _pipe_clksrc here. The gcc driver takes care + * of assigning this _pipe_clksrc as parent to _pipe_clk. + * Below picture shows this relationship. + * + * +---------------+ + * | PHY block |<<---------------------------------------+ + * | | | + * | +-------+ | +-----+ | + * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ + * clk | +-------+ | +-----+ + * +---------------+ + */ +static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) +{ + struct clk_fixed_rate *fixed; + struct clk_init_data init = { }; + int ret; + + ret = of_property_read_string(np, "clock-output-names", &init.name); + if (ret) { + dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); + return ret; + } + + fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); + if (!fixed) + return -ENOMEM; + + init.ops = &clk_fixed_rate_ops; + + /* + * Controllers using QMP PHY-s use 125MHz pipe clock interface + * unless other frequency is specified in the PHY config. + */ + if (qmp->phys[0]->cfg->pipe_clock_rate) + fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate; + else + fixed->fixed_rate = 125000000; + + fixed->hw.init = &init; + + ret = devm_clk_hw_register(qmp->dev, &fixed->hw); + if (ret) + return ret; + + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); + if (ret) + return ret; + + /* + * Roll a devm action because the clock provider is the child node, but + * the child node is not actually a device. + */ + return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); +} + +static const struct phy_ops qcom_qmp_phy_pcie_ops = { + .power_on = qcom_qmp_phy_pcie_enable, + .power_off = qcom_qmp_phy_pcie_disable, + .set_mode = qcom_qmp_phy_pcie_set_mode, + .owner = THIS_MODULE, +}; + +static +int qcom_qmp_phy_pcie_create(struct device *dev, struct device_node *np, int id, + void __iomem *serdes, const struct qmp_phy_cfg *cfg) +{ + struct qcom_qmp *qmp = dev_get_drvdata(dev); + struct phy *generic_phy; + struct qmp_phy *qphy; + char prop_name[MAX_PROP_NAME]; + int ret; + + qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); + if (!qphy) + return -ENOMEM; + + qphy->cfg = cfg; + qphy->serdes = serdes; + /* + * Get memory resources for each phy lane: + * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. + * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 + * For single lane PHYs: pcs_misc (optional) -> 3. + */ + qphy->tx = of_iomap(np, 0); + if (!qphy->tx) + return -ENOMEM; + + qphy->rx = of_iomap(np, 1); + if (!qphy->rx) + return -ENOMEM; + + qphy->pcs = of_iomap(np, 2); + if (!qphy->pcs) + return -ENOMEM; + + /* + * If this is a dual-lane PHY, then there should be registers for the + * second lane. Some old device trees did not specify this, so fall + * back to old legacy behavior of assuming they can be reached at an + * offset from the first lane. + */ + if (cfg->is_dual_lane_phy) { + qphy->tx2 = of_iomap(np, 3); + qphy->rx2 = of_iomap(np, 4); + if (!qphy->tx2 || !qphy->rx2) { + dev_warn(dev, + "Underspecified device tree, falling back to legacy register regions\n"); + + /* In the old version, pcs_misc is at index 3. */ + qphy->pcs_misc = qphy->tx2; + qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; + qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; + + } else { + qphy->pcs_misc = of_iomap(np, 5); + } + + } else { + qphy->pcs_misc = of_iomap(np, 3); + } + + if (!qphy->pcs_misc && + of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) + qphy->pcs_misc = qphy->pcs + 0x400; + + if (!qphy->pcs_misc) + dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); + + snprintf(prop_name, sizeof(prop_name), "pipe%d", id); + qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); + if (IS_ERR(qphy->pipe_clk)) { + return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), + "failed to get lane%d pipe clock\n", id); + } + + generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_ops); + if (IS_ERR(generic_phy)) { + ret = PTR_ERR(generic_phy); + dev_err(dev, "failed to create qphy %d\n", ret); + return ret; + } + + qphy->phy = generic_phy; + qphy->index = id; + qphy->qmp = qmp; + qmp->phys[id] = qphy; + phy_set_drvdata(generic_phy, qphy); + + return 0; +} + +static const struct of_device_id qcom_qmp_phy_pcie_of_match_table[] = { + { + .compatible = "qcom,msm8998-qmp-pcie-phy", + .data = &msm8998_pciephy_cfg, + }, { + .compatible = "qcom,ipq8074-qmp-pcie-phy", + .data = &ipq8074_pciephy_cfg, + }, { + .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy", + .data = &ipq8074_pciephy_gen3_cfg, + }, { + .compatible = "qcom,ipq6018-qmp-pcie-phy", + .data = &ipq6018_pciephy_cfg, + }, { + .compatible = "qcom,sc8180x-qmp-pcie-phy", + .data = &sc8180x_pciephy_cfg, + }, { + .compatible = "qcom,sdm845-qhp-pcie-phy", + .data = &sdm845_qhp_pciephy_cfg, + }, { + .compatible = "qcom,sdm845-qmp-pcie-phy", + .data = &sdm845_qmp_pciephy_cfg, + }, { + .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", + .data = &sm8250_qmp_gen3x1_pciephy_cfg, + }, { + .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", + .data = &sm8250_qmp_gen3x2_pciephy_cfg, + }, { + .compatible = "qcom,sm8250-qmp-modem-pcie-phy", + .data = &sm8250_qmp_gen3x2_pciephy_cfg, + }, { + .compatible = "qcom,sdx55-qmp-pcie-phy", + .data = &sdx55_qmp_pciephy_cfg, + }, { + .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", + .data = &sm8450_qmp_gen3x1_pciephy_cfg, + }, { + .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", + .data = &sm8450_qmp_gen4x2_pciephy_cfg, + }, + { }, +}; +MODULE_DEVICE_TABLE(of, qcom_qmp_phy_pcie_of_match_table); + +static int qcom_qmp_phy_pcie_probe(struct platform_device *pdev) +{ + struct qcom_qmp *qmp; + struct device *dev = &pdev->dev; + struct device_node *child; + struct phy_provider *phy_provider; + void __iomem *serdes; + const struct qmp_phy_cfg *cfg = NULL; + int num, id; + int ret; + + qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); + if (!qmp) + return -ENOMEM; + + qmp->dev = dev; + dev_set_drvdata(dev, qmp); + + /* Get the specific init parameters of QMP phy */ + cfg = of_device_get_match_data(dev); + if (!cfg) + return -EINVAL; + + /* per PHY serdes; usually located at base address */ + serdes = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(serdes)) + return PTR_ERR(serdes); + + ret = qcom_qmp_phy_pcie_clk_init(dev, cfg); + if (ret) + return ret; + + ret = qcom_qmp_phy_pcie_reset_init(dev, cfg); + if (ret) + return ret; + + ret = qcom_qmp_phy_pcie_vreg_init(dev, cfg); + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(dev, "failed to get regulator supplies: %d\n", + ret); + return ret; + } + + num = of_get_available_child_count(dev->of_node); + /* do we have a rogue child node ? */ + if (num > 1) + return -EINVAL; + + qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); + if (!qmp->phys) + return -ENOMEM; + + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + /* + * Prevent runtime pm from being ON by default. Users can enable + * it using power/control in sysfs. + */ + pm_runtime_forbid(dev); + + id = 0; + for_each_available_child_of_node(dev->of_node, child) { + /* Create per-lane phy */ + ret = qcom_qmp_phy_pcie_create(dev, child, id, serdes, cfg); + if (ret) { + dev_err(dev, "failed to create lane%d phy, %d\n", + id, ret); + goto err_node_put; + } + + /* + * Register the pipe clock provided by phy. + * See function description to see details of this pipe clock. + */ + ret = phy_pipe_clk_register(qmp, child); + if (ret) { + dev_err(qmp->dev, + "failed to register pipe clock source\n"); + goto err_node_put; + } + + id++; + } + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (!IS_ERR(phy_provider)) + dev_info(dev, "Registered Qcom-QMP phy\n"); + else + pm_runtime_disable(dev); + + return PTR_ERR_OR_ZERO(phy_provider); + +err_node_put: + pm_runtime_disable(dev); + of_node_put(child); + return ret; +} + +static struct platform_driver qcom_qmp_phy_pcie_driver = { + .probe = qcom_qmp_phy_pcie_probe, + .driver = { + .name = "qcom-qmp-pcie-phy", + .of_match_table = qcom_qmp_phy_pcie_of_match_table, + }, +}; + +module_platform_driver(qcom_qmp_phy_pcie_driver); + +MODULE_AUTHOR("Vivek Gautam "); +MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v3.h new file mode 100644 index 000000000000..a45bd301bc9e --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v3.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_MISC_V3_H_ +#define QCOM_PHY_QMP_PCS_MISC_V3_H_ + +/* Only for QMP V3 PHY - PCS_MISC registers */ +#define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c +#define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c +#define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44 +#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54 +#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c +#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h new file mode 100644 index 000000000000..4cc02288d418 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V4_H_ + +/* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */ +#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_STATUS 0x00 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_STATUS 0x04 +#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG1 0x08 +#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c +#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG3 0x10 +#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 +#define QPHY_V4_PCS_PCIE_PCS_TX_RX_CONFIG 0x18 +#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c +#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_CNTRL 0x20 +#define QPHY_V4_PCS_PCIE_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK 0x24 +#define QPHY_V4_PCS_PCIE_EPCLK_DLY_COUNT_VAL_L 0x28 +#define QPHY_V4_PCS_PCIE_EPCLK_DLY_COUNT_VAL_H 0x2c +#define QPHY_V4_PCS_PCIE_RX_IDLE_DTCT_CNTRL1 0x30 +#define QPHY_V4_PCS_PCIE_RX_IDLE_DTCT_CNTRL2 0x34 +#define QPHY_V4_PCS_PCIE_SIGDET_CNTRL 0x38 +#define QPHY_V4_PCS_PCIE_SIGDET_LOW_2_IDLE_TIME 0x3c +#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 +#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x44 +#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 +#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x4c +#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 +#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG2 0x54 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG1 0x58 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2 0x5c +#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG3 0x60 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG4 0x64 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG5 0x68 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG6 0x6c +#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG7 0x70 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG1 0x74 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x78 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG3 0x7c +#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x80 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x84 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x88 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG7 0x8c +#define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 +#define QPHY_V4_PCS_PCIE_LOCAL_FS 0x94 +#define QPHY_V4_PCS_PCIE_LOCAL_LF 0x98 +#define QPHY_V4_PCS_PCIE_LOCAL_FS_RS 0x9c +#define QPHY_V4_PCS_PCIE_EQ_CONFIG1 0xa0 +#define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 +#define QPHY_V4_PCS_PCIE_PRESET_P0_P1_PRE 0xa8 +#define QPHY_V4_PCS_PCIE_PRESET_P2_P3_PRE 0xac +#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_PRE 0xb0 +#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 +#define QPHY_V4_PCS_PCIE_PRESET_P8_P9_PRE 0xb8 +#define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc +#define QPHY_V4_PCS_PCIE_PRESET_P1_P3_PRE_RS 0xc0 +#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_PRE_RS 0xc4 +#define QPHY_V4_PCS_PCIE_PRESET_P6_P9_PRE_RS 0xc8 +#define QPHY_V4_PCS_PCIE_PRESET_P0_P1_POST 0xcc +#define QPHY_V4_PCS_PCIE_PRESET_P2_P3_POST 0xd0 +#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_POST 0xd4 +#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_POST 0xd8 +#define QPHY_V4_PCS_PCIE_PRESET_P8_P9_POST 0xdc +#define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 +#define QPHY_V4_PCS_PCIE_PRESET_P1_P3_POST_RS 0xe4 +#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_POST_RS 0xe8 +#define QPHY_V4_PCS_PCIE_PRESET_P6_P9_POST_RS 0xec +#define QPHY_V4_PCS_PCIE_RXEQEVAL_TIME 0xf0 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h new file mode 100644 index 000000000000..af273602998e --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_20_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V4_20_H_ + +#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 +#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 +#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 +#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc +#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 +#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824 +#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h new file mode 100644 index 000000000000..2e19fb3f051e --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h @@ -0,0 +1,16 @@ +/* Only for QMP V5 PHY - PCS_PCIE registers */ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V5_H_ + +/* Only for QMP V5 PHY - PCS_PCIE registers */ +#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 +#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 +#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 +#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h new file mode 100644 index 000000000000..1eedf50cf9cb --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_20_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V5_20_H_ + +/* Only for QMP V5_20 PHY - PCIe PCS registers */ +#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c +#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 +#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0 +#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 +#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c +#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h new file mode 100644 index 000000000000..ba1ea29d2884 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_UFS_V3_H_ +#define QCOM_PHY_QMP_PCS_UFS_V3_H_ + +#define QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x02c +#define QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x034 +#define QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL 0x134 +#define QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME 0x138 +#define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1 0x13c +#define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2 0x140 +#define QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1 0x1bc +#define QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1 0x1c4 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v4.h new file mode 100644 index 000000000000..a1c7d3d17150 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v4.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_UFS_V4_H_ +#define QCOM_PHY_QMP_PCS_UFS_V4_H_ + +/* Only for QMP V4 PHY - UFS PCS registers */ +#define QPHY_V4_PCS_UFS_PHY_START 0x000 +#define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004 +#define QPHY_V4_PCS_UFS_SW_RESET 0x008 +#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c +#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 +#define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c +#define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 +#define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 +#define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 +#define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 +#define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 +#define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 +#define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148 +#define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 +#define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158 +#define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160 +#define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168 +#define QPHY_V4_PCS_UFS_READY_STATUS 0x180 +#define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 +#define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h new file mode 100644 index 000000000000..bcca23493b7e --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h @@ -0,0 +1,27 @@ +/* Only for QMP V5 PHY - UFS PCS registers */ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_UFS_V5_H_ +#define QCOM_PHY_QMP_PCS_UFS_V5_H_ + +/* Only for QMP V5 PHY - UFS PCS registers */ +#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c +#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 +#define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c +#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 +#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 +#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 +#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 +#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 +#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 +#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154 +#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158 +#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160 +#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168 +#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 +#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v4.h new file mode 100644 index 000000000000..d7fd4ac0fc55 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v4.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_USB_V4_H_ +#define QCOM_PHY_QMP_PCS_USB_V4_H_ + +/* Only for QMP V4 PHY - USB3 PCS registers */ +#define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x000 +#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004 +#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008 +#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c +#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010 +#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014 +#define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018 +#define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x01c +#define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x020 +#define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024 +#define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x028 +#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x02c +#define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x030 +#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x034 +#define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x038 +#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x03c +#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x040 +#define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x044 +#define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x048 +#define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x04c +#define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x050 +#define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x054 +#define QPHY_V4_PCS_USB3_TEST_CONTROL 0x058 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h new file mode 100644 index 000000000000..73de626223ed --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_USB_V5_H_ +#define QCOM_PHY_QMP_PCS_USB_V5_H_ + +/* Only for QMP V5 PHY - USB3 have different offsets than V4 */ +#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000 +#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004 +#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008 +#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c +#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010 +#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014 +#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018 +#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c +#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020 +#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024 +#define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x028 +#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x02c +#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x030 +#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x034 +#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x038 +#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x03c +#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x040 +#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x044 +#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x048 +#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x04c +#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x050 +#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x054 +#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x058 +#define QPHY_V5_PCS_USB3_TEST_CONTROL 0x05c +#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x060 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h new file mode 100644 index 000000000000..c8515f506872 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_V2_H_ +#define QCOM_PHY_QMP_PCS_V2_H_ + +/* Only for QMP V2 PHY - PCS registers */ +#define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004 +#define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024 +#define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028 +#define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x034 +#define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x038 +#define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x03c +#define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x040 +#define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x054 +#define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x058 +#define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x060 +#define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x064 +#define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x06c +#define QPHY_V2_PCS_LOCK_DETECT_CONFIG1 0x080 +#define QPHY_V2_PCS_LOCK_DETECT_CONFIG2 0x084 +#define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x088 +#define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 +#define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 +#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 +#define QPHY_V2_PCS_FLL_CNTRL1 0x0c0 +#define QPHY_V2_PCS_FLL_CNTRL2 0x0c4 +#define QPHY_V2_PCS_FLL_CNT_VAL_L 0x0c8 +#define QPHY_V2_PCS_FLL_CNT_VAL_H_TOL 0x0cc +#define QPHY_V2_PCS_FLL_MAN_CODE 0x0d0 + +/* UFS only ? */ +#define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0x0cc +#define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c +#define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140 +#define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148 +#define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154 +#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8 +#define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac +#define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8 +#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc +#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h new file mode 100644 index 000000000000..10dbbb006201 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_V3_H_ +#define QCOM_PHY_QMP_PCS_V3_H_ + +/* Only for QMP V3 PHY - PCS registers */ +#define QPHY_V3_PCS_SW_RESET 0x000 +#define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 +#define QPHY_V3_PCS_START_CONTROL 0x008 +#define QPHY_V3_PCS_TXMGN_V0 0x00c +#define QPHY_V3_PCS_TXMGN_V1 0x010 +#define QPHY_V3_PCS_TXMGN_V2 0x014 +#define QPHY_V3_PCS_TXMGN_V3 0x018 +#define QPHY_V3_PCS_TXMGN_V4 0x01c +#define QPHY_V3_PCS_TXMGN_LS 0x020 +#define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 +#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028 +#define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c +#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030 +#define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034 +#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038 +#define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c +#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040 +#define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044 +#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048 +#define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c +#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050 +#define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054 +#define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058 +#define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c +#define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060 +#define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064 +#define QPHY_V3_PCS_POWER_STATE_CONFIG3 0x068 +#define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c +#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070 +#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074 +#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078 +#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c +#define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080 +#define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084 +#define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088 +#define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c +#define QPHY_V3_PCS_SIGDET_LOW_2_IDLE_TIME 0x090 +#define QPHY_V3_PCS_BEACON_2_IDLE_TIME_L 0x094 +#define QPHY_V3_PCS_BEACON_2_IDLE_TIME_H 0x098 +#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_SYSCLK 0x09c +#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 +#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 +#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 +#define QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL 0x0ac +#define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0 +#define QPHY_V3_PCS_LFPS_TX_END_CNT_P2U3_START 0x0b4 +#define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8 +#define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc +#define QPHY_V3_PCS_TXONESZEROS_RUN_LENGTH 0x0c0 +#define QPHY_V3_PCS_FLL_CNTRL1 0x0c4 +#define QPHY_V3_PCS_FLL_CNTRL2 0x0c8 +#define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc +#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0 +#define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4 +#define QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL 0x0d8 +#define QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR 0x0dc +#define QPHY_V3_PCS_ARCVR_DTCT_EN_PERIOD 0x0e0 +#define QPHY_V3_PCS_ARCVR_DTCT_CM_DLY 0x0e4 +#define QPHY_V3_PCS_ALFPS_DEGLITCH_VAL 0x0e8 +#define QPHY_V3_PCS_INSIG_SW_CTRL1 0x0ec +#define QPHY_V3_PCS_INSIG_SW_CTRL2 0x0f0 +#define QPHY_V3_PCS_INSIG_SW_CTRL3 0x0f4 +#define QPHY_V3_PCS_INSIG_MX_CTRL1 0x0f8 +#define QPHY_V3_PCS_INSIG_MX_CTRL2 0x0fc +#define QPHY_V3_PCS_INSIG_MX_CTRL3 0x100 +#define QPHY_V3_PCS_OUTSIG_SW_CTRL1 0x104 +#define QPHY_V3_PCS_OUTSIG_MX_CTRL1 0x108 +#define QPHY_V3_PCS_CLK_DEBUG_BYPASS_CTRL 0x10c +#define QPHY_V3_PCS_TEST_CONTROL 0x110 +#define QPHY_V3_PCS_TEST_CONTROL2 0x114 +#define QPHY_V3_PCS_TEST_CONTROL3 0x118 +#define QPHY_V3_PCS_TEST_CONTROL4 0x11c +#define QPHY_V3_PCS_TEST_CONTROL5 0x120 +#define QPHY_V3_PCS_TEST_CONTROL6 0x124 +#define QPHY_V3_PCS_TEST_CONTROL7 0x128 +#define QPHY_V3_PCS_COM_RESET_CONTROL 0x12c +#define QPHY_V3_PCS_BIST_CTRL 0x130 +#define QPHY_V3_PCS_PRBS_POLY0 0x134 +#define QPHY_V3_PCS_PRBS_POLY1 0x138 +#define QPHY_V3_PCS_PRBS_SEED0 0x13c +#define QPHY_V3_PCS_PRBS_SEED1 0x140 +#define QPHY_V3_PCS_FIXED_PAT_CTRL 0x144 +#define QPHY_V3_PCS_FIXED_PAT0 0x148 +#define QPHY_V3_PCS_FIXED_PAT1 0x14c +#define QPHY_V3_PCS_FIXED_PAT2 0x150 +#define QPHY_V3_PCS_FIXED_PAT3 0x154 +#define QPHY_V3_PCS_COM_CLK_SWITCH_CTRL 0x158 +#define QPHY_V3_PCS_ELECIDLE_DLY_SEL 0x15c +#define QPHY_V3_PCS_SPARE1 0x160 +#define QPHY_V3_PCS_BIST_CHK_ERR_CNT_L_STATUS 0x164 +#define QPHY_V3_PCS_BIST_CHK_ERR_CNT_H_STATUS 0x168 +#define QPHY_V3_PCS_BIST_CHK_STATUS 0x16c +#define QPHY_V3_PCS_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x170 +#define QPHY_V3_PCS_PCS_STATUS 0x174 +#define QPHY_V3_PCS_PCS_STATUS2 0x178 +#define QPHY_V3_PCS_PCS_STATUS3 0x17c +#define QPHY_V3_PCS_COM_RESET_STATUS 0x180 +#define QPHY_V3_PCS_OSC_DTCT_STATUS 0x184 +#define QPHY_V3_PCS_REVISION_ID0 0x188 +#define QPHY_V3_PCS_REVISION_ID1 0x18c +#define QPHY_V3_PCS_REVISION_ID2 0x190 +#define QPHY_V3_PCS_REVISION_ID3 0x194 +#define QPHY_V3_PCS_DEBUG_BUS_0_STATUS 0x198 +#define QPHY_V3_PCS_DEBUG_BUS_1_STATUS 0x19c +#define QPHY_V3_PCS_DEBUG_BUS_2_STATUS 0x1a0 +#define QPHY_V3_PCS_DEBUG_BUS_3_STATUS 0x1a4 +#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8 +#define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac +#define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0 +#define QPHY_V3_PCS_IDAC_CAL_CNTRL 0x1b4 +#define QPHY_V3_PCS_CMN_ACK_OUT_SEL 0x1b8 +#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME_SYSCLK 0x1bc +#define QPHY_V3_PCS_AUTONOMOUS_MODE_STATUS 0x1c0 +#define QPHY_V3_PCS_ENDPOINT_REFCLK_CNTRL 0x1c4 +#define QPHY_V3_PCS_EPCLK_PRE_PLL_LOCK_DLY_SYSCLK 0x1c8 +#define QPHY_V3_PCS_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK 0x1cc +#define QPHY_V3_PCS_EPCLK_DLY_COUNT_VAL_L 0x1d0 +#define QPHY_V3_PCS_EPCLK_DLY_COUNT_VAL_H 0x1d4 +#define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8 +#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc +#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 +#define QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL2 0x1e4 +#define QPHY_V3_PCS_RXTERMINATION_DLY_SEL 0x1e8 +#define QPHY_V3_PCS_LFPS_PER_TIMER_VAL 0x1ec +#define QPHY_V3_PCS_SIGDET_STARTUP_TIMER_VAL 0x1f0 +#define QPHY_V3_PCS_LOCK_DETECT_CONFIG4 0x1f4 +#define QPHY_V3_PCS_RX_SIGDET_DTCT_CNTRL 0x1f8 +#define QPHY_V3_PCS_PCS_STATUS4 0x1fc +#define QPHY_V3_PCS_PCS_STATUS4_CLEAR 0x200 +#define QPHY_V3_PCS_DEC_ERROR_COUNT_STATUS 0x204 +#define QPHY_V3_PCS_COMMA_POS_STATUS 0x208 +#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c +#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210 +#define QPHY_V3_PCS_REFGEN_REQ_CONFIG3 0x214 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4.h new file mode 100644 index 000000000000..a2c1eba2b693 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_V4_H_ +#define QCOM_PHY_QMP_PCS_V4_H_ + +/* Only for QMP V4 PHY - USB/PCIe PCS registers */ +#define QPHY_V4_PCS_SW_RESET 0x000 +#define QPHY_V4_PCS_REVISION_ID0 0x004 +#define QPHY_V4_PCS_REVISION_ID1 0x008 +#define QPHY_V4_PCS_REVISION_ID2 0x00c +#define QPHY_V4_PCS_REVISION_ID3 0x010 +#define QPHY_V4_PCS_PCS_STATUS1 0x014 +#define QPHY_V4_PCS_PCS_STATUS2 0x018 +#define QPHY_V4_PCS_PCS_STATUS3 0x01c +#define QPHY_V4_PCS_PCS_STATUS4 0x020 +#define QPHY_V4_PCS_PCS_STATUS5 0x024 +#define QPHY_V4_PCS_PCS_STATUS6 0x028 +#define QPHY_V4_PCS_PCS_STATUS7 0x02c +#define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030 +#define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034 +#define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038 +#define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c +#define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040 +#define QPHY_V4_PCS_START_CONTROL 0x044 +#define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048 +#define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c +#define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050 +#define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054 +#define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058 +#define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c +#define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060 +#define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064 +#define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068 +#define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c +#define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070 +#define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074 +#define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078 +#define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c +#define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080 +#define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084 +#define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088 +#define QPHY_V4_PCS_CLAMP_ENABLE 0x08c +#define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090 +#define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094 +#define QPHY_V4_PCS_FLL_CNTRL1 0x098 +#define QPHY_V4_PCS_FLL_CNTRL2 0x09c +#define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0 +#define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4 +#define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8 +#define QPHY_V4_PCS_TEST_CONTROL1 0x0ac +#define QPHY_V4_PCS_TEST_CONTROL2 0x0b0 +#define QPHY_V4_PCS_TEST_CONTROL3 0x0b4 +#define QPHY_V4_PCS_TEST_CONTROL4 0x0b8 +#define QPHY_V4_PCS_TEST_CONTROL5 0x0bc +#define QPHY_V4_PCS_TEST_CONTROL6 0x0c0 +#define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4 +#define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8 +#define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc +#define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0 +#define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4 +#define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8 +#define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc +#define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0 +#define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4 +#define QPHY_V4_PCS_BIST_CTRL 0x0e8 +#define QPHY_V4_PCS_PRBS_POLY0 0x0ec +#define QPHY_V4_PCS_PRBS_POLY1 0x0f0 +#define QPHY_V4_PCS_FIXED_PAT0 0x0f4 +#define QPHY_V4_PCS_FIXED_PAT1 0x0f8 +#define QPHY_V4_PCS_FIXED_PAT2 0x0fc +#define QPHY_V4_PCS_FIXED_PAT3 0x100 +#define QPHY_V4_PCS_FIXED_PAT4 0x104 +#define QPHY_V4_PCS_FIXED_PAT5 0x108 +#define QPHY_V4_PCS_FIXED_PAT6 0x10c +#define QPHY_V4_PCS_FIXED_PAT7 0x110 +#define QPHY_V4_PCS_FIXED_PAT8 0x114 +#define QPHY_V4_PCS_FIXED_PAT9 0x118 +#define QPHY_V4_PCS_FIXED_PAT10 0x11c +#define QPHY_V4_PCS_FIXED_PAT11 0x120 +#define QPHY_V4_PCS_FIXED_PAT12 0x124 +#define QPHY_V4_PCS_FIXED_PAT13 0x128 +#define QPHY_V4_PCS_FIXED_PAT14 0x12c +#define QPHY_V4_PCS_FIXED_PAT15 0x130 +#define QPHY_V4_PCS_TXMGN_CONFIG 0x134 +#define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138 +#define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c +#define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140 +#define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144 +#define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148 +#define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c +#define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150 +#define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154 +#define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158 +#define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c +#define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160 +#define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164 +#define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168 +#define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c +#define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170 +#define QPHY_V4_PCS_G3S2_POST_GAIN 0x174 +#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178 +#define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c +#define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180 +#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184 +#define QPHY_V4_PCS_RX_SIGDET_LVL 0x188 +#define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c +#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 +#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 +#define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198 +#define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c +#define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0 +#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 +#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 +#define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac +#define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0 +#define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4 +#define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8 +#define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc +#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0 +#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4 +#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8 +#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc +#define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0 +#define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4 +#define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8 +#define QPHY_V4_PCS_EQ_CONFIG1 0x1dc +#define QPHY_V4_PCS_EQ_CONFIG2 0x1e0 +#define QPHY_V4_PCS_EQ_CONFIG3 0x1e4 +#define QPHY_V4_PCS_EQ_CONFIG4 0x1e8 +#define QPHY_V4_PCS_EQ_CONFIG5 0x1ec + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h new file mode 100644 index 000000000000..08c3dd115488 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_V4_20_H_ +#define QCOM_PHY_QMP_PCS_V4_20_H_ + +/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */ +#define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188 +#define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8 +#define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0 +#define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h new file mode 100644 index 000000000000..61a44519f969 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_V5_H_ +#define QCOM_PHY_QMP_PCS_V5_H_ + +/* Only for QMP V5 PHY - USB/PCIe PCS registers */ +#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc +#define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170 +#define QPHY_V5_PCS_RX_SIGDET_LVL 0x188 +#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198 +#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0 +#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h new file mode 100644 index 000000000000..c0bd54e0e7b6 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h @@ -0,0 +1,111 @@ + +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_COM_V3_H_ +#define QCOM_PHY_QMP_QSERDES_COM_V3_H_ + +/* Only for QMP V3 PHY - QSERDES COM registers */ +#define QSERDES_V3_COM_ATB_SEL1 0x000 +#define QSERDES_V3_COM_ATB_SEL2 0x004 +#define QSERDES_V3_COM_FREQ_UPDATE 0x008 +#define QSERDES_V3_COM_BG_TIMER 0x00c +#define QSERDES_V3_COM_SSC_EN_CENTER 0x010 +#define QSERDES_V3_COM_SSC_ADJ_PER1 0x014 +#define QSERDES_V3_COM_SSC_ADJ_PER2 0x018 +#define QSERDES_V3_COM_SSC_PER1 0x01c +#define QSERDES_V3_COM_SSC_PER2 0x020 +#define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024 +#define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028 +#define QSERDES_V3_COM_POST_DIV 0x02c +#define QSERDES_V3_COM_POST_DIV_MUX 0x030 +#define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034 +#define QSERDES_V3_COM_CLK_ENABLE1 0x038 +#define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c +#define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040 +#define QSERDES_V3_COM_PLL_EN 0x044 +#define QSERDES_V3_COM_PLL_IVCO 0x048 +#define QSERDES_V3_COM_CMN_IETRIM 0x04c +#define QSERDES_V3_COM_CMN_IPTRIM 0x050 +#define QSERDES_V3_COM_EP_CLOCK_DETECT_CTR 0x054 +#define QSERDES_V3_COM_SYSCLK_DET_COMP_STATUS 0x058 +#define QSERDES_V3_COM_CLK_EP_DIV 0x05c +#define QSERDES_V3_COM_CP_CTRL_MODE0 0x060 +#define QSERDES_V3_COM_CP_CTRL_MODE1 0x064 +#define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068 +#define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c +#define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070 +#define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074 +#define QSERDES_V3_COM_PLL_CNTRL 0x078 +#define QSERDES_V3_COM_BIAS_EN_CTRL_BY_PSM 0x07c +#define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080 +#define QSERDES_V3_COM_CML_SYSCLK_SEL 0x084 +#define QSERDES_V3_COM_RESETSM_CNTRL 0x088 +#define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c +#define QSERDES_V3_COM_LOCK_CMP_EN 0x090 +#define QSERDES_V3_COM_LOCK_CMP_CFG 0x094 +#define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098 +#define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c +#define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0 +#define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4 +#define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8 +#define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac +#define QSERDES_V3_COM_DEC_START_MODE0 0x0b0 +#define QSERDES_V3_COM_DEC_START_MODE1 0x0b4 +#define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8 +#define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc +#define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0 +#define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4 +#define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8 +#define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc +#define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0 +#define QSERDES_V3_COM_INTEGLOOP_EN 0x0d4 +#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8 +#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc +#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0 +#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4 +#define QSERDES_V3_COM_VCOCAL_DEADMAN_CTRL 0x0e8 +#define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec +#define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0 +#define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4 +#define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8 +#define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc +#define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100 +#define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104 +#define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108 +#define QSERDES_V3_COM_VCO_TUNE_MINVAL1 0x10c +#define QSERDES_V3_COM_VCO_TUNE_MINVAL2 0x110 +#define QSERDES_V3_COM_VCO_TUNE_MAXVAL1 0x114 +#define QSERDES_V3_COM_VCO_TUNE_MAXVAL2 0x118 +#define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c +#define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120 +#define QSERDES_V3_COM_CMN_STATUS 0x124 +#define QSERDES_V3_COM_RESET_SM_STATUS 0x128 +#define QSERDES_V3_COM_RESTRIM_CODE_STATUS 0x12c +#define QSERDES_V3_COM_PLLCAL_CODE1_STATUS 0x130 +#define QSERDES_V3_COM_PLLCAL_CODE2_STATUS 0x134 +#define QSERDES_V3_COM_CLK_SELECT 0x138 +#define QSERDES_V3_COM_HSCLK_SEL 0x13c +#define QSERDES_V3_COM_INTEGLOOP_BINCODE_STATUS 0x140 +#define QSERDES_V3_COM_PLL_ANALOG 0x144 +#define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148 +#define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c +#define QSERDES_V3_COM_SW_RESET 0x150 +#define QSERDES_V3_COM_CORE_CLK_EN 0x154 +#define QSERDES_V3_COM_C_READY_STATUS 0x158 +#define QSERDES_V3_COM_CMN_CONFIG 0x15c +#define QSERDES_V3_COM_CMN_RATE_OVERRIDE 0x160 +#define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164 +#define QSERDES_V3_COM_DEBUG_BUS0 0x168 +#define QSERDES_V3_COM_DEBUG_BUS1 0x16c +#define QSERDES_V3_COM_DEBUG_BUS2 0x170 +#define QSERDES_V3_COM_DEBUG_BUS3 0x174 +#define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178 +#define QSERDES_V3_COM_CMN_MISC1 0x17c +#define QSERDES_V3_COM_CMN_MISC2 0x180 +#define QSERDES_V3_COM_CMN_MODE 0x184 +#define QSERDES_V3_COM_CMN_VREG_SEL 0x188 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v4.h new file mode 100644 index 000000000000..b0e3298d990d --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v4.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_COM_V4_H_ +#define QCOM_PHY_QMP_QSERDES_COM_V4_H_ + +/* Only for QMP V4 PHY - QSERDES COM registers */ +#define QSERDES_V4_COM_ATB_SEL1 0x000 +#define QSERDES_V4_COM_ATB_SEL2 0x004 +#define QSERDES_V4_COM_FREQ_UPDATE 0x008 +#define QSERDES_V4_COM_BG_TIMER 0x00c +#define QSERDES_V4_COM_SSC_EN_CENTER 0x010 +#define QSERDES_V4_COM_SSC_ADJ_PER1 0x014 +#define QSERDES_V4_COM_SSC_ADJ_PER2 0x018 +#define QSERDES_V4_COM_SSC_PER1 0x01c +#define QSERDES_V4_COM_SSC_PER2 0x020 +#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024 +#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028 +#define QSERDES_V4_COM_SSC_STEP_SIZE3_MODE0 0x02c +#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030 +#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034 +#define QSERDES_V4_COM_SSC_STEP_SIZE3_MODE1 0x038 +#define QSERDES_V4_COM_POST_DIV 0x03c +#define QSERDES_V4_COM_POST_DIV_MUX 0x040 +#define QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN 0x044 +#define QSERDES_V4_COM_CLK_ENABLE1 0x048 +#define QSERDES_V4_COM_SYS_CLK_CTRL 0x04c +#define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050 +#define QSERDES_V4_COM_PLL_EN 0x054 +#define QSERDES_V4_COM_PLL_IVCO 0x058 +#define QSERDES_V4_COM_CMN_IETRIM 0x05c +#define QSERDES_V4_COM_CMN_IPTRIM 0x060 +#define QSERDES_V4_COM_EP_CLOCK_DETECT_CTRL 0x064 +#define QSERDES_V4_COM_SYSCLK_DET_COMP_STATUS 0x068 +#define QSERDES_V4_COM_CLK_EP_DIV_MODE0 0x06c +#define QSERDES_V4_COM_CLK_EP_DIV_MODE1 0x070 +#define QSERDES_V4_COM_CP_CTRL_MODE0 0x074 +#define QSERDES_V4_COM_CP_CTRL_MODE1 0x078 +#define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c +#define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080 +#define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084 +#define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088 +#define QSERDES_V4_COM_PLL_CNTRL 0x08c +#define QSERDES_V4_COM_BIAS_EN_CTRL_BY_PSM 0x090 +#define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094 +#define QSERDES_V4_COM_CML_SYSCLK_SEL 0x098 +#define QSERDES_V4_COM_RESETSM_CNTRL 0x09c +#define QSERDES_V4_COM_RESETSM_CNTRL2 0x0a0 +#define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4 +#define QSERDES_V4_COM_LOCK_CMP_CFG 0x0a8 +#define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac +#define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 +#define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 +#define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8 +#define QSERDES_V4_COM_DEC_START_MODE0 0x0bc +#define QSERDES_V4_COM_DEC_START_MSB_MODE0 0x0c0 +#define QSERDES_V4_COM_DEC_START_MODE1 0x0c4 +#define QSERDES_V4_COM_DEC_START_MSB_MODE1 0x0c8 +#define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc +#define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0 +#define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4 +#define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8 +#define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc +#define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0 +#define QSERDES_V4_COM_INTEGLOOP_INITVAL 0x0e4 +#define QSERDES_V4_COM_INTEGLOOP_EN 0x0e8 +#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0 0x0ec +#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0 0x0f0 +#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1 0x0f4 +#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1 0x0f8 +#define QSERDES_V4_COM_INTEGLOOP_P_PATH_GAIN0 0x0fc +#define QSERDES_V4_COM_INTEGLOOP_P_PATH_GAIN1 0x100 +#define QSERDES_V4_COM_VCOCAL_DEADMAN_CTRL 0x104 +#define QSERDES_V4_COM_VCO_TUNE_CTRL 0x108 +#define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c +#define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110 +#define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114 +#define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118 +#define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c +#define QSERDES_V4_COM_VCO_TUNE_INITVAL1 0x120 +#define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124 +#define QSERDES_V4_COM_VCO_TUNE_MINVAL1 0x128 +#define QSERDES_V4_COM_VCO_TUNE_MINVAL2 0x12c +#define QSERDES_V4_COM_VCO_TUNE_MAXVAL1 0x130 +#define QSERDES_V4_COM_VCO_TUNE_MAXVAL2 0x134 +#define QSERDES_V4_COM_VCO_TUNE_TIMER1 0x138 +#define QSERDES_V4_COM_VCO_TUNE_TIMER2 0x13c +#define QSERDES_V4_COM_CMN_STATUS 0x140 +#define QSERDES_V4_COM_RESET_SM_STATUS 0x144 +#define QSERDES_V4_COM_RESTRIM_CODE_STATUS 0x148 +#define QSERDES_V4_COM_PLLCAL_CODE1_STATUS 0x14c +#define QSERDES_V4_COM_PLLCAL_CODE2_STATUS 0x150 +#define QSERDES_V4_COM_CLK_SELECT 0x154 +#define QSERDES_V4_COM_HSCLK_SEL 0x158 +#define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c +#define QSERDES_V4_COM_INTEGLOOP_BINCODE_STATUS 0x160 +#define QSERDES_V4_COM_PLL_ANALOG 0x164 +#define QSERDES_V4_COM_CORECLK_DIV_MODE0 0x168 +#define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c +#define QSERDES_V4_COM_SW_RESET 0x170 +#define QSERDES_V4_COM_CORE_CLK_EN 0x174 +#define QSERDES_V4_COM_C_READY_STATUS 0x178 +#define QSERDES_V4_COM_CMN_CONFIG 0x17c +#define QSERDES_V4_COM_CMN_RATE_OVERRIDE 0x180 +#define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184 +#define QSERDES_V4_COM_DEBUG_BUS0 0x188 +#define QSERDES_V4_COM_DEBUG_BUS1 0x18c +#define QSERDES_V4_COM_DEBUG_BUS2 0x190 +#define QSERDES_V4_COM_DEBUG_BUS3 0x194 +#define QSERDES_V4_COM_DEBUG_BUS_SEL 0x198 +#define QSERDES_V4_COM_CMN_MISC1 0x19c +#define QSERDES_V4_COM_CMN_MISC2 0x1a0 +#define QSERDES_V4_COM_CMN_MODE 0x1a4 +#define QSERDES_V4_COM_VCO_DC_LEVEL_CTRL 0x1a8 +#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac +#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 +#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 +#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 +#define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h new file mode 100644 index 000000000000..c8afdf7bc1ee --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_COM_V5_H_ +#define QCOM_PHY_QMP_QSERDES_COM_V5_H_ + +/* Only for QMP V5 PHY - QSERDES COM registers */ +#define QSERDES_V5_COM_ATB_SEL1 0x000 +#define QSERDES_V5_COM_ATB_SEL2 0x004 +#define QSERDES_V5_COM_FREQ_UPDATE 0x008 +#define QSERDES_V5_COM_BG_TIMER 0x00c +#define QSERDES_V5_COM_SSC_EN_CENTER 0x010 +#define QSERDES_V5_COM_SSC_ADJ_PER1 0x014 +#define QSERDES_V5_COM_SSC_ADJ_PER2 0x018 +#define QSERDES_V5_COM_SSC_PER1 0x01c +#define QSERDES_V5_COM_SSC_PER2 0x020 +#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024 +#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028 +#define QSERDES_V5_COM_SSC_STEP_SIZE3_MODE0 0x02c +#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030 +#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034 +#define QSERDES_V5_COM_SSC_STEP_SIZE3_MODE1 0x038 +#define QSERDES_V5_COM_POST_DIV 0x03c +#define QSERDES_V5_COM_POST_DIV_MUX 0x040 +#define QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN 0x044 +#define QSERDES_V5_COM_CLK_ENABLE1 0x048 +#define QSERDES_V5_COM_SYS_CLK_CTRL 0x04c +#define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050 +#define QSERDES_V5_COM_PLL_EN 0x054 +#define QSERDES_V5_COM_PLL_IVCO 0x058 +#define QSERDES_V5_COM_CMN_IETRIM 0x05c +#define QSERDES_V5_COM_CMN_IPTRIM 0x060 +#define QSERDES_V5_COM_EP_CLOCK_DETECT_CTRL 0x064 +#define QSERDES_V5_COM_SYSCLK_DET_COMP_STATUS 0x068 +#define QSERDES_V5_COM_CLK_EP_DIV_MODE0 0x06c +#define QSERDES_V5_COM_CLK_EP_DIV_MODE1 0x070 +#define QSERDES_V5_COM_CP_CTRL_MODE0 0x074 +#define QSERDES_V5_COM_CP_CTRL_MODE1 0x078 +#define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c +#define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080 +#define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084 +#define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088 +#define QSERDES_V5_COM_PLL_CNTRL 0x08c +#define QSERDES_V5_COM_BIAS_EN_CTRL_BY_PSM 0x090 +#define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094 +#define QSERDES_V5_COM_CML_SYSCLK_SEL 0x098 +#define QSERDES_V5_COM_RESETSM_CNTRL 0x09c +#define QSERDES_V5_COM_RESETSM_CNTRL2 0x0a0 +#define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4 +#define QSERDES_V5_COM_LOCK_CMP_CFG 0x0a8 +#define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac +#define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0 +#define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4 +#define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8 +#define QSERDES_V5_COM_DEC_START_MODE0 0x0bc +#define QSERDES_V5_COM_DEC_START_MSB_MODE0 0x0c0 +#define QSERDES_V5_COM_DEC_START_MODE1 0x0c4 +#define QSERDES_V5_COM_DEC_START_MSB_MODE1 0x0c8 +#define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc +#define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0 +#define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4 +#define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8 +#define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc +#define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0 +#define QSERDES_V5_COM_INTEGLOOP_INITVAL 0x0e4 +#define QSERDES_V5_COM_INTEGLOOP_EN 0x0e8 +#define QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0 0x0ec +#define QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0 0x0f0 +#define QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1 0x0f4 +#define QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1 0x0f8 +#define QSERDES_V5_COM_INTEGLOOP_P_PATH_GAIN0 0x0fc +#define QSERDES_V5_COM_INTEGLOOP_P_PATH_GAIN1 0x100 +#define QSERDES_V5_COM_VCOCAL_DEADMAN_CTRL 0x104 +#define QSERDES_V5_COM_VCO_TUNE_CTRL 0x108 +#define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c +#define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110 +#define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114 +#define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118 +#define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c +#define QSERDES_V5_COM_VCO_TUNE_INITVAL1 0x120 +#define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124 +#define QSERDES_V5_COM_VCO_TUNE_MINVAL1 0x128 +#define QSERDES_V5_COM_VCO_TUNE_MINVAL2 0x12c +#define QSERDES_V5_COM_VCO_TUNE_MAXVAL1 0x130 +#define QSERDES_V5_COM_VCO_TUNE_MAXVAL2 0x134 +#define QSERDES_V5_COM_VCO_TUNE_TIMER1 0x138 +#define QSERDES_V5_COM_VCO_TUNE_TIMER2 0x13c +#define QSERDES_V5_COM_CMN_STATUS 0x140 +#define QSERDES_V5_COM_RESET_SM_STATUS 0x144 +#define QSERDES_V5_COM_RESTRIM_CODE_STATUS 0x148 +#define QSERDES_V5_COM_PLLCAL_CODE1_STATUS 0x14c +#define QSERDES_V5_COM_PLLCAL_CODE2_STATUS 0x150 +#define QSERDES_V5_COM_CLK_SELECT 0x154 +#define QSERDES_V5_COM_HSCLK_SEL 0x158 +#define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c +#define QSERDES_V5_COM_INTEGLOOP_BINCODE_STATUS 0x160 +#define QSERDES_V5_COM_PLL_ANALOG 0x164 +#define QSERDES_V5_COM_CORECLK_DIV_MODE0 0x168 +#define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c +#define QSERDES_V5_COM_SW_RESET 0x170 +#define QSERDES_V5_COM_CORE_CLK_EN 0x174 +#define QSERDES_V5_COM_C_READY_STATUS 0x178 +#define QSERDES_V5_COM_CMN_CONFIG 0x17c +#define QSERDES_V5_COM_CMN_RATE_OVERRIDE 0x180 +#define QSERDES_V5_COM_SVS_MODE_CLK_SEL 0x184 +#define QSERDES_V5_COM_DEBUG_BUS0 0x188 +#define QSERDES_V5_COM_DEBUG_BUS1 0x18c +#define QSERDES_V5_COM_DEBUG_BUS2 0x190 +#define QSERDES_V5_COM_DEBUG_BUS3 0x194 +#define QSERDES_V5_COM_DEBUG_BUS_SEL 0x198 +#define QSERDES_V5_COM_CMN_MISC1 0x19c +#define QSERDES_V5_COM_CMN_MODE 0x1a0 +#define QSERDES_V5_COM_CMN_MODE_CONTD 0x1a4 +#define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL 0x1a8 +#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac +#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 +#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 +#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 +#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc +#define QSERDES_V5_COM_RESERVED_1 0x1c0 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h new file mode 100644 index 000000000000..fbaf6ef467f8 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_COM_H_ +#define QCOM_PHY_QMP_QSERDES_COM_H_ + +/* Only for QMP V2 PHY - QSERDES COM registers */ +#define QSERDES_COM_ATB_SEL1 0x000 +#define QSERDES_COM_ATB_SEL2 0x004 +#define QSERDES_COM_FREQ_UPDATE 0x008 +#define QSERDES_COM_BG_TIMER 0x00c +#define QSERDES_COM_SSC_EN_CENTER 0x010 +#define QSERDES_COM_SSC_ADJ_PER1 0x014 +#define QSERDES_COM_SSC_ADJ_PER2 0x018 +#define QSERDES_COM_SSC_PER1 0x01c +#define QSERDES_COM_SSC_PER2 0x020 +#define QSERDES_COM_SSC_STEP_SIZE1 0x024 +#define QSERDES_COM_SSC_STEP_SIZE2 0x028 +#define QSERDES_COM_POST_DIV 0x02c +#define QSERDES_COM_POST_DIV_MUX 0x030 +#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034 +#define QSERDES_COM_CLK_ENABLE1 0x038 +#define QSERDES_COM_SYS_CLK_CTRL 0x03c +#define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040 +#define QSERDES_COM_PLL_EN 0x044 +#define QSERDES_COM_PLL_IVCO 0x048 +#define QSERDES_COM_LOCK_CMP1_MODE0 0x04c +#define QSERDES_COM_LOCK_CMP2_MODE0 0x050 +#define QSERDES_COM_LOCK_CMP3_MODE0 0x054 +#define QSERDES_COM_LOCK_CMP1_MODE1 0x058 +#define QSERDES_COM_LOCK_CMP2_MODE1 0x05c +#define QSERDES_COM_LOCK_CMP3_MODE1 0x060 +#define QSERDES_COM_LOCK_CMP1_MODE2 0x064 +#define QSERDES_COM_CMN_RSVD0 0x064 +#define QSERDES_COM_LOCK_CMP2_MODE2 0x068 +#define QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x068 +#define QSERDES_COM_LOCK_CMP3_MODE2 0x06c +#define QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x06c +#define QSERDES_COM_BG_TRIM 0x070 +#define QSERDES_COM_CLK_EP_DIV 0x074 +#define QSERDES_COM_CP_CTRL_MODE0 0x078 +#define QSERDES_COM_CP_CTRL_MODE1 0x07c +#define QSERDES_COM_CP_CTRL_MODE2 0x080 +#define QSERDES_COM_CMN_RSVD1 0x080 +#define QSERDES_COM_PLL_RCTRL_MODE0 0x084 +#define QSERDES_COM_PLL_RCTRL_MODE1 0x088 +#define QSERDES_COM_PLL_RCTRL_MODE2 0x08c +#define QSERDES_COM_CMN_RSVD2 0x08c +#define QSERDES_COM_PLL_CCTRL_MODE0 0x090 +#define QSERDES_COM_PLL_CCTRL_MODE1 0x094 +#define QSERDES_COM_PLL_CCTRL_MODE2 0x098 +#define QSERDES_COM_CMN_RSVD3 0x098 +#define QSERDES_COM_PLL_CNTRL 0x09c +#define QSERDES_COM_PHASE_SEL_CTRL 0x0a0 +#define QSERDES_COM_PHASE_SEL_DC 0x0a4 +#define QSERDES_COM_CORE_CLK_IN_SYNC_SEL 0x0a8 +#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8 +#define QSERDES_COM_SYSCLK_EN_SEL 0x0ac +#define QSERDES_COM_CML_SYSCLK_SEL 0x0b0 +#define QSERDES_COM_RESETSM_CNTRL 0x0b4 +#define QSERDES_COM_RESETSM_CNTRL2 0x0b8 +#define QSERDES_COM_RESTRIM_CTRL 0x0bc +#define QSERDES_COM_RESTRIM_CTRL2 0x0c0 +#define QSERDES_COM_RESCODE_DIV_NUM 0x0c4 +#define QSERDES_COM_LOCK_CMP_EN 0x0c8 +#define QSERDES_COM_LOCK_CMP_CFG 0x0cc +#define QSERDES_COM_DEC_START_MODE0 0x0d0 +#define QSERDES_COM_DEC_START_MODE1 0x0d4 +#define QSERDES_COM_DEC_START_MODE2 0x0d8 +#define QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x0d8 +#define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc +#define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0 +#define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4 +#define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8 +#define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec +#define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0 +#define QSERDES_COM_DIV_FRAC_START1_MODE2 0x0f4 +#define QSERDES_COM_VCO_TUNE_MINVAL1 0x0f4 +#define QSERDES_COM_DIV_FRAC_START2_MODE2 0x0f8 +#define QSERDES_COM_VCO_TUNE_MINVAL2 0x0f8 +#define QSERDES_COM_DIV_FRAC_START3_MODE2 0x0fc +#define QSERDES_COM_CMN_RSVD4 0x0fc +#define QSERDES_COM_INTEGLOOP_INITVAL 0x100 +#define QSERDES_COM_INTEGLOOP_EN 0x104 +#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108 +#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c +#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110 +#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114 +#define QSERDES_COM_INTEGLOOP_GAIN0_MODE2 0x118 +#define QSERDES_COM_VCO_TUNE_MAXVAL1 0x118 +#define QSERDES_COM_INTEGLOOP_GAIN1_MODE2 0x11c +#define QSERDES_COM_VCO_TUNE_MAXVAL2 0x11c +#define QSERDES_COM_RES_TRIM_CONTROL2 0x120 +#define QSERDES_COM_VCO_TUNE_CTRL 0x124 +#define QSERDES_COM_VCO_TUNE_MAP 0x128 +#define QSERDES_COM_VCO_TUNE1_MODE0 0x12c +#define QSERDES_COM_VCO_TUNE2_MODE0 0x130 +#define QSERDES_COM_VCO_TUNE1_MODE1 0x134 +#define QSERDES_COM_VCO_TUNE2_MODE1 0x138 +#define QSERDES_COM_VCO_TUNE1_MODE2 0x13c +#define QSERDES_COM_VCO_TUNE_INITVAL1 0x13c +#define QSERDES_COM_VCO_TUNE2_MODE2 0x140 +#define QSERDES_COM_VCO_TUNE_INITVAL2 0x140 +#define QSERDES_COM_VCO_TUNE_TIMER1 0x144 +#define QSERDES_COM_VCO_TUNE_TIMER2 0x148 +#define QSERDES_COM_SAR 0x14c +#define QSERDES_COM_SAR_CLK 0x150 +#define QSERDES_COM_SAR_CODE_OUT_STATUS 0x154 +#define QSERDES_COM_SAR_CODE_READY_STATUS 0x158 +#define QSERDES_COM_CMN_STATUS 0x15c +#define QSERDES_COM_RESET_SM_STATUS 0x160 +#define QSERDES_COM_RESTRIM_CODE_STATUS 0x164 +#define QSERDES_COM_PLLCAL_CODE1_STATUS 0x168 +#define QSERDES_COM_PLLCAL_CODE2_STATUS 0x16c +#define QSERDES_COM_BG_CTRL 0x170 +#define QSERDES_COM_CLK_SELECT 0x174 +#define QSERDES_COM_HSCLK_SEL 0x178 +#define QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x17c +#define QSERDES_COM_PLL_ANALOG 0x180 +#define QSERDES_COM_CORECLK_DIV 0x184 +#define QSERDES_COM_SW_RESET 0x188 +#define QSERDES_COM_CORE_CLK_EN 0x18c +#define QSERDES_COM_C_READY_STATUS 0x190 +#define QSERDES_COM_CMN_CONFIG 0x194 +#define QSERDES_COM_CMN_RATE_OVERRIDE 0x198 +#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c +#define QSERDES_COM_DEBUG_BUS0 0x1a0 +#define QSERDES_COM_DEBUG_BUS1 0x1a4 +#define QSERDES_COM_DEBUG_BUS2 0x1a8 +#define QSERDES_COM_DEBUG_BUS3 0x1ac +#define QSERDES_COM_DEBUG_BUS_SEL 0x1b0 +#define QSERDES_COM_CMN_MISC1 0x1b4 +#define QSERDES_COM_CMN_MISC2 0x1b8 +#define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc +#define QSERDES_COM_CORECLK_DIV_MODE2 0x1c0 +#define QSERDES_COM_CMN_RSVD5 0x1c0 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h new file mode 100644 index 000000000000..ad326e301a3a --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_PLL_H_ +#define QCOM_PHY_QMP_QSERDES_PLL_H_ + +/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */ +#define QSERDES_PLL_BG_TIMER 0x00c +#define QSERDES_PLL_SSC_PER1 0x01c +#define QSERDES_PLL_SSC_PER2 0x020 +#define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024 +#define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028 +#define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c +#define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030 +#define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c +#define QSERDES_PLL_CLK_ENABLE1 0x040 +#define QSERDES_PLL_SYS_CLK_CTRL 0x044 +#define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048 +#define QSERDES_PLL_PLL_IVCO 0x050 +#define QSERDES_PLL_LOCK_CMP1_MODE0 0x054 +#define QSERDES_PLL_LOCK_CMP2_MODE0 0x058 +#define QSERDES_PLL_LOCK_CMP1_MODE1 0x060 +#define QSERDES_PLL_LOCK_CMP2_MODE1 0x064 +#define QSERDES_PLL_BG_TRIM 0x074 +#define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078 +#define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c +#define QSERDES_PLL_CP_CTRL_MODE0 0x080 +#define QSERDES_PLL_CP_CTRL_MODE1 0x084 +#define QSERDES_PLL_PLL_RCTRL_MODE0 0x088 +#define QSERDES_PLL_PLL_RCTRL_MODE1 0x08c +#define QSERDES_PLL_PLL_CCTRL_MODE0 0x090 +#define QSERDES_PLL_PLL_CCTRL_MODE1 0x094 +#define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4 +#define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8 +#define QSERDES_PLL_RESETSM_CNTRL 0x0b0 +#define QSERDES_PLL_LOCK_CMP_EN 0x0c4 +#define QSERDES_PLL_DEC_START_MODE0 0x0cc +#define QSERDES_PLL_DEC_START_MODE1 0x0d0 +#define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8 +#define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc +#define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0 +#define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4 +#define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8 +#define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0ec +#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100 +#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104 +#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108 +#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c +#define QSERDES_PLL_VCO_TUNE_MAP 0x120 +#define QSERDES_PLL_VCO_TUNE1_MODE0 0x124 +#define QSERDES_PLL_VCO_TUNE2_MODE0 0x128 +#define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c +#define QSERDES_PLL_VCO_TUNE2_MODE1 0x130 +#define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c +#define QSERDES_PLL_VCO_TUNE_TIMER2 0x140 +#define QSERDES_PLL_CLK_SELECT 0x16c +#define QSERDES_PLL_HSCLK_SEL 0x170 +#define QSERDES_PLL_CORECLK_DIV 0x17c +#define QSERDES_PLL_CORE_CLK_EN 0x184 +#define QSERDES_PLL_CMN_CONFIG 0x18c +#define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194 +#define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h new file mode 100644 index 000000000000..161e6df30ea8 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V3_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_V3_H_ + +/* Only for QMP V3 PHY - TX registers */ +#define QSERDES_V3_TX_BIST_MODE_LANENO 0x000 +#define QSERDES_V3_TX_CLKBUF_ENABLE 0x008 +#define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c +#define QSERDES_V3_TX_TX_DRV_LVL 0x01c +#define QSERDES_V3_TX_RESET_TSYNC_EN 0x024 +#define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028 +#define QSERDES_V3_TX_TX_BAND 0x02c +#define QSERDES_V3_TX_SLEW_CNTL 0x030 +#define QSERDES_V3_TX_INTERFACE_SELECT 0x034 +#define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c +#define QSERDES_V3_TX_RES_CODE_LANE_RX 0x040 +#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044 +#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048 +#define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058 +#define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN 0x05c +#define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060 +#define QSERDES_V3_TX_TX_POL_INV 0x064 +#define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068 +#define QSERDES_V3_TX_LANE_MODE_1 0x08c +#define QSERDES_V3_TX_LANE_MODE_2 0x090 +#define QSERDES_V3_TX_LANE_MODE_3 0x094 +#define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4 +#define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0 +#define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4 +#define QSERDES_V3_TX_VMODE_CTRL1 0x0f0 + +/* Only for QMP V3 PHY - RX registers */ +#define QSERDES_V3_RX_UCDR_FO_GAIN 0x008 +#define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c +#define QSERDES_V3_RX_UCDR_SO_GAIN 0x014 +#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024 +#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 +#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c +#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030 +#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 +#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c +#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 +#define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044 +#define QSERDES_V3_RX_RX_TERM_BW 0x07c +#define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc +#define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0 +#define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8 +#define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc +#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL1 0x0d0 +#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4 +#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8 +#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc +#define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8 +#define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc +#define QSERDES_V3_RX_SIGDET_ENABLES 0x100 +#define QSERDES_V3_RX_SIGDET_CNTRL 0x104 +#define QSERDES_V3_RX_SIGDET_LVL 0x108 +#define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c +#define QSERDES_V3_RX_RX_BAND 0x110 +#define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c +#define QSERDES_V3_RX_RX_MODE_00 0x164 +#define QSERDES_V3_RX_RX_MODE_01 0x168 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h new file mode 100644 index 000000000000..6ee3bec9ac4a --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h @@ -0,0 +1,233 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V4_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_V4_H_ + +/* Only for QMP V4 PHY - TX registers */ +#define QSERDES_V4_TX_BIST_MODE_LANENO 0x000 +#define QSERDES_V4_TX_BIST_INVERT 0x004 +#define QSERDES_V4_TX_CLKBUF_ENABLE 0x008 +#define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c +#define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010 +#define QSERDES_V4_TX_TX_DRV_LVL 0x014 +#define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018 +#define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c +#define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020 +#define QSERDES_V4_TX_TX_BAND 0x024 +#define QSERDES_V4_TX_SLEW_CNTL 0x028 +#define QSERDES_V4_TX_INTERFACE_SELECT 0x02c +#define QSERDES_V4_TX_LPB_EN 0x030 +#define QSERDES_V4_TX_RES_CODE_LANE_TX 0x034 +#define QSERDES_V4_TX_RES_CODE_LANE_RX 0x038 +#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x03c +#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x040 +#define QSERDES_V4_TX_PERL_LENGTH1 0x044 +#define QSERDES_V4_TX_PERL_LENGTH2 0x048 +#define QSERDES_V4_TX_SERDES_BYP_EN_OUT 0x04c +#define QSERDES_V4_TX_DEBUG_BUS_SEL 0x050 +#define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN 0x054 +#define QSERDES_V4_TX_HIGHZ_DRVR_EN 0x058 +#define QSERDES_V4_TX_TX_POL_INV 0x05c +#define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN 0x060 +#define QSERDES_V4_TX_BIST_PATTERN1 0x064 +#define QSERDES_V4_TX_BIST_PATTERN2 0x068 +#define QSERDES_V4_TX_BIST_PATTERN3 0x06c +#define QSERDES_V4_TX_BIST_PATTERN4 0x070 +#define QSERDES_V4_TX_BIST_PATTERN5 0x074 +#define QSERDES_V4_TX_BIST_PATTERN6 0x078 +#define QSERDES_V4_TX_BIST_PATTERN7 0x07c +#define QSERDES_V4_TX_BIST_PATTERN8 0x080 +#define QSERDES_V4_TX_LANE_MODE_1 0x084 +#define QSERDES_V4_TX_LANE_MODE_2 0x088 +#define QSERDES_V4_TX_LANE_MODE_3 0x08c +#define QSERDES_V4_TX_ATB_SEL1 0x090 +#define QSERDES_V4_TX_ATB_SEL2 0x094 +#define QSERDES_V4_TX_RCV_DETECT_LVL 0x098 +#define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x09c +#define QSERDES_V4_TX_PRBS_SEED1 0x0a0 +#define QSERDES_V4_TX_PRBS_SEED2 0x0a4 +#define QSERDES_V4_TX_PRBS_SEED3 0x0a8 +#define QSERDES_V4_TX_PRBS_SEED4 0x0ac +#define QSERDES_V4_TX_RESET_GEN 0x0b0 +#define QSERDES_V4_TX_RESET_GEN_MUXES 0x0b4 +#define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0x0b8 +#define QSERDES_V4_TX_TX_INTERFACE_MODE 0x0bc +#define QSERDES_V4_TX_PWM_CTRL 0x0c0 +#define QSERDES_V4_TX_PWM_ENCODED_OR_DATA 0x0c4 +#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND2 0x0c8 +#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND2 0x0cc +#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND2 0x0d0 +#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND2 0x0d4 +#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x0d8 +#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x0dc +#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x0e0 +#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x0e4 +#define QSERDES_V4_TX_VMODE_CTRL1 0x0e8 +#define QSERDES_V4_TX_ALOG_OBSV_BUS_CTRL_1 0x0ec +#define QSERDES_V4_TX_BIST_STATUS 0x0f0 +#define QSERDES_V4_TX_BIST_ERROR_COUNT1 0x0f4 +#define QSERDES_V4_TX_BIST_ERROR_COUNT2 0x0f8 +#define QSERDES_V4_TX_ALOG_OBSV_BUS_STATUS_1 0x0fc +#define QSERDES_V4_TX_LANE_DIG_CONFIG 0x100 +#define QSERDES_V4_TX_PI_QEC_CTRL 0x104 +#define QSERDES_V4_TX_PRE_EMPH 0x108 +#define QSERDES_V4_TX_SW_RESET 0x10c +#define QSERDES_V4_TX_DCC_OFFSET 0x110 +#define QSERDES_V4_TX_DIG_BKUP_CTRL 0x114 +#define QSERDES_V4_TX_DEBUG_BUS0 0x118 +#define QSERDES_V4_TX_DEBUG_BUS1 0x11c +#define QSERDES_V4_TX_DEBUG_BUS2 0x120 +#define QSERDES_V4_TX_DEBUG_BUS3 0x124 +#define QSERDES_V4_TX_READ_EQCODE 0x128 +#define QSERDES_V4_TX_READ_OFFSETCODE 0x12c +#define QSERDES_V4_TX_IA_ERROR_COUNTER_LOW 0x130 +#define QSERDES_V4_TX_IA_ERROR_COUNTER_HIGH 0x134 +#define QSERDES_V4_TX_VGA_READ_CODE 0x138 +#define QSERDES_V4_TX_VTH_READ_CODE 0x13c +#define QSERDES_V4_TX_DFE_TAP1_READ_CODE 0x140 +#define QSERDES_V4_TX_DFE_TAP2_READ_CODE 0x144 +#define QSERDES_V4_TX_IDAC_STATUS_I 0x148 +#define QSERDES_V4_TX_IDAC_STATUS_IBAR 0x14c +#define QSERDES_V4_TX_IDAC_STATUS_Q 0x150 +#define QSERDES_V4_TX_IDAC_STATUS_QBAR 0x154 +#define QSERDES_V4_TX_IDAC_STATUS_A 0x158 +#define QSERDES_V4_TX_IDAC_STATUS_ABAR 0x15c +#define QSERDES_V4_TX_IDAC_STATUS_SM_ON 0x160 +#define QSERDES_V4_TX_IDAC_STATUS_CAL_DONE 0x164 +#define QSERDES_V4_TX_IDAC_STATUS_SIGNERROR 0x168 +#define QSERDES_V4_TX_DCC_CAL_STATUS 0x16c + +/* Only for QMP V4 PHY - RX registers */ +#define QSERDES_V4_RX_UCDR_FO_GAIN_HALF 0x000 +#define QSERDES_V4_RX_UCDR_FO_GAIN_QUARTER 0x004 +#define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 +#define QSERDES_V4_RX_UCDR_SO_GAIN_HALF 0x00c +#define QSERDES_V4_RX_UCDR_SO_GAIN_QUARTER 0x010 +#define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 +#define QSERDES_V4_RX_UCDR_SVS_FO_GAIN_HALF 0x018 +#define QSERDES_V4_RX_UCDR_SVS_FO_GAIN_QUARTER 0x01c +#define QSERDES_V4_RX_UCDR_SVS_FO_GAIN 0x020 +#define QSERDES_V4_RX_UCDR_SVS_SO_GAIN_HALF 0x024 +#define QSERDES_V4_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 +#define QSERDES_V4_RX_UCDR_SVS_SO_GAIN 0x02c +#define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030 +#define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 +#define QSERDES_V4_RX_UCDR_FO_TO_SO_DELAY 0x038 +#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c +#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 +#define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044 +#define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048 +#define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c +#define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050 +#define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054 +#define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058 +#define QSERDES_V4_RX_AUX_CONTROL 0x05c +#define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060 +#define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064 +#define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068 +#define QSERDES_V4_RX_AC_JTAG_INITP 0x06c +#define QSERDES_V4_RX_AC_JTAG_INITN 0x070 +#define QSERDES_V4_RX_AC_JTAG_LVL 0x074 +#define QSERDES_V4_RX_AC_JTAG_MODE 0x078 +#define QSERDES_V4_RX_AC_JTAG_RESET 0x07c +#define QSERDES_V4_RX_RX_TERM_BW 0x080 +#define QSERDES_V4_RX_RX_RCVR_IQ_EN 0x084 +#define QSERDES_V4_RX_RX_IDAC_I_DC_OFFSETS 0x088 +#define QSERDES_V4_RX_RX_IDAC_IBAR_DC_OFFSETS 0x08c +#define QSERDES_V4_RX_RX_IDAC_Q_DC_OFFSETS 0x090 +#define QSERDES_V4_RX_RX_IDAC_QBAR_DC_OFFSETS 0x094 +#define QSERDES_V4_RX_RX_IDAC_A_DC_OFFSETS 0x098 +#define QSERDES_V4_RX_RX_IDAC_ABAR_DC_OFFSETS 0x09c +#define QSERDES_V4_RX_RX_IDAC_EN 0x0a0 +#define QSERDES_V4_RX_RX_IDAC_ENABLES 0x0a4 +#define QSERDES_V4_RX_RX_IDAC_SIGN 0x0a8 +#define QSERDES_V4_RX_RX_HIGHZ_HIGHRATE 0x0ac +#define QSERDES_V4_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0b0 +#define QSERDES_V4_RX_DFE_1 0x0b4 +#define QSERDES_V4_RX_DFE_2 0x0b8 +#define QSERDES_V4_RX_DFE_3 0x0bc +#define QSERDES_V4_RX_DFE_4 0x0c0 +#define QSERDES_V4_RX_TX_ADAPT_PRE_THRESH1 0x0c4 +#define QSERDES_V4_RX_TX_ADAPT_PRE_THRESH2 0x0c8 +#define QSERDES_V4_RX_TX_ADAPT_POST_THRESH 0x0cc +#define QSERDES_V4_RX_TX_ADAPT_MAIN_THRESH 0x0d0 +#define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4 +#define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8 +#define QSERDES_V4_RX_GM_CAL 0x0dc +#define QSERDES_V4_RX_RX_VGA_GAIN2_LSB 0x0e0 +#define QSERDES_V4_RX_RX_VGA_GAIN2_MSB 0x0e4 +#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 +#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec +#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 +#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 +#define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8 +#define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc +#define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100 +#define QSERDES_V4_RX_RX_IDAC_ACCUMULATOR 0x104 +#define QSERDES_V4_RX_RX_EQ_OFFSET_LSB 0x108 +#define QSERDES_V4_RX_RX_EQ_OFFSET_MSB 0x10c +#define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 +#define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 +#define QSERDES_V4_RX_SIGDET_ENABLES 0x118 +#define QSERDES_V4_RX_SIGDET_CNTRL 0x11c +#define QSERDES_V4_RX_SIGDET_LVL 0x120 +#define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124 +#define QSERDES_V4_RX_RX_BAND 0x128 +#define QSERDES_V4_RX_CDR_FREEZE_UP_DN 0x12c +#define QSERDES_V4_RX_CDR_RESET_OVERRIDE 0x130 +#define QSERDES_V4_RX_RX_INTERFACE_MODE 0x134 +#define QSERDES_V4_RX_JITTER_GEN_MODE 0x138 +#define QSERDES_V4_RX_SJ_AMP1 0x13c +#define QSERDES_V4_RX_SJ_AMP2 0x140 +#define QSERDES_V4_RX_SJ_PER1 0x144 +#define QSERDES_V4_RX_SJ_PER2 0x148 +#define QSERDES_V4_RX_PPM_OFFSET1 0x14c +#define QSERDES_V4_RX_PPM_OFFSET2 0x150 +#define QSERDES_V4_RX_SIGN_PPM_PERIOD1 0x154 +#define QSERDES_V4_RX_SIGN_PPM_PERIOD2 0x158 +#define QSERDES_V4_RX_RX_PWM_ENABLE_AND_DATA 0x15c +#define QSERDES_V4_RX_RX_PWM_GEAR1_TIMEOUT_COUNT 0x160 +#define QSERDES_V4_RX_RX_PWM_GEAR2_TIMEOUT_COUNT 0x164 +#define QSERDES_V4_RX_RX_PWM_GEAR3_TIMEOUT_COUNT 0x168 +#define QSERDES_V4_RX_RX_PWM_GEAR4_TIMEOUT_COUNT 0x16c +#define QSERDES_V4_RX_RX_MODE_00_LOW 0x170 +#define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174 +#define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178 +#define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c +#define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180 +#define QSERDES_V4_RX_RX_MODE_01_LOW 0x184 +#define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188 +#define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c +#define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190 +#define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194 +#define QSERDES_V4_RX_RX_MODE_10_LOW 0x198 +#define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c +#define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0 +#define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4 +#define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8 +#define QSERDES_V4_RX_PHPRE_CTRL 0x1ac +#define QSERDES_V4_RX_PHPRE_INITVAL 0x1b0 +#define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4 +#define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8 +#define QSERDES_V4_RX_DCC_CTRL1 0x1bc +#define QSERDES_V4_RX_DCC_CTRL2 0x1c0 +#define QSERDES_V4_RX_VTH_CODE 0x1c4 +#define QSERDES_V4_RX_VTH_MIN_THRESH 0x1c8 +#define QSERDES_V4_RX_VTH_MAX_THRESH 0x1cc +#define QSERDES_V4_RX_ALOG_OBSV_BUS_CTRL_1 0x1d0 +#define QSERDES_V4_RX_PI_CTRL1 0x1d4 +#define QSERDES_V4_RX_PI_CTRL2 0x1d8 +#define QSERDES_V4_RX_PI_QUAD 0x1dc +#define QSERDES_V4_RX_IDATA1 0x1e0 +#define QSERDES_V4_RX_IDATA2 0x1e4 +#define QSERDES_V4_RX_AUX_DATA1 0x1e8 +#define QSERDES_V4_RX_AUX_DATA2 0x1ec +#define QSERDES_V4_RX_AC_JTAG_OUTP 0x1f0 +#define QSERDES_V4_RX_AC_JTAG_OUTN 0x1f4 +#define QSERDES_V4_RX_RX_SIGDET 0x1f8 +#define QSERDES_V4_RX_ALOG_OBSV_BUS_STATUS_1 0x1fc + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4_20.h new file mode 100644 index 000000000000..114570f3017f --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4_20.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V4_20_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_V4_20_H_ + +/* Only for QMP V4_20 PHY - TX registers */ +#define QSERDES_V4_20_TX_LANE_MODE_1 0x88 +#define QSERDES_V4_20_TX_LANE_MODE_2 0x8c +#define QSERDES_V4_20_TX_LANE_MODE_3 0x90 +#define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4 +#define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0 + +/* Only for QMP V4_20 PHY - RX registers */ +#define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008 +#define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058 +#define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac +#define QSERDES_V4_20_RX_DFE_3 0x110 +#define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134 +#define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138 +#define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150 +#define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178 +#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8 +#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc +#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0 +#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4 +#define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8 +#define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc +#define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0 +#define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4 +#define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8 +#define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec +#define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0 +#define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4 +#define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8 +#define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc +#define QSERDES_V4_20_RX_PHPRE_CTRL 0x200 +#define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c +#define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h new file mode 100644 index 000000000000..fe8f3e330d09 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h @@ -0,0 +1,231 @@ + +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_V5_H_ + +/* Only for QMP V5 PHY - TX registers */ +#define QSERDES_V5_TX_BIST_MODE_LANENO 0x000 +#define QSERDES_V5_TX_BIST_INVERT 0x004 +#define QSERDES_V5_TX_CLKBUF_ENABLE 0x008 +#define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c +#define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010 +#define QSERDES_V5_TX_TX_DRV_LVL 0x014 +#define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018 +#define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c +#define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020 +#define QSERDES_V5_TX_TX_BAND 0x024 +#define QSERDES_V5_TX_SLEW_CNTL 0x028 +#define QSERDES_V5_TX_INTERFACE_SELECT 0x02c +#define QSERDES_V5_TX_LPB_EN 0x030 +#define QSERDES_V5_TX_RES_CODE_LANE_TX 0x034 +#define QSERDES_V5_TX_RES_CODE_LANE_RX 0x038 +#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x03c +#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x040 +#define QSERDES_V5_TX_PERL_LENGTH1 0x044 +#define QSERDES_V5_TX_PERL_LENGTH2 0x048 +#define QSERDES_V5_TX_SERDES_BYP_EN_OUT 0x04c +#define QSERDES_V5_TX_DEBUG_BUS_SEL 0x050 +#define QSERDES_V5_TX_TRANSCEIVER_BIAS_EN 0x054 +#define QSERDES_V5_TX_HIGHZ_DRVR_EN 0x058 +#define QSERDES_V5_TX_TX_POL_INV 0x05c +#define QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN 0x060 +#define QSERDES_V5_TX_BIST_PATTERN1 0x064 +#define QSERDES_V5_TX_BIST_PATTERN2 0x068 +#define QSERDES_V5_TX_BIST_PATTERN3 0x06c +#define QSERDES_V5_TX_BIST_PATTERN4 0x070 +#define QSERDES_V5_TX_BIST_PATTERN5 0x074 +#define QSERDES_V5_TX_BIST_PATTERN6 0x078 +#define QSERDES_V5_TX_BIST_PATTERN7 0x07c +#define QSERDES_V5_TX_BIST_PATTERN8 0x080 +#define QSERDES_V5_TX_LANE_MODE_1 0x084 +#define QSERDES_V5_TX_LANE_MODE_2 0x088 +#define QSERDES_V5_TX_LANE_MODE_3 0x08c +#define QSERDES_V5_TX_LANE_MODE_4 0x090 +#define QSERDES_V5_TX_LANE_MODE_5 0x094 +#define QSERDES_V5_TX_ATB_SEL1 0x098 +#define QSERDES_V5_TX_ATB_SEL2 0x09c +#define QSERDES_V5_TX_RCV_DETECT_LVL 0x0a0 +#define QSERDES_V5_TX_RCV_DETECT_LVL_2 0x0a4 +#define QSERDES_V5_TX_PRBS_SEED1 0x0a8 +#define QSERDES_V5_TX_PRBS_SEED2 0x0ac +#define QSERDES_V5_TX_PRBS_SEED3 0x0b0 +#define QSERDES_V5_TX_PRBS_SEED4 0x0b4 +#define QSERDES_V5_TX_RESET_GEN 0x0b8 +#define QSERDES_V5_TX_RESET_GEN_MUXES 0x0bc +#define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0x0c0 +#define QSERDES_V5_TX_TX_INTERFACE_MODE 0x0c4 +#define QSERDES_V5_TX_VMODE_CTRL1 0x0c8 +#define QSERDES_V5_TX_ALOG_OBSV_BUS_CTRL_1 0x0cc +#define QSERDES_V5_TX_BIST_STATUS 0x0d0 +#define QSERDES_V5_TX_BIST_ERROR_COUNT1 0x0d4 +#define QSERDES_V5_TX_BIST_ERROR_COUNT2 0x0d8 +#define QSERDES_V5_TX_ALOG_OBSV_BUS_STATUS_1 0x0dc +#define QSERDES_V5_TX_LANE_DIG_CONFIG 0x0e0 +#define QSERDES_V5_TX_PI_QEC_CTRL 0x0e4 +#define QSERDES_V5_TX_PRE_EMPH 0x0e8 +#define QSERDES_V5_TX_SW_RESET 0x0ec +#define QSERDES_V5_TX_DCC_OFFSET 0x0f0 +#define QSERDES_V5_TX_DCC_CMUX_POSTCAL_OFFSET 0x0f4 +#define QSERDES_V5_TX_DCC_CMUX_CAL_CTRL1 0x0f8 +#define QSERDES_V5_TX_DCC_CMUX_CAL_CTRL2 0x0fc +#define QSERDES_V5_TX_DIG_BKUP_CTRL 0x100 +#define QSERDES_V5_TX_DEBUG_BUS0 0x104 +#define QSERDES_V5_TX_DEBUG_BUS1 0x108 +#define QSERDES_V5_TX_DEBUG_BUS2 0x10c +#define QSERDES_V5_TX_DEBUG_BUS3 0x110 +#define QSERDES_V5_TX_READ_EQCODE 0x114 +#define QSERDES_V5_TX_READ_OFFSETCODE 0x118 +#define QSERDES_V5_TX_IA_ERROR_COUNTER_LOW 0x11c +#define QSERDES_V5_TX_IA_ERROR_COUNTER_HIGH 0x120 +#define QSERDES_V5_TX_VGA_READ_CODE 0x124 +#define QSERDES_V5_TX_VTH_READ_CODE 0x128 +#define QSERDES_V5_TX_DFE_TAP1_READ_CODE 0x12c +#define QSERDES_V5_TX_DFE_TAP2_READ_CODE 0x130 +#define QSERDES_V5_TX_IDAC_STATUS_I 0x134 +#define QSERDES_V5_TX_IDAC_STATUS_IBAR 0x138 +#define QSERDES_V5_TX_IDAC_STATUS_Q 0x13c +#define QSERDES_V5_TX_IDAC_STATUS_QBAR 0x140 +#define QSERDES_V5_TX_IDAC_STATUS_A 0x144 +#define QSERDES_V5_TX_IDAC_STATUS_ABAR 0x148 +#define QSERDES_V5_TX_IDAC_STATUS_SM_ON 0x14c +#define QSERDES_V5_TX_IDAC_STATUS_CAL_DONE 0x150 +#define QSERDES_V5_TX_IDAC_STATUS_SIGNERROR 0x154 +#define QSERDES_V5_TX_DCC_CAL_STATUS 0x158 +#define QSERDES_V5_TX_DCC_READ_CODE_STATUS 0x15c + +/* Only for QMP V5 PHY - RX registers */ +#define QSERDES_V5_RX_UCDR_FO_GAIN_HALF 0x000 +#define QSERDES_V5_RX_UCDR_FO_GAIN_QUARTER 0x004 +#define QSERDES_V5_RX_UCDR_FO_GAIN 0x008 +#define QSERDES_V5_RX_UCDR_SO_GAIN_HALF 0x00c +#define QSERDES_V5_RX_UCDR_SO_GAIN_QUARTER 0x010 +#define QSERDES_V5_RX_UCDR_SO_GAIN 0x014 +#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN_HALF 0x018 +#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN_QUARTER 0x01c +#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN 0x020 +#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN_HALF 0x024 +#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 +#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN 0x02c +#define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030 +#define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 +#define QSERDES_V5_RX_UCDR_FO_TO_SO_DELAY 0x038 +#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c +#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 +#define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044 +#define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048 +#define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c +#define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050 +#define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054 +#define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058 +#define QSERDES_V5_RX_AUX_CONTROL 0x05c +#define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060 +#define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064 +#define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068 +#define QSERDES_V5_RX_AC_JTAG_INITP 0x06c +#define QSERDES_V5_RX_AC_JTAG_INITN 0x070 +#define QSERDES_V5_RX_AC_JTAG_LVL 0x074 +#define QSERDES_V5_RX_AC_JTAG_MODE 0x078 +#define QSERDES_V5_RX_AC_JTAG_RESET 0x07c +#define QSERDES_V5_RX_RX_TERM_BW 0x080 +#define QSERDES_V5_RX_RX_RCVR_IQ_EN 0x084 +#define QSERDES_V5_RX_RX_IDAC_I_DC_OFFSETS 0x088 +#define QSERDES_V5_RX_RX_IDAC_IBAR_DC_OFFSETS 0x08c +#define QSERDES_V5_RX_RX_IDAC_Q_DC_OFFSETS 0x090 +#define QSERDES_V5_RX_RX_IDAC_QBAR_DC_OFFSETS 0x094 +#define QSERDES_V5_RX_RX_IDAC_A_DC_OFFSETS 0x098 +#define QSERDES_V5_RX_RX_IDAC_ABAR_DC_OFFSETS 0x09c +#define QSERDES_V5_RX_RX_IDAC_EN 0x0a0 +#define QSERDES_V5_RX_RX_IDAC_ENABLES 0x0a4 +#define QSERDES_V5_RX_RX_IDAC_SIGN 0x0a8 +#define QSERDES_V5_RX_RX_HIGHZ_HIGHRATE 0x0ac +#define QSERDES_V5_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0b0 +#define QSERDES_V5_RX_DFE_1 0x0b4 +#define QSERDES_V5_RX_DFE_2 0x0b8 +#define QSERDES_V5_RX_DFE_3 0x0bc +#define QSERDES_V5_RX_DFE_4 0x0c0 +#define QSERDES_V5_RX_TX_ADAPT_PRE_THRESH1 0x0c4 +#define QSERDES_V5_RX_TX_ADAPT_PRE_THRESH2 0x0c8 +#define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc +#define QSERDES_V5_RX_TX_ADAPT_MAIN_THRESH 0x0d0 +#define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4 +#define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8 +#define QSERDES_V5_RX_GM_CAL 0x0dc +#define QSERDES_V5_RX_RX_VGA_GAIN2_LSB 0x0e0 +#define QSERDES_V5_RX_RX_VGA_GAIN2_MSB 0x0e4 +#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 +#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec +#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 +#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 +#define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8 +#define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc +#define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100 +#define QSERDES_V5_RX_RX_IDAC_ACCUMULATOR 0x104 +#define QSERDES_V5_RX_RX_EQ_OFFSET_LSB 0x108 +#define QSERDES_V5_RX_RX_EQ_OFFSET_MSB 0x10c +#define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 +#define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 +#define QSERDES_V5_RX_SIGDET_ENABLES 0x118 +#define QSERDES_V5_RX_SIGDET_CNTRL 0x11c +#define QSERDES_V5_RX_SIGDET_LVL 0x120 +#define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124 +#define QSERDES_V5_RX_RX_BAND 0x128 +#define QSERDES_V5_RX_CDR_FREEZE_UP_DN 0x12c +#define QSERDES_V5_RX_CDR_RESET_OVERRIDE 0x130 +#define QSERDES_V5_RX_RX_INTERFACE_MODE 0x134 +#define QSERDES_V5_RX_JITTER_GEN_MODE 0x138 +#define QSERDES_V5_RX_SJ_AMP1 0x13c +#define QSERDES_V5_RX_SJ_AMP2 0x140 +#define QSERDES_V5_RX_SJ_PER1 0x144 +#define QSERDES_V5_RX_SJ_PER2 0x148 +#define QSERDES_V5_RX_PPM_OFFSET1 0x14c +#define QSERDES_V5_RX_PPM_OFFSET2 0x150 +#define QSERDES_V5_RX_SIGN_PPM_PERIOD1 0x154 +#define QSERDES_V5_RX_SIGN_PPM_PERIOD2 0x158 +#define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c +#define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160 +#define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164 +#define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168 +#define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c +#define QSERDES_V5_RX_RX_MODE_01_LOW 0x170 +#define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174 +#define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178 +#define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c +#define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180 +#define QSERDES_V5_RX_RX_MODE_10_LOW 0x184 +#define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188 +#define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c +#define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190 +#define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194 +#define QSERDES_V5_RX_PHPRE_CTRL 0x198 +#define QSERDES_V5_RX_PHPRE_INITVAL 0x19c +#define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0 +#define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 +#define QSERDES_V5_RX_DCC_CTRL1 0x1a8 +#define QSERDES_V5_RX_DCC_CTRL2 0x1ac +#define QSERDES_V5_RX_VTH_CODE 0x1b0 +#define QSERDES_V5_RX_VTH_MIN_THRESH 0x1b4 +#define QSERDES_V5_RX_VTH_MAX_THRESH 0x1b8 +#define QSERDES_V5_RX_ALOG_OBSV_BUS_CTRL_1 0x1bc +#define QSERDES_V5_RX_PI_CTRL1 0x1c0 +#define QSERDES_V5_RX_PI_CTRL2 0x1c4 +#define QSERDES_V5_RX_PI_QUAD 0x1c8 +#define QSERDES_V5_RX_IDATA1 0x1cc +#define QSERDES_V5_RX_IDATA2 0x1d0 +#define QSERDES_V5_RX_AUX_DATA1 0x1d4 +#define QSERDES_V5_RX_AUX_DATA2 0x1d8 +#define QSERDES_V5_RX_AC_JTAG_OUTP 0x1dc +#define QSERDES_V5_RX_AC_JTAG_OUTN 0x1e0 +#define QSERDES_V5_RX_RX_SIGDET 0x1e4 +#define QSERDES_V5_RX_ALOG_OBSV_BUS_STATUS_1 0x1e8 + +/* Only for QMP V5 UFS ? */ +#define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178 +#define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c +#define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180 +#define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h new file mode 100644 index 000000000000..86c01104799e --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_ + +/* Only for QMP V5_20 PHY - TX registers */ +#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 +#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 +#define QSERDES_V5_20_TX_LANE_MODE_1 0x78 +#define QSERDES_V5_20_TX_LANE_MODE_2 0x7c + +/* Only for QMP V5_20 PHY - RX registers */ +#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008 +#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c +#define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020 +#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c +#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030 +#define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c +#define QSERDES_V5_20_RX_DFE_3 0x090 +#define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4 +#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4 +#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8 +#define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc +#define QSERDES_V5_20_RX_GM_CAL 0x0ec +#define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108 +#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164 +#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168 +#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c +#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174 +#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178 +#define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c +#define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180 +#define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184 +#define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188 +#define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c +#define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190 +#define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194 +#define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198 +#define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c +#define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0 +#define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4 +#define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8 +#define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac +#define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0 +#define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4 +#define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0 +#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4 +#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8 +#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc +#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200 +#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204 +#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208 +#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210 +#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218 +#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h new file mode 100644 index 000000000000..d20694513eb4 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h @@ -0,0 +1,205 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_H_ + +/* Only for QMP V2 PHY - TX registers */ +#define QSERDES_TX_BIST_MODE_LANENO 0x000 +#define QSERDES_TX_BIST_INVERT 0x004 +#define QSERDES_TX_CLKBUF_ENABLE 0x008 +#define QSERDES_TX_CMN_CONTROL_ONE 0x00c +#define QSERDES_TX_CMN_CONTROL_TWO 0x010 +#define QSERDES_TX_CMN_CONTROL_THREE 0x014 +#define QSERDES_TX_TX_EMP_POST1_LVL 0x018 +#define QSERDES_TX_TX_POST2_EMPH 0x01c +#define QSERDES_TX_TX_BOOST_LVL_UP_DN 0x020 +#define QSERDES_TX_HP_PD_ENABLES 0x024 +#define QSERDES_TX_TX_IDLE_LVL_LARGE_AMP 0x028 +#define QSERDES_TX_TX_DRV_LVL 0x02c +#define QSERDES_TX_TX_DRV_LVL_OFFSET 0x030 +#define QSERDES_TX_RESET_TSYNC_EN 0x034 +#define QSERDES_TX_PRE_STALL_LDO_BOOST_EN 0x038 +#define QSERDES_TX_TX_BAND 0x03c +#define QSERDES_TX_SLEW_CNTL 0x040 +#define QSERDES_TX_INTERFACE_SELECT 0x044 +#define QSERDES_TX_LPB_EN 0x048 +#define QSERDES_TX_RES_CODE_LANE_TX 0x04c +#define QSERDES_TX_RES_CODE_LANE_RX 0x050 +#define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054 +#define QSERDES_TX_PERL_LENGTH1 0x058 +#define QSERDES_TX_PERL_LENGTH2 0x05c +#define QSERDES_TX_SERDES_BYP_EN_OUT 0x060 +#define QSERDES_TX_DEBUG_BUS_SEL 0x064 +#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068 +#define QSERDES_TX_TX_POL_INV 0x06c +#define QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN 0x070 +#define QSERDES_TX_BIST_PATTERN1 0x074 +#define QSERDES_TX_BIST_PATTERN2 0x078 +#define QSERDES_TX_BIST_PATTERN3 0x07c +#define QSERDES_TX_BIST_PATTERN4 0x080 +#define QSERDES_TX_BIST_PATTERN5 0x084 +#define QSERDES_TX_BIST_PATTERN6 0x088 +#define QSERDES_TX_BIST_PATTERN7 0x08c +#define QSERDES_TX_BIST_PATTERN8 0x090 +#define QSERDES_TX_LANE_MODE 0x094 +#define QSERDES_TX_IDAC_CAL_LANE_MODE 0x098 +#define QSERDES_TX_IDAC_CAL_LANE_MODE_CONFIGURATION 0x09c +#define QSERDES_TX_ATB_SEL1 0x0a0 +#define QSERDES_TX_ATB_SEL2 0x0a4 +#define QSERDES_TX_RCV_DETECT_LVL 0x0a8 +#define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac +#define QSERDES_TX_PRBS_SEED1 0x0b0 +#define QSERDES_TX_PRBS_SEED2 0x0b4 +#define QSERDES_TX_PRBS_SEED3 0x0b8 +#define QSERDES_TX_PRBS_SEED4 0x0bc +#define QSERDES_TX_RESET_GEN 0x0c0 +#define QSERDES_TX_RESET_GEN_MUXES 0x0c4 +#define QSERDES_TX_TRAN_DRVR_EMP_EN 0x0c8 +#define QSERDES_TX_TX_INTERFACE_MODE 0x0cc +#define QSERDES_TX_PWM_CTRL 0x0d0 +#define QSERDES_TX_PWM_ENCODED_OR_DATA 0x0d4 +#define QSERDES_TX_PWM_GEAR_1_DIVIDER_BAND2 0x0d8 +#define QSERDES_TX_PWM_GEAR_2_DIVIDER_BAND2 0x0dc +#define QSERDES_TX_PWM_GEAR_3_DIVIDER_BAND2 0x0e0 +#define QSERDES_TX_PWM_GEAR_4_DIVIDER_BAND2 0x0e4 +#define QSERDES_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x0e8 +#define QSERDES_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x0ec +#define QSERDES_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x0f0 +#define QSERDES_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x0f4 +#define QSERDES_TX_VMODE_CTRL1 0x0f8 +#define QSERDES_TX_VMODE_CTRL2 0x0fc +#define QSERDES_TX_TX_ALOG_INTF_OBSV_CNTL 0x100 +#define QSERDES_TX_BIST_STATUS 0x104 +#define QSERDES_TX_BIST_ERROR_COUNT1 0x108 +#define QSERDES_TX_BIST_ERROR_COUNT2 0x10c +#define QSERDES_TX_TX_ALOG_INTF_OBSV 0x110 + +/* Only for QMP V2 PHY - RX registers */ +#define QSERDES_RX_UCDR_FO_GAIN_HALF 0x000 +#define QSERDES_RX_UCDR_FO_GAIN_QUARTER 0x004 +#define QSERDES_RX_UCDR_FO_GAIN_EIGHTH 0x008 +#define QSERDES_RX_UCDR_FO_GAIN 0x00c +#define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010 +#define QSERDES_RX_UCDR_SO_GAIN_QUARTER 0x014 +#define QSERDES_RX_UCDR_SO_GAIN_EIGHTH 0x018 +#define QSERDES_RX_UCDR_SO_GAIN 0x01c +#define QSERDES_RX_UCDR_SVS_FO_GAIN_HALF 0x020 +#define QSERDES_RX_UCDR_SVS_FO_GAIN_QUARTER 0x024 +#define QSERDES_RX_UCDR_SVS_FO_GAIN_EIGHTH 0x028 +#define QSERDES_RX_UCDR_SVS_FO_GAIN 0x02c +#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF 0x030 +#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER 0x034 +#define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH 0x038 +#define QSERDES_RX_UCDR_SVS_SO_GAIN 0x03c +#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040 +#define QSERDES_RX_UCDR_FD_GAIN 0x044 +#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048 +#define QSERDES_RX_UCDR_FO_TO_SO_DELAY 0x04c +#define QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0x050 +#define QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x054 +#define QSERDES_RX_UCDR_MODULATE 0x058 +#define QSERDES_RX_UCDR_PI_CONTROLS 0x05c +#define QSERDES_RX_RBIST_CONTROL 0x060 +#define QSERDES_RX_AUX_CONTROL 0x064 +#define QSERDES_RX_AUX_DATA_TCOARSE 0x068 +#define QSERDES_RX_AUX_DATA_TFINE_LSB 0x06c +#define QSERDES_RX_AUX_DATA_TFINE_MSB 0x070 +#define QSERDES_RX_RCLK_AUXDATA_SEL 0x074 +#define QSERDES_RX_AC_JTAG_ENABLE 0x078 +#define QSERDES_RX_AC_JTAG_INITP 0x07c +#define QSERDES_RX_AC_JTAG_INITN 0x080 +#define QSERDES_RX_AC_JTAG_LVL 0x084 +#define QSERDES_RX_AC_JTAG_MODE 0x088 +#define QSERDES_RX_AC_JTAG_RESET 0x08c +#define QSERDES_RX_RX_TERM_BW 0x090 +#define QSERDES_RX_RX_RCVR_IQ_EN 0x094 +#define QSERDES_RX_RX_IDAC_I_DC_OFFSETS 0x098 +#define QSERDES_RX_RX_IDAC_IBAR_DC_OFFSETS 0x09c +#define QSERDES_RX_RX_IDAC_Q_DC_OFFSETS 0x0a0 +#define QSERDES_RX_RX_IDAC_QBAR_DC_OFFSETS 0x0a4 +#define QSERDES_RX_RX_IDAC_A_DC_OFFSETS 0x0a8 +#define QSERDES_RX_RX_IDAC_ABAR_DC_OFFSETS 0x0ac +#define QSERDES_RX_RX_IDAC_EN 0x0b0 +#define QSERDES_RX_RX_IDAC_ENABLES 0x0b4 +#define QSERDES_RX_RX_IDAC_SIGN 0x0b8 +#define QSERDES_RX_RX_HIGHZ_HIGHRATE 0x0bc +#define QSERDES_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0c0 +#define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4 +#define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8 +#define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc +#define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0 +#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1 0x0d4 +#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8 +#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc +#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0 +#define QSERDES_RX_RX_IDAC_CAL_CONFIGURATION 0x0e4 +#define QSERDES_RX_RX_IDAC_TSETTLE_LOW 0x0e8 +#define QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x0ec +#define QSERDES_RX_RX_IDAC_ENDSAMP_LOW 0x0f0 +#define QSERDES_RX_RX_IDAC_ENDSAMP_HIGH 0x0f4 +#define QSERDES_RX_RX_IDAC_MIDPOINT_LOW 0x0f8 +#define QSERDES_RX_RX_IDAC_MIDPOINT_HIGH 0x0fc +#define QSERDES_RX_RX_EQ_OFFSET_LSB 0x100 +#define QSERDES_RX_RX_EQ_OFFSET_MSB 0x104 +#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108 +#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c +#define QSERDES_RX_SIGDET_ENABLES 0x110 +#define QSERDES_RX_SIGDET_CNTRL 0x114 +#define QSERDES_RX_SIGDET_LVL 0x118 +#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c +#define QSERDES_RX_RX_BAND 0x120 +#define QSERDES_RX_CDR_FREEZE_UP_DN 0x124 +#define QSERDES_RX_CDR_RESET_OVERRIDE 0x128 +#define QSERDES_RX_RX_INTERFACE_MODE 0x12c +#define QSERDES_RX_JITTER_GEN_MODE 0x130 +#define QSERDES_RX_BUJ_AMP 0x134 +#define QSERDES_RX_SJ_AMP1 0x138 +#define QSERDES_RX_SJ_AMP2 0x13c +#define QSERDES_RX_SJ_PER1 0x140 +#define QSERDES_RX_SJ_PER2 0x144 +#define QSERDES_RX_BUJ_STEP_FREQ1 0x148 +#define QSERDES_RX_BUJ_STEP_FREQ2 0x14c +#define QSERDES_RX_PPM_OFFSET1 0x150 +#define QSERDES_RX_PPM_OFFSET2 0x154 +#define QSERDES_RX_SIGN_PPM_PERIOD1 0x158 +#define QSERDES_RX_SIGN_PPM_PERIOD2 0x15c +#define QSERDES_RX_SSC_CTRL 0x160 +#define QSERDES_RX_SSC_COUNT1 0x164 +#define QSERDES_RX_SSC_COUNT2 0x168 +#define QSERDES_RX_RX_ALOG_INTF_OBSV_CNTL 0x16c +#define QSERDES_RX_RX_PWM_ENABLE_AND_DATA 0x170 +#define QSERDES_RX_RX_PWM_GEAR1_TIMEOUT_COUNT 0x174 +#define QSERDES_RX_RX_PWM_GEAR2_TIMEOUT_COUNT 0x178 +#define QSERDES_RX_RX_PWM_GEAR3_TIMEOUT_COUNT 0x17c +#define QSERDES_RX_RX_PWM_GEAR4_TIMEOUT_COUNT 0x180 +#define QSERDES_RX_PI_CTRL1 0x184 +#define QSERDES_RX_PI_CTRL2 0x188 +#define QSERDES_RX_PI_QUAD 0x18c +#define QSERDES_RX_IDATA1 0x190 +#define QSERDES_RX_IDATA2 0x194 +#define QSERDES_RX_AUX_DATA1 0x198 +#define QSERDES_RX_AUX_DATA2 0x19c +#define QSERDES_RX_AC_JTAG_OUTP 0x1a0 +#define QSERDES_RX_AC_JTAG_OUTN 0x1a4 +#define QSERDES_RX_RX_SIGDET 0x1a8 +#define QSERDES_RX_RX_VDCOFF 0x1ac +#define QSERDES_RX_IDAC_CAL_ON 0x1b0 +#define QSERDES_RX_IDAC_STATUS_I 0x1b4 +#define QSERDES_RX_IDAC_STATUS_IBAR 0x1b8 +#define QSERDES_RX_IDAC_STATUS_Q 0x1bc +#define QSERDES_RX_IDAC_STATUS_QBAR 0x1c0 +#define QSERDES_RX_IDAC_STATUS_A 0x1c4 +#define QSERDES_RX_IDAC_STATUS_ABAR 0x1c8 +#define QSERDES_RX_CALST_STATUS_I 0x1cc +#define QSERDES_RX_CALST_STATUS_Q 0x1d0 +#define QSERDES_RX_CALST_STATUS_A 0x1d4 +#define QSERDES_RX_RX_ALOG_INTF_OBSV 0x1d8 +#define QSERDES_RX_READ_EQCODE 0x1dc +#define QSERDES_RX_READ_OFFSETCODE 0x1e0 +#define QSERDES_RX_IA_ERROR_COUNTER_LOW 0x1e4 +#define QSERDES_RX_IA_ERROR_COUNTER_HIGH 0x1e8 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c new file mode 100644 index 000000000000..c8583f5a54bd --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -0,0 +1,1383 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "phy-qcom-qmp.h" + +/* QPHY_SW_RESET bit */ +#define SW_RESET BIT(0) +/* QPHY_POWER_DOWN_CONTROL */ +#define SW_PWRDN BIT(0) +#define REFCLK_DRV_DSBL BIT(1) +/* QPHY_START_CONTROL bits */ +#define SERDES_START BIT(0) +#define PCS_START BIT(1) +#define PLL_READY_GATE_EN BIT(3) +/* QPHY_PCS_STATUS bit */ +#define PHYSTATUS BIT(6) +#define PHYSTATUS_4_20 BIT(7) +/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ +#define PCS_READY BIT(0) + +/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ +/* DP PHY soft reset */ +#define SW_DPPHY_RESET BIT(0) +/* mux to select DP PHY reset control, 0:HW control, 1: software reset */ +#define SW_DPPHY_RESET_MUX BIT(1) +/* USB3 PHY soft reset */ +#define SW_USB3PHY_RESET BIT(2) +/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ +#define SW_USB3PHY_RESET_MUX BIT(3) + +/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ +#define USB3_MODE BIT(0) /* enables USB3 mode */ +#define DP_MODE BIT(1) /* enables DP mode */ + +/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ +#define ARCVR_DTCT_EN BIT(0) +#define ALFPS_DTCT_EN BIT(1) +#define ARCVR_DTCT_EVENT_SEL BIT(4) + +/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ +#define IRQ_CLEAR BIT(0) + +/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ +#define RCVR_DETECT BIT(0) + +/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ +#define CLAMP_EN BIT(0) /* enables i/o clamp_n */ + +#define PHY_INIT_COMPLETE_TIMEOUT 10000 +#define POWER_DOWN_DELAY_US_MIN 10 +#define POWER_DOWN_DELAY_US_MAX 11 + +#define MAX_PROP_NAME 32 + +/* Define the assumed distance between lanes for underspecified device trees. */ +#define QMP_PHY_LEGACY_LANE_STRIDE 0x400 + +struct qmp_phy_init_tbl { + unsigned int offset; + unsigned int val; + /* + * register part of layout ? + * if yes, then offset gives index in the reg-layout + */ + bool in_layout; + /* + * mask of lanes for which this register is written + * for cases when second lane needs different values + */ + u8 lane_mask; +}; + +#define QMP_PHY_INIT_CFG(o, v) \ + { \ + .offset = o, \ + .val = v, \ + .lane_mask = 0xff, \ + } + +#define QMP_PHY_INIT_CFG_L(o, v) \ + { \ + .offset = o, \ + .val = v, \ + .in_layout = true, \ + .lane_mask = 0xff, \ + } + +#define QMP_PHY_INIT_CFG_LANE(o, v, l) \ + { \ + .offset = o, \ + .val = v, \ + .lane_mask = l, \ + } + +/* set of registers with offsets different per-PHY */ +enum qphy_reg_layout { + /* Common block control registers */ + QPHY_COM_SW_RESET, + QPHY_COM_POWER_DOWN_CONTROL, + QPHY_COM_START_CONTROL, + QPHY_COM_PCS_READY_STATUS, + /* PCS registers */ + QPHY_SW_RESET, + QPHY_START_CTRL, + QPHY_PCS_READY_STATUS, + QPHY_PCS_STATUS, + QPHY_PCS_AUTONOMOUS_MODE_CTRL, + QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, + QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, + QPHY_PCS_POWER_DOWN_CONTROL, + /* PCS_MISC registers */ + QPHY_PCS_MISC_TYPEC_CTRL, + /* Keep last to ensure regs_layout arrays are properly initialized */ + QPHY_LAYOUT_SIZE +}; + +static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_START_CTRL] = 0x00, + [QPHY_PCS_READY_STATUS] = 0x168, +}; + +static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_START_CTRL] = 0x00, + [QPHY_PCS_READY_STATUS] = 0x160, +}; + +static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_START_CTRL] = 0x00, + [QPHY_PCS_READY_STATUS] = 0x168, +}; + +static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START, + [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS, + [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET, +}; + +static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10), + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54), + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), +}; + +static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), +}; + +static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), +}; + +static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04), + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), + + /* Rate B */ + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), +}; + +static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), +}; + +static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), +}; + +static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_PWM_GEAR_BAND, 0x15), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_CTRL2, 0x6d), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL, 0x0f), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL, 0x02), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SYM_RESYNC_CTRL, 0x03), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL, 0x12), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL, 0x0f), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */ +}; + +static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f), + + /* Rate B */ + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), +}; + +static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), +}; + +static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), +}; + +static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02), +}; + +static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), + + /* Rate B */ + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), +}; + +static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), +}; + +static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), + +}; + +static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), +}; + +static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), + + /* Rate B */ + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), +}; + +static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c), +}; + +static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), +}; + +static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), +}; + +struct qmp_phy; + +/* struct qmp_phy_cfg - per-PHY initialization config */ +struct qmp_phy_cfg { + /* phy-type - PCIE/UFS/USB */ + unsigned int type; + /* number of lanes provided by phy */ + int nlanes; + + /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_init_tbl *serdes_tbl; + int serdes_tbl_num; + const struct qmp_phy_init_tbl *tx_tbl; + int tx_tbl_num; + const struct qmp_phy_init_tbl *rx_tbl; + int rx_tbl_num; + const struct qmp_phy_init_tbl *pcs_tbl; + int pcs_tbl_num; + + /* clock ids to be requested */ + const char * const *clk_list; + int num_clks; + /* regulators to be requested */ + const char * const *vreg_list; + int num_vregs; + + /* array of registers with different offsets */ + const unsigned int *regs; + + unsigned int start_ctrl; + unsigned int pwrdn_ctrl; + /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ + unsigned int phy_status; + + /* true, if PHY has secondary tx/rx lanes to be configured */ + bool is_dual_lane_phy; + + /* true, if PCS block has no separate SW_RESET register */ + bool no_pcs_sw_reset; +}; + +/** + * struct qmp_phy - per-lane phy descriptor + * + * @phy: generic phy + * @cfg: phy specific configuration + * @serdes: iomapped memory space for phy's serdes (i.e. PLL) + * @tx: iomapped memory space for lane's tx + * @rx: iomapped memory space for lane's rx + * @pcs: iomapped memory space for lane's pcs + * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) + * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) + * @pcs_misc: iomapped memory space for lane's pcs_misc + * @index: lane index + * @qmp: QMP phy to which this lane belongs + * @mode: current PHY mode + */ +struct qmp_phy { + struct phy *phy; + const struct qmp_phy_cfg *cfg; + void __iomem *serdes; + void __iomem *tx; + void __iomem *rx; + void __iomem *pcs; + void __iomem *tx2; + void __iomem *rx2; + void __iomem *pcs_misc; + unsigned int index; + struct qcom_qmp *qmp; + enum phy_mode mode; +}; + +/** + * struct qcom_qmp - structure holding QMP phy block attributes + * + * @dev: device + * + * @clks: array of clocks required by phy + * @resets: array of resets required by phy + * @vregs: regulator supplies bulk data + * + * @phys: array of per-lane phy descriptors + * @ufs_reset: optional UFS PHY reset handle + */ +struct qcom_qmp { + struct device *dev; + + struct clk_bulk_data *clks; + struct regulator_bulk_data *vregs; + + struct qmp_phy **phys; + + struct reset_control *ufs_reset; +}; + +static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) +{ + u32 reg; + + reg = readl(base + offset); + reg |= val; + writel(reg, base + offset); + + /* ensure that above write is through */ + readl(base + offset); +} + +static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) +{ + u32 reg; + + reg = readl(base + offset); + reg &= ~val; + writel(reg, base + offset); + + /* ensure that above write is through */ + readl(base + offset); +} + +/* list of clocks required by phy */ +static const char * const msm8996_ufs_phy_clk_l[] = { + "ref", +}; + +/* the primary usb3 phy on sm8250 doesn't have a ref clock */ +static const char * const sm8450_ufs_phy_clk_l[] = { + "qref", "ref", "ref_aux", +}; + +static const char * const sdm845_ufs_phy_clk_l[] = { + "ref", "ref_aux", +}; + +/* list of regulators */ +static const char * const qmp_phy_vreg_l[] = { + "vdda-phy", "vdda-pll", +}; + +static const struct qmp_phy_cfg msm8996_ufs_cfg = { + .type = PHY_TYPE_UFS, + .nlanes = 1, + + .serdes_tbl = msm8996_ufs_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl), + .tx_tbl = msm8996_ufs_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl), + .rx_tbl = msm8996_ufs_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl), + + .clk_list = msm8996_ufs_phy_clk_l, + .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l), + + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + + .regs = msm8996_ufsphy_regs_layout, + + .start_ctrl = SERDES_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + .no_pcs_sw_reset = true, +}; + +static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { + .type = PHY_TYPE_UFS, + .nlanes = 2, + + .serdes_tbl = sdm845_ufsphy_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl), + .tx_tbl = sdm845_ufsphy_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl), + .rx_tbl = sdm845_ufsphy_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl), + .pcs_tbl = sdm845_ufsphy_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl), + .clk_list = sdm845_ufs_phy_clk_l, + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sdm845_ufsphy_regs_layout, + + .start_ctrl = SERDES_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + .is_dual_lane_phy = true, + .no_pcs_sw_reset = true, +}; + +static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { + .type = PHY_TYPE_UFS, + .nlanes = 1, + + .serdes_tbl = sm6115_ufsphy_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl), + .tx_tbl = sm6115_ufsphy_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl), + .rx_tbl = sm6115_ufsphy_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl), + .pcs_tbl = sm6115_ufsphy_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl), + .clk_list = sdm845_ufs_phy_clk_l, + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm6115_ufsphy_regs_layout, + + .start_ctrl = SERDES_START, + .pwrdn_ctrl = SW_PWRDN, + + .no_pcs_sw_reset = true, +}; + +static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { + .type = PHY_TYPE_UFS, + .nlanes = 2, + + .serdes_tbl = sm8150_ufsphy_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl), + .tx_tbl = sm8150_ufsphy_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl), + .rx_tbl = sm8150_ufsphy_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl), + .pcs_tbl = sm8150_ufsphy_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl), + .clk_list = sdm845_ufs_phy_clk_l, + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8150_ufsphy_regs_layout, + + .start_ctrl = SERDES_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + .is_dual_lane_phy = true, +}; + +static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { + .type = PHY_TYPE_UFS, + .nlanes = 2, + + .serdes_tbl = sm8350_ufsphy_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), + .tx_tbl = sm8350_ufsphy_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), + .rx_tbl = sm8350_ufsphy_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), + .pcs_tbl = sm8350_ufsphy_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), + .clk_list = sdm845_ufs_phy_clk_l, + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8150_ufsphy_regs_layout, + + .start_ctrl = SERDES_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + .is_dual_lane_phy = true, +}; + +static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { + .type = PHY_TYPE_UFS, + .nlanes = 2, + + .serdes_tbl = sm8350_ufsphy_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), + .tx_tbl = sm8350_ufsphy_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), + .rx_tbl = sm8350_ufsphy_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), + .pcs_tbl = sm8350_ufsphy_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), + .clk_list = sm8450_ufs_phy_clk_l, + .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8150_ufsphy_regs_layout, + + .start_ctrl = SERDES_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + .is_dual_lane_phy = true, +}; + +static void qcom_qmp_phy_ufs_configure_lane(void __iomem *base, + const unsigned int *regs, + const struct qmp_phy_init_tbl tbl[], + int num, + u8 lane_mask) +{ + int i; + const struct qmp_phy_init_tbl *t = tbl; + + if (!t) + return; + + for (i = 0; i < num; i++, t++) { + if (!(t->lane_mask & lane_mask)) + continue; + + if (t->in_layout) + writel(t->val, base + regs[t->offset]); + else + writel(t->val, base + t->offset); + } +} + +static void qcom_qmp_phy_ufs_configure(void __iomem *base, + const unsigned int *regs, + const struct qmp_phy_init_tbl tbl[], + int num) +{ + qcom_qmp_phy_ufs_configure_lane(base, regs, tbl, num, 0xff); +} + +static int qcom_qmp_phy_ufs_serdes_init(struct qmp_phy *qphy) +{ + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *serdes = qphy->serdes; + const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; + int serdes_tbl_num = cfg->serdes_tbl_num; + + qcom_qmp_phy_ufs_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); + + return 0; +} + +static int qcom_qmp_phy_ufs_com_init(struct qmp_phy *qphy) +{ + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *pcs = qphy->pcs; + int ret; + + /* turn on regulator supplies */ + ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); + if (ret) { + dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); + return ret; + } + + ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); + if (ret) + goto err_disable_regulators; + + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) + qphy_setbits(pcs, + cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + cfg->pwrdn_ctrl); + else + qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, + cfg->pwrdn_ctrl); + + return 0; + +err_disable_regulators: + regulator_bulk_disable(cfg->num_vregs, qmp->vregs); + + return ret; +} + +static int qcom_qmp_phy_ufs_com_exit(struct qmp_phy *qphy) +{ + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + + reset_control_assert(qmp->ufs_reset); + + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); + + regulator_bulk_disable(cfg->num_vregs, qmp->vregs); + + return 0; +} + +static int qcom_qmp_phy_ufs_init(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + int ret; + dev_vdbg(qmp->dev, "Initializing QMP phy\n"); + + if (cfg->no_pcs_sw_reset) { + /* + * Get UFS reset, which is delayed until now to avoid a + * circular dependency where UFS needs its PHY, but the PHY + * needs this UFS reset. + */ + if (!qmp->ufs_reset) { + qmp->ufs_reset = + devm_reset_control_get_exclusive(qmp->dev, + "ufsphy"); + + if (IS_ERR(qmp->ufs_reset)) { + ret = PTR_ERR(qmp->ufs_reset); + dev_err(qmp->dev, + "failed to get UFS reset: %d\n", + ret); + + qmp->ufs_reset = NULL; + return ret; + } + } + + ret = reset_control_assert(qmp->ufs_reset); + if (ret) + return ret; + } + + ret = qcom_qmp_phy_ufs_com_init(qphy); + if (ret) + return ret; + + return 0; +} + +static int qcom_qmp_phy_ufs_power_on(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *tx = qphy->tx; + void __iomem *rx = qphy->rx; + void __iomem *pcs = qphy->pcs; + void __iomem *status; + unsigned int mask, val, ready; + int ret; + + qcom_qmp_phy_ufs_serdes_init(qphy); + + /* Tx, Rx, and PCS configurations */ + qcom_qmp_phy_ufs_configure_lane(tx, cfg->regs, + cfg->tx_tbl, cfg->tx_tbl_num, 1); + + /* Configuration for other LANE for USB-DP combo PHY */ + if (cfg->is_dual_lane_phy) { + qcom_qmp_phy_ufs_configure_lane(qphy->tx2, cfg->regs, + cfg->tx_tbl, cfg->tx_tbl_num, 2); + } + + qcom_qmp_phy_ufs_configure_lane(rx, cfg->regs, + cfg->rx_tbl, cfg->rx_tbl_num, 1); + + if (cfg->is_dual_lane_phy) { + qcom_qmp_phy_ufs_configure_lane(qphy->rx2, cfg->regs, + cfg->rx_tbl, cfg->rx_tbl_num, 2); + } + + qcom_qmp_phy_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); + + ret = reset_control_deassert(qmp->ufs_reset); + if (ret) + return ret; + + /* Pull PHY out of reset state */ + if (!cfg->no_pcs_sw_reset) + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + /* start SerDes and Phy-Coding-Sublayer */ + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + + status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; + mask = PCS_READY; + ready = PCS_READY; + + ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, + PHY_INIT_COMPLETE_TIMEOUT); + if (ret) { + dev_err(qmp->dev, "phy initialization timed-out\n"); + return ret; + } + + return 0; +} + +static int qcom_qmp_phy_ufs_power_off(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qphy->cfg; + + /* PHY reset */ + if (!cfg->no_pcs_sw_reset) + qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + + /* stop SerDes and Phy-Coding-Sublayer */ + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + + /* Put PHY into POWER DOWN state: active low */ + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + cfg->pwrdn_ctrl); + } else { + qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, + cfg->pwrdn_ctrl); + } + + return 0; +} + +static int qcom_qmp_phy_ufs_exit(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + + qcom_qmp_phy_ufs_com_exit(qphy); + + return 0; +} + +static int qcom_qmp_phy_ufs_enable(struct phy *phy) +{ + int ret; + + ret = qcom_qmp_phy_ufs_init(phy); + if (ret) + return ret; + + ret = qcom_qmp_phy_ufs_power_on(phy); + if (ret) + qcom_qmp_phy_ufs_exit(phy); + + return ret; +} + +static int qcom_qmp_phy_ufs_disable(struct phy *phy) +{ + int ret; + + ret = qcom_qmp_phy_ufs_power_off(phy); + if (ret) + return ret; + return qcom_qmp_phy_ufs_exit(phy); +} + +static int qcom_qmp_phy_ufs_set_mode(struct phy *phy, + enum phy_mode mode, int submode) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + + qphy->mode = mode; + + return 0; +} + +static int qcom_qmp_phy_ufs_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) +{ + struct qcom_qmp *qmp = dev_get_drvdata(dev); + int num = cfg->num_vregs; + int i; + + qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); + if (!qmp->vregs) + return -ENOMEM; + + for (i = 0; i < num; i++) + qmp->vregs[i].supply = cfg->vreg_list[i]; + + return devm_regulator_bulk_get(dev, num, qmp->vregs); +} + +static int qcom_qmp_phy_ufs_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) +{ + struct qcom_qmp *qmp = dev_get_drvdata(dev); + int num = cfg->num_clks; + int i; + + qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); + if (!qmp->clks) + return -ENOMEM; + + for (i = 0; i < num; i++) + qmp->clks[i].id = cfg->clk_list[i]; + + return devm_clk_bulk_get(dev, num, qmp->clks); +} + +static const struct phy_ops qcom_qmp_ufs_ops = { + .power_on = qcom_qmp_phy_ufs_enable, + .power_off = qcom_qmp_phy_ufs_disable, + .set_mode = qcom_qmp_phy_ufs_set_mode, + .owner = THIS_MODULE, +}; + +static +int qcom_qmp_phy_ufs_create(struct device *dev, struct device_node *np, int id, + void __iomem *serdes, const struct qmp_phy_cfg *cfg) +{ + struct qcom_qmp *qmp = dev_get_drvdata(dev); + struct phy *generic_phy; + struct qmp_phy *qphy; + int ret; + + qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); + if (!qphy) + return -ENOMEM; + + qphy->cfg = cfg; + qphy->serdes = serdes; + /* + * Get memory resources for each phy lane: + * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. + * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 + * For single lane PHYs: pcs_misc (optional) -> 3. + */ + qphy->tx = of_iomap(np, 0); + if (!qphy->tx) + return -ENOMEM; + + qphy->rx = of_iomap(np, 1); + if (!qphy->rx) + return -ENOMEM; + + qphy->pcs = of_iomap(np, 2); + if (!qphy->pcs) + return -ENOMEM; + + /* + * If this is a dual-lane PHY, then there should be registers for the + * second lane. Some old device trees did not specify this, so fall + * back to old legacy behavior of assuming they can be reached at an + * offset from the first lane. + */ + if (cfg->is_dual_lane_phy) { + qphy->tx2 = of_iomap(np, 3); + qphy->rx2 = of_iomap(np, 4); + if (!qphy->tx2 || !qphy->rx2) { + dev_warn(dev, + "Underspecified device tree, falling back to legacy register regions\n"); + + /* In the old version, pcs_misc is at index 3. */ + qphy->pcs_misc = qphy->tx2; + qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; + qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; + + } else { + qphy->pcs_misc = of_iomap(np, 5); + } + + } else { + qphy->pcs_misc = of_iomap(np, 3); + } + + if (!qphy->pcs_misc) + dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); + + generic_phy = devm_phy_create(dev, np, &qcom_qmp_ufs_ops); + if (IS_ERR(generic_phy)) { + ret = PTR_ERR(generic_phy); + dev_err(dev, "failed to create qphy %d\n", ret); + return ret; + } + + qphy->phy = generic_phy; + qphy->index = id; + qphy->qmp = qmp; + qmp->phys[id] = qphy; + phy_set_drvdata(generic_phy, qphy); + + return 0; +} + +static const struct of_device_id qcom_qmp_phy_ufs_of_match_table[] = { + { + .compatible = "qcom,msm8996-qmp-ufs-phy", + .data = &msm8996_ufs_cfg, + }, { + .compatible = "qcom,msm8998-qmp-ufs-phy", + .data = &sdm845_ufsphy_cfg, + }, { + .compatible = "qcom,sc8180x-qmp-ufs-phy", + .data = &sm8150_ufsphy_cfg, + }, { + .compatible = "qcom,sc8280xp-qmp-ufs-phy", + .data = &sm8350_ufsphy_cfg, + }, { + .compatible = "qcom,sdm845-qmp-ufs-phy", + .data = &sdm845_ufsphy_cfg, + }, { + .compatible = "qcom,sm6115-qmp-ufs-phy", + .data = &sm6115_ufsphy_cfg, + }, { + .compatible = "qcom,sm6350-qmp-ufs-phy", + .data = &sdm845_ufsphy_cfg, + }, { + .compatible = "qcom,sm8150-qmp-ufs-phy", + .data = &sm8150_ufsphy_cfg, + }, { + .compatible = "qcom,sm8250-qmp-ufs-phy", + .data = &sm8150_ufsphy_cfg, + }, { + .compatible = "qcom,sm8350-qmp-ufs-phy", + .data = &sm8350_ufsphy_cfg, + }, { + .compatible = "qcom,sm8450-qmp-ufs-phy", + .data = &sm8450_ufsphy_cfg, + }, + { }, +}; +MODULE_DEVICE_TABLE(of, qcom_qmp_phy_ufs_of_match_table); + +static int qcom_qmp_phy_ufs_probe(struct platform_device *pdev) +{ + struct qcom_qmp *qmp; + struct device *dev = &pdev->dev; + struct device_node *child; + struct phy_provider *phy_provider; + void __iomem *serdes; + const struct qmp_phy_cfg *cfg = NULL; + int num, id; + int ret; + + qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); + if (!qmp) + return -ENOMEM; + + qmp->dev = dev; + dev_set_drvdata(dev, qmp); + + /* Get the specific init parameters of QMP phy */ + cfg = of_device_get_match_data(dev); + if (!cfg) + return -EINVAL; + + /* per PHY serdes; usually located at base address */ + serdes = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(serdes)) + return PTR_ERR(serdes); + + ret = qcom_qmp_phy_ufs_clk_init(dev, cfg); + if (ret) + return ret; + + ret = qcom_qmp_phy_ufs_vreg_init(dev, cfg); + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(dev, "failed to get regulator supplies: %d\n", + ret); + return ret; + } + + num = of_get_available_child_count(dev->of_node); + /* do we have a rogue child node ? */ + if (num > 1) + return -EINVAL; + + qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); + if (!qmp->phys) + return -ENOMEM; + + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + /* + * Prevent runtime pm from being ON by default. Users can enable + * it using power/control in sysfs. + */ + pm_runtime_forbid(dev); + + id = 0; + for_each_available_child_of_node(dev->of_node, child) { + /* Create per-lane phy */ + ret = qcom_qmp_phy_ufs_create(dev, child, id, serdes, cfg); + if (ret) { + dev_err(dev, "failed to create lane%d phy, %d\n", + id, ret); + goto err_node_put; + } + + id++; + } + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (!IS_ERR(phy_provider)) + dev_info(dev, "Registered Qcom-QMP phy\n"); + else + pm_runtime_disable(dev); + + return PTR_ERR_OR_ZERO(phy_provider); + +err_node_put: + pm_runtime_disable(dev); + of_node_put(child); + return ret; +} + +static struct platform_driver qcom_qmp_phy_ufs_driver = { + .probe = qcom_qmp_phy_ufs_probe, + .driver = { + .name = "qcom-qmp-ufs-phy", + .of_match_table = qcom_qmp_phy_ufs_of_match_table, + }, +}; + +module_platform_driver(qcom_qmp_phy_ufs_driver); + +MODULE_AUTHOR("Vivek Gautam "); +MODULE_DESCRIPTION("Qualcomm QMP UFS PHY driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c new file mode 100644 index 000000000000..1d270356a97f --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -0,0 +1,2765 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "phy-qcom-qmp.h" + +/* QPHY_SW_RESET bit */ +#define SW_RESET BIT(0) +/* QPHY_POWER_DOWN_CONTROL */ +#define SW_PWRDN BIT(0) +#define REFCLK_DRV_DSBL BIT(1) +/* QPHY_START_CONTROL bits */ +#define SERDES_START BIT(0) +#define PCS_START BIT(1) +#define PLL_READY_GATE_EN BIT(3) +/* QPHY_PCS_STATUS bit */ +#define PHYSTATUS BIT(6) +#define PHYSTATUS_4_20 BIT(7) +/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ +#define PCS_READY BIT(0) + +/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ +/* DP PHY soft reset */ +#define SW_DPPHY_RESET BIT(0) +/* mux to select DP PHY reset control, 0:HW control, 1: software reset */ +#define SW_DPPHY_RESET_MUX BIT(1) +/* USB3 PHY soft reset */ +#define SW_USB3PHY_RESET BIT(2) +/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ +#define SW_USB3PHY_RESET_MUX BIT(3) + +/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ +#define USB3_MODE BIT(0) /* enables USB3 mode */ +#define DP_MODE BIT(1) /* enables DP mode */ + +/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ +#define ARCVR_DTCT_EN BIT(0) +#define ALFPS_DTCT_EN BIT(1) +#define ARCVR_DTCT_EVENT_SEL BIT(4) + +/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ +#define IRQ_CLEAR BIT(0) + +/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ +#define RCVR_DETECT BIT(0) + +/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ +#define CLAMP_EN BIT(0) /* enables i/o clamp_n */ + +#define PHY_INIT_COMPLETE_TIMEOUT 10000 +#define POWER_DOWN_DELAY_US_MIN 10 +#define POWER_DOWN_DELAY_US_MAX 11 + +#define MAX_PROP_NAME 32 + +/* Define the assumed distance between lanes for underspecified device trees. */ +#define QMP_PHY_LEGACY_LANE_STRIDE 0x400 + +struct qmp_phy_init_tbl { + unsigned int offset; + unsigned int val; + /* + * register part of layout ? + * if yes, then offset gives index in the reg-layout + */ + bool in_layout; + /* + * mask of lanes for which this register is written + * for cases when second lane needs different values + */ + u8 lane_mask; +}; + +#define QMP_PHY_INIT_CFG(o, v) \ + { \ + .offset = o, \ + .val = v, \ + .lane_mask = 0xff, \ + } + +#define QMP_PHY_INIT_CFG_L(o, v) \ + { \ + .offset = o, \ + .val = v, \ + .in_layout = true, \ + .lane_mask = 0xff, \ + } + +#define QMP_PHY_INIT_CFG_LANE(o, v, l) \ + { \ + .offset = o, \ + .val = v, \ + .lane_mask = l, \ + } + +/* set of registers with offsets different per-PHY */ +enum qphy_reg_layout { + /* Common block control registers */ + QPHY_COM_SW_RESET, + QPHY_COM_POWER_DOWN_CONTROL, + QPHY_COM_START_CONTROL, + QPHY_COM_PCS_READY_STATUS, + /* PCS registers */ + QPHY_SW_RESET, + QPHY_START_CTRL, + QPHY_PCS_READY_STATUS, + QPHY_PCS_STATUS, + QPHY_PCS_AUTONOMOUS_MODE_CTRL, + QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, + QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, + QPHY_PCS_POWER_DOWN_CONTROL, + /* PCS_MISC registers */ + QPHY_PCS_MISC_TYPEC_CTRL, + /* Keep last to ensure regs_layout arrays are properly initialized */ + QPHY_LAYOUT_SIZE +}; + +static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = 0x00, + [QPHY_START_CTRL] = 0x08, + [QPHY_PCS_STATUS] = 0x17c, + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4, + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8, + [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178, +}; + +static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = 0x00, + [QPHY_START_CTRL] = 0x08, + [QPHY_PCS_STATUS] = 0x174, + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8, + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc, + [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170, +}; + +static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = 0x00, + [QPHY_START_CTRL] = 0x44, + [QPHY_PCS_STATUS] = 0x14, + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, + + /* In PCS_USB */ + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x008, + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x014, +}; + +static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = 0x00, + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, + [QPHY_START_CTRL] = 0x08, + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8, + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc, + [QPHY_PCS_STATUS] = 0x174, + [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00, +}; + +static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), + /* PLL and Loop filter settings */ + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), + /* SSC settings */ + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), +}; + +static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0), +}; + +static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), +}; + +static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04), + /* PLL and Loop filter settings */ + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), + /* SSC settings */ + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), +}; + +static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), +}; + +static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), +}; + +static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = { + /* FLL settings */ + QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL2, 0x03), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL1, 0x02), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_L, 0x09), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_H_TOL, 0x42), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_MAN_CODE, 0x85), + + /* Lock Det settings */ + QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG2, 0x1f), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG3, 0x47), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG2, 0x08), +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { + /* FLL settings */ + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), + + /* Lock Det settings */ + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), + + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), + + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { + /* FLL settings */ + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), + + /* Lock Det settings */ + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), + + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), + + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), + + QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), +}; + +static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), +}; + +static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), +}; + +static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), +}; + +static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), +}; + +static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), +}; + +static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), +}; + +static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), +}; + +static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { + /* Lock Det settings */ + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), + + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), +}; + +static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), +}; + +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), +}; + +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05), +}; + +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), +}; + +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), +}; + +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_usb_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), +}; + +static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), +}; + +static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), +}; + +static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), +}; + +static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), +}; + +static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), +}; + +static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), +}; + +static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), +}; + +static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_usb_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), +}; + +static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08), +}; + +static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), +}; + +static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b), +}; + +static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), +}; + +static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), +}; + +static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), + QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), + QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), +}; + +static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), +}; + +static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), +}; + +static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), +}; + +static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), +}; + +static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), +}; + +static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), +}; + +static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01), +}; + +static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00), +}; + +static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00), +}; + +static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), +}; + +struct qmp_phy; + +/* struct qmp_phy_cfg - per-PHY initialization config */ +struct qmp_phy_cfg { + /* phy-type - PCIE/UFS/USB */ + unsigned int type; + /* number of lanes provided by phy */ + int nlanes; + + /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_init_tbl *serdes_tbl; + int serdes_tbl_num; + const struct qmp_phy_init_tbl *tx_tbl; + int tx_tbl_num; + const struct qmp_phy_init_tbl *rx_tbl; + int rx_tbl_num; + const struct qmp_phy_init_tbl *pcs_tbl; + int pcs_tbl_num; + const struct qmp_phy_init_tbl *pcs_usb_tbl; + int pcs_usb_tbl_num; + + /* clock ids to be requested */ + const char * const *clk_list; + int num_clks; + /* resets to be requested */ + const char * const *reset_list; + int num_resets; + /* regulators to be requested */ + const char * const *vreg_list; + int num_vregs; + + /* array of registers with different offsets */ + const unsigned int *regs; + + unsigned int start_ctrl; + unsigned int pwrdn_ctrl; + /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ + unsigned int phy_status; + + /* true, if PHY needs delay after POWER_DOWN */ + bool has_pwrdn_delay; + /* power_down delay in usec */ + int pwrdn_delay_min; + int pwrdn_delay_max; + + /* true, if PHY has a separate DP_COM control block */ + bool has_phy_dp_com_ctrl; + /* true, if PHY has secondary tx/rx lanes to be configured */ + bool is_dual_lane_phy; + + /* Offset from PCS to PCS_USB region */ + unsigned int pcs_usb_offset; +}; + +/** + * struct qmp_phy - per-lane phy descriptor + * + * @phy: generic phy + * @cfg: phy specific configuration + * @serdes: iomapped memory space for phy's serdes (i.e. PLL) + * @tx: iomapped memory space for lane's tx + * @rx: iomapped memory space for lane's rx + * @pcs: iomapped memory space for lane's pcs + * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) + * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) + * @pcs_misc: iomapped memory space for lane's pcs_misc + * @pcs_usb: iomapped memory space for lane's pcs_usb + * @pipe_clk: pipe clock + * @index: lane index + * @qmp: QMP phy to which this lane belongs + * @mode: current PHY mode + */ +struct qmp_phy { + struct phy *phy; + const struct qmp_phy_cfg *cfg; + void __iomem *serdes; + void __iomem *tx; + void __iomem *rx; + void __iomem *pcs; + void __iomem *tx2; + void __iomem *rx2; + void __iomem *pcs_misc; + void __iomem *pcs_usb; + struct clk *pipe_clk; + unsigned int index; + struct qcom_qmp *qmp; + enum phy_mode mode; +}; + +/** + * struct qcom_qmp - structure holding QMP phy block attributes + * + * @dev: device + * @dp_com: iomapped memory space for phy's dp_com control block + * + * @clks: array of clocks required by phy + * @resets: array of resets required by phy + * @vregs: regulator supplies bulk data + * + * @phys: array of per-lane phy descriptors + */ +struct qcom_qmp { + struct device *dev; + void __iomem *dp_com; + + struct clk_bulk_data *clks; + struct reset_control_bulk_data *resets; + struct regulator_bulk_data *vregs; + + struct qmp_phy **phys; +}; + +static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) +{ + u32 reg; + + reg = readl(base + offset); + reg |= val; + writel(reg, base + offset); + + /* ensure that above write is through */ + readl(base + offset); +} + +static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) +{ + u32 reg; + + reg = readl(base + offset); + reg &= ~val; + writel(reg, base + offset); + + /* ensure that above write is through */ + readl(base + offset); +} + +/* list of clocks required by phy */ +static const char * const msm8996_phy_clk_l[] = { + "aux", "cfg_ahb", "ref", +}; + +static const char * const qmp_v3_phy_clk_l[] = { + "aux", "cfg_ahb", "ref", "com_aux", +}; + +static const char * const qmp_v4_phy_clk_l[] = { + "aux", "ref_clk_src", "ref", "com_aux", +}; + +/* the primary usb3 phy on sm8250 doesn't have a ref clock */ +static const char * const qmp_v4_sm8250_usbphy_clk_l[] = { + "aux", "ref_clk_src", "com_aux" +}; + +/* usb3 phy on sdx55 doesn't have com_aux clock */ +static const char * const qmp_v4_sdx55_usbphy_clk_l[] = { + "aux", "cfg_ahb", "ref" +}; + +static const char * const qcm2290_usb3phy_clk_l[] = { + "cfg_ahb", "ref", "com_aux", +}; + +/* list of resets */ +static const char * const msm8996_usb3phy_reset_l[] = { + "phy", "common", +}; + +static const char * const sc7180_usb3phy_reset_l[] = { + "phy", +}; + +static const char * const qcm2290_usb3phy_reset_l[] = { + "phy_phy", "phy", +}; + +/* list of regulators */ +static const char * const qmp_phy_vreg_l[] = { + "vdda-phy", "vdda-pll", +}; + +static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = ipq8074_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl), + .tx_tbl = msm8996_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), + .rx_tbl = ipq8074_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl), + .pcs_tbl = ipq8074_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl), + .clk_list = msm8996_phy_clk_l, + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = usb3phy_regs_layout, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, +}; + +static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = msm8996_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl), + .tx_tbl = msm8996_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), + .rx_tbl = msm8996_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl), + .pcs_tbl = msm8996_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl), + .clk_list = msm8996_phy_clk_l, + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = usb3phy_regs_layout, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, +}; + +static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = qmp_v3_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), + .tx_tbl = qmp_v3_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), + .rx_tbl = qmp_v3_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), + .pcs_tbl = qmp_v3_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), + .clk_list = qmp_v3_phy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v3_usb3phy_regs_layout, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, + + .has_phy_dp_com_ctrl = true, + .is_dual_lane_phy = true, +}; + +static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = qmp_v3_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), + .tx_tbl = qmp_v3_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), + .rx_tbl = qmp_v3_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), + .pcs_tbl = qmp_v3_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), + .clk_list = qmp_v3_phy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), + .reset_list = sc7180_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v3_usb3phy_regs_layout, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, + + .has_phy_dp_com_ctrl = true, + .is_dual_lane_phy = true, +}; + +static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl), + .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl), + .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl), + .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl), + .clk_list = qmp_v3_phy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v3_usb3phy_regs_layout, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, +}; + +static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = msm8998_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl), + .tx_tbl = msm8998_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl), + .rx_tbl = msm8998_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl), + .pcs_tbl = msm8998_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl), + .clk_list = msm8996_phy_clk_l, + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v3_usb3phy_regs_layout, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + .is_dual_lane_phy = true, +}; + +static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = sm8150_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), + .tx_tbl = sm8150_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), + .rx_tbl = sm8150_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), + .pcs_tbl = sm8150_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), + .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl, + .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl), + .clk_list = qmp_v4_phy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v4_usb3phy_regs_layout, + .pcs_usb_offset = 0x300, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + + .has_pwrdn_delay = true, + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, + + .has_phy_dp_com_ctrl = true, + .is_dual_lane_phy = true, +}; + +static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), + .tx_tbl = sm8150_usb3_uniphy_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl), + .rx_tbl = sm8150_usb3_uniphy_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl), + .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl), + .pcs_usb_tbl = sm8150_usb3_uniphy_pcs_usb_tbl, + .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_usb_tbl), + .clk_list = qmp_v4_phy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v4_usb3phy_regs_layout, + .pcs_usb_offset = 0x600, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, +}; + +static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = sm8150_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), + .tx_tbl = sm8250_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), + .rx_tbl = sm8250_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), + .pcs_tbl = sm8250_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), + .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl, + .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl), + .clk_list = qmp_v4_sm8250_usbphy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v4_usb3phy_regs_layout, + .pcs_usb_offset = 0x300, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, + + .has_phy_dp_com_ctrl = true, + .is_dual_lane_phy = true, +}; + +static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), + .tx_tbl = sm8250_usb3_uniphy_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl), + .rx_tbl = sm8250_usb3_uniphy_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl), + .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), + .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl, + .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl), + .clk_list = qmp_v4_phy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v4_usb3phy_regs_layout, + .pcs_usb_offset = 0x600, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, +}; + +static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), + .tx_tbl = sdx55_usb3_uniphy_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl), + .rx_tbl = sdx55_usb3_uniphy_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl), + .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), + .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl, + .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl), + .clk_list = qmp_v4_sdx55_usbphy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v4_usb3phy_regs_layout, + .pcs_usb_offset = 0x600, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, +}; + +static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), + .tx_tbl = sdx65_usb3_uniphy_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl), + .rx_tbl = sdx65_usb3_uniphy_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl), + .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), + .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl, + .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl), + .clk_list = qmp_v4_sdx55_usbphy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v4_usb3phy_regs_layout, + .pcs_usb_offset = 0x1000, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, +}; + +static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = sm8150_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), + .tx_tbl = sm8350_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl), + .rx_tbl = sm8350_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl), + .pcs_tbl = sm8350_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl), + .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl, + .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl), + .clk_list = qmp_v4_sm8250_usbphy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v4_usb3phy_regs_layout, + .pcs_usb_offset = 0x300, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, + + .has_phy_dp_com_ctrl = true, + .is_dual_lane_phy = true, +}; + +static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), + .tx_tbl = sm8350_usb3_uniphy_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl), + .rx_tbl = sm8350_usb3_uniphy_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl), + .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), + .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl, + .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl), + .clk_list = qmp_v4_phy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v4_usb3phy_regs_layout, + .pcs_usb_offset = 0x1000, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, +}; + +static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = qcm2290_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), + .tx_tbl = qcm2290_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), + .rx_tbl = qcm2290_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl), + .pcs_tbl = qcm2290_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), + .clk_list = qcm2290_usb3phy_clk_l, + .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l), + .reset_list = qcm2290_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qcm2290_usb3phy_regs_layout, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + .is_dual_lane_phy = true, +}; + +static void qcom_qmp_phy_usb_configure_lane(void __iomem *base, + const unsigned int *regs, + const struct qmp_phy_init_tbl tbl[], + int num, + u8 lane_mask) +{ + int i; + const struct qmp_phy_init_tbl *t = tbl; + + if (!t) + return; + + for (i = 0; i < num; i++, t++) { + if (!(t->lane_mask & lane_mask)) + continue; + + if (t->in_layout) + writel(t->val, base + regs[t->offset]); + else + writel(t->val, base + t->offset); + } +} + +static void qcom_qmp_phy_usb_configure(void __iomem *base, + const unsigned int *regs, + const struct qmp_phy_init_tbl tbl[], + int num) +{ + qcom_qmp_phy_usb_configure_lane(base, regs, tbl, num, 0xff); +} + +static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy) +{ + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *serdes = qphy->serdes; + const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; + int serdes_tbl_num = cfg->serdes_tbl_num; + + qcom_qmp_phy_usb_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); + + return 0; +} + +static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy) +{ + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *pcs = qphy->pcs; + void __iomem *dp_com = qmp->dp_com; + int ret; + + /* turn on regulator supplies */ + ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); + if (ret) { + dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); + return ret; + } + + ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); + if (ret) { + dev_err(qmp->dev, "reset assert failed\n"); + goto err_disable_regulators; + } + + ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); + if (ret) { + dev_err(qmp->dev, "reset deassert failed\n"); + goto err_disable_regulators; + } + + ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); + if (ret) + goto err_assert_reset; + + if (cfg->has_phy_dp_com_ctrl) { + qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, + SW_PWRDN); + /* override hardware control for reset of qmp phy */ + qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, + SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | + SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); + + /* Default type-c orientation, i.e CC1 */ + qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); + + qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, + USB3_MODE | DP_MODE); + + /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ + qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, + SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | + SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); + + qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); + qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); + } + + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) + qphy_setbits(pcs, + cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + cfg->pwrdn_ctrl); + else + qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, + cfg->pwrdn_ctrl); + + return 0; + +err_assert_reset: + reset_control_bulk_assert(cfg->num_resets, qmp->resets); +err_disable_regulators: + regulator_bulk_disable(cfg->num_vregs, qmp->vregs); + + return ret; +} + +static int qcom_qmp_phy_usb_com_exit(struct qmp_phy *qphy) +{ + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + + reset_control_bulk_assert(cfg->num_resets, qmp->resets); + + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); + + regulator_bulk_disable(cfg->num_vregs, qmp->vregs); + + return 0; +} + +static int qcom_qmp_phy_usb_init(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + struct qcom_qmp *qmp = qphy->qmp; + int ret; + dev_vdbg(qmp->dev, "Initializing QMP phy\n"); + + ret = qcom_qmp_phy_usb_com_init(qphy); + if (ret) + return ret; + + return 0; +} + +static int qcom_qmp_phy_usb_power_on(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *tx = qphy->tx; + void __iomem *rx = qphy->rx; + void __iomem *pcs = qphy->pcs; + void __iomem *status; + unsigned int mask, val, ready; + int ret; + + qcom_qmp_phy_usb_serdes_init(qphy); + + ret = clk_prepare_enable(qphy->pipe_clk); + if (ret) { + dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); + return ret; + } + + /* Tx, Rx, and PCS configurations */ + qcom_qmp_phy_usb_configure_lane(tx, cfg->regs, + cfg->tx_tbl, cfg->tx_tbl_num, 1); + + /* Configuration for other LANE for USB-DP combo PHY */ + if (cfg->is_dual_lane_phy) { + qcom_qmp_phy_usb_configure_lane(qphy->tx2, cfg->regs, + cfg->tx_tbl, cfg->tx_tbl_num, 2); + } + + qcom_qmp_phy_usb_configure_lane(rx, cfg->regs, + cfg->rx_tbl, cfg->rx_tbl_num, 1); + + if (cfg->is_dual_lane_phy) { + qcom_qmp_phy_usb_configure_lane(qphy->rx2, cfg->regs, + cfg->rx_tbl, cfg->rx_tbl_num, 2); + } + + /* Configure link rate, swing, etc. */ + qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); + + if (cfg->has_pwrdn_delay) + usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); + + /* Pull PHY out of reset state */ + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + + /* start SerDes and Phy-Coding-Sublayer */ + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + + status = pcs + cfg->regs[QPHY_PCS_STATUS]; + mask = cfg->phy_status; + ready = 0; + + ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, + PHY_INIT_COMPLETE_TIMEOUT); + if (ret) { + dev_err(qmp->dev, "phy initialization timed-out\n"); + goto err_disable_pipe_clk; + } + + return 0; + +err_disable_pipe_clk: + clk_disable_unprepare(qphy->pipe_clk); + + return ret; +} + +static int qcom_qmp_phy_usb_power_off(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qphy->cfg; + + clk_disable_unprepare(qphy->pipe_clk); + + /* PHY reset */ + qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + + /* stop SerDes and Phy-Coding-Sublayer */ + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + + /* Put PHY into POWER DOWN state: active low */ + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + cfg->pwrdn_ctrl); + } else { + qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, + cfg->pwrdn_ctrl); + } + + return 0; +} + +static int qcom_qmp_phy_usb_exit(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + + qcom_qmp_phy_usb_com_exit(qphy); + + return 0; +} + +static int qcom_qmp_phy_usb_enable(struct phy *phy) +{ + int ret; + + ret = qcom_qmp_phy_usb_init(phy); + if (ret) + return ret; + + ret = qcom_qmp_phy_usb_power_on(phy); + if (ret) + qcom_qmp_phy_usb_exit(phy); + + return ret; +} + +static int qcom_qmp_phy_usb_disable(struct phy *phy) +{ + int ret; + + ret = qcom_qmp_phy_usb_power_off(phy); + if (ret) + return ret; + return qcom_qmp_phy_usb_exit(phy); +} + +static int qcom_qmp_phy_usb_set_mode(struct phy *phy, + enum phy_mode mode, int submode) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + + qphy->mode = mode; + + return 0; +} + +static void qcom_qmp_phy_usb_enable_autonomous_mode(struct qmp_phy *qphy) +{ + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs; + void __iomem *pcs_misc = qphy->pcs_misc; + u32 intr_mask; + + if (qphy->mode == PHY_MODE_USB_HOST_SS || + qphy->mode == PHY_MODE_USB_DEVICE_SS) + intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; + else + intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; + + /* Clear any pending interrupts status */ + qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); + /* Writing 1 followed by 0 clears the interrupt */ + qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); + + qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], + ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); + + /* Enable required PHY autonomous mode interrupts */ + qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); + + /* Enable i/o clamp_n for autonomous mode */ + if (pcs_misc) + qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); +} + +static void qcom_qmp_phy_usb_disable_autonomous_mode(struct qmp_phy *qphy) +{ + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs; + void __iomem *pcs_misc = qphy->pcs_misc; + + /* Disable i/o clamp_n on resume for normal mode */ + if (pcs_misc) + qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); + + qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], + ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); + + qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); + /* Writing 1 followed by 0 clears the interrupt */ + qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); +} + +static int __maybe_unused qcom_qmp_phy_usb_runtime_suspend(struct device *dev) +{ + struct qcom_qmp *qmp = dev_get_drvdata(dev); + struct qmp_phy *qphy = qmp->phys[0]; + const struct qmp_phy_cfg *cfg = qphy->cfg; + + dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); + + /* Supported only for USB3 PHY and luckily USB3 is the first phy */ + if (cfg->type != PHY_TYPE_USB3) + return 0; + + if (!qphy->phy->init_count) { + dev_vdbg(dev, "PHY not initialized, bailing out\n"); + return 0; + } + + qcom_qmp_phy_usb_enable_autonomous_mode(qphy); + + clk_disable_unprepare(qphy->pipe_clk); + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); + + return 0; +} + +static int __maybe_unused qcom_qmp_phy_usb_runtime_resume(struct device *dev) +{ + struct qcom_qmp *qmp = dev_get_drvdata(dev); + struct qmp_phy *qphy = qmp->phys[0]; + const struct qmp_phy_cfg *cfg = qphy->cfg; + int ret = 0; + + dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); + + /* Supported only for USB3 PHY and luckily USB3 is the first phy */ + if (cfg->type != PHY_TYPE_USB3) + return 0; + + if (!qphy->phy->init_count) { + dev_vdbg(dev, "PHY not initialized, bailing out\n"); + return 0; + } + + ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); + if (ret) + return ret; + + ret = clk_prepare_enable(qphy->pipe_clk); + if (ret) { + dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); + return ret; + } + + qcom_qmp_phy_usb_disable_autonomous_mode(qphy); + + return 0; +} + +static int qcom_qmp_phy_usb_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) +{ + struct qcom_qmp *qmp = dev_get_drvdata(dev); + int num = cfg->num_vregs; + int i; + + qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); + if (!qmp->vregs) + return -ENOMEM; + + for (i = 0; i < num; i++) + qmp->vregs[i].supply = cfg->vreg_list[i]; + + return devm_regulator_bulk_get(dev, num, qmp->vregs); +} + +static int qcom_qmp_phy_usb_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) +{ + struct qcom_qmp *qmp = dev_get_drvdata(dev); + int i; + int ret; + + qmp->resets = devm_kcalloc(dev, cfg->num_resets, + sizeof(*qmp->resets), GFP_KERNEL); + if (!qmp->resets) + return -ENOMEM; + + for (i = 0; i < cfg->num_resets; i++) + qmp->resets[i].id = cfg->reset_list[i]; + + ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); + if (ret) + return dev_err_probe(dev, ret, "failed to get resets\n"); + + return 0; +} + +static int qcom_qmp_phy_usb_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) +{ + struct qcom_qmp *qmp = dev_get_drvdata(dev); + int num = cfg->num_clks; + int i; + + qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); + if (!qmp->clks) + return -ENOMEM; + + for (i = 0; i < num; i++) + qmp->clks[i].id = cfg->clk_list[i]; + + return devm_clk_bulk_get(dev, num, qmp->clks); +} + +static void phy_clk_release_provider(void *res) +{ + of_clk_del_provider(res); +} + +/* + * Register a fixed rate pipe clock. + * + * The _pipe_clksrc generated by PHY goes to the GCC that gate + * controls it. The _pipe_clk coming out of the GCC is requested + * by the PHY driver for its operations. + * We register the _pipe_clksrc here. The gcc driver takes care + * of assigning this _pipe_clksrc as parent to _pipe_clk. + * Below picture shows this relationship. + * + * +---------------+ + * | PHY block |<<---------------------------------------+ + * | | | + * | +-------+ | +-----+ | + * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ + * clk | +-------+ | +-----+ + * +---------------+ + */ +static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) +{ + struct clk_fixed_rate *fixed; + struct clk_init_data init = { }; + int ret; + + ret = of_property_read_string(np, "clock-output-names", &init.name); + if (ret) { + dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); + return ret; + } + + fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); + if (!fixed) + return -ENOMEM; + + init.ops = &clk_fixed_rate_ops; + + /* controllers using QMP phys use 125MHz pipe clock interface */ + fixed->fixed_rate = 125000000; + fixed->hw.init = &init; + + ret = devm_clk_hw_register(qmp->dev, &fixed->hw); + if (ret) + return ret; + + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); + if (ret) + return ret; + + /* + * Roll a devm action because the clock provider is the child node, but + * the child node is not actually a device. + */ + return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); +} + +static const struct phy_ops qcom_qmp_phy_usb_ops = { + .init = qcom_qmp_phy_usb_enable, + .exit = qcom_qmp_phy_usb_disable, + .set_mode = qcom_qmp_phy_usb_set_mode, + .owner = THIS_MODULE, +}; + +static +int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id, + void __iomem *serdes, const struct qmp_phy_cfg *cfg) +{ + struct qcom_qmp *qmp = dev_get_drvdata(dev); + struct phy *generic_phy; + struct qmp_phy *qphy; + char prop_name[MAX_PROP_NAME]; + int ret; + + qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); + if (!qphy) + return -ENOMEM; + + qphy->cfg = cfg; + qphy->serdes = serdes; + /* + * Get memory resources for each phy lane: + * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. + * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 + * For single lane PHYs: pcs_misc (optional) -> 3. + */ + qphy->tx = of_iomap(np, 0); + if (!qphy->tx) + return -ENOMEM; + + qphy->rx = of_iomap(np, 1); + if (!qphy->rx) + return -ENOMEM; + + qphy->pcs = of_iomap(np, 2); + if (!qphy->pcs) + return -ENOMEM; + + if (cfg->pcs_usb_offset) + qphy->pcs_usb = qphy->pcs + cfg->pcs_usb_offset; + + /* + * If this is a dual-lane PHY, then there should be registers for the + * second lane. Some old device trees did not specify this, so fall + * back to old legacy behavior of assuming they can be reached at an + * offset from the first lane. + */ + if (cfg->is_dual_lane_phy) { + qphy->tx2 = of_iomap(np, 3); + qphy->rx2 = of_iomap(np, 4); + if (!qphy->tx2 || !qphy->rx2) { + dev_warn(dev, + "Underspecified device tree, falling back to legacy register regions\n"); + + /* In the old version, pcs_misc is at index 3. */ + qphy->pcs_misc = qphy->tx2; + qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; + qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; + + } else { + qphy->pcs_misc = of_iomap(np, 5); + } + + } else { + qphy->pcs_misc = of_iomap(np, 3); + } + + if (!qphy->pcs_misc) + dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); + + snprintf(prop_name, sizeof(prop_name), "pipe%d", id); + qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); + if (IS_ERR(qphy->pipe_clk)) { + return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), + "failed to get lane%d pipe clock\n", id); + } + + generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_usb_ops); + if (IS_ERR(generic_phy)) { + ret = PTR_ERR(generic_phy); + dev_err(dev, "failed to create qphy %d\n", ret); + return ret; + } + + qphy->phy = generic_phy; + qphy->index = id; + qphy->qmp = qmp; + qmp->phys[id] = qphy; + phy_set_drvdata(generic_phy, qphy); + + return 0; +} + +static const struct of_device_id qcom_qmp_phy_usb_of_match_table[] = { + { + .compatible = "qcom,ipq8074-qmp-usb3-phy", + .data = &ipq8074_usb3phy_cfg, + }, { + .compatible = "qcom,msm8996-qmp-usb3-phy", + .data = &msm8996_usb3phy_cfg, + }, { + .compatible = "qcom,ipq6018-qmp-usb3-phy", + .data = &ipq8074_usb3phy_cfg, + }, { + .compatible = "qcom,sc7180-qmp-usb3-phy", + .data = &sc7180_usb3phy_cfg, + }, { + .compatible = "qcom,sc8180x-qmp-usb3-phy", + .data = &sm8150_usb3phy_cfg, + }, { + .compatible = "qcom,sdm845-qmp-usb3-phy", + .data = &qmp_v3_usb3phy_cfg, + }, { + .compatible = "qcom,sdm845-qmp-usb3-uni-phy", + .data = &qmp_v3_usb3_uniphy_cfg, + }, { + .compatible = "qcom,msm8998-qmp-usb3-phy", + .data = &msm8998_usb3phy_cfg, + }, { + .compatible = "qcom,sm8150-qmp-usb3-phy", + .data = &sm8150_usb3phy_cfg, + }, { + .compatible = "qcom,sm8150-qmp-usb3-uni-phy", + .data = &sm8150_usb3_uniphy_cfg, + }, { + .compatible = "qcom,sm8250-qmp-usb3-phy", + .data = &sm8250_usb3phy_cfg, + }, { + .compatible = "qcom,sm8250-qmp-usb3-uni-phy", + .data = &sm8250_usb3_uniphy_cfg, + }, { + .compatible = "qcom,sdx55-qmp-usb3-uni-phy", + .data = &sdx55_usb3_uniphy_cfg, + }, { + .compatible = "qcom,sdx65-qmp-usb3-uni-phy", + .data = &sdx65_usb3_uniphy_cfg, + }, { + .compatible = "qcom,sm8350-qmp-usb3-phy", + .data = &sm8350_usb3phy_cfg, + }, { + .compatible = "qcom,sm8350-qmp-usb3-uni-phy", + .data = &sm8350_usb3_uniphy_cfg, + }, { + .compatible = "qcom,sm8450-qmp-usb3-phy", + .data = &sm8350_usb3phy_cfg, + }, { + .compatible = "qcom,qcm2290-qmp-usb3-phy", + .data = &qcm2290_usb3phy_cfg, + }, + { }, +}; +MODULE_DEVICE_TABLE(of, qcom_qmp_phy_usb_of_match_table); + +static const struct dev_pm_ops qcom_qmp_phy_usb_pm_ops = { + SET_RUNTIME_PM_OPS(qcom_qmp_phy_usb_runtime_suspend, + qcom_qmp_phy_usb_runtime_resume, NULL) +}; + +static int qcom_qmp_phy_usb_probe(struct platform_device *pdev) +{ + struct qcom_qmp *qmp; + struct device *dev = &pdev->dev; + struct device_node *child; + struct phy_provider *phy_provider; + void __iomem *serdes; + const struct qmp_phy_cfg *cfg = NULL; + int num, id; + int ret; + + qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); + if (!qmp) + return -ENOMEM; + + qmp->dev = dev; + dev_set_drvdata(dev, qmp); + + /* Get the specific init parameters of QMP phy */ + cfg = of_device_get_match_data(dev); + if (!cfg) + return -EINVAL; + + /* per PHY serdes; usually located at base address */ + serdes = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(serdes)) + return PTR_ERR(serdes); + + /* per PHY dp_com; if PHY has dp_com control block */ + if (cfg->has_phy_dp_com_ctrl) { + qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(qmp->dp_com)) + return PTR_ERR(qmp->dp_com); + } + + ret = qcom_qmp_phy_usb_clk_init(dev, cfg); + if (ret) + return ret; + + ret = qcom_qmp_phy_usb_reset_init(dev, cfg); + if (ret) + return ret; + + ret = qcom_qmp_phy_usb_vreg_init(dev, cfg); + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(dev, "failed to get regulator supplies: %d\n", + ret); + return ret; + } + + num = of_get_available_child_count(dev->of_node); + /* do we have a rogue child node ? */ + if (num > 1) + return -EINVAL; + + qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); + if (!qmp->phys) + return -ENOMEM; + + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + /* + * Prevent runtime pm from being ON by default. Users can enable + * it using power/control in sysfs. + */ + pm_runtime_forbid(dev); + + id = 0; + for_each_available_child_of_node(dev->of_node, child) { + /* Create per-lane phy */ + ret = qcom_qmp_phy_usb_create(dev, child, id, serdes, cfg); + if (ret) { + dev_err(dev, "failed to create lane%d phy, %d\n", + id, ret); + goto err_node_put; + } + + /* + * Register the pipe clock provided by phy. + * See function description to see details of this pipe clock. + */ + ret = phy_pipe_clk_register(qmp, child); + if (ret) { + dev_err(qmp->dev, + "failed to register pipe clock source\n"); + goto err_node_put; + } + + id++; + } + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (!IS_ERR(phy_provider)) + dev_info(dev, "Registered Qcom-QMP phy\n"); + else + pm_runtime_disable(dev); + + return PTR_ERR_OR_ZERO(phy_provider); + +err_node_put: + pm_runtime_disable(dev); + of_node_put(child); + return ret; +} + +static struct platform_driver qcom_qmp_phy_usb_driver = { + .probe = qcom_qmp_phy_usb_probe, + .driver = { + .name = "qcom-qmp-usb-phy", + .pm = &qcom_qmp_phy_usb_pm_ops, + .of_match_table = qcom_qmp_phy_usb_of_match_table, + }, +}; + +module_platform_driver(qcom_qmp_phy_usb_driver); + +MODULE_AUTHOR("Vivek Gautam "); +MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c deleted file mode 100644 index c7309e981bfb..000000000000 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ /dev/null @@ -1,6350 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2017, The Linux Foundation. All rights reserved. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "phy-qcom-qmp.h" - -/* QPHY_SW_RESET bit */ -#define SW_RESET BIT(0) -/* QPHY_POWER_DOWN_CONTROL */ -#define SW_PWRDN BIT(0) -#define REFCLK_DRV_DSBL BIT(1) -/* QPHY_START_CONTROL bits */ -#define SERDES_START BIT(0) -#define PCS_START BIT(1) -#define PLL_READY_GATE_EN BIT(3) -/* QPHY_PCS_STATUS bit */ -#define PHYSTATUS BIT(6) -#define PHYSTATUS_4_20 BIT(7) -/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ -#define PCS_READY BIT(0) - -/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ -/* DP PHY soft reset */ -#define SW_DPPHY_RESET BIT(0) -/* mux to select DP PHY reset control, 0:HW control, 1: software reset */ -#define SW_DPPHY_RESET_MUX BIT(1) -/* USB3 PHY soft reset */ -#define SW_USB3PHY_RESET BIT(2) -/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ -#define SW_USB3PHY_RESET_MUX BIT(3) - -/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ -#define USB3_MODE BIT(0) /* enables USB3 mode */ -#define DP_MODE BIT(1) /* enables DP mode */ - -/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ -#define ARCVR_DTCT_EN BIT(0) -#define ALFPS_DTCT_EN BIT(1) -#define ARCVR_DTCT_EVENT_SEL BIT(4) - -/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ -#define IRQ_CLEAR BIT(0) - -/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ -#define RCVR_DETECT BIT(0) - -/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ -#define CLAMP_EN BIT(0) /* enables i/o clamp_n */ - -#define PHY_INIT_COMPLETE_TIMEOUT 10000 -#define POWER_DOWN_DELAY_US_MIN 10 -#define POWER_DOWN_DELAY_US_MAX 11 - -#define MAX_PROP_NAME 32 - -/* Define the assumed distance between lanes for underspecified device trees. */ -#define QMP_PHY_LEGACY_LANE_STRIDE 0x400 - -struct qmp_phy_init_tbl { - unsigned int offset; - unsigned int val; - /* - * register part of layout ? - * if yes, then offset gives index in the reg-layout - */ - bool in_layout; - /* - * mask of lanes for which this register is written - * for cases when second lane needs different values - */ - u8 lane_mask; -}; - -#define QMP_PHY_INIT_CFG(o, v) \ - { \ - .offset = o, \ - .val = v, \ - .lane_mask = 0xff, \ - } - -#define QMP_PHY_INIT_CFG_L(o, v) \ - { \ - .offset = o, \ - .val = v, \ - .in_layout = true, \ - .lane_mask = 0xff, \ - } - -#define QMP_PHY_INIT_CFG_LANE(o, v, l) \ - { \ - .offset = o, \ - .val = v, \ - .lane_mask = l, \ - } - -/* set of registers with offsets different per-PHY */ -enum qphy_reg_layout { - /* Common block control registers */ - QPHY_COM_SW_RESET, - QPHY_COM_POWER_DOWN_CONTROL, - QPHY_COM_START_CONTROL, - QPHY_COM_PCS_READY_STATUS, - /* PCS registers */ - QPHY_PLL_LOCK_CHK_DLY_TIME, - QPHY_FLL_CNTRL1, - QPHY_FLL_CNTRL2, - QPHY_FLL_CNT_VAL_L, - QPHY_FLL_CNT_VAL_H_TOL, - QPHY_FLL_MAN_CODE, - QPHY_SW_RESET, - QPHY_START_CTRL, - QPHY_PCS_READY_STATUS, - QPHY_PCS_STATUS, - QPHY_PCS_AUTONOMOUS_MODE_CTRL, - QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, - QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, - QPHY_PCS_POWER_DOWN_CONTROL, - /* PCS_MISC registers */ - QPHY_PCS_MISC_TYPEC_CTRL, - /* Keep last to ensure regs_layout arrays are properly initialized */ - QPHY_LAYOUT_SIZE -}; - -static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_START_CTRL] = 0x00, - [QPHY_PCS_READY_STATUS] = 0x168, -}; - -static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_SW_RESET] = 0x00, - [QPHY_START_CTRL] = 0x44, - [QPHY_PCS_STATUS] = 0x14, - [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, -}; - -static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_COM_SW_RESET] = 0x400, - [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, - [QPHY_COM_START_CONTROL] = 0x408, - [QPHY_COM_PCS_READY_STATUS] = 0x448, - [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8, - [QPHY_FLL_CNTRL1] = 0xc4, - [QPHY_FLL_CNTRL2] = 0xc8, - [QPHY_FLL_CNT_VAL_L] = 0xcc, - [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0, - [QPHY_FLL_MAN_CODE] = 0xd4, - [QPHY_SW_RESET] = 0x00, - [QPHY_START_CTRL] = 0x08, - [QPHY_PCS_STATUS] = 0x174, -}; - -static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_FLL_CNTRL1] = 0xc0, - [QPHY_FLL_CNTRL2] = 0xc4, - [QPHY_FLL_CNT_VAL_L] = 0xc8, - [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc, - [QPHY_FLL_MAN_CODE] = 0xd0, - [QPHY_SW_RESET] = 0x00, - [QPHY_START_CTRL] = 0x08, - [QPHY_PCS_STATUS] = 0x17c, - [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4, - [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8, - [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178, -}; - -static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_SW_RESET] = 0x00, - [QPHY_START_CTRL] = 0x08, - [QPHY_PCS_STATUS] = 0x174, - [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8, - [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc, - [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170, -}; - -static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_SW_RESET] = 0x00, - [QPHY_START_CTRL] = 0x08, - [QPHY_PCS_STATUS] = 0x174, -}; - -static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_SW_RESET] = 0x00, - [QPHY_START_CTRL] = 0x08, - [QPHY_PCS_STATUS] = 0x2ac, -}; - -static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_SW_RESET] = 0x00, - [QPHY_START_CTRL] = 0x44, - [QPHY_PCS_STATUS] = 0x14, - [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, - [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308, - [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314, -}; - -static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_SW_RESET] = 0x00, - [QPHY_START_CTRL] = 0x44, - [QPHY_PCS_STATUS] = 0x14, - [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, - [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608, - [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614, -}; - -static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_SW_RESET] = 0x00, - [QPHY_START_CTRL] = 0x44, - [QPHY_PCS_STATUS] = 0x14, - [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, - [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008, - [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014, -}; - -static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_SW_RESET] = 0x00, - [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, - [QPHY_START_CTRL] = 0x08, - [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8, - [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc, - [QPHY_PCS_STATUS] = 0x174, - [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00, -}; - -static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_START_CTRL] = 0x00, - [QPHY_PCS_READY_STATUS] = 0x160, -}; - -static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_START_CTRL] = 0x00, - [QPHY_PCS_READY_STATUS] = 0x168, -}; - -static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_SW_RESET] = 0x00, - [QPHY_START_CTRL] = 0x44, - [QPHY_PCS_STATUS] = 0x14, - [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, -}; - -static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START, - [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS, - [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET, -}; - -static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), - QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), - /* PLL and Loop filter settings */ - QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), - QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), - /* SSC settings */ - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), -}; - -static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0), -}; - -static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), -}; - -static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), - QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09), - QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), - QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04), - QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), - QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40), -}; - -static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), - QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), -}; - -static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19), -}; - -static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c), - QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00), - QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), - - QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05), - - QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05), - QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02), - QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00), - QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3), - QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e), -}; - -static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), -}; - -static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), -}; - -static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), -}; - -static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), -}; - -static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), - QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), - QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05), - QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10), - QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), - QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54), - QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), - QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), -}; - -static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), - QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), -}; - -static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), -}; - -static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), - QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), - QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), - QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04), - /* PLL and Loop filter settings */ - QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), - QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), - /* SSC settings */ - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), -}; - -static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), - QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), - QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), -}; - -static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), -}; - -static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = { - /* FLL settings */ - QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03), - QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02), - QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09), - QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42), - QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85), - - /* Lock Det settings */ - QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1), - QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f), - QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47), - QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08), -}; - -static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), - QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), - QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), - QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), - QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), - QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), - QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), - QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), - QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), - QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), - QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), - QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), - QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), - QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), - QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), - QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), - QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), - QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), - QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), - QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), - QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), - QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), - QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), - QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), - QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), - QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), - QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), - QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), - QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), - QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), - QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), - QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), - QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), - QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), - QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), - QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), - QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), - QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), - QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), -}; - -static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02), - QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06), - QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12), -}; - -static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02), - QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70), - QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61), - QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04), - QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e), - QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0), - QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00), - QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), - QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), - QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c), - QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03), - QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14), - QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0), - QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01), - QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f), - QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3), - QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40), - QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01), - QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02), - QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8), - QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09), - QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1), - QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00), - QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02), - QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8), - QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09), - QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1), - QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04), -}; - -static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { - QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01), - QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d), - QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10), - QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa), - QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), - QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01), - QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01), - QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), - QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07), - QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), - QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), - QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), - QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), - QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11), - QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00), - QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58), -}; - -static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), - QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), - QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), - QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), - QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), - QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), - QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), -}; - -static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), - QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), - QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), - QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), - QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36), - QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), -}; - -static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), -}; - -static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4), - QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0), - QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), - QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), - QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), - QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), - QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), - QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73), - QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99), - QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15), - QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe), - QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0), - QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), -}; - -static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), -}; - -static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), -}; - -static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), -}; - -static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), - - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), - - QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), - - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), - - QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), -}; - -static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), -}; - -static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), -}; - -static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), -}; - -static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = { -}; - -static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), - QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), -}; - -static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), -}; - -static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), -}; - -static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), -}; - -static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), -}; - -static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), -}; - -static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), -}; - -static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), -}; - -static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), -}; - -static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), -}; - -static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { - /* FLL settings */ - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), - - /* Lock Det settings */ - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), - - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), - - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), -}; - -static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), -}; - -static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), -}; - -static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), -}; - -static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { - /* FLL settings */ - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), - - /* Lock Det settings */ - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), - - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), - - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), - - QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), -}; - -static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), - QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), - QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), - QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04), - QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), - QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), - - /* Rate B */ - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), -}; - -static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), - QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), -}; - -static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), -}; - -static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15), - QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d), - QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f), - QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02), - QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), - QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03), - QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12), - QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f), - QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */ -}; - -static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f), - - /* Rate B */ - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), -}; - -static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), -}; - -static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), -}; - -static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02), -}; - -static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), -}; - -static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), -}; - -static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), -}; - -static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), -}; - -static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), - - /* Rate B */ - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), -}; - -static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), -}; - -static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), - -}; - -static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), -}; - -static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), -}; - -static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), -}; - -static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), -}; - -static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { - /* Lock Det settings */ - QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), - - QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), -}; - -static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), -}; - -static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05), -}; - -static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), -}; - -static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), -}; - -static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), - QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), - QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), -}; - -static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), - QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), - QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), - QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), - QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), -}; - -static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), -}; - -static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), -}; - -static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), -}; - -static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), -}; - -static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), -}; - -static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), -}; - -static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), -}; - -static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), -}; - -static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), -}; - -static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), -}; - -static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), -}; - -static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), -}; - -static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), -}; - -static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), -}; - -static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), -}; - -static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), -}; - -static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), -}; - -static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), -}; - -static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), -}; - -static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), -}; - -static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), -}; - -static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), -}; - -static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), -}; - -static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), -}; - -static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), -}; - -static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), -}; - -static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), -}; - -static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), -}; - -static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), - QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08), -}; - -static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), -}; - -static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), -}; - -static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), - QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), - QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), -}; - -static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), - QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), -}; - -static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), - QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), - QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), - QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), -}; - -static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), - QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), - QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), - QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), - QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), - QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), - QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), -}; - -static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b), -}; - -static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), -}; - -static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), - - /* Rate B */ - QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), -}; - -static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c), -}; - -static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), -}; - -static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), -}; - -static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), -}; - -static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), - QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), - QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), -}; - -static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), -}; - -static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), -}; - -static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), -}; - -static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), -}; - -static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), - QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), - QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), - QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), - QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01), -}; - -static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00), -}; - -static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00), -}; - -static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), -}; - -static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), -}; - -static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), -}; - -static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), -}; - -static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), -}; - -static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), -}; - -static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), -}; - -static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), - QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), - QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), -}; - -static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), - - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), - - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), - - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), - - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), -}; - -/* Register names should be validated, they might be different for this PHY */ -static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99), -}; - -static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), - QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), - QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), - QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), - QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), - QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), -}; - -struct qmp_phy; - -/* struct qmp_phy_cfg - per-PHY initialization config */ -struct qmp_phy_cfg { - /* phy-type - PCIE/UFS/USB */ - unsigned int type; - /* number of lanes provided by phy */ - int nlanes; - - /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ - const struct qmp_phy_init_tbl *serdes_tbl; - int serdes_tbl_num; - const struct qmp_phy_init_tbl *serdes_tbl_sec; - int serdes_tbl_num_sec; - const struct qmp_phy_init_tbl *tx_tbl; - int tx_tbl_num; - const struct qmp_phy_init_tbl *tx_tbl_sec; - int tx_tbl_num_sec; - const struct qmp_phy_init_tbl *rx_tbl; - int rx_tbl_num; - const struct qmp_phy_init_tbl *rx_tbl_sec; - int rx_tbl_num_sec; - const struct qmp_phy_init_tbl *pcs_tbl; - int pcs_tbl_num; - const struct qmp_phy_init_tbl *pcs_tbl_sec; - int pcs_tbl_num_sec; - const struct qmp_phy_init_tbl *pcs_misc_tbl; - int pcs_misc_tbl_num; - const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; - int pcs_misc_tbl_num_sec; - - /* Init sequence for DP PHY block link rates */ - const struct qmp_phy_init_tbl *serdes_tbl_rbr; - int serdes_tbl_rbr_num; - const struct qmp_phy_init_tbl *serdes_tbl_hbr; - int serdes_tbl_hbr_num; - const struct qmp_phy_init_tbl *serdes_tbl_hbr2; - int serdes_tbl_hbr2_num; - const struct qmp_phy_init_tbl *serdes_tbl_hbr3; - int serdes_tbl_hbr3_num; - - /* DP PHY callbacks */ - int (*configure_dp_phy)(struct qmp_phy *qphy); - void (*configure_dp_tx)(struct qmp_phy *qphy); - int (*calibrate_dp_phy)(struct qmp_phy *qphy); - void (*dp_aux_init)(struct qmp_phy *qphy); - - /* clock ids to be requested */ - const char * const *clk_list; - int num_clks; - /* resets to be requested */ - const char * const *reset_list; - int num_resets; - /* regulators to be requested */ - const char * const *vreg_list; - int num_vregs; - - /* array of registers with different offsets */ - const unsigned int *regs; - - unsigned int start_ctrl; - unsigned int pwrdn_ctrl; - unsigned int mask_com_pcs_ready; - /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ - unsigned int phy_status; - - /* true, if PHY has a separate PHY_COM control block */ - bool has_phy_com_ctrl; - /* true, if PHY has a reset for individual lanes */ - bool has_lane_rst; - /* true, if PHY needs delay after POWER_DOWN */ - bool has_pwrdn_delay; - /* power_down delay in usec */ - int pwrdn_delay_min; - int pwrdn_delay_max; - - /* true, if PHY has a separate DP_COM control block */ - bool has_phy_dp_com_ctrl; - /* true, if PHY has secondary tx/rx lanes to be configured */ - bool is_dual_lane_phy; - - /* true, if PCS block has no separate SW_RESET register */ - bool no_pcs_sw_reset; -}; - -struct qmp_phy_combo_cfg { - const struct qmp_phy_cfg *usb_cfg; - const struct qmp_phy_cfg *dp_cfg; -}; - -/** - * struct qmp_phy - per-lane phy descriptor - * - * @phy: generic phy - * @cfg: phy specific configuration - * @serdes: iomapped memory space for phy's serdes (i.e. PLL) - * @tx: iomapped memory space for lane's tx - * @rx: iomapped memory space for lane's rx - * @pcs: iomapped memory space for lane's pcs - * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) - * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) - * @pcs_misc: iomapped memory space for lane's pcs_misc - * @pipe_clk: pipe clock - * @index: lane index - * @qmp: QMP phy to which this lane belongs - * @lane_rst: lane's reset controller - * @mode: current PHY mode - * @dp_aux_cfg: Display port aux config - * @dp_opts: Display port optional config - * @dp_clks: Display port clocks - */ -struct qmp_phy { - struct phy *phy; - const struct qmp_phy_cfg *cfg; - void __iomem *serdes; - void __iomem *tx; - void __iomem *rx; - void __iomem *pcs; - void __iomem *tx2; - void __iomem *rx2; - void __iomem *pcs_misc; - struct clk *pipe_clk; - unsigned int index; - struct qcom_qmp *qmp; - struct reset_control *lane_rst; - enum phy_mode mode; - unsigned int dp_aux_cfg; - struct phy_configure_opts_dp dp_opts; - struct qmp_phy_dp_clks *dp_clks; -}; - -struct qmp_phy_dp_clks { - struct qmp_phy *qphy; - struct clk_hw dp_link_hw; - struct clk_hw dp_pixel_hw; -}; - -/** - * struct qcom_qmp - structure holding QMP phy block attributes - * - * @dev: device - * @dp_com: iomapped memory space for phy's dp_com control block - * - * @clks: array of clocks required by phy - * @resets: array of resets required by phy - * @vregs: regulator supplies bulk data - * - * @phys: array of per-lane phy descriptors - * @phy_mutex: mutex lock for PHY common block initialization - * @init_count: phy common block initialization count - * @ufs_reset: optional UFS PHY reset handle - */ -struct qcom_qmp { - struct device *dev; - void __iomem *dp_com; - - struct clk_bulk_data *clks; - struct reset_control **resets; - struct regulator_bulk_data *vregs; - - struct qmp_phy **phys; - - struct mutex phy_mutex; - int init_count; - - struct reset_control *ufs_reset; -}; - -static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy); -static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy); -static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy); -static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy); - -static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy); -static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy); -static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy); -static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy); - -static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) -{ - u32 reg; - - reg = readl(base + offset); - reg |= val; - writel(reg, base + offset); - - /* ensure that above write is through */ - readl(base + offset); -} - -static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) -{ - u32 reg; - - reg = readl(base + offset); - reg &= ~val; - writel(reg, base + offset); - - /* ensure that above write is through */ - readl(base + offset); -} - -/* list of clocks required by phy */ -static const char * const msm8996_phy_clk_l[] = { - "aux", "cfg_ahb", "ref", -}; - -static const char * const msm8996_ufs_phy_clk_l[] = { - "ref", -}; - -static const char * const qmp_v3_phy_clk_l[] = { - "aux", "cfg_ahb", "ref", "com_aux", -}; - -static const char * const sdm845_pciephy_clk_l[] = { - "aux", "cfg_ahb", "ref", "refgen", -}; - -static const char * const qmp_v4_phy_clk_l[] = { - "aux", "ref_clk_src", "ref", "com_aux", -}; - -/* the primary usb3 phy on sm8250 doesn't have a ref clock */ -static const char * const qmp_v4_sm8250_usbphy_clk_l[] = { - "aux", "ref_clk_src", "com_aux" -}; - -static const char * const sm8450_ufs_phy_clk_l[] = { - "qref", "ref", "ref_aux", -}; - -static const char * const sdm845_ufs_phy_clk_l[] = { - "ref", "ref_aux", -}; - -/* usb3 phy on sdx55 doesn't have com_aux clock */ -static const char * const qmp_v4_sdx55_usbphy_clk_l[] = { - "aux", "cfg_ahb", "ref" -}; - -static const char * const qcm2290_usb3phy_clk_l[] = { - "cfg_ahb", "ref", "com_aux", -}; - -/* list of resets */ -static const char * const msm8996_pciephy_reset_l[] = { - "phy", "common", "cfg", -}; - -static const char * const msm8996_usb3phy_reset_l[] = { - "phy", "common", -}; - -static const char * const sc7180_usb3phy_reset_l[] = { - "phy", -}; - -static const char * const qcm2290_usb3phy_reset_l[] = { - "phy_phy", "phy", -}; - -static const char * const sdm845_pciephy_reset_l[] = { - "phy", -}; - -/* list of regulators */ -static const char * const qmp_phy_vreg_l[] = { - "vdda-phy", "vdda-pll", -}; - -static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { - .type = PHY_TYPE_USB3, - .nlanes = 1, - - .serdes_tbl = ipq8074_usb3_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl), - .tx_tbl = msm8996_usb3_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), - .rx_tbl = ipq8074_usb3_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl), - .pcs_tbl = ipq8074_usb3_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl), - .clk_list = msm8996_phy_clk_l, - .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), - .reset_list = msm8996_usb3phy_reset_l, - .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = usb3phy_regs_layout, - - .start_ctrl = SERDES_START | PCS_START, - .pwrdn_ctrl = SW_PWRDN, - .phy_status = PHYSTATUS, -}; - -static const struct qmp_phy_cfg msm8996_pciephy_cfg = { - .type = PHY_TYPE_PCIE, - .nlanes = 3, - - .serdes_tbl = msm8996_pcie_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl), - .tx_tbl = msm8996_pcie_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl), - .rx_tbl = msm8996_pcie_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl), - .pcs_tbl = msm8996_pcie_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl), - .clk_list = msm8996_phy_clk_l, - .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), - .reset_list = msm8996_pciephy_reset_l, - .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = pciephy_regs_layout, - - .start_ctrl = PCS_START | PLL_READY_GATE_EN, - .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, - .mask_com_pcs_ready = PCS_READY, - .phy_status = PHYSTATUS, - - .has_phy_com_ctrl = true, - .has_lane_rst = true, - .has_pwrdn_delay = true, - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, -}; - -static const struct qmp_phy_cfg msm8996_ufs_cfg = { - .type = PHY_TYPE_UFS, - .nlanes = 1, - - .serdes_tbl = msm8996_ufs_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl), - .tx_tbl = msm8996_ufs_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl), - .rx_tbl = msm8996_ufs_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl), - - .clk_list = msm8996_ufs_phy_clk_l, - .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l), - - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - - .regs = msm8996_ufsphy_regs_layout, - - .start_ctrl = SERDES_START, - .pwrdn_ctrl = SW_PWRDN, - .phy_status = PHYSTATUS, - - .no_pcs_sw_reset = true, -}; - -static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { - .type = PHY_TYPE_USB3, - .nlanes = 1, - - .serdes_tbl = msm8996_usb3_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl), - .tx_tbl = msm8996_usb3_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), - .rx_tbl = msm8996_usb3_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl), - .pcs_tbl = msm8996_usb3_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl), - .clk_list = msm8996_phy_clk_l, - .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), - .reset_list = msm8996_usb3phy_reset_l, - .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = usb3phy_regs_layout, - - .start_ctrl = SERDES_START | PCS_START, - .pwrdn_ctrl = SW_PWRDN, - .phy_status = PHYSTATUS, -}; - -static const char * const ipq8074_pciephy_clk_l[] = { - "aux", "cfg_ahb", -}; -/* list of resets */ -static const char * const ipq8074_pciephy_reset_l[] = { - "phy", "common", -}; - -static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { - .type = PHY_TYPE_PCIE, - .nlanes = 1, - - .serdes_tbl = ipq8074_pcie_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), - .tx_tbl = ipq8074_pcie_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), - .rx_tbl = ipq8074_pcie_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), - .pcs_tbl = ipq8074_pcie_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), - .clk_list = ipq8074_pciephy_clk_l, - .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), - .reset_list = ipq8074_pciephy_reset_l, - .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), - .vreg_list = NULL, - .num_vregs = 0, - .regs = pciephy_regs_layout, - - .start_ctrl = SERDES_START | PCS_START, - .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, - .phy_status = PHYSTATUS, - - .has_phy_com_ctrl = false, - .has_lane_rst = false, - .has_pwrdn_delay = true, - .pwrdn_delay_min = 995, /* us */ - .pwrdn_delay_max = 1005, /* us */ -}; - -static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { - .type = PHY_TYPE_PCIE, - .nlanes = 1, - - .serdes_tbl = ipq6018_pcie_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), - .tx_tbl = ipq6018_pcie_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), - .rx_tbl = ipq6018_pcie_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), - .pcs_tbl = ipq6018_pcie_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), - .clk_list = ipq8074_pciephy_clk_l, - .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), - .reset_list = ipq8074_pciephy_reset_l, - .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), - .vreg_list = NULL, - .num_vregs = 0, - .regs = ipq_pciephy_gen3_regs_layout, - - .start_ctrl = SERDES_START | PCS_START, - .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, - - .has_phy_com_ctrl = false, - .has_lane_rst = false, - .has_pwrdn_delay = true, - .pwrdn_delay_min = 995, /* us */ - .pwrdn_delay_max = 1005, /* us */ -}; - -static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { - .type = PHY_TYPE_PCIE, - .nlanes = 1, - - .serdes_tbl = sdm845_qmp_pcie_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), - .tx_tbl = sdm845_qmp_pcie_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), - .rx_tbl = sdm845_qmp_pcie_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), - .pcs_tbl = sdm845_qmp_pcie_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), - .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl, - .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), - .clk_list = sdm845_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), - .reset_list = sdm845_pciephy_reset_l, - .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sdm845_qmp_pciephy_regs_layout, - - .start_ctrl = PCS_START | SERDES_START, - .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, - .phy_status = PHYSTATUS, - - .has_pwrdn_delay = true, - .pwrdn_delay_min = 995, /* us */ - .pwrdn_delay_max = 1005, /* us */ -}; - -static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { - .type = PHY_TYPE_PCIE, - .nlanes = 1, - - .serdes_tbl = sdm845_qhp_pcie_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), - .tx_tbl = sdm845_qhp_pcie_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), - .rx_tbl = sdm845_qhp_pcie_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), - .pcs_tbl = sdm845_qhp_pcie_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), - .clk_list = sdm845_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), - .reset_list = sdm845_pciephy_reset_l, - .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sdm845_qhp_pciephy_regs_layout, - - .start_ctrl = PCS_START | SERDES_START, - .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, - .phy_status = PHYSTATUS, - - .has_pwrdn_delay = true, - .pwrdn_delay_min = 995, /* us */ - .pwrdn_delay_max = 1005, /* us */ -}; - -static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { - .type = PHY_TYPE_PCIE, - .nlanes = 1, - - .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), - .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl, - .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), - .tx_tbl = sm8250_qmp_pcie_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), - .rx_tbl = sm8250_qmp_pcie_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), - .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl, - .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), - .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), - .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl, - .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), - .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, - .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), - .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, - .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), - .clk_list = sdm845_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), - .reset_list = sdm845_pciephy_reset_l, - .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8250_pcie_regs_layout, - - .start_ctrl = PCS_START | SERDES_START, - .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, - .phy_status = PHYSTATUS, - - .has_pwrdn_delay = true, - .pwrdn_delay_min = 995, /* us */ - .pwrdn_delay_max = 1005, /* us */ -}; - -static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { - .type = PHY_TYPE_PCIE, - .nlanes = 2, - - .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), - .tx_tbl = sm8250_qmp_pcie_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), - .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl, - .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), - .rx_tbl = sm8250_qmp_pcie_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), - .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl, - .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), - .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), - .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl, - .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), - .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, - .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), - .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, - .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), - .clk_list = sdm845_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), - .reset_list = sdm845_pciephy_reset_l, - .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8250_pcie_regs_layout, - - .start_ctrl = PCS_START | SERDES_START, - .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, - .phy_status = PHYSTATUS, - - .is_dual_lane_phy = true, - .has_pwrdn_delay = true, - .pwrdn_delay_min = 995, /* us */ - .pwrdn_delay_max = 1005, /* us */ -}; - -static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { - .type = PHY_TYPE_USB3, - .nlanes = 1, - - .serdes_tbl = qmp_v3_usb3_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), - .tx_tbl = qmp_v3_usb3_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), - .rx_tbl = qmp_v3_usb3_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), - .pcs_tbl = qmp_v3_usb3_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), - .clk_list = qmp_v3_phy_clk_l, - .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), - .reset_list = msm8996_usb3phy_reset_l, - .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = qmp_v3_usb3phy_regs_layout, - - .start_ctrl = SERDES_START | PCS_START, - .pwrdn_ctrl = SW_PWRDN, - .phy_status = PHYSTATUS, - - .has_pwrdn_delay = true, - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, - - .has_phy_dp_com_ctrl = true, - .is_dual_lane_phy = true, -}; - -static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { - .type = PHY_TYPE_USB3, - .nlanes = 1, - - .serdes_tbl = qmp_v3_usb3_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), - .tx_tbl = qmp_v3_usb3_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), - .rx_tbl = qmp_v3_usb3_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), - .pcs_tbl = qmp_v3_usb3_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), - .clk_list = qmp_v3_phy_clk_l, - .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), - .reset_list = sc7180_usb3phy_reset_l, - .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = qmp_v3_usb3phy_regs_layout, - - .start_ctrl = SERDES_START | PCS_START, - .pwrdn_ctrl = SW_PWRDN, - .phy_status = PHYSTATUS, - - .has_pwrdn_delay = true, - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, - - .has_phy_dp_com_ctrl = true, - .is_dual_lane_phy = true, -}; - -static const struct qmp_phy_cfg sc7180_dpphy_cfg = { - .type = PHY_TYPE_DP, - .nlanes = 1, - - .serdes_tbl = qmp_v3_dp_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), - .tx_tbl = qmp_v3_dp_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), - - .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, - .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), - .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, - .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), - .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, - .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), - .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, - .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), - - .clk_list = qmp_v3_phy_clk_l, - .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), - .reset_list = sc7180_usb3phy_reset_l, - .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = qmp_v3_usb3phy_regs_layout, - - .has_phy_dp_com_ctrl = true, - .is_dual_lane_phy = true, - - .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init, - .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx, - .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy, - .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate, -}; - -static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = { - .usb_cfg = &sc7180_usb3phy_cfg, - .dp_cfg = &sc7180_dpphy_cfg, -}; - -static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { - .type = PHY_TYPE_USB3, - .nlanes = 1, - - .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl), - .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl), - .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl), - .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl), - .clk_list = qmp_v3_phy_clk_l, - .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), - .reset_list = msm8996_usb3phy_reset_l, - .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = qmp_v3_usb3phy_regs_layout, - - .start_ctrl = SERDES_START | PCS_START, - .pwrdn_ctrl = SW_PWRDN, - .phy_status = PHYSTATUS, - - .has_pwrdn_delay = true, - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, -}; - -static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { - .type = PHY_TYPE_UFS, - .nlanes = 2, - - .serdes_tbl = sdm845_ufsphy_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl), - .tx_tbl = sdm845_ufsphy_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl), - .rx_tbl = sdm845_ufsphy_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl), - .pcs_tbl = sdm845_ufsphy_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl), - .clk_list = sdm845_ufs_phy_clk_l, - .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sdm845_ufsphy_regs_layout, - - .start_ctrl = SERDES_START, - .pwrdn_ctrl = SW_PWRDN, - .phy_status = PHYSTATUS, - - .is_dual_lane_phy = true, - .no_pcs_sw_reset = true, -}; - -static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { - .type = PHY_TYPE_UFS, - .nlanes = 1, - - .serdes_tbl = sm6115_ufsphy_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl), - .tx_tbl = sm6115_ufsphy_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl), - .rx_tbl = sm6115_ufsphy_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl), - .pcs_tbl = sm6115_ufsphy_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl), - .clk_list = sdm845_ufs_phy_clk_l, - .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm6115_ufsphy_regs_layout, - - .start_ctrl = SERDES_START, - .pwrdn_ctrl = SW_PWRDN, - - .is_dual_lane_phy = false, - .no_pcs_sw_reset = true, -}; - -static const struct qmp_phy_cfg msm8998_pciephy_cfg = { - .type = PHY_TYPE_PCIE, - .nlanes = 1, - - .serdes_tbl = msm8998_pcie_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), - .tx_tbl = msm8998_pcie_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), - .rx_tbl = msm8998_pcie_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), - .pcs_tbl = msm8998_pcie_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), - .clk_list = msm8996_phy_clk_l, - .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), - .reset_list = ipq8074_pciephy_reset_l, - .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = pciephy_regs_layout, - - .start_ctrl = SERDES_START | PCS_START, - .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, - .phy_status = PHYSTATUS, -}; - -static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { - .type = PHY_TYPE_USB3, - .nlanes = 1, - - .serdes_tbl = msm8998_usb3_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl), - .tx_tbl = msm8998_usb3_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl), - .rx_tbl = msm8998_usb3_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl), - .pcs_tbl = msm8998_usb3_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl), - .clk_list = msm8996_phy_clk_l, - .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), - .reset_list = msm8996_usb3phy_reset_l, - .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = qmp_v3_usb3phy_regs_layout, - - .start_ctrl = SERDES_START | PCS_START, - .pwrdn_ctrl = SW_PWRDN, - .phy_status = PHYSTATUS, - - .is_dual_lane_phy = true, -}; - -static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { - .type = PHY_TYPE_UFS, - .nlanes = 2, - - .serdes_tbl = sm8150_ufsphy_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl), - .tx_tbl = sm8150_ufsphy_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl), - .rx_tbl = sm8150_ufsphy_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl), - .pcs_tbl = sm8150_ufsphy_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl), - .clk_list = sdm845_ufs_phy_clk_l, - .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8150_ufsphy_regs_layout, - - .start_ctrl = SERDES_START, - .pwrdn_ctrl = SW_PWRDN, - .phy_status = PHYSTATUS, - - .is_dual_lane_phy = true, -}; - -static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { - .type = PHY_TYPE_USB3, - .nlanes = 1, - - .serdes_tbl = sm8150_usb3_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), - .tx_tbl = sm8150_usb3_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), - .rx_tbl = sm8150_usb3_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), - .pcs_tbl = sm8150_usb3_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), - .clk_list = qmp_v4_phy_clk_l, - .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), - .reset_list = msm8996_usb3phy_reset_l, - .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = qmp_v4_usb3phy_regs_layout, - - .start_ctrl = SERDES_START | PCS_START, - .pwrdn_ctrl = SW_PWRDN, - .phy_status = PHYSTATUS, - - - .has_pwrdn_delay = true, - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, - - .has_phy_dp_com_ctrl = true, - .is_dual_lane_phy = true, -}; - -static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { - .type = PHY_TYPE_PCIE, - .nlanes = 1, - - .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), - .tx_tbl = sc8180x_qmp_pcie_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), - .rx_tbl = sc8180x_qmp_pcie_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), - .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), - .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl, - .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), - .clk_list = sdm845_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), - .reset_list = sdm845_pciephy_reset_l, - .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8250_pcie_regs_layout, - - .start_ctrl = PCS_START | SERDES_START, - .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, - - .has_pwrdn_delay = true, - .pwrdn_delay_min = 995, /* us */ - .pwrdn_delay_max = 1005, /* us */ -}; - -static const struct qmp_phy_cfg sc8180x_dpphy_cfg = { - .type = PHY_TYPE_DP, - .nlanes = 1, - - .serdes_tbl = qmp_v4_dp_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), - .tx_tbl = qmp_v4_dp_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), - - .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, - .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), - .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, - .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), - .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, - .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), - .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, - .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), - - .clk_list = qmp_v3_phy_clk_l, - .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), - .reset_list = sc7180_usb3phy_reset_l, - .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = qmp_v3_usb3phy_regs_layout, - - .has_phy_dp_com_ctrl = true, - .is_dual_lane_phy = true, - - .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, - .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, - .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, - .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, -}; - -static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = { - .usb_cfg = &sm8150_usb3phy_cfg, - .dp_cfg = &sc8180x_dpphy_cfg, -}; - -static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { - .type = PHY_TYPE_USB3, - .nlanes = 1, - - .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), - .tx_tbl = sm8150_usb3_uniphy_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl), - .rx_tbl = sm8150_usb3_uniphy_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl), - .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl), - .clk_list = qmp_v4_phy_clk_l, - .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), - .reset_list = msm8996_usb3phy_reset_l, - .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = qmp_v4_usb3_uniphy_regs_layout, - - .start_ctrl = SERDES_START | PCS_START, - .pwrdn_ctrl = SW_PWRDN, - .phy_status = PHYSTATUS, - - .has_pwrdn_delay = true, - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, -}; - -static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { - .type = PHY_TYPE_USB3, - .nlanes = 1, - - .serdes_tbl = sm8150_usb3_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), - .tx_tbl = sm8250_usb3_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), - .rx_tbl = sm8250_usb3_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), - .pcs_tbl = sm8250_usb3_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), - .clk_list = qmp_v4_sm8250_usbphy_clk_l, - .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), - .reset_list = msm8996_usb3phy_reset_l, - .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = qmp_v4_usb3phy_regs_layout, - - .start_ctrl = SERDES_START | PCS_START, - .pwrdn_ctrl = SW_PWRDN, - .phy_status = PHYSTATUS, - - .has_pwrdn_delay = true, - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, - - .has_phy_dp_com_ctrl = true, - .is_dual_lane_phy = true, -}; - -static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { - .type = PHY_TYPE_USB3, - .nlanes = 1, - - .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), - .tx_tbl = sm8250_usb3_uniphy_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl), - .rx_tbl = sm8250_usb3_uniphy_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl), - .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), - .clk_list = qmp_v4_phy_clk_l, - .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), - .reset_list = msm8996_usb3phy_reset_l, - .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = qmp_v4_usb3_uniphy_regs_layout, - - .start_ctrl = SERDES_START | PCS_START, - .pwrdn_ctrl = SW_PWRDN, - .phy_status = PHYSTATUS, - - .has_pwrdn_delay = true, - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, -}; - -static const struct qmp_phy_cfg sm8250_dpphy_cfg = { - .type = PHY_TYPE_DP, - .nlanes = 1, - - .serdes_tbl = qmp_v4_dp_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), - .tx_tbl = qmp_v4_dp_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), - - .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, - .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), - .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, - .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), - .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, - .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), - .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, - .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), - - .clk_list = qmp_v4_phy_clk_l, - .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), - .reset_list = msm8996_usb3phy_reset_l, - .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = qmp_v4_usb3phy_regs_layout, - - .has_phy_dp_com_ctrl = true, - .is_dual_lane_phy = true, - - .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, - .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, - .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, - .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, -}; - -static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = { - .usb_cfg = &sm8250_usb3phy_cfg, - .dp_cfg = &sm8250_dpphy_cfg, -}; - -static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { - .type = PHY_TYPE_USB3, - .nlanes = 1, - - .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), - .tx_tbl = sdx55_usb3_uniphy_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl), - .rx_tbl = sdx55_usb3_uniphy_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl), - .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), - .clk_list = qmp_v4_sdx55_usbphy_clk_l, - .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), - .reset_list = msm8996_usb3phy_reset_l, - .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = qmp_v4_usb3_uniphy_regs_layout, - - .start_ctrl = SERDES_START | PCS_START, - .pwrdn_ctrl = SW_PWRDN, - .phy_status = PHYSTATUS, - - .has_pwrdn_delay = true, - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, -}; - -static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { - .type = PHY_TYPE_PCIE, - .nlanes = 2, - - .serdes_tbl = sdx55_qmp_pcie_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), - .tx_tbl = sdx55_qmp_pcie_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), - .rx_tbl = sdx55_qmp_pcie_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), - .pcs_tbl = sdx55_qmp_pcie_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), - .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl, - .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), - .clk_list = sdm845_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), - .reset_list = sdm845_pciephy_reset_l, - .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8250_pcie_regs_layout, - - .start_ctrl = PCS_START | SERDES_START, - .pwrdn_ctrl = SW_PWRDN, - .phy_status = PHYSTATUS_4_20, - - .is_dual_lane_phy = true, - .has_pwrdn_delay = true, - .pwrdn_delay_min = 995, /* us */ - .pwrdn_delay_max = 1005, /* us */ -}; - -static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { - .type = PHY_TYPE_USB3, - .nlanes = 1, - - .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), - .tx_tbl = sdx65_usb3_uniphy_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl), - .rx_tbl = sdx65_usb3_uniphy_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl), - .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), - .clk_list = qmp_v4_sdx55_usbphy_clk_l, - .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), - .reset_list = msm8996_usb3phy_reset_l, - .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8350_usb3_uniphy_regs_layout, - - .start_ctrl = SERDES_START | PCS_START, - .pwrdn_ctrl = SW_PWRDN, - .phy_status = PHYSTATUS, - - .has_pwrdn_delay = true, - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, -}; - -static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { - .type = PHY_TYPE_UFS, - .nlanes = 2, - - .serdes_tbl = sm8350_ufsphy_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), - .tx_tbl = sm8350_ufsphy_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), - .rx_tbl = sm8350_ufsphy_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), - .pcs_tbl = sm8350_ufsphy_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), - .clk_list = sdm845_ufs_phy_clk_l, - .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8150_ufsphy_regs_layout, - - .start_ctrl = SERDES_START, - .pwrdn_ctrl = SW_PWRDN, - .phy_status = PHYSTATUS, - - .is_dual_lane_phy = true, -}; - -static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { - .type = PHY_TYPE_USB3, - .nlanes = 1, - - .serdes_tbl = sm8150_usb3_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), - .tx_tbl = sm8350_usb3_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl), - .rx_tbl = sm8350_usb3_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl), - .pcs_tbl = sm8350_usb3_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl), - .clk_list = qmp_v4_sm8250_usbphy_clk_l, - .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), - .reset_list = msm8996_usb3phy_reset_l, - .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = qmp_v4_usb3phy_regs_layout, - - .start_ctrl = SERDES_START | PCS_START, - .pwrdn_ctrl = SW_PWRDN, - .phy_status = PHYSTATUS, - - .has_pwrdn_delay = true, - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, - - .has_phy_dp_com_ctrl = true, - .is_dual_lane_phy = true, -}; - -static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { - .type = PHY_TYPE_USB3, - .nlanes = 1, - - .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), - .tx_tbl = sm8350_usb3_uniphy_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl), - .rx_tbl = sm8350_usb3_uniphy_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl), - .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), - .clk_list = qmp_v4_phy_clk_l, - .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), - .reset_list = msm8996_usb3phy_reset_l, - .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8350_usb3_uniphy_regs_layout, - - .start_ctrl = SERDES_START | PCS_START, - .pwrdn_ctrl = SW_PWRDN, - .phy_status = PHYSTATUS, - - .has_pwrdn_delay = true, - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, -}; - -static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { - .type = PHY_TYPE_UFS, - .nlanes = 2, - - .serdes_tbl = sm8350_ufsphy_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), - .tx_tbl = sm8350_ufsphy_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), - .rx_tbl = sm8350_ufsphy_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), - .pcs_tbl = sm8350_ufsphy_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), - .clk_list = sm8450_ufs_phy_clk_l, - .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8150_ufsphy_regs_layout, - - .start_ctrl = SERDES_START, - .pwrdn_ctrl = SW_PWRDN, - .phy_status = PHYSTATUS, - - .is_dual_lane_phy = true, -}; - -static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { - .type = PHY_TYPE_PCIE, - .nlanes = 1, - - .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), - .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), - .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), - .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), - .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, - .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), - .clk_list = sdm845_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), - .reset_list = sdm845_pciephy_reset_l, - .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8250_pcie_regs_layout, - - .start_ctrl = SERDES_START | PCS_START, - .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, - .phy_status = PHYSTATUS, - - .has_pwrdn_delay = true, - .pwrdn_delay_min = 995, /* us */ - .pwrdn_delay_max = 1005, /* us */ -}; - -static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { - .type = PHY_TYPE_PCIE, - .nlanes = 2, - - .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), - .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), - .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), - .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), - .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, - .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), - .clk_list = sdm845_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), - .reset_list = sdm845_pciephy_reset_l, - .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8250_pcie_regs_layout, - - .start_ctrl = SERDES_START | PCS_START, - .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, - .phy_status = PHYSTATUS_4_20, - - .is_dual_lane_phy = true, - .has_pwrdn_delay = true, - .pwrdn_delay_min = 995, /* us */ - .pwrdn_delay_max = 1005, /* us */ -}; - -static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { - .type = PHY_TYPE_USB3, - .nlanes = 1, - - .serdes_tbl = qcm2290_usb3_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), - .tx_tbl = qcm2290_usb3_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), - .rx_tbl = qcm2290_usb3_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl), - .pcs_tbl = qcm2290_usb3_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), - .clk_list = qcm2290_usb3phy_clk_l, - .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l), - .reset_list = qcm2290_usb3phy_reset_l, - .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = qcm2290_usb3phy_regs_layout, - - .start_ctrl = SERDES_START | PCS_START, - .pwrdn_ctrl = SW_PWRDN, - .phy_status = PHYSTATUS, - - .is_dual_lane_phy = true, -}; - -static void qcom_qmp_phy_configure_lane(void __iomem *base, - const unsigned int *regs, - const struct qmp_phy_init_tbl tbl[], - int num, - u8 lane_mask) -{ - int i; - const struct qmp_phy_init_tbl *t = tbl; - - if (!t) - return; - - for (i = 0; i < num; i++, t++) { - if (!(t->lane_mask & lane_mask)) - continue; - - if (t->in_layout) - writel(t->val, base + regs[t->offset]); - else - writel(t->val, base + t->offset); - } -} - -static void qcom_qmp_phy_configure(void __iomem *base, - const unsigned int *regs, - const struct qmp_phy_init_tbl tbl[], - int num) -{ - qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff); -} - -static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy) -{ - struct qcom_qmp *qmp = qphy->qmp; - const struct qmp_phy_cfg *cfg = qphy->cfg; - void __iomem *serdes = qphy->serdes; - const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; - const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; - int serdes_tbl_num = cfg->serdes_tbl_num; - int ret; - - qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); - if (cfg->serdes_tbl_sec) - qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, - cfg->serdes_tbl_num_sec); - - if (cfg->type == PHY_TYPE_DP) { - switch (dp_opts->link_rate) { - case 1620: - qcom_qmp_phy_configure(serdes, cfg->regs, - cfg->serdes_tbl_rbr, - cfg->serdes_tbl_rbr_num); - break; - case 2700: - qcom_qmp_phy_configure(serdes, cfg->regs, - cfg->serdes_tbl_hbr, - cfg->serdes_tbl_hbr_num); - break; - case 5400: - qcom_qmp_phy_configure(serdes, cfg->regs, - cfg->serdes_tbl_hbr2, - cfg->serdes_tbl_hbr2_num); - break; - case 8100: - qcom_qmp_phy_configure(serdes, cfg->regs, - cfg->serdes_tbl_hbr3, - cfg->serdes_tbl_hbr3_num); - break; - default: - /* Other link rates aren't supported */ - return -EINVAL; - } - } - - - if (cfg->has_phy_com_ctrl) { - void __iomem *status; - unsigned int mask, val; - - qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); - qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], - SERDES_START | PCS_START); - - status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; - mask = cfg->mask_com_pcs_ready; - - ret = readl_poll_timeout(status, val, (val & mask), 10, - PHY_INIT_COMPLETE_TIMEOUT); - if (ret) { - dev_err(qmp->dev, - "phy common block init timed-out\n"); - return ret; - } - } - - return 0; -} - -static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy) -{ - writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | - DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, - qphy->pcs + QSERDES_DP_PHY_PD_CTL); - - /* Turn on BIAS current for PHY/PLL */ - writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | - QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, - qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); - - writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); - - writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | - DP_PHY_PD_CTL_LANE_0_1_PWRDN | - DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | - DP_PHY_PD_CTL_DP_CLAMP_EN, - qphy->pcs + QSERDES_DP_PHY_PD_CTL); - - writel(QSERDES_V3_COM_BIAS_EN | - QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | - QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | - QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, - qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); - - writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); - writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); - writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); - writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); - writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); - writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); - writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); - writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); - writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); - writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); - qphy->dp_aux_cfg = 0; - - writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | - PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | - PHY_AUX_REQ_ERR_MASK, - qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); -} - -static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { - { 0x00, 0x0c, 0x15, 0x1a }, - { 0x02, 0x0e, 0x16, 0xff }, - { 0x02, 0x11, 0xff, 0xff }, - { 0x04, 0xff, 0xff, 0xff } -}; - -static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { - { 0x02, 0x12, 0x16, 0x1a }, - { 0x09, 0x19, 0x1f, 0xff }, - { 0x10, 0x1f, 0xff, 0xff }, - { 0x1f, 0xff, 0xff, 0xff } -}; - -static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { - { 0x00, 0x0c, 0x14, 0x19 }, - { 0x00, 0x0b, 0x12, 0xff }, - { 0x00, 0x0b, 0xff, 0xff }, - { 0x04, 0xff, 0xff, 0xff } -}; - -static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { - { 0x08, 0x0f, 0x16, 0x1f }, - { 0x11, 0x1e, 0x1f, 0xff }, - { 0x19, 0x1f, 0xff, 0xff }, - { 0x1f, 0xff, 0xff, 0xff } -}; - -static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy, - unsigned int drv_lvl_reg, unsigned int emp_post_reg) -{ - const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; - unsigned int v_level = 0, p_level = 0; - u8 voltage_swing_cfg, pre_emphasis_cfg; - int i; - - for (i = 0; i < dp_opts->lanes; i++) { - v_level = max(v_level, dp_opts->voltage[i]); - p_level = max(p_level, dp_opts->pre[i]); - } - - if (dp_opts->link_rate <= 2700) { - voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level]; - pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level]; - } else { - voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level]; - pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level]; - } - - /* TODO: Move check to config check */ - if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) - return -EINVAL; - - /* Enable MUX to use Cursor values from these registers */ - voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; - pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; - - writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg); - writel(pre_emphasis_cfg, qphy->tx + emp_post_reg); - writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg); - writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg); - - return 0; -} - -static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy) -{ - const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; - u32 bias_en, drvr_en; - - if (qcom_qmp_phy_configure_dp_swing(qphy, - QSERDES_V3_TX_TX_DRV_LVL, - QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0) - return; - - if (dp_opts->lanes == 1) { - bias_en = 0x3e; - drvr_en = 0x13; - } else { - bias_en = 0x3f; - drvr_en = 0x10; - } - - writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); - writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); - writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); - writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); -} - -static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy) -{ - u32 val; - bool reverse = false; - - val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | - DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; - - /* - * TODO: Assume orientation is CC1 for now and two lanes, need to - * use type-c connector to understand orientation and lanes. - * - * Otherwise val changes to be like below if this code understood - * the orientation of the type-c cable. - * - * if (lane_cnt == 4 || orientation == ORIENTATION_CC2) - * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; - * if (lane_cnt == 4 || orientation == ORIENTATION_CC1) - * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; - * if (orientation == ORIENTATION_CC2) - * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); - */ - val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; - writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL); - - writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE); - - return reverse; -} - -static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) -{ - const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; - const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; - u32 phy_vco_div, status; - unsigned long pixel_freq; - - qcom_qmp_phy_configure_dp_mode(qphy); - - writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); - writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); - - switch (dp_opts->link_rate) { - case 1620: - phy_vco_div = 0x1; - pixel_freq = 1620000000UL / 2; - break; - case 2700: - phy_vco_div = 0x1; - pixel_freq = 2700000000UL / 2; - break; - case 5400: - phy_vco_div = 0x2; - pixel_freq = 5400000000UL / 4; - break; - case 8100: - phy_vco_div = 0x0; - pixel_freq = 8100000000UL / 6; - break; - default: - /* Other link rates aren't supported */ - return -EINVAL; - } - writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV); - - clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); - clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); - - writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); - writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); - writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); - writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); - writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); - - writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL); - - if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS, - status, - ((status & BIT(0)) > 0), - 500, - 10000)) - return -ETIMEDOUT; - - writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); - - if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, - status, - ((status & BIT(1)) > 0), - 500, - 10000)) - return -ETIMEDOUT; - - writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); - udelay(2000); - writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); - - return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, - status, - ((status & BIT(1)) > 0), - 500, - 10000); -} - -/* - * We need to calibrate the aux setting here as many times - * as the caller tries - */ -static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy) -{ - static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; - u8 val; - - qphy->dp_aux_cfg++; - qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); - val = cfg1_settings[qphy->dp_aux_cfg]; - - writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); - - return 0; -} - -static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy) -{ - writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | - DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, - qphy->pcs + QSERDES_DP_PHY_PD_CTL); - - /* Turn on BIAS current for PHY/PLL */ - writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); - - writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); - writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); - writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); - writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); - writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); - writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); - writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); - writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); - writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); - writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); - qphy->dp_aux_cfg = 0; - - writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | - PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | - PHY_AUX_REQ_ERR_MASK, - qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); -} - -static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy) -{ - /* Program default values before writing proper values */ - writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); - writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); - - writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); - writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); - - qcom_qmp_phy_configure_dp_swing(qphy, - QSERDES_V4_TX_TX_DRV_LVL, - QSERDES_V4_TX_TX_EMP_POST1_LVL); -} - -static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy) -{ - const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; - const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; - u32 phy_vco_div, status; - unsigned long pixel_freq; - u32 bias0_en, drvr0_en, bias1_en, drvr1_en; - bool reverse; - - writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1); - - reverse = qcom_qmp_phy_configure_dp_mode(qphy); - - writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); - writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); - - writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); - writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); - - switch (dp_opts->link_rate) { - case 1620: - phy_vco_div = 0x1; - pixel_freq = 1620000000UL / 2; - break; - case 2700: - phy_vco_div = 0x1; - pixel_freq = 2700000000UL / 2; - break; - case 5400: - phy_vco_div = 0x2; - pixel_freq = 5400000000UL / 4; - break; - case 8100: - phy_vco_div = 0x0; - pixel_freq = 8100000000UL / 6; - break; - default: - /* Other link rates aren't supported */ - return -EINVAL; - } - writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV); - - clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); - clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); - - writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); - writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); - writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); - writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); - - writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL); - - if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS, - status, - ((status & BIT(0)) > 0), - 500, - 10000)) - return -ETIMEDOUT; - - if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, - status, - ((status & BIT(0)) > 0), - 500, - 10000)) - return -ETIMEDOUT; - - if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, - status, - ((status & BIT(1)) > 0), - 500, - 10000)) - return -ETIMEDOUT; - - writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); - - if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, - status, - ((status & BIT(0)) > 0), - 500, - 10000)) - return -ETIMEDOUT; - - if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, - status, - ((status & BIT(1)) > 0), - 500, - 10000)) - return -ETIMEDOUT; - - /* - * At least for 7nm DP PHY this has to be done after enabling link - * clock. - */ - - if (dp_opts->lanes == 1) { - bias0_en = reverse ? 0x3e : 0x15; - bias1_en = reverse ? 0x15 : 0x3e; - drvr0_en = reverse ? 0x13 : 0x10; - drvr1_en = reverse ? 0x10 : 0x13; - } else if (dp_opts->lanes == 2) { - bias0_en = reverse ? 0x3f : 0x15; - bias1_en = reverse ? 0x15 : 0x3f; - drvr0_en = 0x10; - drvr1_en = 0x10; - } else { - bias0_en = 0x3f; - bias1_en = 0x3f; - drvr0_en = 0x10; - drvr1_en = 0x10; - } - - writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); - writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); - writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); - writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); - - writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); - udelay(2000); - writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); - - if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, - status, - ((status & BIT(1)) > 0), - 500, - 10000)) - return -ETIMEDOUT; - - writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV); - writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV); - - writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); - writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); - - writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); - writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); - - return 0; -} - -/* - * We need to calibrate the aux setting here as many times - * as the caller tries - */ -static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy) -{ - static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; - u8 val; - - qphy->dp_aux_cfg++; - qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); - val = cfg1_settings[qphy->dp_aux_cfg]; - - writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); - - return 0; -} - -static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) -{ - const struct phy_configure_opts_dp *dp_opts = &opts->dp; - struct qmp_phy *qphy = phy_get_drvdata(phy); - const struct qmp_phy_cfg *cfg = qphy->cfg; - - memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); - if (qphy->dp_opts.set_voltages) { - cfg->configure_dp_tx(qphy); - qphy->dp_opts.set_voltages = 0; - } - - return 0; -} - -static int qcom_qmp_dp_phy_calibrate(struct phy *phy) -{ - struct qmp_phy *qphy = phy_get_drvdata(phy); - const struct qmp_phy_cfg *cfg = qphy->cfg; - - if (cfg->calibrate_dp_phy) - return cfg->calibrate_dp_phy(qphy); - - return 0; -} - -static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) -{ - struct qcom_qmp *qmp = qphy->qmp; - const struct qmp_phy_cfg *cfg = qphy->cfg; - void __iomem *serdes = qphy->serdes; - void __iomem *pcs = qphy->pcs; - void __iomem *dp_com = qmp->dp_com; - int ret, i; - - mutex_lock(&qmp->phy_mutex); - if (qmp->init_count++) { - mutex_unlock(&qmp->phy_mutex); - return 0; - } - - /* turn on regulator supplies */ - ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); - if (ret) { - dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); - goto err_unlock; - } - - for (i = 0; i < cfg->num_resets; i++) { - ret = reset_control_assert(qmp->resets[i]); - if (ret) { - dev_err(qmp->dev, "%s reset assert failed\n", - cfg->reset_list[i]); - goto err_disable_regulators; - } - } - - for (i = cfg->num_resets - 1; i >= 0; i--) { - ret = reset_control_deassert(qmp->resets[i]); - if (ret) { - dev_err(qmp->dev, "%s reset deassert failed\n", - qphy->cfg->reset_list[i]); - goto err_assert_reset; - } - } - - ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); - if (ret) - goto err_assert_reset; - - if (cfg->has_phy_dp_com_ctrl) { - qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, - SW_PWRDN); - /* override hardware control for reset of qmp phy */ - qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, - SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | - SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); - - /* Default type-c orientation, i.e CC1 */ - qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); - - qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, - USB3_MODE | DP_MODE); - - /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ - qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, - SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | - SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); - - qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); - qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); - } - - if (cfg->has_phy_com_ctrl) { - qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], - SW_PWRDN); - } else { - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) - qphy_setbits(pcs, - cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], - cfg->pwrdn_ctrl); - else - qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, - cfg->pwrdn_ctrl); - } - - mutex_unlock(&qmp->phy_mutex); - - return 0; - -err_assert_reset: - while (++i < cfg->num_resets) - reset_control_assert(qmp->resets[i]); -err_disable_regulators: - regulator_bulk_disable(cfg->num_vregs, qmp->vregs); -err_unlock: - mutex_unlock(&qmp->phy_mutex); - - return ret; -} - -static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy) -{ - struct qcom_qmp *qmp = qphy->qmp; - const struct qmp_phy_cfg *cfg = qphy->cfg; - void __iomem *serdes = qphy->serdes; - int i = cfg->num_resets; - - mutex_lock(&qmp->phy_mutex); - if (--qmp->init_count) { - mutex_unlock(&qmp->phy_mutex); - return 0; - } - - reset_control_assert(qmp->ufs_reset); - if (cfg->has_phy_com_ctrl) { - qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], - SERDES_START | PCS_START); - qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], - SW_RESET); - qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], - SW_PWRDN); - } - - while (--i >= 0) - reset_control_assert(qmp->resets[i]); - - clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); - - regulator_bulk_disable(cfg->num_vregs, qmp->vregs); - - mutex_unlock(&qmp->phy_mutex); - - return 0; -} - -static int qcom_qmp_phy_init(struct phy *phy) -{ - struct qmp_phy *qphy = phy_get_drvdata(phy); - struct qcom_qmp *qmp = qphy->qmp; - const struct qmp_phy_cfg *cfg = qphy->cfg; - int ret; - dev_vdbg(qmp->dev, "Initializing QMP phy\n"); - - if (cfg->no_pcs_sw_reset) { - /* - * Get UFS reset, which is delayed until now to avoid a - * circular dependency where UFS needs its PHY, but the PHY - * needs this UFS reset. - */ - if (!qmp->ufs_reset) { - qmp->ufs_reset = - devm_reset_control_get_exclusive(qmp->dev, - "ufsphy"); - - if (IS_ERR(qmp->ufs_reset)) { - ret = PTR_ERR(qmp->ufs_reset); - dev_err(qmp->dev, - "failed to get UFS reset: %d\n", - ret); - - qmp->ufs_reset = NULL; - return ret; - } - } - - ret = reset_control_assert(qmp->ufs_reset); - if (ret) - return ret; - } - - ret = qcom_qmp_phy_com_init(qphy); - if (ret) - return ret; - - if (cfg->type == PHY_TYPE_DP) - cfg->dp_aux_init(qphy); - - return 0; -} - -static int qcom_qmp_phy_power_on(struct phy *phy) -{ - struct qmp_phy *qphy = phy_get_drvdata(phy); - struct qcom_qmp *qmp = qphy->qmp; - const struct qmp_phy_cfg *cfg = qphy->cfg; - void __iomem *tx = qphy->tx; - void __iomem *rx = qphy->rx; - void __iomem *pcs = qphy->pcs; - void __iomem *pcs_misc = qphy->pcs_misc; - void __iomem *status; - unsigned int mask, val, ready; - int ret; - - qcom_qmp_phy_serdes_init(qphy); - - if (cfg->has_lane_rst) { - ret = reset_control_deassert(qphy->lane_rst); - if (ret) { - dev_err(qmp->dev, "lane%d reset deassert failed\n", - qphy->index); - return ret; - } - } - - ret = clk_prepare_enable(qphy->pipe_clk); - if (ret) { - dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); - goto err_reset_lane; - } - - /* Tx, Rx, and PCS configurations */ - qcom_qmp_phy_configure_lane(tx, cfg->regs, - cfg->tx_tbl, cfg->tx_tbl_num, 1); - if (cfg->tx_tbl_sec) - qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, - cfg->tx_tbl_num_sec, 1); - - /* Configuration for other LANE for USB-DP combo PHY */ - if (cfg->is_dual_lane_phy) { - qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs, - cfg->tx_tbl, cfg->tx_tbl_num, 2); - if (cfg->tx_tbl_sec) - qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs, - cfg->tx_tbl_sec, - cfg->tx_tbl_num_sec, 2); - } - - /* Configure special DP tx tunings */ - if (cfg->type == PHY_TYPE_DP) - cfg->configure_dp_tx(qphy); - - qcom_qmp_phy_configure_lane(rx, cfg->regs, - cfg->rx_tbl, cfg->rx_tbl_num, 1); - if (cfg->rx_tbl_sec) - qcom_qmp_phy_configure_lane(rx, cfg->regs, - cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); - - if (cfg->is_dual_lane_phy) { - qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs, - cfg->rx_tbl, cfg->rx_tbl_num, 2); - if (cfg->rx_tbl_sec) - qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs, - cfg->rx_tbl_sec, - cfg->rx_tbl_num_sec, 2); - } - - /* Configure link rate, swing, etc. */ - if (cfg->type == PHY_TYPE_DP) { - cfg->configure_dp_phy(qphy); - } else { - qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); - if (cfg->pcs_tbl_sec) - qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, - cfg->pcs_tbl_num_sec); - } - - ret = reset_control_deassert(qmp->ufs_reset); - if (ret) - goto err_disable_pipe_clk; - - qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, - cfg->pcs_misc_tbl_num); - if (cfg->pcs_misc_tbl_sec) - qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, - cfg->pcs_misc_tbl_num_sec); - - /* - * Pull out PHY from POWER DOWN state. - * This is active low enable signal to power-down PHY. - */ - if(cfg->type == PHY_TYPE_PCIE) - qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); - - if (cfg->has_pwrdn_delay) - usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); - - if (cfg->type != PHY_TYPE_DP) { - /* Pull PHY out of reset state */ - if (!cfg->no_pcs_sw_reset) - qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); - /* start SerDes and Phy-Coding-Sublayer */ - qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); - - if (cfg->type == PHY_TYPE_UFS) { - status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; - mask = PCS_READY; - ready = PCS_READY; - } else { - status = pcs + cfg->regs[QPHY_PCS_STATUS]; - mask = cfg->phy_status; - ready = 0; - } - - ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, - PHY_INIT_COMPLETE_TIMEOUT); - if (ret) { - dev_err(qmp->dev, "phy initialization timed-out\n"); - goto err_disable_pipe_clk; - } - } - return 0; - -err_disable_pipe_clk: - clk_disable_unprepare(qphy->pipe_clk); -err_reset_lane: - if (cfg->has_lane_rst) - reset_control_assert(qphy->lane_rst); - - return ret; -} - -static int qcom_qmp_phy_power_off(struct phy *phy) -{ - struct qmp_phy *qphy = phy_get_drvdata(phy); - const struct qmp_phy_cfg *cfg = qphy->cfg; - - clk_disable_unprepare(qphy->pipe_clk); - - if (cfg->type == PHY_TYPE_DP) { - /* Assert DP PHY power down */ - writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); - } else { - /* PHY reset */ - if (!cfg->no_pcs_sw_reset) - qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); - - /* stop SerDes and Phy-Coding-Sublayer */ - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); - - /* Put PHY into POWER DOWN state: active low */ - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], - cfg->pwrdn_ctrl); - } else { - qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, - cfg->pwrdn_ctrl); - } - } - - return 0; -} - -static int qcom_qmp_phy_exit(struct phy *phy) -{ - struct qmp_phy *qphy = phy_get_drvdata(phy); - const struct qmp_phy_cfg *cfg = qphy->cfg; - - if (cfg->has_lane_rst) - reset_control_assert(qphy->lane_rst); - - qcom_qmp_phy_com_exit(qphy); - - return 0; -} - -static int qcom_qmp_phy_enable(struct phy *phy) -{ - int ret; - - ret = qcom_qmp_phy_init(phy); - if (ret) - return ret; - - ret = qcom_qmp_phy_power_on(phy); - if (ret) - qcom_qmp_phy_exit(phy); - - return ret; -} - -static int qcom_qmp_phy_disable(struct phy *phy) -{ - int ret; - - ret = qcom_qmp_phy_power_off(phy); - if (ret) - return ret; - return qcom_qmp_phy_exit(phy); -} - -static int qcom_qmp_phy_set_mode(struct phy *phy, - enum phy_mode mode, int submode) -{ - struct qmp_phy *qphy = phy_get_drvdata(phy); - - qphy->mode = mode; - - return 0; -} - -static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy) -{ - const struct qmp_phy_cfg *cfg = qphy->cfg; - void __iomem *pcs = qphy->pcs; - void __iomem *pcs_misc = qphy->pcs_misc; - u32 intr_mask; - - if (qphy->mode == PHY_MODE_USB_HOST_SS || - qphy->mode == PHY_MODE_USB_DEVICE_SS) - intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; - else - intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; - - /* Clear any pending interrupts status */ - qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); - /* Writing 1 followed by 0 clears the interrupt */ - qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); - - qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], - ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); - - /* Enable required PHY autonomous mode interrupts */ - qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); - - /* Enable i/o clamp_n for autonomous mode */ - if (pcs_misc) - qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); -} - -static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy) -{ - const struct qmp_phy_cfg *cfg = qphy->cfg; - void __iomem *pcs = qphy->pcs; - void __iomem *pcs_misc = qphy->pcs_misc; - - /* Disable i/o clamp_n on resume for normal mode */ - if (pcs_misc) - qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); - - qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], - ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); - - qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); - /* Writing 1 followed by 0 clears the interrupt */ - qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); -} - -static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) -{ - struct qcom_qmp *qmp = dev_get_drvdata(dev); - struct qmp_phy *qphy = qmp->phys[0]; - const struct qmp_phy_cfg *cfg = qphy->cfg; - - dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); - - /* Supported only for USB3 PHY and luckily USB3 is the first phy */ - if (cfg->type != PHY_TYPE_USB3) - return 0; - - if (!qmp->init_count) { - dev_vdbg(dev, "PHY not initialized, bailing out\n"); - return 0; - } - - qcom_qmp_phy_enable_autonomous_mode(qphy); - - clk_disable_unprepare(qphy->pipe_clk); - clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); - - return 0; -} - -static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) -{ - struct qcom_qmp *qmp = dev_get_drvdata(dev); - struct qmp_phy *qphy = qmp->phys[0]; - const struct qmp_phy_cfg *cfg = qphy->cfg; - int ret = 0; - - dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); - - /* Supported only for USB3 PHY and luckily USB3 is the first phy */ - if (cfg->type != PHY_TYPE_USB3) - return 0; - - if (!qmp->init_count) { - dev_vdbg(dev, "PHY not initialized, bailing out\n"); - return 0; - } - - ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); - if (ret) - return ret; - - ret = clk_prepare_enable(qphy->pipe_clk); - if (ret) { - dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); - clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); - return ret; - } - - qcom_qmp_phy_disable_autonomous_mode(qphy); - - return 0; -} - -static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) -{ - struct qcom_qmp *qmp = dev_get_drvdata(dev); - int num = cfg->num_vregs; - int i; - - qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); - if (!qmp->vregs) - return -ENOMEM; - - for (i = 0; i < num; i++) - qmp->vregs[i].supply = cfg->vreg_list[i]; - - return devm_regulator_bulk_get(dev, num, qmp->vregs); -} - -static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) -{ - struct qcom_qmp *qmp = dev_get_drvdata(dev); - int i; - - qmp->resets = devm_kcalloc(dev, cfg->num_resets, - sizeof(*qmp->resets), GFP_KERNEL); - if (!qmp->resets) - return -ENOMEM; - - for (i = 0; i < cfg->num_resets; i++) { - struct reset_control *rst; - const char *name = cfg->reset_list[i]; - - rst = devm_reset_control_get_exclusive(dev, name); - if (IS_ERR(rst)) { - dev_err(dev, "failed to get %s reset\n", name); - return PTR_ERR(rst); - } - qmp->resets[i] = rst; - } - - return 0; -} - -static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) -{ - struct qcom_qmp *qmp = dev_get_drvdata(dev); - int num = cfg->num_clks; - int i; - - qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); - if (!qmp->clks) - return -ENOMEM; - - for (i = 0; i < num; i++) - qmp->clks[i].id = cfg->clk_list[i]; - - return devm_clk_bulk_get(dev, num, qmp->clks); -} - -static void phy_clk_release_provider(void *res) -{ - of_clk_del_provider(res); -} - -/* - * Register a fixed rate pipe clock. - * - * The _pipe_clksrc generated by PHY goes to the GCC that gate - * controls it. The _pipe_clk coming out of the GCC is requested - * by the PHY driver for its operations. - * We register the _pipe_clksrc here. The gcc driver takes care - * of assigning this _pipe_clksrc as parent to _pipe_clk. - * Below picture shows this relationship. - * - * +---------------+ - * | PHY block |<<---------------------------------------+ - * | | | - * | +-------+ | +-----+ | - * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ - * clk | +-------+ | +-----+ - * +---------------+ - */ -static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) -{ - struct clk_fixed_rate *fixed; - struct clk_init_data init = { }; - int ret; - - ret = of_property_read_string(np, "clock-output-names", &init.name); - if (ret) { - dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); - return ret; - } - - fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); - if (!fixed) - return -ENOMEM; - - init.ops = &clk_fixed_rate_ops; - - /* controllers using QMP phys use 125MHz pipe clock interface */ - fixed->fixed_rate = 125000000; - fixed->hw.init = &init; - - ret = devm_clk_hw_register(qmp->dev, &fixed->hw); - if (ret) - return ret; - - ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); - if (ret) - return ret; - - /* - * Roll a devm action because the clock provider is the child node, but - * the child node is not actually a device. - */ - return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); -} - -/* - * Display Port PLL driver block diagram for branch clocks - * - * +------------------------------+ - * | DP_VCO_CLK | - * | | - * | +-------------------+ | - * | | (DP PLL/VCO) | | - * | +---------+---------+ | - * | v | - * | +----------+-----------+ | - * | | hsclk_divsel_clk_src | | - * | +----------+-----------+ | - * +------------------------------+ - * | - * +---------<---------v------------>----------+ - * | | - * +--------v----------------+ | - * | dp_phy_pll_link_clk | | - * | link_clk | | - * +--------+----------------+ | - * | | - * | | - * v v - * Input to DISPCC block | - * for link clk, crypto clk | - * and interface clock | - * | - * | - * +--------<------------+-----------------+---<---+ - * | | | - * +----v---------+ +--------v-----+ +--------v------+ - * | vco_divided | | vco_divided | | vco_divided | - * | _clk_src | | _clk_src | | _clk_src | - * | | | | | | - * |divsel_six | | divsel_two | | divsel_four | - * +-------+------+ +-----+--------+ +--------+------+ - * | | | - * v---->----------v-------------<------v - * | - * +----------+-----------------+ - * | dp_phy_pll_vco_div_clk | - * +---------+------------------+ - * | - * v - * Input to DISPCC block - * for DP pixel clock - * - */ -static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - switch (req->rate) { - case 1620000000UL / 2: - case 2700000000UL / 2: - /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ - return 0; - default: - return -EINVAL; - } -} - -static unsigned long -qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) -{ - const struct qmp_phy_dp_clks *dp_clks; - const struct qmp_phy *qphy; - const struct phy_configure_opts_dp *dp_opts; - - dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw); - qphy = dp_clks->qphy; - dp_opts = &qphy->dp_opts; - - switch (dp_opts->link_rate) { - case 1620: - return 1620000000UL / 2; - case 2700: - return 2700000000UL / 2; - case 5400: - return 5400000000UL / 4; - case 8100: - return 8100000000UL / 6; - default: - return 0; - } -} - -static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = { - .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate, - .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate, -}; - -static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - switch (req->rate) { - case 162000000: - case 270000000: - case 540000000: - case 810000000: - return 0; - default: - return -EINVAL; - } -} - -static unsigned long -qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) -{ - const struct qmp_phy_dp_clks *dp_clks; - const struct qmp_phy *qphy; - const struct phy_configure_opts_dp *dp_opts; - - dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw); - qphy = dp_clks->qphy; - dp_opts = &qphy->dp_opts; - - switch (dp_opts->link_rate) { - case 1620: - case 2700: - case 5400: - case 8100: - return dp_opts->link_rate * 100000; - default: - return 0; - } -} - -static const struct clk_ops qcom_qmp_dp_link_clk_ops = { - .determine_rate = qcom_qmp_dp_link_clk_determine_rate, - .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate, -}; - -static struct clk_hw * -qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) -{ - struct qmp_phy_dp_clks *dp_clks = data; - unsigned int idx = clkspec->args[0]; - - if (idx >= 2) { - pr_err("%s: invalid index %u\n", __func__, idx); - return ERR_PTR(-EINVAL); - } - - if (idx == 0) - return &dp_clks->dp_link_hw; - - return &dp_clks->dp_pixel_hw; -} - -static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, - struct device_node *np) -{ - struct clk_init_data init = { }; - struct qmp_phy_dp_clks *dp_clks; - char name[64]; - int ret; - - dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL); - if (!dp_clks) - return -ENOMEM; - - dp_clks->qphy = qphy; - qphy->dp_clks = dp_clks; - - snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); - init.ops = &qcom_qmp_dp_link_clk_ops; - init.name = name; - dp_clks->dp_link_hw.init = &init; - ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw); - if (ret) - return ret; - - snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); - init.ops = &qcom_qmp_dp_pixel_clk_ops; - init.name = name; - dp_clks->dp_pixel_hw.init = &init; - ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw); - if (ret) - return ret; - - ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks); - if (ret) - return ret; - - /* - * Roll a devm action because the clock provider is the child node, but - * the child node is not actually a device. - */ - return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); -} - -static const struct phy_ops qcom_qmp_phy_gen_ops = { - .init = qcom_qmp_phy_enable, - .exit = qcom_qmp_phy_disable, - .set_mode = qcom_qmp_phy_set_mode, - .owner = THIS_MODULE, -}; - -static const struct phy_ops qcom_qmp_phy_dp_ops = { - .init = qcom_qmp_phy_init, - .configure = qcom_qmp_dp_phy_configure, - .power_on = qcom_qmp_phy_power_on, - .calibrate = qcom_qmp_dp_phy_calibrate, - .power_off = qcom_qmp_phy_power_off, - .exit = qcom_qmp_phy_exit, - .set_mode = qcom_qmp_phy_set_mode, - .owner = THIS_MODULE, -}; - -static const struct phy_ops qcom_qmp_pcie_ufs_ops = { - .power_on = qcom_qmp_phy_enable, - .power_off = qcom_qmp_phy_disable, - .set_mode = qcom_qmp_phy_set_mode, - .owner = THIS_MODULE, -}; - -static void qcom_qmp_reset_control_put(void *data) -{ - reset_control_put(data); -} - -static -int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, - void __iomem *serdes, const struct qmp_phy_cfg *cfg) -{ - struct qcom_qmp *qmp = dev_get_drvdata(dev); - struct phy *generic_phy; - struct qmp_phy *qphy; - const struct phy_ops *ops; - char prop_name[MAX_PROP_NAME]; - int ret; - - qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); - if (!qphy) - return -ENOMEM; - - qphy->cfg = cfg; - qphy->serdes = serdes; - /* - * Get memory resources for each phy lane: - * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. - * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 - * For single lane PHYs: pcs_misc (optional) -> 3. - */ - qphy->tx = of_iomap(np, 0); - if (!qphy->tx) - return -ENOMEM; - - qphy->rx = of_iomap(np, 1); - if (!qphy->rx) - return -ENOMEM; - - qphy->pcs = of_iomap(np, 2); - if (!qphy->pcs) - return -ENOMEM; - - /* - * If this is a dual-lane PHY, then there should be registers for the - * second lane. Some old device trees did not specify this, so fall - * back to old legacy behavior of assuming they can be reached at an - * offset from the first lane. - */ - if (cfg->is_dual_lane_phy) { - qphy->tx2 = of_iomap(np, 3); - qphy->rx2 = of_iomap(np, 4); - if (!qphy->tx2 || !qphy->rx2) { - dev_warn(dev, - "Underspecified device tree, falling back to legacy register regions\n"); - - /* In the old version, pcs_misc is at index 3. */ - qphy->pcs_misc = qphy->tx2; - qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; - qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; - - } else { - qphy->pcs_misc = of_iomap(np, 5); - } - - } else { - qphy->pcs_misc = of_iomap(np, 3); - } - - if (!qphy->pcs_misc) - dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); - - /* - * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3 - * based phys, so they essentially have pipe clock. So, - * we return error in case phy is USB3 or PIPE type. - * Otherwise, we initialize pipe clock to NULL for - * all phys that don't need this. - */ - snprintf(prop_name, sizeof(prop_name), "pipe%d", id); - qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); - if (IS_ERR(qphy->pipe_clk)) { - if (cfg->type == PHY_TYPE_PCIE || - cfg->type == PHY_TYPE_USB3) { - ret = PTR_ERR(qphy->pipe_clk); - if (ret != -EPROBE_DEFER) - dev_err(dev, - "failed to get lane%d pipe_clk, %d\n", - id, ret); - return ret; - } - qphy->pipe_clk = NULL; - } - - /* Get lane reset, if any */ - if (cfg->has_lane_rst) { - snprintf(prop_name, sizeof(prop_name), "lane%d", id); - qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name); - if (IS_ERR(qphy->lane_rst)) { - dev_err(dev, "failed to get lane%d reset\n", id); - return PTR_ERR(qphy->lane_rst); - } - ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put, - qphy->lane_rst); - if (ret) - return ret; - } - - if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE) - ops = &qcom_qmp_pcie_ufs_ops; - else if (cfg->type == PHY_TYPE_DP) - ops = &qcom_qmp_phy_dp_ops; - else - ops = &qcom_qmp_phy_gen_ops; - - generic_phy = devm_phy_create(dev, np, ops); - if (IS_ERR(generic_phy)) { - ret = PTR_ERR(generic_phy); - dev_err(dev, "failed to create qphy %d\n", ret); - return ret; - } - - qphy->phy = generic_phy; - qphy->index = id; - qphy->qmp = qmp; - qmp->phys[id] = qphy; - phy_set_drvdata(generic_phy, qphy); - - return 0; -} - -static const struct of_device_id qcom_qmp_phy_of_match_table[] = { - { - .compatible = "qcom,ipq8074-qmp-usb3-phy", - .data = &ipq8074_usb3phy_cfg, - }, { - .compatible = "qcom,msm8996-qmp-pcie-phy", - .data = &msm8996_pciephy_cfg, - }, { - .compatible = "qcom,msm8996-qmp-ufs-phy", - .data = &msm8996_ufs_cfg, - }, { - .compatible = "qcom,msm8996-qmp-usb3-phy", - .data = &msm8996_usb3phy_cfg, - }, { - .compatible = "qcom,msm8998-qmp-pcie-phy", - .data = &msm8998_pciephy_cfg, - }, { - .compatible = "qcom,msm8998-qmp-ufs-phy", - .data = &sdm845_ufsphy_cfg, - }, { - .compatible = "qcom,ipq8074-qmp-pcie-phy", - .data = &ipq8074_pciephy_cfg, - }, { - .compatible = "qcom,ipq6018-qmp-pcie-phy", - .data = &ipq6018_pciephy_cfg, - }, { - .compatible = "qcom,ipq6018-qmp-usb3-phy", - .data = &ipq8074_usb3phy_cfg, - }, { - .compatible = "qcom,sc7180-qmp-usb3-phy", - .data = &sc7180_usb3phy_cfg, - }, { - .compatible = "qcom,sc7180-qmp-usb3-dp-phy", - /* It's a combo phy */ - }, { - .compatible = "qcom,sc8180x-qmp-pcie-phy", - .data = &sc8180x_pciephy_cfg, - }, { - .compatible = "qcom,sc8180x-qmp-ufs-phy", - .data = &sm8150_ufsphy_cfg, - }, { - .compatible = "qcom,sc8280xp-qmp-ufs-phy", - .data = &sm8350_ufsphy_cfg, - }, { - .compatible = "qcom,sc8180x-qmp-usb3-phy", - .data = &sm8150_usb3phy_cfg, - }, { - .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", - /* It's a combo phy */ - }, { - .compatible = "qcom,sdm845-qhp-pcie-phy", - .data = &sdm845_qhp_pciephy_cfg, - }, { - .compatible = "qcom,sdm845-qmp-pcie-phy", - .data = &sdm845_qmp_pciephy_cfg, - }, { - .compatible = "qcom,sdm845-qmp-usb3-phy", - .data = &qmp_v3_usb3phy_cfg, - }, { - .compatible = "qcom,sdm845-qmp-usb3-uni-phy", - .data = &qmp_v3_usb3_uniphy_cfg, - }, { - .compatible = "qcom,sdm845-qmp-ufs-phy", - .data = &sdm845_ufsphy_cfg, - }, { - .compatible = "qcom,msm8998-qmp-usb3-phy", - .data = &msm8998_usb3phy_cfg, - }, { - .compatible = "qcom,sm6115-qmp-ufs-phy", - .data = &sm6115_ufsphy_cfg, - }, { - .compatible = "qcom,sm6350-qmp-ufs-phy", - .data = &sdm845_ufsphy_cfg, - }, { - .compatible = "qcom,sm8150-qmp-ufs-phy", - .data = &sm8150_ufsphy_cfg, - }, { - .compatible = "qcom,sm8250-qmp-ufs-phy", - .data = &sm8150_ufsphy_cfg, - }, { - .compatible = "qcom,sm8150-qmp-usb3-phy", - .data = &sm8150_usb3phy_cfg, - }, { - .compatible = "qcom,sm8150-qmp-usb3-uni-phy", - .data = &sm8150_usb3_uniphy_cfg, - }, { - .compatible = "qcom,sm8250-qmp-usb3-phy", - .data = &sm8250_usb3phy_cfg, - }, { - .compatible = "qcom,sm8250-qmp-usb3-dp-phy", - /* It's a combo phy */ - }, { - .compatible = "qcom,sm8250-qmp-usb3-uni-phy", - .data = &sm8250_usb3_uniphy_cfg, - }, { - .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", - .data = &sm8250_qmp_gen3x1_pciephy_cfg, - }, { - .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", - .data = &sm8250_qmp_gen3x2_pciephy_cfg, - }, { - .compatible = "qcom,sm8350-qmp-ufs-phy", - .data = &sm8350_ufsphy_cfg, - }, { - .compatible = "qcom,sm8250-qmp-modem-pcie-phy", - .data = &sm8250_qmp_gen3x2_pciephy_cfg, - }, { - .compatible = "qcom,sdx55-qmp-pcie-phy", - .data = &sdx55_qmp_pciephy_cfg, - }, { - .compatible = "qcom,sdx55-qmp-usb3-uni-phy", - .data = &sdx55_usb3_uniphy_cfg, - }, { - .compatible = "qcom,sdx65-qmp-usb3-uni-phy", - .data = &sdx65_usb3_uniphy_cfg, - }, { - .compatible = "qcom,sm8350-qmp-usb3-phy", - .data = &sm8350_usb3phy_cfg, - }, { - .compatible = "qcom,sm8350-qmp-usb3-uni-phy", - .data = &sm8350_usb3_uniphy_cfg, - }, { - .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", - .data = &sm8450_qmp_gen3x1_pciephy_cfg, - }, { - .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", - .data = &sm8450_qmp_gen4x2_pciephy_cfg, - }, { - .compatible = "qcom,sm8450-qmp-ufs-phy", - .data = &sm8450_ufsphy_cfg, - }, { - .compatible = "qcom,sm8450-qmp-usb3-phy", - .data = &sm8350_usb3phy_cfg, - }, { - .compatible = "qcom,qcm2290-qmp-usb3-phy", - .data = &qcm2290_usb3phy_cfg, - }, - { }, -}; -MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table); - -static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = { - { - .compatible = "qcom,sc7180-qmp-usb3-dp-phy", - .data = &sc7180_usb3dpphy_cfg, - }, - { - .compatible = "qcom,sm8250-qmp-usb3-dp-phy", - .data = &sm8250_usb3dpphy_cfg, - }, - { - .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", - .data = &sc8180x_usb3dpphy_cfg, - }, - { } -}; - -static const struct dev_pm_ops qcom_qmp_phy_pm_ops = { - SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend, - qcom_qmp_phy_runtime_resume, NULL) -}; - -static int qcom_qmp_phy_probe(struct platform_device *pdev) -{ - struct qcom_qmp *qmp; - struct device *dev = &pdev->dev; - struct device_node *child; - struct phy_provider *phy_provider; - void __iomem *serdes; - void __iomem *usb_serdes; - void __iomem *dp_serdes = NULL; - const struct qmp_phy_combo_cfg *combo_cfg = NULL; - const struct qmp_phy_cfg *cfg = NULL; - const struct qmp_phy_cfg *usb_cfg = NULL; - const struct qmp_phy_cfg *dp_cfg = NULL; - int num, id, expected_phys; - int ret; - - qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); - if (!qmp) - return -ENOMEM; - - qmp->dev = dev; - dev_set_drvdata(dev, qmp); - - /* Get the specific init parameters of QMP phy */ - cfg = of_device_get_match_data(dev); - if (!cfg) { - const struct of_device_id *match; - - match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev); - if (!match) - return -EINVAL; - - combo_cfg = match->data; - if (!combo_cfg) - return -EINVAL; - - usb_cfg = combo_cfg->usb_cfg; - cfg = usb_cfg; /* Setup clks and regulators */ - } - - /* per PHY serdes; usually located at base address */ - usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(serdes)) - return PTR_ERR(serdes); - - /* per PHY dp_com; if PHY has dp_com control block */ - if (combo_cfg || cfg->has_phy_dp_com_ctrl) { - qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(qmp->dp_com)) - return PTR_ERR(qmp->dp_com); - } - - if (combo_cfg) { - /* Only two serdes for combo PHY */ - dp_serdes = devm_platform_ioremap_resource(pdev, 2); - if (IS_ERR(dp_serdes)) - return PTR_ERR(dp_serdes); - - dp_cfg = combo_cfg->dp_cfg; - expected_phys = 2; - } else { - expected_phys = cfg->nlanes; - } - - mutex_init(&qmp->phy_mutex); - - ret = qcom_qmp_phy_clk_init(dev, cfg); - if (ret) - return ret; - - ret = qcom_qmp_phy_reset_init(dev, cfg); - if (ret) - return ret; - - ret = qcom_qmp_phy_vreg_init(dev, cfg); - if (ret) { - if (ret != -EPROBE_DEFER) - dev_err(dev, "failed to get regulator supplies: %d\n", - ret); - return ret; - } - - num = of_get_available_child_count(dev->of_node); - /* do we have a rogue child node ? */ - if (num > expected_phys) - return -EINVAL; - - qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); - if (!qmp->phys) - return -ENOMEM; - - pm_runtime_set_active(dev); - pm_runtime_enable(dev); - /* - * Prevent runtime pm from being ON by default. Users can enable - * it using power/control in sysfs. - */ - pm_runtime_forbid(dev); - - id = 0; - for_each_available_child_of_node(dev->of_node, child) { - if (of_node_name_eq(child, "dp-phy")) { - cfg = dp_cfg; - serdes = dp_serdes; - } else if (of_node_name_eq(child, "usb3-phy")) { - cfg = usb_cfg; - serdes = usb_serdes; - } - - /* Create per-lane phy */ - ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg); - if (ret) { - dev_err(dev, "failed to create lane%d phy, %d\n", - id, ret); - goto err_node_put; - } - - /* - * Register the pipe clock provided by phy. - * See function description to see details of this pipe clock. - */ - if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) { - ret = phy_pipe_clk_register(qmp, child); - if (ret) { - dev_err(qmp->dev, - "failed to register pipe clock source\n"); - goto err_node_put; - } - } else if (cfg->type == PHY_TYPE_DP) { - ret = phy_dp_clks_register(qmp, qmp->phys[id], child); - if (ret) { - dev_err(qmp->dev, - "failed to register DP clock source\n"); - goto err_node_put; - } - } - id++; - } - - phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); - if (!IS_ERR(phy_provider)) - dev_info(dev, "Registered Qcom-QMP phy\n"); - else - pm_runtime_disable(dev); - - return PTR_ERR_OR_ZERO(phy_provider); - -err_node_put: - pm_runtime_disable(dev); - of_node_put(child); - return ret; -} - -static struct platform_driver qcom_qmp_phy_driver = { - .probe = qcom_qmp_phy_probe, - .driver = { - .name = "qcom-qmp-phy", - .pm = &qcom_qmp_phy_pm_ops, - .of_match_table = qcom_qmp_phy_of_match_table, - }, -}; - -module_platform_driver(qcom_qmp_phy_driver); - -MODULE_AUTHOR("Vivek Gautam "); -MODULE_DESCRIPTION("Qualcomm QMP PHY driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 06b2556ed93a..b139c8af5e8b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -6,275 +6,44 @@ #ifndef QCOM_PHY_QMP_H_ #define QCOM_PHY_QMP_H_ -/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */ +#include "phy-qcom-qmp-qserdes-com.h" +#include "phy-qcom-qmp-qserdes-txrx.h" -#define QSERDES_PLL_BG_TIMER 0x00c -#define QSERDES_PLL_SSC_PER1 0x01c -#define QSERDES_PLL_SSC_PER2 0x020 -#define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024 -#define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028 -#define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c -#define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030 -#define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c -#define QSERDES_PLL_CLK_ENABLE1 0x040 -#define QSERDES_PLL_SYS_CLK_CTRL 0x044 -#define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048 -#define QSERDES_PLL_PLL_IVCO 0x050 -#define QSERDES_PLL_LOCK_CMP1_MODE0 0x054 -#define QSERDES_PLL_LOCK_CMP2_MODE0 0x058 -#define QSERDES_PLL_LOCK_CMP1_MODE1 0x060 -#define QSERDES_PLL_LOCK_CMP2_MODE1 0x064 -#define QSERDES_PLL_BG_TRIM 0x074 -#define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078 -#define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c -#define QSERDES_PLL_CP_CTRL_MODE0 0x080 -#define QSERDES_PLL_CP_CTRL_MODE1 0x084 -#define QSERDES_PLL_PLL_RCTRL_MODE0 0x088 -#define QSERDES_PLL_PLL_RCTRL_MODE1 0x08C -#define QSERDES_PLL_PLL_CCTRL_MODE0 0x090 -#define QSERDES_PLL_PLL_CCTRL_MODE1 0x094 -#define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4 -#define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8 -#define QSERDES_PLL_RESETSM_CNTRL 0x0b0 -#define QSERDES_PLL_LOCK_CMP_EN 0x0c4 -#define QSERDES_PLL_DEC_START_MODE0 0x0cc -#define QSERDES_PLL_DEC_START_MODE1 0x0d0 -#define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8 -#define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc -#define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0 -#define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4 -#define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8 -#define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0eC -#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100 -#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104 -#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108 -#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c -#define QSERDES_PLL_VCO_TUNE_MAP 0x120 -#define QSERDES_PLL_VCO_TUNE1_MODE0 0x124 -#define QSERDES_PLL_VCO_TUNE2_MODE0 0x128 -#define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c -#define QSERDES_PLL_VCO_TUNE2_MODE1 0x130 -#define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c -#define QSERDES_PLL_VCO_TUNE_TIMER2 0x140 -#define QSERDES_PLL_CLK_SELECT 0x16c -#define QSERDES_PLL_HSCLK_SEL 0x170 -#define QSERDES_PLL_CORECLK_DIV 0x17c -#define QSERDES_PLL_CORE_CLK_EN 0x184 -#define QSERDES_PLL_CMN_CONFIG 0x18c -#define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194 -#define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4 +#include "phy-qcom-qmp-qserdes-com-v3.h" +#include "phy-qcom-qmp-qserdes-txrx-v3.h" -/* QMP V2 PHY for PCIE gen3 ports - QSERDES TX registers */ +#include "phy-qcom-qmp-qserdes-com-v4.h" +#include "phy-qcom-qmp-qserdes-txrx-v4.h" +#include "phy-qcom-qmp-qserdes-txrx-v4_20.h" -#define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX 0x03c -#define QSERDES_TX0_HIGHZ_DRVR_EN 0x058 -#define QSERDES_TX0_LANE_MODE_1 0x084 -#define QSERDES_TX0_RCV_DETECT_LVL_2 0x09c +#include "phy-qcom-qmp-qserdes-com-v5.h" +#include "phy-qcom-qmp-qserdes-txrx-v5.h" +#include "phy-qcom-qmp-qserdes-txrx-v5_20.h" -/* QMP V2 PHY for PCIE gen3 ports - QSERDES RX registers */ +#include "phy-qcom-qmp-qserdes-pll.h" -#define QSERDES_RX0_UCDR_FO_GAIN 0x008 -#define QSERDES_RX0_UCDR_SO_GAIN 0x014 -#define QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE 0x034 -#define QSERDES_RX0_UCDR_PI_CONTROLS 0x044 -#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2 0x0ec -#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3 0x0f0 -#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4 0x0f4 -#define QSERDES_RX0_RX_IDAC_TSETTLE_LOW 0x0f8 -#define QSERDES_RX0_RX_IDAC_TSETTLE_HIGH 0x0fc -#define QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 -#define QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2 0x114 -#define QSERDES_RX0_SIGDET_ENABLES 0x118 -#define QSERDES_RX0_SIGDET_CNTRL 0x11c -#define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL 0x124 -#define QSERDES_RX0_RX_MODE_00_LOW 0x170 -#define QSERDES_RX0_RX_MODE_00_HIGH 0x174 -#define QSERDES_RX0_RX_MODE_00_HIGH2 0x178 -#define QSERDES_RX0_RX_MODE_00_HIGH3 0x17c -#define QSERDES_RX0_RX_MODE_00_HIGH4 0x180 -#define QSERDES_RX0_RX_MODE_01_LOW 0x184 -#define QSERDES_RX0_RX_MODE_01_HIGH 0x188 -#define QSERDES_RX0_RX_MODE_01_HIGH2 0x18c -#define QSERDES_RX0_RX_MODE_01_HIGH3 0x190 -#define QSERDES_RX0_RX_MODE_01_HIGH4 0x194 -#define QSERDES_RX0_RX_MODE_10_LOW 0x198 -#define QSERDES_RX0_RX_MODE_10_HIGH 0x19c -#define QSERDES_RX0_RX_MODE_10_HIGH2 0x1a0 -#define QSERDES_RX0_RX_MODE_10_HIGH3 0x1a4 -#define QSERDES_RX0_RX_MODE_10_HIGH4 0x1a8 -#define QSERDES_RX0_DFE_EN_TIMER 0x1b4 +#include "phy-qcom-qmp-pcs-v2.h" -/* QMP V2 PHY for PCIE gen3 ports - PCS registers */ +#include "phy-qcom-qmp-pcs-v3.h" +#include "phy-qcom-qmp-pcs-misc-v3.h" +#include "phy-qcom-qmp-pcs-ufs-v3.h" -#define PCS_COM_FLL_CNTRL1 0x098 -#define PCS_COM_FLL_CNTRL2 0x09c -#define PCS_COM_FLL_CNT_VAL_L 0x0a0 -#define PCS_COM_FLL_CNT_VAL_H_TOL 0x0a4 -#define PCS_COM_FLL_MAN_CODE 0x0a8 -#define PCS_COM_REFGEN_REQ_CONFIG1 0x0dc -#define PCS_COM_G12S1_TXDEEMPH_M3P5DB 0x16c -#define PCS_COM_RX_SIGDET_LVL 0x188 -#define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 -#define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 -#define PCS_COM_RX_DCC_CAL_CONFIG 0x1d8 -#define PCS_COM_EQ_CONFIG5 0x1ec +#include "phy-qcom-qmp-pcs-v4.h" +#include "phy-qcom-qmp-pcs-pcie-v4.h" +#include "phy-qcom-qmp-pcs-usb-v4.h" +#include "phy-qcom-qmp-pcs-ufs-v4.h" -/* QMP V2 PHY for PCIE gen3 ports - PCS Misc registers */ +#include "phy-qcom-qmp-pcs-v4_20.h" +#include "phy-qcom-qmp-pcs-pcie-v4_20.h" -#define PCS_PCIE_POWER_STATE_CONFIG2 0x40c -#define PCS_PCIE_POWER_STATE_CONFIG4 0x414 -#define PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x41c -#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x440 -#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x444 -#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x448 -#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x44c -#define PCS_PCIE_OSC_DTCT_CONFIG2 0x45c -#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x478 -#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x480 -#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x484 -#define PCS_PCIE_OSC_DTCT_ACTIONS 0x490 -#define PCS_PCIE_EQ_CONFIG1 0x4a0 -#define PCS_PCIE_EQ_CONFIG2 0x4a4 -#define PCS_PCIE_PRESET_P10_PRE 0x4bc -#define PCS_PCIE_PRESET_P10_POST 0x4e0 +#include "phy-qcom-qmp-pcs-v5.h" +#include "phy-qcom-qmp-pcs-pcie-v5.h" +#include "phy-qcom-qmp-pcs-usb-v5.h" +#include "phy-qcom-qmp-pcs-ufs-v5.h" -/* Only for QMP V2 PHY - QSERDES COM registers */ -#define QSERDES_COM_BG_TIMER 0x00c -#define QSERDES_COM_SSC_EN_CENTER 0x010 -#define QSERDES_COM_SSC_ADJ_PER1 0x014 -#define QSERDES_COM_SSC_ADJ_PER2 0x018 -#define QSERDES_COM_SSC_PER1 0x01c -#define QSERDES_COM_SSC_PER2 0x020 -#define QSERDES_COM_SSC_STEP_SIZE1 0x024 -#define QSERDES_COM_SSC_STEP_SIZE2 0x028 -#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034 -#define QSERDES_COM_CLK_ENABLE1 0x038 -#define QSERDES_COM_SYS_CLK_CTRL 0x03c -#define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040 -#define QSERDES_COM_PLL_IVCO 0x048 -#define QSERDES_COM_LOCK_CMP1_MODE0 0x04c -#define QSERDES_COM_LOCK_CMP2_MODE0 0x050 -#define QSERDES_COM_LOCK_CMP3_MODE0 0x054 -#define QSERDES_COM_LOCK_CMP1_MODE1 0x058 -#define QSERDES_COM_LOCK_CMP2_MODE1 0x05c -#define QSERDES_COM_LOCK_CMP3_MODE1 0x060 -#define QSERDES_COM_BG_TRIM 0x070 -#define QSERDES_COM_CLK_EP_DIV 0x074 -#define QSERDES_COM_CP_CTRL_MODE0 0x078 -#define QSERDES_COM_CP_CTRL_MODE1 0x07c -#define QSERDES_COM_PLL_RCTRL_MODE0 0x084 -#define QSERDES_COM_PLL_RCTRL_MODE1 0x088 -#define QSERDES_COM_PLL_CCTRL_MODE0 0x090 -#define QSERDES_COM_PLL_CCTRL_MODE1 0x094 -#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8 -#define QSERDES_COM_SYSCLK_EN_SEL 0x0ac -#define QSERDES_COM_RESETSM_CNTRL 0x0b4 -#define QSERDES_COM_RESETSM_CNTRL2 0x0b8 -#define QSERDES_COM_RESTRIM_CTRL 0x0bc -#define QSERDES_COM_RESCODE_DIV_NUM 0x0c4 -#define QSERDES_COM_LOCK_CMP_EN 0x0c8 -#define QSERDES_COM_LOCK_CMP_CFG 0x0cc -#define QSERDES_COM_DEC_START_MODE0 0x0d0 -#define QSERDES_COM_DEC_START_MODE1 0x0d4 -#define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc -#define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0 -#define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4 -#define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8 -#define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec -#define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0 -#define QSERDES_COM_INTEGLOOP_INITVAL 0x100 -#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108 -#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c -#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110 -#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114 -#define QSERDES_COM_VCO_TUNE_CTRL 0x124 -#define QSERDES_COM_VCO_TUNE_MAP 0x128 -#define QSERDES_COM_VCO_TUNE1_MODE0 0x12c -#define QSERDES_COM_VCO_TUNE2_MODE0 0x130 -#define QSERDES_COM_VCO_TUNE1_MODE1 0x134 -#define QSERDES_COM_VCO_TUNE2_MODE1 0x138 -#define QSERDES_COM_VCO_TUNE_INITVAL1 0x13c -#define QSERDES_COM_VCO_TUNE_INITVAL2 0x140 -#define QSERDES_COM_VCO_TUNE_TIMER1 0x144 -#define QSERDES_COM_VCO_TUNE_TIMER2 0x148 -#define QSERDES_COM_BG_CTRL 0x170 -#define QSERDES_COM_CLK_SELECT 0x174 -#define QSERDES_COM_HSCLK_SEL 0x178 -#define QSERDES_COM_CORECLK_DIV 0x184 -#define QSERDES_COM_CORE_CLK_EN 0x18c -#define QSERDES_COM_C_READY_STATUS 0x190 -#define QSERDES_COM_CMN_CONFIG 0x194 -#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c -#define QSERDES_COM_DEBUG_BUS0 0x1a0 -#define QSERDES_COM_DEBUG_BUS1 0x1a4 -#define QSERDES_COM_DEBUG_BUS2 0x1a8 -#define QSERDES_COM_DEBUG_BUS3 0x1ac -#define QSERDES_COM_DEBUG_BUS_SEL 0x1b0 -#define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc +#include "phy-qcom-qmp-pcs-pcie-v5_20.h" -/* Only for QMP V2 PHY - TX registers */ -#define QSERDES_TX_EMP_POST1_LVL 0x018 -#define QSERDES_TX_SLEW_CNTL 0x040 -#define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054 -#define QSERDES_TX_DEBUG_BUS_SEL 0x064 -#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068 -#define QSERDES_TX_LANE_MODE 0x094 -#define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac - -/* Only for QMP V2 PHY - RX registers */ -#define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010 -#define QSERDES_RX_UCDR_SO_GAIN 0x01c -#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF 0x030 -#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER 0x034 -#define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH 0x038 -#define QSERDES_RX_UCDR_SVS_SO_GAIN 0x03c -#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040 -#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048 -#define QSERDES_RX_RX_TERM_BW 0x090 -#define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4 -#define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8 -#define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc -#define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0 -#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8 -#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc -#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0 -#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108 -#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c -#define QSERDES_RX_SIGDET_ENABLES 0x110 -#define QSERDES_RX_SIGDET_CNTRL 0x114 -#define QSERDES_RX_SIGDET_LVL 0x118 -#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c -#define QSERDES_RX_RX_BAND 0x120 -#define QSERDES_RX_RX_INTERFACE_MODE 0x12c - -/* Only for QMP V2 PHY - PCS registers */ -#define QPHY_POWER_DOWN_CONTROL 0x04 -#define QPHY_TXDEEMPH_M6DB_V0 0x24 -#define QPHY_TXDEEMPH_M3P5DB_V0 0x28 -#define QPHY_TX_LARGE_AMP_DRV_LVL 0x34 -#define QPHY_TX_LARGE_AMP_POST_EMP_LVL 0x38 -#define QPHY_TX_SMALL_AMP_DRV_LVL 0x3c -#define QPHY_TX_SMALL_AMP_POST_EMP_LVL 0x40 -#define QPHY_ENDPOINT_REFCLK_DRIVE 0x54 -#define QPHY_RX_IDLE_DTCT_CNTRL 0x58 -#define QPHY_POWER_STATE_CONFIG1 0x60 -#define QPHY_POWER_STATE_CONFIG2 0x64 -#define QPHY_POWER_STATE_CONFIG4 0x6c -#define QPHY_LOCK_DETECT_CONFIG1 0x80 -#define QPHY_LOCK_DETECT_CONFIG2 0x84 -#define QPHY_LOCK_DETECT_CONFIG3 0x88 -#define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0 -#define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4 -#define QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP 0xcc -#define QPHY_RX_SYM_RESYNC_CTRL 0x13c -#define QPHY_RX_MIN_HIBERN8_TIME 0x140 -#define QPHY_RX_SIGDET_CTRL2 0x148 -#define QPHY_RX_PWM_GEAR_BAND 0x154 -#define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8 -#define QPHY_OSC_DTCT_ACTIONS 0x1AC -#define QPHY_RX_SIGDET_LVL 0x1D8 -#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1DC -#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1E0 +#include "phy-qcom-qmp-pcie-qhp.h" /* Only for QMP V3 & V4 PHY - DP COM registers */ #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 @@ -285,21 +54,7 @@ #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c -/* Only for QMP V3 PHY - QSERDES COM registers */ -#define QSERDES_V3_COM_ATB_SEL1 0x000 -#define QSERDES_V3_COM_ATB_SEL2 0x004 -#define QSERDES_V3_COM_FREQ_UPDATE 0x008 -#define QSERDES_V3_COM_BG_TIMER 0x00c -#define QSERDES_V3_COM_SSC_EN_CENTER 0x010 -#define QSERDES_V3_COM_SSC_ADJ_PER1 0x014 -#define QSERDES_V3_COM_SSC_ADJ_PER2 0x018 -#define QSERDES_V3_COM_SSC_PER1 0x01c -#define QSERDES_V3_COM_SSC_PER2 0x020 -#define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024 -#define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028 -#define QSERDES_V3_COM_POST_DIV 0x02c -#define QSERDES_V3_COM_POST_DIV_MUX 0x030 -#define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034 +/* QSERDES V3 COM bits */ # define QSERDES_V3_COM_BIAS_EN 0x0001 # define QSERDES_V3_COM_BIAS_EN_MUX 0x0002 # define QSERDES_V3_COM_CLKBUF_R_EN 0x0004 @@ -307,200 +62,13 @@ # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010 # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020 # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040 -#define QSERDES_V3_COM_CLK_ENABLE1 0x038 -#define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c -#define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040 -#define QSERDES_V3_COM_PLL_EN 0x044 -#define QSERDES_V3_COM_PLL_IVCO 0x048 -#define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098 -#define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c -#define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0 -#define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4 -#define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8 -#define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac -#define QSERDES_V3_COM_CLK_EP_DIV 0x05c -#define QSERDES_V3_COM_CP_CTRL_MODE0 0x060 -#define QSERDES_V3_COM_CP_CTRL_MODE1 0x064 -#define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068 -#define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c -#define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070 -#define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074 -#define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080 -#define QSERDES_V3_COM_RESETSM_CNTRL 0x088 -#define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c -#define QSERDES_V3_COM_LOCK_CMP_EN 0x090 -#define QSERDES_V3_COM_LOCK_CMP_CFG 0x094 -#define QSERDES_V3_COM_DEC_START_MODE0 0x0b0 -#define QSERDES_V3_COM_DEC_START_MODE1 0x0b4 -#define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8 -#define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc -#define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0 -#define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4 -#define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8 -#define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc -#define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0 -#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8 -#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc -#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0 -#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4 -#define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec -#define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0 -#define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4 -#define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8 -#define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc -#define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100 -#define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104 -#define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108 -#define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c -#define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120 -#define QSERDES_V3_COM_CLK_SELECT 0x138 -#define QSERDES_V3_COM_HSCLK_SEL 0x13c -#define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148 -#define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c -#define QSERDES_V3_COM_CORE_CLK_EN 0x154 -#define QSERDES_V3_COM_C_READY_STATUS 0x158 -#define QSERDES_V3_COM_CMN_CONFIG 0x15c -#define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164 -#define QSERDES_V3_COM_DEBUG_BUS0 0x168 -#define QSERDES_V3_COM_DEBUG_BUS1 0x16c -#define QSERDES_V3_COM_DEBUG_BUS2 0x170 -#define QSERDES_V3_COM_DEBUG_BUS3 0x174 -#define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178 -#define QSERDES_V3_COM_CMN_MODE 0x184 -/* Only for QMP V3 PHY - TX registers */ -#define QSERDES_V3_TX_BIST_MODE_LANENO 0x000 -#define QSERDES_V3_TX_CLKBUF_ENABLE 0x008 -#define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c +/* QSERDES V3 TX bits */ # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020 - -#define QSERDES_V3_TX_TX_DRV_LVL 0x01c # define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020 -#define QSERDES_V3_TX_RESET_TSYNC_EN 0x024 -#define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028 - -#define QSERDES_V3_TX_TX_BAND 0x02c -#define QSERDES_V3_TX_SLEW_CNTL 0x030 -#define QSERDES_V3_TX_INTERFACE_SELECT 0x034 -#define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c -#define QSERDES_V3_TX_RES_CODE_LANE_RX 0x040 -#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044 -#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048 -#define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058 -#define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN 0x05c -#define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060 -#define QSERDES_V3_TX_TX_POL_INV 0x064 -#define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068 -#define QSERDES_V3_TX_LANE_MODE_1 0x08c -#define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4 -#define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0 -#define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4 -#define QSERDES_V3_TX_VMODE_CTRL1 0x0f0 - -/* Only for QMP V3 PHY - RX registers */ -#define QSERDES_V3_RX_UCDR_FO_GAIN 0x008 -#define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c -#define QSERDES_V3_RX_UCDR_SO_GAIN 0x014 -#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024 -#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 -#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c -#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030 -#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 -#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c -#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 -#define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044 -#define QSERDES_V3_RX_RX_TERM_BW 0x07c -#define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc -#define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0 -#define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8 -#define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc -#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4 -#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8 -#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc -#define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8 -#define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc -#define QSERDES_V3_RX_SIGDET_ENABLES 0x100 -#define QSERDES_V3_RX_SIGDET_CNTRL 0x104 -#define QSERDES_V3_RX_SIGDET_LVL 0x108 -#define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c -#define QSERDES_V3_RX_RX_BAND 0x110 -#define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c -#define QSERDES_V3_RX_RX_MODE_00 0x164 -#define QSERDES_V3_RX_RX_MODE_01 0x168 - -/* Only for QMP V3 PHY - PCS registers */ -#define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 -#define QPHY_V3_PCS_TXMGN_V0 0x00c -#define QPHY_V3_PCS_TXMGN_V1 0x010 -#define QPHY_V3_PCS_TXMGN_V2 0x014 -#define QPHY_V3_PCS_TXMGN_V3 0x018 -#define QPHY_V3_PCS_TXMGN_V4 0x01c -#define QPHY_V3_PCS_TXMGN_LS 0x020 -#define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c -#define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034 -#define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 -#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028 -#define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c -#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030 -#define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034 -#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038 -#define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c -#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040 -#define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044 -#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048 -#define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c -#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050 -#define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054 -#define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058 -#define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c -#define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060 -#define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064 -#define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c -#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070 -#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074 -#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078 -#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c -#define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080 -#define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084 -#define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088 -#define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c -#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 -#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 -#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 -#define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0 -#define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8 -#define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc -#define QPHY_V3_PCS_FLL_CNTRL1 0x0c4 -#define QPHY_V3_PCS_FLL_CNTRL2 0x0c8 -#define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc -#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0 -#define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4 -#define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134 -#define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138 -#define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c -#define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140 -#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8 -#define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac -#define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0 -#define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc -#define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4 -#define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8 -#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc -#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 -#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c -#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210 - -/* Only for QMP V3 PHY - PCS_MISC registers */ -#define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c -#define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c -#define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44 -#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54 -#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c -#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 - /* QMP PHY - DP PHY registers */ #define QSERDES_DP_PHY_REVISION_ID0 0x000 #define QSERDES_DP_PHY_REVISION_ID1 0x004 @@ -548,165 +116,6 @@ #define QSERDES_V3_DP_PHY_STATUS 0x0c0 -/* Only for QMP V4 PHY - QSERDES COM registers */ -#define QSERDES_V4_COM_BG_TIMER 0x00c -#define QSERDES_V4_COM_SSC_EN_CENTER 0x010 -#define QSERDES_V4_COM_SSC_ADJ_PER1 0x014 -#define QSERDES_V4_COM_SSC_PER1 0x01c -#define QSERDES_V4_COM_SSC_PER2 0x020 -#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024 -#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028 -#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030 -#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034 -#define QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN 0x044 -#define QSERDES_V4_COM_CLK_ENABLE1 0x048 -#define QSERDES_V4_COM_SYS_CLK_CTRL 0x04c -#define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050 -#define QSERDES_V4_COM_PLL_IVCO 0x058 -#define QSERDES_V4_COM_CMN_IPTRIM 0x060 -#define QSERDES_V4_COM_CP_CTRL_MODE0 0x074 -#define QSERDES_V4_COM_CP_CTRL_MODE1 0x078 -#define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c -#define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080 -#define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084 -#define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088 -#define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094 -#define QSERDES_V4_COM_RESETSM_CNTRL 0x09c -#define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4 -#define QSERDES_V4_COM_LOCK_CMP_CFG 0x0a8 -#define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac -#define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 -#define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 -#define QSERDES_V4_COM_DEC_START_MODE0 0x0bc -#define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8 -#define QSERDES_V4_COM_DEC_START_MODE1 0x0c4 -#define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc -#define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0 -#define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4 -#define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8 -#define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc -#define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0 -#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0 0x0ec -#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0 0x0f0 -#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1 0x0f4 -#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1 0x0f8 -#define QSERDES_V4_COM_VCO_TUNE_CTRL 0x108 -#define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c -#define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110 -#define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114 -#define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118 -#define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c -#define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124 -#define QSERDES_V4_COM_CMN_STATUS 0x140 -#define QSERDES_V4_COM_CLK_SELECT 0x154 -#define QSERDES_V4_COM_HSCLK_SEL 0x158 -#define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c -#define QSERDES_V4_COM_CORECLK_DIV_MODE0 0x168 -#define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c -#define QSERDES_V4_COM_CORE_CLK_EN 0x174 -#define QSERDES_V4_COM_C_READY_STATUS 0x178 -#define QSERDES_V4_COM_CMN_CONFIG 0x17c -#define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184 -#define QSERDES_V4_COM_CMN_MISC1 0x19c -#define QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV 0x1a0 -#define QSERDES_V4_COM_CMN_MODE 0x1a4 -#define QSERDES_V4_COM_VCO_DC_LEVEL_CTRL 0x1a8 -#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac -#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 -#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 -#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 -#define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc - -/* Only for QMP V4 PHY - TX registers */ -#define QSERDES_V4_TX_CLKBUF_ENABLE 0x08 -#define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x0c -#define QSERDES_V4_TX_TX_DRV_LVL 0x14 -#define QSERDES_V4_TX_RESET_TSYNC_EN 0x1c -#define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x20 -#define QSERDES_V4_TX_TX_BAND 0x24 -#define QSERDES_V4_TX_INTERFACE_SELECT 0x2c -#define QSERDES_V4_TX_RES_CODE_LANE_TX 0x34 -#define QSERDES_V4_TX_RES_CODE_LANE_RX 0x38 -#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x3c -#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40 -#define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN 0x54 -#define QSERDES_V4_TX_HIGHZ_DRVR_EN 0x58 -#define QSERDES_V4_TX_TX_POL_INV 0x5c -#define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN 0x60 -#define QSERDES_V4_TX_LANE_MODE_1 0x84 -#define QSERDES_V4_TX_LANE_MODE_2 0x88 -#define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c -#define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8 -#define QSERDES_V4_TX_TX_INTERFACE_MODE 0xbc -#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8 -#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC -#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0 -#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4 -#define QSERDES_V4_TX_VMODE_CTRL1 0xe8 -#define QSERDES_V4_TX_PI_QEC_CTRL 0x104 - -/* Only for QMP V4_20 PHY - TX registers */ -#define QSERDES_V4_20_TX_LANE_MODE_1 0x88 -#define QSERDES_V4_20_TX_LANE_MODE_2 0x8c -#define QSERDES_V4_20_TX_LANE_MODE_3 0x90 -#define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4 -#define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0 - -/* Only for QMP V4 PHY - RX registers */ -#define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 -#define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 -#define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030 -#define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 -#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c -#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 -#define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044 -#define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048 -#define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c -#define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050 -#define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054 -#define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058 -#define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060 -#define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064 -#define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068 -#define QSERDES_V4_RX_AC_JTAG_MODE 0x078 -#define QSERDES_V4_RX_RX_TERM_BW 0x080 -#define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4 -#define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8 -#define QSERDES_V4_RX_GM_CAL 0x0dc -#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 -#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec -#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 -#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 -#define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8 -#define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc -#define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100 -#define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 -#define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 -#define QSERDES_V4_RX_SIGDET_ENABLES 0x118 -#define QSERDES_V4_RX_SIGDET_CNTRL 0x11c -#define QSERDES_V4_RX_SIGDET_LVL 0x120 -#define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124 -#define QSERDES_V4_RX_RX_BAND 0x128 -#define QSERDES_V4_RX_RX_MODE_00_LOW 0x170 -#define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174 -#define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178 -#define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c -#define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180 -#define QSERDES_V4_RX_RX_MODE_01_LOW 0x184 -#define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188 -#define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c -#define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190 -#define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194 -#define QSERDES_V4_RX_RX_MODE_10_LOW 0x198 -#define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c -#define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0 -#define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4 -#define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8 -#define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4 -#define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8 -#define QSERDES_V4_RX_DCC_CTRL1 0x1bc -#define QSERDES_V4_RX_VTH_CODE 0x1c4 - /* Only for QMP V4 PHY - DP PHY registers */ #define QSERDES_V4_DP_PHY_CFG_1 0x014 #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054 @@ -718,328 +127,6 @@ #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8 #define QSERDES_V4_DP_PHY_STATUS 0x0dc -/* Only for QMP V4_20 PHY - RX registers */ -#define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008 -#define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058 -#define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac -#define QSERDES_V4_20_RX_DFE_3 0x110 -#define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134 -#define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138 -#define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150 -#define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178 -#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8 -#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc -#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0 -#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4 -#define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8 -#define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc -#define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0 -#define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4 -#define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8 -#define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec -#define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0 -#define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4 -#define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8 -#define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc -#define QSERDES_V4_20_RX_PHPRE_CTRL 0x200 -#define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c -#define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c - -/* Only for QMP V4 PHY - UFS PCS registers */ -#define QPHY_V4_PCS_UFS_PHY_START 0x000 -#define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004 -#define QPHY_V4_PCS_UFS_SW_RESET 0x008 -#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c -#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 -#define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c -#define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 -#define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 -#define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 -#define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 -#define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 -#define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 -#define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148 -#define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 -#define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158 -#define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160 -#define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168 -#define QPHY_V4_PCS_UFS_READY_STATUS 0x180 -#define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 -#define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 - -/* PCIE GEN3 COM registers */ -#define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 -#define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 -#define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 -#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 -#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c -#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 -#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 -#define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 -#define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 -#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c -#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70 -#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78 -#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c -#define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98 -#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4 -#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8 -#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0 -#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4 -#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc -#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0 -#define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc -#define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0 -#define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8 -#define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100 -#define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108 -#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c -#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120 -#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124 -#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128 -#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c -#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130 -#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150 -#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158 -#define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178 -#define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8 -#define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc -#define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0 -#define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0 -#define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8 -#define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0 -#define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc -#define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c -#define PCIE_GEN3_QHP_COM_CMN_MODE 0x224 -#define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228 -#define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c - -/* PCIE GEN3 QHP Lane registers */ -#define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc -#define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10 -#define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14 -#define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18 -#define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60 -#define PCIE_GEN3_QHP_L0_LANE_MODE 0x64 -#define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c -#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0 -#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4 -#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8 -#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0 -#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4 -#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8 -#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc -#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0 -#define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc -#define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100 -#define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108 -#define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114 -#define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118 -#define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c -#define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120 -#define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124 -#define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128 -#define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130 -#define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134 -#define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138 -#define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c -#define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154 -#define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160 -#define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168 -#define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c -#define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178 -#define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180 -#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184 -#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188 -#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c -#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190 -#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194 -#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198 -#define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c -#define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4 -#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0 -#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4 -#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8 -#define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230 -#define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234 -#define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238 -#define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4 -#define PCIE_GEN3_QHP_L0_RSM_START 0x2a8 -#define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac -#define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0 -#define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8 -#define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0 -#define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4 -#define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc - -/* PCIE GEN3 PCS registers */ -#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c -#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40 -#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54 -#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68 -#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c -#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c -#define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174 - -/* Only for QMP V4 PHY - USB/PCIe PCS registers */ -#define QPHY_V4_PCS_SW_RESET 0x000 -#define QPHY_V4_PCS_REVISION_ID0 0x004 -#define QPHY_V4_PCS_REVISION_ID1 0x008 -#define QPHY_V4_PCS_REVISION_ID2 0x00c -#define QPHY_V4_PCS_REVISION_ID3 0x010 -#define QPHY_V4_PCS_PCS_STATUS1 0x014 -#define QPHY_V4_PCS_PCS_STATUS2 0x018 -#define QPHY_V4_PCS_PCS_STATUS3 0x01c -#define QPHY_V4_PCS_PCS_STATUS4 0x020 -#define QPHY_V4_PCS_PCS_STATUS5 0x024 -#define QPHY_V4_PCS_PCS_STATUS6 0x028 -#define QPHY_V4_PCS_PCS_STATUS7 0x02c -#define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030 -#define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034 -#define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038 -#define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c -#define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040 -#define QPHY_V4_PCS_START_CONTROL 0x044 -#define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048 -#define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c -#define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050 -#define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054 -#define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058 -#define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c -#define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060 -#define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064 -#define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068 -#define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c -#define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070 -#define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074 -#define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078 -#define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c -#define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080 -#define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084 -#define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088 -#define QPHY_V4_PCS_CLAMP_ENABLE 0x08c -#define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090 -#define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094 -#define QPHY_V4_PCS_FLL_CNTRL1 0x098 -#define QPHY_V4_PCS_FLL_CNTRL2 0x09c -#define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0 -#define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4 -#define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8 -#define QPHY_V4_PCS_TEST_CONTROL1 0x0ac -#define QPHY_V4_PCS_TEST_CONTROL2 0x0b0 -#define QPHY_V4_PCS_TEST_CONTROL3 0x0b4 -#define QPHY_V4_PCS_TEST_CONTROL4 0x0b8 -#define QPHY_V4_PCS_TEST_CONTROL5 0x0bc -#define QPHY_V4_PCS_TEST_CONTROL6 0x0c0 -#define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4 -#define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8 -#define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc -#define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0 -#define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4 -#define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8 -#define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc -#define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0 -#define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4 -#define QPHY_V4_PCS_BIST_CTRL 0x0e8 -#define QPHY_V4_PCS_PRBS_POLY0 0x0ec -#define QPHY_V4_PCS_PRBS_POLY1 0x0f0 -#define QPHY_V4_PCS_FIXED_PAT0 0x0f4 -#define QPHY_V4_PCS_FIXED_PAT1 0x0f8 -#define QPHY_V4_PCS_FIXED_PAT2 0x0fc -#define QPHY_V4_PCS_FIXED_PAT3 0x100 -#define QPHY_V4_PCS_FIXED_PAT4 0x104 -#define QPHY_V4_PCS_FIXED_PAT5 0x108 -#define QPHY_V4_PCS_FIXED_PAT6 0x10c -#define QPHY_V4_PCS_FIXED_PAT7 0x110 -#define QPHY_V4_PCS_FIXED_PAT8 0x114 -#define QPHY_V4_PCS_FIXED_PAT9 0x118 -#define QPHY_V4_PCS_FIXED_PAT10 0x11c -#define QPHY_V4_PCS_FIXED_PAT11 0x120 -#define QPHY_V4_PCS_FIXED_PAT12 0x124 -#define QPHY_V4_PCS_FIXED_PAT13 0x128 -#define QPHY_V4_PCS_FIXED_PAT14 0x12c -#define QPHY_V4_PCS_FIXED_PAT15 0x130 -#define QPHY_V4_PCS_TXMGN_CONFIG 0x134 -#define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138 -#define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c -#define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140 -#define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144 -#define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148 -#define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c -#define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150 -#define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154 -#define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158 -#define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c -#define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160 -#define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164 -#define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168 -#define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c -#define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170 -#define QPHY_V4_PCS_G3S2_POST_GAIN 0x174 -#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178 -#define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c -#define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180 -#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184 -#define QPHY_V4_PCS_RX_SIGDET_LVL 0x188 -#define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c -#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 -#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 -#define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198 -#define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c -#define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0 -#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 -#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 -#define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac -#define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0 -#define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4 -#define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8 -#define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc -#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0 -#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4 -#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8 -#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc -#define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0 -#define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4 -#define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8 -#define QPHY_V4_PCS_EQ_CONFIG1 0x1dc -#define QPHY_V4_PCS_EQ_CONFIG2 0x1e0 -#define QPHY_V4_PCS_EQ_CONFIG3 0x1e4 -#define QPHY_V4_PCS_EQ_CONFIG4 0x1e8 -#define QPHY_V4_PCS_EQ_CONFIG5 0x1ec -#define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x300 -#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304 -#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308 -#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c -#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310 -#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314 -#define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318 -#define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x31c -#define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x320 -#define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324 -#define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x328 -#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x32c -#define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x330 -#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x334 -#define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x338 -#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x33c -#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x340 -#define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x344 -#define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x348 -#define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x34c -#define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x350 -#define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x354 -#define QPHY_V4_PCS_USB3_TEST_CONTROL 0x358 - -/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */ -#define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188 -#define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8 -#define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0 -#define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4 - -/* Only for QMP V4 PHY - UNI has 0x300 offset for PCS_USB3 regs */ -#define QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x618 -#define QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x638 - /* Only for QMP V4 PHY - PCS_MISC registers */ #define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 @@ -1048,275 +135,4 @@ #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 -/* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */ -#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c -#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 -#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c -#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 -#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 -#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 -#define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 -#define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 -#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 -#define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc -#define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 - -#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 -#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 -#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 -#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc -#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 -#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824 -#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828 - -/* Only for QMP V5 PHY - QSERDES COM registers */ -#define QSERDES_V5_COM_SSC_EN_CENTER 0x010 -#define QSERDES_V5_COM_SSC_PER1 0x01c -#define QSERDES_V5_COM_SSC_PER2 0x020 -#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024 -#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028 -#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030 -#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034 -#define QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN 0x044 -#define QSERDES_V5_COM_CLK_ENABLE1 0x048 -#define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050 -#define QSERDES_V5_COM_PLL_IVCO 0x058 -#define QSERDES_V5_COM_CP_CTRL_MODE0 0x074 -#define QSERDES_V5_COM_CP_CTRL_MODE1 0x078 -#define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c -#define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080 -#define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084 -#define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088 -#define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094 -#define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4 -#define QSERDES_V5_COM_LOCK_CMP_CFG 0x0a8 -#define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac -#define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0 -#define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4 -#define QSERDES_V5_COM_DEC_START_MODE0 0x0bc -#define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8 -#define QSERDES_V5_COM_DEC_START_MODE1 0x0c4 -#define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc -#define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0 -#define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4 -#define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8 -#define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc -#define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0 -#define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c -#define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110 -#define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114 -#define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118 -#define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c -#define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124 -#define QSERDES_V5_COM_CLK_SELECT 0x154 -#define QSERDES_V5_COM_HSCLK_SEL 0x158 -#define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c -#define QSERDES_V5_COM_CORECLK_DIV_MODE0 0x168 -#define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c -#define QSERDES_V5_COM_CORE_CLK_EN 0x174 -#define QSERDES_V5_COM_CMN_CONFIG 0x17c -#define QSERDES_V5_COM_CMN_MISC1 0x19c -#define QSERDES_V5_COM_CMN_MODE 0x1a4 -#define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL 0x1a8 -#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac -#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 -#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 -#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc -#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 - -/* Only for QMP V5 PHY - TX registers */ -#define QSERDES_V5_TX_RES_CODE_LANE_TX 0x34 -#define QSERDES_V5_TX_RES_CODE_LANE_RX 0x38 -#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x3c -#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x40 -#define QSERDES_V5_TX_LANE_MODE_1 0x84 -#define QSERDES_V5_TX_LANE_MODE_2 0x88 -#define QSERDES_V5_TX_LANE_MODE_3 0x8c -#define QSERDES_V5_TX_LANE_MODE_4 0x90 -#define QSERDES_V5_TX_LANE_MODE_5 0x94 -#define QSERDES_V5_TX_RCV_DETECT_LVL_2 0xa4 -#define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0xc0 -#define QSERDES_V5_TX_PI_QEC_CTRL 0xe4 -#define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178 -#define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c -#define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180 -#define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184 - -/* Only for QMP V5_20 PHY - TX registers */ -#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 -#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 -#define QSERDES_V5_20_TX_LANE_MODE_1 0x78 -#define QSERDES_V5_20_TX_LANE_MODE_2 0x7c - -/* Only for QMP V5 PHY - RX registers */ -#define QSERDES_V5_RX_UCDR_FO_GAIN 0x008 -#define QSERDES_V5_RX_UCDR_SO_GAIN 0x014 -#define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030 -#define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 -#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c -#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 -#define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044 -#define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048 -#define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c -#define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050 -#define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054 -#define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058 -#define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060 -#define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064 -#define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068 -#define QSERDES_V5_RX_AC_JTAG_MODE 0x078 -#define QSERDES_V5_RX_RX_TERM_BW 0x080 -#define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc -#define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4 -#define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8 -#define QSERDES_V5_RX_GM_CAL 0x0dc -#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 -#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec -#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 -#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 -#define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8 -#define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc -#define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100 -#define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 -#define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 -#define QSERDES_V5_RX_SIGDET_ENABLES 0x118 -#define QSERDES_V5_RX_SIGDET_CNTRL 0x11c -#define QSERDES_V5_RX_SIGDET_LVL 0x120 -#define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124 -#define QSERDES_V5_RX_RX_BAND 0x128 -#define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c -#define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160 -#define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164 -#define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168 -#define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c -#define QSERDES_V5_RX_RX_MODE_01_LOW 0x170 -#define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174 -#define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178 -#define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c -#define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180 -#define QSERDES_V5_RX_RX_MODE_10_LOW 0x184 -#define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188 -#define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c -#define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190 -#define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194 -#define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0 -#define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 -#define QSERDES_V5_RX_DCC_CTRL1 0x1a8 -#define QSERDES_V5_RX_VTH_CODE 0x1b0 - -/* Only for QMP V5_20 PHY - RX registers */ -#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008 -#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c -#define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020 -#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c -#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030 -#define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c -#define QSERDES_V5_20_RX_DFE_3 0x090 -#define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4 -#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4 -#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8 -#define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc -#define QSERDES_V5_20_RX_GM_CAL 0x0ec -#define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108 -#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164 -#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168 -#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c -#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174 -#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178 -#define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c -#define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180 -#define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184 -#define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188 -#define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c -#define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190 -#define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194 -#define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198 -#define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c -#define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0 -#define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4 -#define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8 -#define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac -#define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0 -#define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4 -#define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0 -#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4 -#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8 -#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc -#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200 -#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204 -#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208 -#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210 -#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218 -#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220 - -/* Only for QMP V5 PHY - USB/PCIe PCS registers */ -#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc -#define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170 -#define QPHY_V5_PCS_RX_SIGDET_LVL 0x188 -#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198 -#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0 -#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4 - -/* Only for QMP V5 PHY - PCS_PCIE registers */ -#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 -#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 -#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 -#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 - -/* Only for QMP V5_20 PHY - PCIe PCS registers */ -#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c -#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 -#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0 -#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 -#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c -#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184 - -/* Only for QMP V5 PHY - UFS PCS registers */ -#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c -#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 -#define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c -#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 -#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 -#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 -#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 -#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 -#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 -#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154 -#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158 -#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160 -#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168 -#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 -#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 - -/* Only for QMP V5 PHY - USB3 have different offsets than V4 */ -#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x300 -#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304 -#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308 -#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c -#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310 -#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314 -#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318 -#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x31c -#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x320 -#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324 -#define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x328 -#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x32c -#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x330 -#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x334 -#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x338 -#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x33c -#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x340 -#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x344 -#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x348 -#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x34c -#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x350 -#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x354 -#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x358 -#define QPHY_V5_PCS_USB3_TEST_CONTROL 0x35c -#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x360 - -/* Only for QMP V5 PHY - UNI has 0x1000 offset for PCS_USB3 regs */ -#define QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x1018 -#define QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x103c - #endif diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 6711659f727c..0b1e9337ee8e 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -978,7 +978,9 @@ static irqreturn_t rockchip_usb2phy_irq(int irq, void *data) switch (rport->port_id) { case USB2PHY_PORT_OTG: - ret |= rockchip_usb2phy_otg_mux_irq(irq, rport); + if (rport->mode != USB_DR_MODE_HOST && + rport->mode != USB_DR_MODE_UNKNOWN) + ret |= rockchip_usb2phy_otg_mux_irq(irq, rport); break; case USB2PHY_PORT_HOST: ret |= rockchip_usb2phy_linestate_irq(irq, rport); @@ -1162,6 +1164,12 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy, EXTCON_USB_HOST, &rport->event_nb); if (ret) dev_err(rphy->dev, "register USB HOST notifier failed\n"); + + if (!of_property_read_bool(rphy->dev->of_node, "extcon")) { + /* do initial sync of usb state */ + ret = property_enabled(rphy->grf, &rport->port_cfg->utmi_id); + extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !ret); + } } out: @@ -1283,7 +1291,7 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev) phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops); if (IS_ERR(phy)) { - dev_err(dev, "failed to create phy\n"); + dev_err_probe(dev, PTR_ERR(phy), "failed to create phy\n"); ret = PTR_ERR(phy); goto put_child; } diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile index 65e4cc59403f..afb34a153e34 100644 --- a/drivers/phy/samsung/Makefile +++ b/drivers/phy/samsung/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-exynos-ufs.o phy-exynos-ufs-y += phy-samsung-ufs.o phy-exynos-ufs-y += phy-exynos7-ufs.o phy-exynos-ufs-y += phy-exynosautov9-ufs.o +phy-exynos-ufs-y += phy-fsd-ufs.o obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o phy-exynos-usb2-y += phy-samsung-usb2.o phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o diff --git a/drivers/phy/samsung/phy-exynos7-ufs.c b/drivers/phy/samsung/phy-exynos7-ufs.c index 7c9008e163db..a982e7c128c5 100644 --- a/drivers/phy/samsung/phy-exynos7-ufs.c +++ b/drivers/phy/samsung/phy-exynos7-ufs.c @@ -11,6 +11,8 @@ #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0) +#define EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e + /* Calibration for phy initialization */ static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = { PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY), @@ -66,12 +68,18 @@ static const struct samsung_ufs_phy_cfg *exynos7_ufs_phy_cfgs[CFG_TAG_MAX] = { [CFG_POST_PWR_HS] = exynos7_post_pwr_hs_cfg, }; +static const char * const exynos7_ufs_phy_clks[] = { + "tx0_symbol_clk", "rx0_symbol_clk", "rx1_symbol_clk", "ref_clk", +}; + const struct samsung_ufs_phy_drvdata exynos7_ufs_phy = { - .cfg = exynos7_ufs_phy_cfgs, + .cfgs = exynos7_ufs_phy_cfgs, .isol = { .offset = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL, .mask = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK, .en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN, }, - .has_symbol_clk = 1, + .clk_list = exynos7_ufs_phy_clks, + .num_clks = ARRAY_SIZE(exynos7_ufs_phy_clks), + .cdr_lock_status_offset = EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS, }; diff --git a/drivers/phy/samsung/phy-exynosautov9-ufs.c b/drivers/phy/samsung/phy-exynosautov9-ufs.c index 36398a15c2db..49e2bcbef0b4 100644 --- a/drivers/phy/samsung/phy-exynosautov9-ufs.c +++ b/drivers/phy/samsung/phy-exynosautov9-ufs.c @@ -10,6 +10,7 @@ #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL 0x728 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0) +#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e #define PHY_TRSV_REG_CFG_AUTOV9(o, v, d) \ PHY_TRSV_REG_CFG_OFFSET(o, v, d, 0x50) @@ -31,22 +32,22 @@ static const struct samsung_ufs_phy_cfg exynosautov9_pre_init_cfg[] = { PHY_COMN_REG_CFG(0x023, 0xc0, PWR_MODE_ANY), PHY_COMN_REG_CFG(0x023, 0x00, PWR_MODE_ANY), - PHY_TRSV_REG_CFG(0x042, 0x5d, PWR_MODE_ANY), - PHY_TRSV_REG_CFG(0x043, 0x80, PWR_MODE_ANY), + PHY_TRSV_REG_CFG_AUTOV9(0x042, 0x5d, PWR_MODE_ANY), + PHY_TRSV_REG_CFG_AUTOV9(0x043, 0x80, PWR_MODE_ANY), END_UFS_PHY_CFG, }; /* Calibration for HS mode series A/B */ static const struct samsung_ufs_phy_cfg exynosautov9_pre_pwr_hs_cfg[] = { - PHY_TRSV_REG_CFG(0x032, 0xbc, PWR_MODE_HS_ANY), - PHY_TRSV_REG_CFG(0x03c, 0x7f, PWR_MODE_HS_ANY), - PHY_TRSV_REG_CFG(0x048, 0xc0, PWR_MODE_HS_ANY), + PHY_TRSV_REG_CFG_AUTOV9(0x032, 0xbc, PWR_MODE_HS_ANY), + PHY_TRSV_REG_CFG_AUTOV9(0x03c, 0x7f, PWR_MODE_HS_ANY), + PHY_TRSV_REG_CFG_AUTOV9(0x048, 0xc0, PWR_MODE_HS_ANY), - PHY_TRSV_REG_CFG(0x04a, 0x00, PWR_MODE_HS_G3_SER_B), - PHY_TRSV_REG_CFG(0x04b, 0x10, PWR_MODE_HS_G1_SER_B | - PWR_MODE_HS_G3_SER_B), - PHY_TRSV_REG_CFG(0x04d, 0x63, PWR_MODE_HS_G3_SER_B), + PHY_TRSV_REG_CFG_AUTOV9(0x04a, 0x00, PWR_MODE_HS_G3_SER_B), + PHY_TRSV_REG_CFG_AUTOV9(0x04b, 0x10, PWR_MODE_HS_G1_SER_B | + PWR_MODE_HS_G3_SER_B), + PHY_TRSV_REG_CFG_AUTOV9(0x04d, 0x63, PWR_MODE_HS_G3_SER_B), END_UFS_PHY_CFG, }; @@ -56,12 +57,18 @@ static const struct samsung_ufs_phy_cfg *exynosautov9_ufs_phy_cfgs[CFG_TAG_MAX] [CFG_PRE_PWR_HS] = exynosautov9_pre_pwr_hs_cfg, }; +static const char * const exynosautov9_ufs_phy_clks[] = { + "ref_clk", +}; + const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy = { - .cfg = exynosautov9_ufs_phy_cfgs, + .cfgs = exynosautov9_ufs_phy_cfgs, .isol = { .offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL, .mask = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK, .en = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN, }, - .has_symbol_clk = 0, + .clk_list = exynosautov9_ufs_phy_clks, + .num_clks = ARRAY_SIZE(exynosautov9_ufs_phy_clks), + .cdr_lock_status_offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS, }; diff --git a/drivers/phy/samsung/phy-fsd-ufs.c b/drivers/phy/samsung/phy-fsd-ufs.c new file mode 100644 index 000000000000..d36cabd53434 --- /dev/null +++ b/drivers/phy/samsung/phy-fsd-ufs.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * UFS PHY driver data for FSD SoC + * + * Copyright (C) 2022 Samsung Electronics Co., Ltd. + * + */ +#include "phy-samsung-ufs.h" + +#define FSD_EMBEDDED_COMBO_PHY_CTRL 0x724 +#define FSD_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1 +#define FSD_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0) +#define FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x6e + +static const struct samsung_ufs_phy_cfg fsd_pre_init_cfg[] = { + PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY), + PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY), + PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY), + PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY), + END_UFS_PHY_CFG +}; + +/* Calibration for HS mode series A/B */ +static const struct samsung_ufs_phy_cfg fsd_pre_pwr_hs_cfg[] = { + END_UFS_PHY_CFG +}; + +/* Calibration for HS mode series A/B atfer PMC */ +static const struct samsung_ufs_phy_cfg fsd_post_pwr_hs_cfg[] = { + END_UFS_PHY_CFG +}; + +static const struct samsung_ufs_phy_cfg *fsd_ufs_phy_cfgs[CFG_TAG_MAX] = { + [CFG_PRE_INIT] = fsd_pre_init_cfg, + [CFG_PRE_PWR_HS] = fsd_pre_pwr_hs_cfg, + [CFG_POST_PWR_HS] = fsd_post_pwr_hs_cfg, +}; + +static const char * const fsd_ufs_phy_clks[] = { + "ref_clk", +}; + +const struct samsung_ufs_phy_drvdata fsd_ufs_phy = { + .cfgs = fsd_ufs_phy_cfgs, + .isol = { + .offset = FSD_EMBEDDED_COMBO_PHY_CTRL, + .mask = FSD_EMBEDDED_COMBO_PHY_CTRL_MASK, + .en = FSD_EMBEDDED_COMBO_PHY_CTRL_EN, + }, + .clk_list = fsd_ufs_phy_clks, + .num_clks = ARRAY_SIZE(fsd_ufs_phy_clks), + .cdr_lock_status_offset = FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS, +}; diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c index 602ddef259eb..183c88e3d1ec 100644 --- a/drivers/phy/samsung/phy-samsung-ufs.c +++ b/drivers/phy/samsung/phy-samsung-ufs.c @@ -63,7 +63,8 @@ static int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy) } err = readl_poll_timeout( - ufs_phy->reg_pma + PHY_APB_ADDR(PHY_CDR_LOCK_STATUS), + ufs_phy->reg_pma + + PHY_APB_ADDR(ufs_phy->drvdata->cdr_lock_status_offset), val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us); if (err) dev_err(ufs_phy->dev, @@ -75,7 +76,7 @@ out: static int samsung_ufs_phy_calibrate(struct phy *phy) { struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy); - struct samsung_ufs_phy_cfg **cfgs = ufs_phy->cfg; + const struct samsung_ufs_phy_cfg * const *cfgs = ufs_phy->cfgs; const struct samsung_ufs_phy_cfg *cfg; int err = 0; int i; @@ -130,113 +131,63 @@ out: return err; } -static int samsung_ufs_phy_symbol_clk_init(struct samsung_ufs_phy *phy) -{ - int ret; - - phy->tx0_symbol_clk = devm_clk_get(phy->dev, "tx0_symbol_clk"); - if (IS_ERR(phy->tx0_symbol_clk)) { - dev_err(phy->dev, "failed to get tx0_symbol_clk clock\n"); - return PTR_ERR(phy->tx0_symbol_clk); - } - - phy->rx0_symbol_clk = devm_clk_get(phy->dev, "rx0_symbol_clk"); - if (IS_ERR(phy->rx0_symbol_clk)) { - dev_err(phy->dev, "failed to get rx0_symbol_clk clock\n"); - return PTR_ERR(phy->rx0_symbol_clk); - } - - phy->rx1_symbol_clk = devm_clk_get(phy->dev, "rx1_symbol_clk"); - if (IS_ERR(phy->rx1_symbol_clk)) { - dev_err(phy->dev, "failed to get rx1_symbol_clk clock\n"); - return PTR_ERR(phy->rx1_symbol_clk); - } - - ret = clk_prepare_enable(phy->tx0_symbol_clk); - if (ret) { - dev_err(phy->dev, "%s: tx0_symbol_clk enable failed %d\n", __func__, ret); - goto out; - } - - ret = clk_prepare_enable(phy->rx0_symbol_clk); - if (ret) { - dev_err(phy->dev, "%s: rx0_symbol_clk enable failed %d\n", __func__, ret); - goto out_disable_tx0_clk; - } - - ret = clk_prepare_enable(phy->rx1_symbol_clk); - if (ret) { - dev_err(phy->dev, "%s: rx1_symbol_clk enable failed %d\n", __func__, ret); - goto out_disable_rx0_clk; - } - - return 0; - -out_disable_rx0_clk: - clk_disable_unprepare(phy->rx0_symbol_clk); -out_disable_tx0_clk: - clk_disable_unprepare(phy->tx0_symbol_clk); -out: - return ret; -} - static int samsung_ufs_phy_clks_init(struct samsung_ufs_phy *phy) { - int ret; + int i; + const struct samsung_ufs_phy_drvdata *drvdata = phy->drvdata; + int num_clks = drvdata->num_clks; - phy->ref_clk = devm_clk_get(phy->dev, "ref_clk"); - if (IS_ERR(phy->ref_clk)) - dev_err(phy->dev, "failed to get ref_clk clock\n"); + phy->clks = devm_kcalloc(phy->dev, num_clks, sizeof(*phy->clks), + GFP_KERNEL); + if (!phy->clks) + return -ENOMEM; - ret = clk_prepare_enable(phy->ref_clk); - if (ret) { - dev_err(phy->dev, "%s: ref_clk enable failed %d\n", __func__, ret); - return ret; - } + for (i = 0; i < num_clks; i++) + phy->clks[i].id = drvdata->clk_list[i]; - dev_dbg(phy->dev, "UFS MPHY ref_clk_rate = %ld\n", clk_get_rate(phy->ref_clk)); - - return 0; + return devm_clk_bulk_get(phy->dev, num_clks, phy->clks); } static int samsung_ufs_phy_init(struct phy *phy) { struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy); - int ret; ss_phy->lane_cnt = phy->attrs.bus_width; ss_phy->ufs_phy_state = CFG_PRE_INIT; - if (ss_phy->drvdata->has_symbol_clk) { - ret = samsung_ufs_phy_symbol_clk_init(ss_phy); - if (ret) - dev_err(ss_phy->dev, "failed to set ufs phy symbol clocks\n"); - } - - ret = samsung_ufs_phy_clks_init(ss_phy); - if (ret) - dev_err(ss_phy->dev, "failed to set ufs phy clocks\n"); - - ret = samsung_ufs_phy_calibrate(phy); - if (ret) - dev_err(ss_phy->dev, "ufs phy calibration failed\n"); - - return ret; + return 0; } static int samsung_ufs_phy_power_on(struct phy *phy) { struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy); + int ret; samsung_ufs_phy_ctrl_isol(ss_phy, false); - return 0; + + ret = clk_bulk_prepare_enable(ss_phy->drvdata->num_clks, ss_phy->clks); + if (ret) { + dev_err(ss_phy->dev, "failed to enable ufs phy clocks\n"); + return ret; + } + + if (ss_phy->ufs_phy_state == CFG_PRE_INIT) { + ret = samsung_ufs_phy_calibrate(phy); + if (ret) + dev_err(ss_phy->dev, "ufs phy calibration failed\n"); + } + + return ret; } static int samsung_ufs_phy_power_off(struct phy *phy) { struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy); + clk_bulk_disable_unprepare(ss_phy->drvdata->num_clks, ss_phy->clks); + samsung_ufs_phy_ctrl_isol(ss_phy, true); + return 0; } @@ -257,13 +208,7 @@ static int samsung_ufs_phy_exit(struct phy *phy) { struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy); - clk_disable_unprepare(ss_phy->ref_clk); - - if (ss_phy->drvdata->has_symbol_clk) { - clk_disable_unprepare(ss_phy->tx0_symbol_clk); - clk_disable_unprepare(ss_phy->rx0_symbol_clk); - clk_disable_unprepare(ss_phy->rx1_symbol_clk); - } + ss_phy->ufs_phy_state = CFG_TAG_MAX; return 0; } @@ -288,6 +233,7 @@ static int samsung_ufs_phy_probe(struct platform_device *pdev) struct phy *gen_phy; struct phy_provider *phy_provider; const struct samsung_ufs_phy_drvdata *drvdata; + u32 isol_offset; int err = 0; match = of_match_node(samsung_ufs_phy_match, dev->of_node); @@ -327,10 +273,21 @@ static int samsung_ufs_phy_probe(struct platform_device *pdev) drvdata = match->data; phy->dev = dev; phy->drvdata = drvdata; - phy->cfg = (struct samsung_ufs_phy_cfg **)drvdata->cfg; - phy->isol = &drvdata->isol; + phy->cfgs = drvdata->cfgs; + memcpy(&phy->isol, &drvdata->isol, sizeof(phy->isol)); + + if (!of_property_read_u32_index(dev->of_node, "samsung,pmu-syscon", 1, + &isol_offset)) + phy->isol.offset = isol_offset; + phy->lane_cnt = PHY_DEF_LANE_CNT; + err = samsung_ufs_phy_clks_init(phy); + if (err) { + dev_err(dev, "failed to get phy clocks\n"); + goto out; + } + phy_set_drvdata(gen_phy, phy); phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); @@ -350,6 +307,9 @@ static const struct of_device_id samsung_ufs_phy_match[] = { }, { .compatible = "samsung,exynosautov9-ufs-phy", .data = &exynosautov9_ufs_phy, + }, { + .compatible = "tesla,fsd-ufs-phy", + .data = &fsd_ufs_phy, }, {}, }; diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h index 91a0e9f94f98..e122960cfee8 100644 --- a/drivers/phy/samsung/phy-samsung-ufs.h +++ b/drivers/phy/samsung/phy-samsung-ufs.h @@ -40,7 +40,6 @@ /* UFS PHY registers */ #define PHY_PLL_LOCK_STATUS 0x1e -#define PHY_CDR_LOCK_STATUS 0x5e #define PHY_PLL_LOCK_BIT BIT(5) #define PHY_CDR_LOCK_BIT BIT(4) @@ -101,28 +100,28 @@ struct samsung_ufs_phy_cfg { u8 id; }; +struct samsung_ufs_phy_pmu_isol { + u32 offset; + u32 mask; + u32 en; +}; + struct samsung_ufs_phy_drvdata { - const struct samsung_ufs_phy_cfg **cfg; - struct pmu_isol { - u32 offset; - u32 mask; - u32 en; - } isol; - bool has_symbol_clk; + const struct samsung_ufs_phy_cfg **cfgs; + struct samsung_ufs_phy_pmu_isol isol; + const char * const *clk_list; + int num_clks; + u32 cdr_lock_status_offset; }; struct samsung_ufs_phy { struct device *dev; void __iomem *reg_pma; struct regmap *reg_pmu; - struct clk *ref_clk; - struct clk *ref_clk_parent; - struct clk *tx0_symbol_clk; - struct clk *rx0_symbol_clk; - struct clk *rx1_symbol_clk; + struct clk_bulk_data *clks; const struct samsung_ufs_phy_drvdata *drvdata; - struct samsung_ufs_phy_cfg **cfg; - const struct pmu_isol *isol; + const struct samsung_ufs_phy_cfg * const *cfgs; + struct samsung_ufs_phy_pmu_isol isol; u8 lane_cnt; int ufs_phy_state; enum phy_mode mode; @@ -136,11 +135,12 @@ static inline struct samsung_ufs_phy *get_samsung_ufs_phy(struct phy *phy) static inline void samsung_ufs_phy_ctrl_isol( struct samsung_ufs_phy *phy, u32 isol) { - regmap_update_bits(phy->reg_pmu, phy->isol->offset, - phy->isol->mask, isol ? 0 : phy->isol->en); + regmap_update_bits(phy->reg_pmu, phy->isol.offset, + phy->isol.mask, isol ? 0 : phy->isol.en); } extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy; extern const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy; +extern const struct samsung_ufs_phy_drvdata fsd_ufs_phy; #endif /* _PHY_SAMSUNG_UFS_ */ diff --git a/drivers/phy/st/phy-stm32-usbphyc.c b/drivers/phy/st/phy-stm32-usbphyc.c index 007a23c78d56..a98c911cc37a 100644 --- a/drivers/phy/st/phy-stm32-usbphyc.c +++ b/drivers/phy/st/phy-stm32-usbphyc.c @@ -358,7 +358,9 @@ static int stm32_usbphyc_phy_init(struct phy *phy) return 0; pll_disable: - return stm32_usbphyc_pll_disable(usbphyc); + stm32_usbphyc_pll_disable(usbphyc); + + return ret; } static int stm32_usbphyc_phy_exit(struct phy *phy) diff --git a/drivers/phy/tegra/phy-tegra194-p2u.c b/drivers/phy/tegra/phy-tegra194-p2u.c index 3ee02b9eb04f..1415ca71de38 100644 --- a/drivers/phy/tegra/phy-tegra194-p2u.c +++ b/drivers/phy/tegra/phy-tegra194-p2u.c @@ -2,7 +2,7 @@ /* * P2U (PIPE to UPHY) driver for Tegra T194 SoC * - * Copyright (C) 2019 NVIDIA Corporation. + * Copyright (C) 2019-2022 NVIDIA Corporation. * * Author: Vidya Sagar */ @@ -14,6 +14,9 @@ #include #include +#define P2U_CONTROL_CMN 0x74 +#define P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN BIT(20) + #define P2U_PERIODIC_EQ_CTRL_GEN3 0xc0 #define P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN BIT(0) #define P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN BIT(1) @@ -24,8 +27,17 @@ #define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK 0xffff #define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL 160 +#define P2U_DIR_SEARCH_CTRL 0xd4 +#define P2U_DIR_SEARCH_CTRL_GEN4_FINE_GRAIN_SEARCH_TWICE BIT(18) + +struct tegra_p2u_of_data { + bool one_dir_search; +}; + struct tegra_p2u { void __iomem *base; + bool skip_sz_protection_en; /* Needed to support two retimers */ + struct tegra_p2u_of_data *of_data; }; static inline void p2u_writel(struct tegra_p2u *phy, const u32 value, @@ -44,6 +56,12 @@ static int tegra_p2u_power_on(struct phy *x) struct tegra_p2u *phy = phy_get_drvdata(x); u32 val; + if (phy->skip_sz_protection_en) { + val = p2u_readl(phy, P2U_CONTROL_CMN); + val |= P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN; + p2u_writel(phy, val, P2U_CONTROL_CMN); + } + val = p2u_readl(phy, P2U_PERIODIC_EQ_CTRL_GEN3); val &= ~P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN; val |= P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN; @@ -58,6 +76,12 @@ static int tegra_p2u_power_on(struct phy *x) val |= P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL; p2u_writel(phy, val, P2U_RX_DEBOUNCE_TIME); + if (phy->of_data->one_dir_search) { + val = p2u_readl(phy, P2U_DIR_SEARCH_CTRL); + val &= ~P2U_DIR_SEARCH_CTRL_GEN4_FINE_GRAIN_SEARCH_TWICE; + p2u_writel(phy, val, P2U_DIR_SEARCH_CTRL); + } + return 0; } @@ -77,10 +101,19 @@ static int tegra_p2u_probe(struct platform_device *pdev) if (!phy) return -ENOMEM; + phy->of_data = + (struct tegra_p2u_of_data *)of_device_get_match_data(dev); + if (!phy->of_data) + return -EINVAL; + phy->base = devm_platform_ioremap_resource_byname(pdev, "ctl"); if (IS_ERR(phy->base)) return PTR_ERR(phy->base); + phy->skip_sz_protection_en = + of_property_read_bool(dev->of_node, + "nvidia,skip-sz-protect-en"); + platform_set_drvdata(pdev, phy); generic_phy = devm_phy_create(dev, NULL, &ops); @@ -96,9 +129,22 @@ static int tegra_p2u_probe(struct platform_device *pdev) return 0; } +static const struct tegra_p2u_of_data tegra194_p2u_of_data = { + .one_dir_search = false, +}; + +static const struct tegra_p2u_of_data tegra234_p2u_of_data = { + .one_dir_search = true, +}; + static const struct of_device_id tegra_p2u_id_table[] = { { .compatible = "nvidia,tegra194-p2u", + .data = &tegra194_p2u_of_data, + }, + { + .compatible = "nvidia,tegra234-p2u", + .data = &tegra234_p2u_of_data, }, {} }; diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index da546c35d1d5..70bac931f99a 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -253,6 +253,14 @@ enum wiz_type { AM64_WIZ_10G, }; +struct wiz_data { + enum wiz_type type; + const struct reg_field *refclk_dig_sel; + const struct reg_field *pma_cmn_refclk1_dig_div; + const struct wiz_clk_mux_sel *clk_mux_sel; + unsigned int clk_div_sel_num; +}; + #define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */ #define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000 @@ -290,6 +298,7 @@ struct wiz { struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS]; struct clk *output_clks[WIZ_MAX_OUTPUT_CLOCKS]; struct clk_onecell_data clk_data; + const struct wiz_data *data; }; static int wiz_reset(struct wiz *wiz) @@ -409,6 +418,7 @@ static int wiz_regfield_init(struct wiz *wiz) struct regmap *regmap = wiz->regmap; int num_lanes = wiz->num_lanes; struct device *dev = wiz->dev; + const struct wiz_data *data = wiz->data; int i; wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en); @@ -445,10 +455,10 @@ static int wiz_regfield_init(struct wiz *wiz) return PTR_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV]); } - if (wiz->type == J721E_WIZ_16G) { + if (data->pma_cmn_refclk1_dig_div) { wiz->div_sel_field[CMN_REFCLK1_DIG_DIV] = devm_regmap_field_alloc(dev, regmap, - pma_cmn_refclk1_dig_div); + *data->pma_cmn_refclk1_dig_div); if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV])) { dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n"); return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV]); @@ -469,15 +479,8 @@ static int wiz_regfield_init(struct wiz *wiz) return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]); } - if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G) - wiz->mux_sel_field[REFCLK_DIG] = - devm_regmap_field_alloc(dev, regmap, - refclk_dig_sel_10g); - else - wiz->mux_sel_field[REFCLK_DIG] = - devm_regmap_field_alloc(dev, regmap, - refclk_dig_sel_16g); - + wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, regmap, + *data->refclk_dig_sel); if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) { dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n"); return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]); @@ -1078,15 +1081,37 @@ static const struct regmap_config wiz_regmap_config = { .fast_io = true, }; +static struct wiz_data j721e_16g_data = { + .type = J721E_WIZ_16G, + .refclk_dig_sel = &refclk_dig_sel_16g, + .pma_cmn_refclk1_dig_div = &pma_cmn_refclk1_dig_div, + .clk_mux_sel = clk_mux_sel_16g, + .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G, +}; + +static struct wiz_data j721e_10g_data = { + .type = J721E_WIZ_10G, + .refclk_dig_sel = &refclk_dig_sel_10g, + .clk_mux_sel = clk_mux_sel_10g, + .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, +}; + +static struct wiz_data am64_10g_data = { + .type = AM64_WIZ_10G, + .refclk_dig_sel = &refclk_dig_sel_10g, + .clk_mux_sel = clk_mux_sel_10g, + .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, +}; + static const struct of_device_id wiz_id_table[] = { { - .compatible = "ti,j721e-wiz-16g", .data = (void *)J721E_WIZ_16G + .compatible = "ti,j721e-wiz-16g", .data = &j721e_16g_data, }, { - .compatible = "ti,j721e-wiz-10g", .data = (void *)J721E_WIZ_10G + .compatible = "ti,j721e-wiz-10g", .data = &j721e_10g_data, }, { - .compatible = "ti,am64-wiz-10g", .data = (void *)AM64_WIZ_10G + .compatible = "ti,am64-wiz-10g", .data = &am64_10g_data, }, {} }; @@ -1145,12 +1170,20 @@ static int wiz_probe(struct platform_device *pdev) struct wiz *wiz; int ret, val, i; u32 num_lanes; + const struct wiz_data *data; wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL); if (!wiz) return -ENOMEM; - wiz->type = (enum wiz_type)of_device_get_match_data(dev); + data = of_device_get_match_data(dev); + if (!data) { + dev_err(dev, "NULL device data\n"); + return -EINVAL; + } + + wiz->data = data; + wiz->type = data->type; child_node = of_get_child_by_name(node, "serdes"); if (!child_node) { @@ -1226,17 +1259,9 @@ static int wiz_probe(struct platform_device *pdev) wiz->dev = dev; wiz->regmap = regmap; wiz->num_lanes = num_lanes; - if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G) - wiz->clk_mux_sel = clk_mux_sel_10g; - else - wiz->clk_mux_sel = clk_mux_sel_16g; - + wiz->clk_mux_sel = data->clk_mux_sel; wiz->clk_div_sel = clk_div_sel; - - if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G) - wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G; - else - wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G; + wiz->clk_div_sel_num = data->clk_div_sel_num; platform_set_drvdata(pdev, wiz); diff --git a/drivers/phy/ti/phy-tusb1210.c b/drivers/phy/ti/phy-tusb1210.c index c3ab4b69ea68..669c13d6e402 100644 --- a/drivers/phy/ti/phy-tusb1210.c +++ b/drivers/phy/ti/phy-tusb1210.c @@ -105,8 +105,9 @@ static int tusb1210_power_on(struct phy *phy) msleep(TUSB1210_RESET_TIME_MS); /* Restore the optional eye diagram optimization value */ - return tusb1210_ulpi_write(tusb, TUSB1210_VENDOR_SPECIFIC2, - tusb->vendor_specific2); + tusb1210_ulpi_write(tusb, TUSB1210_VENDOR_SPECIFIC2, tusb->vendor_specific2); + + return 0; } static int tusb1210_power_off(struct phy *phy) diff --git a/drivers/slimbus/core.c b/drivers/slimbus/core.c index 78480e332ab8..219483b79c09 100644 --- a/drivers/slimbus/core.c +++ b/drivers/slimbus/core.c @@ -250,7 +250,7 @@ int slim_register_controller(struct slim_controller *ctrl) { int id; - id = ida_simple_get(&ctrl_ida, 0, 0, GFP_KERNEL); + id = ida_alloc(&ctrl_ida, GFP_KERNEL); if (id < 0) return id; @@ -299,7 +299,7 @@ int slim_unregister_controller(struct slim_controller *ctrl) { /* Remove all clients */ device_for_each_child(ctrl->dev, NULL, slim_ctrl_remove_device); - ida_simple_remove(&ctrl_ida, ctrl->id); + ida_free(&ctrl_ida, ctrl->id); return 0; } @@ -323,7 +323,7 @@ void slim_report_absent(struct slim_device *sbdev) sbdev->is_laddr_valid = false; mutex_unlock(&ctrl->lock); if (!ctrl->get_laddr) - ida_simple_remove(&ctrl->laddr_ida, sbdev->laddr); + ida_free(&ctrl->laddr_ida, sbdev->laddr); slim_device_update_status(sbdev, SLIM_DEVICE_STATUS_DOWN); } EXPORT_SYMBOL_GPL(slim_report_absent); diff --git a/drivers/slimbus/messaging.c b/drivers/slimbus/messaging.c index e5ae26227bdb..4ce0cb61e481 100644 --- a/drivers/slimbus/messaging.c +++ b/drivers/slimbus/messaging.c @@ -79,7 +79,7 @@ int slim_alloc_txn_tid(struct slim_controller *ctrl, struct slim_msg_txn *txn) EXPORT_SYMBOL_GPL(slim_alloc_txn_tid); /** - * slim_free_txn_tid() - Freee tid of txn + * slim_free_txn_tid() - Free tid of txn * * @ctrl: Controller handle * @txn: transaction whose tid should be freed @@ -101,7 +101,7 @@ EXPORT_SYMBOL_GPL(slim_free_txn_tid); * @txn: Transaction to be sent over SLIMbus * * Called by controller to transmit messaging transactions not dealing with - * Interface/Value elements. (e.g. transmittting a message to assign logical + * Interface/Value elements. (e.g. transmitting a message to assign logical * address to a slave device * * Return: -ETIMEDOUT: If transmission of this message timed out diff --git a/drivers/soundwire/bus.c b/drivers/soundwire/bus.c index a2bfb0434a67..8d4000664fa3 100644 --- a/drivers/soundwire/bus.c +++ b/drivers/soundwire/bus.c @@ -7,6 +7,7 @@ #include #include #include +#include #include "bus.h" #include "sysfs_local.h" @@ -842,15 +843,21 @@ static int sdw_slave_clk_stop_callback(struct sdw_slave *slave, enum sdw_clk_stop_mode mode, enum sdw_clk_stop_type type) { - int ret; + int ret = 0; - if (slave->ops && slave->ops->clk_stop) { - ret = slave->ops->clk_stop(slave, mode, type); - if (ret < 0) - return ret; + mutex_lock(&slave->sdw_dev_lock); + + if (slave->probed) { + struct device *dev = &slave->dev; + struct sdw_driver *drv = drv_to_sdw_driver(dev->driver); + + if (drv->ops && drv->ops->clk_stop) + ret = drv->ops->clk_stop(slave, mode, type); } - return 0; + mutex_unlock(&slave->sdw_dev_lock); + + return ret; } static int sdw_slave_clk_stop_prepare(struct sdw_slave *slave, @@ -1611,14 +1618,24 @@ static int sdw_handle_slave_alerts(struct sdw_slave *slave) } /* Update the Slave driver */ - if (slave_notify && slave->ops && - slave->ops->interrupt_callback) { - slave_intr.sdca_cascade = sdca_cascade; - slave_intr.control_port = clear; - memcpy(slave_intr.port, &port_status, - sizeof(slave_intr.port)); + if (slave_notify) { + mutex_lock(&slave->sdw_dev_lock); - slave->ops->interrupt_callback(slave, &slave_intr); + if (slave->probed) { + struct device *dev = &slave->dev; + struct sdw_driver *drv = drv_to_sdw_driver(dev->driver); + + if (drv->ops && drv->ops->interrupt_callback) { + slave_intr.sdca_cascade = sdca_cascade; + slave_intr.control_port = clear; + memcpy(slave_intr.port, &port_status, + sizeof(slave_intr.port)); + + drv->ops->interrupt_callback(slave, &slave_intr); + } + } + + mutex_unlock(&slave->sdw_dev_lock); } /* Ack interrupt */ @@ -1692,29 +1709,21 @@ io_err: static int sdw_update_slave_status(struct sdw_slave *slave, enum sdw_slave_status status) { - unsigned long time; + int ret = 0; - if (!slave->probed) { - /* - * the slave status update is typically handled in an - * interrupt thread, which can race with the driver - * probe, e.g. when a module needs to be loaded. - * - * make sure the probe is complete before updating - * status. - */ - time = wait_for_completion_timeout(&slave->probe_complete, - msecs_to_jiffies(DEFAULT_PROBE_TIMEOUT)); - if (!time) { - dev_err(&slave->dev, "Probe not complete, timed out\n"); - return -ETIMEDOUT; - } + mutex_lock(&slave->sdw_dev_lock); + + if (slave->probed) { + struct device *dev = &slave->dev; + struct sdw_driver *drv = drv_to_sdw_driver(dev->driver); + + if (drv->ops && drv->ops->update_status) + ret = drv->ops->update_status(slave, status); } - if (!slave->ops || !slave->ops->update_status) - return 0; + mutex_unlock(&slave->sdw_dev_lock); - return slave->ops->update_status(slave, status); + return ret; } /** diff --git a/drivers/soundwire/bus_type.c b/drivers/soundwire/bus_type.c index 893296f3fe39..04b3529f8929 100644 --- a/drivers/soundwire/bus_type.c +++ b/drivers/soundwire/bus_type.c @@ -98,8 +98,6 @@ static int sdw_drv_probe(struct device *dev) if (!id) return -ENODEV; - slave->ops = drv->ops; - /* * attach to power domain but don't turn on (last arg) */ @@ -107,19 +105,23 @@ static int sdw_drv_probe(struct device *dev) if (ret) return ret; + mutex_lock(&slave->sdw_dev_lock); + ret = drv->probe(slave, id); if (ret) { name = drv->name; if (!name) name = drv->driver.name; + mutex_unlock(&slave->sdw_dev_lock); + dev_err(dev, "Probe of %s failed: %d\n", name, ret); dev_pm_domain_detach(dev, false); return ret; } /* device is probed so let's read the properties now */ - if (slave->ops && slave->ops->read_prop) - slave->ops->read_prop(slave); + if (drv->ops && drv->ops->read_prop) + drv->ops->read_prop(slave); /* init the sysfs as we have properties now */ ret = sdw_slave_sysfs_init(slave); @@ -139,7 +141,19 @@ static int sdw_drv_probe(struct device *dev) slave->prop.clk_stop_timeout); slave->probed = true; - complete(&slave->probe_complete); + + /* + * if the probe happened after the bus was started, notify the codec driver + * of the current hardware status to e.g. start the initialization. + * Errors are only logged as warnings to avoid failing the probe. + */ + if (drv->ops && drv->ops->update_status) { + ret = drv->ops->update_status(slave, slave->status); + if (ret < 0) + dev_warn(dev, "%s: update_status failed with status %d\n", __func__, ret); + } + + mutex_unlock(&slave->sdw_dev_lock); dev_dbg(dev, "probe complete\n"); @@ -152,9 +166,15 @@ static int sdw_drv_remove(struct device *dev) struct sdw_driver *drv = drv_to_sdw_driver(dev->driver); int ret = 0; + mutex_lock(&slave->sdw_dev_lock); + + slave->probed = false; + if (drv->remove) ret = drv->remove(slave); + mutex_unlock(&slave->sdw_dev_lock); + dev_pm_domain_detach(dev, false); return ret; @@ -193,12 +213,8 @@ int __sdw_register_driver(struct sdw_driver *drv, struct module *owner) drv->driver.owner = owner; drv->driver.probe = sdw_drv_probe; - - if (drv->remove) - drv->driver.remove = sdw_drv_remove; - - if (drv->shutdown) - drv->driver.shutdown = sdw_drv_shutdown; + drv->driver.remove = sdw_drv_remove; + drv->driver.shutdown = sdw_drv_shutdown; return driver_register(&drv->driver); } diff --git a/drivers/soundwire/intel.c b/drivers/soundwire/intel.c index 505c5ef061e3..95ce292994cc 100644 --- a/drivers/soundwire/intel.c +++ b/drivers/soundwire/intel.c @@ -1043,6 +1043,23 @@ static int intel_trigger(struct snd_pcm_substream *substream, int cmd, struct sn return ret; } +static int intel_component_probe(struct snd_soc_component *component) +{ + int ret; + + /* + * make sure the device is pm_runtime_active before initiating + * bus transactions during the card registration. + * We use pm_runtime_resume() here, without taking a reference + * and releasing it immediately. + */ + ret = pm_runtime_resume(component->dev); + if (ret < 0 && ret != -EACCES) + return ret; + + return 0; +} + static int intel_component_dais_suspend(struct snd_soc_component *component) { struct snd_soc_dai *dai; @@ -1098,6 +1115,7 @@ static const struct snd_soc_dai_ops intel_pcm_dai_ops = { static const struct snd_soc_component_driver dai_component = { .name = "soundwire", + .probe = intel_component_probe, .suspend = intel_component_dais_suspend }; diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index 22b706350ead..9df970eeca45 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -142,6 +143,7 @@ struct qcom_swrm_ctrl { struct device *dev; struct regmap *regmap; void __iomem *mmio; + struct reset_control *audio_cgcr; #ifdef CONFIG_DEBUG_FS struct dentry *debugfs; #endif @@ -179,6 +181,7 @@ struct qcom_swrm_ctrl { struct qcom_swrm_data { u32 default_cols; u32 default_rows; + bool sw_clk_gate_required; }; static const struct qcom_swrm_data swrm_v1_3_data = { @@ -191,6 +194,12 @@ static const struct qcom_swrm_data swrm_v1_5_data = { .default_cols = 16, }; +static const struct qcom_swrm_data swrm_v1_6_data = { + .default_rows = 50, + .default_cols = 16, + .sw_clk_gate_required = true, +}; + #define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus) static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, @@ -471,6 +480,10 @@ static int qcom_swrm_enumerate(struct sdw_bus *bus) char *buf1 = (char *)&val1, *buf2 = (char *)&val2; for (i = 1; i <= SDW_MAX_DEVICES; i++) { + /* do not continue if the status is Not Present */ + if (!ctrl->status[i]) + continue; + /*SCP_Devid5 - Devid 4*/ ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1); @@ -656,6 +669,8 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index); val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index); + reset_control_reset(ctrl->audio_cgcr); + ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); /* Enable Auto enumeration */ @@ -1307,6 +1322,15 @@ static int qcom_swrm_probe(struct platform_device *pdev) return PTR_ERR(ctrl->mmio); } + if (data->sw_clk_gate_required) { + ctrl->audio_cgcr = devm_reset_control_get_exclusive(dev, "swr_audio_cgcr"); + if (IS_ERR_OR_NULL(ctrl->audio_cgcr)) { + dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n"); + ret = PTR_ERR(ctrl->audio_cgcr); + goto err_init; + } + } + ctrl->irq = of_irq_get(dev->of_node, 0); if (ctrl->irq < 0) { ret = ctrl->irq; @@ -1332,6 +1356,10 @@ static int qcom_swrm_probe(struct platform_device *pdev) ctrl->bus.compute_params = &qcom_swrm_compute_params; ctrl->bus.clk_stop_timeout = 300; + ctrl->audio_cgcr = devm_reset_control_get_exclusive(dev, "swr_audio_cgcr"); + if (IS_ERR(ctrl->audio_cgcr)) + dev_err(dev, "Failed to get audio_cgcr reset required for soundwire-v1.6.0\n"); + ret = qcom_swrm_get_port_config(ctrl); if (ret) goto err_clk; @@ -1485,6 +1513,8 @@ static int __maybe_unused swrm_runtime_resume(struct device *dev) qcom_swrm_get_device_status(ctrl); sdw_handle_slave_status(&ctrl->bus, ctrl->status); } else { + reset_control_reset(ctrl->audio_cgcr); + ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET); @@ -1548,7 +1578,7 @@ static const struct dev_pm_ops swrm_dev_pm_ops = { static const struct of_device_id qcom_swrm_of_match[] = { { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data }, { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data }, - { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_5_data }, + { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data }, {/* sentinel */}, }; diff --git a/drivers/soundwire/slave.c b/drivers/soundwire/slave.c index 00f7b490a95d..c1c1a2ac293a 100644 --- a/drivers/soundwire/slave.c +++ b/drivers/soundwire/slave.c @@ -12,6 +12,7 @@ static void sdw_slave_release(struct device *dev) { struct sdw_slave *slave = dev_to_sdw_dev(dev); + mutex_destroy(&slave->sdw_dev_lock); kfree(slave); } @@ -58,9 +59,9 @@ int sdw_slave_add(struct sdw_bus *bus, init_completion(&slave->enumeration_complete); init_completion(&slave->initialization_complete); slave->dev_num = 0; - init_completion(&slave->probe_complete); slave->probed = false; slave->first_interrupt_done = false; + mutex_init(&slave->sdw_dev_lock); for (i = 0; i < SDW_MAX_PORTS; i++) init_completion(&slave->port_ready[i]); diff --git a/drivers/soundwire/stream.c b/drivers/soundwire/stream.c index d34150559142..bd502368339e 100644 --- a/drivers/soundwire/stream.c +++ b/drivers/soundwire/stream.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include "bus.h" @@ -401,20 +402,26 @@ static int sdw_do_port_prep(struct sdw_slave_runtime *s_rt, struct sdw_prepare_ch prep_ch, enum sdw_port_prep_ops cmd) { - const struct sdw_slave_ops *ops = s_rt->slave->ops; - int ret; + int ret = 0; + struct sdw_slave *slave = s_rt->slave; - if (ops->port_prep) { - ret = ops->port_prep(s_rt->slave, &prep_ch, cmd); - if (ret < 0) { - dev_err(&s_rt->slave->dev, - "Slave Port Prep cmd %d failed: %d\n", - cmd, ret); - return ret; + mutex_lock(&slave->sdw_dev_lock); + + if (slave->probed) { + struct device *dev = &slave->dev; + struct sdw_driver *drv = drv_to_sdw_driver(dev->driver); + + if (drv->ops && drv->ops->port_prep) { + ret = drv->ops->port_prep(slave, &prep_ch, cmd); + if (ret < 0) + dev_err(dev, "Slave Port Prep cmd %d failed: %d\n", + cmd, ret); } } - return 0; + mutex_unlock(&slave->sdw_dev_lock); + + return ret; } static int sdw_prep_deprep_slave_ports(struct sdw_bus *bus, @@ -578,7 +585,7 @@ static int sdw_notify_config(struct sdw_master_runtime *m_rt) struct sdw_slave_runtime *s_rt; struct sdw_bus *bus = m_rt->bus; struct sdw_slave *slave; - int ret = 0; + int ret; if (bus->ops->set_bus_conf) { ret = bus->ops->set_bus_conf(bus, &bus->params); @@ -589,17 +596,27 @@ static int sdw_notify_config(struct sdw_master_runtime *m_rt) list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { slave = s_rt->slave; - if (slave->ops->bus_config) { - ret = slave->ops->bus_config(slave, &bus->params); - if (ret < 0) { - dev_err(bus->dev, "Notify Slave: %d failed\n", - slave->dev_num); - return ret; + mutex_lock(&slave->sdw_dev_lock); + + if (slave->probed) { + struct device *dev = &slave->dev; + struct sdw_driver *drv = drv_to_sdw_driver(dev->driver); + + if (drv->ops && drv->ops->bus_config) { + ret = drv->ops->bus_config(slave, &bus->params); + if (ret < 0) { + dev_err(dev, "Notify Slave: %d failed\n", + slave->dev_num); + mutex_unlock(&slave->sdw_dev_lock); + return ret; + } } } + + mutex_unlock(&slave->sdw_dev_lock); } - return ret; + return 0; } /** diff --git a/drivers/spmi/spmi.c b/drivers/spmi/spmi.c index b37ead9e2fad..a456ce5141e1 100644 --- a/drivers/spmi/spmi.c +++ b/drivers/spmi/spmi.c @@ -386,6 +386,23 @@ static struct bus_type spmi_bus_type = { .uevent = spmi_drv_uevent, }; +/** + * spmi_device_from_of() - get the associated SPMI device from a device node + * + * @np: device node + * + * Returns the struct spmi_device associated with a device node or NULL. + */ +struct spmi_device *spmi_device_from_of(struct device_node *np) +{ + struct device *dev = bus_find_device_by_of_node(&spmi_bus_type, np); + + if (dev) + return to_spmi_device(dev); + return NULL; +} +EXPORT_SYMBOL_GPL(spmi_device_from_of); + /** * spmi_controller_alloc() - Allocate a new SPMI device * @ctrl: associated controller diff --git a/drivers/virt/acrn/ioreq.c b/drivers/virt/acrn/ioreq.c index 5ff1c53740c0..d75ab3f66da4 100644 --- a/drivers/virt/acrn/ioreq.c +++ b/drivers/virt/acrn/ioreq.c @@ -246,12 +246,8 @@ void acrn_ioreq_request_clear(struct acrn_vm *vm) spin_lock_bh(&vm->ioreq_clients_lock); client = vm->default_client; if (client) { - vcpu = find_first_bit(client->ioreqs_map, ACRN_IO_REQUEST_MAX); - while (vcpu < ACRN_IO_REQUEST_MAX) { + for_each_set_bit(vcpu, client->ioreqs_map, ACRN_IO_REQUEST_MAX) acrn_ioreq_complete_request(client, vcpu, NULL); - vcpu = find_next_bit(client->ioreqs_map, - ACRN_IO_REQUEST_MAX, vcpu + 1); - } } spin_unlock_bh(&vm->ioreq_clients_lock); diff --git a/drivers/virt/vboxguest/vboxguest_linux.c b/drivers/virt/vboxguest/vboxguest_linux.c index 73eb34849eab..4ccfd30c2a30 100644 --- a/drivers/virt/vboxguest/vboxguest_linux.c +++ b/drivers/virt/vboxguest/vboxguest_linux.c @@ -356,8 +356,8 @@ static int vbg_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) goto err_vbg_core_exit; } - ret = devm_request_irq(dev, pci->irq, vbg_core_isr, IRQF_SHARED, - DEVICE_NAME, gdev); + ret = request_irq(pci->irq, vbg_core_isr, IRQF_SHARED, DEVICE_NAME, + gdev); if (ret) { vbg_err("vboxguest: Error requesting irq: %d\n", ret); goto err_vbg_core_exit; @@ -367,7 +367,7 @@ static int vbg_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) if (ret) { vbg_err("vboxguest: Error misc_register %s failed: %d\n", DEVICE_NAME, ret); - goto err_vbg_core_exit; + goto err_free_irq; } ret = misc_register(&gdev->misc_device_user); @@ -403,6 +403,8 @@ err_unregister_misc_device_user: misc_deregister(&gdev->misc_device_user); err_unregister_misc_device: misc_deregister(&gdev->misc_device); +err_free_irq: + free_irq(pci->irq, gdev); err_vbg_core_exit: vbg_core_exit(gdev); err_disable_pcidev: @@ -419,6 +421,7 @@ static void vbg_pci_remove(struct pci_dev *pci) vbg_gdev = NULL; mutex_unlock(&vbg_gdev_mutex); + free_irq(pci->irq, gdev); device_remove_file(gdev->dev, &dev_attr_host_features); device_remove_file(gdev->dev, &dev_attr_host_version); misc_deregister(&gdev->misc_device_user); diff --git a/include/dt-bindings/interconnect/fsl,imx8mp.h b/include/dt-bindings/interconnect/fsl,imx8mp.h new file mode 100644 index 000000000000..7357d417529a --- /dev/null +++ b/include/dt-bindings/interconnect/fsl,imx8mp.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright 2022 NXP + * Peng Fan + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MP_H +#define __DT_BINDINGS_INTERCONNECT_IMX8MP_H + +#define IMX8MP_ICN_NOC 0 +#define IMX8MP_ICN_MAIN 1 +#define IMX8MP_ICS_DRAM 2 +#define IMX8MP_ICS_OCRAM 3 +#define IMX8MP_ICM_A53 4 +#define IMX8MP_ICM_SUPERMIX 5 +#define IMX8MP_ICM_GIC 6 +#define IMX8MP_ICM_MLMIX 7 + +#define IMX8MP_ICN_AUDIO 8 +#define IMX8MP_ICM_DSP 9 +#define IMX8MP_ICM_SDMA2PER 10 +#define IMX8MP_ICM_SDMA2BURST 11 +#define IMX8MP_ICM_SDMA3PER 12 +#define IMX8MP_ICM_SDMA3BURST 13 +#define IMX8MP_ICM_EDMA 14 + +#define IMX8MP_ICN_GPU 15 +#define IMX8MP_ICM_GPU2D 16 +#define IMX8MP_ICM_GPU3D 17 + +#define IMX8MP_ICN_HDMI 18 +#define IMX8MP_ICM_HRV 19 +#define IMX8MP_ICM_LCDIF_HDMI 20 +#define IMX8MP_ICM_HDCP 21 + +#define IMX8MP_ICN_HSIO 22 +#define IMX8MP_ICM_NOC_PCIE 23 +#define IMX8MP_ICM_USB1 24 +#define IMX8MP_ICM_USB2 25 +#define IMX8MP_ICM_PCIE 26 + +#define IMX8MP_ICN_MEDIA 27 +#define IMX8MP_ICM_LCDIF_RD 28 +#define IMX8MP_ICM_LCDIF_WR 29 +#define IMX8MP_ICM_ISI0 30 +#define IMX8MP_ICM_ISI1 31 +#define IMX8MP_ICM_ISI2 32 +#define IMX8MP_ICM_ISP0 33 +#define IMX8MP_ICM_ISP1 34 +#define IMX8MP_ICM_DWE 35 + +#define IMX8MP_ICN_VIDEO 36 +#define IMX8MP_ICM_VPU_G1 37 +#define IMX8MP_ICM_VPU_G2 38 +#define IMX8MP_ICM_VPU_H1 39 + +#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MP_H */ diff --git a/include/dt-bindings/interconnect/qcom,sm6350.h b/include/dt-bindings/interconnect/qcom,sm6350.h new file mode 100644 index 000000000000..e662cede9aaa --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sm6350.h @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Qualcomm SM6350 interconnect IDs + * + * Copyright (C) 2022 Luca Weiss + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM6350_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SM6350_H + +#define MASTER_A1NOC_CFG 0 +#define MASTER_QUP_0 1 +#define MASTER_EMMC 2 +#define MASTER_UFS_MEM 3 +#define A1NOC_SNOC_SLV 4 +#define SLAVE_SERVICE_A1NOC 5 + +#define MASTER_A2NOC_CFG 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_QUP_1 2 +#define MASTER_CRYPTO_CORE_0 3 +#define MASTER_IPA 4 +#define MASTER_QDSS_ETR 5 +#define MASTER_SDCC_2 6 +#define MASTER_USB3 7 +#define A2NOC_SNOC_SLV 8 +#define SLAVE_SERVICE_A2NOC 9 + +#define MASTER_CAMNOC_HF0_UNCOMP 0 +#define MASTER_CAMNOC_ICP_UNCOMP 1 +#define MASTER_CAMNOC_SF_UNCOMP 2 +#define MASTER_QUP_CORE_0 3 +#define MASTER_QUP_CORE_1 4 +#define MASTER_LLCC 5 +#define SLAVE_CAMNOC_UNCOMP 6 +#define SLAVE_QUP_CORE_0 7 +#define SLAVE_QUP_CORE_1 8 +#define SLAVE_EBI_CH0 9 + +#define MASTER_NPU 0 +#define MASTER_NPU_PROC 1 +#define SLAVE_CDSP_GEM_NOC 2 + +#define SNOC_CNOC_MAS 0 +#define MASTER_QDSS_DAP 1 +#define SLAVE_A1NOC_CFG 2 +#define SLAVE_A2NOC_CFG 3 +#define SLAVE_AHB2PHY 4 +#define SLAVE_AHB2PHY_2 5 +#define SLAVE_AOSS 6 +#define SLAVE_BOOT_ROM 7 +#define SLAVE_CAMERA_CFG 8 +#define SLAVE_CAMERA_NRT_THROTTLE_CFG 9 +#define SLAVE_CAMERA_RT_THROTTLE_CFG 10 +#define SLAVE_CLK_CTL 11 +#define SLAVE_RBCPR_CX_CFG 12 +#define SLAVE_RBCPR_MX_CFG 13 +#define SLAVE_CRYPTO_0_CFG 14 +#define SLAVE_DCC_CFG 15 +#define SLAVE_CNOC_DDRSS 16 +#define SLAVE_DISPLAY_CFG 17 +#define SLAVE_DISPLAY_THROTTLE_CFG 18 +#define SLAVE_EMMC_CFG 19 +#define SLAVE_GLM 20 +#define SLAVE_GRAPHICS_3D_CFG 21 +#define SLAVE_IMEM_CFG 22 +#define SLAVE_IPA_CFG 23 +#define SLAVE_CNOC_MNOC_CFG 24 +#define SLAVE_CNOC_MSS 25 +#define SLAVE_NPU_CFG 26 +#define SLAVE_PDM 27 +#define SLAVE_PIMEM_CFG 28 +#define SLAVE_PRNG 29 +#define SLAVE_QDSS_CFG 30 +#define SLAVE_QM_CFG 31 +#define SLAVE_QM_MPU_CFG 32 +#define SLAVE_QUP_0 33 +#define SLAVE_QUP_1 34 +#define SLAVE_SDCC_2 35 +#define SLAVE_SECURITY 36 +#define SLAVE_SNOC_CFG 37 +#define SLAVE_TCSR 38 +#define SLAVE_UFS_MEM_CFG 39 +#define SLAVE_USB3 40 +#define SLAVE_VENUS_CFG 41 +#define SLAVE_VENUS_THROTTLE_CFG 42 +#define SLAVE_VSENSE_CTRL_CFG 43 +#define SLAVE_SERVICE_CNOC 44 + +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_GEM_NOC_CFG 1 +#define SLAVE_LLCC_CFG 2 + +#define MASTER_AMPSS_M0 0 +#define MASTER_SYS_TCU 1 +#define MASTER_GEM_NOC_CFG 2 +#define MASTER_COMPUTE_NOC 3 +#define MASTER_MNOC_HF_MEM_NOC 4 +#define MASTER_MNOC_SF_MEM_NOC 5 +#define MASTER_SNOC_GC_MEM_NOC 6 +#define MASTER_SNOC_SF_MEM_NOC 7 +#define MASTER_GRAPHICS_3D 8 +#define SLAVE_MCDMA_MS_MPU_CFG 9 +#define SLAVE_MSS_PROC_MS_MPU_CFG 10 +#define SLAVE_GEM_NOC_SNOC 11 +#define SLAVE_LLCC 12 +#define SLAVE_SERVICE_GEM_NOC 13 + +#define MASTER_CNOC_MNOC_CFG 0 +#define MASTER_VIDEO_P0 1 +#define MASTER_VIDEO_PROC 2 +#define MASTER_CAMNOC_HF 3 +#define MASTER_CAMNOC_ICP 4 +#define MASTER_CAMNOC_SF 5 +#define MASTER_MDP_PORT0 6 +#define SLAVE_MNOC_HF_MEM_NOC 7 +#define SLAVE_MNOC_SF_MEM_NOC 8 +#define SLAVE_SERVICE_MNOC 9 + +#define MASTER_NPU_SYS 0 +#define MASTER_NPU_NOC_CFG 1 +#define SLAVE_NPU_CAL_DP0 2 +#define SLAVE_NPU_CP 3 +#define SLAVE_NPU_INT_DMA_BWMON_CFG 4 +#define SLAVE_NPU_DPM 5 +#define SLAVE_ISENSE_CFG 6 +#define SLAVE_NPU_LLM_CFG 7 +#define SLAVE_NPU_TCM 8 +#define SLAVE_NPU_COMPUTE_NOC 9 +#define SLAVE_SERVICE_NPU_NOC 10 + +#define MASTER_SNOC_CFG 0 +#define A1NOC_SNOC_MAS 1 +#define A2NOC_SNOC_MAS 2 +#define MASTER_GEM_NOC_SNOC 3 +#define MASTER_PIMEM 4 +#define MASTER_GIC 5 +#define SLAVE_APPSS 6 +#define SNOC_CNOC_SLV 7 +#define SLAVE_SNOC_GEM_NOC_GC 8 +#define SLAVE_SNOC_GEM_NOC_SF 9 +#define SLAVE_OCIMEM 10 +#define SLAVE_PIMEM 11 +#define SLAVE_SERVICE_SNOC 12 +#define SLAVE_QDSS_STM 13 +#define SLAVE_TCU 14 + +#endif diff --git a/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h b/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h new file mode 100644 index 000000000000..f570b23165a2 --- /dev/null +++ b/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ + +#ifndef _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H +#define _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H + +/* + * Need to have it as a multiple of 4 as NVMEM memory is registered with + * stride = 4. + */ +#define OTP_PKT(id) ((id) * 4) + +#endif diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index 4ac5c081af93..6c2fd6cc5a98 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -18,6 +18,7 @@ * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and * directly use below macros as config bits. */ +#define ETM_OPT_BRANCH_BROADCAST 8 #define ETM_OPT_CYCACC 12 #define ETM_OPT_CTXTID 14 #define ETM_OPT_CTXTID2 15 @@ -25,6 +26,7 @@ #define ETM_OPT_RETSTK 29 /* ETMv4 CONFIGR programming bits for the ETM OPTs */ +#define ETM4_CFG_BIT_BB 3 #define ETM4_CFG_BIT_CYCACC 4 #define ETM4_CFG_BIT_CTXTID 6 #define ETM4_CFG_BIT_VMID 7 diff --git a/include/linux/extcon.h b/include/linux/extcon.h index 685401d94d39..3c45c3846fe9 100644 --- a/include/linux/extcon.h +++ b/include/linux/extcon.h @@ -76,6 +76,8 @@ #define EXTCON_DISP_VGA 43 /* Video Graphics Array */ #define EXTCON_DISP_DP 44 /* Display Port */ #define EXTCON_DISP_HMD 45 /* Head-Mounted Display */ +#define EXTCON_DISP_CVBS 46 /* Composite Video Broadcast Signal */ +#define EXTCON_DISP_EDP 47 /* Embedded Display Port */ /* Miscellaneous external connector */ #define EXTCON_DOCK 60 diff --git a/include/linux/firmware/intel/stratix10-smc.h b/include/linux/firmware/intel/stratix10-smc.h index aad497a9ad8b..a718f853d457 100644 --- a/include/linux/firmware/intel/stratix10-smc.h +++ b/include/linux/firmware/intel/stratix10-smc.h @@ -403,6 +403,52 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) #define INTEL_SIP_SMC_RSU_MAX_RETRY \ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_MAX_RETRY) +/** + * Request INTEL_SIP_SMC_RSU_DCMF_STATUS + * + * Sync call used by service driver at EL1 to query DCMF status from FW + * + * Call register usage: + * a0 INTEL_SIP_SMC_RSU_DCMF_STATUS + * a1-7 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK + * a1 dcmf3 | dcmf2 | dcmf1 | dcmf0 + * + * Or + * + * a0 INTEL_SIP_SMC_RSU_ERROR + */ +#define INTEL_SIP_SMC_FUNCID_RSU_DCMF_STATUS 20 +#define INTEL_SIP_SMC_RSU_DCMF_STATUS \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_DCMF_STATUS) + +/** + * Request INTEL_SIP_SMC_SERVICE_COMPLETED + * Sync call to check if the secure world have completed service request + * or not. + * + * Call register usage: + * a0: INTEL_SIP_SMC_SERVICE_COMPLETED + * a1: this register is optional. If used, it is the physical address for + * secure firmware to put output data + * a2: this register is optional. If used, it is the size of output data + * a3-a7: not used + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_ERROR, + * INTEL_SIP_SMC_REJECTED or INTEL_SIP_SMC_STATUS_BUSY + * a1: mailbox error if a0 is INTEL_SIP_SMC_STATUS_ERROR + * a2: physical address containing the process info + * for FCS certificate -- the data contains the certificate status + * for FCS cryption -- the data contains the actual data size FW processes + * a3: output data size + */ +#define INTEL_SIP_SMC_FUNCID_SERVICE_COMPLETED 30 +#define INTEL_SIP_SMC_SERVICE_COMPLETED \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_SERVICE_COMPLETED) + /** * Request INTEL_SIP_SMC_FIRMWARE_VERSION * @@ -420,4 +466,133 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) #define INTEL_SIP_SMC_FIRMWARE_VERSION \ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FIRMWARE_VERSION) +/** + * Request INTEL_SIP_SMC_SVC_VERSION + * + * Sync call used to query the SIP SMC API Version + * + * Call register usage: + * a0 INTEL_SIP_SMC_SVC_VERSION + * a1-a7 not used + * + * Return status: + * a0 INTEL_SIP_SMC_STATUS_OK + * a1 Major + * a2 Minor + */ +#define INTEL_SIP_SMC_SVC_FUNCID_VERSION 512 +#define INTEL_SIP_SMC_SVC_VERSION \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_SVC_FUNCID_VERSION) + +/** + * SMC call protocol for FPGA Crypto Service (FCS) + * FUNCID starts from 90 + */ + +/** + * Request INTEL_SIP_SMC_FCS_RANDOM_NUMBER + * + * Sync call used to query the random number generated by the firmware + * + * Call register usage: + * a0 INTEL_SIP_SMC_FCS_RANDOM_NUMBER + * a1 the physical address for firmware to write generated random data + * a2-a7 not used + * + * Return status: + * a0 INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FCS_ERROR or + * INTEL_SIP_SMC_FCS_REJECTED + * a1 mailbox error + * a2 the physical address of generated random number + * a3 size + */ +#define INTEL_SIP_SMC_FUNCID_FCS_RANDOM_NUMBER 90 +#define INTEL_SIP_SMC_FCS_RANDOM_NUMBER \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FCS_RANDOM_NUMBER) + +/** + * Request INTEL_SIP_SMC_FCS_CRYPTION + * Async call for data encryption and HMAC signature generation, or for + * data decryption and HMAC verification. + * + * Call INTEL_SIP_SMC_SERVICE_COMPLETED to get the output encrypted or + * decrypted data + * + * Call register usage: + * a0 INTEL_SIP_SMC_FCS_CRYPTION + * a1 cryption mode (1 for encryption and 0 for decryption) + * a2 physical address which stores to be encrypted or decrypted data + * a3 input data size + * a4 physical address which will hold the encrypted or decrypted output data + * a5 output data size + * a6-a7 not used + * + * Return status: + * a0 INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_ERROR or + * INTEL_SIP_SMC_STATUS_REJECTED + * a1-3 not used + */ +#define INTEL_SIP_SMC_FUNCID_FCS_CRYPTION 91 +#define INTEL_SIP_SMC_FCS_CRYPTION \ + INTEL_SIP_SMC_STD_CALL_VAL(INTEL_SIP_SMC_FUNCID_FCS_CRYPTION) + +/** + * Request INTEL_SIP_SMC_FCS_SERVICE_REQUEST + * Async call for authentication service of HPS software + * + * Call register usage: + * a0 INTEL_SIP_SMC_FCS_SERVICE_REQUEST + * a1 the physical address of data block + * a2 size of data block + * a3-a7 not used + * + * Return status: + * a0 INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_ERROR or + * INTEL_SIP_SMC_REJECTED + * a1-a3 not used + */ +#define INTEL_SIP_SMC_FUNCID_FCS_SERVICE_REQUEST 92 +#define INTEL_SIP_SMC_FCS_SERVICE_REQUEST \ + INTEL_SIP_SMC_STD_CALL_VAL(INTEL_SIP_SMC_FUNCID_FCS_SERVICE_REQUEST) + +/** + * Request INTEL_SIP_SMC_FUNCID_FCS_SEND_CERTIFICATE + * Sync call to send a signed certificate + * + * Call register usage: + * a0 INTEL_SIP_SMC_FCS_SEND_CERTIFICATE + * a1 the physical address of CERTIFICATE block + * a2 size of data block + * a3-a7 not used + * + * Return status: + * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_FCS_REJECTED + * a1-a3 not used + */ +#define INTEL_SIP_SMC_FUNCID_FCS_SEND_CERTIFICATE 93 +#define INTEL_SIP_SMC_FCS_SEND_CERTIFICATE \ + INTEL_SIP_SMC_STD_CALL_VAL(INTEL_SIP_SMC_FUNCID_FCS_SEND_CERTIFICATE) + +/** + * Request INTEL_SIP_SMC_FCS_GET_PROVISION_DATA + * Sync call to dump all the fuses and key hashes + * + * Call register usage: + * a0 INTEL_SIP_SMC_FCS_GET_PROVISION_DATA + * a1 the physical address for firmware to write structure of fuse and + * key hashes + * a2-a7 not used + * + * Return status: + * a0 INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FCS_ERROR or + * INTEL_SIP_SMC_FCS_REJECTED + * a1 mailbox error + * a2 physical address for the structure of fuse and key hashes + * a3 the size of structure + * + */ +#define INTEL_SIP_SMC_FUNCID_FCS_GET_PROVISION_DATA 94 +#define INTEL_SIP_SMC_FCS_GET_PROVISION_DATA \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FCS_GET_PROVISION_DATA) + #endif diff --git a/include/linux/firmware/intel/stratix10-svc-client.h b/include/linux/firmware/intel/stratix10-svc-client.h index 18c1841fdb1f..0c16037fd08d 100644 --- a/include/linux/firmware/intel/stratix10-svc-client.h +++ b/include/linux/firmware/intel/stratix10-svc-client.h @@ -14,6 +14,7 @@ */ #define SVC_CLIENT_FPGA "fpga" #define SVC_CLIENT_RSU "rsu" +#define SVC_CLIENT_FCS "fcs" /* * Status of the sent command, in bit number @@ -49,6 +50,7 @@ #define SVC_STATUS_BUSY 4 #define SVC_STATUS_ERROR 5 #define SVC_STATUS_NO_SUPPORT 6 +#define SVC_STATUS_INVALID_PARAM 7 /* * Flag bit for COMMAND_RECONFIG @@ -66,6 +68,8 @@ #define SVC_RECONFIG_REQUEST_TIMEOUT_MS 300 #define SVC_RECONFIG_BUFFER_TIMEOUT_MS 720 #define SVC_RSU_REQUEST_TIMEOUT_MS 300 +#define SVC_FCS_REQUEST_TIMEOUT_MS 2000 +#define SVC_COMPLETED_TIMEOUT_MS 30000 struct stratix10_svc_chan; @@ -105,34 +109,79 @@ struct stratix10_svc_chan; * @COMMAND_RSU_DCMF_VERSION: query firmware for the DCMF version, return status * is SVC_STATUS_OK or SVC_STATUS_ERROR * + * @COMMAND_POLL_SERVICE_STATUS: poll if the service request is complete, + * return statis is SVC_STATUS_OK, SVC_STATUS_ERROR or SVC_STATUS_BUSY + * * @COMMAND_FIRMWARE_VERSION: query running firmware version, return status * is SVC_STATUS_OK or SVC_STATUS_ERROR + * + * @COMMAND_SMC_SVC_VERSION: Non-mailbox SMC SVC API Version, + * return status is SVC_STATUS_OK + * + * @COMMAND_RSU_DCMF_STATUS: query firmware for the DCMF status + * return status is SVC_STATUS_OK or SVC_STATUS_ERROR + * + * @COMMAND_FCS_REQUEST_SERVICE: request validation of image from firmware, + * return status is SVC_STATUS_OK, SVC_STATUS_INVALID_PARAM + * + * @COMMAND_FCS_SEND_CERTIFICATE: send a certificate, return status is + * SVC_STATUS_OK, SVC_STATUS_INVALID_PARAM, SVC_STATUS_ERROR + * + * @COMMAND_FCS_GET_PROVISION_DATA: read the provisioning data, return status is + * SVC_STATUS_OK, SVC_STATUS_INVALID_PARAM, SVC_STATUS_ERROR + * + * @COMMAND_FCS_DATA_ENCRYPTION: encrypt the data, return status is + * SVC_STATUS_OK, SVC_STATUS_INVALID_PARAM, SVC_STATUS_ERROR + * + * @COMMAND_FCS_DATA_DECRYPTION: decrypt the data, return status is + * SVC_STATUS_OK, SVC_STATUS_INVALID_PARAM, SVC_STATUS_ERROR + * + * @COMMAND_FCS_RANDOM_NUMBER_GEN: generate a random number, return status + * is SVC_STATUS_OK, SVC_STATUS_ERROR */ enum stratix10_svc_command_code { + /* for FPGA */ COMMAND_NOOP = 0, COMMAND_RECONFIG, COMMAND_RECONFIG_DATA_SUBMIT, COMMAND_RECONFIG_DATA_CLAIM, COMMAND_RECONFIG_STATUS, - COMMAND_RSU_STATUS, + /* for RSU */ + COMMAND_RSU_STATUS = 10, COMMAND_RSU_UPDATE, COMMAND_RSU_NOTIFY, COMMAND_RSU_RETRY, COMMAND_RSU_MAX_RETRY, COMMAND_RSU_DCMF_VERSION, + COMMAND_RSU_DCMF_STATUS, COMMAND_FIRMWARE_VERSION, + /* for FCS */ + COMMAND_FCS_REQUEST_SERVICE = 20, + COMMAND_FCS_SEND_CERTIFICATE, + COMMAND_FCS_GET_PROVISION_DATA, + COMMAND_FCS_DATA_ENCRYPTION, + COMMAND_FCS_DATA_DECRYPTION, + COMMAND_FCS_RANDOM_NUMBER_GEN, + /* for general status poll */ + COMMAND_POLL_SERVICE_STATUS = 40, + /* Non-mailbox SMC Call */ + COMMAND_SMC_SVC_VERSION = 200, }; /** * struct stratix10_svc_client_msg - message sent by client to service * @payload: starting address of data need be processed - * @payload_length: data size in bytes + * @payload_length: to be processed data size in bytes + * @payload_output: starting address of processed data + * @payload_length_output: processed data size in bytes * @command: service command * @arg: args to be passed via registers and not physically mapped buffers */ struct stratix10_svc_client_msg { void *payload; size_t payload_length; + void *payload_output; + size_t payload_length_output; enum stratix10_svc_command_code command; u64 arg[3]; }; diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h index 0f9468771bb9..54f63459efd6 100644 --- a/include/linux/fpga/fpga-mgr.h +++ b/include/linux/fpga/fpga-mgr.h @@ -22,6 +22,8 @@ struct sg_table; * @FPGA_MGR_STATE_RESET: FPGA in reset state * @FPGA_MGR_STATE_FIRMWARE_REQ: firmware request in progress * @FPGA_MGR_STATE_FIRMWARE_REQ_ERR: firmware request failed + * @FPGA_MGR_STATE_PARSE_HEADER: parse FPGA image header + * @FPGA_MGR_STATE_PARSE_HEADER_ERR: Error during PARSE_HEADER stage * @FPGA_MGR_STATE_WRITE_INIT: preparing FPGA for programming * @FPGA_MGR_STATE_WRITE_INIT_ERR: Error during WRITE_INIT stage * @FPGA_MGR_STATE_WRITE: writing image to FPGA @@ -41,7 +43,9 @@ enum fpga_mgr_states { FPGA_MGR_STATE_FIRMWARE_REQ, FPGA_MGR_STATE_FIRMWARE_REQ_ERR, - /* write sequence: init, write, complete */ + /* write sequence: parse header, init, write, complete */ + FPGA_MGR_STATE_PARSE_HEADER, + FPGA_MGR_STATE_PARSE_HEADER_ERR, FPGA_MGR_STATE_WRITE_INIT, FPGA_MGR_STATE_WRITE_INIT_ERR, FPGA_MGR_STATE_WRITE, @@ -85,6 +89,9 @@ enum fpga_mgr_states { * @sgt: scatter/gather table containing FPGA image * @buf: contiguous buffer containing FPGA image * @count: size of buf + * @header_size: size of image header. + * @data_size: size of image data to be sent to the device. If not specified, + * whole image will be used. Header may be skipped in either case. * @region_id: id of target region * @dev: device that owns this * @overlay: Device Tree overlay @@ -98,6 +105,8 @@ struct fpga_image_info { struct sg_table *sgt; const char *buf; size_t count; + size_t header_size; + size_t data_size; int region_id; struct device *dev; #ifdef CONFIG_OF @@ -137,9 +146,16 @@ struct fpga_manager_info { /** * struct fpga_manager_ops - ops for low level fpga manager drivers - * @initial_header_size: Maximum number of bytes that should be passed into write_init + * @initial_header_size: minimum number of bytes that should be passed into + * parse_header and write_init. + * @skip_header: bool flag to tell fpga-mgr core whether it should skip + * info->header_size part at the beginning of the image when invoking + * write callback. * @state: returns an enum value of the FPGA's state * @status: returns status of the FPGA, including reconfiguration error code + * @parse_header: parse FPGA image header to set info->header_size and + * info->data_size. In case the input buffer is not large enough, set + * required size to info->header_size and return -EAGAIN. * @write_init: prepare the FPGA to receive configuration data * @write: write count bytes of configuration data to the FPGA * @write_sg: write the scatter list of configuration data to the FPGA @@ -153,8 +169,12 @@ struct fpga_manager_info { */ struct fpga_manager_ops { size_t initial_header_size; + bool skip_header; enum fpga_mgr_states (*state)(struct fpga_manager *mgr); u64 (*status)(struct fpga_manager *mgr); + int (*parse_header)(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t count); int (*write_init)(struct fpga_manager *mgr, struct fpga_image_info *info, const char *buf, size_t count); diff --git a/include/linux/iio/common/cros_ec_sensors_core.h b/include/linux/iio/common/cros_ec_sensors_core.h index c582e1a14232..e72167b96d27 100644 --- a/include/linux/iio/common/cros_ec_sensors_core.h +++ b/include/linux/iio/common/cros_ec_sensors_core.h @@ -41,7 +41,6 @@ typedef irqreturn_t (*cros_ec_sensors_capture_t)(int irq, void *p); * @param: motion sensor parameters structure * @resp: motion sensor response structure * @type: type of motion sensor - * @loc: location where the motion sensor is placed * @range_updated: True if the range of the sensor has been * updated. * @curr_range: If updated, the current range value. @@ -67,7 +66,6 @@ struct cros_ec_sensors_core_state { struct ec_response_motion_sense *resp; enum motionsensor_type type; - enum motionsensor_location loc; bool range_updated; int curr_range; @@ -95,8 +93,11 @@ int cros_ec_sensors_read_cmd(struct iio_dev *indio_dev, unsigned long scan_mask, struct platform_device; int cros_ec_sensors_core_init(struct platform_device *pdev, struct iio_dev *indio_dev, bool physical_device, - cros_ec_sensors_capture_t trigger_capture, - cros_ec_sensorhub_push_data_cb_t push_data); + cros_ec_sensors_capture_t trigger_capture); + +int cros_ec_sensors_core_register(struct device *dev, + struct iio_dev *indio_dev, + cros_ec_sensorhub_push_data_cb_t push_data); irqreturn_t cros_ec_sensors_capture(int irq, void *p); int cros_ec_sensors_push_data(struct iio_dev *indio_dev, diff --git a/include/linux/iio/iio.h b/include/linux/iio/iio.h index 233d2e6b7721..5dfbfc991c69 100644 --- a/include/linux/iio/iio.h +++ b/include/linux/iio/iio.h @@ -9,14 +9,16 @@ #include #include +#include #include -#include /* IIO TODO LIST */ /* * Provide means of adjusting timer accuracy. * Currently assumes nano seconds. */ +struct of_phandle_args; + enum iio_shared_by { IIO_SEPARATE, IIO_SHARED_BY_TYPE, @@ -313,7 +315,6 @@ static inline bool iio_channel_has_available(const struct iio_chan_spec *chan, } s64 iio_get_time_ns(const struct iio_dev *indio_dev); -unsigned int iio_get_time_res(const struct iio_dev *indio_dev); /* * Device operating modes @@ -709,8 +710,13 @@ static inline void *iio_device_get_drvdata(const struct iio_dev *indio_dev) return dev_get_drvdata(&indio_dev->dev); } -/* Can we make this smaller? */ -#define IIO_ALIGN L1_CACHE_BYTES +/* + * Used to ensure the iio_priv() structure is aligned to allow that structure + * to in turn include IIO_DMA_MINALIGN'd elements such as buffers which + * must not share cachelines with the rest of the structure, thus making + * them safe for use with non-coherent DMA. + */ +#define IIO_DMA_MINALIGN ARCH_KMALLOC_MINALIGN struct iio_dev *iio_device_alloc(struct device *parent, int sizeof_priv); /* The information at the returned address is guaranteed to be cacheline aligned */ @@ -721,10 +727,13 @@ static inline void *iio_priv(const struct iio_dev *indio_dev) void iio_device_free(struct iio_dev *indio_dev); struct iio_dev *devm_iio_device_alloc(struct device *parent, int sizeof_priv); -__printf(2, 3) -struct iio_trigger *devm_iio_trigger_alloc(struct device *parent, - const char *fmt, ...); +#define devm_iio_trigger_alloc(parent, fmt, ...) \ + __devm_iio_trigger_alloc((parent), THIS_MODULE, (fmt), ##__VA_ARGS__) +__printf(3, 4) +struct iio_trigger *__devm_iio_trigger_alloc(struct device *parent, + struct module *this_mod, + const char *fmt, ...); /** * iio_get_debugfs_dentry() - helper function to get the debugfs_dentry * @indio_dev: IIO device structure for device diff --git a/include/linux/iio/trigger.h b/include/linux/iio/trigger.h index 4c69b144677b..f6360d9a492d 100644 --- a/include/linux/iio/trigger.h +++ b/include/linux/iio/trigger.h @@ -93,6 +93,11 @@ static inline void iio_trigger_put(struct iio_trigger *trig) static inline struct iio_trigger *iio_trigger_get(struct iio_trigger *trig) { get_device(&trig->dev); + + WARN_ONCE(list_empty(&trig->list), + "Getting non-registered iio trigger %s is prohibited\n", + trig->name); + __module_get(trig->owner); return trig; @@ -126,16 +131,10 @@ static inline void *iio_trigger_get_drvdata(struct iio_trigger *trig) * iio_trigger_register() - register a trigger with the IIO core * @trig_info: trigger to be registered **/ -#define iio_trigger_register(trig_info) \ - __iio_trigger_register((trig_info), THIS_MODULE) -int __iio_trigger_register(struct iio_trigger *trig_info, - struct module *this_mod); +int iio_trigger_register(struct iio_trigger *trig_info); -#define devm_iio_trigger_register(dev, trig_info) \ - __devm_iio_trigger_register((dev), (trig_info), THIS_MODULE) -int __devm_iio_trigger_register(struct device *dev, - struct iio_trigger *trig_info, - struct module *this_mod); +int devm_iio_trigger_register(struct device *dev, + struct iio_trigger *trig_info); /** * iio_trigger_unregister() - unregister a trigger from the core @@ -163,8 +162,13 @@ void iio_trigger_poll_chained(struct iio_trigger *trig); irqreturn_t iio_trigger_generic_data_rdy_poll(int irq, void *private); -__printf(2, 3) -struct iio_trigger *iio_trigger_alloc(struct device *parent, const char *fmt, ...); +#define iio_trigger_alloc(parent, fmt, ...) \ + __iio_trigger_alloc((parent), THIS_MODULE, (fmt), ##__VA_ARGS__) + +__printf(3, 4) +struct iio_trigger *__iio_trigger_alloc(struct device *parent, + struct module *this_mod, + const char *fmt, ...); void iio_trigger_free(struct iio_trigger *trig); /** diff --git a/include/linux/interconnect.h b/include/linux/interconnect.h index f685777b875e..2b0e784ba771 100644 --- a/include/linux/interconnect.h +++ b/include/linux/interconnect.h @@ -44,6 +44,7 @@ struct icc_path *icc_get(struct device *dev, const int src_id, const int dst_id); struct icc_path *of_icc_get(struct device *dev, const char *name); struct icc_path *devm_of_icc_get(struct device *dev, const char *name); +int devm_of_icc_bulk_get(struct device *dev, int num_paths, struct icc_bulk_data *paths); struct icc_path *of_icc_get_by_index(struct device *dev, int idx); void icc_put(struct icc_path *path); int icc_enable(struct icc_path *path); @@ -116,6 +117,12 @@ static inline int of_icc_bulk_get(struct device *dev, int num_paths, struct icc_ return 0; } +static inline int devm_of_icc_bulk_get(struct device *dev, int num_paths, + struct icc_bulk_data *paths) +{ + return 0; +} + static inline void icc_bulk_put(int num_paths, struct icc_bulk_data *paths) { } diff --git a/include/linux/miscdevice.h b/include/linux/miscdevice.h index 0676f18093f9..c0fea6ca5076 100644 --- a/include/linux/miscdevice.h +++ b/include/linux/miscdevice.h @@ -44,7 +44,7 @@ #define AGPGART_MINOR 175 #define TOSH_MINOR_DEV 181 #define HWRNG_MINOR 183 -#define MICROCODE_MINOR 184 +/*#define MICROCODE_MINOR 184 unused */ #define KEYPAD_MINOR 185 #define IRNET_MINOR 187 #define D7S_MINOR 193 diff --git a/include/linux/soundwire/sdw.h b/include/linux/soundwire/sdw.h index 76ce3f3ac0f2..39058c841469 100644 --- a/include/linux/soundwire/sdw.h +++ b/include/linux/soundwire/sdw.h @@ -637,7 +637,6 @@ struct sdw_slave_ops { * @dev: Linux device * @status: Status reported by the Slave * @bus: Bus handle - * @ops: Slave callback ops * @prop: Slave properties * @debugfs: Slave debugfs * @node: node for bus list @@ -646,9 +645,6 @@ struct sdw_slave_ops { * @dev_num: Current Device Number, values can be 0 or dev_num_sticky * @dev_num_sticky: one-time static Device Number assigned by Bus * @probed: boolean tracking driver state - * @probe_complete: completion utility to control potential races - * on startup between driver probe/initialization and SoundWire - * Slave state changes/implementation-defined interrupts * @enumeration_complete: completion utility to control potential races * on startup between device enumeration and read/write access to the * Slave device @@ -663,13 +659,13 @@ struct sdw_slave_ops { * for a Slave happens for the first time after enumeration * @is_mockup_device: status flag used to squelch errors in the command/control * protocol for SoundWire mockup devices + * @sdw_dev_lock: mutex used to protect callbacks/remove races */ struct sdw_slave { struct sdw_slave_id id; struct device dev; enum sdw_slave_status status; struct sdw_bus *bus; - const struct sdw_slave_ops *ops; struct sdw_slave_prop prop; #ifdef CONFIG_DEBUG_FS struct dentry *debugfs; @@ -680,12 +676,12 @@ struct sdw_slave { u16 dev_num; u16 dev_num_sticky; bool probed; - struct completion probe_complete; struct completion enumeration_complete; struct completion initialization_complete; u32 unattach_request; bool first_interrupt_done; bool is_mockup_device; + struct mutex sdw_dev_lock; /* protect callbacks/remove races */ }; #define dev_to_sdw_dev(_dev) container_of(_dev, struct sdw_slave, dev) diff --git a/include/linux/spmi.h b/include/linux/spmi.h index 729bcbf9f5ad..eac1956a8727 100644 --- a/include/linux/spmi.h +++ b/include/linux/spmi.h @@ -164,6 +164,9 @@ static inline void spmi_driver_unregister(struct spmi_driver *sdrv) module_driver(__spmi_driver, spmi_driver_register, \ spmi_driver_unregister) +struct device_node; + +struct spmi_device *spmi_device_from_of(struct device_node *np); int spmi_register_read(struct spmi_device *sdev, u8 addr, u8 *buf); int spmi_ext_register_read(struct spmi_device *sdev, u8 addr, u8 *buf, size_t len); diff --git a/include/linux/uacce.h b/include/linux/uacce.h index 48e319f40275..9ce88c28b0a8 100644 --- a/include/linux/uacce.h +++ b/include/linux/uacce.h @@ -70,6 +70,7 @@ enum uacce_q_state { * @wait: wait queue head * @list: index into uacce queues list * @qfrs: pointer of qfr regions + * @mutex: protects queue state * @state: queue state machine * @pasid: pasid associated to the mm * @handle: iommu_sva handle returned by iommu_sva_bind_device() @@ -80,6 +81,7 @@ struct uacce_queue { wait_queue_head_t wait; struct list_head list; struct uacce_qfile_region *qfrs[UACCE_MAX_REGION]; + struct mutex mutex; enum uacce_q_state state; u32 pasid; struct iommu_sva *handle; @@ -97,9 +99,9 @@ struct uacce_queue { * @dev_id: id of the uacce device * @cdev: cdev of the uacce * @dev: dev of the uacce + * @mutex: protects uacce operation * @priv: private pointer of the uacce * @queues: list of queues - * @queues_lock: lock for queues list * @inode: core vfs */ struct uacce_device { @@ -113,9 +115,9 @@ struct uacce_device { u32 dev_id; struct cdev *cdev; struct device dev; + struct mutex mutex; void *priv; struct list_head queues; - struct mutex queues_lock; struct inode *inode; }; diff --git a/include/soc/qcom/qcom-spmi-pmic.h b/include/soc/qcom/qcom-spmi-pmic.h new file mode 100644 index 000000000000..72398ff44719 --- /dev/null +++ b/include/soc/qcom/qcom-spmi-pmic.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2022 Linaro. All rights reserved. + * Author: Caleb Connolly + */ + +#ifndef __QCOM_SPMI_PMIC_H__ +#define __QCOM_SPMI_PMIC_H__ + +#include + +#define COMMON_SUBTYPE 0x00 +#define PM8941_SUBTYPE 0x01 +#define PM8841_SUBTYPE 0x02 +#define PM8019_SUBTYPE 0x03 +#define PM8226_SUBTYPE 0x04 +#define PM8110_SUBTYPE 0x05 +#define PMA8084_SUBTYPE 0x06 +#define PMI8962_SUBTYPE 0x07 +#define PMD9635_SUBTYPE 0x08 +#define PM8994_SUBTYPE 0x09 +#define PMI8994_SUBTYPE 0x0a +#define PM8916_SUBTYPE 0x0b +#define PM8004_SUBTYPE 0x0c +#define PM8909_SUBTYPE 0x0d +#define PM8028_SUBTYPE 0x0e +#define PM8901_SUBTYPE 0x0f +#define PM8950_SUBTYPE 0x10 +#define PMI8950_SUBTYPE 0x11 +#define PM8998_SUBTYPE 0x14 +#define PMI8998_SUBTYPE 0x15 +#define PM8005_SUBTYPE 0x18 +#define PM660L_SUBTYPE 0x1A +#define PM660_SUBTYPE 0x1B +#define PM8150_SUBTYPE 0x1E +#define PM8150L_SUBTYPE 0x1f +#define PM8150B_SUBTYPE 0x20 +#define PMK8002_SUBTYPE 0x21 +#define PM8009_SUBTYPE 0x24 +#define PM8150C_SUBTYPE 0x26 +#define SMB2351_SUBTYPE 0x29 + +#define PMI8998_FAB_ID_SMIC 0x11 +#define PMI8998_FAB_ID_GF 0x30 + +#define PM660_FAB_ID_GF 0x0 +#define PM660_FAB_ID_TSMC 0x2 +#define PM660_FAB_ID_MX 0x3 + +struct qcom_spmi_pmic { + unsigned int type; + unsigned int subtype; + unsigned int major; + unsigned int minor; + unsigned int rev2; + unsigned int fab_id; + const char *name; +}; + +const struct qcom_spmi_pmic *qcom_pmic_get(struct device *dev); + +#endif /* __QCOM_SPMI_PMIC_H__ */ diff --git a/include/trace/events/spmi.h b/include/trace/events/spmi.h index 8b60efe18ba6..a6819fd85cdf 100644 --- a/include/trace/events/spmi.h +++ b/include/trace/events/spmi.h @@ -21,15 +21,15 @@ TRACE_EVENT(spmi_write_begin, __field ( u8, sid ) __field ( u16, addr ) __field ( u8, len ) - __dynamic_array ( u8, buf, len + 1 ) + __dynamic_array ( u8, buf, len ) ), TP_fast_assign( __entry->opcode = opcode; __entry->sid = sid; __entry->addr = addr; - __entry->len = len + 1; - memcpy(__get_dynamic_array(buf), buf, len + 1); + __entry->len = len; + memcpy(__get_dynamic_array(buf), buf, len); ), TP_printk("opc=%d sid=%02d addr=0x%04x len=%d buf=0x[%*phD]", @@ -92,7 +92,7 @@ TRACE_EVENT(spmi_read_end, __field ( u16, addr ) __field ( int, ret ) __field ( u8, len ) - __dynamic_array ( u8, buf, len + 1 ) + __dynamic_array ( u8, buf, len ) ), TP_fast_assign( @@ -100,8 +100,8 @@ TRACE_EVENT(spmi_read_end, __entry->sid = sid; __entry->addr = addr; __entry->ret = ret; - __entry->len = len + 1; - memcpy(__get_dynamic_array(buf), buf, len + 1); + __entry->len = len; + memcpy(__get_dynamic_array(buf), buf, len); ), TP_printk("opc=%d sid=%02d addr=0x%04x ret=%d len=%02d buf=0x[%*phD]", diff --git a/include/uapi/linux/android/binder.h b/include/uapi/linux/android/binder.h index 986333cf5bbe..e72e4de8f452 100644 --- a/include/uapi/linux/android/binder.h +++ b/include/uapi/linux/android/binder.h @@ -287,6 +287,7 @@ enum transaction_flags { TF_STATUS_CODE = 0x08, /* contents are a 32-bit status code */ TF_ACCEPT_FDS = 0x10, /* allow replies with file descriptors */ TF_CLEAR_BUF = 0x20, /* clear buffer on txn complete */ + TF_UPDATE_TXN = 0x40, /* update the outdated pending async txn */ }; struct binder_transaction_data { diff --git a/include/uapi/misc/habanalabs.h b/include/uapi/misc/habanalabs.h index 52540d5b4fc9..5d06d5c74dd1 100644 --- a/include/uapi/misc/habanalabs.h +++ b/include/uapi/misc/habanalabs.h @@ -184,6 +184,285 @@ enum gaudi_queue_id { GAUDI_QUEUE_ID_SIZE }; +/* + * In GAUDI2 we have two modes of operation in regard to queues: + * 1. Legacy mode, where each QMAN exposes 4 streams to the user + * 2. F/W mode, where we use F/W to schedule the JOBS to the different queues. + * + * When in legacy mode, the user sends the queue id per JOB according to + * enum gaudi2_queue_id below. + * + * When in F/W mode, the user sends a stream id per Command Submission. The + * stream id is a running number from 0 up to (N-1), where N is the number + * of streams the F/W exposes and is passed to the user in + * struct hl_info_hw_ip_info + */ + +enum gaudi2_queue_id { + GAUDI2_QUEUE_ID_PDMA_0_0 = 0, + GAUDI2_QUEUE_ID_PDMA_0_1 = 1, + GAUDI2_QUEUE_ID_PDMA_0_2 = 2, + GAUDI2_QUEUE_ID_PDMA_0_3 = 3, + GAUDI2_QUEUE_ID_PDMA_1_0 = 4, + GAUDI2_QUEUE_ID_PDMA_1_1 = 5, + GAUDI2_QUEUE_ID_PDMA_1_2 = 6, + GAUDI2_QUEUE_ID_PDMA_1_3 = 7, + GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0 = 8, + GAUDI2_QUEUE_ID_DCORE0_EDMA_0_1 = 9, + GAUDI2_QUEUE_ID_DCORE0_EDMA_0_2 = 10, + GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3 = 11, + GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0 = 12, + GAUDI2_QUEUE_ID_DCORE0_EDMA_1_1 = 13, + GAUDI2_QUEUE_ID_DCORE0_EDMA_1_2 = 14, + GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3 = 15, + GAUDI2_QUEUE_ID_DCORE0_MME_0_0 = 16, + GAUDI2_QUEUE_ID_DCORE0_MME_0_1 = 17, + GAUDI2_QUEUE_ID_DCORE0_MME_0_2 = 18, + GAUDI2_QUEUE_ID_DCORE0_MME_0_3 = 19, + GAUDI2_QUEUE_ID_DCORE0_TPC_0_0 = 20, + GAUDI2_QUEUE_ID_DCORE0_TPC_0_1 = 21, + GAUDI2_QUEUE_ID_DCORE0_TPC_0_2 = 22, + GAUDI2_QUEUE_ID_DCORE0_TPC_0_3 = 23, + GAUDI2_QUEUE_ID_DCORE0_TPC_1_0 = 24, + GAUDI2_QUEUE_ID_DCORE0_TPC_1_1 = 25, + GAUDI2_QUEUE_ID_DCORE0_TPC_1_2 = 26, + GAUDI2_QUEUE_ID_DCORE0_TPC_1_3 = 27, + GAUDI2_QUEUE_ID_DCORE0_TPC_2_0 = 28, + GAUDI2_QUEUE_ID_DCORE0_TPC_2_1 = 29, + GAUDI2_QUEUE_ID_DCORE0_TPC_2_2 = 30, + GAUDI2_QUEUE_ID_DCORE0_TPC_2_3 = 31, + GAUDI2_QUEUE_ID_DCORE0_TPC_3_0 = 32, + GAUDI2_QUEUE_ID_DCORE0_TPC_3_1 = 33, + GAUDI2_QUEUE_ID_DCORE0_TPC_3_2 = 34, + GAUDI2_QUEUE_ID_DCORE0_TPC_3_3 = 35, + GAUDI2_QUEUE_ID_DCORE0_TPC_4_0 = 36, + GAUDI2_QUEUE_ID_DCORE0_TPC_4_1 = 37, + GAUDI2_QUEUE_ID_DCORE0_TPC_4_2 = 38, + GAUDI2_QUEUE_ID_DCORE0_TPC_4_3 = 39, + GAUDI2_QUEUE_ID_DCORE0_TPC_5_0 = 40, + GAUDI2_QUEUE_ID_DCORE0_TPC_5_1 = 41, + GAUDI2_QUEUE_ID_DCORE0_TPC_5_2 = 42, + GAUDI2_QUEUE_ID_DCORE0_TPC_5_3 = 43, + GAUDI2_QUEUE_ID_DCORE0_TPC_6_0 = 44, + GAUDI2_QUEUE_ID_DCORE0_TPC_6_1 = 45, + GAUDI2_QUEUE_ID_DCORE0_TPC_6_2 = 46, + GAUDI2_QUEUE_ID_DCORE0_TPC_6_3 = 47, + GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0 = 48, + GAUDI2_QUEUE_ID_DCORE1_EDMA_0_1 = 49, + GAUDI2_QUEUE_ID_DCORE1_EDMA_0_2 = 50, + GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3 = 51, + GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0 = 52, + GAUDI2_QUEUE_ID_DCORE1_EDMA_1_1 = 53, + GAUDI2_QUEUE_ID_DCORE1_EDMA_1_2 = 54, + GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3 = 55, + GAUDI2_QUEUE_ID_DCORE1_MME_0_0 = 56, + GAUDI2_QUEUE_ID_DCORE1_MME_0_1 = 57, + GAUDI2_QUEUE_ID_DCORE1_MME_0_2 = 58, + GAUDI2_QUEUE_ID_DCORE1_MME_0_3 = 59, + GAUDI2_QUEUE_ID_DCORE1_TPC_0_0 = 60, + GAUDI2_QUEUE_ID_DCORE1_TPC_0_1 = 61, + GAUDI2_QUEUE_ID_DCORE1_TPC_0_2 = 62, + GAUDI2_QUEUE_ID_DCORE1_TPC_0_3 = 63, + GAUDI2_QUEUE_ID_DCORE1_TPC_1_0 = 64, + GAUDI2_QUEUE_ID_DCORE1_TPC_1_1 = 65, + GAUDI2_QUEUE_ID_DCORE1_TPC_1_2 = 66, + GAUDI2_QUEUE_ID_DCORE1_TPC_1_3 = 67, + GAUDI2_QUEUE_ID_DCORE1_TPC_2_0 = 68, + GAUDI2_QUEUE_ID_DCORE1_TPC_2_1 = 69, + GAUDI2_QUEUE_ID_DCORE1_TPC_2_2 = 70, + GAUDI2_QUEUE_ID_DCORE1_TPC_2_3 = 71, + GAUDI2_QUEUE_ID_DCORE1_TPC_3_0 = 72, + GAUDI2_QUEUE_ID_DCORE1_TPC_3_1 = 73, + GAUDI2_QUEUE_ID_DCORE1_TPC_3_2 = 74, + GAUDI2_QUEUE_ID_DCORE1_TPC_3_3 = 75, + GAUDI2_QUEUE_ID_DCORE1_TPC_4_0 = 76, + GAUDI2_QUEUE_ID_DCORE1_TPC_4_1 = 77, + GAUDI2_QUEUE_ID_DCORE1_TPC_4_2 = 78, + GAUDI2_QUEUE_ID_DCORE1_TPC_4_3 = 79, + GAUDI2_QUEUE_ID_DCORE1_TPC_5_0 = 80, + GAUDI2_QUEUE_ID_DCORE1_TPC_5_1 = 81, + GAUDI2_QUEUE_ID_DCORE1_TPC_5_2 = 82, + GAUDI2_QUEUE_ID_DCORE1_TPC_5_3 = 83, + GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0 = 84, + GAUDI2_QUEUE_ID_DCORE2_EDMA_0_1 = 85, + GAUDI2_QUEUE_ID_DCORE2_EDMA_0_2 = 86, + GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3 = 87, + GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0 = 88, + GAUDI2_QUEUE_ID_DCORE2_EDMA_1_1 = 89, + GAUDI2_QUEUE_ID_DCORE2_EDMA_1_2 = 90, + GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3 = 91, + GAUDI2_QUEUE_ID_DCORE2_MME_0_0 = 92, + GAUDI2_QUEUE_ID_DCORE2_MME_0_1 = 93, + GAUDI2_QUEUE_ID_DCORE2_MME_0_2 = 94, + GAUDI2_QUEUE_ID_DCORE2_MME_0_3 = 95, + GAUDI2_QUEUE_ID_DCORE2_TPC_0_0 = 96, + GAUDI2_QUEUE_ID_DCORE2_TPC_0_1 = 97, + GAUDI2_QUEUE_ID_DCORE2_TPC_0_2 = 98, + GAUDI2_QUEUE_ID_DCORE2_TPC_0_3 = 99, + GAUDI2_QUEUE_ID_DCORE2_TPC_1_0 = 100, + GAUDI2_QUEUE_ID_DCORE2_TPC_1_1 = 101, + GAUDI2_QUEUE_ID_DCORE2_TPC_1_2 = 102, + GAUDI2_QUEUE_ID_DCORE2_TPC_1_3 = 103, + GAUDI2_QUEUE_ID_DCORE2_TPC_2_0 = 104, + GAUDI2_QUEUE_ID_DCORE2_TPC_2_1 = 105, + GAUDI2_QUEUE_ID_DCORE2_TPC_2_2 = 106, + GAUDI2_QUEUE_ID_DCORE2_TPC_2_3 = 107, + GAUDI2_QUEUE_ID_DCORE2_TPC_3_0 = 108, + GAUDI2_QUEUE_ID_DCORE2_TPC_3_1 = 109, + GAUDI2_QUEUE_ID_DCORE2_TPC_3_2 = 110, + GAUDI2_QUEUE_ID_DCORE2_TPC_3_3 = 111, + GAUDI2_QUEUE_ID_DCORE2_TPC_4_0 = 112, + GAUDI2_QUEUE_ID_DCORE2_TPC_4_1 = 113, + GAUDI2_QUEUE_ID_DCORE2_TPC_4_2 = 114, + GAUDI2_QUEUE_ID_DCORE2_TPC_4_3 = 115, + GAUDI2_QUEUE_ID_DCORE2_TPC_5_0 = 116, + GAUDI2_QUEUE_ID_DCORE2_TPC_5_1 = 117, + GAUDI2_QUEUE_ID_DCORE2_TPC_5_2 = 118, + GAUDI2_QUEUE_ID_DCORE2_TPC_5_3 = 119, + GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0 = 120, + GAUDI2_QUEUE_ID_DCORE3_EDMA_0_1 = 121, + GAUDI2_QUEUE_ID_DCORE3_EDMA_0_2 = 122, + GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3 = 123, + GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0 = 124, + GAUDI2_QUEUE_ID_DCORE3_EDMA_1_1 = 125, + GAUDI2_QUEUE_ID_DCORE3_EDMA_1_2 = 126, + GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3 = 127, + GAUDI2_QUEUE_ID_DCORE3_MME_0_0 = 128, + GAUDI2_QUEUE_ID_DCORE3_MME_0_1 = 129, + GAUDI2_QUEUE_ID_DCORE3_MME_0_2 = 130, + GAUDI2_QUEUE_ID_DCORE3_MME_0_3 = 131, + GAUDI2_QUEUE_ID_DCORE3_TPC_0_0 = 132, + GAUDI2_QUEUE_ID_DCORE3_TPC_0_1 = 133, + GAUDI2_QUEUE_ID_DCORE3_TPC_0_2 = 134, + GAUDI2_QUEUE_ID_DCORE3_TPC_0_3 = 135, + GAUDI2_QUEUE_ID_DCORE3_TPC_1_0 = 136, + GAUDI2_QUEUE_ID_DCORE3_TPC_1_1 = 137, + GAUDI2_QUEUE_ID_DCORE3_TPC_1_2 = 138, + GAUDI2_QUEUE_ID_DCORE3_TPC_1_3 = 139, + GAUDI2_QUEUE_ID_DCORE3_TPC_2_0 = 140, + GAUDI2_QUEUE_ID_DCORE3_TPC_2_1 = 141, + GAUDI2_QUEUE_ID_DCORE3_TPC_2_2 = 142, + GAUDI2_QUEUE_ID_DCORE3_TPC_2_3 = 143, + GAUDI2_QUEUE_ID_DCORE3_TPC_3_0 = 144, + GAUDI2_QUEUE_ID_DCORE3_TPC_3_1 = 145, + GAUDI2_QUEUE_ID_DCORE3_TPC_3_2 = 146, + GAUDI2_QUEUE_ID_DCORE3_TPC_3_3 = 147, + GAUDI2_QUEUE_ID_DCORE3_TPC_4_0 = 148, + GAUDI2_QUEUE_ID_DCORE3_TPC_4_1 = 149, + GAUDI2_QUEUE_ID_DCORE3_TPC_4_2 = 150, + GAUDI2_QUEUE_ID_DCORE3_TPC_4_3 = 151, + GAUDI2_QUEUE_ID_DCORE3_TPC_5_0 = 152, + GAUDI2_QUEUE_ID_DCORE3_TPC_5_1 = 153, + GAUDI2_QUEUE_ID_DCORE3_TPC_5_2 = 154, + GAUDI2_QUEUE_ID_DCORE3_TPC_5_3 = 155, + GAUDI2_QUEUE_ID_NIC_0_0 = 156, + GAUDI2_QUEUE_ID_NIC_0_1 = 157, + GAUDI2_QUEUE_ID_NIC_0_2 = 158, + GAUDI2_QUEUE_ID_NIC_0_3 = 159, + GAUDI2_QUEUE_ID_NIC_1_0 = 160, + GAUDI2_QUEUE_ID_NIC_1_1 = 161, + GAUDI2_QUEUE_ID_NIC_1_2 = 162, + GAUDI2_QUEUE_ID_NIC_1_3 = 163, + GAUDI2_QUEUE_ID_NIC_2_0 = 164, + GAUDI2_QUEUE_ID_NIC_2_1 = 165, + GAUDI2_QUEUE_ID_NIC_2_2 = 166, + GAUDI2_QUEUE_ID_NIC_2_3 = 167, + GAUDI2_QUEUE_ID_NIC_3_0 = 168, + GAUDI2_QUEUE_ID_NIC_3_1 = 169, + GAUDI2_QUEUE_ID_NIC_3_2 = 170, + GAUDI2_QUEUE_ID_NIC_3_3 = 171, + GAUDI2_QUEUE_ID_NIC_4_0 = 172, + GAUDI2_QUEUE_ID_NIC_4_1 = 173, + GAUDI2_QUEUE_ID_NIC_4_2 = 174, + GAUDI2_QUEUE_ID_NIC_4_3 = 175, + GAUDI2_QUEUE_ID_NIC_5_0 = 176, + GAUDI2_QUEUE_ID_NIC_5_1 = 177, + GAUDI2_QUEUE_ID_NIC_5_2 = 178, + GAUDI2_QUEUE_ID_NIC_5_3 = 179, + GAUDI2_QUEUE_ID_NIC_6_0 = 180, + GAUDI2_QUEUE_ID_NIC_6_1 = 181, + GAUDI2_QUEUE_ID_NIC_6_2 = 182, + GAUDI2_QUEUE_ID_NIC_6_3 = 183, + GAUDI2_QUEUE_ID_NIC_7_0 = 184, + GAUDI2_QUEUE_ID_NIC_7_1 = 185, + GAUDI2_QUEUE_ID_NIC_7_2 = 186, + GAUDI2_QUEUE_ID_NIC_7_3 = 187, + GAUDI2_QUEUE_ID_NIC_8_0 = 188, + GAUDI2_QUEUE_ID_NIC_8_1 = 189, + GAUDI2_QUEUE_ID_NIC_8_2 = 190, + GAUDI2_QUEUE_ID_NIC_8_3 = 191, + GAUDI2_QUEUE_ID_NIC_9_0 = 192, + GAUDI2_QUEUE_ID_NIC_9_1 = 193, + GAUDI2_QUEUE_ID_NIC_9_2 = 194, + GAUDI2_QUEUE_ID_NIC_9_3 = 195, + GAUDI2_QUEUE_ID_NIC_10_0 = 196, + GAUDI2_QUEUE_ID_NIC_10_1 = 197, + GAUDI2_QUEUE_ID_NIC_10_2 = 198, + GAUDI2_QUEUE_ID_NIC_10_3 = 199, + GAUDI2_QUEUE_ID_NIC_11_0 = 200, + GAUDI2_QUEUE_ID_NIC_11_1 = 201, + GAUDI2_QUEUE_ID_NIC_11_2 = 202, + GAUDI2_QUEUE_ID_NIC_11_3 = 203, + GAUDI2_QUEUE_ID_NIC_12_0 = 204, + GAUDI2_QUEUE_ID_NIC_12_1 = 205, + GAUDI2_QUEUE_ID_NIC_12_2 = 206, + GAUDI2_QUEUE_ID_NIC_12_3 = 207, + GAUDI2_QUEUE_ID_NIC_13_0 = 208, + GAUDI2_QUEUE_ID_NIC_13_1 = 209, + GAUDI2_QUEUE_ID_NIC_13_2 = 210, + GAUDI2_QUEUE_ID_NIC_13_3 = 211, + GAUDI2_QUEUE_ID_NIC_14_0 = 212, + GAUDI2_QUEUE_ID_NIC_14_1 = 213, + GAUDI2_QUEUE_ID_NIC_14_2 = 214, + GAUDI2_QUEUE_ID_NIC_14_3 = 215, + GAUDI2_QUEUE_ID_NIC_15_0 = 216, + GAUDI2_QUEUE_ID_NIC_15_1 = 217, + GAUDI2_QUEUE_ID_NIC_15_2 = 218, + GAUDI2_QUEUE_ID_NIC_15_3 = 219, + GAUDI2_QUEUE_ID_NIC_16_0 = 220, + GAUDI2_QUEUE_ID_NIC_16_1 = 221, + GAUDI2_QUEUE_ID_NIC_16_2 = 222, + GAUDI2_QUEUE_ID_NIC_16_3 = 223, + GAUDI2_QUEUE_ID_NIC_17_0 = 224, + GAUDI2_QUEUE_ID_NIC_17_1 = 225, + GAUDI2_QUEUE_ID_NIC_17_2 = 226, + GAUDI2_QUEUE_ID_NIC_17_3 = 227, + GAUDI2_QUEUE_ID_NIC_18_0 = 228, + GAUDI2_QUEUE_ID_NIC_18_1 = 229, + GAUDI2_QUEUE_ID_NIC_18_2 = 230, + GAUDI2_QUEUE_ID_NIC_18_3 = 231, + GAUDI2_QUEUE_ID_NIC_19_0 = 232, + GAUDI2_QUEUE_ID_NIC_19_1 = 233, + GAUDI2_QUEUE_ID_NIC_19_2 = 234, + GAUDI2_QUEUE_ID_NIC_19_3 = 235, + GAUDI2_QUEUE_ID_NIC_20_0 = 236, + GAUDI2_QUEUE_ID_NIC_20_1 = 237, + GAUDI2_QUEUE_ID_NIC_20_2 = 238, + GAUDI2_QUEUE_ID_NIC_20_3 = 239, + GAUDI2_QUEUE_ID_NIC_21_0 = 240, + GAUDI2_QUEUE_ID_NIC_21_1 = 241, + GAUDI2_QUEUE_ID_NIC_21_2 = 242, + GAUDI2_QUEUE_ID_NIC_21_3 = 243, + GAUDI2_QUEUE_ID_NIC_22_0 = 244, + GAUDI2_QUEUE_ID_NIC_22_1 = 245, + GAUDI2_QUEUE_ID_NIC_22_2 = 246, + GAUDI2_QUEUE_ID_NIC_22_3 = 247, + GAUDI2_QUEUE_ID_NIC_23_0 = 248, + GAUDI2_QUEUE_ID_NIC_23_1 = 249, + GAUDI2_QUEUE_ID_NIC_23_2 = 250, + GAUDI2_QUEUE_ID_NIC_23_3 = 251, + GAUDI2_QUEUE_ID_ROT_0_0 = 252, + GAUDI2_QUEUE_ID_ROT_0_1 = 253, + GAUDI2_QUEUE_ID_ROT_0_2 = 254, + GAUDI2_QUEUE_ID_ROT_0_3 = 255, + GAUDI2_QUEUE_ID_ROT_1_0 = 256, + GAUDI2_QUEUE_ID_ROT_1_1 = 257, + GAUDI2_QUEUE_ID_ROT_1_2 = 258, + GAUDI2_QUEUE_ID_ROT_1_3 = 259, + GAUDI2_QUEUE_ID_CPU_PQ = 260, + GAUDI2_QUEUE_ID_SIZE +}; + /* * Engine Numbering * @@ -242,6 +521,85 @@ enum gaudi_engine_id { GAUDI_ENGINE_ID_SIZE }; +enum gaudi2_engine_id { + GAUDI2_DCORE0_ENGINE_ID_EDMA_0 = 0, + GAUDI2_DCORE0_ENGINE_ID_EDMA_1, + GAUDI2_DCORE0_ENGINE_ID_MME, + GAUDI2_DCORE0_ENGINE_ID_TPC_0, + GAUDI2_DCORE0_ENGINE_ID_TPC_1, + GAUDI2_DCORE0_ENGINE_ID_TPC_2, + GAUDI2_DCORE0_ENGINE_ID_TPC_3, + GAUDI2_DCORE0_ENGINE_ID_TPC_4, + GAUDI2_DCORE0_ENGINE_ID_TPC_5, + GAUDI2_DCORE0_ENGINE_ID_DEC_0, + GAUDI2_DCORE0_ENGINE_ID_DEC_1, + GAUDI2_DCORE1_ENGINE_ID_EDMA_0, + GAUDI2_DCORE1_ENGINE_ID_EDMA_1, + GAUDI2_DCORE1_ENGINE_ID_MME, + GAUDI2_DCORE1_ENGINE_ID_TPC_0, + GAUDI2_DCORE1_ENGINE_ID_TPC_1, + GAUDI2_DCORE1_ENGINE_ID_TPC_2, + GAUDI2_DCORE1_ENGINE_ID_TPC_3, + GAUDI2_DCORE1_ENGINE_ID_TPC_4, + GAUDI2_DCORE1_ENGINE_ID_TPC_5, + GAUDI2_DCORE1_ENGINE_ID_DEC_0, + GAUDI2_DCORE1_ENGINE_ID_DEC_1, + GAUDI2_DCORE2_ENGINE_ID_EDMA_0, + GAUDI2_DCORE2_ENGINE_ID_EDMA_1, + GAUDI2_DCORE2_ENGINE_ID_MME, + GAUDI2_DCORE2_ENGINE_ID_TPC_0, + GAUDI2_DCORE2_ENGINE_ID_TPC_1, + GAUDI2_DCORE2_ENGINE_ID_TPC_2, + GAUDI2_DCORE2_ENGINE_ID_TPC_3, + GAUDI2_DCORE2_ENGINE_ID_TPC_4, + GAUDI2_DCORE2_ENGINE_ID_TPC_5, + GAUDI2_DCORE2_ENGINE_ID_DEC_0, + GAUDI2_DCORE2_ENGINE_ID_DEC_1, + GAUDI2_DCORE3_ENGINE_ID_EDMA_0, + GAUDI2_DCORE3_ENGINE_ID_EDMA_1, + GAUDI2_DCORE3_ENGINE_ID_MME, + GAUDI2_DCORE3_ENGINE_ID_TPC_0, + GAUDI2_DCORE3_ENGINE_ID_TPC_1, + GAUDI2_DCORE3_ENGINE_ID_TPC_2, + GAUDI2_DCORE3_ENGINE_ID_TPC_3, + GAUDI2_DCORE3_ENGINE_ID_TPC_4, + GAUDI2_DCORE3_ENGINE_ID_TPC_5, + GAUDI2_DCORE3_ENGINE_ID_DEC_0, + GAUDI2_DCORE3_ENGINE_ID_DEC_1, + GAUDI2_DCORE0_ENGINE_ID_TPC_6, + GAUDI2_ENGINE_ID_PDMA_0, + GAUDI2_ENGINE_ID_PDMA_1, + GAUDI2_ENGINE_ID_ROT_0, + GAUDI2_ENGINE_ID_ROT_1, + GAUDI2_PCIE_ENGINE_ID_DEC_0, + GAUDI2_PCIE_ENGINE_ID_DEC_1, + GAUDI2_ENGINE_ID_NIC0_0, + GAUDI2_ENGINE_ID_NIC0_1, + GAUDI2_ENGINE_ID_NIC1_0, + GAUDI2_ENGINE_ID_NIC1_1, + GAUDI2_ENGINE_ID_NIC2_0, + GAUDI2_ENGINE_ID_NIC2_1, + GAUDI2_ENGINE_ID_NIC3_0, + GAUDI2_ENGINE_ID_NIC3_1, + GAUDI2_ENGINE_ID_NIC4_0, + GAUDI2_ENGINE_ID_NIC4_1, + GAUDI2_ENGINE_ID_NIC5_0, + GAUDI2_ENGINE_ID_NIC5_1, + GAUDI2_ENGINE_ID_NIC6_0, + GAUDI2_ENGINE_ID_NIC6_1, + GAUDI2_ENGINE_ID_NIC7_0, + GAUDI2_ENGINE_ID_NIC7_1, + GAUDI2_ENGINE_ID_NIC8_0, + GAUDI2_ENGINE_ID_NIC8_1, + GAUDI2_ENGINE_ID_NIC9_0, + GAUDI2_ENGINE_ID_NIC9_1, + GAUDI2_ENGINE_ID_NIC10_0, + GAUDI2_ENGINE_ID_NIC10_1, + GAUDI2_ENGINE_ID_NIC11_0, + GAUDI2_ENGINE_ID_NIC11_1, + GAUDI2_ENGINE_ID_SIZE +}; + /* * ASIC specific PLL index * @@ -275,6 +633,49 @@ enum hl_gaudi_pll_index { HL_GAUDI_PLL_MAX }; +enum hl_gaudi2_pll_index { + HL_GAUDI2_CPU_PLL = 0, + HL_GAUDI2_PCI_PLL, + HL_GAUDI2_SRAM_PLL, + HL_GAUDI2_HBM_PLL, + HL_GAUDI2_NIC_PLL, + HL_GAUDI2_DMA_PLL, + HL_GAUDI2_MESH_PLL, + HL_GAUDI2_MME_PLL, + HL_GAUDI2_TPC_PLL, + HL_GAUDI2_IF_PLL, + HL_GAUDI2_VID_PLL, + HL_GAUDI2_MSS_PLL, + HL_GAUDI2_PLL_MAX +}; + +/** + * enum hl_goya_dma_direction - Direction of DMA operation inside a LIN_DMA packet that is + * submitted to the GOYA's DMA QMAN. This attribute is not relevant + * to the H/W but the kernel driver use it to parse the packet's + * addresses and patch/validate them. + * @HL_DMA_HOST_TO_DRAM: DMA operation from Host memory to GOYA's DDR. + * @HL_DMA_HOST_TO_SRAM: DMA operation from Host memory to GOYA's SRAM. + * @HL_DMA_DRAM_TO_SRAM: DMA operation from GOYA's DDR to GOYA's SRAM. + * @HL_DMA_SRAM_TO_DRAM: DMA operation from GOYA's SRAM to GOYA's DDR. + * @HL_DMA_SRAM_TO_HOST: DMA operation from GOYA's SRAM to Host memory. + * @HL_DMA_DRAM_TO_HOST: DMA operation from GOYA's DDR to Host memory. + * @HL_DMA_DRAM_TO_DRAM: DMA operation from GOYA's DDR to GOYA's DDR. + * @HL_DMA_SRAM_TO_SRAM: DMA operation from GOYA's SRAM to GOYA's SRAM. + * @HL_DMA_ENUM_MAX: number of values in enum + */ +enum hl_goya_dma_direction { + HL_DMA_HOST_TO_DRAM, + HL_DMA_HOST_TO_SRAM, + HL_DMA_DRAM_TO_SRAM, + HL_DMA_SRAM_TO_DRAM, + HL_DMA_SRAM_TO_HOST, + HL_DMA_DRAM_TO_HOST, + HL_DMA_DRAM_TO_DRAM, + HL_DMA_SRAM_TO_SRAM, + HL_DMA_ENUM_MAX +}; + /** * enum hl_device_status - Device status information. * @HL_DEVICE_STATUS_OPERATIONAL: Device is operational. @@ -283,6 +684,8 @@ enum hl_gaudi_pll_index { * @HL_DEVICE_STATUS_NEEDS_RESET: Device needs reset because auto reset was disabled. * @HL_DEVICE_STATUS_IN_DEVICE_CREATION: Device is operational but its creation is still in * progress. + * @HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE: Device is currently during reset that was + * triggered because the user released the device * @HL_DEVICE_STATUS_LAST: Last status. */ enum hl_device_status { @@ -291,7 +694,8 @@ enum hl_device_status { HL_DEVICE_STATUS_MALFUNCTION, HL_DEVICE_STATUS_NEEDS_RESET, HL_DEVICE_STATUS_IN_DEVICE_CREATION, - HL_DEVICE_STATUS_LAST = HL_DEVICE_STATUS_IN_DEVICE_CREATION + HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE, + HL_DEVICE_STATUS_LAST = HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE }; enum hl_server_type { @@ -299,7 +703,8 @@ enum hl_server_type { HL_SERVER_GAUDI_HLS1 = 1, HL_SERVER_GAUDI_HLS1H = 2, HL_SERVER_GAUDI_TYPE1 = 3, - HL_SERVER_GAUDI_TYPE2 = 4 + HL_SERVER_GAUDI_TYPE2 = 4, + HL_SERVER_GAUDI2_HLS2 = 5 }; /* Opcode for management ioctl @@ -352,6 +757,7 @@ enum hl_server_type { * HL_INFO_REGISTER_EVENTFD - Register eventfd for event notifications. * HL_INFO_UNREGISTER_EVENTFD - Unregister eventfd * HL_INFO_GET_EVENTS - Retrieve the last occurred events + * HL_INFO_UNDEFINED_OPCODE_EVENT - Retrieve last undefined opcode error information. */ #define HL_INFO_HW_IP_INFO 0 #define HL_INFO_HW_EVENTS 1 @@ -380,6 +786,7 @@ enum hl_server_type { #define HL_INFO_REGISTER_EVENTFD 28 #define HL_INFO_UNREGISTER_EVENTFD 29 #define HL_INFO_GET_EVENTS 30 +#define HL_INFO_UNDEFINED_OPCODE_EVENT 31 #define HL_INFO_VERSION_MAX_LEN 128 #define HL_INFO_CARD_NAME_MAX_LEN 16 @@ -399,8 +806,10 @@ enum hl_server_type { * @device_id: PCI device ID of the ASIC. * @module_id: Module ID of the ASIC for mezzanine cards in servers * (From OCP spec). + * @decoder_enabled_mask: Bit-mask that represents which decoders are enabled. * @first_available_interrupt_id: The first available interrupt ID for the user * to be used when it works with user interrupts. + * Relevant for Gaudi2 and later. * @server_type: Server type that the Gaudi ASIC is currently installed in. * The value is according to enum hl_server_type * @cpld_version: CPLD version on the board. @@ -412,9 +821,15 @@ enum hl_server_type { * @tpc_enabled_mask: Bit-mask that represents which TPCs are enabled. Relevant * for Goya/Gaudi only. * @dram_enabled: Whether the DRAM is enabled. + * @mme_master_slave_mode: Indicate whether the MME is working in master/slave + * configuration. Relevant for Greco and later. * @cpucp_version: The CPUCP f/w version. * @card_name: The card name as passed by the f/w. + * @tpc_enabled_mask_ext: Bit-mask that represents which TPCs are enabled. + * Relevant for Greco and later. * @dram_page_size: The DRAM physical page size. + * @edma_enabled_mask: Bit-mask that represents which EDMAs are enabled. + * Relevant for Gaudi2 and later. * @number_of_user_interrupts: The number of interrupts that are available to the userspace * application to use. Relevant for Gaudi2 and later. * @device_mem_alloc_default_page_size: default page size used in device memory allocation. @@ -427,7 +842,7 @@ struct hl_info_hw_ip_info { __u32 num_of_events; __u32 device_id; __u32 module_id; - __u32 reserved; + __u32 decoder_enabled_mask; __u16 first_available_interrupt_id; __u16 server_type; __u32 cpld_version; @@ -437,12 +852,13 @@ struct hl_info_hw_ip_info { __u32 psoc_pci_pll_div_factor; __u8 tpc_enabled_mask; __u8 dram_enabled; - __u8 pad[2]; + __u8 reserved; + __u8 mme_master_slave_mode; __u8 cpucp_version[HL_INFO_VERSION_MAX_LEN]; __u8 card_name[HL_INFO_CARD_NAME_MAX_LEN]; - __u64 reserved2; + __u64 tpc_enabled_mask_ext; __u64 dram_page_size; - __u32 reserved3; + __u32 edma_enabled_mask; __u16 number_of_user_interrupts; __u16 pad2; __u64 reserved4; @@ -656,6 +1072,34 @@ struct hl_info_razwi_event { __u8 pad[2]; }; +#define MAX_QMAN_STREAMS_INFO 4 +#define OPCODE_INFO_MAX_ADDR_SIZE 8 +/** + * struct hl_info_undefined_opcode_event - info about last undefined opcode error + * @timestamp: timestamp of the undefined opcode error + * @cb_addr_streams: CB addresses (per stream) that are currently exists in the PQ + * entiers. In case all streams array entries are + * filled with values, it means the execution was in Lower-CP. + * @cq_addr: the address of the current handled command buffer + * @cq_size: the size of the current handled command buffer + * @cb_addr_streams_len: num of streams - actual len of cb_addr_streams array. + * should be equal to 1 incase of undefined opcode + * in Upper-CP (specific stream) and equal to 4 incase + * of undefined opcode in Lower-CP. + * @engine_id: engine-id that the error occurred on + * @stream_id: the stream id the error occurred on. In case the stream equals to + * MAX_QMAN_STREAMS_INFO it means the error occurred on a Lower-CP. + */ +struct hl_info_undefined_opcode_event { + __s64 timestamp; + __u64 cb_addr_streams[MAX_QMAN_STREAMS_INFO][OPCODE_INFO_MAX_ADDR_SIZE]; + __u64 cq_addr; + __u32 cq_size; + __u32 cb_addr_streams_len; + __u32 engine_id; + __u32 stream_id; +}; + /** * struct hl_info_dev_memalloc_page_sizes - valid page sizes in device mem alloc information. * @page_order_bitmask: bitmap in which a set bit represents the order of the supported page size @@ -764,16 +1208,16 @@ union hl_cb_args { /* HL_CS_CHUNK_FLAGS_ values * * HL_CS_CHUNK_FLAGS_USER_ALLOC_CB: - * Indicates if the CB was allocated and mapped by userspace. - * User allocated CB is a command buffer allocated by the user, via malloc - * (or similar). After allocating the CB, the user invokes “memory ioctl” - * to map the user memory into a device virtual address. The user provides - * this address via the cb_handle field. The interface provides the - * ability to create a large CBs, Which aren’t limited to - * “HL_MAX_CB_SIZE”. Therefore, it increases the PCI-DMA queues - * throughput. This CB allocation method also reduces the use of Linux - * DMA-able memory pool. Which are limited and used by other Linux - * sub-systems. + * Indicates if the CB was allocated and mapped by userspace + * (relevant to greco and above). User allocated CB is a command buffer, + * allocated by the user, via malloc (or similar). After allocating the + * CB, the user invokes - “memory ioctl” to map the user memory into a + * device virtual address. The user provides this address via the + * cb_handle field. The interface provides the ability to create a + * large CBs, Which aren’t limited to “HL_MAX_CB_SIZE”. Therefore, it + * increases the PCI-DMA queues throughput. This CB allocation method + * also reduces the use of Linux DMA-able memory pool. Which are limited + * and used by other Linux sub-systems. */ #define HL_CS_CHUNK_FLAGS_USER_ALLOC_CB 0x1 @@ -783,12 +1227,17 @@ union hl_cb_args { */ struct hl_cs_chunk { union { - /* For external queue, this represents a Handle of CB on the + /* Goya/Gaudi: + * For external queue, this represents a Handle of CB on the * Host. * For internal queue in Goya, this represents an SRAM or * a DRAM address of the internal CB. In Gaudi, this might also * represent a mapped host address of the CB. * + * Greco onwards: + * For H/W queue, this represents either a Handle of CB on the + * Host, or an SRAM, a DRAM, or a mapped host address of the CB. + * * A mapped host address is in the device address space, after * a host address was mapped by the device MMU. */ @@ -853,11 +1302,12 @@ struct hl_cs_chunk { __u32 pad[10]; }; -/* SIGNAL and WAIT/COLLECTIVE_WAIT flags are mutually exclusive */ +/* SIGNAL/WAIT/COLLECTIVE_WAIT flags are mutually exclusive */ #define HL_CS_FLAGS_FORCE_RESTORE 0x1 #define HL_CS_FLAGS_SIGNAL 0x2 #define HL_CS_FLAGS_WAIT 0x4 #define HL_CS_FLAGS_COLLECTIVE_WAIT 0x8 + #define HL_CS_FLAGS_TIMESTAMP 0x20 #define HL_CS_FLAGS_STAGED_SUBMISSION 0x40 #define HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 0x80 @@ -949,6 +1399,7 @@ struct hl_cs_in { /* Context ID - Currently not in use */ __u32 ctx_id; + __u8 pad[4]; }; struct hl_cs_out { @@ -994,6 +1445,8 @@ union hl_cs_args { #define HL_WAIT_CS_FLAGS_INTERRUPT 0x2 #define HL_WAIT_CS_FLAGS_INTERRUPT_MASK 0xFFF00000 +#define HL_WAIT_CS_FLAGS_ANY_CQ_INTERRUPT 0xFFF00000 +#define HL_WAIT_CS_FLAGS_ANY_DEC_INTERRUPT 0xFFE00000 #define HL_WAIT_CS_FLAGS_MULTI_CS 0x4 #define HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ 0x10 #define HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT 0x20 @@ -1043,8 +1496,13 @@ struct hl_wait_cs_in { /* HL_WAIT_CS_FLAGS_* * If HL_WAIT_CS_FLAGS_INTERRUPT is set, this field should include - * interrupt id according to HL_WAIT_CS_FLAGS_INTERRUPT_MASK, in order - * not to specify an interrupt id ,set mask to all 1s. + * interrupt id according to HL_WAIT_CS_FLAGS_INTERRUPT_MASK + * + * in order to wait for any CQ interrupt, set interrupt value to + * HL_WAIT_CS_FLAGS_ANY_CQ_INTERRUPT. + * + * in order to wait for any decoder interrupt, set interrupt value to + * HL_WAIT_CS_FLAGS_ANY_DEC_INTERRUPT. */ __u32 flags; @@ -1116,14 +1574,19 @@ union hl_wait_cs_args { /* Opcode to allocate device memory */ #define HL_MEM_OP_ALLOC 0 + /* Opcode to free previously allocated device memory */ #define HL_MEM_OP_FREE 1 + /* Opcode to map host and device memory */ #define HL_MEM_OP_MAP 2 + /* Opcode to unmap previously mapped host and device memory */ #define HL_MEM_OP_UNMAP 3 + /* Opcode to map a hw block */ #define HL_MEM_OP_MAP_BLOCK 4 + /* Opcode to create DMA-BUF object for an existing device memory allocation * and to export an FD of that DMA-BUF back to the caller */ @@ -1342,7 +1805,16 @@ struct hl_debug_params_bmon { /* Trace source ID */ __u32 id; - __u32 pad; + + /* Control register */ + __u32 control; + + /* Two more address ranges that the user can request to filter */ + __u64 start_addr2; + __u64 end_addr2; + + __u64 start_addr3; + __u64 end_addr3; }; struct hl_debug_params_spmu { @@ -1351,7 +1823,11 @@ struct hl_debug_params_spmu { /* Number of event types selection */ __u32 event_types_num; - __u32 pad; + + /* TRC configuration register values */ + __u32 pmtrc_val; + __u32 trc_ctrl_host_val; + __u32 trc_en_host_val; }; /* Opcode for ETR component */ @@ -1401,9 +1877,17 @@ struct hl_debug_args { /* * Notifier event values - for the notification mechanism and the HL_INFO_GET_EVENTS command * - * HL_NOTIFIER_EVENT_TPC_ASSERT - Indicates TPC assert event + * HL_NOTIFIER_EVENT_TPC_ASSERT - Indicates TPC assert event + * HL_NOTIFIER_EVENT_UNDEFINED_OPCODE - Indicates undefined operation code + * HL_NOTIFIER_EVENT_DEVICE_RESET - Indicates device requires a reset + * HL_NOTIFIER_EVENT_CS_TIMEOUT - Indicates CS timeout error + * HL_NOTIFIER_EVENT_DEVICE_UNAVAILABLE - Indicates device is unavailable */ -#define HL_NOTIFIER_EVENT_TPC_ASSERT (1 << 0) +#define HL_NOTIFIER_EVENT_TPC_ASSERT (1ULL << 0) +#define HL_NOTIFIER_EVENT_UNDEFINED_OPCODE (1ULL << 1) +#define HL_NOTIFIER_EVENT_DEVICE_RESET (1ULL << 2) +#define HL_NOTIFIER_EVENT_CS_TIMEOUT (1ULL << 3) +#define HL_NOTIFIER_EVENT_DEVICE_UNAVAILABLE (1ULL << 4) /* * Various information operations such as: @@ -1458,16 +1942,23 @@ struct hl_debug_args { * (or if its the first CS for this context). The user can also order the * driver to run the "restore" phase explicitly * + * Goya/Gaudi: * There are two types of queues - external and internal. External queues * are DMA queues which transfer data from/to the Host. All other queues are * internal. The driver will get completion notifications from the device only * on JOBS which are enqueued in the external queues. * + * Greco onwards: + * There is a single type of queue for all types of engines, either DMA engines + * for transfers from/to the host or inside the device, or compute engines. + * The driver will get completion notifications from the device for all queues. + * * For jobs on external queues, the user needs to create command buffers * through the CB ioctl and give the CB's handle to the CS ioctl. For jobs on * internal queues, the user needs to prepare a "command buffer" with packets * on either the device SRAM/DRAM or the host, and give the device address of * that buffer to the CS ioctl. + * For jobs on H/W queues both options of command buffers are valid. * * This IOCTL is asynchronous in regard to the actual execution of the CS. This * means it returns immediately after ALL the JOBS were enqueued on their @@ -1476,7 +1967,7 @@ struct hl_debug_args { * * Upon successful enqueue, the IOCTL returns a sequence number which the user * can use with the "Wait for CS" IOCTL to check whether the handle's CS - * external JOBS have been completed. Note that if the CS has internal JOBS + * non-internal JOBS have been completed. Note that if the CS has internal JOBS * which can execute AFTER the external JOBS have finished, the driver might * report that the CS has finished executing BEFORE the internal JOBS have * actually finished executing. diff --git a/kernel/configs/android-base.config b/kernel/configs/android-base.config index eb701b2ac72f..44b0f0146a3f 100644 --- a/kernel/configs/android-base.config +++ b/kernel/configs/android-base.config @@ -7,7 +7,6 @@ # CONFIG_OABI_COMPAT is not set # CONFIG_SYSVIPC is not set # CONFIG_USELIB is not set -CONFIG_ANDROID=y CONFIG_ANDROID_BINDER_IPC=y CONFIG_ANDROID_BINDER_DEVICES=binder,hwbinder,vndbinder CONFIG_ANDROID_LOW_MEMORY_KILLER=y diff --git a/kernel/power/Kconfig b/kernel/power/Kconfig index a12779650f15..60a1d3051cc7 100644 --- a/kernel/power/Kconfig +++ b/kernel/power/Kconfig @@ -143,6 +143,26 @@ config PM_AUTOSLEEP Allow the kernel to trigger a system transition into a global sleep state automatically whenever there are no active wakeup sources. +config PM_USERSPACE_AUTOSLEEP + bool "Userspace opportunistic sleep" + depends on PM_SLEEP + help + Notify kernel of aggressive userspace autosleep power management policy. + + This option changes the behavior of various sleep-sensitive code to deal + with frequent userspace-initiated transitions into a global sleep state. + + Saying Y here, disables code paths that most users really should keep + enabled. In particular, only enable this if it is very common to be + asleep/awake for very short periods of time (<= 2 seconds). + + Only platforms, such as Android, that implement opportunistic sleep from + a userspace power manager service should enable this option; and not + other machines. Therefore, you should say N here, unless you are + extremely certain that this is what you want. The option otherwise has + bad, undesirable effects, and should not be enabled just for fun. + + config PM_WAKELOCKS bool "User space wakeup sources interface" depends on PM_SLEEP diff --git a/kernel/rcu/Kconfig.debug b/kernel/rcu/Kconfig.debug index 4da05beb13d7..1b0c41d490f0 100644 --- a/kernel/rcu/Kconfig.debug +++ b/kernel/rcu/Kconfig.debug @@ -86,8 +86,7 @@ config RCU_EXP_CPU_STALL_TIMEOUT int "Expedited RCU CPU stall timeout in milliseconds" depends on RCU_STALL_COMMON range 0 21000 - default 20 if ANDROID - default 0 if !ANDROID + default 0 help If a given expedited RCU grace period extends more than the specified number of milliseconds, a CPU stall warning is printed. diff --git a/scripts/tags.sh b/scripts/tags.sh index 01fab3d4f90b..e137cf15aae9 100755 --- a/scripts/tags.sh +++ b/scripts/tags.sh @@ -25,13 +25,6 @@ else tree=${srctree}/ fi -# ignore userspace tools -if [ -n "$COMPILED_SOURCE" ]; then - ignore="$ignore ( -path ./tools ) -prune -o" -else - ignore="$ignore ( -path ${tree}tools ) -prune -o" -fi - # Detect if ALLSOURCE_ARCHS is set. If not, we assume SRCARCH if [ "${ALLSOURCE_ARCHS}" = "" ]; then ALLSOURCE_ARCHS=${SRCARCH} @@ -100,7 +93,7 @@ all_compiled_sources() find $ignore -name "*.cmd" -exec \ grep -Poh '(?(?=^source_.* \K).*|(?=^ \K\S).*(?= \\))' {} \+ | awk '!a[$0]++' - } | xargs realpath -es $([ -z "$KBUILD_ABS_SRCTREE" ] && echo --relative-to=.) | + } | xargs realpath -esq $([ -z "$KBUILD_ABS_SRCTREE" ] && echo --relative-to=.) | sort -u } diff --git a/tools/testing/selftests/filesystems/binderfs/config b/tools/testing/selftests/filesystems/binderfs/config index 02dd6cc9cf99..7b4fc6ee6205 100644 --- a/tools/testing/selftests/filesystems/binderfs/config +++ b/tools/testing/selftests/filesystems/binderfs/config @@ -1,3 +1,2 @@ -CONFIG_ANDROID=y CONFIG_ANDROID_BINDERFS=y CONFIG_ANDROID_BINDER_IPC=y diff --git a/tools/testing/selftests/sync/config b/tools/testing/selftests/sync/config index 47ff5afc3727..64c60f38b446 100644 --- a/tools/testing/selftests/sync/config +++ b/tools/testing/selftests/sync/config @@ -1,3 +1,2 @@ CONFIG_STAGING=y -CONFIG_ANDROID=y CONFIG_SW_SYNC=y