drm/panfrost: Really power off GPU cores in panfrost_gpu_power_off()
The layout of the registers {TILER,SHADER,L2}_PWROFF_LO, used to request powering off cores, is the same as the {TILER,SHADER,L2}_PWRON_LO ones: this means that in order to request poweroff of cores, we are supposed to write a bitmask of cores that should be powered off! This means that the panfrost_gpu_power_off() function has always been doing nothing. Fix powering off the GPU by writing a bitmask of the cores to poweroff to the relevant PWROFF_LO registers and then check that the transition (from ON to OFF) has finished by polling the relevant PWRTRANS_LO registers. While at it, in order to avoid code duplication, move the core mask logic from panfrost_gpu_power_on() to a new panfrost_get_core_mask() function, used in both poweron and poweroff. Fixes: f3ba91228e8e ("drm/panfrost: Add initial panfrost driver") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Steven Price <steven.price@arm.com> Signed-off-by: Steven Price <steven.price@arm.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231102141507.73481-1-angelogioacchino.delregno@collabora.com
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@ -362,28 +362,38 @@ unsigned long long panfrost_cycle_counter_read(struct panfrost_device *pfdev)
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return ((u64)hi << 32) | lo;
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}
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static u64 panfrost_get_core_mask(struct panfrost_device *pfdev)
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{
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u64 core_mask;
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if (pfdev->features.l2_present == 1)
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return U64_MAX;
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/*
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* Only support one core group now.
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* ~(l2_present - 1) unsets all bits in l2_present except
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* the bottom bit. (l2_present - 2) has all the bits in
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* the first core group set. AND them together to generate
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* a mask of cores in the first core group.
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*/
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core_mask = ~(pfdev->features.l2_present - 1) &
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(pfdev->features.l2_present - 2);
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dev_info_once(pfdev->dev, "using only 1st core group (%lu cores from %lu)\n",
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hweight64(core_mask),
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hweight64(pfdev->features.shader_present));
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return core_mask;
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}
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void panfrost_gpu_power_on(struct panfrost_device *pfdev)
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{
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int ret;
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u32 val;
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u64 core_mask = U64_MAX;
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u64 core_mask;
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panfrost_gpu_init_quirks(pfdev);
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core_mask = panfrost_get_core_mask(pfdev);
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if (pfdev->features.l2_present != 1) {
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/*
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* Only support one core group now.
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* ~(l2_present - 1) unsets all bits in l2_present except
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* the bottom bit. (l2_present - 2) has all the bits in
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* the first core group set. AND them together to generate
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* a mask of cores in the first core group.
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*/
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core_mask = ~(pfdev->features.l2_present - 1) &
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(pfdev->features.l2_present - 2);
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dev_info_once(pfdev->dev, "using only 1st core group (%lu cores from %lu)\n",
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hweight64(core_mask),
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hweight64(pfdev->features.shader_present));
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}
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gpu_write(pfdev, L2_PWRON_LO, pfdev->features.l2_present & core_mask);
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ret = readl_relaxed_poll_timeout(pfdev->iomem + L2_READY_LO,
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val, val == (pfdev->features.l2_present & core_mask),
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@ -408,9 +418,27 @@ void panfrost_gpu_power_on(struct panfrost_device *pfdev)
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void panfrost_gpu_power_off(struct panfrost_device *pfdev)
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{
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gpu_write(pfdev, TILER_PWROFF_LO, 0);
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gpu_write(pfdev, SHADER_PWROFF_LO, 0);
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gpu_write(pfdev, L2_PWROFF_LO, 0);
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u64 core_mask = panfrost_get_core_mask(pfdev);
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int ret;
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u32 val;
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gpu_write(pfdev, SHADER_PWROFF_LO, pfdev->features.shader_present & core_mask);
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ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_PWRTRANS_LO,
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val, !val, 1, 1000);
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if (ret)
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dev_err(pfdev->dev, "shader power transition timeout");
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gpu_write(pfdev, TILER_PWROFF_LO, pfdev->features.tiler_present);
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ret = readl_relaxed_poll_timeout(pfdev->iomem + TILER_PWRTRANS_LO,
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val, !val, 1, 1000);
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if (ret)
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dev_err(pfdev->dev, "tiler power transition timeout");
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gpu_write(pfdev, L2_PWROFF_LO, pfdev->features.l2_present & core_mask);
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ret = readl_poll_timeout(pfdev->iomem + L2_PWRTRANS_LO,
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val, !val, 0, 1000);
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if (ret)
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dev_err(pfdev->dev, "l2 power transition timeout");
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}
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int panfrost_gpu_init(struct panfrost_device *pfdev)
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