drm/amd/display: add DCN351 IRQ changes
Add DCN3.5.1 interrupt support. Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hamza Mahfooz
Alex Deucher
parent
ebb20fc19a
commit
22b66700f6
@ -170,4 +170,13 @@ IRQ_DCN35 = irq_service_dcn35.o
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AMD_DAL_IRQ_DCN35= $(addprefix $(AMDDALPATH)/dc/irq/dcn35/,$(IRQ_DCN35))
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AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN35)
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AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN35)
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###############################################################################
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# DCN 351
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###############################################################################
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IRQ_DCN351 = irq_service_dcn351.o
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AMD_DAL_IRQ_DCN351= $(addprefix $(AMDDALPATH)/dc/irq/dcn351/,$(IRQ_DCN351))
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AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN351)
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409
drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
Normal file
409
drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
Normal file
@ -0,0 +1,409 @@
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/* SPDX-License-Identifier: MIT */
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/* Copyright 2024 Advanced Micro Devices, Inc. */
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#include "dm_services.h"
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#include "include/logger_interface.h"
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#include "../dce110/irq_service_dce110.h"
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#include "dcn/dcn_3_5_1_offset.h"
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#include "dcn/dcn_3_5_1_sh_mask.h"
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#include "irq_service_dcn351.h"
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#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
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static enum dc_irq_source to_dal_irq_source_dcn351(
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struct irq_service *irq_service,
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uint32_t src_id,
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uint32_t ext_id)
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{
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switch (src_id) {
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case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
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return DC_IRQ_SOURCE_VBLANK1;
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case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
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return DC_IRQ_SOURCE_VBLANK2;
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case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
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return DC_IRQ_SOURCE_VBLANK3;
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case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
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return DC_IRQ_SOURCE_VBLANK4;
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case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
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return DC_IRQ_SOURCE_VBLANK5;
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case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
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return DC_IRQ_SOURCE_VBLANK6;
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case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
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return DC_IRQ_SOURCE_DC1_VLINE0;
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case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
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return DC_IRQ_SOURCE_DC2_VLINE0;
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case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
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return DC_IRQ_SOURCE_DC3_VLINE0;
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case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
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return DC_IRQ_SOURCE_DC4_VLINE0;
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case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
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return DC_IRQ_SOURCE_DC5_VLINE0;
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case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
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return DC_IRQ_SOURCE_DC6_VLINE0;
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case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
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return DC_IRQ_SOURCE_PFLIP1;
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case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
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return DC_IRQ_SOURCE_PFLIP2;
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case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
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return DC_IRQ_SOURCE_PFLIP3;
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case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
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return DC_IRQ_SOURCE_PFLIP4;
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case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
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return DC_IRQ_SOURCE_PFLIP5;
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case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
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return DC_IRQ_SOURCE_PFLIP6;
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case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
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return DC_IRQ_SOURCE_VUPDATE1;
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case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
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return DC_IRQ_SOURCE_VUPDATE2;
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case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
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return DC_IRQ_SOURCE_VUPDATE3;
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case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
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return DC_IRQ_SOURCE_VUPDATE4;
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case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
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return DC_IRQ_SOURCE_VUPDATE5;
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case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
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return DC_IRQ_SOURCE_VUPDATE6;
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case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
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return DC_IRQ_SOURCE_DMCUB_OUTBOX;
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case DCN_1_0__SRCID__DC_HPD1_INT:
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/* generic src_id for all HPD and HPDRX interrupts */
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switch (ext_id) {
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case DCN_1_0__CTXID__DC_HPD1_INT:
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return DC_IRQ_SOURCE_HPD1;
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case DCN_1_0__CTXID__DC_HPD2_INT:
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return DC_IRQ_SOURCE_HPD2;
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case DCN_1_0__CTXID__DC_HPD3_INT:
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return DC_IRQ_SOURCE_HPD3;
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case DCN_1_0__CTXID__DC_HPD4_INT:
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return DC_IRQ_SOURCE_HPD4;
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case DCN_1_0__CTXID__DC_HPD5_INT:
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return DC_IRQ_SOURCE_HPD5;
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case DCN_1_0__CTXID__DC_HPD6_INT:
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return DC_IRQ_SOURCE_HPD6;
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case DCN_1_0__CTXID__DC_HPD1_RX_INT:
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return DC_IRQ_SOURCE_HPD1RX;
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case DCN_1_0__CTXID__DC_HPD2_RX_INT:
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return DC_IRQ_SOURCE_HPD2RX;
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case DCN_1_0__CTXID__DC_HPD3_RX_INT:
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return DC_IRQ_SOURCE_HPD3RX;
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case DCN_1_0__CTXID__DC_HPD4_RX_INT:
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return DC_IRQ_SOURCE_HPD4RX;
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case DCN_1_0__CTXID__DC_HPD5_RX_INT:
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return DC_IRQ_SOURCE_HPD5RX;
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case DCN_1_0__CTXID__DC_HPD6_RX_INT:
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return DC_IRQ_SOURCE_HPD6RX;
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default:
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return DC_IRQ_SOURCE_INVALID;
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}
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break;
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default:
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return DC_IRQ_SOURCE_INVALID;
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}
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}
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static bool hpd_ack(
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struct irq_service *irq_service,
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const struct irq_source_info *info)
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{
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uint32_t addr = info->status_reg;
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uint32_t value = dm_read_reg(irq_service->ctx, addr);
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uint32_t current_status =
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get_reg_field_value(
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value,
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HPD0_DC_HPD_INT_STATUS,
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DC_HPD_SENSE_DELAYED);
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dal_irq_service_ack_generic(irq_service, info);
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value = dm_read_reg(irq_service->ctx, info->enable_reg);
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set_reg_field_value(
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value,
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current_status ? 0 : 1,
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HPD0_DC_HPD_INT_CONTROL,
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DC_HPD_INT_POLARITY);
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dm_write_reg(irq_service->ctx, info->enable_reg, value);
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return true;
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}
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static struct irq_source_info_funcs hpd_irq_info_funcs = {
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.set = NULL,
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.ack = hpd_ack
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};
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static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
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.set = NULL,
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.ack = NULL
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};
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static struct irq_source_info_funcs pflip_irq_info_funcs = {
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.set = NULL,
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.ack = NULL
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};
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static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
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.set = NULL,
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.ack = NULL
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};
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static struct irq_source_info_funcs vblank_irq_info_funcs = {
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.set = NULL,
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.ack = NULL
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};
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static struct irq_source_info_funcs outbox_irq_info_funcs = {
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.set = NULL,
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.ack = NULL
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};
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static struct irq_source_info_funcs vline0_irq_info_funcs = {
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.set = NULL,
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.ack = NULL
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};
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#undef BASE_INNER
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#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
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/* compile time expand base address. */
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#define BASE(seg) \
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BASE_INNER(seg)
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#define SRI(reg_name, block, id)\
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BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
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reg ## block ## id ## _ ## reg_name
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#define SRI_DMUB(reg_name)\
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BASE(reg ## reg_name ## _BASE_IDX) + \
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reg ## reg_name
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#define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\
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REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
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REG_STRUCT[base + reg_num].enable_mask = \
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block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
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REG_STRUCT[base + reg_num].enable_value[0] = \
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block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
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REG_STRUCT[base + reg_num].enable_value[1] = \
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~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
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REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
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REG_STRUCT[base + reg_num].ack_mask = \
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block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
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REG_STRUCT[base + reg_num].ack_value = \
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block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
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#define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\
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REG_STRUCT[base].enable_reg = SRI_DMUB(reg1),\
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REG_STRUCT[base].enable_mask = \
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reg1 ## __ ## mask1 ## _MASK,\
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REG_STRUCT[base].enable_value[0] = \
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reg1 ## __ ## mask1 ## _MASK,\
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REG_STRUCT[base].enable_value[1] = \
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~reg1 ## __ ## mask1 ## _MASK, \
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REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\
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REG_STRUCT[base].ack_mask = \
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reg2 ## __ ## mask2 ## _MASK,\
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REG_STRUCT[base].ack_value = \
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reg2 ## __ ## mask2 ## _MASK \
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#define hpd_int_entry(reg_num)\
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IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1, HPD, reg_num,\
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DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
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DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
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REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].funcs = &hpd_irq_info_funcs;\
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REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\
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#define hpd_rx_int_entry(reg_num)\
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IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1RX, HPD, reg_num,\
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DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
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DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
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REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\
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REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].funcs = &hpd_rx_irq_info_funcs;\
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#define pflip_int_entry(reg_num)\
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IRQ_REG_ENTRY(DC_IRQ_SOURCE_PFLIP1, HUBPREQ, reg_num,\
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DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
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DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
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REG_STRUCT[DC_IRQ_SOURCE_PFLIP1 + reg_num].funcs = &pflip_irq_info_funcs\
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/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
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* of DCE's DC_IRQ_SOURCE_VUPDATEx.
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*/
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#define vupdate_no_lock_int_entry(reg_num)\
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IRQ_REG_ENTRY(DC_IRQ_SOURCE_VUPDATE1, OTG, reg_num,\
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OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
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OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
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REG_STRUCT[DC_IRQ_SOURCE_VUPDATE1 + reg_num].funcs = &vupdate_no_lock_irq_info_funcs\
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#define vblank_int_entry(reg_num)\
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IRQ_REG_ENTRY(DC_IRQ_SOURCE_VBLANK1, OTG, reg_num,\
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OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
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OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
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REG_STRUCT[DC_IRQ_SOURCE_VBLANK1 + reg_num].funcs = &vblank_irq_info_funcs\
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#define vline0_int_entry(reg_num)\
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IRQ_REG_ENTRY(DC_IRQ_SOURCE_DC1_VLINE0, OTG, reg_num,\
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OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
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OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
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REG_STRUCT[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num].funcs = &vline0_irq_info_funcs\
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#define dmub_outbox_int_entry()\
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IRQ_REG_ENTRY_DMUB(DC_IRQ_SOURCE_DMCUB_OUTBOX, \
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DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
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DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
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REG_STRUCT[DC_IRQ_SOURCE_DMCUB_OUTBOX].funcs = &outbox_irq_info_funcs
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#define dummy_irq_entry(irqno) \
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REG_STRUCT[irqno].funcs = &dummy_irq_info_funcs\
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#define i2c_int_entry(reg_num) \
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dummy_irq_entry(DC_IRQ_SOURCE_I2C_DDC ## reg_num)
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#define dp_sink_int_entry(reg_num) \
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dummy_irq_entry(DC_IRQ_SOURCE_DPSINK ## reg_num)
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#define gpio_pad_int_entry(reg_num) \
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dummy_irq_entry(DC_IRQ_SOURCE_GPIOPAD ## reg_num)
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#define dc_underflow_int_entry(reg_num) \
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dummy_irq_entry(DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW)
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static struct irq_source_info_funcs dummy_irq_info_funcs = {
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.set = dal_irq_service_dummy_set,
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.ack = dal_irq_service_dummy_ack
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};
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#define dcn351_irq_init_part_1() {\
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dummy_irq_entry(DC_IRQ_SOURCE_INVALID); \
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hpd_int_entry(0); \
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hpd_int_entry(1); \
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hpd_int_entry(2); \
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hpd_int_entry(3); \
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hpd_int_entry(4); \
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hpd_rx_int_entry(0); \
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hpd_rx_int_entry(1); \
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hpd_rx_int_entry(2); \
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hpd_rx_int_entry(3); \
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hpd_rx_int_entry(4); \
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i2c_int_entry(1); \
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i2c_int_entry(2); \
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i2c_int_entry(3); \
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i2c_int_entry(4); \
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i2c_int_entry(5); \
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i2c_int_entry(6); \
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dp_sink_int_entry(1); \
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dp_sink_int_entry(2); \
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dp_sink_int_entry(3); \
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dp_sink_int_entry(4); \
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dp_sink_int_entry(5); \
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dp_sink_int_entry(6); \
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dummy_irq_entry(DC_IRQ_SOURCE_TIMER); \
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pflip_int_entry(0); \
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pflip_int_entry(1); \
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pflip_int_entry(2); \
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pflip_int_entry(3); \
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dummy_irq_entry(DC_IRQ_SOURCE_PFLIP5); \
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dummy_irq_entry(DC_IRQ_SOURCE_PFLIP6); \
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dummy_irq_entry(DC_IRQ_SOURCE_PFLIP_UNDERLAY0); \
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gpio_pad_int_entry(0); \
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gpio_pad_int_entry(1); \
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gpio_pad_int_entry(2); \
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gpio_pad_int_entry(3); \
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gpio_pad_int_entry(4); \
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gpio_pad_int_entry(5); \
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gpio_pad_int_entry(6); \
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gpio_pad_int_entry(7); \
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gpio_pad_int_entry(8); \
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gpio_pad_int_entry(9); \
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gpio_pad_int_entry(10); \
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gpio_pad_int_entry(11); \
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gpio_pad_int_entry(12); \
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gpio_pad_int_entry(13); \
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gpio_pad_int_entry(14); \
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gpio_pad_int_entry(15); \
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gpio_pad_int_entry(16); \
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gpio_pad_int_entry(17); \
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gpio_pad_int_entry(18); \
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gpio_pad_int_entry(19); \
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gpio_pad_int_entry(20); \
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gpio_pad_int_entry(21); \
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gpio_pad_int_entry(22); \
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gpio_pad_int_entry(23); \
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gpio_pad_int_entry(24); \
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gpio_pad_int_entry(25); \
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gpio_pad_int_entry(26); \
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gpio_pad_int_entry(27); \
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gpio_pad_int_entry(28); \
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gpio_pad_int_entry(29); \
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gpio_pad_int_entry(30); \
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dc_underflow_int_entry(1); \
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dc_underflow_int_entry(2); \
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dc_underflow_int_entry(3); \
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dc_underflow_int_entry(4); \
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dc_underflow_int_entry(5); \
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dc_underflow_int_entry(6); \
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dummy_irq_entry(DC_IRQ_SOURCE_DMCU_SCP); \
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dummy_irq_entry(DC_IRQ_SOURCE_VBIOS_SW); \
|
||||
}
|
||||
|
||||
#define dcn351_irq_init_part_2() {\
|
||||
vupdate_no_lock_int_entry(0); \
|
||||
vupdate_no_lock_int_entry(1); \
|
||||
vupdate_no_lock_int_entry(2); \
|
||||
vupdate_no_lock_int_entry(3); \
|
||||
vblank_int_entry(0); \
|
||||
vblank_int_entry(1); \
|
||||
vblank_int_entry(2); \
|
||||
vblank_int_entry(3); \
|
||||
vline0_int_entry(0); \
|
||||
vline0_int_entry(1); \
|
||||
vline0_int_entry(2); \
|
||||
vline0_int_entry(3); \
|
||||
dummy_irq_entry(DC_IRQ_SOURCE_DC5_VLINE1); \
|
||||
dummy_irq_entry(DC_IRQ_SOURCE_DC6_VLINE1); \
|
||||
dmub_outbox_int_entry(); \
|
||||
}
|
||||
|
||||
#define dcn351_irq_init() {\
|
||||
dcn351_irq_init_part_1(); \
|
||||
dcn351_irq_init_part_2(); \
|
||||
}
|
||||
|
||||
static struct irq_source_info irq_source_info_dcn351[DAL_IRQ_SOURCES_NUMBER] = {0};
|
||||
|
||||
static struct irq_service_funcs irq_service_funcs_dcn351 = {
|
||||
.to_dal_irq_source = to_dal_irq_source_dcn351
|
||||
};
|
||||
|
||||
static void dcn351_irq_construct(
|
||||
struct irq_service *irq_service,
|
||||
struct irq_service_init_data *init_data)
|
||||
{
|
||||
struct dc_context *ctx = init_data->ctx;
|
||||
|
||||
#define REG_STRUCT irq_source_info_dcn351
|
||||
dcn351_irq_init();
|
||||
|
||||
dal_irq_service_construct(irq_service, init_data);
|
||||
|
||||
irq_service->info = irq_source_info_dcn351;
|
||||
irq_service->funcs = &irq_service_funcs_dcn351;
|
||||
}
|
||||
|
||||
struct irq_service *dal_irq_service_dcn351_create(
|
||||
struct irq_service_init_data *init_data)
|
||||
{
|
||||
struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
|
||||
GFP_KERNEL);
|
||||
|
||||
if (!irq_service)
|
||||
return NULL;
|
||||
|
||||
dcn351_irq_construct(irq_service, init_data);
|
||||
return irq_service;
|
||||
}
|
||||
@ -0,0 +1,12 @@
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
/* Copyright 2021 Advanced Micro Devices, Inc. */
|
||||
|
||||
#ifndef __DAL_IRQ_SERVICE_DCN351_H__
|
||||
#define __DAL_IRQ_SERVICE_DCN351_H__
|
||||
|
||||
#include "../irq_service.h"
|
||||
|
||||
struct irq_service *dal_irq_service_dcn351_create(
|
||||
struct irq_service_init_data *init_data);
|
||||
|
||||
#endif /* __DAL_IRQ_SERVICE_DCN351_H__ */
|
||||
Loading…
x
Reference in New Issue
Block a user