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spi: cadence-quadspi: Update the read timeout based on the length

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When performing indirect read via external DMA the timeout for
completion is set equal to the read length instead of fixed timeout value.
For reads larger than 500 bytes, the timeout will continue to be
equal to the read length whereas for a small read like the Read Status
Register command, the timeout would be 1 or 2 milliseconds. This is not
enough to cover the overhead needed in setting up DMA, in that case make
sure the timeout is at least 500ms to allow DMA to finish. This solution
is inline with the timeout used for Direct read via DMA.

Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Link: https://lore.kernel.org/r/20230320095931.2651714-2-sai.krishna.potthuri@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Sai Krishna Potthuri 2023-03-20 15:29:30 +05:30 committed by Mark Brown
parent 6d87552c0b
commit 22c8ce0aa2
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1 changed files with 1 additions and 1 deletions
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2
drivers/spi/spi-cadence-quadspi.c
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@ -863,7 +863,7 @@ static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata,
reinit_completion(&cqspi->transfer_complete);
if (!wait_for_completion_timeout(&cqspi->transfer_complete,
msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) {
msecs_to_jiffies(max_t(size_t, bytes_to_dma, 500)))) {
ret = -ETIMEDOUT;
goto failrd;
}