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clk: rockchip: Optimize PLL table memory usage

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Before the change: The sizeof rk3568_pll_rates = 2544
Use union: The sizeof rk3568_pll_rates = 1696

In future Soc, more PLL types will be added, and the
rockchip_pll_rate_table will add more members,
and the space savings will be even more pronounced
by using union.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Link: https://lore.kernel.org/r/20210511090726.15146-1-zhangqing@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Elaine Zhang 2021-05-11 17:07:26 +08:00 committed by Heiko Stuebner
parent 6efb943b86
commit 23029150a0
1 changed files with 18 additions and 11 deletions
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29
drivers/clk/rockchip/clk.h
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@ -271,17 +271,24 @@ struct rockchip_clk_provider {
struct rockchip_pll_rate_table {
unsigned long rate;
unsigned int nr;
unsigned int nf;
unsigned int no;
unsigned int nb;
/* for RK3036/RK3399 */
unsigned int fbdiv;
unsigned int postdiv1;
unsigned int refdiv;
unsigned int postdiv2;
unsigned int dsmpd;
unsigned int frac;
union {
struct {
/* for RK3066 */
unsigned int nr;
unsigned int nf;
unsigned int no;
unsigned int nb;
};
struct {
/* for RK3036/RK3399 */
unsigned int fbdiv;
unsigned int postdiv1;
unsigned int refdiv;
unsigned int postdiv2;
unsigned int dsmpd;
unsigned int frac;
};
};
};
/**