Qualcomm clock updates for v5.18
This introduces support for A7 PLL on SDX65, GPU clock controller for SM6350, display clock controller for SM6125, SM6350 and QCS2290 and multimedia clock controller for MSM8226. The RPMCC drivers get support for SC8280XP and MSM8992, MSM8994 and MSM8998 gains some missing clocks. A new gcc DeviceTree binding is introduced, to allow platform-specific GCC bindings to inherit common properties. The SDM845 camera clock controller binding is converted to YAML. SDM845 camera clock controller, SDM660 GPU clock controller, IPQ8074 global clock controller, IPQ806x global clock controller, SC7180 camera and video clock controllers, MSM8996 globacl clock controller are converted to parent_data and/or parent_hws and cleanups related to this. Test clocks are removed from the SC7180, SDM845 camera clock controller drivers and SDM660 GPU clock controller driver. IPQ806x gains clocks and resets for CryptoEngine and additional frequencies for SDCC and NSS cores. Floor ops are introduced for RCG clocks and used for IPQ8074 SDCC clocks. SM8150 gains EMAC, PCIe and UFS GDSCs. The RCG2 logic for calculating D value is updated to support pixel clock frequencies on newer platforms. -----BEGIN PGP SIGNATURE----- iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmIqzbMbHGJqb3JuLmFu ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3FYZUP/0eGVOIJ4ltbHZLwbKPK 4uKJSAMbDtF7BgZZNr0gBisNfOJcKh0Br4Z1uci5fI46anp7SgFKKOxaFzQDUmPR ZsFOTtDzjTBuN4Nh0w9nYgwTaabq8aFqCVChC5tw+3kHG29Xl3cw2Rg0OOBVDeCX kBaj44Ofvgblh8IrW5qfAWTNCBC0p/9ovawOS9/E/6LPfeDfLgO8TmmhNKhcOTZH Mef/AyJrfjC+vJZzSv6p0EjTQtGJdyu4Gh1VEeH5rCsKMDV5Iw5njPmXfi5KFwDI Enq4mg7qP+XIrSkjfnkf9qrREskw0c2UzWTtmbg2mVEKFLAoQkJN2dcGAroFmkUx tt23+2p8jrwSe+sClZUOxqRnImLhk0n3wEYkvHrstsqDHCqOCgLCVIZ2NJ7zr8b4 Cz+v2wsw6sRza+uKIXf1DLia//VCLjh8Gb6rGOtsU951VtAxheEzC3d/3YzJWtQA bMIycPcf6MCNFPWLADU0DM1BtMRM6Ro+Eov4X3KYG0+Q5mKPLI1cb4aOzgoPgBRT qGu+DgcThpNn398czAeuoGyr/a+AaJPqsX/Y+5ysYJ52HuS5oWpE6OzC2OwmGJKP 9YYL3RMbQDbVhT6OJjGQwCQu7//evcIqVv1J5d0hwyERK0dW/RjVL/alI5r+D81i RajOStmDHbnnu+OeenEsHRsF =KAJL -----END PGP SIGNATURE----- Merge tag 'qcom-clk-for-5.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom Pull Qualcomm clk driver updates from Bjorn Andersson: This introduces support for A7 PLL on SDX65, GPU clock controller for SM6350, display clock controller for SM6125, SM6350 and QCS2290 and multimedia clock controller for MSM8226. The RPMCC drivers get support for SC8280XP and MSM8992, MSM8994 and MSM8998 gains some missing clocks. A new gcc DeviceTree binding is introduced, to allow platform-specific GCC bindings to inherit common properties. The SDM845 camera clock controller binding is converted to YAML. SDM845 camera clock controller, SDM660 GPU clock controller, IPQ8074 global clock controller, IPQ806x global clock controller, SC7180 camera and video clock controllers, MSM8996 globacl clock controller are converted to parent_data and/or parent_hws and cleanups related to this. Test clocks are removed from the SC7180, SDM845 camera clock controller drivers and SDM660 GPU clock controller driver. IPQ806x gains clocks and resets for CryptoEngine and additional frequencies for SDCC and NSS cores. Floor ops are introduced for RCG clocks and used for IPQ8074 SDCC clocks. SM8150 gains EMAC, PCIe and UFS GDSCs. The RCG2 logic for calculating D value is updated to support pixel clock frequencies on newer platforms. * tag 'qcom-clk-for-5.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (59 commits) clk: qcom: Add display clock controller driver for SM6125 dt-bindings: clock: add QCOM SM6125 display clock bindings clk: qcom: Fix sorting of SDX_GCC_65 in Makefile and Kconfig clk: qcom: gcc: Add emac GDSC support for SM8150 clk: qcom: gcc: sm8150: Fix some identation issues clk: qcom: gcc: Add UFS_CARD and UFS_PHY GDSCs for SM8150 clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150 clk: qcom: clk-rcg2: Update the frac table for pixel clock clk: qcom: clk-rcg2: Update logic to calculate D value for RCG clk: qcom: smd: Add missing MSM8998 RPM clocks clk: qcom: smd: Add missing RPM clocks for msm8992/4 dt-bindings: clock: qcom: rpmcc: Add RPM Modem SubSystem (MSS) clocks clk: qcom: gcc-ipq806x: add CryptoEngine resets dt-bindings: reset: add ipq8064 ce5 resets clk: qcom: gcc-ipq806x: add CryptoEngine clocks dt-bindings: clock: add ipq8064 ce5 clk define clk: qcom: gcc-ipq806x: add additional freq for sdc table clk: qcom: clk-rcg: add clk_rcg_floor_ops ops clk: qcom: gcc-ipq806x: add unusued flag for critical clock clk: qcom: gcc-ipq806x: add additional freq nss cores ...
This commit is contained in:
Stephen Boyd
commit
234af44f33
@ -10,7 +10,7 @@ maintainers:
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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description:
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The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high
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The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high
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frequency clock to the CPU.
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properties:
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@ -1,18 +0,0 @@
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Qualcomm Camera Clock & Reset Controller Binding
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------------------------------------------------
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Required properties :
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- compatible : shall contain "qcom,sdm845-camcc".
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- reg : shall contain base register location and length.
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- #clock-cells : from common clock binding, shall contain 1.
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- #reset-cells : from common reset binding, shall contain 1.
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- #power-domain-cells : from generic power domain binding, shall contain 1.
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Example:
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camcc: clock-controller@ad00000 {
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compatible = "qcom,sdm845-camcc";
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reg = <0xad00000 0x10000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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@ -0,0 +1,87 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock Controller Binding for SM6125
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maintainers:
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- Martin Botka <martin.botka@somainline.org>
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description: |
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Qualcomm display clock control module which supports the clocks and
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power domains on SM6125.
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See also:
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dt-bindings/clock/qcom,dispcc-sm6125.h
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properties:
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compatible:
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enum:
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- qcom,sm6125-dispcc
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clocks:
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items:
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- description: Board XO source
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY0
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- description: Pixel clock from DSI PHY1
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- description: Link clock from DP PHY
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- description: VCO DIV clock from DP PHY
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- description: AHB config clock from GCC
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clock-names:
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items:
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- const: bi_tcxo
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- const: dsi0_phy_pll_out_byteclk
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- const: dsi0_phy_pll_out_dsiclk
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- const: dsi1_phy_pll_out_dsiclk
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- const: dp_phy_pll_link_clk
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- const: dp_phy_pll_vco_div_clk
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- const: cfg_ahb_clk
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'#clock-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/clock/qcom,gcc-sm6125.h>
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clock-controller@5f00000 {
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compatible = "qcom,sm6125-dispcc";
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reg = <0x5f00000 0x20000>;
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
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<&dsi0_phy 0>,
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<&dsi0_phy 1>,
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<&dsi1_phy 1>,
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<&dp_phy 0>,
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<&dp_phy 1>,
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<&gcc GCC_DISP_AHB_CLK>;
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clock-names = "bi_tcxo",
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"dsi0_phy_pll_out_byteclk",
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"dsi0_phy_pll_out_dsiclk",
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"dsi1_phy_pll_out_dsiclk",
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"dp_phy_pll_link_clk",
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"dp_phy_pll_vco_div_clk",
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"cfg_ahb_clk";
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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@ -0,0 +1,86 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6350.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller Binding for SM6350
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maintainers:
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- Konrad Dybcio <konrad.dybcio@somainline.org>
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description: |
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Qualcomm display clock control module which supports the clocks, resets and
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power domains on SM6350.
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See also dt-bindings/clock/qcom,dispcc-sm6350.h.
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properties:
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compatible:
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const: qcom,sm6350-dispcc
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clocks:
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items:
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- description: Board XO source
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- description: GPLL0 source from GCC
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- description: Byte clock from DSI PHY
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- description: Pixel clock from DSI PHY
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- description: Link clock from DP PHY
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- description: VCO DIV clock from DP PHY
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clock-names:
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items:
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- const: bi_tcxo
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- const: gcc_disp_gpll0_clk
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- const: dsi0_phy_pll_out_byteclk
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- const: dsi0_phy_pll_out_dsiclk
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- const: dp_phy_pll_link_clk
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- const: dp_phy_pll_vco_div_clk
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sm6350.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@af00000 {
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compatible = "qcom,sm6350-dispcc";
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reg = <0x0af00000 0x20000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_DISP_GPLL0_CLK>,
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<&dsi_phy 0>,
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<&dsi_phy 1>,
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<&dp_phy 0>,
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<&dp_phy 1>;
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clock-names = "bi_tcxo",
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"gcc_disp_gpll0_clk",
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"dsi0_phy_pll_out_byteclk",
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"dsi0_phy_pll_out_dsiclk",
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"dp_phy_pll_link_clk",
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"dp_phy_pll_vco_div_clk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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@ -6,6 +6,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller Binding for APQ8064
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allOf:
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- $ref: qcom,gcc.yaml#
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maintainers:
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- Stephen Boyd <sboyd@kernel.org>
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- Taniya Das <tdas@codeaurora.org>
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@ -17,22 +20,12 @@ description: |
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See also:
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- dt-bindings/clock/qcom,gcc-msm8960.h
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- dt-bindings/reset/qcom,gcc-msm8960.h
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- dt-bindings/clock/qcom,gcc-apq8084.h
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- dt-bindings/reset/qcom,gcc-apq8084.h
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properties:
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compatible:
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const: qcom,gcc-apq8064
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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const: qcom,gcc-apq8084
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nvmem-cells:
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minItems: 1
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@ -53,21 +46,13 @@ properties:
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'#thermal-sensor-cells':
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const: 1
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protected-clocks:
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description:
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Protected clock specifier list as per common clock binding.
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required:
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- compatible
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- reg
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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- nvmem-cells
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- nvmem-cell-names
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- '#thermal-sensor-cells'
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additionalProperties: false
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unevaluatedProperties: false
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examples:
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- |
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@ -0,0 +1,76 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064
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allOf:
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- $ref: qcom,gcc.yaml#
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maintainers:
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- Ansuel Smith <ansuelsmth@gmail.com>
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description: |
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Qualcomm global clock control module which supports the clocks, resets and
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power domains on IPQ8064.
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See also:
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- dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
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- dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
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properties:
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compatible:
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items:
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- const: qcom,gcc-ipq8064
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- const: syscon
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clocks:
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items:
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- description: PXO source
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- description: CXO source
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clock-names:
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items:
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- const: pxo
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- const: cxo
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thermal-sensor:
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type: object
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allOf:
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- $ref: /schemas/thermal/qcom-tsens.yaml#
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required:
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- compatible
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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gcc: clock-controller@900000 {
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compatible = "qcom,gcc-ipq8064", "syscon";
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reg = <0x00900000 0x4000>;
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clocks = <&pxo_board>, <&cxo_board>;
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clock-names = "pxo", "cxo";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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tsens: thermal-sensor {
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compatible = "qcom,ipq8064-tsens";
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nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
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nvmem-cell-names = "calib", "calib_backup";
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interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "uplow";
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#qcom,sensors = <11>;
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#thermal-sensor-cells = <1>;
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};
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};
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70
Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
Normal file
70
Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
Normal file
@ -0,0 +1,70 @@
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# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
|
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---
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$id: http://devicetree.org/schemas/clock/qcom,gcc-other.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
|
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|
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title: Qualcomm Global Clock & Reset Controller Binding
|
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|
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maintainers:
|
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- Stephen Boyd <sboyd@kernel.org>
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- Taniya Das <tdas@codeaurora.org>
|
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|
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description:
|
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Qualcomm global clock control module which supports the clocks, resets and
|
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power domains.
|
||||
|
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See also:
|
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- dt-bindings/clock/qcom,gcc-ipq4019.h
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- dt-bindings/clock/qcom,gcc-ipq6018.h
|
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- dt-bindings/reset/qcom,gcc-ipq6018.h
|
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- dt-bindings/clock/qcom,gcc-msm8939.h
|
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- dt-bindings/clock/qcom,gcc-msm8953.h
|
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- dt-bindings/reset/qcom,gcc-msm8939.h
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- dt-bindings/clock/qcom,gcc-msm8660.h
|
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- dt-bindings/reset/qcom,gcc-msm8660.h
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- dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
|
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- dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
|
||||
- dt-bindings/clock/qcom,gcc-mdm9607.h
|
||||
- dt-bindings/clock/qcom,gcc-mdm9615.h
|
||||
- dt-bindings/reset/qcom,gcc-mdm9615.h
|
||||
- dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
|
||||
|
||||
allOf:
|
||||
- $ref: "qcom,gcc.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,gcc-ipq4019
|
||||
- qcom,gcc-ipq6018
|
||||
- qcom,gcc-mdm9607
|
||||
- qcom,gcc-msm8226
|
||||
- qcom,gcc-msm8660
|
||||
- qcom,gcc-msm8916
|
||||
- qcom,gcc-msm8939
|
||||
- qcom,gcc-msm8953
|
||||
- qcom,gcc-msm8960
|
||||
- qcom,gcc-msm8974
|
||||
- qcom,gcc-msm8974pro
|
||||
- qcom,gcc-msm8974pro-ac
|
||||
- qcom,gcc-mdm9615
|
||||
- qcom,gcc-sdm630
|
||||
- qcom,gcc-sdm660
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
# Example for GCC for MSM8960:
|
||||
- |
|
||||
clock-controller@900000 {
|
||||
compatible = "qcom,gcc-msm8960";
|
||||
reg = <0x900000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -4,57 +4,17 @@
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding
|
||||
title: Qualcomm Global Clock & Reset Controller Binding Common Bindings
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-apq8084.h
|
||||
- dt-bindings/reset/qcom,gcc-apq8084.h
|
||||
- dt-bindings/clock/qcom,gcc-ipq4019.h
|
||||
- dt-bindings/clock/qcom,gcc-ipq6018.h
|
||||
- dt-bindings/reset/qcom,gcc-ipq6018.h
|
||||
- dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
|
||||
- dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
|
||||
- dt-bindings/clock/qcom,gcc-msm8939.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8953.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8939.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8660.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8660.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
|
||||
- dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
|
||||
- dt-bindings/clock/qcom,gcc-mdm9607.h
|
||||
- dt-bindings/clock/qcom,gcc-mdm9615.h
|
||||
- dt-bindings/reset/qcom,gcc-mdm9615.h
|
||||
- dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
|
||||
Common bindings for Qualcomm global clock control module which supports
|
||||
the clocks, resets and power domains.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,gcc-apq8084
|
||||
- qcom,gcc-ipq4019
|
||||
- qcom,gcc-ipq6018
|
||||
- qcom,gcc-ipq8064
|
||||
- qcom,gcc-mdm9607
|
||||
- qcom,gcc-msm8226
|
||||
- qcom,gcc-msm8660
|
||||
- qcom,gcc-msm8916
|
||||
- qcom,gcc-msm8939
|
||||
- qcom,gcc-msm8953
|
||||
- qcom,gcc-msm8960
|
||||
- qcom,gcc-msm8974
|
||||
- qcom,gcc-msm8974pro
|
||||
- qcom,gcc-msm8974pro-ac
|
||||
- qcom,gcc-mdm9615
|
||||
- qcom,gcc-sdm630
|
||||
- qcom,gcc-sdm660
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
@ -72,22 +32,11 @@ properties:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
additionalProperties: true
|
||||
|
||||
examples:
|
||||
# Example for GCC for MSM8960:
|
||||
- |
|
||||
clock-controller@900000 {
|
||||
compatible = "qcom,gcc-msm8960";
|
||||
reg = <0x900000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
||||
@ -17,6 +17,7 @@ description: |
|
||||
dt-bindings/clock/qcom,gpucc-sdm845.h
|
||||
dt-bindings/clock/qcom,gpucc-sc7180.h
|
||||
dt-bindings/clock/qcom,gpucc-sc7280.h
|
||||
dt-bindings/clock/qcom,gpucc-sm6350.h
|
||||
dt-bindings/clock/qcom,gpucc-sm8150.h
|
||||
dt-bindings/clock/qcom,gpucc-sm8250.h
|
||||
|
||||
@ -27,6 +28,7 @@ properties:
|
||||
- qcom,sc7180-gpucc
|
||||
- qcom,sc7280-gpucc
|
||||
- qcom,sc8180x-gpucc
|
||||
- qcom,sm6350-gpucc
|
||||
- qcom,sm8150-gpucc
|
||||
- qcom,sm8250-gpucc
|
||||
|
||||
|
||||
@ -19,6 +19,7 @@ properties:
|
||||
enum:
|
||||
- qcom,mmcc-apq8064
|
||||
- qcom,mmcc-apq8084
|
||||
- qcom,mmcc-msm8226
|
||||
- qcom,mmcc-msm8660
|
||||
- qcom,mmcc-msm8960
|
||||
- qcom,mmcc-msm8974
|
||||
|
||||
@ -0,0 +1,87 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,qcm2290-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller Binding for qcm2290
|
||||
|
||||
maintainers:
|
||||
- Loic Poulain <loic.poulain@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks, resets and
|
||||
power domains on qcm2290.
|
||||
|
||||
See also dt-bindings/clock/qcom,dispcc-qcm2290.h.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,qcm2290-dispcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board active-only XO source
|
||||
- description: GPLL0 source from GCC
|
||||
- description: GPLL0 div source from GCC
|
||||
- description: Byte clock from DSI PHY
|
||||
- description: Pixel clock from DSI PHY
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
- const: gcc_disp_gpll0_clk_src
|
||||
- const: gcc_disp_gpll0_div_clk_src
|
||||
- const: dsi0_phy_pll_out_byteclk
|
||||
- const: dsi0_phy_pll_out_dsiclk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
clock-controller@5f00000 {
|
||||
compatible = "qcom,qcm2290-dispcc";
|
||||
reg = <0x5f00000 0x20000>;
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&rpmcc RPM_SMD_XO_A_CLK_SRC>,
|
||||
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
|
||||
<&dsi0_phy 0>,
|
||||
<&dsi0_phy 1>;
|
||||
clock-names = "bi_tcxo",
|
||||
"bi_tcxo_ao",
|
||||
"gcc_disp_gpll0_clk_src",
|
||||
"gcc_disp_gpll0_div_clk_src",
|
||||
"dsi0_phy_pll_out_byteclk",
|
||||
"dsi0_phy_pll_out_dsiclk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -20,6 +20,7 @@ properties:
|
||||
- qcom,sc7180-rpmh-clk
|
||||
- qcom,sc7280-rpmh-clk
|
||||
- qcom,sc8180x-rpmh-clk
|
||||
- qcom,sc8280xp-rpmh-clk
|
||||
- qcom,sdm845-rpmh-clk
|
||||
- qcom,sdx55-rpmh-clk
|
||||
- qcom,sdx65-rpmh-clk
|
||||
|
||||
@ -0,0 +1,65 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sdm845-camcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Camera Clock & Reset Controller Binding for SDM845
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm camera clock control module which supports the clocks, resets and
|
||||
power domains on SDM845.
|
||||
|
||||
See also dt-bindings/clock/qcom,camcc-sm845.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sdm845-camcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@ad00000 {
|
||||
compatible = "qcom,sdm845-camcc";
|
||||
reg = <0x0ad00000 0x10000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "bi_tcxo";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -29,11 +29,11 @@ config QCOM_A53PLL
|
||||
devices.
|
||||
|
||||
config QCOM_A7PLL
|
||||
tristate "SDX55 A7 PLL"
|
||||
tristate "A7 PLL driver for SDX55 and SDX65"
|
||||
help
|
||||
Support for the A7 PLL on SDX55 devices. It provides the CPU with
|
||||
Support for the A7 PLL on SDX55 and SDX65 devices. It provides the CPU with
|
||||
frequencies above 1GHz.
|
||||
Say Y if you want to support higher CPU frequencies on SDX55
|
||||
Say Y if you want to support higher CPU frequencies on SDX55 and SDX65
|
||||
devices.
|
||||
|
||||
config QCOM_CLK_APCS_MSM8916
|
||||
@ -55,13 +55,13 @@ config QCOM_CLK_APCC_MSM8996
|
||||
drivers for dynamic power management.
|
||||
|
||||
config QCOM_CLK_APCS_SDX55
|
||||
tristate "SDX55 APCS Clock Controller"
|
||||
tristate "SDX55 and SDX65 APCS Clock Controller"
|
||||
depends on QCOM_APCS_IPC || COMPILE_TEST
|
||||
help
|
||||
Support for the APCS Clock Controller on SDX55 platform. The
|
||||
Support for the APCS Clock Controller on SDX55, SDX65 platforms. The
|
||||
APCS is managing the mux and divider which feeds the CPUs.
|
||||
Say Y if you want to support CPU frequency scaling on devices
|
||||
such as SDX55.
|
||||
such as SDX55, SDX65.
|
||||
|
||||
config QCOM_CLK_RPM
|
||||
tristate "RPM based Clock Controller"
|
||||
@ -340,6 +340,15 @@ config QCM_GCC_2290
|
||||
Say Y if you want to use multimedia devices or peripheral
|
||||
devices such as UART, SPI, I2C, USB, SD/eMMC etc.
|
||||
|
||||
config QCM_DISPCC_2290
|
||||
tristate "QCM2290 Display Clock Controller"
|
||||
select QCM_GCC_2290
|
||||
help
|
||||
Support for the display clock controller on Qualcomm Technologies, Inc
|
||||
QCM2290 devices.
|
||||
Say Y if you want to support display devices and functionality such as
|
||||
splash screen.
|
||||
|
||||
config QCS_GCC_404
|
||||
tristate "QCS404 Global Clock Controller"
|
||||
help
|
||||
@ -565,13 +574,6 @@ config SDX_GCC_55
|
||||
Say Y if you want to use peripheral devices such as UART,
|
||||
SPI, I2C, USB, SD/UFS, PCIe etc.
|
||||
|
||||
config SM_CAMCC_8250
|
||||
tristate "SM8250 Camera Clock Controller"
|
||||
select SM_GCC_8250
|
||||
help
|
||||
Support for the camera clock controller on SM8250 devices.
|
||||
Say Y if you want to support camera devices and camera functionality.
|
||||
|
||||
config SDX_GCC_65
|
||||
tristate "SDX65 Global Clock Controller"
|
||||
select QCOM_GDSC
|
||||
@ -580,6 +582,22 @@ config SDX_GCC_65
|
||||
Say Y if you want to use peripheral devices such as UART,
|
||||
SPI, I2C, USB, SD/UFS, PCIe etc.
|
||||
|
||||
config SM_CAMCC_8250
|
||||
tristate "SM8250 Camera Clock Controller"
|
||||
select SM_GCC_8250
|
||||
help
|
||||
Support for the camera clock controller on SM8250 devices.
|
||||
Say Y if you want to support camera devices and camera functionality.
|
||||
|
||||
config SM_DISPCC_6125
|
||||
tristate "SM6125 Display Clock Controller"
|
||||
depends on SM_GCC_6125
|
||||
help
|
||||
Support for the display clock controller on Qualcomm Technologies, Inc
|
||||
SM6125 devices.
|
||||
Say Y if you want to support display devices and functionality such as
|
||||
splash screen
|
||||
|
||||
config SM_DISPCC_8250
|
||||
tristate "SM8150 and SM8250 Display Clock Controller"
|
||||
depends on SM_GCC_8150 || SM_GCC_8250
|
||||
@ -589,6 +607,15 @@ config SM_DISPCC_8250
|
||||
Say Y if you want to support display devices and functionality such as
|
||||
splash screen.
|
||||
|
||||
config SM_DISPCC_6350
|
||||
tristate "SM6350 Display Clock Controller"
|
||||
depends on SM_GCC_6350
|
||||
help
|
||||
Support for the display clock controller on Qualcomm Technologies, Inc
|
||||
SM6350 devices.
|
||||
Say Y if you want to support display devices and functionality such as
|
||||
splash screen.
|
||||
|
||||
config SM_GCC_6115
|
||||
tristate "SM6115 and SM4250 Global Clock Controller"
|
||||
help
|
||||
@ -642,6 +669,14 @@ config SM_GCC_8450
|
||||
Say Y if you want to use peripheral devices such as UART,
|
||||
SPI, I2C, USB, SD/UFS, PCIe etc.
|
||||
|
||||
config SM_GPUCC_6350
|
||||
tristate "SM6350 Graphics Clock Controller"
|
||||
select SM_GCC_6350
|
||||
help
|
||||
Support for the graphics clock controller on SM6350 devices.
|
||||
Say Y if you want to support graphics controller devices and
|
||||
functionality such as 3D graphics.
|
||||
|
||||
config SM_GPUCC_8150
|
||||
tristate "SM8150 Graphics Clock Controller"
|
||||
select SM_GCC_8150
|
||||
|
||||
@ -56,6 +56,7 @@ obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
|
||||
obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o
|
||||
obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
|
||||
obj-$(CONFIG_QCM_GCC_2290) += gcc-qcm2290.o
|
||||
obj-$(CONFIG_QCM_DISPCC_2290) += dispcc-qcm2290.o
|
||||
obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o
|
||||
obj-$(CONFIG_QCS_Q6SSTOP_404) += q6sstop-qcs404.o
|
||||
obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o
|
||||
@ -83,8 +84,10 @@ obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o
|
||||
obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
|
||||
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
|
||||
obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o
|
||||
obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
|
||||
obj-$(CONFIG_SDX_GCC_65) += gcc-sdx65.o
|
||||
obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
|
||||
obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
|
||||
obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o
|
||||
obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
|
||||
obj-$(CONFIG_SM_GCC_6115) += gcc-sm6115.o
|
||||
obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o
|
||||
@ -93,6 +96,7 @@ obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
|
||||
obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
|
||||
obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o
|
||||
obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o
|
||||
obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o
|
||||
obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
|
||||
obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
|
||||
obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
|
||||
|
||||
@ -29,7 +29,6 @@ enum {
|
||||
P_CAM_CC_PLL2_OUT_AUX,
|
||||
P_CAM_CC_PLL2_OUT_EARLY,
|
||||
P_CAM_CC_PLL3_OUT_MAIN,
|
||||
P_CORE_BI_PLL_TEST_SE,
|
||||
};
|
||||
|
||||
static const struct pll_vco agera_vco[] = {
|
||||
@ -127,7 +126,9 @@ static struct clk_fixed_factor cam_cc_pll2_out_early = {
|
||||
.div = 2,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_pll2_out_early",
|
||||
.parent_names = (const char *[]){ "cam_cc_pll2" },
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_pll2.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
},
|
||||
@ -147,8 +148,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux = {
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA],
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_pll2_out_aux",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_pll2.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_pll2.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -187,26 +188,22 @@ static const struct parent_map cam_cc_parent_map_0[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
|
||||
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
|
||||
{ P_CORE_BI_PLL_TEST_SE, 7 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data cam_cc_parent_data_0[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .hw = &cam_cc_pll1.clkr.hw },
|
||||
{ .hw = &cam_cc_pll0.clkr.hw },
|
||||
{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
|
||||
};
|
||||
|
||||
static const struct parent_map cam_cc_parent_map_1[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_CAM_CC_PLL2_OUT_AUX, 1 },
|
||||
{ P_CORE_BI_PLL_TEST_SE, 7 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data cam_cc_parent_data_1[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .hw = &cam_cc_pll2_out_aux.clkr.hw },
|
||||
{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
|
||||
};
|
||||
|
||||
static const struct parent_map cam_cc_parent_map_2[] = {
|
||||
@ -214,7 +211,6 @@ static const struct parent_map cam_cc_parent_map_2[] = {
|
||||
{ P_CAM_CC_PLL2_OUT_EARLY, 4 },
|
||||
{ P_CAM_CC_PLL3_OUT_MAIN, 5 },
|
||||
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
|
||||
{ P_CORE_BI_PLL_TEST_SE, 7 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data cam_cc_parent_data_2[] = {
|
||||
@ -222,7 +218,6 @@ static const struct clk_parent_data cam_cc_parent_data_2[] = {
|
||||
{ .hw = &cam_cc_pll2_out_early.hw },
|
||||
{ .hw = &cam_cc_pll3.clkr.hw },
|
||||
{ .hw = &cam_cc_pll0.clkr.hw },
|
||||
{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
|
||||
};
|
||||
|
||||
static const struct parent_map cam_cc_parent_map_3[] = {
|
||||
@ -231,7 +226,6 @@ static const struct parent_map cam_cc_parent_map_3[] = {
|
||||
{ P_CAM_CC_PLL2_OUT_EARLY, 4 },
|
||||
{ P_CAM_CC_PLL3_OUT_MAIN, 5 },
|
||||
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
|
||||
{ P_CORE_BI_PLL_TEST_SE, 7 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data cam_cc_parent_data_3[] = {
|
||||
@ -240,33 +234,28 @@ static const struct clk_parent_data cam_cc_parent_data_3[] = {
|
||||
{ .hw = &cam_cc_pll2_out_early.hw },
|
||||
{ .hw = &cam_cc_pll3.clkr.hw },
|
||||
{ .hw = &cam_cc_pll0.clkr.hw },
|
||||
{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
|
||||
};
|
||||
|
||||
static const struct parent_map cam_cc_parent_map_4[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_CAM_CC_PLL3_OUT_MAIN, 5 },
|
||||
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
|
||||
{ P_CORE_BI_PLL_TEST_SE, 7 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data cam_cc_parent_data_4[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .hw = &cam_cc_pll3.clkr.hw },
|
||||
{ .hw = &cam_cc_pll0.clkr.hw },
|
||||
{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
|
||||
};
|
||||
|
||||
static const struct parent_map cam_cc_parent_map_5[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
|
||||
{ P_CORE_BI_PLL_TEST_SE, 7 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data cam_cc_parent_data_5[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .hw = &cam_cc_pll0.clkr.hw },
|
||||
{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
|
||||
};
|
||||
|
||||
static const struct parent_map cam_cc_parent_map_6[] = {
|
||||
@ -274,7 +263,6 @@ static const struct parent_map cam_cc_parent_map_6[] = {
|
||||
{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
|
||||
{ P_CAM_CC_PLL3_OUT_MAIN, 5 },
|
||||
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
|
||||
{ P_CORE_BI_PLL_TEST_SE, 7 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data cam_cc_parent_data_6[] = {
|
||||
@ -282,7 +270,6 @@ static const struct clk_parent_data cam_cc_parent_data_6[] = {
|
||||
{ .hw = &cam_cc_pll1.clkr.hw },
|
||||
{ .hw = &cam_cc_pll3.clkr.hw },
|
||||
{ .hw = &cam_cc_pll0.clkr.hw },
|
||||
{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
|
||||
@ -303,7 +290,7 @@ static struct clk_rcg2 cam_cc_bps_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_bps_clk_src",
|
||||
.parent_data = cam_cc_parent_data_2,
|
||||
.num_parents = 5,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -324,7 +311,7 @@ static struct clk_rcg2 cam_cc_cci_0_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_cci_0_clk_src",
|
||||
.parent_data = cam_cc_parent_data_5,
|
||||
.num_parents = 3,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -338,7 +325,7 @@ static struct clk_rcg2 cam_cc_cci_1_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_cci_1_clk_src",
|
||||
.parent_data = cam_cc_parent_data_5,
|
||||
.num_parents = 3,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -359,7 +346,7 @@ static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_cphy_rx_clk_src",
|
||||
.parent_data = cam_cc_parent_data_3,
|
||||
.num_parents = 6,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -378,7 +365,7 @@ static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_csi0phytimer_clk_src",
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = 4,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -392,7 +379,7 @@ static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_csi1phytimer_clk_src",
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = 4,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -406,7 +393,7 @@ static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_csi2phytimer_clk_src",
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = 4,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -420,7 +407,7 @@ static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_csi3phytimer_clk_src",
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = 4,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -442,7 +429,7 @@ static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_fast_ahb_clk_src",
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = 4,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -465,7 +452,7 @@ static struct clk_rcg2 cam_cc_icp_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_icp_clk_src",
|
||||
.parent_data = cam_cc_parent_data_2,
|
||||
.num_parents = 5,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -487,7 +474,7 @@ static struct clk_rcg2 cam_cc_ife_0_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_0_clk_src",
|
||||
.parent_data = cam_cc_parent_data_4,
|
||||
.num_parents = 4,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -509,7 +496,7 @@ static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_0_csid_clk_src",
|
||||
.parent_data = cam_cc_parent_data_3,
|
||||
.num_parents = 6,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -523,7 +510,7 @@ static struct clk_rcg2 cam_cc_ife_1_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_1_clk_src",
|
||||
.parent_data = cam_cc_parent_data_4,
|
||||
.num_parents = 4,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -537,7 +524,7 @@ static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_1_csid_clk_src",
|
||||
.parent_data = cam_cc_parent_data_3,
|
||||
.num_parents = 6,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -551,7 +538,7 @@ static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_lite_clk_src",
|
||||
.parent_data = cam_cc_parent_data_4,
|
||||
.num_parents = 4,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
@ -566,7 +553,7 @@ static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_lite_csid_clk_src",
|
||||
.parent_data = cam_cc_parent_data_3,
|
||||
.num_parents = 6,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -589,7 +576,7 @@ static struct clk_rcg2 cam_cc_ipe_0_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ipe_0_clk_src",
|
||||
.parent_data = cam_cc_parent_data_2,
|
||||
.num_parents = 5,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -612,7 +599,7 @@ static struct clk_rcg2 cam_cc_jpeg_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_jpeg_clk_src",
|
||||
.parent_data = cam_cc_parent_data_2,
|
||||
.num_parents = 5,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -634,7 +621,7 @@ static struct clk_rcg2 cam_cc_lrme_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_lrme_clk_src",
|
||||
.parent_data = cam_cc_parent_data_6,
|
||||
.num_parents = 5,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -655,7 +642,7 @@ static struct clk_rcg2 cam_cc_mclk0_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_mclk0_clk_src",
|
||||
.parent_data = cam_cc_parent_data_1,
|
||||
.num_parents = 3,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -669,7 +656,7 @@ static struct clk_rcg2 cam_cc_mclk1_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_mclk1_clk_src",
|
||||
.parent_data = cam_cc_parent_data_1,
|
||||
.num_parents = 3,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -683,7 +670,7 @@ static struct clk_rcg2 cam_cc_mclk2_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_mclk2_clk_src",
|
||||
.parent_data = cam_cc_parent_data_1,
|
||||
.num_parents = 3,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -697,7 +684,7 @@ static struct clk_rcg2 cam_cc_mclk3_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_mclk3_clk_src",
|
||||
.parent_data = cam_cc_parent_data_1,
|
||||
.num_parents = 3,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -711,7 +698,7 @@ static struct clk_rcg2 cam_cc_mclk4_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_mclk4_clk_src",
|
||||
.parent_data = cam_cc_parent_data_1,
|
||||
.num_parents = 3,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -730,7 +717,7 @@ static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_slow_ahb_clk_src",
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = 4,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
@ -744,8 +731,8 @@ static struct clk_branch cam_cc_bps_ahb_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_bps_ahb_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_slow_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -762,8 +749,8 @@ static struct clk_branch cam_cc_bps_areg_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_bps_areg_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_fast_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -793,8 +780,8 @@ static struct clk_branch cam_cc_bps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_bps_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_bps_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_bps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -824,8 +811,8 @@ static struct clk_branch cam_cc_cci_0_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_cci_0_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_cci_0_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_cci_0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -842,8 +829,8 @@ static struct clk_branch cam_cc_cci_1_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_cci_1_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_cci_1_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_cci_1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -860,8 +847,8 @@ static struct clk_branch cam_cc_core_ahb_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_core_ahb_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_slow_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -878,8 +865,8 @@ static struct clk_branch cam_cc_cpas_ahb_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_cpas_ahb_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_slow_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -896,8 +883,8 @@ static struct clk_branch cam_cc_csi0phytimer_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_csi0phytimer_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_csi0phytimer_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_csi0phytimer_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -914,8 +901,8 @@ static struct clk_branch cam_cc_csi1phytimer_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_csi1phytimer_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_csi1phytimer_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_csi1phytimer_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -932,8 +919,8 @@ static struct clk_branch cam_cc_csi2phytimer_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_csi2phytimer_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_csi2phytimer_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_csi2phytimer_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -950,8 +937,8 @@ static struct clk_branch cam_cc_csi3phytimer_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_csi3phytimer_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_csi3phytimer_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_csi3phytimer_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -968,8 +955,8 @@ static struct clk_branch cam_cc_csiphy0_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_csiphy0_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -986,8 +973,8 @@ static struct clk_branch cam_cc_csiphy1_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_csiphy1_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1004,8 +991,8 @@ static struct clk_branch cam_cc_csiphy2_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_csiphy2_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1022,8 +1009,8 @@ static struct clk_branch cam_cc_csiphy3_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_csiphy3_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1040,8 +1027,8 @@ static struct clk_branch cam_cc_icp_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_icp_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_icp_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_icp_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1071,8 +1058,8 @@ static struct clk_branch cam_cc_ife_0_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_0_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_ife_0_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_ife_0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1089,8 +1076,8 @@ static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_0_cphy_rx_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1107,8 +1094,8 @@ static struct clk_branch cam_cc_ife_0_csid_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_0_csid_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_ife_0_csid_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_ife_0_csid_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1125,8 +1112,8 @@ static struct clk_branch cam_cc_ife_0_dsp_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_0_dsp_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_ife_0_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_ife_0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1156,8 +1143,8 @@ static struct clk_branch cam_cc_ife_1_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_1_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_ife_1_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_ife_1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1174,8 +1161,8 @@ static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_1_cphy_rx_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1192,8 +1179,8 @@ static struct clk_branch cam_cc_ife_1_csid_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_1_csid_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_ife_1_csid_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_ife_1_csid_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1210,8 +1197,8 @@ static struct clk_branch cam_cc_ife_1_dsp_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_1_dsp_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_ife_1_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_ife_1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1228,8 +1215,8 @@ static struct clk_branch cam_cc_ife_lite_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_lite_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_ife_lite_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_ife_lite_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1246,8 +1233,8 @@ static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_lite_cphy_rx_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1264,8 +1251,8 @@ static struct clk_branch cam_cc_ife_lite_csid_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_lite_csid_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_ife_lite_csid_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_ife_lite_csid_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1282,8 +1269,8 @@ static struct clk_branch cam_cc_ipe_0_ahb_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ipe_0_ahb_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_slow_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1300,8 +1287,8 @@ static struct clk_branch cam_cc_ipe_0_areg_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ipe_0_areg_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_fast_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1331,8 +1318,8 @@ static struct clk_branch cam_cc_ipe_0_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ipe_0_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_ipe_0_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_ipe_0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1349,8 +1336,8 @@ static struct clk_branch cam_cc_jpeg_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_jpeg_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_jpeg_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_jpeg_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1367,8 +1354,8 @@ static struct clk_branch cam_cc_lrme_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_lrme_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_lrme_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_lrme_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1385,8 +1372,8 @@ static struct clk_branch cam_cc_mclk0_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_mclk0_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_mclk0_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_mclk0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1403,8 +1390,8 @@ static struct clk_branch cam_cc_mclk1_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_mclk1_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_mclk1_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_mclk1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1421,8 +1408,8 @@ static struct clk_branch cam_cc_mclk2_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_mclk2_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_mclk2_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_mclk2_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1439,8 +1426,8 @@ static struct clk_branch cam_cc_mclk3_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_mclk3_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_mclk3_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_mclk3_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1457,8 +1444,8 @@ static struct clk_branch cam_cc_mclk4_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_mclk4_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &cam_cc_mclk4_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_mclk4_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
||||
@ -23,25 +23,6 @@ enum {
|
||||
P_CAM_CC_PLL1_OUT_EVEN,
|
||||
P_CAM_CC_PLL2_OUT_EVEN,
|
||||
P_CAM_CC_PLL3_OUT_EVEN,
|
||||
P_CORE_BI_PLL_TEST_SE,
|
||||
};
|
||||
|
||||
static const struct parent_map cam_cc_parent_map_0[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_CAM_CC_PLL2_OUT_EVEN, 1 },
|
||||
{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
|
||||
{ P_CAM_CC_PLL3_OUT_EVEN, 5 },
|
||||
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
|
||||
{ P_CORE_BI_PLL_TEST_SE, 7 },
|
||||
};
|
||||
|
||||
static const char * const cam_cc_parent_names_0[] = {
|
||||
"bi_tcxo",
|
||||
"cam_cc_pll2_out_even",
|
||||
"cam_cc_pll1_out_even",
|
||||
"cam_cc_pll3_out_even",
|
||||
"cam_cc_pll0_out_even",
|
||||
"core_bi_pll_test_se",
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll cam_cc_pll0 = {
|
||||
@ -50,7 +31,9 @@ static struct clk_alpha_pll cam_cc_pll0 = {
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_pll0",
|
||||
.parent_names = (const char *[]){ "bi_tcxo" },
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.fw_name = "bi_tcxo", .name = "bi_tcxo",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_fabia_ops,
|
||||
},
|
||||
@ -72,7 +55,9 @@ static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_pll0_out_even",
|
||||
.parent_names = (const char *[]){ "cam_cc_pll0" },
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_pll0.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_postdiv_fabia_ops,
|
||||
},
|
||||
@ -84,7 +69,9 @@ static struct clk_alpha_pll cam_cc_pll1 = {
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_pll1",
|
||||
.parent_names = (const char *[]){ "bi_tcxo" },
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.fw_name = "bi_tcxo", .name = "bi_tcxo",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_fabia_ops,
|
||||
},
|
||||
@ -100,7 +87,9 @@ static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_pll1_out_even",
|
||||
.parent_names = (const char *[]){ "cam_cc_pll1" },
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_pll1.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_postdiv_fabia_ops,
|
||||
},
|
||||
@ -112,7 +101,9 @@ static struct clk_alpha_pll cam_cc_pll2 = {
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_pll2",
|
||||
.parent_names = (const char *[]){ "bi_tcxo" },
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.fw_name = "bi_tcxo", .name = "bi_tcxo",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_fabia_ops,
|
||||
},
|
||||
@ -128,7 +119,9 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even = {
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_pll2_out_even",
|
||||
.parent_names = (const char *[]){ "cam_cc_pll2" },
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_pll2.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_postdiv_fabia_ops,
|
||||
},
|
||||
@ -140,7 +133,9 @@ static struct clk_alpha_pll cam_cc_pll3 = {
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_pll3",
|
||||
.parent_names = (const char *[]){ "bi_tcxo" },
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.fw_name = "bi_tcxo", .name = "bi_tcxo",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_fabia_ops,
|
||||
},
|
||||
@ -156,12 +151,30 @@ static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_pll3_out_even",
|
||||
.parent_names = (const char *[]){ "cam_cc_pll3" },
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_pll3.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_postdiv_fabia_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct parent_map cam_cc_parent_map_0[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_CAM_CC_PLL2_OUT_EVEN, 1 },
|
||||
{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
|
||||
{ P_CAM_CC_PLL3_OUT_EVEN, 5 },
|
||||
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data cam_cc_parent_data_0[] = {
|
||||
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
|
||||
{ .hw = &cam_cc_pll2_out_even.clkr.hw },
|
||||
{ .hw = &cam_cc_pll1_out_even.clkr.hw },
|
||||
{ .hw = &cam_cc_pll3_out_even.clkr.hw },
|
||||
{ .hw = &cam_cc_pll0_out_even.clkr.hw },
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
|
||||
@ -189,8 +202,8 @@ static struct clk_rcg2 cam_cc_bps_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_bps_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_bps_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
@ -212,8 +225,8 @@ static struct clk_rcg2 cam_cc_cci_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_cci_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_cci_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
@ -232,8 +245,8 @@ static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_cphy_rx_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
@ -253,8 +266,8 @@ static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_csi0phytimer_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -268,8 +281,8 @@ static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_csi1phytimer_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -283,8 +296,8 @@ static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_csi2phytimer_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -298,8 +311,8 @@ static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_csi3phytimer_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -323,8 +336,8 @@ static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_fast_ahb_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
@ -346,8 +359,8 @@ static struct clk_rcg2 cam_cc_fd_core_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_fd_core_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_fd_core_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -369,8 +382,8 @@ static struct clk_rcg2 cam_cc_icp_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_icp_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_icp_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -393,8 +406,8 @@ static struct clk_rcg2 cam_cc_ife_0_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_0_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
@ -416,8 +429,8 @@ static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_0_csid_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -430,8 +443,8 @@ static struct clk_rcg2 cam_cc_ife_1_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_1_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
@ -445,8 +458,8 @@ static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_1_csid_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -459,8 +472,8 @@ static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_lite_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
@ -474,8 +487,8 @@ static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_lite_csid_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -499,8 +512,8 @@ static struct clk_rcg2 cam_cc_ipe_0_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ipe_0_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
@ -514,8 +527,8 @@ static struct clk_rcg2 cam_cc_ipe_1_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ipe_1_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
@ -529,8 +542,8 @@ static struct clk_rcg2 cam_cc_jpeg_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_bps_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_jpeg_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
@ -554,8 +567,8 @@ static struct clk_rcg2 cam_cc_lrme_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_lrme_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_lrme_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
@ -577,8 +590,8 @@ static struct clk_rcg2 cam_cc_mclk0_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_mclk0_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -592,8 +605,8 @@ static struct clk_rcg2 cam_cc_mclk1_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_mclk1_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -607,8 +620,8 @@ static struct clk_rcg2 cam_cc_mclk2_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_mclk2_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -622,8 +635,8 @@ static struct clk_rcg2 cam_cc_mclk3_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_mclk3_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -646,8 +659,8 @@ static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
|
||||
.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_slow_ahb_clk_src",
|
||||
.parent_names = cam_cc_parent_names_0,
|
||||
.num_parents = 6,
|
||||
.parent_data = cam_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -661,8 +674,8 @@ static struct clk_branch cam_cc_bps_ahb_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_bps_ahb_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_slow_ahb_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_slow_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -679,8 +692,8 @@ static struct clk_branch cam_cc_bps_areg_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_bps_areg_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_fast_ahb_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_fast_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -710,8 +723,8 @@ static struct clk_branch cam_cc_bps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_bps_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_bps_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_bps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -754,8 +767,8 @@ static struct clk_branch cam_cc_cci_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_cci_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_cci_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_cci_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -772,8 +785,8 @@ static struct clk_branch cam_cc_cpas_ahb_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_cpas_ahb_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_slow_ahb_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_slow_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -790,8 +803,8 @@ static struct clk_branch cam_cc_csi0phytimer_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_csi0phytimer_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_csi0phytimer_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_csi0phytimer_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -808,8 +821,8 @@ static struct clk_branch cam_cc_csi1phytimer_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_csi1phytimer_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_csi1phytimer_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_csi1phytimer_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -826,8 +839,8 @@ static struct clk_branch cam_cc_csi2phytimer_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_csi2phytimer_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_csi2phytimer_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_csi2phytimer_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -844,8 +857,8 @@ static struct clk_branch cam_cc_csi3phytimer_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_csi3phytimer_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_csi3phytimer_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_csi3phytimer_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -862,8 +875,8 @@ static struct clk_branch cam_cc_csiphy0_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_csiphy0_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_cphy_rx_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -880,8 +893,8 @@ static struct clk_branch cam_cc_csiphy1_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_csiphy1_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_cphy_rx_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -898,8 +911,8 @@ static struct clk_branch cam_cc_csiphy2_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_csiphy2_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_cphy_rx_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -916,8 +929,8 @@ static struct clk_branch cam_cc_csiphy3_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_csiphy3_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_cphy_rx_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -934,8 +947,8 @@ static struct clk_branch cam_cc_fd_core_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_fd_core_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_fd_core_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_fd_core_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -952,8 +965,8 @@ static struct clk_branch cam_cc_fd_core_uar_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_fd_core_uar_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_fd_core_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_fd_core_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch2_ops,
|
||||
@ -995,8 +1008,8 @@ static struct clk_branch cam_cc_icp_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_icp_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_icp_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_icp_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1052,8 +1065,8 @@ static struct clk_branch cam_cc_ife_0_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_0_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_ife_0_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_ife_0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1070,8 +1083,8 @@ static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_0_cphy_rx_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_cphy_rx_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1088,8 +1101,8 @@ static struct clk_branch cam_cc_ife_0_csid_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_0_csid_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_ife_0_csid_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_ife_0_csid_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1106,8 +1119,8 @@ static struct clk_branch cam_cc_ife_0_dsp_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_0_dsp_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_ife_0_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_ife_0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch2_ops,
|
||||
@ -1136,8 +1149,8 @@ static struct clk_branch cam_cc_ife_1_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_1_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_ife_1_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_ife_1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1154,8 +1167,8 @@ static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_1_cphy_rx_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_cphy_rx_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1172,8 +1185,8 @@ static struct clk_branch cam_cc_ife_1_csid_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_1_csid_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_ife_1_csid_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_ife_1_csid_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1190,8 +1203,8 @@ static struct clk_branch cam_cc_ife_1_dsp_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_1_dsp_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_ife_1_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_ife_1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch2_ops,
|
||||
@ -1207,8 +1220,8 @@ static struct clk_branch cam_cc_ife_lite_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_lite_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_ife_lite_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_ife_lite_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1225,8 +1238,8 @@ static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_lite_cphy_rx_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_cphy_rx_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1243,8 +1256,8 @@ static struct clk_branch cam_cc_ife_lite_csid_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ife_lite_csid_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_ife_lite_csid_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_ife_lite_csid_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1261,8 +1274,8 @@ static struct clk_branch cam_cc_ipe_0_ahb_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ipe_0_ahb_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_slow_ahb_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_slow_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1279,8 +1292,8 @@ static struct clk_branch cam_cc_ipe_0_areg_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ipe_0_areg_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_fast_ahb_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_fast_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1310,8 +1323,8 @@ static struct clk_branch cam_cc_ipe_0_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ipe_0_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_ipe_0_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_ipe_0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1328,8 +1341,8 @@ static struct clk_branch cam_cc_ipe_1_ahb_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ipe_1_ahb_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_slow_ahb_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_slow_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1346,8 +1359,8 @@ static struct clk_branch cam_cc_ipe_1_areg_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ipe_1_areg_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_fast_ahb_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_fast_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1377,8 +1390,8 @@ static struct clk_branch cam_cc_ipe_1_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_ipe_1_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_ipe_1_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_ipe_1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1395,8 +1408,8 @@ static struct clk_branch cam_cc_jpeg_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_jpeg_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_jpeg_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_jpeg_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1413,8 +1426,8 @@ static struct clk_branch cam_cc_lrme_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_lrme_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_lrme_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_lrme_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1431,8 +1444,8 @@ static struct clk_branch cam_cc_mclk0_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_mclk0_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_mclk0_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_mclk0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1449,8 +1462,8 @@ static struct clk_branch cam_cc_mclk1_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_mclk1_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_mclk1_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_mclk1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1467,8 +1480,8 @@ static struct clk_branch cam_cc_mclk2_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_mclk2_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_mclk2_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_mclk2_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1485,8 +1498,8 @@ static struct clk_branch cam_cc_mclk3_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cam_cc_mclk3_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"cam_cc_mclk3_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&cam_cc_mclk3_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
||||
@ -526,6 +526,19 @@ static int clk_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
return __clk_rcg_set_rate(rcg, f);
|
||||
}
|
||||
|
||||
static int clk_rcg_set_floor_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_rcg *rcg = to_clk_rcg(hw);
|
||||
const struct freq_tbl *f;
|
||||
|
||||
f = qcom_find_freq_floor(rcg->freq_tbl, rate);
|
||||
if (!f)
|
||||
return -EINVAL;
|
||||
|
||||
return __clk_rcg_set_rate(rcg, f);
|
||||
}
|
||||
|
||||
static int clk_rcg_bypass_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
@ -816,6 +829,17 @@ const struct clk_ops clk_rcg_ops = {
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_rcg_ops);
|
||||
|
||||
const struct clk_ops clk_rcg_floor_ops = {
|
||||
.enable = clk_enable_regmap,
|
||||
.disable = clk_disable_regmap,
|
||||
.get_parent = clk_rcg_get_parent,
|
||||
.set_parent = clk_rcg_set_parent,
|
||||
.recalc_rate = clk_rcg_recalc_rate,
|
||||
.determine_rate = clk_rcg_determine_rate,
|
||||
.set_rate = clk_rcg_set_floor_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_rcg_floor_ops);
|
||||
|
||||
const struct clk_ops clk_rcg_bypass_ops = {
|
||||
.enable = clk_enable_regmap,
|
||||
.disable = clk_disable_regmap,
|
||||
|
||||
@ -86,6 +86,7 @@ struct clk_rcg {
|
||||
};
|
||||
|
||||
extern const struct clk_ops clk_rcg_ops;
|
||||
extern const struct clk_ops clk_rcg_floor_ops;
|
||||
extern const struct clk_ops clk_rcg_bypass_ops;
|
||||
extern const struct clk_ops clk_rcg_bypass2_ops;
|
||||
extern const struct clk_ops clk_rcg_pixel_ops;
|
||||
|
||||
@ -264,7 +264,7 @@ static int clk_rcg2_determine_floor_rate(struct clk_hw *hw,
|
||||
|
||||
static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
|
||||
{
|
||||
u32 cfg, mask;
|
||||
u32 cfg, mask, d_val, not2d_val, n_minus_m;
|
||||
struct clk_hw *hw = &rcg->clkr.hw;
|
||||
int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);
|
||||
|
||||
@ -283,8 +283,17 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Calculate 2d value */
|
||||
d_val = f->n;
|
||||
|
||||
n_minus_m = f->n - f->m;
|
||||
n_minus_m *= 2;
|
||||
|
||||
d_val = clamp_t(u32, d_val, f->m, n_minus_m);
|
||||
not2d_val = ~d_val & mask;
|
||||
|
||||
ret = regmap_update_bits(rcg->clkr.regmap,
|
||||
RCG_D_OFFSET(rcg), mask, ~f->n);
|
||||
RCG_D_OFFSET(rcg), mask, not2d_val);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
@ -720,6 +729,7 @@ static const struct frac_entry frac_table_pixel[] = {
|
||||
{ 2, 9 },
|
||||
{ 4, 9 },
|
||||
{ 1, 1 },
|
||||
{ 2, 3 },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
||||
@ -512,6 +512,23 @@ static const struct clk_rpmh_desc clk_rpmh_sm8350 = {
|
||||
.num_clks = ARRAY_SIZE(sm8350_rpmh_clocks),
|
||||
};
|
||||
|
||||
DEFINE_CLK_RPMH_VRM(sc8280xp, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
|
||||
|
||||
static struct clk_hw *sc8280xp_rpmh_clocks[] = {
|
||||
[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
|
||||
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
|
||||
[RPMH_LN_BB_CLK3] = &sc8280xp_ln_bb_clk3.hw,
|
||||
[RPMH_LN_BB_CLK3_A] = &sc8280xp_ln_bb_clk3_ao.hw,
|
||||
[RPMH_IPA_CLK] = &sdm845_ipa.hw,
|
||||
[RPMH_PKA_CLK] = &sm8350_pka.hw,
|
||||
[RPMH_HWKM_CLK] = &sm8350_hwkm.hw,
|
||||
};
|
||||
|
||||
static const struct clk_rpmh_desc clk_rpmh_sc8280xp = {
|
||||
.clks = sc8280xp_rpmh_clocks,
|
||||
.num_clks = ARRAY_SIZE(sc8280xp_rpmh_clocks),
|
||||
};
|
||||
|
||||
/* Resource name must match resource id present in cmd-db */
|
||||
DEFINE_CLK_RPMH_ARC(sc7280, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 4);
|
||||
|
||||
@ -691,6 +708,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
|
||||
static const struct of_device_id clk_rpmh_match_table[] = {
|
||||
{ .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180},
|
||||
{ .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x},
|
||||
{ .compatible = "qcom,sc8280xp-rpmh-clk", .data = &clk_rpmh_sc8280xp},
|
||||
{ .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
|
||||
{ .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55},
|
||||
{ .compatible = "qcom,sdx65-rpmh-clk", .data = &clk_rpmh_sdx65},
|
||||
|
||||
@ -413,6 +413,7 @@ static const struct clk_ops clk_smd_rpm_branch_ops = {
|
||||
.recalc_rate = clk_smd_rpm_recalc_rate,
|
||||
};
|
||||
|
||||
DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0, 19200000);
|
||||
DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
|
||||
DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
|
||||
DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
|
||||
@ -604,7 +605,11 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, ln_bb_clk, ln_bb_a_clk, 8, 19200000);
|
||||
DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
|
||||
DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1);
|
||||
|
||||
DEFINE_CLK_SMD_RPM_BRANCH(msm8992, mss_cfg_ahb_clk, mss_cfg_ahb_a_clk,
|
||||
QCOM_SMD_RPM_MCFG_CLK, 0, 19200000);
|
||||
static struct clk_smd_rpm *msm8992_clks[] = {
|
||||
[RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
|
||||
[RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
|
||||
[RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
|
||||
[RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
|
||||
[RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk,
|
||||
@ -637,6 +642,8 @@ static struct clk_smd_rpm *msm8992_clks[] = {
|
||||
[RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
|
||||
[RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk,
|
||||
[RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
|
||||
[RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_mss_cfg_ahb_clk,
|
||||
[RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_mss_cfg_ahb_a_clk,
|
||||
[RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
|
||||
[RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
|
||||
[RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
|
||||
@ -661,6 +668,8 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8992 = {
|
||||
DEFINE_CLK_SMD_RPM(msm8994, ce3_clk, ce3_a_clk, QCOM_SMD_RPM_CE_CLK, 2);
|
||||
|
||||
static struct clk_smd_rpm *msm8994_clks[] = {
|
||||
[RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
|
||||
[RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
|
||||
[RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
|
||||
[RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
|
||||
[RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk,
|
||||
@ -693,6 +702,8 @@ static struct clk_smd_rpm *msm8994_clks[] = {
|
||||
[RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
|
||||
[RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk,
|
||||
[RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
|
||||
[RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_mss_cfg_ahb_clk,
|
||||
[RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_mss_cfg_ahb_a_clk,
|
||||
[RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
|
||||
[RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
|
||||
[RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
|
||||
@ -805,15 +816,18 @@ static const struct rpm_smd_clk_desc rpm_clk_qcs404 = {
|
||||
.num_clks = ARRAY_SIZE(qcs404_clks),
|
||||
};
|
||||
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin,
|
||||
3, 19200000);
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000);
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin, 3, 19200000);
|
||||
DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk,
|
||||
QCOM_SMD_RPM_AGGR_CLK, 1);
|
||||
DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk,
|
||||
QCOM_SMD_RPM_AGGR_CLK, 2);
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk3, rf_clk3_a, 6, 19200000);
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3_pin, rf_clk3_a_pin, 6, 19200000);
|
||||
|
||||
static struct clk_smd_rpm *msm8998_clks[] = {
|
||||
[RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
|
||||
[RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
|
||||
[RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
|
||||
[RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
|
||||
[RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
|
||||
@ -826,12 +840,22 @@ static struct clk_smd_rpm *msm8998_clks[] = {
|
||||
[RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
|
||||
[RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
|
||||
[RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
|
||||
[RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
|
||||
[RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
|
||||
[RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
|
||||
[RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
|
||||
[RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
|
||||
[RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
|
||||
[RPM_SMD_LN_BB_CLK1] = &msm8916_bb_clk1,
|
||||
[RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a,
|
||||
[RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
|
||||
[RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
|
||||
[RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3,
|
||||
[RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a,
|
||||
[RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
|
||||
[RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
|
||||
[RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
|
||||
[RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
|
||||
[RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin,
|
||||
[RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin,
|
||||
[RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
|
||||
@ -844,10 +868,14 @@ static struct clk_smd_rpm *msm8998_clks[] = {
|
||||
[RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
|
||||
[RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
|
||||
[RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
|
||||
[RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
|
||||
[RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
|
||||
[RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
|
||||
[RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
|
||||
[RPM_SMD_RF_CLK3] = &msm8998_rf_clk3,
|
||||
[RPM_SMD_RF_CLK3_A] = &msm8998_rf_clk3_a,
|
||||
[RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
|
||||
[RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
|
||||
[RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
|
||||
[RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
|
||||
[RPM_SMD_RF_CLK3_PIN] = &msm8998_rf_clk3_pin,
|
||||
[RPM_SMD_RF_CLK3_A_PIN] = &msm8998_rf_clk3_a_pin,
|
||||
};
|
||||
@ -857,11 +885,6 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
|
||||
.num_clks = ARRAY_SIZE(msm8998_clks),
|
||||
};
|
||||
|
||||
DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0,
|
||||
19200000);
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000);
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin, ln_bb_clk3_pin_a, 3, 19200000);
|
||||
|
||||
static struct clk_smd_rpm *sdm660_clks[] = {
|
||||
[RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
|
||||
[RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
|
||||
@ -891,16 +914,16 @@ static struct clk_smd_rpm *sdm660_clks[] = {
|
||||
[RPM_SMD_LN_BB_A_CLK] = &msm8916_bb_clk1_a,
|
||||
[RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
|
||||
[RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
|
||||
[RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3,
|
||||
[RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a,
|
||||
[RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3,
|
||||
[RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a,
|
||||
[RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
|
||||
[RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
|
||||
[RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
|
||||
[RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
|
||||
[RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
|
||||
[RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
|
||||
[RPM_SMD_LN_BB_CLK3_PIN] = &sdm660_ln_bb_clk3_pin,
|
||||
[RPM_SMD_LN_BB_CLK3_A_PIN] = &sdm660_ln_bb_clk3_pin_a,
|
||||
[RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin,
|
||||
[RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin,
|
||||
};
|
||||
|
||||
static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
|
||||
@ -1002,8 +1025,8 @@ static struct clk_smd_rpm *sm6125_clks[] = {
|
||||
[RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a,
|
||||
[RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
|
||||
[RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
|
||||
[RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3,
|
||||
[RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a,
|
||||
[RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3,
|
||||
[RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a,
|
||||
[RPM_SMD_QUP_CLK] = &sm6125_qup_clk,
|
||||
[RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk,
|
||||
[RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk,
|
||||
|
||||
555
drivers/clk/qcom/dispcc-qcm2290.c
Normal file
555
drivers/clk/qcom/dispcc-qcm2290.c
Normal file
@ -0,0 +1,555 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2021, Linaro Ltd.
|
||||
*/
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
|
||||
|
||||
#include "clk-alpha-pll.h"
|
||||
#include "clk-branch.h"
|
||||
#include "clk-rcg.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "clk-regmap-divider.h"
|
||||
#include "common.h"
|
||||
#include "gdsc.h"
|
||||
|
||||
enum {
|
||||
P_BI_TCXO,
|
||||
P_DISP_CC_PLL0_OUT_MAIN,
|
||||
P_DSI0_PHY_PLL_OUT_BYTECLK,
|
||||
P_DSI0_PHY_PLL_OUT_DSICLK,
|
||||
P_DSI1_PHY_PLL_OUT_DSICLK,
|
||||
P_GPLL0_OUT_MAIN,
|
||||
P_SLEEP_CLK,
|
||||
};
|
||||
|
||||
static const struct pll_vco spark_vco[] = {
|
||||
{ 500000000, 1000000000, 2 },
|
||||
};
|
||||
|
||||
/* 768MHz configuration */
|
||||
static const struct alpha_pll_config disp_cc_pll0_config = {
|
||||
.l = 0x28,
|
||||
.alpha = 0x0,
|
||||
.alpha_en_mask = BIT(24),
|
||||
.vco_val = 0x2 << 20,
|
||||
.vco_mask = GENMASK(21, 20),
|
||||
.main_output_mask = BIT(0),
|
||||
.config_ctl_val = 0x4001055B,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll disp_cc_pll0 = {
|
||||
.offset = 0x0,
|
||||
.vco_table = spark_vco,
|
||||
.num_vco = ARRAY_SIZE(spark_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_pll0",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.fw_name = "bi_tcxo",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_0[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_0[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .fw_name = "dsi0_phy_pll_out_byteclk" },
|
||||
{ .fw_name = "core_bi_pll_test_se" },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_1[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_1[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .fw_name = "core_bi_pll_test_se" },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_2[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPLL0_OUT_MAIN, 4 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_2[] = {
|
||||
{ .fw_name = "bi_tcxo_ao" },
|
||||
{ .fw_name = "gcc_disp_gpll0_div_clk_src" },
|
||||
{ .fw_name = "core_bi_pll_test_se" },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_3[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
|
||||
{ P_GPLL0_OUT_MAIN, 4 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_3[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .hw = &disp_cc_pll0.clkr.hw },
|
||||
{ .fw_name = "gcc_disp_gpll0_clk_src" },
|
||||
{ .fw_name = "core_bi_pll_test_se" },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_4[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
|
||||
{ P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_4[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .fw_name = "dsi0_phy_pll_out_dsiclk" },
|
||||
{ .fw_name = "dsi1_phy_pll_out_dsiclk" },
|
||||
{ .fw_name = "core_bi_pll_test_se" },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_5[] = {
|
||||
{ P_SLEEP_CLK, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_5[] = {
|
||||
{ .fw_name = "sleep_clk" },
|
||||
{ .fw_name = "core_bi_pll_test_se" },
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
|
||||
.cmd_rcgr = 0x20a4,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_0,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_byte0_clk_src",
|
||||
.parent_data = disp_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
||||
/* For set_rate and set_parent to succeed, parent(s) must be enabled */
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
|
||||
.ops = &clk_byte2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
|
||||
.reg = 0x20bc,
|
||||
.shift = 0,
|
||||
.width = 2,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_byte0_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_byte0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_regmap_div_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0),
|
||||
F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
|
||||
.cmd_rcgr = 0x2154,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_2,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_ahb_clk_src",
|
||||
.parent_data = disp_cc_parent_data_2,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
|
||||
.cmd_rcgr = 0x20c0,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_esc0_clk_src",
|
||||
.parent_data = disp_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
|
||||
F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
||||
F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
|
||||
F(384000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
|
||||
.cmd_rcgr = 0x2074,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_3,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_mdp_clk_src",
|
||||
.parent_data = disp_cc_parent_data_3,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
|
||||
.cmd_rcgr = 0x205c,
|
||||
.mnd_width = 8,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_4,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_pclk0_clk_src",
|
||||
.parent_data = disp_cc_parent_data_4,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
|
||||
/* For set_rate and set_parent to succeed, parent(s) must be enabled */
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
|
||||
.ops = &clk_pixel_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
|
||||
.cmd_rcgr = 0x208c,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_vsync_clk_src",
|
||||
.parent_data = disp_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
|
||||
F(32764, P_SLEEP_CLK, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_sleep_clk_src = {
|
||||
.cmd_rcgr = 0x6050,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_5,
|
||||
.freq_tbl = ftbl_disp_cc_sleep_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_sleep_clk_src",
|
||||
.parent_data = disp_cc_parent_data_5,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_ahb_clk = {
|
||||
.halt_reg = 0x2044,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2044,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_byte0_clk = {
|
||||
.halt_reg = 0x201c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x201c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_byte0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_byte0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
|
||||
.halt_reg = 0x2020,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2020,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_byte0_intf_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_esc0_clk = {
|
||||
.halt_reg = 0x2024,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2024,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_esc0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_esc0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_mdp_clk = {
|
||||
.halt_reg = 0x2008,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2008,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_mdp_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
|
||||
.halt_reg = 0x2010,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2010,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_mdp_lut_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
|
||||
.halt_reg = 0x4004,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x4004,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_non_gdsc_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_pclk0_clk = {
|
||||
.halt_reg = 0x2004,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2004,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_pclk0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_vsync_clk = {
|
||||
.halt_reg = 0x2018,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2018,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_vsync_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_vsync_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_sleep_clk = {
|
||||
.halt_reg = 0x6068,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x6068,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_sleep_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_sleep_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct gdsc mdss_gdsc = {
|
||||
.gdscr = 0x3000,
|
||||
.pd = {
|
||||
.name = "mdss_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = HW_CTRL,
|
||||
};
|
||||
|
||||
static struct gdsc *disp_cc_qcm2290_gdscs[] = {
|
||||
[MDSS_GDSC] = &mdss_gdsc,
|
||||
};
|
||||
|
||||
static struct clk_regmap *disp_cc_qcm2290_clocks[] = {
|
||||
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
|
||||
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
|
||||
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
|
||||
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
|
||||
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
|
||||
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
|
||||
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
|
||||
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
|
||||
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
|
||||
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
|
||||
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
|
||||
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
|
||||
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
|
||||
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
|
||||
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
|
||||
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
|
||||
[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
|
||||
[DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
|
||||
[DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
|
||||
};
|
||||
|
||||
static const struct regmap_config disp_cc_qcm2290_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x10000,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc disp_cc_qcm2290_desc = {
|
||||
.config = &disp_cc_qcm2290_regmap_config,
|
||||
.clks = disp_cc_qcm2290_clocks,
|
||||
.num_clks = ARRAY_SIZE(disp_cc_qcm2290_clocks),
|
||||
.gdscs = disp_cc_qcm2290_gdscs,
|
||||
.num_gdscs = ARRAY_SIZE(disp_cc_qcm2290_gdscs),
|
||||
};
|
||||
|
||||
static const struct of_device_id disp_cc_qcm2290_match_table[] = {
|
||||
{ .compatible = "qcom,qcm2290-dispcc" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, disp_cc_qcm2290_match_table);
|
||||
|
||||
static int disp_cc_qcm2290_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int ret;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &disp_cc_qcm2290_desc);
|
||||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
|
||||
|
||||
/* Keep DISP_CC_XO_CLK always-ON */
|
||||
regmap_update_bits(regmap, 0x604c, BIT(0), BIT(0));
|
||||
|
||||
ret = qcom_cc_really_probe(pdev, &disp_cc_qcm2290_desc, regmap);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to register DISP CC clocks\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct platform_driver disp_cc_qcm2290_driver = {
|
||||
.probe = disp_cc_qcm2290_probe,
|
||||
.driver = {
|
||||
.name = "dispcc-qcm2290",
|
||||
.of_match_table = disp_cc_qcm2290_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init disp_cc_qcm2290_init(void)
|
||||
{
|
||||
return platform_driver_register(&disp_cc_qcm2290_driver);
|
||||
}
|
||||
subsys_initcall(disp_cc_qcm2290_init);
|
||||
|
||||
static void __exit disp_cc_qcm2290_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&disp_cc_qcm2290_driver);
|
||||
}
|
||||
module_exit(disp_cc_qcm2290_exit);
|
||||
|
||||
MODULE_DESCRIPTION("QTI DISP_CC qcm2290 Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
709
drivers/clk/qcom/dispcc-sm6125.c
Normal file
709
drivers/clk/qcom/dispcc-sm6125.c
Normal file
@ -0,0 +1,709 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,dispcc-sm6125.h>
|
||||
|
||||
#include "clk-alpha-pll.h"
|
||||
#include "clk-branch.h"
|
||||
#include "clk-rcg.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "common.h"
|
||||
#include "gdsc.h"
|
||||
|
||||
enum {
|
||||
P_BI_TCXO,
|
||||
P_DISP_CC_PLL0_OUT_MAIN,
|
||||
P_DP_PHY_PLL_LINK_CLK,
|
||||
P_DP_PHY_PLL_VCO_DIV_CLK,
|
||||
P_DSI0_PHY_PLL_OUT_BYTECLK,
|
||||
P_DSI0_PHY_PLL_OUT_DSICLK,
|
||||
P_DSI1_PHY_PLL_OUT_DSICLK,
|
||||
P_GPLL0_OUT_MAIN,
|
||||
};
|
||||
|
||||
static struct pll_vco disp_cc_pll_vco[] = {
|
||||
{ 500000000, 1000000000, 2 },
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll disp_cc_pll0 = {
|
||||
.offset = 0x0,
|
||||
.vco_table = disp_cc_pll_vco,
|
||||
.num_vco = ARRAY_SIZE(disp_cc_pll_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
|
||||
.flags = SUPPORTS_DYNAMIC_UPDATE,
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_pll0",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.fw_name = "bi_tcxo",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* 768MHz configuration */
|
||||
static const struct alpha_pll_config disp_cc_pll0_config = {
|
||||
.l = 0x28,
|
||||
.vco_val = 0x2 << 20,
|
||||
.vco_mask = 0x3 << 20,
|
||||
.main_output_mask = BIT(0),
|
||||
.config_ctl_val = 0x4001055b,
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_0[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_0[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_1[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_DP_PHY_PLL_LINK_CLK, 1 },
|
||||
{ P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_1[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .fw_name = "dp_phy_pll_link_clk" },
|
||||
{ .fw_name = "dp_phy_pll_vco_div_clk" },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_2[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_2[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .fw_name = "dsi0_phy_pll_out_byteclk" },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_3[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
|
||||
{ P_GPLL0_OUT_MAIN, 4 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_3[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .hw = &disp_cc_pll0.clkr.hw },
|
||||
{ .fw_name = "gcc_disp_gpll0_div_clk_src" },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_4[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPLL0_OUT_MAIN, 4 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_4[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .fw_name = "gcc_disp_gpll0_div_clk_src" },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_5[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
|
||||
{ P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_5[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .fw_name = "dsi0_phy_pll_out_dsiclk" },
|
||||
{ .fw_name = "dsi1_phy_pll_out_dsiclk" },
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
|
||||
F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
|
||||
.cmd_rcgr = 0x2154,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_4,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_ahb_clk_src",
|
||||
.parent_data = disp_cc_parent_data_4,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
|
||||
.cmd_rcgr = 0x20bc,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_2,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_byte0_clk_src",
|
||||
.parent_data = disp_cc_parent_data_2,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_byte2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux1_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
|
||||
.cmd_rcgr = 0x213c,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_aux_clk_src",
|
||||
.parent_data = disp_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = {
|
||||
F( 180000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0),
|
||||
F( 360000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
|
||||
.cmd_rcgr = 0x210c,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_crypto_clk_src",
|
||||
.parent_data = disp_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
||||
.flags = CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = {
|
||||
F( 162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
|
||||
F( 270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
|
||||
F( 540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
|
||||
.cmd_rcgr = 0x20f0,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_link_clk_src",
|
||||
.parent_data = disp_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
|
||||
.cmd_rcgr = 0x2124,
|
||||
.mnd_width = 16,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_1,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_pixel_clk_src",
|
||||
.parent_data = disp_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_dp_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
|
||||
.cmd_rcgr = 0x20d8,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_2,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_esc0_clk_src",
|
||||
.parent_data = disp_cc_parent_data_2,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
|
||||
F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
||||
F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
|
||||
F(384000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
|
||||
F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
|
||||
.cmd_rcgr = 0x2074,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_3,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_mdp_clk_src",
|
||||
.parent_data = disp_cc_parent_data_3,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
|
||||
.cmd_rcgr = 0x205c,
|
||||
.mnd_width = 8,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_5,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_pclk0_clk_src",
|
||||
.parent_data = disp_cc_parent_data_5,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_pixel_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
|
||||
F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
||||
F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
|
||||
.cmd_rcgr = 0x208c,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_3,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_rot_clk_src",
|
||||
.parent_data = disp_cc_parent_data_3,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
|
||||
.cmd_rcgr = 0x20a4,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_vsync_clk_src",
|
||||
.parent_data = disp_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_ahb_clk = {
|
||||
.halt_reg = 0x2044,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2044,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_byte0_clk = {
|
||||
.halt_reg = 0x2024,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2024,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_byte0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_byte0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
|
||||
.halt_reg = 0x2028,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2028,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_byte0_intf_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_byte0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_dp_aux_clk = {
|
||||
.halt_reg = 0x2040,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2040,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_aux_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_dp_aux_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
|
||||
.halt_reg = 0x2038,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2038,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_crypto_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_dp_link_clk = {
|
||||
.halt_reg = 0x2030,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2030,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_link_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_dp_link_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
|
||||
.halt_reg = 0x2034,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2034,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_link_intf_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_dp_link_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
|
||||
.halt_reg = 0x203c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x203c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_pixel_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_esc0_clk = {
|
||||
.halt_reg = 0x202c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x202c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_esc0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_esc0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_mdp_clk = {
|
||||
.halt_reg = 0x2008,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2008,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_mdp_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
|
||||
.halt_reg = 0x2018,
|
||||
.halt_check = BRANCH_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2018,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_mdp_lut_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
|
||||
.halt_reg = 0x4004,
|
||||
.halt_check = BRANCH_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x4004,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_non_gdsc_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_pclk0_clk = {
|
||||
.halt_reg = 0x2004,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2004,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_pclk0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_rot_clk = {
|
||||
.halt_reg = 0x2010,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2010,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_rot_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_rot_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_vsync_clk = {
|
||||
.halt_reg = 0x2020,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2020,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_vsync_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_vsync_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_xo_clk = {
|
||||
.halt_reg = 0x604c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x604c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_xo_clk",
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct gdsc mdss_gdsc = {
|
||||
.gdscr = 0x3000,
|
||||
.pd = {
|
||||
.name = "mdss_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = HW_CTRL,
|
||||
};
|
||||
|
||||
static struct clk_regmap *disp_cc_sm6125_clocks[] = {
|
||||
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
|
||||
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
|
||||
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
|
||||
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
|
||||
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
|
||||
[DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
|
||||
[DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
|
||||
[DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
|
||||
[DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr,
|
||||
[DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
|
||||
[DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
|
||||
[DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
|
||||
[DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
|
||||
[DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
|
||||
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
|
||||
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
|
||||
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
|
||||
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
|
||||
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
|
||||
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
|
||||
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
|
||||
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
|
||||
[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
|
||||
[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
|
||||
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
|
||||
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
|
||||
[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
|
||||
[DISP_CC_XO_CLK] = &disp_cc_xo_clk.clkr,
|
||||
};
|
||||
|
||||
static struct gdsc *disp_cc_sm6125_gdscs[] = {
|
||||
[MDSS_GDSC] = &mdss_gdsc,
|
||||
};
|
||||
|
||||
static const struct regmap_config disp_cc_sm6125_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x10000,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc disp_cc_sm6125_desc = {
|
||||
.config = &disp_cc_sm6125_regmap_config,
|
||||
.clks = disp_cc_sm6125_clocks,
|
||||
.num_clks = ARRAY_SIZE(disp_cc_sm6125_clocks),
|
||||
.gdscs = disp_cc_sm6125_gdscs,
|
||||
.num_gdscs = ARRAY_SIZE(disp_cc_sm6125_gdscs),
|
||||
};
|
||||
|
||||
static const struct of_device_id disp_cc_sm6125_match_table[] = {
|
||||
{ .compatible = "qcom,dispcc-sm6125" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, disp_cc_sm6125_match_table);
|
||||
|
||||
static int disp_cc_sm6125_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &disp_cc_sm6125_desc);
|
||||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
|
||||
|
||||
return qcom_cc_really_probe(pdev, &disp_cc_sm6125_desc, regmap);
|
||||
}
|
||||
|
||||
static struct platform_driver disp_cc_sm6125_driver = {
|
||||
.probe = disp_cc_sm6125_probe,
|
||||
.driver = {
|
||||
.name = "disp_cc-sm6125",
|
||||
.of_match_table = disp_cc_sm6125_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init disp_cc_sm6125_init(void)
|
||||
{
|
||||
return platform_driver_register(&disp_cc_sm6125_driver);
|
||||
}
|
||||
subsys_initcall(disp_cc_sm6125_init);
|
||||
|
||||
static void __exit disp_cc_sm6125_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&disp_cc_sm6125_driver);
|
||||
}
|
||||
module_exit(disp_cc_sm6125_exit);
|
||||
|
||||
MODULE_DESCRIPTION("QTI DISPCC SM6125 Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
797
drivers/clk/qcom/dispcc-sm6350.c
Normal file
797
drivers/clk/qcom/dispcc-sm6350.c
Normal file
@ -0,0 +1,797 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,dispcc-sm6350.h>
|
||||
|
||||
#include "clk-alpha-pll.h"
|
||||
#include "clk-branch.h"
|
||||
#include "clk-rcg.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "clk-regmap-divider.h"
|
||||
#include "common.h"
|
||||
#include "gdsc.h"
|
||||
#include "reset.h"
|
||||
|
||||
enum {
|
||||
P_BI_TCXO,
|
||||
P_DISP_CC_PLL0_OUT_EVEN,
|
||||
P_DISP_CC_PLL0_OUT_MAIN,
|
||||
P_DP_PHY_PLL_LINK_CLK,
|
||||
P_DP_PHY_PLL_VCO_DIV_CLK,
|
||||
P_DSI0_PHY_PLL_OUT_BYTECLK,
|
||||
P_DSI0_PHY_PLL_OUT_DSICLK,
|
||||
P_GCC_DISP_GPLL0_CLK,
|
||||
};
|
||||
|
||||
static struct pll_vco fabia_vco[] = {
|
||||
{ 249600000, 2000000000, 0 },
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config disp_cc_pll0_config = {
|
||||
.l = 0x3a,
|
||||
.alpha = 0x5555,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00002067,
|
||||
.test_ctl_val = 0x40000000,
|
||||
.test_ctl_hi_val = 0x00000002,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00004805,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll disp_cc_pll0 = {
|
||||
.offset = 0x0,
|
||||
.vco_table = fabia_vco,
|
||||
.num_vco = ARRAY_SIZE(fabia_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_pll0",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.fw_name = "bi_tcxo",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_fabia_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_0[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_DP_PHY_PLL_LINK_CLK, 1 },
|
||||
{ P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_0[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .fw_name = "dp_phy_pll_link_clk" },
|
||||
{ .fw_name = "dp_phy_pll_vco_div_clk" },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_1[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_1[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .fw_name = "dsi0_phy_pll_out_byteclk" },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_3[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
|
||||
{ P_GCC_DISP_GPLL0_CLK, 4 },
|
||||
{ P_DISP_CC_PLL0_OUT_EVEN, 5 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_3[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .hw = &disp_cc_pll0.clkr.hw },
|
||||
{ .fw_name = "gcc_disp_gpll0_clk" },
|
||||
{ .hw = &disp_cc_pll0.clkr.hw },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_4[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GCC_DISP_GPLL0_CLK, 4 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_4[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .fw_name = "gcc_disp_gpll0_clk" },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_5[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_5[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .fw_name = "dsi0_phy_pll_out_dsiclk" },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_6[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_6[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
F(37500000, P_GCC_DISP_GPLL0_CLK, 16, 0, 0),
|
||||
F(75000000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
|
||||
.cmd_rcgr = 0x115c,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_4,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_ahb_clk_src",
|
||||
.parent_data = disp_cc_parent_data_4,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
|
||||
.cmd_rcgr = 0x10c4,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_1,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_byte0_clk_src",
|
||||
.parent_data = disp_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_byte2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
|
||||
.reg = 0x10dc,
|
||||
.shift = 0,
|
||||
.width = 2,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_byte0_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_byte0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
|
||||
.cmd_rcgr = 0x1144,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_aux_clk_src",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.fw_name = "bi_tcxo",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = {
|
||||
F(108000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
|
||||
F(180000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
|
||||
F(360000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0),
|
||||
F(540000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
|
||||
.cmd_rcgr = 0x1114,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_crypto_clk_src",
|
||||
.parent_data = disp_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
||||
.flags = CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = {
|
||||
F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
|
||||
F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
|
||||
F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
|
||||
F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
|
||||
.cmd_rcgr = 0x10f8,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_link_clk_src",
|
||||
.parent_data = disp_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
|
||||
.cmd_rcgr = 0x112c,
|
||||
.mnd_width = 16,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_0,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_pixel_clk_src",
|
||||
.parent_data = disp_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_dp_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
|
||||
.cmd_rcgr = 0x10e0,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_esc0_clk_src",
|
||||
.parent_data = disp_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
F(200000000, P_GCC_DISP_GPLL0_CLK, 3, 0, 0),
|
||||
F(300000000, P_GCC_DISP_GPLL0_CLK, 2, 0, 0),
|
||||
F(373333333, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
||||
F(448000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
|
||||
F(560000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
|
||||
.cmd_rcgr = 0x107c,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_3,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_mdp_clk_src",
|
||||
.parent_data = disp_cc_parent_data_3,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
|
||||
.cmd_rcgr = 0x1064,
|
||||
.mnd_width = 8,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_5,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_pclk0_clk_src",
|
||||
.parent_data = disp_cc_parent_data_5,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_pixel_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
|
||||
.cmd_rcgr = 0x1094,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_3,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_rot_clk_src",
|
||||
.parent_data = disp_cc_parent_data_3,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
|
||||
.cmd_rcgr = 0x10ac,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = disp_cc_parent_map_6,
|
||||
.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_vsync_clk_src",
|
||||
.parent_data = disp_cc_parent_data_6,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
|
||||
.reg = 0x1110,
|
||||
.shift = 0,
|
||||
.width = 2,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.name = "disp_cc_mdss_dp_link_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_dp_link_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_ahb_clk = {
|
||||
.halt_reg = 0x104c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x104c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_byte0_clk = {
|
||||
.halt_reg = 0x102c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x102c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_byte0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_byte0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
|
||||
.halt_reg = 0x1030,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1030,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_byte0_intf_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_dp_aux_clk = {
|
||||
.halt_reg = 0x1048,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1048,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_aux_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_dp_aux_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
|
||||
.halt_reg = 0x1040,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1040,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_crypto_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_dp_link_clk = {
|
||||
.halt_reg = 0x1038,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1038,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_link_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_dp_link_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
|
||||
.halt_reg = 0x103c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x103c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_link_intf_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
|
||||
.halt_reg = 0x1044,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1044,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_pixel_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_esc0_clk = {
|
||||
.halt_reg = 0x1034,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1034,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_esc0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_esc0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_mdp_clk = {
|
||||
.halt_reg = 0x1010,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1010,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_mdp_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
|
||||
.halt_reg = 0x1020,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1020,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_mdp_lut_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
|
||||
.halt_reg = 0x2004,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2004,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_non_gdsc_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_pclk0_clk = {
|
||||
.halt_reg = 0x100c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x100c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_pclk0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_rot_clk = {
|
||||
.halt_reg = 0x1018,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1018,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_rot_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_rot_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
|
||||
.halt_reg = 0x200c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x200c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_rscc_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
|
||||
.halt_reg = 0x2008,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x2008,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_rscc_vsync_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_vsync_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_mdss_vsync_clk = {
|
||||
.halt_reg = 0x1028,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1028,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_vsync_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_vsync_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_sleep_clk = {
|
||||
.halt_reg = 0x5004,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x5004,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_sleep_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch disp_cc_xo_clk = {
|
||||
.halt_reg = 0x5008,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x5008,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_xo_clk",
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct gdsc mdss_gdsc = {
|
||||
.gdscr = 0x1004,
|
||||
.pd = {
|
||||
.name = "mdss_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct clk_regmap *disp_cc_sm6350_clocks[] = {
|
||||
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
|
||||
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
|
||||
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
|
||||
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
|
||||
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
|
||||
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
|
||||
[DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
|
||||
[DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
|
||||
[DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
|
||||
[DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr,
|
||||
[DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
|
||||
[DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
|
||||
[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] =
|
||||
&disp_cc_mdss_dp_link_div_clk_src.clkr,
|
||||
[DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
|
||||
[DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
|
||||
[DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
|
||||
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
|
||||
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
|
||||
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
|
||||
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
|
||||
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
|
||||
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
|
||||
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
|
||||
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
|
||||
[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
|
||||
[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
|
||||
[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
|
||||
[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
|
||||
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
|
||||
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
|
||||
[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
|
||||
[DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
|
||||
[DISP_CC_XO_CLK] = &disp_cc_xo_clk.clkr,
|
||||
};
|
||||
|
||||
static struct gdsc *disp_cc_sm6350_gdscs[] = {
|
||||
[MDSS_GDSC] = &mdss_gdsc,
|
||||
};
|
||||
|
||||
static const struct regmap_config disp_cc_sm6350_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x10000,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc disp_cc_sm6350_desc = {
|
||||
.config = &disp_cc_sm6350_regmap_config,
|
||||
.clks = disp_cc_sm6350_clocks,
|
||||
.num_clks = ARRAY_SIZE(disp_cc_sm6350_clocks),
|
||||
.gdscs = disp_cc_sm6350_gdscs,
|
||||
.num_gdscs = ARRAY_SIZE(disp_cc_sm6350_gdscs),
|
||||
};
|
||||
|
||||
static const struct of_device_id disp_cc_sm6350_match_table[] = {
|
||||
{ .compatible = "qcom,sm6350-dispcc" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, disp_cc_sm6350_match_table);
|
||||
|
||||
static int disp_cc_sm6350_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &disp_cc_sm6350_desc);
|
||||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
|
||||
|
||||
return qcom_cc_really_probe(pdev, &disp_cc_sm6350_desc, regmap);
|
||||
}
|
||||
|
||||
static struct platform_driver disp_cc_sm6350_driver = {
|
||||
.probe = disp_cc_sm6350_probe,
|
||||
.driver = {
|
||||
.name = "disp_cc-sm6350",
|
||||
.of_match_table = disp_cc_sm6350_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init disp_cc_sm6350_init(void)
|
||||
{
|
||||
return platform_driver_register(&disp_cc_sm6350_driver);
|
||||
}
|
||||
subsys_initcall(disp_cc_sm6350_init);
|
||||
|
||||
static void __exit disp_cc_sm6350_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&disp_cc_sm6350_driver);
|
||||
}
|
||||
module_exit(disp_cc_sm6350_exit);
|
||||
|
||||
MODULE_DESCRIPTION("QTI DISP_CC SM6350 Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
File diff suppressed because it is too large
Load Diff
@ -60,11 +60,6 @@ static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
|
||||
{ P_GPLL0_DIV2, 4 },
|
||||
};
|
||||
|
||||
static const char * const gcc_xo_gpll0[] = {
|
||||
"xo",
|
||||
"gpll0",
|
||||
};
|
||||
|
||||
static const struct parent_map gcc_xo_gpll0_map[] = {
|
||||
{ P_XO, 0 },
|
||||
{ P_GPLL0, 1 },
|
||||
@ -956,6 +951,11 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gcc_xo_gpll0[] = {
|
||||
{ .fw_name = "xo" },
|
||||
{ .hw = &gpll0.clkr.hw },
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
F(200000000, P_GPLL0, 4, 0, 0),
|
||||
@ -969,7 +969,7 @@ static struct clk_rcg2 pcie0_axi_clk_src = {
|
||||
.parent_map = gcc_xo_gpll0_map,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "pcie0_axi_clk_src",
|
||||
.parent_names = gcc_xo_gpll0,
|
||||
.parent_data = gcc_xo_gpll0,
|
||||
.num_parents = 2,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -1016,7 +1016,7 @@ static struct clk_rcg2 pcie1_axi_clk_src = {
|
||||
.parent_map = gcc_xo_gpll0_map,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "pcie1_axi_clk_src",
|
||||
.parent_names = gcc_xo_gpll0,
|
||||
.parent_data = gcc_xo_gpll0,
|
||||
.num_parents = 2,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -1074,7 +1074,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
|
||||
.name = "sdcc1_apps_clk_src",
|
||||
.parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
|
||||
.num_parents = 4,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_floor_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -1330,7 +1330,7 @@ static struct clk_rcg2 nss_ce_clk_src = {
|
||||
.parent_map = gcc_xo_gpll0_map,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "nss_ce_clk_src",
|
||||
.parent_names = gcc_xo_gpll0,
|
||||
.parent_data = gcc_xo_gpll0,
|
||||
.num_parents = 2,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -4329,8 +4329,7 @@ static struct clk_rcg2 pcie0_rchng_clk_src = {
|
||||
.parent_map = gcc_xo_gpll0_map,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "pcie0_rchng_clk_src",
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&gpll0.clkr.hw },
|
||||
.parent_data = gcc_xo_gpll0,
|
||||
.num_parents = 2,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -3448,22 +3448,67 @@ static struct clk_branch gcc_video_xo_clk = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct gdsc pcie_0_gdsc = {
|
||||
.gdscr = 0x6b004,
|
||||
.pd = {
|
||||
.name = "pcie_0_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = POLL_CFG_GDSCR,
|
||||
};
|
||||
|
||||
static struct gdsc pcie_1_gdsc = {
|
||||
.gdscr = 0x8d004,
|
||||
.pd = {
|
||||
.name = "pcie_1_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = POLL_CFG_GDSCR,
|
||||
};
|
||||
|
||||
static struct gdsc ufs_card_gdsc = {
|
||||
.gdscr = 0x75004,
|
||||
.pd = {
|
||||
.name = "ufs_card_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = POLL_CFG_GDSCR,
|
||||
};
|
||||
|
||||
static struct gdsc ufs_phy_gdsc = {
|
||||
.gdscr = 0x77004,
|
||||
.pd = {
|
||||
.name = "ufs_phy_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = POLL_CFG_GDSCR,
|
||||
};
|
||||
|
||||
static struct gdsc emac_gdsc = {
|
||||
.gdscr = 0x6004,
|
||||
.pd = {
|
||||
.name = "emac_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = POLL_CFG_GDSCR,
|
||||
};
|
||||
|
||||
static struct gdsc usb30_prim_gdsc = {
|
||||
.gdscr = 0xf004,
|
||||
.pd = {
|
||||
.name = "usb30_prim_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = POLL_CFG_GDSCR,
|
||||
.gdscr = 0xf004,
|
||||
.pd = {
|
||||
.name = "usb30_prim_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = POLL_CFG_GDSCR,
|
||||
};
|
||||
|
||||
static struct gdsc usb30_sec_gdsc = {
|
||||
.gdscr = 0x10004,
|
||||
.pd = {
|
||||
.name = "usb30_sec_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = POLL_CFG_GDSCR,
|
||||
.gdscr = 0x10004,
|
||||
.pd = {
|
||||
.name = "usb30_sec_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = POLL_CFG_GDSCR,
|
||||
};
|
||||
|
||||
static struct clk_regmap *gcc_sm8150_clocks[] = {
|
||||
@ -3714,6 +3759,11 @@ static const struct qcom_reset_map gcc_sm8150_resets[] = {
|
||||
};
|
||||
|
||||
static struct gdsc *gcc_sm8150_gdscs[] = {
|
||||
[EMAC_GDSC] = &emac_gdsc,
|
||||
[PCIE_0_GDSC] = &pcie_0_gdsc,
|
||||
[PCIE_1_GDSC] = &pcie_1_gdsc,
|
||||
[UFS_CARD_GDSC] = &ufs_card_gdsc,
|
||||
[UFS_PHY_GDSC] = &ufs_phy_gdsc,
|
||||
[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
|
||||
[USB30_SEC_GDSC] = &usb30_sec_gdsc,
|
||||
};
|
||||
|
||||
@ -29,7 +29,6 @@
|
||||
|
||||
enum {
|
||||
P_GPU_XO,
|
||||
P_CORE_BI_PLL_TEST_SE,
|
||||
P_GPLL0_OUT_MAIN,
|
||||
P_GPLL0_OUT_MAIN_DIV,
|
||||
P_GPU_PLL0_PLL_OUT_MAIN,
|
||||
@ -66,8 +65,8 @@ static struct clk_alpha_pll gpu_pll0_pll_out_main = {
|
||||
.num_vco = ARRAY_SIZE(gpu_vco),
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_pll0_pll_out_main",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gpucc_cxo_clk.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpucc_cxo_clk.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_ops,
|
||||
@ -81,8 +80,8 @@ static struct clk_alpha_pll gpu_pll1_pll_out_main = {
|
||||
.num_vco = ARRAY_SIZE(gpu_vco),
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_pll1_pll_out_main",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gpucc_cxo_clk.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpucc_cxo_clk.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_ops,
|
||||
@ -135,8 +134,8 @@ static struct clk_branch gpucc_gfx3d_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpucc_gfx3d_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gfx3d_clk_src.rcg.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gfx3d_clk_src.rcg.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch2_ops,
|
||||
@ -204,8 +203,8 @@ static struct clk_branch gpucc_rbbmtimer_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpucc_rbbmtimer_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"rbbmtimer_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&rbbmtimer_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -222,8 +221,8 @@ static struct clk_branch gpucc_rbcpr_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpucc_rbcpr_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"rbcpr_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&rbcpr_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
||||
521
drivers/clk/qcom/gpucc-sm6350.c
Normal file
521
drivers/clk/qcom/gpucc-sm6350.c
Normal file
@ -0,0 +1,521 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,gpucc-sm6350.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "clk-alpha-pll.h"
|
||||
#include "clk-branch.h"
|
||||
#include "clk-rcg.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "reset.h"
|
||||
#include "gdsc.h"
|
||||
|
||||
#define CX_GMU_CBCR_SLEEP_MASK 0xF
|
||||
#define CX_GMU_CBCR_SLEEP_SHIFT 4
|
||||
#define CX_GMU_CBCR_WAKE_MASK 0xF
|
||||
#define CX_GMU_CBCR_WAKE_SHIFT 8
|
||||
|
||||
enum {
|
||||
P_BI_TCXO,
|
||||
P_GPLL0_OUT_MAIN,
|
||||
P_GPLL0_OUT_MAIN_DIV,
|
||||
P_GPU_CC_PLL0_OUT_MAIN,
|
||||
P_GPU_CC_PLL0_OUT_ODD,
|
||||
P_GPU_CC_PLL1_OUT_EVEN,
|
||||
P_GPU_CC_PLL1_OUT_MAIN,
|
||||
P_GPU_CC_PLL1_OUT_ODD,
|
||||
P_CRC_DIV,
|
||||
};
|
||||
|
||||
static const struct pll_vco fabia_vco[] = {
|
||||
{ 249600000, 2000000000, 0 },
|
||||
};
|
||||
|
||||
/* 506MHz Configuration*/
|
||||
static const struct alpha_pll_config gpu_cc_pll0_config = {
|
||||
.l = 0x1A,
|
||||
.alpha = 0x5AAA,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00002067,
|
||||
.test_ctl_val = 0x40000000,
|
||||
.test_ctl_hi_val = 0x00000002,
|
||||
.user_ctl_val = 0x00000001,
|
||||
.user_ctl_hi_val = 0x00004805,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll gpu_cc_pll0 = {
|
||||
.offset = 0x0,
|
||||
.vco_table = fabia_vco,
|
||||
.num_vco = ARRAY_SIZE(fabia_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_pll0",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.fw_name = "bi_tcxo",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_fabia_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor crc_div = {
|
||||
.mult = 1,
|
||||
.div = 2,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "crc_div",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_pll0.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
},
|
||||
};
|
||||
|
||||
/* 514MHz Configuration*/
|
||||
static const struct alpha_pll_config gpu_cc_pll1_config = {
|
||||
.l = 0x1A,
|
||||
.alpha = 0xC555,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00002067,
|
||||
.test_ctl_val = 0x40000000,
|
||||
.test_ctl_hi_val = 0x00000002,
|
||||
.user_ctl_val = 0x00000001,
|
||||
.user_ctl_hi_val = 0x00004805,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll gpu_cc_pll1 = {
|
||||
.offset = 0x100,
|
||||
.vco_table = fabia_vco,
|
||||
.num_vco = ARRAY_SIZE(fabia_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_pll1",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.fw_name = "bi_tcxo",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_fabia_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_0[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
|
||||
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
|
||||
{ P_GPLL0_OUT_MAIN, 5 },
|
||||
{ P_GPLL0_OUT_MAIN_DIV, 6 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .hw = &gpu_cc_pll0.clkr.hw },
|
||||
{ .hw = &gpu_cc_pll1.clkr.hw },
|
||||
{ .fw_name = "gcc_gpu_gpll0_clk" },
|
||||
{ .fw_name = "gcc_gpu_gpll0_div_clk" },
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_1[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_CRC_DIV, 1 },
|
||||
{ P_GPU_CC_PLL0_OUT_ODD, 2 },
|
||||
{ P_GPU_CC_PLL1_OUT_EVEN, 3 },
|
||||
{ P_GPU_CC_PLL1_OUT_ODD, 4 },
|
||||
{ P_GPLL0_OUT_MAIN, 5 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .hw = &crc_div.hw },
|
||||
{ .hw = &gpu_cc_pll0.clkr.hw },
|
||||
{ .hw = &gpu_cc_pll1.clkr.hw },
|
||||
{ .hw = &gpu_cc_pll1.clkr.hw },
|
||||
{ .fw_name = "gcc_gpu_gpll0_clk" },
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
|
||||
F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
|
||||
.cmd_rcgr = 0x1120,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gmu_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
|
||||
F(253000000, P_CRC_DIV, 1, 0, 0),
|
||||
F(355000000, P_CRC_DIV, 1, 0, 0),
|
||||
F(430000000, P_CRC_DIV, 1, 0, 0),
|
||||
F(565000000, P_CRC_DIV, 1, 0, 0),
|
||||
F(650000000, P_CRC_DIV, 1, 0, 0),
|
||||
F(800000000, P_CRC_DIV, 1, 0, 0),
|
||||
F(825000000, P_CRC_DIV, 1, 0, 0),
|
||||
F(850000000, P_CRC_DIV, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
|
||||
.cmd_rcgr = 0x101c,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_gfx3d_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_acd_ahb_clk = {
|
||||
.halt_reg = 0x1168,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1168,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_acd_ahb_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_acd_cxo_clk = {
|
||||
.halt_reg = 0x1164,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1164,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_acd_cxo_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_ahb_clk = {
|
||||
.halt_reg = 0x1078,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1078,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_ahb_clk",
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_crc_ahb_clk = {
|
||||
.halt_reg = 0x107c,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x107c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_crc_ahb_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_gfx3d_clk = {
|
||||
.halt_reg = 0x10a4,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x10a4,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cx_gfx3d_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_gfx3d_slv_clk = {
|
||||
.halt_reg = 0x10a8,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x10a8,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cx_gfx3d_slv_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_gmu_clk = {
|
||||
.halt_reg = 0x1098,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1098,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cx_gmu_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_gmu_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
|
||||
.halt_reg = 0x108c,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x108c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cx_snoc_dvm_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cxo_aon_clk = {
|
||||
.halt_reg = 0x1004,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1004,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cxo_aon_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cxo_clk = {
|
||||
.halt_reg = 0x109c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x109c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cxo_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_cxo_clk = {
|
||||
.halt_reg = 0x1060,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1060,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_cxo_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_gfx3d_clk = {
|
||||
.halt_reg = 0x1054,
|
||||
.halt_check = BRANCH_HALT_SKIP,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1054,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_gfx3d_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_gmu_clk = {
|
||||
.halt_reg = 0x1064,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1064,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_gmu_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_gmu_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_vsense_clk = {
|
||||
.halt_reg = 0x1058,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1058,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_vsense_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct gdsc gpu_cx_gdsc = {
|
||||
.gdscr = 0x106c,
|
||||
.gds_hw_ctrl = 0x1540,
|
||||
.pd = {
|
||||
.name = "gpu_cx_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = VOTABLE,
|
||||
};
|
||||
|
||||
static struct gdsc gpu_gx_gdsc = {
|
||||
.gdscr = 0x100c,
|
||||
.clamp_io_ctrl = 0x1508,
|
||||
.pd = {
|
||||
.name = "gpu_gx_gdsc",
|
||||
.power_on = gdsc_gx_do_nothing_enable,
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = CLAMP_IO | POLL_CFG_GDSCR,
|
||||
};
|
||||
|
||||
static struct clk_hw *gpu_cc_sm6350_hws[] = {
|
||||
[GPU_CC_CRC_DIV] = &crc_div.hw,
|
||||
};
|
||||
|
||||
static struct clk_regmap *gpu_cc_sm6350_clocks[] = {
|
||||
[GPU_CC_ACD_AHB_CLK] = &gpu_cc_acd_ahb_clk.clkr,
|
||||
[GPU_CC_ACD_CXO_CLK] = &gpu_cc_acd_cxo_clk.clkr,
|
||||
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
|
||||
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
|
||||
[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
|
||||
[GPU_CC_CX_GFX3D_SLV_CLK] = &gpu_cc_cx_gfx3d_slv_clk.clkr,
|
||||
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
|
||||
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
|
||||
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
|
||||
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
|
||||
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
|
||||
[GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr,
|
||||
[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
|
||||
[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
|
||||
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
|
||||
[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
|
||||
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
|
||||
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
|
||||
};
|
||||
|
||||
static struct gdsc *gpu_cc_sm6350_gdscs[] = {
|
||||
[GPU_CX_GDSC] = &gpu_cx_gdsc,
|
||||
[GPU_GX_GDSC] = &gpu_gx_gdsc,
|
||||
};
|
||||
|
||||
static const struct regmap_config gpu_cc_sm6350_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x8008,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc gpu_cc_sm6350_desc = {
|
||||
.config = &gpu_cc_sm6350_regmap_config,
|
||||
.clk_hws = gpu_cc_sm6350_hws,
|
||||
.num_clk_hws = ARRAY_SIZE(gpu_cc_sm6350_hws),
|
||||
.clks = gpu_cc_sm6350_clocks,
|
||||
.num_clks = ARRAY_SIZE(gpu_cc_sm6350_clocks),
|
||||
.gdscs = gpu_cc_sm6350_gdscs,
|
||||
.num_gdscs = ARRAY_SIZE(gpu_cc_sm6350_gdscs),
|
||||
};
|
||||
|
||||
static const struct of_device_id gpu_cc_sm6350_match_table[] = {
|
||||
{ .compatible = "qcom,sm6350-gpucc" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, gpu_cc_sm6350_match_table);
|
||||
|
||||
static int gpu_cc_sm6350_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
unsigned int value, mask;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &gpu_cc_sm6350_desc);
|
||||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
clk_fabia_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
|
||||
clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
|
||||
|
||||
/* Configure gpu_cc_cx_gmu_clk with recommended wakeup/sleep settings */
|
||||
mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
|
||||
mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
|
||||
value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT;
|
||||
regmap_update_bits(regmap, 0x1098, mask, value);
|
||||
|
||||
return qcom_cc_really_probe(pdev, &gpu_cc_sm6350_desc, regmap);
|
||||
}
|
||||
|
||||
static struct platform_driver gpu_cc_sm6350_driver = {
|
||||
.probe = gpu_cc_sm6350_probe,
|
||||
.driver = {
|
||||
.name = "sm6350-gpucc",
|
||||
.of_match_table = gpu_cc_sm6350_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init gpu_cc_sm6350_init(void)
|
||||
{
|
||||
return platform_driver_register(&gpu_cc_sm6350_driver);
|
||||
}
|
||||
core_initcall(gpu_cc_sm6350_init);
|
||||
|
||||
static void __exit gpu_cc_sm6350_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&gpu_cc_sm6350_driver);
|
||||
}
|
||||
module_exit(gpu_cc_sm6350_exit);
|
||||
|
||||
MODULE_DESCRIPTION("QTI GPU_CC LAGOON Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
@ -257,6 +257,18 @@ static struct clk_rcg2 mmss_ahb_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mmss_axi_clk_msm8226[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
F(37500000, P_GPLL0, 16, 0, 0),
|
||||
F(50000000, P_GPLL0, 12, 0, 0),
|
||||
F(75000000, P_GPLL0, 8, 0, 0),
|
||||
F(100000000, P_GPLL0, 6, 0, 0),
|
||||
F(150000000, P_GPLL0, 4, 0, 0),
|
||||
F(200000000, P_MMPLL0, 4, 0, 0),
|
||||
F(266666666, P_MMPLL0, 3, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mmss_axi_clk[] = {
|
||||
F( 19200000, P_XO, 1, 0, 0),
|
||||
F( 37500000, P_GPLL0, 16, 0, 0),
|
||||
@ -364,6 +376,23 @@ static struct clk_rcg2 csi3_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_vfe_vfe0_clk_msm8226[] = {
|
||||
F(37500000, P_GPLL0, 16, 0, 0),
|
||||
F(50000000, P_GPLL0, 12, 0, 0),
|
||||
F(60000000, P_GPLL0, 10, 0, 0),
|
||||
F(80000000, P_GPLL0, 7.5, 0, 0),
|
||||
F(100000000, P_GPLL0, 6, 0, 0),
|
||||
F(109090000, P_GPLL0, 5.5, 0, 0),
|
||||
F(133330000, P_GPLL0, 4.5, 0, 0),
|
||||
F(150000000, P_GPLL0, 4, 0, 0),
|
||||
F(200000000, P_GPLL0, 3, 0, 0),
|
||||
F(228570000, P_MMPLL0, 3.5, 0, 0),
|
||||
F(266670000, P_MMPLL0, 3, 0, 0),
|
||||
F(320000000, P_MMPLL0, 2.5, 0, 0),
|
||||
F(400000000, P_MMPLL0, 2, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
|
||||
F(37500000, P_GPLL0, 16, 0, 0),
|
||||
F(50000000, P_GPLL0, 12, 0, 0),
|
||||
@ -407,6 +436,18 @@ static struct clk_rcg2 vfe1_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mdss_mdp_clk_msm8226[] = {
|
||||
F(37500000, P_GPLL0, 16, 0, 0),
|
||||
F(60000000, P_GPLL0, 10, 0, 0),
|
||||
F(75000000, P_GPLL0, 8, 0, 0),
|
||||
F(92310000, P_GPLL0, 6.5, 0, 0),
|
||||
F(100000000, P_GPLL0, 6, 0, 0),
|
||||
F(133330000, P_MMPLL0, 6, 0, 0),
|
||||
F(177780000, P_MMPLL0, 4.5, 0, 0),
|
||||
F(200000000, P_MMPLL0, 4, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_mdss_mdp_clk[] = {
|
||||
F(37500000, P_GPLL0, 16, 0, 0),
|
||||
F(60000000, P_GPLL0, 10, 0, 0),
|
||||
@ -513,6 +554,14 @@ static struct clk_rcg2 pclk1_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_venus0_vcodec0_clk_msm8226[] = {
|
||||
F(66700000, P_GPLL0, 9, 0, 0),
|
||||
F(100000000, P_GPLL0, 6, 0, 0),
|
||||
F(133330000, P_MMPLL0, 6, 0, 0),
|
||||
F(160000000, P_MMPLL0, 5, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
|
||||
F(50000000, P_GPLL0, 12, 0, 0),
|
||||
F(100000000, P_GPLL0, 6, 0, 0),
|
||||
@ -593,6 +642,13 @@ static struct clk_rcg2 camss_gp1_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_mclk0_3_clk_msm8226[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
F(24000000, P_GPLL0, 5, 1, 5),
|
||||
F(66670000, P_GPLL0, 9, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
|
||||
F(4800000, P_XO, 4, 0, 0),
|
||||
F(6000000, P_GPLL0, 10, 1, 10),
|
||||
@ -705,6 +761,15 @@ static struct clk_rcg2 csi2phytimer_clk_src = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_vfe_cpp_clk_msm8226[] = {
|
||||
F(133330000, P_GPLL0, 4.5, 0, 0),
|
||||
F(150000000, P_GPLL0, 4, 0, 0),
|
||||
F(266670000, P_MMPLL0, 3, 0, 0),
|
||||
F(320000000, P_MMPLL0, 2.5, 0, 0),
|
||||
F(400000000, P_MMPLL0, 2, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
|
||||
F(133330000, P_GPLL0, 4.5, 0, 0),
|
||||
F(266670000, P_MMPLL0, 3, 0, 0),
|
||||
@ -2366,6 +2431,116 @@ static struct gdsc oxilicx_gdsc = {
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
};
|
||||
|
||||
static struct clk_regmap *mmcc_msm8226_clocks[] = {
|
||||
[MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
|
||||
[MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
|
||||
[MMPLL0] = &mmpll0.clkr,
|
||||
[MMPLL0_VOTE] = &mmpll0_vote,
|
||||
[MMPLL1] = &mmpll1.clkr,
|
||||
[MMPLL1_VOTE] = &mmpll1_vote,
|
||||
[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
|
||||
[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
|
||||
[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
|
||||
[MDP_CLK_SRC] = &mdp_clk_src.clkr,
|
||||
[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
|
||||
[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
|
||||
[VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
|
||||
[CCI_CLK_SRC] = &cci_clk_src.clkr,
|
||||
[CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
|
||||
[CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
|
||||
[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
|
||||
[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
|
||||
[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
|
||||
[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
|
||||
[CPP_CLK_SRC] = &cpp_clk_src.clkr,
|
||||
[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
|
||||
[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
|
||||
[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
|
||||
[CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
|
||||
[CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
|
||||
[CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
|
||||
[CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
|
||||
[CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
|
||||
[CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
|
||||
[CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
|
||||
[CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
|
||||
[CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
|
||||
[CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
|
||||
[CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
|
||||
[CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
|
||||
[CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
|
||||
[CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
|
||||
[CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
|
||||
[CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
|
||||
[CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
|
||||
[CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
|
||||
[CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
|
||||
[CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
|
||||
[CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
|
||||
[CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
|
||||
[CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
|
||||
[CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
|
||||
[CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
|
||||
[CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
|
||||
[CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
|
||||
[CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
|
||||
[CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
|
||||
[CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
|
||||
[MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
|
||||
[MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
|
||||
[MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
|
||||
[MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
|
||||
[MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
|
||||
[MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
|
||||
[MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
|
||||
[MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
|
||||
[MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
|
||||
[MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
|
||||
[MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
|
||||
[MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
|
||||
[MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
|
||||
[OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
|
||||
[OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
|
||||
[OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
|
||||
[OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
|
||||
[OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
|
||||
[VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
|
||||
[VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
|
||||
[VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
|
||||
};
|
||||
|
||||
static const struct qcom_reset_map mmcc_msm8226_resets[] = {
|
||||
[SPDM_RESET] = { 0x0200 },
|
||||
[SPDM_RM_RESET] = { 0x0300 },
|
||||
[VENUS0_RESET] = { 0x1020 },
|
||||
[MDSS_RESET] = { 0x2300 },
|
||||
};
|
||||
|
||||
static struct gdsc *mmcc_msm8226_gdscs[] = {
|
||||
[VENUS0_GDSC] = &venus0_gdsc,
|
||||
[MDSS_GDSC] = &mdss_gdsc,
|
||||
[CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
|
||||
[CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
|
||||
};
|
||||
|
||||
static const struct regmap_config mmcc_msm8226_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x5104,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc mmcc_msm8226_desc = {
|
||||
.config = &mmcc_msm8226_regmap_config,
|
||||
.clks = mmcc_msm8226_clocks,
|
||||
.num_clks = ARRAY_SIZE(mmcc_msm8226_clocks),
|
||||
.resets = mmcc_msm8226_resets,
|
||||
.num_resets = ARRAY_SIZE(mmcc_msm8226_resets),
|
||||
.gdscs = mmcc_msm8226_gdscs,
|
||||
.num_gdscs = ARRAY_SIZE(mmcc_msm8226_gdscs),
|
||||
};
|
||||
|
||||
static struct clk_regmap *mmcc_msm8974_clocks[] = {
|
||||
[MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
|
||||
[MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
|
||||
@ -2569,23 +2744,44 @@ static const struct qcom_cc_desc mmcc_msm8974_desc = {
|
||||
};
|
||||
|
||||
static const struct of_device_id mmcc_msm8974_match_table[] = {
|
||||
{ .compatible = "qcom,mmcc-msm8974" },
|
||||
{ .compatible = "qcom,mmcc-msm8226", .data = &mmcc_msm8226_desc },
|
||||
{ .compatible = "qcom,mmcc-msm8974", .data = &mmcc_msm8974_desc },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
|
||||
|
||||
static void msm8226_clock_override(void)
|
||||
{
|
||||
mmss_axi_clk_src.freq_tbl = ftbl_mmss_axi_clk_msm8226;
|
||||
vfe0_clk_src.freq_tbl = ftbl_camss_vfe_vfe0_clk_msm8226;
|
||||
mdp_clk_src.freq_tbl = ftbl_mdss_mdp_clk_msm8226;
|
||||
vcodec0_clk_src.freq_tbl = ftbl_venus0_vcodec0_clk_msm8226;
|
||||
mclk0_clk_src.freq_tbl = ftbl_camss_mclk0_3_clk_msm8226;
|
||||
mclk1_clk_src.freq_tbl = ftbl_camss_mclk0_3_clk_msm8226;
|
||||
cpp_clk_src.freq_tbl = ftbl_camss_vfe_cpp_clk_msm8226;
|
||||
}
|
||||
|
||||
static int mmcc_msm8974_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
const struct qcom_cc_desc *desc;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &mmcc_msm8974_desc);
|
||||
desc = of_device_get_match_data(&pdev->dev);
|
||||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
regmap = qcom_cc_map(pdev, desc);
|
||||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
|
||||
clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
|
||||
if (desc == &mmcc_msm8974_desc) {
|
||||
clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
|
||||
clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
|
||||
} else {
|
||||
msm8226_clock_override();
|
||||
}
|
||||
|
||||
return qcom_cc_really_probe(pdev, &mmcc_msm8974_desc, regmap);
|
||||
return qcom_cc_really_probe(pdev, desc, regmap);
|
||||
}
|
||||
|
||||
static struct platform_driver mmcc_msm8974_driver = {
|
||||
|
||||
@ -99,8 +99,8 @@ static struct clk_branch video_cc_vcodec0_core_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_vcodec0_core_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &video_cc_venus_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&video_cc_venus_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -143,8 +143,8 @@ static struct clk_branch video_cc_venus_ctl_core_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_venus_ctl_core_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &video_cc_venus_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&video_cc_venus_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
||||
34
include/dt-bindings/clock/qcom,dispcc-qcm2290.h
Normal file
34
include/dt-bindings/clock/qcom,dispcc-qcm2290.h
Normal file
@ -0,0 +1,34 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_QCM2290_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_QCM2290_H
|
||||
|
||||
/* DISP_CC clocks */
|
||||
#define DISP_CC_PLL0 0
|
||||
#define DISP_CC_MDSS_AHB_CLK 1
|
||||
#define DISP_CC_MDSS_AHB_CLK_SRC 2
|
||||
#define DISP_CC_MDSS_BYTE0_CLK 3
|
||||
#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
|
||||
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
|
||||
#define DISP_CC_MDSS_BYTE0_INTF_CLK 6
|
||||
#define DISP_CC_MDSS_ESC0_CLK 7
|
||||
#define DISP_CC_MDSS_ESC0_CLK_SRC 8
|
||||
#define DISP_CC_MDSS_MDP_CLK 9
|
||||
#define DISP_CC_MDSS_MDP_CLK_SRC 10
|
||||
#define DISP_CC_MDSS_MDP_LUT_CLK 11
|
||||
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 12
|
||||
#define DISP_CC_MDSS_PCLK0_CLK 13
|
||||
#define DISP_CC_MDSS_PCLK0_CLK_SRC 14
|
||||
#define DISP_CC_MDSS_VSYNC_CLK 15
|
||||
#define DISP_CC_MDSS_VSYNC_CLK_SRC 16
|
||||
#define DISP_CC_SLEEP_CLK 17
|
||||
#define DISP_CC_SLEEP_CLK_SRC 18
|
||||
#define DISP_CC_XO_CLK 19
|
||||
#define DISP_CC_XO_CLK_SRC 20
|
||||
|
||||
#define MDSS_GDSC 0
|
||||
|
||||
#endif
|
||||
41
include/dt-bindings/clock/qcom,dispcc-sm6125.h
Normal file
41
include/dt-bindings/clock/qcom,dispcc-sm6125.h
Normal file
@ -0,0 +1,41 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6125_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6125_H
|
||||
|
||||
#define DISP_CC_PLL0 0
|
||||
#define DISP_CC_MDSS_AHB_CLK 1
|
||||
#define DISP_CC_MDSS_AHB_CLK_SRC 2
|
||||
#define DISP_CC_MDSS_BYTE0_CLK 3
|
||||
#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
|
||||
#define DISP_CC_MDSS_BYTE0_INTF_CLK 5
|
||||
#define DISP_CC_MDSS_DP_AUX_CLK 6
|
||||
#define DISP_CC_MDSS_DP_AUX_CLK_SRC 7
|
||||
#define DISP_CC_MDSS_DP_CRYPTO_CLK 8
|
||||
#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 9
|
||||
#define DISP_CC_MDSS_DP_LINK_CLK 10
|
||||
#define DISP_CC_MDSS_DP_LINK_CLK_SRC 11
|
||||
#define DISP_CC_MDSS_DP_LINK_INTF_CLK 12
|
||||
#define DISP_CC_MDSS_DP_PIXEL_CLK 13
|
||||
#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 14
|
||||
#define DISP_CC_MDSS_ESC0_CLK 15
|
||||
#define DISP_CC_MDSS_ESC0_CLK_SRC 16
|
||||
#define DISP_CC_MDSS_MDP_CLK 17
|
||||
#define DISP_CC_MDSS_MDP_CLK_SRC 18
|
||||
#define DISP_CC_MDSS_MDP_LUT_CLK 19
|
||||
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 20
|
||||
#define DISP_CC_MDSS_PCLK0_CLK 21
|
||||
#define DISP_CC_MDSS_PCLK0_CLK_SRC 22
|
||||
#define DISP_CC_MDSS_ROT_CLK 23
|
||||
#define DISP_CC_MDSS_ROT_CLK_SRC 24
|
||||
#define DISP_CC_MDSS_VSYNC_CLK 25
|
||||
#define DISP_CC_MDSS_VSYNC_CLK_SRC 26
|
||||
#define DISP_CC_XO_CLK 27
|
||||
|
||||
/* DISP_CC GDSCR */
|
||||
#define MDSS_GDSC 0
|
||||
|
||||
#endif
|
||||
48
include/dt-bindings/clock/qcom,dispcc-sm6350.h
Normal file
48
include/dt-bindings/clock/qcom,dispcc-sm6350.h
Normal file
@ -0,0 +1,48 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6350_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6350_H
|
||||
|
||||
/* DISP_CC clocks */
|
||||
#define DISP_CC_PLL0 0
|
||||
#define DISP_CC_MDSS_AHB_CLK 1
|
||||
#define DISP_CC_MDSS_AHB_CLK_SRC 2
|
||||
#define DISP_CC_MDSS_BYTE0_CLK 3
|
||||
#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
|
||||
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
|
||||
#define DISP_CC_MDSS_BYTE0_INTF_CLK 6
|
||||
#define DISP_CC_MDSS_DP_AUX_CLK 7
|
||||
#define DISP_CC_MDSS_DP_AUX_CLK_SRC 8
|
||||
#define DISP_CC_MDSS_DP_CRYPTO_CLK 9
|
||||
#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 10
|
||||
#define DISP_CC_MDSS_DP_LINK_CLK 11
|
||||
#define DISP_CC_MDSS_DP_LINK_CLK_SRC 12
|
||||
#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 13
|
||||
#define DISP_CC_MDSS_DP_LINK_INTF_CLK 14
|
||||
#define DISP_CC_MDSS_DP_PIXEL_CLK 15
|
||||
#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 16
|
||||
#define DISP_CC_MDSS_ESC0_CLK 17
|
||||
#define DISP_CC_MDSS_ESC0_CLK_SRC 18
|
||||
#define DISP_CC_MDSS_MDP_CLK 19
|
||||
#define DISP_CC_MDSS_MDP_CLK_SRC 20
|
||||
#define DISP_CC_MDSS_MDP_LUT_CLK 21
|
||||
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 22
|
||||
#define DISP_CC_MDSS_PCLK0_CLK 23
|
||||
#define DISP_CC_MDSS_PCLK0_CLK_SRC 24
|
||||
#define DISP_CC_MDSS_ROT_CLK 25
|
||||
#define DISP_CC_MDSS_ROT_CLK_SRC 26
|
||||
#define DISP_CC_MDSS_RSCC_AHB_CLK 27
|
||||
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 28
|
||||
#define DISP_CC_MDSS_VSYNC_CLK 29
|
||||
#define DISP_CC_MDSS_VSYNC_CLK_SRC 30
|
||||
#define DISP_CC_SLEEP_CLK 31
|
||||
#define DISP_CC_XO_CLK 32
|
||||
|
||||
/* GDSCs */
|
||||
#define MDSS_GDSC 0
|
||||
|
||||
#endif
|
||||
@ -240,7 +240,7 @@
|
||||
#define PLL14 232
|
||||
#define PLL14_VOTE 233
|
||||
#define PLL18 234
|
||||
#define CE5_SRC 235
|
||||
#define CE5_A_CLK 235
|
||||
#define CE5_H_CLK 236
|
||||
#define CE5_CORE_CLK 237
|
||||
#define CE3_SLEEP_CLK 238
|
||||
@ -283,5 +283,8 @@
|
||||
#define EBI2_AON_CLK 281
|
||||
#define NSSTCM_CLK_SRC 282
|
||||
#define NSSTCM_CLK 283
|
||||
#define CE5_A_CLK_SRC 285
|
||||
#define CE5_H_CLK_SRC 286
|
||||
#define CE5_CORE_CLK_SRC 287
|
||||
|
||||
#endif
|
||||
|
||||
@ -241,7 +241,12 @@
|
||||
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 28
|
||||
|
||||
/* GCC GDSCRs */
|
||||
#define PCIE_0_GDSC 0
|
||||
#define PCIE_1_GDSC 1
|
||||
#define UFS_CARD_GDSC 2
|
||||
#define UFS_PHY_GDSC 3
|
||||
#define USB30_PRIM_GDSC 4
|
||||
#define USB30_SEC_GDSC 5
|
||||
#define EMAC_GDSC 6
|
||||
|
||||
#endif
|
||||
|
||||
37
include/dt-bindings/clock/qcom,gpucc-sm6350.h
Normal file
37
include/dt-bindings/clock/qcom,gpucc-sm6350.h
Normal file
@ -0,0 +1,37 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6350_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6350_H
|
||||
|
||||
/* GPU_CC clocks */
|
||||
#define GPU_CC_PLL0 0
|
||||
#define GPU_CC_PLL1 1
|
||||
#define GPU_CC_ACD_AHB_CLK 2
|
||||
#define GPU_CC_ACD_CXO_CLK 3
|
||||
#define GPU_CC_AHB_CLK 4
|
||||
#define GPU_CC_CRC_AHB_CLK 5
|
||||
#define GPU_CC_CX_GFX3D_CLK 6
|
||||
#define GPU_CC_CX_GFX3D_SLV_CLK 7
|
||||
#define GPU_CC_CX_GMU_CLK 8
|
||||
#define GPU_CC_CX_SNOC_DVM_CLK 9
|
||||
#define GPU_CC_CXO_AON_CLK 10
|
||||
#define GPU_CC_CXO_CLK 11
|
||||
#define GPU_CC_GMU_CLK_SRC 12
|
||||
#define GPU_CC_GX_CXO_CLK 13
|
||||
#define GPU_CC_GX_GFX3D_CLK 14
|
||||
#define GPU_CC_GX_GFX3D_CLK_SRC 15
|
||||
#define GPU_CC_GX_GMU_CLK 16
|
||||
#define GPU_CC_GX_VSENSE_CLK 17
|
||||
|
||||
/* CLK_HW */
|
||||
#define GPU_CC_CRC_DIV 0
|
||||
|
||||
/* GDSCs */
|
||||
#define GPU_CX_GDSC 0
|
||||
#define GPU_GX_GDSC 1
|
||||
|
||||
#endif
|
||||
@ -165,5 +165,7 @@
|
||||
#define RPM_SMD_PKA_A_CLK 119
|
||||
#define RPM_SMD_CPUSS_GNOC_CLK 120
|
||||
#define RPM_SMD_CPUSS_GNOC_A_CLK 121
|
||||
#define RPM_SMD_MSS_CFG_AHB_CLK 122
|
||||
#define RPM_SMD_MSS_CFG_AHB_A_CLK 123
|
||||
|
||||
#endif
|
||||
|
||||
@ -163,5 +163,10 @@
|
||||
#define NSS_CAL_PRBS_RST_N_RESET 154
|
||||
#define NSS_LCKDT_RST_N_RESET 155
|
||||
#define NSS_SRDS_N_RESET 156
|
||||
#define CRYPTO_ENG1_RESET 157
|
||||
#define CRYPTO_ENG2_RESET 158
|
||||
#define CRYPTO_ENG3_RESET 159
|
||||
#define CRYPTO_ENG4_RESET 160
|
||||
#define CRYPTO_AHB_RESET 161
|
||||
|
||||
#endif
|
||||
|
||||
@ -40,6 +40,7 @@ struct qcom_smd_rpm;
|
||||
#define QCOM_SMD_RPM_AGGR_CLK 0x72676761
|
||||
#define QCOM_SMD_RPM_HWKM_CLK 0x6d6b7768
|
||||
#define QCOM_SMD_RPM_PKA_CLK 0x616b70
|
||||
#define QCOM_SMD_RPM_MCFG_CLK 0x6766636d
|
||||
|
||||
int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,
|
||||
int state,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user