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Merge branches 'clk-imx', 'clk-qcom', 'clk-amlogic' and 'clk-mediatek' into clk-next

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* clk-imx:
  clk: imx: pll14xx: change naming of fvco to fout
  clk: imx: clk-imx8qxp: fix LVDS bypass, pixel and phy clocks
  clk: imx: scu: Fix memory leak in __imx_clk_gpr_scu()
  dt-bindings: clock: support i.MX93 ANATOP clock module

* clk-qcom: (41 commits)
  clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL config
  clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL config
  clk: qcom: dispcc-sm8550: Use the correct PLL configuration function
  clk: qcom: dispcc-sm8550: Update disp PLL settings
  clk: qcom: gpucc-sm8550: Update GPU PLL settings
  clk: qcom: gcc-sm8550: Mark RCGs shared where applicable
  clk: qcom: gcc-sm8550: use collapse-voting for PCIe GDSCs
  clk: qcom: gcc-sm8550: Mark the PCIe GDSCs votable
  clk: qcom: gcc-sm8550: Add the missing RETAIN_FF_ENABLE GDSC flag
  clk: qcom: camcc-sc8280xp: Prevent error pointer dereference
  clk: qcom: videocc-sm8150: Add runtime PM support
  clk: qcom: videocc-sm8150: Add missing PLL config property
  clk: qcom: videocc-sm8150: Update the videocc resets
  dt-bindings: clock: Update the videocc resets for sm8150
  clk: qcom: rpmh: Add support for X1E80100 rpmh clocks
  clk: qcom: Add Global Clock controller (GCC) driver for X1E80100
  dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for X1E80100
  dt-bindings: clock: qcom: Add X1E80100 GCC clocks
  clk: qcom: Add ECPRICC driver support for QDU1000 and QRU1000
  clk: qcom: branch: Add mem ops support for branch2 clocks
  ...

* clk-amlogic:
  clk: meson: g12a: add CSI & ISP gates clocks
  clk: meson: g12a: add MIPI ISP clocks
  dt-bindings: clock: g12a-clkc: add MIPI ISP & CSI PHY clock ids
  clk: meson: g12a: add CTS_ENCL & CTS_ENCL_SEL clocks
  dt-bindings: clk: g12a-clkc: add CTS_ENCL clock ids

* clk-mediatek:
  clk: mediatek: add drivers for MT7988 SoC
  clk: mediatek: add pcw_chg_bit control for PLLs of MT7988
  dt-bindings: clock: mediatek: add clock controllers of MT7988
  dt-bindings: reset: mediatek: add MT7988 ethwarp reset IDs
  dt-bindings: clock: mediatek: add MT7988 clock IDs
  clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxes
  clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes
  clk: mediatek: clk-mux: Support custom parent indices for muxes
  dt-bindings: clock: brcm,kona-ccu: convert to YAML
  dt-bindings: arm: mediatek: move ethsys controller & convert to DT schema
  dt-bindings: Remove alt_ref from versal
This commit is contained in:
Stephen Boyd 2024-01-09 11:52:49 -08:00
commit 23bd8c4ad1
78 changed files with 22858 additions and 365 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
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@ -1,29 +0,0 @@
Mediatek ethsys controller
============================
The Mediatek ethsys controller provides various clocks to the system.
Required Properties:
- compatible: Should be:
- "mediatek,mt2701-ethsys", "syscon"
- "mediatek,mt7622-ethsys", "syscon"
- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
- "mediatek,mt7629-ethsys", "syscon"
- "mediatek,mt7981-ethsys", "syscon"
- "mediatek,mt7986-ethsys", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1
The ethsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
Example:
ethsys: clock-controller@1b000000 {
compatible = "mediatek,mt2701-ethsys", "syscon";
reg = <0 0x1b000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
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@ -30,6 +30,7 @@ properties:
- mediatek,mt7629-infracfg
- mediatek,mt7981-infracfg
- mediatek,mt7986-infracfg
- mediatek,mt7988-infracfg
- mediatek,mt8135-infracfg
- mediatek,mt8167-infracfg
- mediatek,mt8173-infracfg

138
Documentation/devicetree/bindings/clock/brcm,kona-ccu.txt
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Broadcom Kona Family Clocks
This binding is associated with Broadcom SoCs having "Kona" style
clock control units (CCUs). A CCU is a clock provider that manages
a set of clock signals. Each CCU is represented by a node in the
device tree.
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible
Shall have a value of the form "brcm,<model>-<which>-ccu",
where <model> is a Broadcom SoC model number and <which> is
the name of a defined CCU. For example:
"brcm,bcm11351-root-ccu"
The compatible strings used for each supported SoC family
are defined below.
- reg
Shall define the base and range of the address space
containing clock control registers
- #clock-cells
Shall have value <1>. The permitted clock-specifier values
are defined below.
- clock-output-names
Shall be an ordered list of strings defining the names of
the clocks provided by the CCU.
Device tree example:
slave_ccu: slave_ccu {
compatible = "brcm,bcm11351-slave-ccu";
reg = <0x3e011000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "uartb",
"uartb2",
"uartb3",
"uartb4";
};
ref_crystal_clk: ref_crystal {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <26000000>;
};
uart@3e002000 {
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
reg = <0x3e002000 0x1000>;
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
};
BCM281XX family
---------------
CCU compatible string values for SoCs in the BCM281XX family are:
"brcm,bcm11351-root-ccu"
"brcm,bcm11351-aon-ccu"
"brcm,bcm11351-hub-ccu"
"brcm,bcm11351-master-ccu"
"brcm,bcm11351-slave-ccu"
The following table defines the set of CCUs and clock specifiers for
BCM281XX family clocks. When a clock consumer references a clocks,
its symbolic specifier (rather than its numeric index value) should
be used. These specifiers are defined in:
"include/dt-bindings/clock/bcm281xx.h"
CCU Clock Type Index Specifier
--- ----- ---- ----- ---------
root frac_1m peri 0 BCM281XX_ROOT_CCU_FRAC_1M
aon hub_timer peri 0 BCM281XX_AON_CCU_HUB_TIMER
aon pmu_bsc peri 1 BCM281XX_AON_CCU_PMU_BSC
aon pmu_bsc_var peri 2 BCM281XX_AON_CCU_PMU_BSC_VAR
hub tmon_1m peri 0 BCM281XX_HUB_CCU_TMON_1M
master sdio1 peri 0 BCM281XX_MASTER_CCU_SDIO1
master sdio2 peri 1 BCM281XX_MASTER_CCU_SDIO2
master sdio3 peri 2 BCM281XX_MASTER_CCU_SDIO3
master sdio4 peri 3 BCM281XX_MASTER_CCU_SDIO4
master dmac peri 4 BCM281XX_MASTER_CCU_DMAC
master usb_ic peri 5 BCM281XX_MASTER_CCU_USB_IC
master hsic2_48m peri 6 BCM281XX_MASTER_CCU_HSIC_48M
master hsic2_12m peri 7 BCM281XX_MASTER_CCU_HSIC_12M
slave uartb peri 0 BCM281XX_SLAVE_CCU_UARTB
slave uartb2 peri 1 BCM281XX_SLAVE_CCU_UARTB2
slave uartb3 peri 2 BCM281XX_SLAVE_CCU_UARTB3
slave uartb4 peri 3 BCM281XX_SLAVE_CCU_UARTB4
slave ssp0 peri 4 BCM281XX_SLAVE_CCU_SSP0
slave ssp2 peri 5 BCM281XX_SLAVE_CCU_SSP2
slave bsc1 peri 6 BCM281XX_SLAVE_CCU_BSC1
slave bsc2 peri 7 BCM281XX_SLAVE_CCU_BSC2
slave bsc3 peri 8 BCM281XX_SLAVE_CCU_BSC3
slave pwm peri 9 BCM281XX_SLAVE_CCU_PWM
BCM21664 family
---------------
CCU compatible string values for SoCs in the BCM21664 family are:
"brcm,bcm21664-root-ccu"
"brcm,bcm21664-aon-ccu"
"brcm,bcm21664-master-ccu"
"brcm,bcm21664-slave-ccu"
The following table defines the set of CCUs and clock specifiers for
BCM21664 family clocks. When a clock consumer references a clocks,
its symbolic specifier (rather than its numeric index value) should
be used. These specifiers are defined in:
"include/dt-bindings/clock/bcm21664.h"
CCU Clock Type Index Specifier
--- ----- ---- ----- ---------
root frac_1m peri 0 BCM21664_ROOT_CCU_FRAC_1M
aon hub_timer peri 0 BCM21664_AON_CCU_HUB_TIMER
master sdio1 peri 0 BCM21664_MASTER_CCU_SDIO1
master sdio2 peri 1 BCM21664_MASTER_CCU_SDIO2
master sdio3 peri 2 BCM21664_MASTER_CCU_SDIO3
master sdio4 peri 3 BCM21664_MASTER_CCU_SDIO4
master sdio1_sleep peri 4 BCM21664_MASTER_CCU_SDIO1_SLEEP
master sdio2_sleep peri 5 BCM21664_MASTER_CCU_SDIO2_SLEEP
master sdio3_sleep peri 6 BCM21664_MASTER_CCU_SDIO3_SLEEP
master sdio4_sleep peri 7 BCM21664_MASTER_CCU_SDIO4_SLEEP
slave uartb peri 0 BCM21664_SLAVE_CCU_UARTB
slave uartb2 peri 1 BCM21664_SLAVE_CCU_UARTB2
slave uartb3 peri 2 BCM21664_SLAVE_CCU_UARTB3
slave uartb4 peri 3 BCM21664_SLAVE_CCU_UARTB4
slave bsc1 peri 4 BCM21664_SLAVE_CCU_BSC1
slave bsc2 peri 5 BCM21664_SLAVE_CCU_BSC2
slave bsc3 peri 6 BCM21664_SLAVE_CCU_BSC3
slave bsc4 peri 7 BCM21664_SLAVE_CCU_BSC4

181
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/brcm,kona-ccu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Kona family clock control units (CCU)
maintainers:
- Florian Fainelli <florian.fainelli@broadcom.com>
- Ray Jui <rjui@broadcom.com>
- Scott Branden <sbranden@broadcom.com>
description: |
Broadcom "Kona" style clock control unit (CCU) is a clock provider that
manages a set of clock signals.
All available clock IDs are defined in
- include/dt-bindings/clock/bcm281xx.h for BCM281XX family
- include/dt-bindings/clock/bcm21664.h for BCM21664 family
properties:
compatible:
enum:
- brcm,bcm11351-aon-ccu
- brcm,bcm11351-hub-ccu
- brcm,bcm11351-master-ccu
- brcm,bcm11351-root-ccu
- brcm,bcm11351-slave-ccu
- brcm,bcm21664-aon-ccu
- brcm,bcm21664-master-ccu
- brcm,bcm21664-root-ccu
- brcm,bcm21664-slave-ccu
reg:
maxItems: 1
'#clock-cells':
const: 1
clock-output-names:
minItems: 1
maxItems: 10
required:
- compatible
- reg
- '#clock-cells'
- clock-output-names
allOf:
- if:
properties:
compatible:
contains:
const: brcm,bcm11351-aon-ccu
then:
properties:
clock-output-names:
items:
- const: hub_timer
- const: pmu_bsc
- const: pmu_bsc_var
- if:
properties:
compatible:
contains:
const: brcm,bcm11351-hub-ccu
then:
properties:
clock-output-names:
const: tmon_1m
- if:
properties:
compatible:
contains:
const: brcm,bcm11351-master-ccu
then:
properties:
clock-output-names:
items:
- const: sdio1
- const: sdio2
- const: sdio3
- const: sdio4
- const: usb_ic
- const: hsic2_48m
- const: hsic2_12m
- if:
properties:
compatible:
contains:
enum:
- brcm,bcm11351-root-ccu
- brcm,bcm21664-root-ccu
then:
properties:
clock-output-names:
const: frac_1m
- if:
properties:
compatible:
contains:
const: brcm,bcm11351-slave-ccu
then:
properties:
clock-output-names:
items:
- const: uartb
- const: uartb2
- const: uartb3
- const: uartb4
- const: ssp0
- const: ssp2
- const: bsc1
- const: bsc2
- const: bsc3
- const: pwm
- if:
properties:
compatible:
contains:
const: brcm,bcm21664-aon-ccu
then:
properties:
clock-output-names:
const: hub_timer
- if:
properties:
compatible:
contains:
const: brcm,bcm21664-master-ccu
then:
properties:
clock-output-names:
items:
- const: sdio1
- const: sdio2
- const: sdio3
- const: sdio4
- const: sdio1_sleep
- const: sdio2_sleep
- const: sdio3_sleep
- const: sdio4_sleep
- if:
properties:
compatible:
contains:
const: brcm,bcm21664-slave-ccu
then:
properties:
clock-output-names:
items:
- const: uartb
- const: uartb2
- const: uartb3
- const: bsc1
- const: bsc2
- const: bsc3
- const: bsc4
additionalProperties: false
examples:
- |
clock-controller@3e011000 {
compatible = "brcm,bcm11351-slave-ccu";
reg = <0x3e011000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "uartb",
"uartb2",
"uartb3",
"uartb4",
"ssp0",
"ssp2",
"bsc1",
"bsc2",
"bsc3",
"pwm";
};
...

42
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fsl,imx93-anatop.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX93 ANATOP Clock Module
maintainers:
- Peng Fan <peng.fan@nxp.com>
description: |
NXP i.MX93 ANATOP module which contains PLL and OSC to Clock Controller
Module.
properties:
compatible:
items:
- const: fsl,imx93-anatop
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@44480000 {
compatible = "fsl,imx93-anatop";
reg = <0x44480000 0x2000>;
#clock-cells = <1>;
};
...

1
Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
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@ -22,6 +22,7 @@ properties:
- mediatek,mt7622-apmixedsys
- mediatek,mt7981-apmixedsys
- mediatek,mt7986-apmixedsys
- mediatek,mt7988-apmixedsys
- mediatek,mt8135-apmixedsys
- mediatek,mt8173-apmixedsys
- mediatek,mt8516-apmixedsys

55
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,ethsys.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek ethsys controller
description:
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
maintainers:
- James Liao <jamesjj.liao@mediatek.com>
properties:
compatible:
oneOf:
- items:
- enum:
- mediatek,mt2701-ethsys
- mediatek,mt7622-ethsys
- mediatek,mt7629-ethsys
- mediatek,mt7981-ethsys
- mediatek,mt7986-ethsys
- mediatek,mt7988-ethsys
- const: syscon
- items:
- const: mediatek,mt7623-ethsys
- const: mediatek,mt2701-ethsys
- const: syscon
reg:
maxItems: 1
"#clock-cells":
const: 1
"#reset-cells":
const: 1
required:
- reg
- "#clock-cells"
- "#reset-cells"
additionalProperties: false
examples:
- |
clock-controller@1b000000 {
compatible = "mediatek,mt2701-ethsys", "syscon";
reg = <0x1b000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

52
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt7988-ethwarp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MT7988 ethwarp Controller
maintainers:
- Daniel Golle <daniel@makrotopia.org>
description:
The Mediatek MT7988 ethwarp controller provides clocks and resets for the
Ethernet related subsystems found the MT7988 SoC.
The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
properties:
compatible:
items:
- const: mediatek,mt7988-ethwarp
reg:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
- '#reset-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/reset/ti-syscon.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@15031000 {
compatible = "mediatek,mt7988-ethwarp";
reg = <0 0x15031000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
};

48
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt7988-xfi-pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MT7988 XFI PLL Clock Controller
maintainers:
- Daniel Golle <daniel@makrotopia.org>
description:
The MediaTek XFI PLL controller provides the 156.25MHz clock for the
Ethernet SerDes PHY from the 40MHz top_xtal clock.
properties:
compatible:
const: mediatek,mt7988-xfi-pll
reg:
maxItems: 1
resets:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- resets
- '#clock-cells'
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@11f40000 {
compatible = "mediatek,mt7988-xfi-pll";
reg = <0 0x11f40000 0 0x1000>;
resets = <&watchdog 16>;
#clock-cells = <1>;
};
};

2
Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
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@ -37,6 +37,8 @@ properties:
- mediatek,mt7629-topckgen
- mediatek,mt7981-topckgen
- mediatek,mt7986-topckgen
- mediatek,mt7988-mcusys
- mediatek,mt7988-topckgen
- mediatek,mt8167-topckgen
- mediatek,mt8183-topckgen
- const: syscon

1
Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
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@ -16,6 +16,7 @@ description:
properties:
compatible:
enum:
- qcom,ipq5018-a53pll
- qcom,ipq5332-a53pll
- qcom,ipq6018-a53pll
- qcom,ipq8074-a53pll

18
Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml
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@ -15,6 +15,9 @@ description: |
See also:: include/dt-bindings/clock/qcom,camcc-sm8250.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
const: qcom,sm8250-camcc
@ -33,15 +36,6 @@ properties:
- const: bi_tcxo_ao
- const: sleep_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
power-domains:
items:
- description: MMCX power domain
@ -56,14 +50,10 @@ properties:
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
unevaluatedProperties: false
examples:
- |

57
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@ -0,0 +1,57 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq6018.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on IPQ6018
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <quic_tdas@quicinc.com>
- Robert Marko <robimarko@gmail.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ6018.
See also::
include/dt-bindings/clock/qcom,gcc-ipq6018.h
include/dt-bindings/reset/qcom,gcc-ipq6018.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
const: qcom,gcc-ipq6018
clocks:
items:
- description: board XO clock
- description: sleep clock
clock-names:
items:
- const: xo
- const: sleep_clk
required:
- compatible
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
clock-controller@1800000 {
compatible = "qcom,gcc-ipq6018";
reg = <0x01800000 0x80000>;
clocks = <&xo>, <&sleep_clk>;
clock-names = "xo", "sleep_clk";
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
};
...

3
Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
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@ -15,8 +15,6 @@ description: |
domains.
See also::
include/dt-bindings/clock/qcom,gcc-ipq6018.h
include/dt-bindings/reset/qcom,gcc-ipq6018.h
include/dt-bindings/clock/qcom,gcc-msm8953.h
include/dt-bindings/clock/qcom,gcc-mdm9607.h
@ -26,7 +24,6 @@ allOf:
properties:
compatible:
enum:
- qcom,gcc-ipq6018
- qcom,gcc-mdm9607
required:

68
Documentation/devicetree/bindings/clock/qcom,qdu1000-ecpricc.yaml Normal file
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@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,qdu1000-ecpricc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm ECPRI Clock & Reset Controller for QDU1000 and QRU1000
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
- Imran Shaik <quic_imrashai@quicinc.com>
description: |
Qualcomm ECPRI Specification V2.0 Common Public Radio Interface clock control
module which supports the clocks, resets on QDU1000 and QRU1000
See also:: include/dt-bindings/clock/qcom,qdu1000-ecpricc.h
properties:
compatible:
enum:
- qcom,qdu1000-ecpricc
reg:
maxItems: 1
clocks:
items:
- description: Board XO source
- description: GPLL0 source from GCC
- description: GPLL1 source from GCC
- description: GPLL2 source from GCC
- description: GPLL3 source from GCC
- description: GPLL4 source from GCC
- description: GPLL5 source from GCC
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,qdu1000-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@280000 {
compatible = "qcom,qdu1000-ecpricc";
reg = <0x00280000 0x31c00>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>,
<&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>,
<&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>,
<&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>,
<&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>,
<&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>;
#clock-cells = <1>;
#reset-cells = <1>;
};

2
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
View File

@ -35,6 +35,8 @@ properties:
- qcom,sm8350-rpmh-clk
- qcom,sm8450-rpmh-clk
- qcom,sm8550-rpmh-clk
- qcom,sm8650-rpmh-clk
- qcom,x1e80100-rpmh-clk
clocks:
maxItems: 1

18
Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml
View File

@ -15,6 +15,9 @@ description: |
See also:: include/dt-bindings/clock/qcom,camcc-sc7180.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
const: qcom,sc7180-camcc
@ -31,28 +34,15 @@ properties:
- const: iface
- const: xo
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
unevaluatedProperties: false
examples:
- |

18
Documentation/devicetree/bindings/clock/qcom,sc7280-camcc.yaml
View File

@ -15,6 +15,9 @@ description: |
See also:: include/dt-bindings/clock/qcom,camcc-sc7280.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
const: qcom,sc7280-camcc
@ -31,28 +34,15 @@ properties:
- const: bi_tcxo_ao
- const: sleep_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
unevaluatedProperties: false
examples:
- |

18
Documentation/devicetree/bindings/clock/qcom,sdm845-camcc.yaml
View File

@ -15,6 +15,9 @@ description: |
See also:: include/dt-bindings/clock/qcom,camcc-sm845.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
const: qcom,sdm845-camcc
@ -27,28 +30,15 @@ properties:
items:
- const: bi_tcxo
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
unevaluatedProperties: false
examples:
- |

20
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
View File

@ -16,10 +16,15 @@ description: |
See also::
include/dt-bindings/clock/qcom,sm8450-camcc.h
include/dt-bindings/clock/qcom,sm8550-camcc.h
include/dt-bindings/clock/qcom,sc8280xp-camcc.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
enum:
- qcom,sc8280xp-camcc
- qcom,sm8450-camcc
- qcom,sm8550-camcc
@ -40,29 +45,16 @@ properties:
description:
A phandle to an OPP node describing required MMCX performance point.
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- power-domains
- required-opps
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
unevaluatedProperties: false
examples:
- |

2
Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
View File

@ -17,12 +17,14 @@ description: |
include/dt-bindings/clock/qcom,sm8450-gpucc.h
include/dt-bindings/clock/qcom,sm8550-gpucc.h
include/dt-bindings/reset/qcom,sm8450-gpucc.h
include/dt-bindings/reset/qcom,sm8650-gpucc.h
properties:
compatible:
enum:
- qcom,sm8450-gpucc
- qcom,sm8550-gpucc
- qcom,sm8650-gpucc
clocks:
items:

8
Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
View File

@ -13,12 +13,16 @@ description: |
Qualcomm TCSR clock control module provides the clocks, resets and
power domains on SM8550
See also:: include/dt-bindings/clock/qcom,sm8550-tcsr.h
See also:
- include/dt-bindings/clock/qcom,sm8550-tcsr.h
- include/dt-bindings/clock/qcom,sm8650-tcsr.h
properties:
compatible:
items:
- const: qcom,sm8550-tcsr
- enum:
- qcom,sm8550-tcsr
- qcom,sm8650-tcsr
- const: syscon
clocks:

106
Documentation/devicetree/bindings/clock/qcom,sm8650-dispcc.yaml Normal file
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@ -0,0 +1,106 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8650-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller for SM8650
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Neil Armstrong <neil.armstrong@linaro.org>
description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SM8650.
See also:: include/dt-bindings/clock/qcom,sm8650-dispcc.h
properties:
compatible:
enum:
- qcom,sm8650-dispcc
clocks:
items:
- description: Board XO source
- description: Board Always On XO source
- description: Display's AHB clock
- description: sleep clock
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
- description: Byte clock from DSI PHY1
- description: Pixel clock from DSI PHY1
- description: Link clock from DP PHY0
- description: VCO DIV clock from DP PHY0
- description: Link clock from DP PHY1
- description: VCO DIV clock from DP PHY1
- description: Link clock from DP PHY2
- description: VCO DIV clock from DP PHY2
- description: Link clock from DP PHY3
- description: VCO DIV clock from DP PHY3
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
power-domains:
description:
A phandle and PM domain specifier for the MMCX power domain.
maxItems: 1
required-opps:
description:
A phandle to an OPP node describing required MMCX performance point.
maxItems: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,sm8650-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@af00000 {
compatible = "qcom,sm8650-dispcc";
reg = <0x0af00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&gcc GCC_DISP_AHB_CLK>,
<&sleep_clk>,
<&dsi0_phy 0>,
<&dsi0_phy 1>,
<&dsi1_phy 0>,
<&dsi1_phy 1>,
<&dp0_phy 0>,
<&dp0_phy 1>,
<&dp1_phy 0>,
<&dp1_phy 1>,
<&dp2_phy 0>,
<&dp2_phy 1>,
<&dp3_phy 0>,
<&dp3_phy 1>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
};
...

65
Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml Normal file
View File

@ -0,0 +1,65 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8650-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on SM8650
maintainers:
- Bjorn Andersson <andersson@kernel.org>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8650
See also:: include/dt-bindings/clock/qcom,sm8650-gcc.h
properties:
compatible:
const: qcom,sm8650-gcc
clocks:
items:
- description: Board XO source
- description: Board Always On XO source
- description: Sleep clock source
- description: PCIE 0 Pipe clock source
- description: PCIE 1 Pipe clock source
- description: PCIE 1 Phy Auxiliary clock source
- description: UFS Phy Rx symbol 0 clock source
- description: UFS Phy Rx symbol 1 clock source
- description: UFS Phy Tx symbol 0 clock source
- description: USB3 Phy wrapper pipe clock source
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,sm8650-gcc";
reg = <0x00100000 0x001f4200>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
<&pcie0_phy>,
<&pcie1_phy>,
<&pcie_1_phy_aux_clk>,
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
<&usb_1_qmpphy>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

72
Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml Normal file
View File

@ -0,0 +1,72 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,x1e80100-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on X1E80100
maintainers:
- Rajendra Nayak <quic_rjendra@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on X1E80100
See also:: include/dt-bindings/clock/qcom,x1e80100-gcc.h
properties:
compatible:
const: qcom,x1e80100-gcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: PCIe 3 pipe clock
- description: PCIe 4 pipe clock
- description: PCIe 5 pipe clock
- description: PCIe 6a pipe clock
- description: PCIe 6b pipe clock
- description: USB QMP Phy 0 clock source
- description: USB QMP Phy 1 clock source
- description: USB QMP Phy 2 clock source
power-domains:
description:
A phandle and PM domain specifier for the CX power domain.
maxItems: 1
required:
- compatible
- clocks
- power-domains
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@100000 {
compatible = "qcom,x1e80100-gcc";
reg = <0x00100000 0x200000>;
clocks = <&bi_tcxo_div2>,
<&sleep_clk>,
<&pcie3_phy>,
<&pcie4_phy>,
<&pcie5_phy>,
<&pcie6a_phy>,
<&pcie6b_phy>,
<&usb_1_ss0_qmpphy 0>,
<&usb_1_ss1_qmpphy 1>,
<&usb_1_ss2_qmpphy 2>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

31
Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
View File

@ -31,11 +31,11 @@ properties:
clocks:
description: List of clock specifiers which are external input
clocks to the given clock controller.
minItems: 3
minItems: 2
maxItems: 8
clock-names:
minItems: 3
minItems: 2
maxItems: 8
required:
@ -59,15 +59,34 @@ allOf:
clocks:
items:
- description: reference clock
- description: alternate reference clock
- description: alternate reference clock for programmable logic
clock-names:
items:
- const: ref
- const: alt_ref
- const: pl_alt_ref
- if:
properties:
compatible:
contains:
enum:
- xlnx,versal-net-clk
then:
properties:
clocks:
items:
- description: reference clock
- description: alternate reference clock for programmable logic
- description: alternate reference clock
clock-names:
items:
- const: ref
- const: pl_alt_ref
- const: alt_ref
- if:
properties:
compatible:
@ -110,8 +129,8 @@ examples:
versal_clk: clock-controller {
#clock-cells = <1>;
compatible = "xlnx,versal-clk";
clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
clock-names = "ref", "alt_ref", "pl_alt_ref";
clocks = <&ref>, <&pl_alt_ref>;
clock-names = "ref", "pl_alt_ref";
};
};
};

4
Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
View File

@ -95,8 +95,8 @@ examples:
versal_clk: clock-controller {
#clock-cells = <1>;
compatible = "xlnx,versal-clk";
clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
clock-names = "ref", "alt_ref", "pl_alt_ref";
clocks = <&ref>, <&pl_alt_ref>;
clock-names = "ref", "pl_alt_ref";
};
};

65
Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
View File

@ -15,15 +15,22 @@ description:
properties:
compatible:
items:
- enum:
- mediatek,mt7622-sgmiisys
- mediatek,mt7629-sgmiisys
- mediatek,mt7981-sgmiisys_0
- mediatek,mt7981-sgmiisys_1
- mediatek,mt7986-sgmiisys_0
- mediatek,mt7986-sgmiisys_1
- const: syscon
oneOf:
- items:
- enum:
- mediatek,mt7622-sgmiisys
- mediatek,mt7629-sgmiisys
- mediatek,mt7981-sgmiisys_0
- mediatek,mt7981-sgmiisys_1
- mediatek,mt7986-sgmiisys_0
- mediatek,mt7986-sgmiisys_1
- const: syscon
- items:
- enum:
- mediatek,mt7988-sgmiisys0
- mediatek,mt7988-sgmiisys1
- const: simple-mfd
- const: syscon
reg:
maxItems: 1
@ -35,11 +42,51 @@ properties:
description: Invert polarity of the SGMII data lanes
type: boolean
pcs:
type: object
description: MediaTek LynxI HSGMII PCS
properties:
compatible:
const: mediatek,mt7988-sgmii
clocks:
maxItems: 3
clock-names:
items:
- const: sgmii_sel
- const: sgmii_tx
- const: sgmii_rx
required:
- compatible
- clocks
- clock-names
additionalProperties: false
required:
- compatible
- reg
- '#clock-cells'
allOf:
- if:
properties:
compatible:
contains:
enum:
- mediatek,mt7988-sgmiisys0
- mediatek,mt7988-sgmiisys1
then:
required:
- pcs
else:
properties:
pcs: false
additionalProperties: false
examples:

24
drivers/clk/imx/clk-imx8qxp.c
View File

@ -66,6 +66,22 @@ static const char * const lcd_pxl_sels[] = {
"lcd_pxl_bypass_div_clk",
};
static const char *const lvds0_sels[] = {
"clk_dummy",
"clk_dummy",
"clk_dummy",
"clk_dummy",
"mipi0_lvds_bypass_clk",
};
static const char *const lvds1_sels[] = {
"clk_dummy",
"clk_dummy",
"clk_dummy",
"clk_dummy",
"mipi1_lvds_bypass_clk",
};
static const char * const mipi_sels[] = {
"clk_dummy",
"clk_dummy",
@ -207,9 +223,9 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
/* MIPI-LVDS SS */
imx_clk_scu("mipi0_bypass_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_BYPASS);
imx_clk_scu("mipi0_pixel_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("mipi0_lvds_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2);
imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS);
imx_clk_scu("mipi0_lvds_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3);
imx_clk_scu2("mipi0_lvds_pixel_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2);
imx_clk_scu2("mipi0_lvds_phy_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3);
imx_clk_scu2("mipi0_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_MST_BUS);
imx_clk_scu2("mipi0_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_SLV_BUS);
imx_clk_scu2("mipi0_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PHY);
@ -219,9 +235,9 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
imx_clk_scu("mipi1_bypass_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_BYPASS);
imx_clk_scu("mipi1_pixel_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("mipi1_lvds_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2);
imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS);
imx_clk_scu("mipi1_lvds_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3);
imx_clk_scu2("mipi1_lvds_pixel_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2);
imx_clk_scu2("mipi1_lvds_phy_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3);
imx_clk_scu2("mipi1_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_MST_BUS);
imx_clk_scu2("mipi1_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_SLV_BUS);

23
drivers/clk/imx/clk-pll14xx.c
View File

@ -104,15 +104,15 @@ static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
static long pll14xx_calc_rate(struct clk_pll14xx *pll, int mdiv, int pdiv,
int sdiv, int kdiv, unsigned long prate)
{
u64 fvco = prate;
u64 fout = prate;
/* fvco = (m * 65536 + k) * Fin / (p * 65536) */
fvco *= (mdiv * 65536 + kdiv);
/* fout = (m * 65536 + k) * Fin / (p * 65536) / (1 << sdiv) */
fout *= (mdiv * 65536 + kdiv);
pdiv *= 65536;
do_div(fvco, pdiv << sdiv);
do_div(fout, pdiv << sdiv);
return fvco;
return fout;
}
static long pll1443x_calc_kdiv(int mdiv, int pdiv, int sdiv,
@ -131,7 +131,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat
{
u32 pll_div_ctl0, pll_div_ctl1;
int mdiv, pdiv, sdiv, kdiv;
long fvco, rate_min, rate_max, dist, best = LONG_MAX;
long fout, rate_min, rate_max, dist, best = LONG_MAX;
const struct imx_pll14xx_rate_table *tt;
/*
@ -143,6 +143,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat
* d) -32768 <= k <= 32767
*
* fvco = (m * 65536 + k) * prate / (p * 65536)
* fout = (m * 65536 + k) * prate / (p * 65536) / (1 << sdiv)
*/
/* First try if we can get the desired rate from one of the static entries */
@ -173,8 +174,8 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat
pr_debug("%s: in=%ld, want=%ld Only adjust kdiv %ld -> %d\n",
clk_hw_get_name(&pll->hw), prate, rate,
FIELD_GET(KDIV_MASK, pll_div_ctl1), kdiv);
fvco = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate);
t->rate = (unsigned int)fvco;
fout = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate);
t->rate = (unsigned int)fout;
t->mdiv = mdiv;
t->pdiv = pdiv;
t->sdiv = sdiv;
@ -190,13 +191,13 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat
mdiv = clamp(mdiv, 64, 1023);
kdiv = pll1443x_calc_kdiv(mdiv, pdiv, sdiv, rate, prate);
fvco = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate);
fout = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate);
/* best match */
dist = abs((long)rate - (long)fvco);
dist = abs((long)rate - (long)fout);
if (dist < best) {
best = dist;
t->rate = (unsigned int)fvco;
t->rate = (unsigned int)fout;
t->mdiv = mdiv;
t->pdiv = pdiv;
t->sdiv = sdiv;

4
drivers/clk/imx/clk-scu.c
View File

@ -886,8 +886,10 @@ struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_na
return ERR_PTR(-EINVAL);
}
if (!imx_clk_is_resource_owned(rsrc_id))
if (!imx_clk_is_resource_owned(rsrc_id)) {
kfree(clk_node);
return NULL;
}
clk = kzalloc(sizeof(*clk), GFP_KERNEL);
if (!clk) {

9
drivers/clk/mediatek/Kconfig
View File

@ -423,6 +423,15 @@ config COMMON_CLK_MT7986_ETHSYS
This driver adds support for clocks for Ethernet and SGMII
required on MediaTek MT7986 SoC.
config COMMON_CLK_MT7988
tristate "Clock driver for MediaTek MT7988"
depends on ARCH_MEDIATEK || COMPILE_TEST
select COMMON_CLK_MEDIATEK
default ARCH_MEDIATEK
help
This driver supports MediaTek MT7988 basic clocks and clocks
required for various periperals found on this SoC.
config COMMON_CLK_MT8135
tristate "Clock driver for MediaTek MT8135"
depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST

5
drivers/clk/mediatek/Makefile
View File

@ -62,6 +62,11 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o
obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o
obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o
obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o
obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o
obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o
obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-xfipll.o
obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135-apmixedsys.o clk-mt8135.o
obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167-apmixedsys.o clk-mt8167.o
obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o

114
drivers/clk/mediatek/clk-mt7988-apmixed.c Normal file
View File

@ -0,0 +1,114 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
* Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
*/
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include "clk-mux.h"
#include "clk-pll.h"
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
#define MT7988_PLL_FMAX (2500UL * MHZ)
#define MT7988_PCW_CHG_BIT 2
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, _pd_reg, \
_pd_shift, _tuner_reg, _tuner_en_reg, _tuner_en_bit, _pcw_reg, _pcw_shift, \
_pcw_chg_reg) \
{ \
.id = _id, \
.name = _name, \
.reg = _reg, \
.pwr_reg = _pwr_reg, \
.en_mask = _en_mask, \
.flags = _flags, \
.rst_bar_mask = BIT(_rst_bar_mask), \
.fmax = MT7988_PLL_FMAX, \
.pcwbits = _pcwbits, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.tuner_reg = _tuner_reg, \
.tuner_en_reg = _tuner_en_reg, \
.tuner_en_bit = _tuner_en_bit, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
.pcw_chg_reg = _pcw_chg_reg, \
.pcw_chg_bit = MT7988_PCW_CHG_BIT, \
.parent_name = "clkxtal", \
}
static const struct mtk_pll_data plls[] = {
PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, 0, 32, 0x0104, 4, 0,
0, 0, 0x0108, 0, 0x0104),
PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0114, 4,
0, 0, 0, 0x0118, 0, 0x0114),
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0124, 4,
0, 0, 0, 0x0128, 0, 0x0124),
PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, 0x0134, 4, 0x0704,
0x0700, 1, 0x0138, 0, 0x0134),
PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, HAVE_RST_BAR, 23, 32,
0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),
PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23,
32, 0x0154, 4, 0, 0, 0, 0x0158, 0, 0x0154),
PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, 0, 32, 0x0164, 4, 0,
0, 0, 0x0168, 0, 0x0164),
PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32, 0x0174, 4, 0, 0, 0,
0x0178, 0, 0x0174),
PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23, 32,
0x0204, 4, 0, 0, 0, 0x0208, 0, 0x0204),
PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001, HAVE_RST_BAR, 23, 32,
0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214),
PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001, HAVE_RST_BAR, 23, 32,
0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304),
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0, 32, 0x0314, 4, 0, 0,
0, 0x0318, 0, 0x0314),
};
static const struct of_device_id of_match_clk_mt7988_apmixed[] = {
{ .compatible = "mediatek,mt7988-apmixedsys" },
{ /* sentinel */ }
};
static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
if (!clk_data)
return -ENOMEM;
r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
if (r)
goto free_apmixed_data;
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto unregister_plls;
return r;
unregister_plls:
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
free_apmixed_data:
mtk_free_clk_data(clk_data);
return r;
}
static struct platform_driver clk_mt7988_apmixed_drv = {
.probe = clk_mt7988_apmixed_probe,
.driver = {
.name = "clk-mt7988-apmixed",
.of_match_table = of_match_clk_mt7988_apmixed,
},
};
builtin_platform_driver(clk_mt7988_apmixed_drv);
MODULE_LICENSE("GPL");

150
drivers/clk/mediatek/clk-mt7988-eth.c Normal file
View File

@ -0,0 +1,150 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
* Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
*/
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include "reset.h"
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
#include <dt-bindings/reset/mediatek,mt7988-resets.h>
static const struct mtk_gate_regs ethdma_cg_regs = {
.set_ofs = 0x30,
.clr_ofs = 0x30,
.sta_ofs = 0x30,
};
#define GATE_ETHDMA(_id, _name, _parent, _shift) \
{ \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &ethdma_cg_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
}
static const struct mtk_gate ethdma_clks[] = {
GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0),
GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1),
GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2),
GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6),
GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7),
GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8),
GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10),
GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16),
GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel", 29),
};
static const struct mtk_clk_desc ethdma_desc = {
.clks = ethdma_clks,
.num_clks = ARRAY_SIZE(ethdma_clks),
};
static const struct mtk_gate_regs sgmii_cg_regs = {
.set_ofs = 0xe4,
.clr_ofs = 0xe4,
.sta_ofs = 0xe4,
};
#define GATE_SGMII(_id, _name, _parent, _shift) \
{ \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &sgmii_cg_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
}
static const struct mtk_gate sgmii0_clks[] = {
GATE_SGMII(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2),
GATE_SGMII(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3),
};
static const struct mtk_clk_desc sgmii0_desc = {
.clks = sgmii0_clks,
.num_clks = ARRAY_SIZE(sgmii0_clks),
};
static const struct mtk_gate sgmii1_clks[] = {
GATE_SGMII(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2),
GATE_SGMII(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3),
};
static const struct mtk_clk_desc sgmii1_desc = {
.clks = sgmii1_clks,
.num_clks = ARRAY_SIZE(sgmii1_clks),
};
static const struct mtk_gate_regs ethwarp_cg_regs = {
.set_ofs = 0x14,
.clr_ofs = 0x14,
.sta_ofs = 0x14,
};
#define GATE_ETHWARP(_id, _name, _parent, _shift) \
{ \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &ethwarp_cg_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
}
static const struct mtk_gate ethwarp_clks[] = {
GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", "netsys_mcu_sel", 13),
GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", "netsys_mcu_sel", 14),
GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", "netsys_mcu_sel", 15),
};
static u16 ethwarp_rst_ofs[] = { 0x8 };
static u16 ethwarp_idx_map[] = {
[MT7988_ETHWARP_RST_SWITCH] = 9,
};
static const struct mtk_clk_rst_desc ethwarp_rst_desc = {
.version = MTK_RST_SIMPLE,
.rst_bank_ofs = ethwarp_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(ethwarp_rst_ofs),
.rst_idx_map = ethwarp_idx_map,
.rst_idx_map_nr = ARRAY_SIZE(ethwarp_idx_map),
};
static const struct mtk_clk_desc ethwarp_desc = {
.clks = ethwarp_clks,
.num_clks = ARRAY_SIZE(ethwarp_clks),
.rst_desc = &ethwarp_rst_desc,
};
static const struct of_device_id of_match_clk_mt7988_eth[] = {
{ .compatible = "mediatek,mt7988-ethsys", .data = &ethdma_desc },
{ .compatible = "mediatek,mt7988-sgmiisys0", .data = &sgmii0_desc },
{ .compatible = "mediatek,mt7988-sgmiisys1", .data = &sgmii1_desc },
{ .compatible = "mediatek,mt7988-ethwarp", .data = &ethwarp_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth);
static struct platform_driver clk_mt7988_eth_drv = {
.driver = {
.name = "clk-mt7988-eth",
.of_match_table = of_match_clk_mt7988_eth,
},
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt7988_eth_drv);
MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver");
MODULE_LICENSE("GPL");

275
drivers/clk/mediatek/clk-mt7988-infracfg.c Normal file
View File

@ -0,0 +1,275 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
* Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
*/
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include "clk-mux.h"
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
static DEFINE_SPINLOCK(mt7988_clk_lock);
static const char *const infra_mux_uart0_parents[] __initconst = { "csw_infra_f26m_sel",
"uart_sel" };
static const char *const infra_mux_uart1_parents[] __initconst = { "csw_infra_f26m_sel",
"uart_sel" };
static const char *const infra_mux_uart2_parents[] __initconst = { "csw_infra_f26m_sel",
"uart_sel" };
static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel", "spi_sel" };
static const char *const infra_mux_spi1_parents[] __initconst = { "i2c_sel", "spim_mst_sel" };
static const char *const infra_pwm_bck_parents[] __initconst = { "top_rtc_32p7k",
"csw_infra_f26m_sel", "sysaxi_sel",
"pwm_sel" };
static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = {
"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_sel"
};
static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = {
"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p1_sel"
};
static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = {
"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p2_sel"
};
static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = {
"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p3_sel"
};
static const struct mtk_mux infra_muxes[] = {
/* MODULE_CLK_SEL_0 */
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", infra_mux_spi0_parents,
0x0018, 0x0010, 0x0014, 4, 1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", infra_mux_spi1_parents,
0x0018, 0x0010, 0x0014, 5, 1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", infra_mux_spi0_parents,
0x0018, 0x0010, 0x0014, 6, 1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x0018,
0x0010, 0x0014, 14, 2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", infra_pwm_bck_parents,
0x0018, 0x0010, 0x0014, 16, 2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", infra_pwm_bck_parents,
0x0018, 0x0010, 0x0014, 18, 2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", infra_pwm_bck_parents,
0x0018, 0x0010, 0x0014, 20, 2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", infra_pwm_bck_parents,
0x0018, 0x0010, 0x0014, 22, 2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", infra_pwm_bck_parents,
0x0018, 0x0010, 0x0014, 24, 2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", infra_pwm_bck_parents,
0x0018, 0x0010, 0x0014, 26, 2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", infra_pwm_bck_parents,
0x0018, 0x0010, 0x0014, 28, 2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", infra_pwm_bck_parents,
0x0018, 0x0010, 0x0014, 30, 2, -1, -1, -1),
/* MODULE_CLK_SEL_1 */
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_o_p0_sel",
infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, 0x0020, 0x0024, 0, 2, -1,
-1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_o_p1_sel",
infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, 0x0020, 0x0024, 2, 2, -1,
-1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, "infra_pcie_gfmux_tl_o_p2_sel",
infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, 0x0020, 0x0024, 4, 2, -1,
-1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, "infra_pcie_gfmux_tl_o_p3_sel",
infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, 0x0020, 0x0024, 6, 2, -1,
-1, -1),
};
static const struct mtk_gate_regs infra0_cg_regs = {
.set_ofs = 0x10,
.clr_ofs = 0x14,
.sta_ofs = 0x18,
};
static const struct mtk_gate_regs infra1_cg_regs = {
.set_ofs = 0x40,
.clr_ofs = 0x44,
.sta_ofs = 0x48,
};
static const struct mtk_gate_regs infra2_cg_regs = {
.set_ofs = 0x50,
.clr_ofs = 0x54,
.sta_ofs = 0x58,
};
static const struct mtk_gate_regs infra3_cg_regs = {
.set_ofs = 0x60,
.clr_ofs = 0x64,
.sta_ofs = 0x68,
};
#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
_flags)
#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
_flags)
#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
_flags)
#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
_flags)
#define GATE_INFRA0(_id, _name, _parent, _shift) GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_INFRA1(_id, _name, _parent, _shift) GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_INFRA2(_id, _name, _parent, _shift) GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_INFRA3(_id, _name, _parent, _shift) GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
static const struct mtk_gate infra_clks[] = {
/* INFRA0 */
GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0, "infra_pcie_peri_ck_26m_ck_p0",
"csw_infra_f26m_sel", 7),
GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1",
"csw_infra_f26m_sel", 8),
GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2",
"csw_infra_f26m_sel", 9),
GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3",
"csw_infra_f26m_sel", 10),
/* INFRA1 */
GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", "sysaxi_sel", 0),
GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", "sysaxi_sel", 1),
GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", "infra_pwm_sel", 2),
GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", "infra_pwm_ck1_sel", 3),
GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", "infra_pwm_ck2_sel", 4),
GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", "infra_pwm_ck3_sel", 5),
GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", "infra_pwm_ck4_sel", 6),
GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", "infra_pwm_ck5_sel", 7),
GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", "infra_pwm_ck6_sel", 8),
GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", "infra_pwm_ck7_sel", 9),
GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", "infra_pwm_ck8_sel", 10),
GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", "sysaxi_sel", 12),
GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", "sysaxi_sel", 13),
GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m", "csw_infra_f26m_sel", 14),
GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15),
GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16),
GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18),
GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "csw_infra_f26m_sel", 19,
CLK_IS_CRITICAL),
/* JTAG */
GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", "sysaxi_sel", 20,
CLK_IS_CRITICAL),
GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", "sysaxi_sel", 21),
GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", "sysaxi_sel", 29),
GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", "csw_infra_f26m_sel", 30),
/* INFRA2 */
GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", "csw_infra_f26m_sel",
0),
GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1),
GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", "infra_mux_uart0_sel", 3),
GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", "infra_mux_uart1_sel", 4),
GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", "infra_mux_uart2_sel", 5),
GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9),
GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10),
GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", "sysaxi_sel", 11,
CLK_IS_CRITICAL),
GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12,
CLK_IS_CRITICAL),
GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", "infra_mux_spi1_sel", 13),
GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", "infra_mux_spi2_sel", 14),
GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15,
CLK_IS_CRITICAL),
GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", "sysaxi_sel", 16),
GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", "sysaxi_sel", 17),
GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", "sysaxi_sel", 18),
GATE_INFRA2_FLAGS(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", 19, CLK_IS_CRITICAL),
GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", "csw_infra_f26m_sel", 20),
GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck", 21),
GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel", 22),
GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel", 23),
GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", "sysaxi_sel", 24),
GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", "sysaxi_sel", 25),
GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", "sysaxi_sel", 26),
GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27),
GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29),
GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31),
/* INFRA3 */
GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel", 0),
GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", "sysaxi_sel", 1),
GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel", 2),
GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", "sysaxi_sel", 3),
GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4),
GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", "usb_sys_p1_sel", 5),
GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6),
GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7),
GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", "usb_frmcnt_sel", 8,
CLK_IS_CRITICAL),
GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", "usb_frmcnt_p1_sel",
9, CLK_IS_CRITICAL),
GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10),
GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", "usb_phy_sel", 11),
GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12),
GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", "top_xtal", 13),
GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14),
GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", "usb_xhci_p1_sel", 15),
GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
"infra_pcie_gfmux_tl_o_p0_sel", 20),
GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
"infra_pcie_gfmux_tl_o_p1_sel", 21),
GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
"infra_pcie_gfmux_tl_o_p2_sel", 22),
GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
"infra_pcie_gfmux_tl_o_p3_sel", 23),
GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", "top_xtal", 24),
GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", "top_xtal", 25),
GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", "top_xtal", 26),
GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", "top_xtal", 27),
GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", "sysaxi_sel", 28),
GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", "sysaxi_sel", 29),
GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", "sysaxi_sel", 30),
GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31),
};
static const struct mtk_clk_desc infra_desc = {
.clks = infra_clks,
.num_clks = ARRAY_SIZE(infra_clks),
.mux_clks = infra_muxes,
.num_mux_clks = ARRAY_SIZE(infra_muxes),
.clk_lock = &mt7988_clk_lock,
};
static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
{ .compatible = "mediatek,mt7988-infracfg", .data = &infra_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_infracfg);
static struct platform_driver clk_mt7988_infracfg_drv = {
.driver = {
.name = "clk-mt7988-infracfg",
.of_match_table = of_match_clk_mt7988_infracfg,
},
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt7988_infracfg_drv);
MODULE_LICENSE("GPL");

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drivers/clk/mediatek/clk-mt7988-topckgen.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
* Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
*/
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include "clk-mux.h"
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
static DEFINE_SPINLOCK(mt7988_clk_lock);
static const struct mtk_fixed_clk top_fixed_clks[] = {
FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
};
static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2),
FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2),
FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4),
FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8),
FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16),
FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15),
FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12),
FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8),
FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4),
FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5),
FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10),
FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20),
FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8),
FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16),
FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32),
FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64),
FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128),
FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2),
FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4),
FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16),
FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32),
FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6),
FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8),
};
static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2", "mmpll_d2" };
static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5", "net1pll_d5_d2" };
static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll", "mmpll" };
static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4", "net1pll_d5" };
static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" };
static const char *const netsys_mcu_parents[] = { "top_xtal", "net2pll", "mmpll",
"net1pll_d4", "net1pll_d5", "mpll" };
static const char *const eip197_parents[] = { "top_xtal", "netsyspll", "net2pll",
"mmpll", "net1pll_d4", "net1pll_d5" };
static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" };
static const char *const uart_parents[] = { "top_xtal", "mpll_d8", "mpll_d8_d2" };
static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2", "mmpll_d4" };
static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll", "mmpll_d2",
"mpll_d2", "mmpll_d4", "net1pll_d8_d2" };
static const char *const spi_parents[] = { "top_xtal", "mpll_d2", "mmpll_d4",
"net1pll_d8_d2", "net2pll_d6", "net1pll_d5_d4",
"mpll_d4", "net1pll_d8_d4" };
static const char *const nfi1x_parents[] = { "top_xtal", "mmpll_d4", "net1pll_d8_d2", "net2pll_d6",
"mpll_d4", "mmpll_d8", "net1pll_d8_d4", "mpll_d8" };
static const char *const spinfi_parents[] = { "top_xtal_d2", "top_xtal", "net1pll_d5_d4",
"mpll_d4", "mmpll_d8", "net1pll_d8_d4",
"mmpll_d6_d2", "mpll_d8" };
static const char *const pwm_parents[] = { "top_xtal", "net1pll_d8_d2", "net1pll_d5_d4",
"mpll_d4", "mpll_d8_d2", "top_rtc_32k" };
static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4", "mpll_d4",
"net1pll_d8_d4" };
static const char *const pcie_mbist_250m_parents[] = { "top_xtal", "net1pll_d5_d2" };
static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6", "mmpll_d8",
"mpll_d8_d2", "top_rtc_32k" };
static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" };
static const char *const aud_parents[] = { "top_xtal", "apll2" };
static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" };
static const char *const aud_l_parents[] = { "top_xtal", "apll2", "mpll_d8_d2" };
static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" };
static const char *const usxgmii_sbus_0_parents[] = { "top_xtal", "net1pll_d8_d4" };
static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" };
static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" };
static const char *const eth_refck_50m_parents[] = { "top_xtal", "net2pll_d4_d4" };
static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" };
static const char *const eth_xgmii_parents[] = { "top_xtal_d2", "net1pll_d8_d8", "net1pll_d8_d16" };
static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5", "net2pll_d2" };
static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" };
static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2", "wedmcupll" };
static const char *const da_xtp_glb_p0_parents[] = { "top_xtal", "net2pll_d8" };
static const char *const mcusys_backup_625m_parents[] = { "top_xtal", "net1pll_d4" };
static const char *const macsec_parents[] = { "top_xtal", "sgmpll", "net1pll_d8" };
static const char *const netsys_tops_400m_parents[] = { "top_xtal", "net2pll_d2" };
static const char *const eth_mii_parents[] = { "top_xtal_d2", "net2pll_d4_d8" };
static const struct mtk_mux top_muxes[] = {
/* CLK_CFG_0 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x000, 0x004, 0x008,
0, 2, 7, 0x1c0, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x000,
0x004, 0x008, 8, 2, 15, 0x1C0, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x000,
0x004, 0x008, 16, 2, 23, 0x1C0, 2),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, 0x000,
0x004, 0x008, 24, 2, 31, 0x1C0, 3),
/* CLK_CFG_1 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x010, 0x014,
0x018, 0, 1, 7, 0x1C0, 4),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, 0x010,
0x014, 0x018, 8, 3, 15, 0x1C0, 5),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", netsys_mcu_parents,
0x010, 0x014, 0x018, 16, 3, 23, 0x1C0, 6),
MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x010, 0x014, 0x018,
24, 3, 31, 0x1c0, 7),
/* CLK_CFG_2 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x020,
0x024, 0x028, 0, 1, 7, 0x1C0, 8, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020, 0x024, 0x028, 8, 2,
15, 0x1c0, 9),
MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020,
0x024, 0x028, 16, 2, 23, 0x1C0, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x020,
0x024, 0x028, 24, 3, 31, 0x1C0, 11),
/* CLK_CFG_3 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030, 0x034, 0x038, 0, 3, 7,
0x1c0, 12),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x030, 0x034, 0x038,
8, 3, 15, 0x1c0, 13),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x030, 0x034, 0x038, 16,
3, 23, 0x1c0, 14),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x030, 0x034, 0x038,
24, 3, 31, 0x1c0, 15),
/* CLK_CFG_4 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040, 0x044, 0x048, 0, 3, 7,
0x1c0, 16),
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040, 0x044, 0x048, 8, 2, 15,
0x1c0, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
pcie_mbist_250m_parents, 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel", pextp_tl_ck_parents, 0x040,
0x044, 0x048, 24, 3, 31, 0x1C0, 19),
/* CLK_CFG_5 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel", pextp_tl_ck_parents, 0x050,
0x054, 0x058, 0, 3, 7, 0x1C0, 20),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel", pextp_tl_ck_parents, 0x050,
0x054, 0x058, 8, 3, 15, 0x1C0, 21),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel", pextp_tl_ck_parents, 0x050,
0x054, 0x058, 16, 3, 23, 0x1C0, 22),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x050, 0x054,
0x058, 24, 1, 31, 0x1C0, 23),
/* CLK_CFG_6 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x060,
0x064, 0x068, 0, 1, 7, 0x1C0, 24),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x060, 0x064,
0x068, 8, 1, 15, 0x1C0, 25),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents, 0x060,
0x064, 0x068, 16, 1, 23, 0x1C0, 26),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents, 0x060,
0x064, 0x068, 24, 1, 31, 0x1C0, 27),
/* CLK_CFG_7 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", usb_frmcnt_parents,
0x070, 0x074, 0x078, 0, 1, 7, 0x1C0, 28),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070, 0x074, 0x078, 8, 1, 15,
0x1c0, 29),
MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x070, 0x074, 0x078, 16,
1, 23, 0x1c0, 30),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074, 0x078, 24,
2, 31, 0x1c4, 0),
/* CLK_CFG_8 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x080, 0x084, 0x088,
0, 1, 7, 0x1c4, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x080, 0x084, 0x088,
8, 1, 15, 0x1c4, 2),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x080, 0x084,
0x088, 16, 1, 23, 0x1c4, 3),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24, 1, 31, 0x1C4, 4),
/* CLK_CFG_9 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x090, 0x094, 0x098, 8,
1, 15, 0x1c4, 6),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents,
0x090, 0x094, 0x098, 16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x090, 0x094, 0x098, 24,
1, 31, 0x1c4, 8),
/* CLK_CFG_10 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents,
0x0a0, 0x0a4, 0x0a8, 0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,
0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x1C4, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents,
0x0a0, 0x0a4, 0x0a8, 16, 1, 23, 0x1C4, 11),
/* CLK_CFG_11 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0x0a0,
0x0a4, 0x0a8, 24, 1, 31, 0x1C4, 12, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x0b0, 0x0b4,
0x0b8, 0, 1, 7, 0x1c4, 13, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", eth_refck_50m_parents,
0x0b0, 0x0b4, 0x0b8, 8, 1, 15, 0x1C4, 14),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", eth_sys_200m_parents,
0x0b0, 0x0b4, 0x0b8, 16, 1, 23, 0x1C4, 15),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents, 0x0b0,
0x0b4, 0x0b8, 24, 1, 31, 0x1C4, 16),
/* CLK_CFG_12 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0x0c0,
0x0c4, 0x0c8, 0, 2, 7, 0x1C4, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0x0c0, 0x0c4,
0x0c8, 8, 2, 15, 0x1C4, 18),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0x0c0, 0x0c4,
0x0c8, 16, 1, 23, 0x1C4, 19),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0x0c0, 0x0c4,
0x0c8, 24, 1, 31, 0x1C4, 20, CLK_IS_CRITICAL),
/* CLK_CFG_13 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x1C4, 21, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0x0d0, 0x0d4,
0x0d8, 16, 1, 23, 0x1C4, 23),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0x0d0, 0x0d4,
0x0d8, 24, 1, 31, 0x1C4, 24),
/* CLK_CFG_14 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0x0e0, 0x0e4,
0x0e8, 0, 1, 7, 0x1C4, 25),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0x0e0, 0x0e4,
0x0e8, 8, 1, 15, 0x1C4, 26),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", da_xtp_glb_p0_parents,
0x0e0, 0x0e4, 0x0e8, 16, 1, 23, 0x1C4, 27),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", da_xtp_glb_p0_parents,
0x0e0, 0x0e4, 0x0e8, 24, 1, 31, 0x1C4, 28),
/* CLK_CFG_15 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", da_xtp_glb_p0_parents,
0x0f0, 0x0f4, 0x0f8, 0, 1, 7, 0x1C4, 29),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", da_xtp_glb_p0_parents,
0x0f0, 0x0f4, 0x0f8, 8, 1, 15, 0x1C4, 30),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0, 0x0f4, 0x0f8, 16, 1,
23, 0x1c8, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1,
31, 0x1C8, 1),
/* CLK_CFG_16 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x0100, 0x104, 0x108,
0, 1, 7, 0x1c8, 2),
MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents, 0x0100,
0x104, 0x108, 8, 1, 15, 0x1C8, 3),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel",
mcusys_backup_625m_parents, 0x0100, 0x104, 0x108, 16, 1, 23, 0x1C8, 4),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel",
pcie_mbist_250m_parents, 0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5),
/* CLK_CFG_17 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x0110, 0x114, 0x118,
0, 2, 7, 0x1c8, 6),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel",
netsys_tops_400m_parents, 0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel",
pcie_mbist_250m_parents, 0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents, 0x0110,
0x114, 0x118, 24, 2, 31, 0x1C8, 9),
/* CLK_CFG_18 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x0120, 0x124,
0x128, 0, 1, 7, 0x1c8, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents, 0x0120, 0x124, 0x128,
8, 2, 15, 0x1c8, 11),
};
static const struct mtk_composite top_aud_divs[] = {
DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420, 8, 8),
};
static const struct mtk_clk_desc topck_desc = {
.fixed_clks = top_fixed_clks,
.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
.factor_clks = top_divs,
.num_factor_clks = ARRAY_SIZE(top_divs),
.mux_clks = top_muxes,
.num_mux_clks = ARRAY_SIZE(top_muxes),
.composite_clks = top_aud_divs,
.num_composite_clks = ARRAY_SIZE(top_aud_divs),
.clk_lock = &mt7988_clk_lock,
};
static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b", "net1pll_d4" };
static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b", "net1pll_d4" };
static struct mtk_composite mcu_muxes[] = {
/* bus_pll_divider_cfg */
MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel", mcu_bus_div_parents, 0x7C0, 9, 2, -1,
CLK_IS_CRITICAL),
/* mp2_pll_divider_cfg */
MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel", mcu_arm_div_parents, 0x7A8, 9, 2, -1,
CLK_IS_CRITICAL),
};
static const struct mtk_clk_desc mcusys_desc = {
.composite_clks = mcu_muxes,
.num_composite_clks = ARRAY_SIZE(mcu_muxes),
};
static const struct of_device_id of_match_clk_mt7988_topckgen[] = {
{ .compatible = "mediatek,mt7988-topckgen", .data = &topck_desc },
{ .compatible = "mediatek,mt7988-mcusys", .data = &mcusys_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_topckgen);
static struct platform_driver clk_mt7988_topckgen_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt7988-topckgen",
.of_match_table = of_match_clk_mt7988_topckgen,
},
};
module_platform_driver(clk_mt7988_topckgen_drv);
MODULE_LICENSE("GPL");

82
drivers/clk/mediatek/clk-mt7988-xfipll.c Normal file
View File

@ -0,0 +1,82 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org>
*/
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
/* Register to control USXGMII XFI PLL analog */
#define XFI_PLL_ANA_GLB8 0x108
#define RG_XFI_PLL_ANA_SWWA 0x02283248
static const struct mtk_gate_regs xfipll_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0x8,
.sta_ofs = 0x8,
};
#define GATE_XFIPLL(_id, _name, _parent, _shift) \
{ \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &xfipll_cg_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
}
static const struct mtk_fixed_factor xfipll_divs[] = {
FACTOR(CLK_XFIPLL_PLL, "xfipll_pll", "top_xtal", 125, 32),
};
static const struct mtk_gate xfipll_clks[] = {
GATE_XFIPLL(CLK_XFIPLL_PLL_EN, "xfipll_pll_en", "xfipll_pll", 31),
};
static const struct mtk_clk_desc xfipll_desc = {
.clks = xfipll_clks,
.num_clks = ARRAY_SIZE(xfipll_clks),
.factor_clks = xfipll_divs,
.num_factor_clks = ARRAY_SIZE(xfipll_divs),
};
static int clk_mt7988_xfipll_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
void __iomem *base = of_iomap(node, 0);
if (!base)
return -ENOMEM;
/* Apply software workaround for USXGMII PLL TCL issue */
writel(RG_XFI_PLL_ANA_SWWA, base + XFI_PLL_ANA_GLB8);
iounmap(base);
return mtk_clk_simple_probe(pdev);
};
static const struct of_device_id of_match_clk_mt7988_xfipll[] = {
{ .compatible = "mediatek,mt7988-xfi-pll", .data = &xfipll_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_xfipll);
static struct platform_driver clk_mt7988_xfipll_drv = {
.driver = {
.name = "clk-mt7988-xfipll",
.of_match_table = of_match_clk_mt7988_xfipll,
},
.probe = clk_mt7988_xfipll_probe,
.remove_new = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt7988_xfipll_drv);
MODULE_DESCRIPTION("MediaTek MT7988 XFI PLL clock driver");
MODULE_LICENSE("GPL");

27
drivers/clk/mediatek/clk-mt8188-topckgen.c
View File

@ -475,29 +475,28 @@ static const char * const sspm_parents[] = {
"mainpll_d4_d2"
};
/*
* Both DP/eDP can be parented to TVDPLL1 and TVDPLL2, but we force using
* TVDPLL1 on eDP and TVDPLL2 on DP to avoid changing the "other" PLL rate
* in dual output case, which would lead to corruption of functionality loss.
*/
static const char * const dp_parents[] = {
"clk26m",
"tvdpll1_d2",
"tvdpll2_d2",
"tvdpll1_d4",
"tvdpll2_d4",
"tvdpll1_d8",
"tvdpll2_d8",
"tvdpll1_d16",
"tvdpll2_d16"
};
static const u8 dp_parents_idx[] = { 0, 2, 4, 6, 8 };
static const char * const edp_parents[] = {
"clk26m",
"tvdpll1_d2",
"tvdpll2_d2",
"tvdpll1_d4",
"tvdpll2_d4",
"tvdpll1_d8",
"tvdpll2_d8",
"tvdpll1_d16",
"tvdpll2_d16"
"tvdpll1_d16"
};
static const u8 edp_parents_idx[] = { 0, 1, 3, 5, 7 };
static const char * const dpi_parents[] = {
"clk26m",
@ -1038,10 +1037,12 @@ static const struct mtk_mux top_mtk_muxes[] = {
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPM, "top_sspm",
sspm_parents, 0x080, 0x084, 0x088, 24, 4, 31, 0x08, 3),
/* CLK_CFG_9 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_DP, "top_dp",
dp_parents, 0x08C, 0x090, 0x094, 0, 4, 7, 0x08, 4),
MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP, "top_edp",
edp_parents, 0x08C, 0x090, 0x094, 8, 4, 15, 0x08, 5),
MUX_GATE_CLR_SET_UPD_INDEXED(CLK_TOP_DP, "top_dp",
dp_parents, dp_parents_idx, 0x08C, 0x090, 0x094,
0, 4, 7, 0x08, 4),
MUX_GATE_CLR_SET_UPD_INDEXED(CLK_TOP_EDP, "top_edp",
edp_parents, edp_parents_idx, 0x08C, 0x090, 0x094,
8, 4, 15, 0x08, 5),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi",
dpi_parents, 0x08C, 0x090, 0x094, 16, 4, 23, 0x08, 6),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0",

27
drivers/clk/mediatek/clk-mt8195-topckgen.c
View File

@ -415,17 +415,28 @@ static const char * const pwrmcu_parents[] = {
"mainpll_d4_d2"
};
/*
* Both DP/eDP can be parented to TVDPLL1 and TVDPLL2, but we force using
* TVDPLL1 on eDP and TVDPLL2 on DP to avoid changing the "other" PLL rate
* in dual output case, which would lead to corruption of functionality loss.
*/
static const char * const dp_parents[] = {
"clk26m",
"tvdpll1_d2",
"tvdpll2_d2",
"tvdpll1_d4",
"tvdpll2_d4",
"tvdpll1_d8",
"tvdpll2_d8",
"tvdpll1_d16",
"tvdpll2_d16"
};
static const u8 dp_parents_idx[] = { 0, 2, 4, 6, 8 };
static const char * const edp_parents[] = {
"clk26m",
"tvdpll1_d2",
"tvdpll1_d4",
"tvdpll1_d8",
"tvdpll1_d16"
};
static const u8 edp_parents_idx[] = { 0, 1, 3, 5, 7 };
static const char * const disp_pwm_parents[] = {
"clk26m",
@ -957,11 +968,11 @@ static const struct mtk_mux top_mtk_muxes[] = {
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRMCU, "top_pwrmcu",
pwrmcu_parents, 0x08C, 0x090, 0x094, 16, 3, 23, 0x08, 6,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DP, "top_dp",
dp_parents, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7),
MUX_GATE_CLR_SET_UPD_INDEXED(CLK_TOP_DP, "top_dp",
dp_parents, dp_parents_idx, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7),
/* CLK_CFG_10 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP, "top_edp",
dp_parents, 0x098, 0x09C, 0x0A0, 0, 4, 7, 0x08, 8),
MUX_GATE_CLR_SET_UPD_INDEXED(CLK_TOP_EDP, "top_edp",
edp_parents, edp_parents_idx, 0x098, 0x09C, 0x0A0, 0, 4, 7, 0x08, 8),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi",
dp_parents, 0x098, 0x09C, 0x0A0, 8, 4, 15, 0x08, 9),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0",

14
drivers/clk/mediatek/clk-mux.c
View File

@ -89,6 +89,17 @@ static u8 mtk_clk_mux_get_parent(struct clk_hw *hw)
regmap_read(mux->regmap, mux->data->mux_ofs, &val);
val = (val >> mux->data->mux_shift) & mask;
if (mux->data->parent_index) {
int i;
for (i = 0; i < mux->data->num_parents; i++)
if (mux->data->parent_index[i] == val)
return i;
/* Not found: return an impossible index to generate error */
return mux->data->num_parents + 1;
}
return val;
}
@ -104,6 +115,9 @@ static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index)
else
__acquire(mux->lock);
if (mux->data->parent_index)
index = mux->data->parent_index[index];
regmap_read(mux->regmap, mux->data->mux_ofs, &orig);
val = (orig & ~(mask << mux->data->mux_shift))
| (index << mux->data->mux_shift);

43
drivers/clk/mediatek/clk-mux.h
View File

@ -21,6 +21,7 @@ struct mtk_mux {
int id;
const char *name;
const char * const *parent_names;
const u8 *parent_index;
unsigned int flags;
u32 mux_ofs;
@ -37,9 +38,10 @@ struct mtk_mux {
signed char num_parents;
};
#define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
_gate, _upd_ofs, _upd, _flags, _ops) { \
#define __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx, \
_num_parents, _mux_ofs, _mux_set_ofs, \
_mux_clr_ofs, _shift, _width, _gate, _upd_ofs, \
_upd, _flags, _ops) { \
.id = _id, \
.name = _name, \
.mux_ofs = _mux_ofs, \
@ -51,11 +53,28 @@ struct mtk_mux {
.gate_shift = _gate, \
.upd_shift = _upd, \
.parent_names = _parents, \
.num_parents = ARRAY_SIZE(_parents), \
.parent_index = _paridx, \
.num_parents = _num_parents, \
.flags = _flags, \
.ops = &_ops, \
}
#define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
_gate, _upd_ofs, _upd, _flags, _ops) \
__GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
NULL, ARRAY_SIZE(_parents), _mux_ofs, \
_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
_gate, _upd_ofs, _upd, _flags, _ops) \
#define GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, _paridx, \
_mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
_width, _gate, _upd_ofs, _upd, _flags, _ops) \
__GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
_paridx, ARRAY_SIZE(_paridx), _mux_ofs, \
_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
_gate, _upd_ofs, _upd, _flags, _ops) \
extern const struct clk_ops mtk_mux_clr_set_upd_ops;
extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
@ -67,6 +86,14 @@ extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
_gate, _upd_ofs, _upd, _flags, \
mtk_mux_gate_clr_set_upd_ops)
#define MUX_GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, \
_paridx, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
_shift, _width, _gate, _upd_ofs, _upd, _flags) \
GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, \
_paridx, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
_shift, _width, _gate, _upd_ofs, _upd, _flags, \
mtk_mux_gate_clr_set_upd_ops)
#define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
_gate, _upd_ofs, _upd) \
@ -75,6 +102,14 @@ extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
_width, _gate, _upd_ofs, _upd, \
CLK_SET_RATE_PARENT)
#define MUX_GATE_CLR_SET_UPD_INDEXED(_id, _name, _parents, _paridx, \
_mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
_width, _gate, _upd_ofs, _upd) \
MUX_GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, \
_parents, _paridx, _mux_ofs, _mux_set_ofs, \
_mux_clr_ofs, _shift, _width, _gate, _upd_ofs, \
_upd, CLK_SET_RATE_PARENT)
#define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
_upd_ofs, _upd) \

5
drivers/clk/mediatek/clk-pll.c
View File

@ -23,7 +23,7 @@
#define CON0_BASE_EN BIT(0)
#define CON0_PWR_ON BIT(0)
#define CON0_ISO_EN BIT(1)
#define PCW_CHG_MASK BIT(31)
#define PCW_CHG_BIT 31
#define AUDPLL_TUNER_EN BIT(31)
@ -114,7 +114,8 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
pll->data->pcw_shift);
val |= pcw << pll->data->pcw_shift;
writel(val, pll->pcw_addr);
chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
chg = readl(pll->pcw_chg_addr) |
BIT(pll->data->pcw_chg_bit ? : PCW_CHG_BIT);
writel(chg, pll->pcw_chg_addr);
if (pll->tuner_addr)
writel(val + 1, pll->tuner_addr);

1
drivers/clk/mediatek/clk-pll.h
View File

@ -48,6 +48,7 @@ struct mtk_pll_data {
const char *parent_name;
u32 en_reg;
u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
u8 pcw_chg_bit;
};
/*

115
drivers/clk/meson/g12a.c
View File

@ -3549,6 +3549,22 @@ static struct clk_regmap g12a_cts_encp_sel = {
},
};
static struct clk_regmap g12a_cts_encl_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_VIID_CLK_DIV,
.mask = 0xf,
.shift = 12,
.table = mux_table_cts_sel,
},
.hw.init = &(struct clk_init_data){
.name = "cts_encl_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = g12a_cts_parent_hws,
.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
},
};
static struct clk_regmap g12a_cts_vdac_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_VIID_CLK_DIV,
@ -3628,6 +3644,22 @@ static struct clk_regmap g12a_cts_encp = {
},
};
static struct clk_regmap g12a_cts_encl = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_VID_CLK_CNTL2,
.bit_idx = 3,
},
.hw.init = &(struct clk_init_data) {
.name = "cts_encl",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_cts_encl_sel.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
},
};
static struct clk_regmap g12a_cts_vdac = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_VID_CLK_CNTL2,
@ -3722,6 +3754,66 @@ static struct clk_regmap g12a_mipi_dsi_pxclk = {
},
};
/* MIPI ISP Clocks */
static const struct clk_parent_data g12b_mipi_isp_parent_data[] = {
{ .fw_name = "xtal", },
{ .hw = &g12a_gp0_pll.hw },
{ .hw = &g12a_hifi_pll.hw },
{ .hw = &g12a_fclk_div2p5.hw },
{ .hw = &g12a_fclk_div3.hw },
{ .hw = &g12a_fclk_div4.hw },
{ .hw = &g12a_fclk_div5.hw },
{ .hw = &g12a_fclk_div7.hw },
};
static struct clk_regmap g12b_mipi_isp_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_ISP_CLK_CNTL,
.mask = 7,
.shift = 9,
},
.hw.init = &(struct clk_init_data){
.name = "mipi_isp_sel",
.ops = &clk_regmap_mux_ops,
.parent_data = g12b_mipi_isp_parent_data,
.num_parents = ARRAY_SIZE(g12b_mipi_isp_parent_data),
},
};
static struct clk_regmap g12b_mipi_isp_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_ISP_CLK_CNTL,
.shift = 0,
.width = 7,
},
.hw.init = &(struct clk_init_data){
.name = "mipi_isp_div",
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12b_mipi_isp_sel.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap g12b_mipi_isp = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_ISP_CLK_CNTL,
.bit_idx = 8,
},
.hw.init = &(struct clk_init_data) {
.name = "mipi_isp",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12b_mipi_isp_div.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
/* HDMI Clocks */
static const struct clk_parent_data g12a_hdmi_parent_data[] = {
@ -4214,9 +4306,12 @@ static MESON_GATE(g12a_htx_hdcp22, HHI_GCLK_MPEG2, 3);
static MESON_GATE(g12a_htx_pclk, HHI_GCLK_MPEG2, 4);
static MESON_GATE(g12a_bt656, HHI_GCLK_MPEG2, 6);
static MESON_GATE(g12a_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
static MESON_GATE(g12b_mipi_isp_gate, HHI_GCLK_MPEG2, 17);
static MESON_GATE(g12a_mmc_pclk, HHI_GCLK_MPEG2, 11);
static MESON_GATE(g12a_uart2, HHI_GCLK_MPEG2, 15);
static MESON_GATE(g12a_vpu_intr, HHI_GCLK_MPEG2, 25);
static MESON_GATE(g12b_csi_phy1, HHI_GCLK_MPEG2, 28);
static MESON_GATE(g12b_csi_phy0, HHI_GCLK_MPEG2, 29);
static MESON_GATE(g12a_gic, HHI_GCLK_MPEG2, 30);
static MESON_GATE(g12a_vclk2_venci0, HHI_GCLK_OTHER, 1);
@ -4407,10 +4502,12 @@ static struct clk_hw *g12a_hw_clks[] = {
[CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
[CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
[CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
[CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw,
[CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
[CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
[CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
[CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
[CLKID_CTS_ENCL] = &g12a_cts_encl.hw,
[CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
[CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
[CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
@ -4632,10 +4729,12 @@ static struct clk_hw *g12b_hw_clks[] = {
[CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
[CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
[CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
[CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw,
[CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
[CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
[CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
[CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
[CLKID_CTS_ENCL] = &g12a_cts_encl.hw,
[CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
[CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
[CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
@ -4729,6 +4828,12 @@ static struct clk_hw *g12b_hw_clks[] = {
[CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
[CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
[CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
[CLKID_MIPI_ISP_SEL] = &g12b_mipi_isp_sel.hw,
[CLKID_MIPI_ISP_DIV] = &g12b_mipi_isp_div.hw,
[CLKID_MIPI_ISP] = &g12b_mipi_isp.hw,
[CLKID_MIPI_ISP_GATE] = &g12b_mipi_isp_gate.hw,
[CLKID_MIPI_ISP_CSI_PHY0] = &g12b_csi_phy0.hw,
[CLKID_MIPI_ISP_CSI_PHY1] = &g12b_csi_phy1.hw,
};
static struct clk_hw *sm1_hw_clks[] = {
@ -4892,10 +4997,12 @@ static struct clk_hw *sm1_hw_clks[] = {
[CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
[CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
[CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
[CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw,
[CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
[CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
[CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
[CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
[CLKID_CTS_ENCL] = &g12a_cts_encl.hw,
[CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
[CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
[CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
@ -5123,10 +5230,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
&g12a_vclk2_div12_en,
&g12a_cts_enci_sel,
&g12a_cts_encp_sel,
&g12a_cts_encl_sel,
&g12a_cts_vdac_sel,
&g12a_hdmi_tx_sel,
&g12a_cts_enci,
&g12a_cts_encp,
&g12a_cts_encl,
&g12a_cts_vdac,
&g12a_hdmi_tx,
&g12a_hdmi_sel,
@ -5221,6 +5330,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
&g12a_mipi_dsi_pxclk_sel,
&g12a_mipi_dsi_pxclk_div,
&g12a_mipi_dsi_pxclk,
&g12b_mipi_isp_sel,
&g12b_mipi_isp_div,
&g12b_mipi_isp,
&g12b_mipi_isp_gate,
&g12b_csi_phy1,
&g12b_csi_phy0,
};
static const struct reg_sequence g12a_init_regs[] = {

1
drivers/clk/meson/g12a.h
View File

@ -70,6 +70,7 @@
#define HHI_MALI_CLK_CNTL 0x1b0
#define HHI_VPU_CLKC_CNTL 0x1b4
#define HHI_VPU_CLK_CNTL 0x1bC
#define HHI_ISP_CLK_CNTL 0x1C0
#define HHI_NNA_CLK_CNTL 0x1C8
#define HHI_HDMI_CLK_CNTL 0x1CC
#define HHI_VDEC_CLK_CNTL 0x1E0

63
drivers/clk/qcom/Kconfig
View File

@ -20,6 +20,16 @@ menuconfig COMMON_CLK_QCOM
if COMMON_CLK_QCOM
config CLK_X1E80100_GCC
tristate "X1E80100 Global Clock Controller"
depends on ARM64 || COMPILE_TEST
select QCOM_GDSC
help
Support for the global clock controller on Qualcomm Technologies, Inc
X1E80100 devices.
Say Y if you want to use peripheral devices such as UART, SPI, I2C,
USB, UFS, SD/eMMC, PCIe, etc.
config QCOM_A53PLL
tristate "MSM8916 A53 PLL"
help
@ -427,6 +437,15 @@ config SC_CAMCC_7280
Say Y if you want to support camera devices and functionality such as
capturing pictures.
config SC_CAMCC_8280XP
tristate "SC8280XP Camera Clock Controller"
select SC_GCC_8280XP
help
Support for the camera clock controller on Qualcomm Technologies, Inc
SC8280XP devices.
Say Y if you want to support camera devices and functionality such as
capturing pictures.
config SC_DISPCC_7180
tristate "SC7180 Display Clock Controller"
depends on ARM64 || COMPILE_TEST
@ -668,6 +687,15 @@ config QDU_GCC_1000
QRU1000 devices. Say Y if you want to use peripheral
devices such as UART, SPI, I2C, USB, SD, PCIe, etc.
config QDU_ECPRICC_1000
tristate "QDU1000/QRU1000 ECPRI Clock Controller"
depends on ARM64 || COMPILE_TEST
select QDU_GCC_1000
help
Support for the ECPRI clock controller on QDU1000 and
QRU1000 devices. Say Y if you want to support the ECPRI
clock controller functionality such as Ethernet.
config SDM_GCC_845
tristate "SDM845/SDM670 Global Clock Controller"
depends on ARM64 || COMPILE_TEST
@ -842,6 +870,16 @@ config SM_DISPCC_8550
Say Y if you want to support display devices and functionality such as
splash screen.
config SM_DISPCC_8650
tristate "SM8650 Display Clock Controller"
depends on ARM64 || COMPILE_TEST
select SM_GCC_8650
help
Support for the display clock controller on Qualcomm Technologies, Inc
SM8650 devices.
Say Y if you want to support display devices and functionality such as
splash screen.
config SM_GCC_4450
tristate "SM4450 Global Clock Controller"
depends on ARM64 || COMPILE_TEST
@ -938,6 +976,15 @@ config SM_GCC_8550
Say Y if you want to use peripheral devices such as UART,
SPI, I2C, USB, SD/UFS, PCIe etc.
config SM_GCC_8650
tristate "SM8650 Global Clock Controller"
depends on ARM64 || COMPILE_TEST
select QCOM_GDSC
help
Support for the global clock controller on SM8650 devices.
Say Y if you want to use peripheral devices such as UART,
SPI, I2C, USB, SD/UFS, PCIe etc.
config SM_GPUCC_6115
tristate "SM6115 Graphics Clock Controller"
select SM_GCC_6115
@ -1019,6 +1066,14 @@ config SM_GPUCC_8550
Say Y if you want to support graphics controller devices and
functionality such as 3D graphics.
config SM_GPUCC_8650
tristate "SM8650 Graphics Clock Controller"
select SM_GCC_8650
help
Support for the graphics clock controller on SM8650 devices.
Say Y if you want to support graphics controller devices and
functionality such as 3D graphics.
config SM_TCSRCC_8550
tristate "SM8550 TCSR Clock Controller"
depends on ARM64 || COMPILE_TEST
@ -1027,6 +1082,14 @@ config SM_TCSRCC_8550
Support for the TCSR clock controller on SM8550 devices.
Say Y if you want to use peripheral devices such as SD/UFS.
config SM_TCSRCC_8650
tristate "SM8650 TCSR Clock Controller"
depends on ARM64 || COMPILE_TEST
select QCOM_GDSC
help
Support for the TCSR clock controller on SM8650 devices.
Say Y if you want to use peripheral devices such as SD/UFS.
config SM_VIDEOCC_8150
tristate "SM8150 Video Clock Controller"
depends on ARM64 || COMPILE_TEST

7
drivers/clk/qcom/Makefile
View File

@ -21,6 +21,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o
obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
@ -65,9 +66,11 @@ obj-$(CONFIG_QCM_DISPCC_2290) += dispcc-qcm2290.o
obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o
obj-$(CONFIG_QCS_Q6SSTOP_404) += q6sstop-qcs404.o
obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o
obj-$(CONFIG_QDU_ECPRICC_1000) += ecpricc-qdu1000.o
obj-$(CONFIG_QDU_GCC_1000) += gcc-qdu1000.o
obj-$(CONFIG_SC_CAMCC_7180) += camcc-sc7180.o
obj-$(CONFIG_SC_CAMCC_7280) += camcc-sc7280.o
obj-$(CONFIG_SC_CAMCC_8280XP) += camcc-sc8280xp.o
obj-$(CONFIG_SC_DISPCC_7180) += dispcc-sc7180.o
obj-$(CONFIG_SC_DISPCC_7280) += dispcc-sc7280.o
obj-$(CONFIG_SC_DISPCC_8280XP) += dispcc-sc8280xp.o
@ -110,6 +113,7 @@ obj-$(CONFIG_SM_DISPCC_6375) += dispcc-sm6375.o
obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
obj-$(CONFIG_SM_DISPCC_8450) += dispcc-sm8450.o
obj-$(CONFIG_SM_DISPCC_8550) += dispcc-sm8550.o
obj-$(CONFIG_SM_DISPCC_8650) += dispcc-sm8650.o
obj-$(CONFIG_SM_GCC_4450) += gcc-sm4450.o
obj-$(CONFIG_SM_GCC_6115) += gcc-sm6115.o
obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o
@ -121,6 +125,7 @@ obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o
obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o
obj-$(CONFIG_SM_GCC_8550) += gcc-sm8550.o
obj-$(CONFIG_SM_GCC_8650) += gcc-sm8650.o
obj-$(CONFIG_SM_GPUCC_6115) += gpucc-sm6115.o
obj-$(CONFIG_SM_GPUCC_6125) += gpucc-sm6125.o
obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o
@ -130,7 +135,9 @@ obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o
obj-$(CONFIG_SM_GPUCC_8450) += gpucc-sm8450.o
obj-$(CONFIG_SM_GPUCC_8550) += gpucc-sm8550.o
obj-$(CONFIG_SM_GPUCC_8650) += gpucc-sm8650.o
obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o
obj-$(CONFIG_SM_TCSRCC_8650) += tcsrcc-sm8650.o
obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o
obj-$(CONFIG_SM_VIDEOCC_8350) += videocc-sm8350.o

21
drivers/clk/qcom/apss-ipq-pll.c
View File

@ -73,6 +73,20 @@ static struct clk_alpha_pll ipq_pll_stromer_plus = {
},
};
static const struct alpha_pll_config ipq5018_pll_config = {
.l = 0x32,
.config_ctl_val = 0x4001075b,
.config_ctl_hi_val = 0x304,
.main_output_mask = BIT(0),
.aux_output_mask = BIT(1),
.early_output_mask = BIT(3),
.alpha_en_mask = BIT(24),
.status_val = 0x3,
.status_mask = GENMASK(10, 8),
.lock_det = BIT(2),
.test_ctl_hi_val = 0x00400003,
};
static const struct alpha_pll_config ipq5332_pll_config = {
.l = 0x2d,
.config_ctl_val = 0x4001075b,
@ -129,6 +143,12 @@ struct apss_pll_data {
const struct alpha_pll_config *pll_config;
};
static const struct apss_pll_data ipq5018_pll_data = {
.pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
.pll = &ipq_pll_stromer_plus,
.pll_config = &ipq5018_pll_config,
};
static struct apss_pll_data ipq5332_pll_data = {
.pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
.pll = &ipq_pll_stromer_plus,
@ -195,6 +215,7 @@ static int apss_ipq_pll_probe(struct platform_device *pdev)
}
static const struct of_device_id apss_ipq_pll_match_table[] = {
{ .compatible = "qcom,ipq5018-a53pll", .data = &ipq5018_pll_data },
{ .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data },
{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },
{ .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },

3045
drivers/clk/qcom/camcc-sc8280xp.c Normal file
View File

File diff suppressed because it is too large Load Diff

38
drivers/clk/qcom/clk-branch.c
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/kernel.h>
@ -134,6 +135,43 @@ static void clk_branch2_disable(struct clk_hw *hw)
clk_branch_toggle(hw, false, clk_branch2_check_halt);
}
static int clk_branch2_mem_enable(struct clk_hw *hw)
{
struct clk_mem_branch *mem_br = to_clk_mem_branch(hw);
struct clk_branch branch = mem_br->branch;
u32 val;
int ret;
regmap_update_bits(branch.clkr.regmap, mem_br->mem_enable_reg,
mem_br->mem_enable_ack_mask, mem_br->mem_enable_ack_mask);
ret = regmap_read_poll_timeout(branch.clkr.regmap, mem_br->mem_ack_reg,
val, val & mem_br->mem_enable_ack_mask, 0, 200);
if (ret) {
WARN(1, "%s mem enable failed\n", clk_hw_get_name(&branch.clkr.hw));
return ret;
}
return clk_branch2_enable(hw);
}
static void clk_branch2_mem_disable(struct clk_hw *hw)
{
struct clk_mem_branch *mem_br = to_clk_mem_branch(hw);
regmap_update_bits(mem_br->branch.clkr.regmap, mem_br->mem_enable_reg,
mem_br->mem_enable_ack_mask, 0);
return clk_branch2_disable(hw);
}
const struct clk_ops clk_branch2_mem_ops = {
.enable = clk_branch2_mem_enable,
.disable = clk_branch2_mem_disable,
.is_enabled = clk_is_enabled_regmap,
};
EXPORT_SYMBOL_GPL(clk_branch2_mem_ops);
const struct clk_ops clk_branch2_ops = {
.enable = clk_branch2_enable,
.disable = clk_branch2_disable,

21
drivers/clk/qcom/clk-branch.h
View File

@ -38,6 +38,23 @@ struct clk_branch {
struct clk_regmap clkr;
};
/**
* struct clk_mem_branch - gating clock which are associated with memories
*
* @mem_enable_reg: branch clock memory gating register
* @mem_ack_reg: branch clock memory ack register
* @mem_enable_ack_mask: branch clock memory enable and ack field in @mem_ack_reg
* @branch: branch clock gating handle
*
* Clock which can gate its memories.
*/
struct clk_mem_branch {
u32 mem_enable_reg;
u32 mem_ack_reg;
u32 mem_enable_ack_mask;
struct clk_branch branch;
};
/* Branch clock common bits for HLOS-owned clocks */
#define CBCR_CLK_OFF BIT(31)
#define CBCR_NOC_FSM_STATUS GENMASK(30, 28)
@ -85,8 +102,12 @@ extern const struct clk_ops clk_branch_ops;
extern const struct clk_ops clk_branch2_ops;
extern const struct clk_ops clk_branch_simple_ops;
extern const struct clk_ops clk_branch2_aon_ops;
extern const struct clk_ops clk_branch2_mem_ops;
#define to_clk_branch(_hw) \
container_of(to_clk_regmap(_hw), struct clk_branch, clkr)
#define to_clk_mem_branch(_hw) \
container_of(to_clk_branch(_hw), struct clk_mem_branch, branch)
#endif

58
drivers/clk/qcom/clk-rpmh.c
View File

@ -372,6 +372,9 @@ DEFINE_CLK_RPMH_VRM(clk3, _a1, "clka3", 1);
DEFINE_CLK_RPMH_VRM(clk4, _a1, "clka4", 1);
DEFINE_CLK_RPMH_VRM(clk5, _a1, "clka5", 1);
DEFINE_CLK_RPMH_VRM(clk3, _a2, "clka3", 2);
DEFINE_CLK_RPMH_VRM(clk4, _a2, "clka4", 2);
DEFINE_CLK_RPMH_VRM(clk5, _a2, "clka5", 2);
DEFINE_CLK_RPMH_VRM(clk6, _a2, "clka6", 2);
DEFINE_CLK_RPMH_VRM(clk7, _a2, "clka7", 2);
DEFINE_CLK_RPMH_VRM(clk8, _a2, "clka8", 2);
@ -630,6 +633,37 @@ static const struct clk_rpmh_desc clk_rpmh_sm8550 = {
.num_clks = ARRAY_SIZE(sm8550_rpmh_clocks),
};
static struct clk_hw *sm8650_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw,
[RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a2.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a2_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_clk1_a1.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_clk1_a1_ao.hw,
[RPMH_RF_CLK2] = &clk_rpmh_clk2_a1.hw,
[RPMH_RF_CLK2_A] = &clk_rpmh_clk2_a1_ao.hw,
/*
* The clka3 RPMh resource is missing in cmd-db
* for current platforms, while the clka3 exists
* on the PMK8550, the clock is unconnected and
* unused.
*/
[RPMH_RF_CLK4] = &clk_rpmh_clk4_a2.hw,
[RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a2_ao.hw,
[RPMH_RF_CLK5] = &clk_rpmh_clk5_a2.hw,
[RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a2_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sm8650 = {
.clks = sm8650_rpmh_clocks,
.num_clks = ARRAY_SIZE(sm8650_rpmh_clocks),
};
static struct clk_hw *sc7280_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
@ -737,6 +771,28 @@ static const struct clk_rpmh_desc clk_rpmh_sm4450 = {
.num_clks = ARRAY_SIZE(sm4450_rpmh_clocks),
};
static struct clk_hw *x1e80100_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw,
[RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a2.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a2_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_clk3_a2.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a2_ao.hw,
[RPMH_RF_CLK4] = &clk_rpmh_clk4_a2.hw,
[RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a2_ao.hw,
[RPMH_RF_CLK5] = &clk_rpmh_clk5_a2.hw,
[RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a2_ao.hw,
};
static const struct clk_rpmh_desc clk_rpmh_x1e80100 = {
.clks = x1e80100_rpmh_clocks,
.num_clks = ARRAY_SIZE(x1e80100_rpmh_clocks),
};
static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
void *data)
{
@ -837,7 +893,9 @@ static const struct of_device_id clk_rpmh_match_table[] = {
{ .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350},
{ .compatible = "qcom,sm8450-rpmh-clk", .data = &clk_rpmh_sm8450},
{ .compatible = "qcom,sm8550-rpmh-clk", .data = &clk_rpmh_sm8550},
{ .compatible = "qcom,sm8650-rpmh-clk", .data = &clk_rpmh_sm8650},
{ .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280},
{ .compatible = "qcom,x1e80100-rpmh-clk", .data = &clk_rpmh_x1e80100},
{ }
};
MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);

12
drivers/clk/qcom/dispcc-sm8550.c
View File

@ -81,6 +81,10 @@ static const struct alpha_pll_config disp_cc_pll0_config = {
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000005,
};
@ -108,6 +112,10 @@ static const struct alpha_pll_config disp_cc_pll1_config = {
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000005,
};
@ -1766,8 +1774,8 @@ static int disp_cc_sm8550_probe(struct platform_device *pdev)
goto err_put_rpm;
}
clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
/* Enable clock gating for MDP clocks */
regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);

1818
drivers/clk/qcom/dispcc-sm8650.c Normal file
View File

File diff suppressed because it is too large Load Diff

2456
drivers/clk/qcom/ecpricc-qdu1000.c Normal file
View File

File diff suppressed because it is too large Load Diff

110
drivers/clk/qcom/gcc-msm8939.c
View File

@ -696,7 +696,7 @@ static struct clk_rcg2 apss_ahb_clk_src = {
},
};
static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
static const struct freq_tbl ftbl_gcc_camss_csi0_1_2_clk[] = {
F(100000000, P_GPLL0, 8, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
@ -706,7 +706,7 @@ static struct clk_rcg2 csi0_clk_src = {
.cmd_rcgr = 0x4e020,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_camss_csi0_1_clk,
.freq_tbl = ftbl_gcc_camss_csi0_1_2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
@ -719,7 +719,7 @@ static struct clk_rcg2 csi1_clk_src = {
.cmd_rcgr = 0x4f020,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_camss_csi0_1_clk,
.freq_tbl = ftbl_gcc_camss_csi0_1_2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
@ -728,6 +728,19 @@ static struct clk_rcg2 csi1_clk_src = {
},
};
static struct clk_rcg2 csi2_clk_src = {
.cmd_rcgr = 0x3c020,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_camss_csi0_1_2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi2_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
@ -2385,6 +2398,91 @@ static struct clk_branch gcc_camss_csi1rdi_clk = {
},
};
static struct clk_branch gcc_camss_csi2_ahb_clk = {
.halt_reg = 0x3c040,
.clkr = {
.enable_reg = 0x3c040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi2_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi2_clk = {
.halt_reg = 0x3c03c,
.clkr = {
.enable_reg = 0x3c03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi2_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi2phy_clk = {
.halt_reg = 0x3c048,
.clkr = {
.enable_reg = 0x3c048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi2phy_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi2pix_clk = {
.halt_reg = 0x3c058,
.clkr = {
.enable_reg = 0x3c058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi2pix_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi2rdi_clk = {
.halt_reg = 0x3c050,
.clkr = {
.enable_reg = 0x3c050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi2rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi_vfe0_clk = {
.halt_reg = 0x58050,
.clkr = {
@ -3682,6 +3780,7 @@ static struct clk_regmap *gcc_msm8939_clocks[] = {
[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
[CSI2_CLK_SRC] = &csi2_clk_src.clkr,
[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
@ -3751,6 +3850,11 @@ static struct clk_regmap *gcc_msm8939_clocks[] = {
[GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
[GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
[GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
[GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr,
[GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr,
[GCC_CAMSS_CSI2PHY_CLK] = &gcc_camss_csi2phy_clk.clkr,
[GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr,
[GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr,
[GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
[GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
[GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,

110
drivers/clk/qcom/gcc-sm8550.c
View File

@ -401,7 +401,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = {
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -416,7 +416,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = {
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -431,7 +431,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = {
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -451,7 +451,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -471,7 +471,7 @@ static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -486,7 +486,7 @@ static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -501,7 +501,7 @@ static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -521,7 +521,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -536,7 +536,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -551,7 +551,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -566,7 +566,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -581,7 +581,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -596,7 +596,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -611,7 +611,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -626,7 +626,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -641,7 +641,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -656,7 +656,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -671,7 +671,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -700,7 +700,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
@ -717,7 +717,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
@ -750,7 +750,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
@ -767,7 +767,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
@ -784,7 +784,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
@ -801,7 +801,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
@ -818,7 +818,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
@ -835,7 +835,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
@ -852,7 +852,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
@ -869,7 +869,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
@ -886,7 +886,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
@ -903,7 +903,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
@ -920,7 +920,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
@ -937,7 +937,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
@ -975,7 +975,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
@ -992,7 +992,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
@ -1025,7 +1025,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.parent_data = gcc_parent_data_9,
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -1048,7 +1048,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -1071,7 +1071,7 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -1093,7 +1093,7 @@ static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -1114,7 +1114,7 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -1136,7 +1136,7 @@ static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -1159,7 +1159,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -1174,7 +1174,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -1189,7 +1189,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -2998,38 +2998,46 @@ static struct clk_branch gcc_video_axi1_clk = {
static struct gdsc pcie_0_gdsc = {
.gdscr = 0x6b004,
.collapse_ctrl = 0x52020,
.collapse_mask = BIT(0),
.pd = {
.name = "pcie_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc pcie_0_phy_gdsc = {
.gdscr = 0x6c000,
.collapse_ctrl = 0x52020,
.collapse_mask = BIT(3),
.pd = {
.name = "pcie_0_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc pcie_1_gdsc = {
.gdscr = 0x8d004,
.collapse_ctrl = 0x52020,
.collapse_mask = BIT(1),
.pd = {
.name = "pcie_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc pcie_1_phy_gdsc = {
.gdscr = 0x8e000,
.collapse_ctrl = 0x52020,
.collapse_mask = BIT(4),
.pd = {
.name = "pcie_1_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc ufs_phy_gdsc = {
@ -3038,7 +3046,7 @@ static struct gdsc ufs_phy_gdsc = {
.name = "ufs_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc ufs_mem_phy_gdsc = {
@ -3047,7 +3055,7 @@ static struct gdsc ufs_mem_phy_gdsc = {
.name = "ufs_mem_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc usb30_prim_gdsc = {
@ -3056,7 +3064,7 @@ static struct gdsc usb30_prim_gdsc = {
.name = "usb30_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc usb3_phy_gdsc = {
@ -3065,7 +3073,7 @@ static struct gdsc usb3_phy_gdsc = {
.name = "usb3_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct clk_regmap *gcc_sm8550_clocks[] = {

3849
drivers/clk/qcom/gcc-sm8650.c Normal file
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File diff suppressed because it is too large Load Diff

6807
drivers/clk/qcom/gcc-x1e80100.c Normal file
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File diff suppressed because it is too large Load Diff

4
drivers/clk/qcom/gpucc-sm8150.c
View File

@ -37,8 +37,8 @@ static struct alpha_pll_config gpu_cc_pll1_config = {
.config_ctl_hi_val = 0x00002267,
.config_ctl_hi1_val = 0x00000024,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000002,
.test_ctl_hi1_val = 0x00000000,
.test_ctl_hi_val = 0x00000000,
.test_ctl_hi1_val = 0x00000020,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x000000d0,

6
drivers/clk/qcom/gpucc-sm8550.c
View File

@ -35,12 +35,12 @@ enum {
};
static const struct pll_vco lucid_ole_vco[] = {
{ 249600000, 2300000000, 0 },
{ 249600000, 2000000000, 0 },
};
static const struct alpha_pll_config gpu_cc_pll0_config = {
.l = 0x0d,
.alpha = 0x0,
.l = 0x1e,
.alpha = 0xbaaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,

663
drivers/clk/qcom/gpucc-sm8650.c Normal file
View File

@ -0,0 +1,663 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved
* Copyright (c) 2023, Linaro Limited
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm8650-gpucc.h>
#include <dt-bindings/reset/qcom,sm8650-gpucc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_GPLL0_OUT_MAIN,
DT_GPLL0_OUT_MAIN_DIV,
};
enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
P_GPU_CC_PLL0_OUT_MAIN,
P_GPU_CC_PLL1_OUT_MAIN,
};
static struct pll_vco lucid_ole_vco[] = {
{ 249600000, 2100000000, 0 },
};
static const struct alpha_pll_config gpu_cc_pll0_config = {
.l = 0x20,
.alpha = 0x4aaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll gpu_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll0",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct alpha_pll_config gpu_cc_pll1_config = {
.l = 0x1b,
.alpha = 0x1555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll gpu_cc_pll1 = {
.offset = 0x1000,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll1",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_GPLL0_OUT_MAIN },
{ .index = DT_GPLL0_OUT_MAIN_DIV },
};
static const struct parent_map gpu_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GPLL0_OUT_MAIN },
{ .index = DT_GPLL0_OUT_MAIN_DIV },
};
static const struct parent_map gpu_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GPLL0_OUT_MAIN },
{ .index = DT_GPLL0_OUT_MAIN_DIV },
};
static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_ff_clk_src = {
.cmd_rcgr = 0x9474,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_ff_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_ff_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(260000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
F(625000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.cmd_rcgr = 0x9318,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_1,
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_hub_clk_src = {
.cmd_rcgr = 0x93ec,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_2,
.freq_tbl = ftbl_gpu_cc_hub_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_hub_clk_src",
.parent_data = gpu_cc_parent_data_2,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_div gpu_cc_hub_div_clk_src = {
.reg = 0x942c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gpu_cc_ahb_clk = {
.halt_reg = 0x911c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x911c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x9120,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9120,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_crc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_accu_shift_clk = {
.halt_reg = 0x9160,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9160,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cx_accu_shift_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_ff_clk = {
.halt_reg = 0x914c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x914c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_ff_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_ff_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
.halt_reg = 0x913c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x913c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_aon_clk = {
.halt_reg = 0x9004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_aon_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_clk = {
.halt_reg = 0x9144,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9144,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_demet_clk = {
.halt_reg = 0x900c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x900c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_demet_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_freq_measure_clk = {
.halt_reg = 0x9008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_freq_measure_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_gfx3d_clk = {
.halt_reg = 0x90a8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x90a8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_gfx3d_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_gfx3d_rdvm_clk = {
.halt_reg = 0x90c8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x90c8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_gfx3d_rdvm_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_gmu_clk = {
.halt_reg = 0x90bc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x90bc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_gmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_vsense_clk = {
.halt_reg = 0x90b0,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x90b0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_vsense_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_accu_shift_clk = {
.halt_reg = 0x90d0,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x90d0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_gx_accu_shift_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_ff_clk = {
.halt_reg = 0x90c0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x90c0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_gx_ff_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_ff_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
.halt_reg = 0x7000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hub_aon_clk = {
.halt_reg = 0x93e8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x93e8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_hub_aon_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_hub_cx_int_clk = {
.halt_reg = 0x9148,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9148,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_hub_cx_int_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_memnoc_gfx_clk = {
.halt_reg = 0x9150,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9150,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_memnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_sleep_clk = {
.halt_reg = 0x9134,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9134,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_dpm_clk = {
.halt_reg = 0x9164,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9164,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_dpm_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gpu_cx_gdsc = {
.gdscr = 0x9108,
.gds_hw_ctrl = 0x9168,
.clk_dis_wait_val = 8,
.pd = {
.name = "gpu_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE | RETAIN_FF_ENABLE,
};
static struct gdsc gpu_gx_gdsc = {
.gdscr = 0x905c,
.clamp_io_ctrl = 0x9504,
.resets = (unsigned int []){ GPUCC_GPU_CC_GX_BCR,
GPUCC_GPU_CC_ACD_BCR,
GPUCC_GPU_CC_GX_ACD_IROOT_BCR },
.reset_count = 3,
.pd = {
.name = "gpu_gx_gdsc",
.power_on = gdsc_gx_do_nothing_enable,
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
};
static struct clk_regmap *gpu_cc_sm8650_clocks[] = {
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr,
[GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
[GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr,
[GPU_CC_DPM_CLK] = &gpu_cc_dpm_clk.clkr,
[GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
[GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_GX_ACCU_SHIFT_CLK] = &gpu_cc_gx_accu_shift_clk.clkr,
[GPU_CC_GX_FF_CLK] = &gpu_cc_gx_ff_clk.clkr,
[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
[GPU_CC_GX_GFX3D_RDVM_CLK] = &gpu_cc_gx_gfx3d_rdvm_clk.clkr,
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
[GPU_CC_HUB_DIV_CLK_SRC] = &gpu_cc_hub_div_clk_src.clkr,
[GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
};
static const struct qcom_reset_map gpu_cc_sm8650_resets[] = {
[GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
[GPUCC_GPU_CC_GX_BCR] = { 0x9058 },
[GPUCC_GPU_CC_CX_BCR] = { 0x9104 },
[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
[GPUCC_GPU_CC_ACD_BCR] = { 0x9358 },
[GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
[GPUCC_GPU_CC_FF_BCR] = { 0x9470 },
[GPUCC_GPU_CC_GMU_BCR] = { 0x9314 },
[GPUCC_GPU_CC_GX_ACD_IROOT_BCR] = { 0x958c },
};
static struct gdsc *gpu_cc_sm8650_gdscs[] = {
[GPU_CX_GDSC] = &gpu_cx_gdsc,
[GPU_GX_GDSC] = &gpu_gx_gdsc,
};
static const struct regmap_config gpu_cc_sm8650_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xa000,
.fast_io = true,
};
static const struct qcom_cc_desc gpu_cc_sm8650_desc = {
.config = &gpu_cc_sm8650_regmap_config,
.clks = gpu_cc_sm8650_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_sm8650_clocks),
.resets = gpu_cc_sm8650_resets,
.num_resets = ARRAY_SIZE(gpu_cc_sm8650_resets),
.gdscs = gpu_cc_sm8650_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_sm8650_gdscs),
};
static const struct of_device_id gpu_cc_sm8650_match_table[] = {
{ .compatible = "qcom,sm8650-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_sm8650_match_table);
static int gpu_cc_sm8650_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gpu_cc_sm8650_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
return qcom_cc_really_probe(pdev, &gpu_cc_sm8650_desc, regmap);
}
static struct platform_driver gpu_cc_sm8650_driver = {
.probe = gpu_cc_sm8650_probe,
.driver = {
.name = "sm8650-gpucc",
.of_match_table = gpu_cc_sm8650_match_table,
},
};
module_platform_driver(gpu_cc_sm8650_driver);
MODULE_DESCRIPTION("QTI GPU_CC SM8650 Driver");
MODULE_LICENSE("GPL");

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drivers/clk/qcom/tcsrcc-sm8650.c Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm8650-tcsr.h>
#include "clk-branch.h"
#include "clk-regmap.h"
#include "common.h"
#include "reset.h"
enum {
DT_BI_TCXO_PAD,
};
static struct clk_branch tcsr_pcie_0_clkref_en = {
.halt_reg = 0x31100,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x31100,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "tcsr_pcie_0_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_pcie_1_clkref_en = {
.halt_reg = 0x31114,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x31114,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "tcsr_pcie_1_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_ufs_clkref_en = {
.halt_reg = 0x31110,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x31110,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "tcsr_ufs_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_ufs_pad_clkref_en = {
.halt_reg = 0x31104,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x31104,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "tcsr_ufs_pad_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb2_clkref_en = {
.halt_reg = 0x31118,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x31118,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "tcsr_usb2_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb3_clkref_en = {
.halt_reg = 0x31108,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x31108,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "tcsr_usb3_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap *tcsr_cc_sm8650_clocks[] = {
[TCSR_PCIE_0_CLKREF_EN] = &tcsr_pcie_0_clkref_en.clkr,
[TCSR_PCIE_1_CLKREF_EN] = &tcsr_pcie_1_clkref_en.clkr,
[TCSR_UFS_CLKREF_EN] = &tcsr_ufs_clkref_en.clkr,
[TCSR_UFS_PAD_CLKREF_EN] = &tcsr_ufs_pad_clkref_en.clkr,
[TCSR_USB2_CLKREF_EN] = &tcsr_usb2_clkref_en.clkr,
[TCSR_USB3_CLKREF_EN] = &tcsr_usb3_clkref_en.clkr,
};
static const struct regmap_config tcsr_cc_sm8650_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x3b000,
.fast_io = true,
};
static const struct qcom_cc_desc tcsr_cc_sm8650_desc = {
.config = &tcsr_cc_sm8650_regmap_config,
.clks = tcsr_cc_sm8650_clocks,
.num_clks = ARRAY_SIZE(tcsr_cc_sm8650_clocks),
};
static const struct of_device_id tcsr_cc_sm8650_match_table[] = {
{ .compatible = "qcom,sm8650-tcsr" },
{ }
};
MODULE_DEVICE_TABLE(of, tcsr_cc_sm8650_match_table);
static int tcsr_cc_sm8650_probe(struct platform_device *pdev)
{
return qcom_cc_probe(pdev, &tcsr_cc_sm8650_desc);
}
static struct platform_driver tcsr_cc_sm8650_driver = {
.probe = tcsr_cc_sm8650_probe,
.driver = {
.name = "tcsr_cc-sm8650",
.of_match_table = tcsr_cc_sm8650_match_table,
},
};
static int __init tcsr_cc_sm8650_init(void)
{
return platform_driver_register(&tcsr_cc_sm8650_driver);
}
subsys_initcall(tcsr_cc_sm8650_init);
static void __exit tcsr_cc_sm8650_exit(void)
{
platform_driver_unregister(&tcsr_cc_sm8650_driver);
}
module_exit(tcsr_cc_sm8650_exit);
MODULE_DESCRIPTION("QTI TCSRCC SM8650 Driver");
MODULE_LICENSE("GPL");

25
drivers/clk/qcom/videocc-sm8150.c
View File

@ -6,6 +6,7 @@
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,videocc-sm8150.h>
@ -33,6 +34,7 @@ static struct alpha_pll_config video_pll0_config = {
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002267,
.config_ctl_hi1_val = 0x00000024,
.test_ctl_hi1_val = 0x00000020,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x000000D0,
@ -214,6 +216,10 @@ static const struct regmap_config video_cc_sm8150_regmap_config = {
static const struct qcom_reset_map video_cc_sm8150_resets[] = {
[VIDEO_CC_MVSC_CORE_CLK_BCR] = { 0x850, 2 },
[VIDEO_CC_INTERFACE_BCR] = { 0x8f0 },
[VIDEO_CC_MVS0_BCR] = { 0x870 },
[VIDEO_CC_MVS1_BCR] = { 0x8b0 },
[VIDEO_CC_MVSC_BCR] = { 0x810 },
};
static const struct qcom_cc_desc video_cc_sm8150_desc = {
@ -235,17 +241,32 @@ MODULE_DEVICE_TABLE(of, video_cc_sm8150_match_table);
static int video_cc_sm8150_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return ret;
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret)
return ret;
regmap = qcom_cc_map(pdev, &video_cc_sm8150_desc);
if (IS_ERR(regmap))
if (IS_ERR(regmap)) {
pm_runtime_put_sync(&pdev->dev);
return PTR_ERR(regmap);
}
clk_trion_pll_configure(&video_pll0, regmap, &video_pll0_config);
/* Keep VIDEO_CC_XO_CLK ALWAYS-ON */
regmap_update_bits(regmap, 0x984, 0x1, 0x1);
return qcom_cc_really_probe(pdev, &video_cc_sm8150_desc, regmap);
ret = qcom_cc_really_probe(pdev, &video_cc_sm8150_desc, regmap);
pm_runtime_put_sync(&pdev->dev);
return ret;
}
static struct platform_driver video_cc_sm8150_driver = {

8
include/dt-bindings/clock/g12a-clkc.h
View File

@ -279,5 +279,13 @@
#define CLKID_MIPI_DSI_PXCLK_DIV 268
#define CLKID_MIPI_DSI_PXCLK_SEL 269
#define CLKID_MIPI_DSI_PXCLK 270
#define CLKID_CTS_ENCL 271
#define CLKID_CTS_ENCL_SEL 272
#define CLKID_MIPI_ISP_DIV 273
#define CLKID_MIPI_ISP_SEL 274
#define CLKID_MIPI_ISP 275
#define CLKID_MIPI_ISP_GATE 276
#define CLKID_MIPI_ISP_CSI_PHY0 277
#define CLKID_MIPI_ISP_CSI_PHY1 278
#endif /* __G12A_CLKC_H */

280
include/dt-bindings/clock/mediatek,mt7988-clk.h Normal file
View File

@ -0,0 +1,280 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
* Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
*/
#ifndef _DT_BINDINGS_CLK_MT7988_H
#define _DT_BINDINGS_CLK_MT7988_H
/* APMIXEDSYS */
#define CLK_APMIXED_NETSYSPLL 0
#define CLK_APMIXED_MPLL 1
#define CLK_APMIXED_MMPLL 2
#define CLK_APMIXED_APLL2 3
#define CLK_APMIXED_NET1PLL 4
#define CLK_APMIXED_NET2PLL 5
#define CLK_APMIXED_WEDMCUPLL 6
#define CLK_APMIXED_SGMPLL 7
#define CLK_APMIXED_ARM_B 8
#define CLK_APMIXED_CCIPLL2_B 9
#define CLK_APMIXED_USXGMIIPLL 10
#define CLK_APMIXED_MSDCPLL 11
/* TOPCKGEN */
#define CLK_TOP_XTAL 0
#define CLK_TOP_XTAL_D2 1
#define CLK_TOP_RTC_32K 2
#define CLK_TOP_RTC_32P7K 3
#define CLK_TOP_MPLL_D2 4
#define CLK_TOP_MPLL_D3_D2 5
#define CLK_TOP_MPLL_D4 6
#define CLK_TOP_MPLL_D8 7
#define CLK_TOP_MPLL_D8_D2 8
#define CLK_TOP_MMPLL_D2 9
#define CLK_TOP_MMPLL_D3_D5 10
#define CLK_TOP_MMPLL_D4 11
#define CLK_TOP_MMPLL_D6_D2 12
#define CLK_TOP_MMPLL_D8 13
#define CLK_TOP_APLL2_D4 14
#define CLK_TOP_NET1PLL_D4 15
#define CLK_TOP_NET1PLL_D5 16
#define CLK_TOP_NET1PLL_D5_D2 17
#define CLK_TOP_NET1PLL_D5_D4 18
#define CLK_TOP_NET1PLL_D8 19
#define CLK_TOP_NET1PLL_D8_D2 20
#define CLK_TOP_NET1PLL_D8_D4 21
#define CLK_TOP_NET1PLL_D8_D8 22
#define CLK_TOP_NET1PLL_D8_D16 23
#define CLK_TOP_NET2PLL_D2 24
#define CLK_TOP_NET2PLL_D4 25
#define CLK_TOP_NET2PLL_D4_D4 26
#define CLK_TOP_NET2PLL_D4_D8 27
#define CLK_TOP_NET2PLL_D6 28
#define CLK_TOP_NET2PLL_D8 29
#define CLK_TOP_NETSYS_SEL 30
#define CLK_TOP_NETSYS_500M_SEL 31
#define CLK_TOP_NETSYS_2X_SEL 32
#define CLK_TOP_NETSYS_GSW_SEL 33
#define CLK_TOP_ETH_GMII_SEL 34
#define CLK_TOP_NETSYS_MCU_SEL 35
#define CLK_TOP_NETSYS_PAO_2X_SEL 36
#define CLK_TOP_EIP197_SEL 37
#define CLK_TOP_AXI_INFRA_SEL 38
#define CLK_TOP_UART_SEL 39
#define CLK_TOP_EMMC_250M_SEL 40
#define CLK_TOP_EMMC_400M_SEL 41
#define CLK_TOP_SPI_SEL 42
#define CLK_TOP_SPIM_MST_SEL 43
#define CLK_TOP_NFI1X_SEL 44
#define CLK_TOP_SPINFI_SEL 45
#define CLK_TOP_PWM_SEL 46
#define CLK_TOP_I2C_SEL 47
#define CLK_TOP_PCIE_MBIST_250M_SEL 48
#define CLK_TOP_PEXTP_TL_SEL 49
#define CLK_TOP_PEXTP_TL_P1_SEL 50
#define CLK_TOP_PEXTP_TL_P2_SEL 51
#define CLK_TOP_PEXTP_TL_P3_SEL 52
#define CLK_TOP_USB_SYS_SEL 53
#define CLK_TOP_USB_SYS_P1_SEL 54
#define CLK_TOP_USB_XHCI_SEL 55
#define CLK_TOP_USB_XHCI_P1_SEL 56
#define CLK_TOP_USB_FRMCNT_SEL 57
#define CLK_TOP_USB_FRMCNT_P1_SEL 58
#define CLK_TOP_AUD_SEL 59
#define CLK_TOP_A1SYS_SEL 60
#define CLK_TOP_AUD_L_SEL 61
#define CLK_TOP_A_TUNER_SEL 62
#define CLK_TOP_SSPXTP_SEL 63
#define CLK_TOP_USB_PHY_SEL 64
#define CLK_TOP_USXGMII_SBUS_0_SEL 65
#define CLK_TOP_USXGMII_SBUS_1_SEL 66
#define CLK_TOP_SGM_0_SEL 67
#define CLK_TOP_SGM_SBUS_0_SEL 68
#define CLK_TOP_SGM_1_SEL 69
#define CLK_TOP_SGM_SBUS_1_SEL 70
#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71
#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72
#define CLK_TOP_SYSAXI_SEL 73
#define CLK_TOP_SYSAPB_SEL 74
#define CLK_TOP_ETH_REFCK_50M_SEL 75
#define CLK_TOP_ETH_SYS_200M_SEL 76
#define CLK_TOP_ETH_SYS_SEL 77
#define CLK_TOP_ETH_XGMII_SEL 78
#define CLK_TOP_BUS_TOPS_SEL 79
#define CLK_TOP_NPU_TOPS_SEL 80
#define CLK_TOP_DRAMC_SEL 81
#define CLK_TOP_DRAMC_MD32_SEL 82
#define CLK_TOP_INFRA_F26M_SEL 83
#define CLK_TOP_PEXTP_P0_SEL 84
#define CLK_TOP_PEXTP_P1_SEL 85
#define CLK_TOP_PEXTP_P2_SEL 86
#define CLK_TOP_PEXTP_P3_SEL 87
#define CLK_TOP_DA_XTP_GLB_P0_SEL 88
#define CLK_TOP_DA_XTP_GLB_P1_SEL 89
#define CLK_TOP_DA_XTP_GLB_P2_SEL 90
#define CLK_TOP_DA_XTP_GLB_P3_SEL 91
#define CLK_TOP_CKM_SEL 92
#define CLK_TOP_DA_SEL 93
#define CLK_TOP_PEXTP_SEL 94
#define CLK_TOP_TOPS_P2_26M_SEL 95
#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96
#define CLK_TOP_NETSYS_SYNC_250M_SEL 97
#define CLK_TOP_MACSEC_SEL 98
#define CLK_TOP_NETSYS_TOPS_400M_SEL 99
#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100
#define CLK_TOP_NETSYS_WARP_SEL 101
#define CLK_TOP_ETH_MII_SEL 102
#define CLK_TOP_NPU_SEL 103
#define CLK_TOP_AUD_I2S_M 104
/* MCUSYS */
#define CLK_MCU_BUS_DIV_SEL 0
#define CLK_MCU_ARM_DIV_SEL 1
/* INFRACFG_AO */
#define CLK_INFRA_MUX_UART0_SEL 0
#define CLK_INFRA_MUX_UART1_SEL 1
#define CLK_INFRA_MUX_UART2_SEL 2
#define CLK_INFRA_MUX_SPI0_SEL 3
#define CLK_INFRA_MUX_SPI1_SEL 4
#define CLK_INFRA_MUX_SPI2_SEL 5
#define CLK_INFRA_PWM_SEL 6
#define CLK_INFRA_PWM_CK1_SEL 7
#define CLK_INFRA_PWM_CK2_SEL 8
#define CLK_INFRA_PWM_CK3_SEL 9
#define CLK_INFRA_PWM_CK4_SEL 10
#define CLK_INFRA_PWM_CK5_SEL 11
#define CLK_INFRA_PWM_CK6_SEL 12
#define CLK_INFRA_PWM_CK7_SEL 13
#define CLK_INFRA_PWM_CK8_SEL 14
#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
/* INFRACFG */
#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19
#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20
#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21
#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22
#define CLK_INFRA_66M_GPT_BCK 23
#define CLK_INFRA_66M_PWM_HCK 24
#define CLK_INFRA_66M_PWM_BCK 25
#define CLK_INFRA_66M_PWM_CK1 26
#define CLK_INFRA_66M_PWM_CK2 27
#define CLK_INFRA_66M_PWM_CK3 28
#define CLK_INFRA_66M_PWM_CK4 29
#define CLK_INFRA_66M_PWM_CK5 30
#define CLK_INFRA_66M_PWM_CK6 31
#define CLK_INFRA_66M_PWM_CK7 32
#define CLK_INFRA_66M_PWM_CK8 33
#define CLK_INFRA_133M_CQDMA_BCK 34
#define CLK_INFRA_66M_AUD_SLV_BCK 35
#define CLK_INFRA_AUD_26M 36
#define CLK_INFRA_AUD_L 37
#define CLK_INFRA_AUD_AUD 38
#define CLK_INFRA_AUD_EG2 39
#define CLK_INFRA_DRAMC_F26M 40
#define CLK_INFRA_133M_DBG_ACKM 41
#define CLK_INFRA_66M_AP_DMA_BCK 42
#define CLK_INFRA_66M_SEJ_BCK 43
#define CLK_INFRA_PRE_CK_SEJ_F13M 44
#define CLK_INFRA_26M_THERM_SYSTEM 45
#define CLK_INFRA_I2C_BCK 46
#define CLK_INFRA_52M_UART0_CK 47
#define CLK_INFRA_52M_UART1_CK 48
#define CLK_INFRA_52M_UART2_CK 49
#define CLK_INFRA_NFI 50
#define CLK_INFRA_SPINFI 51
#define CLK_INFRA_66M_NFI_HCK 52
#define CLK_INFRA_104M_SPI0 53
#define CLK_INFRA_104M_SPI1 54
#define CLK_INFRA_104M_SPI2_BCK 55
#define CLK_INFRA_66M_SPI0_HCK 56
#define CLK_INFRA_66M_SPI1_HCK 57
#define CLK_INFRA_66M_SPI2_HCK 58
#define CLK_INFRA_66M_FLASHIF_AXI 59
#define CLK_INFRA_RTC 60
#define CLK_INFRA_26M_ADC_BCK 61
#define CLK_INFRA_RC_ADC 62
#define CLK_INFRA_MSDC400 63
#define CLK_INFRA_MSDC2_HCK 64
#define CLK_INFRA_133M_MSDC_0_HCK 65
#define CLK_INFRA_66M_MSDC_0_HCK 66
#define CLK_INFRA_133M_CPUM_BCK 67
#define CLK_INFRA_BIST2FPC 68
#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69
#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70
#define CLK_INFRA_133M_USB_HCK 71
#define CLK_INFRA_133M_USB_HCK_CK_P1 72
#define CLK_INFRA_66M_USB_HCK 73
#define CLK_INFRA_66M_USB_HCK_CK_P1 74
#define CLK_INFRA_USB_SYS 75
#define CLK_INFRA_USB_SYS_CK_P1 76
#define CLK_INFRA_USB_REF 77
#define CLK_INFRA_USB_CK_P1 78
#define CLK_INFRA_USB_FRMCNT 79
#define CLK_INFRA_USB_FRMCNT_CK_P1 80
#define CLK_INFRA_USB_PIPE 81
#define CLK_INFRA_USB_PIPE_CK_P1 82
#define CLK_INFRA_USB_UTMI 83
#define CLK_INFRA_USB_UTMI_CK_P1 84
#define CLK_INFRA_USB_XHCI 85
#define CLK_INFRA_USB_XHCI_CK_P1 86
#define CLK_INFRA_PCIE_GFMUX_TL_P0 87
#define CLK_INFRA_PCIE_GFMUX_TL_P1 88
#define CLK_INFRA_PCIE_GFMUX_TL_P2 89
#define CLK_INFRA_PCIE_GFMUX_TL_P3 90
#define CLK_INFRA_PCIE_PIPE_P0 91
#define CLK_INFRA_PCIE_PIPE_P1 92
#define CLK_INFRA_PCIE_PIPE_P2 93
#define CLK_INFRA_PCIE_PIPE_P3 94
#define CLK_INFRA_133M_PCIE_CK_P0 95
#define CLK_INFRA_133M_PCIE_CK_P1 96
#define CLK_INFRA_133M_PCIE_CK_P2 97
#define CLK_INFRA_133M_PCIE_CK_P3 98
/* ETHDMA */
#define CLK_ETHDMA_XGP1_EN 0
#define CLK_ETHDMA_XGP2_EN 1
#define CLK_ETHDMA_XGP3_EN 2
#define CLK_ETHDMA_FE_EN 3
#define CLK_ETHDMA_GP2_EN 4
#define CLK_ETHDMA_GP1_EN 5
#define CLK_ETHDMA_GP3_EN 6
#define CLK_ETHDMA_ESW_EN 7
#define CLK_ETHDMA_CRYPT0_EN 8
#define CLK_ETHDMA_NR_CLK 9
/* SGMIISYS_0 */
#define CLK_SGM0_TX_EN 0
#define CLK_SGM0_RX_EN 1
#define CLK_SGMII0_NR_CLK 2
/* SGMIISYS_1 */
#define CLK_SGM1_TX_EN 0
#define CLK_SGM1_RX_EN 1
#define CLK_SGMII1_NR_CLK 2
/* ETHWARP */
#define CLK_ETHWARP_WOCPU2_EN 0
#define CLK_ETHWARP_WOCPU1_EN 1
#define CLK_ETHWARP_WOCPU0_EN 2
#define CLK_ETHWARP_NR_CLK 3
/* XFIPLL */
#define CLK_XFIPLL_PLL 0
#define CLK_XFIPLL_PLL_EN 1
#endif /* _DT_BINDINGS_CLK_MT7988_H */

6
include/dt-bindings/clock/qcom,gcc-msm8939.h
View File

@ -193,6 +193,12 @@
#define GCC_VENUS0_CORE1_VCODEC0_CLK 184
#define GCC_OXILI_TIMER_CLK 185
#define SYSTEM_MM_NOC_BFDCD_CLK_SRC 186
#define CSI2_CLK_SRC 187
#define GCC_CAMSS_CSI2_AHB_CLK 188
#define GCC_CAMSS_CSI2_CLK 189
#define GCC_CAMSS_CSI2PHY_CLK 190
#define GCC_CAMSS_CSI2PIX_CLK 191
#define GCC_CAMSS_CSI2RDI_CLK 192
/* Indexes for GDSCs */
#define BIMC_GDSC 0

147
include/dt-bindings/clock/qcom,qdu1000-ecpricc.h Normal file
View File

@ -0,0 +1,147 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_ECPRI_CC_QDU1000_H
#define _DT_BINDINGS_CLK_QCOM_ECPRI_CC_QDU1000_H
/* ECPRI_CC clocks */
#define ECPRI_CC_PLL0 0
#define ECPRI_CC_PLL1 1
#define ECPRI_CC_ECPRI_CG_CLK 2
#define ECPRI_CC_ECPRI_CLK_SRC 3
#define ECPRI_CC_ECPRI_DMA_CLK 4
#define ECPRI_CC_ECPRI_DMA_CLK_SRC 5
#define ECPRI_CC_ECPRI_DMA_NOC_CLK 6
#define ECPRI_CC_ECPRI_FAST_CLK 7
#define ECPRI_CC_ECPRI_FAST_CLK_SRC 8
#define ECPRI_CC_ECPRI_FAST_DIV2_CLK 9
#define ECPRI_CC_ECPRI_FAST_DIV2_CLK_SRC 10
#define ECPRI_CC_ECPRI_FAST_DIV2_NOC_CLK 11
#define ECPRI_CC_ECPRI_FR_CLK 12
#define ECPRI_CC_ECPRI_ORAN_CLK_SRC 13
#define ECPRI_CC_ECPRI_ORAN_DIV2_CLK 14
#define ECPRI_CC_ETH_100G_C2C0_HM_FF_CLK_SRC 15
#define ECPRI_CC_ETH_100G_C2C0_UDP_FIFO_CLK 16
#define ECPRI_CC_ETH_100G_C2C1_UDP_FIFO_CLK 17
#define ECPRI_CC_ETH_100G_C2C_0_HM_FF_0_CLK 18
#define ECPRI_CC_ETH_100G_C2C_0_HM_FF_1_CLK 19
#define ECPRI_CC_ETH_100G_C2C_HM_FF_0_DIV_CLK_SRC 20
#define ECPRI_CC_ETH_100G_C2C_HM_FF_1_DIV_CLK_SRC 21
#define ECPRI_CC_ETH_100G_C2C_HM_MACSEC_CLK 22
#define ECPRI_CC_ETH_100G_C2C_HM_MACSEC_CLK_SRC 23
#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_0_CLK 24
#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_0_DIV_CLK_SRC 25
#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_1_CLK 26
#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_1_DIV_CLK_SRC 27
#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_CLK_SRC 28
#define ECPRI_CC_ETH_100G_DBG_C2C_UDP_FIFO_CLK 29
#define ECPRI_CC_ETH_100G_FH0_HM_FF_CLK_SRC 30
#define ECPRI_CC_ETH_100G_FH0_MACSEC_CLK_SRC 31
#define ECPRI_CC_ETH_100G_FH1_HM_FF_CLK_SRC 32
#define ECPRI_CC_ETH_100G_FH1_MACSEC_CLK_SRC 33
#define ECPRI_CC_ETH_100G_FH2_HM_FF_CLK_SRC 34
#define ECPRI_CC_ETH_100G_FH2_MACSEC_CLK_SRC 35
#define ECPRI_CC_ETH_100G_FH_0_HM_FF_0_CLK 36
#define ECPRI_CC_ETH_100G_FH_0_HM_FF_0_DIV_CLK_SRC 37
#define ECPRI_CC_ETH_100G_FH_0_HM_FF_1_CLK 38
#define ECPRI_CC_ETH_100G_FH_0_HM_FF_1_DIV_CLK_SRC 39
#define ECPRI_CC_ETH_100G_FH_0_HM_FF_2_CLK 40
#define ECPRI_CC_ETH_100G_FH_0_HM_FF_2_DIV_CLK_SRC 41
#define ECPRI_CC_ETH_100G_FH_0_HM_FF_3_CLK 42
#define ECPRI_CC_ETH_100G_FH_0_HM_FF_3_DIV_CLK_SRC 43
#define ECPRI_CC_ETH_100G_FH_0_UDP_FIFO_CLK 44
#define ECPRI_CC_ETH_100G_FH_1_HM_FF_0_CLK 45
#define ECPRI_CC_ETH_100G_FH_1_HM_FF_0_DIV_CLK_SRC 46
#define ECPRI_CC_ETH_100G_FH_1_HM_FF_1_CLK 47
#define ECPRI_CC_ETH_100G_FH_1_HM_FF_1_DIV_CLK_SRC 48
#define ECPRI_CC_ETH_100G_FH_1_HM_FF_2_CLK 49
#define ECPRI_CC_ETH_100G_FH_1_HM_FF_2_DIV_CLK_SRC 50
#define ECPRI_CC_ETH_100G_FH_1_HM_FF_3_CLK 51
#define ECPRI_CC_ETH_100G_FH_1_HM_FF_3_DIV_CLK_SRC 52
#define ECPRI_CC_ETH_100G_FH_1_UDP_FIFO_CLK 53
#define ECPRI_CC_ETH_100G_FH_2_HM_FF_0_CLK 54
#define ECPRI_CC_ETH_100G_FH_2_HM_FF_0_DIV_CLK_SRC 55
#define ECPRI_CC_ETH_100G_FH_2_HM_FF_1_CLK 56
#define ECPRI_CC_ETH_100G_FH_2_HM_FF_1_DIV_CLK_SRC 57
#define ECPRI_CC_ETH_100G_FH_2_HM_FF_2_CLK 58
#define ECPRI_CC_ETH_100G_FH_2_HM_FF_2_DIV_CLK_SRC 59
#define ECPRI_CC_ETH_100G_FH_2_HM_FF_3_CLK 60
#define ECPRI_CC_ETH_100G_FH_2_HM_FF_3_DIV_CLK_SRC 61
#define ECPRI_CC_ETH_100G_FH_2_UDP_FIFO_CLK 62
#define ECPRI_CC_ETH_100G_FH_MACSEC_0_CLK 63
#define ECPRI_CC_ETH_100G_FH_MACSEC_1_CLK 64
#define ECPRI_CC_ETH_100G_FH_MACSEC_2_CLK 65
#define ECPRI_CC_ETH_100G_MAC_C2C_HM_REF_CLK 66
#define ECPRI_CC_ETH_100G_MAC_C2C_HM_REF_CLK_SRC 67
#define ECPRI_CC_ETH_100G_MAC_DBG_C2C_HM_REF_CLK 68
#define ECPRI_CC_ETH_100G_MAC_DBG_C2C_HM_REF_CLK_SRC 69
#define ECPRI_CC_ETH_100G_MAC_FH0_HM_REF_CLK 70
#define ECPRI_CC_ETH_100G_MAC_FH0_HM_REF_CLK_SRC 71
#define ECPRI_CC_ETH_100G_MAC_FH1_HM_REF_CLK 72
#define ECPRI_CC_ETH_100G_MAC_FH1_HM_REF_CLK_SRC 73
#define ECPRI_CC_ETH_100G_MAC_FH2_HM_REF_CLK 74
#define ECPRI_CC_ETH_100G_MAC_FH2_HM_REF_CLK_SRC 75
#define ECPRI_CC_ETH_DBG_NFAPI_AXI_CLK 76
#define ECPRI_CC_ETH_DBG_NOC_AXI_CLK 77
#define ECPRI_CC_ETH_PHY_0_OCK_SRAM_CLK 78
#define ECPRI_CC_ETH_PHY_1_OCK_SRAM_CLK 79
#define ECPRI_CC_ETH_PHY_2_OCK_SRAM_CLK 80
#define ECPRI_CC_ETH_PHY_3_OCK_SRAM_CLK 81
#define ECPRI_CC_ETH_PHY_4_OCK_SRAM_CLK 82
#define ECPRI_CC_MSS_EMAC_CLK 83
#define ECPRI_CC_MSS_EMAC_CLK_SRC 84
#define ECPRI_CC_MSS_ORAN_CLK 85
#define ECPRI_CC_PHY0_LANE0_RX_CLK 86
#define ECPRI_CC_PHY0_LANE0_TX_CLK 87
#define ECPRI_CC_PHY0_LANE1_RX_CLK 88
#define ECPRI_CC_PHY0_LANE1_TX_CLK 89
#define ECPRI_CC_PHY0_LANE2_RX_CLK 90
#define ECPRI_CC_PHY0_LANE2_TX_CLK 91
#define ECPRI_CC_PHY0_LANE3_RX_CLK 92
#define ECPRI_CC_PHY0_LANE3_TX_CLK 93
#define ECPRI_CC_PHY1_LANE0_RX_CLK 94
#define ECPRI_CC_PHY1_LANE0_TX_CLK 95
#define ECPRI_CC_PHY1_LANE1_RX_CLK 96
#define ECPRI_CC_PHY1_LANE1_TX_CLK 97
#define ECPRI_CC_PHY1_LANE2_RX_CLK 98
#define ECPRI_CC_PHY1_LANE2_TX_CLK 99
#define ECPRI_CC_PHY1_LANE3_RX_CLK 100
#define ECPRI_CC_PHY1_LANE3_TX_CLK 101
#define ECPRI_CC_PHY2_LANE0_RX_CLK 102
#define ECPRI_CC_PHY2_LANE0_TX_CLK 103
#define ECPRI_CC_PHY2_LANE1_RX_CLK 104
#define ECPRI_CC_PHY2_LANE1_TX_CLK 105
#define ECPRI_CC_PHY2_LANE2_RX_CLK 106
#define ECPRI_CC_PHY2_LANE2_TX_CLK 107
#define ECPRI_CC_PHY2_LANE3_RX_CLK 108
#define ECPRI_CC_PHY2_LANE3_TX_CLK 109
#define ECPRI_CC_PHY3_LANE0_RX_CLK 110
#define ECPRI_CC_PHY3_LANE0_TX_CLK 111
#define ECPRI_CC_PHY3_LANE1_RX_CLK 112
#define ECPRI_CC_PHY3_LANE1_TX_CLK 113
#define ECPRI_CC_PHY3_LANE2_RX_CLK 114
#define ECPRI_CC_PHY3_LANE2_TX_CLK 115
#define ECPRI_CC_PHY3_LANE3_RX_CLK 116
#define ECPRI_CC_PHY3_LANE3_TX_CLK 117
#define ECPRI_CC_PHY4_LANE0_RX_CLK 118
#define ECPRI_CC_PHY4_LANE0_TX_CLK 119
#define ECPRI_CC_PHY4_LANE1_RX_CLK 120
#define ECPRI_CC_PHY4_LANE1_TX_CLK 121
#define ECPRI_CC_PHY4_LANE2_RX_CLK 122
#define ECPRI_CC_PHY4_LANE2_TX_CLK 123
#define ECPRI_CC_PHY4_LANE3_RX_CLK 124
#define ECPRI_CC_PHY4_LANE3_TX_CLK 125
/* ECPRI_CC resets */
#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ECPRI_SS_BCR 0
#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_C2C_BCR 1
#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH0_BCR 2
#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH1_BCR 3
#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH2_BCR 4
#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_WRAPPER_TOP_BCR 5
#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_MODEM_BCR 6
#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_NOC_BCR 7
#endif

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include/dt-bindings/clock/qcom,sc8280xp-camcc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Linaro Ltd.
*/
#ifndef __DT_BINDINGS_CLK_QCOM_CAMCC_SC8280XP_H__
#define __DT_BINDINGS_CLK_QCOM_CAMCC_SC8280XP_H__
/* CAMCC clocks */
#define CAMCC_PLL0 0
#define CAMCC_PLL0_OUT_EVEN 1
#define CAMCC_PLL0_OUT_ODD 2
#define CAMCC_PLL1 3
#define CAMCC_PLL1_OUT_EVEN 4
#define CAMCC_PLL2 5
#define CAMCC_PLL3 6
#define CAMCC_PLL3_OUT_EVEN 7
#define CAMCC_PLL4 8
#define CAMCC_PLL4_OUT_EVEN 9
#define CAMCC_PLL5 10
#define CAMCC_PLL5_OUT_EVEN 11
#define CAMCC_PLL6 12
#define CAMCC_PLL6_OUT_EVEN 13
#define CAMCC_PLL7 14
#define CAMCC_PLL7_OUT_EVEN 15
#define CAMCC_PLL7_OUT_ODD 16
#define CAMCC_BPS_AHB_CLK 17
#define CAMCC_BPS_AREG_CLK 18
#define CAMCC_BPS_AXI_CLK 19
#define CAMCC_BPS_CLK 20
#define CAMCC_BPS_CLK_SRC 21
#define CAMCC_CAMNOC_AXI_CLK 22
#define CAMCC_CAMNOC_AXI_CLK_SRC 23
#define CAMCC_CAMNOC_DCD_XO_CLK 24
#define CAMCC_CCI_0_CLK 25
#define CAMCC_CCI_0_CLK_SRC 26
#define CAMCC_CCI_1_CLK 27
#define CAMCC_CCI_1_CLK_SRC 28
#define CAMCC_CCI_2_CLK 29
#define CAMCC_CCI_2_CLK_SRC 30
#define CAMCC_CCI_3_CLK 31
#define CAMCC_CCI_3_CLK_SRC 32
#define CAMCC_CORE_AHB_CLK 33
#define CAMCC_CPAS_AHB_CLK 34
#define CAMCC_CPHY_RX_CLK_SRC 35
#define CAMCC_CSI0PHYTIMER_CLK 36
#define CAMCC_CSI0PHYTIMER_CLK_SRC 37
#define CAMCC_CSI1PHYTIMER_CLK 38
#define CAMCC_CSI1PHYTIMER_CLK_SRC 39
#define CAMCC_CSI2PHYTIMER_CLK 40
#define CAMCC_CSI2PHYTIMER_CLK_SRC 41
#define CAMCC_CSI3PHYTIMER_CLK 42
#define CAMCC_CSI3PHYTIMER_CLK_SRC 43
#define CAMCC_CSIPHY0_CLK 44
#define CAMCC_CSIPHY1_CLK 45
#define CAMCC_CSIPHY2_CLK 46
#define CAMCC_CSIPHY3_CLK 47
#define CAMCC_FAST_AHB_CLK_SRC 48
#define CAMCC_GDSC_CLK 49
#define CAMCC_ICP_AHB_CLK 50
#define CAMCC_ICP_CLK 51
#define CAMCC_ICP_CLK_SRC 52
#define CAMCC_IFE_0_AXI_CLK 53
#define CAMCC_IFE_0_CLK 54
#define CAMCC_IFE_0_CLK_SRC 55
#define CAMCC_IFE_0_CPHY_RX_CLK 56
#define CAMCC_IFE_0_CSID_CLK 57
#define CAMCC_IFE_0_CSID_CLK_SRC 58
#define CAMCC_IFE_0_DSP_CLK 59
#define CAMCC_IFE_1_AXI_CLK 60
#define CAMCC_IFE_1_CLK 61
#define CAMCC_IFE_1_CLK_SRC 62
#define CAMCC_IFE_1_CPHY_RX_CLK 63
#define CAMCC_IFE_1_CSID_CLK 64
#define CAMCC_IFE_1_CSID_CLK_SRC 65
#define CAMCC_IFE_1_DSP_CLK 66
#define CAMCC_IFE_2_AXI_CLK 67
#define CAMCC_IFE_2_CLK 68
#define CAMCC_IFE_2_CLK_SRC 69
#define CAMCC_IFE_2_CPHY_RX_CLK 70
#define CAMCC_IFE_2_CSID_CLK 71
#define CAMCC_IFE_2_CSID_CLK_SRC 72
#define CAMCC_IFE_2_DSP_CLK 73
#define CAMCC_IFE_3_AXI_CLK 74
#define CAMCC_IFE_3_CLK 75
#define CAMCC_IFE_3_CLK_SRC 76
#define CAMCC_IFE_3_CPHY_RX_CLK 77
#define CAMCC_IFE_3_CSID_CLK 78
#define CAMCC_IFE_3_CSID_CLK_SRC 79
#define CAMCC_IFE_3_DSP_CLK 80
#define CAMCC_IFE_LITE_0_CLK 81
#define CAMCC_IFE_LITE_0_CLK_SRC 82
#define CAMCC_IFE_LITE_0_CPHY_RX_CLK 83
#define CAMCC_IFE_LITE_0_CSID_CLK 84
#define CAMCC_IFE_LITE_0_CSID_CLK_SRC 85
#define CAMCC_IFE_LITE_1_CLK 86
#define CAMCC_IFE_LITE_1_CLK_SRC 87
#define CAMCC_IFE_LITE_1_CPHY_RX_CLK 88
#define CAMCC_IFE_LITE_1_CSID_CLK 89
#define CAMCC_IFE_LITE_1_CSID_CLK_SRC 90
#define CAMCC_IFE_LITE_2_CLK 91
#define CAMCC_IFE_LITE_2_CLK_SRC 92
#define CAMCC_IFE_LITE_2_CPHY_RX_CLK 93
#define CAMCC_IFE_LITE_2_CSID_CLK 94
#define CAMCC_IFE_LITE_2_CSID_CLK_SRC 95
#define CAMCC_IFE_LITE_3_CLK 96
#define CAMCC_IFE_LITE_3_CLK_SRC 97
#define CAMCC_IFE_LITE_3_CPHY_RX_CLK 98
#define CAMCC_IFE_LITE_3_CSID_CLK 99
#define CAMCC_IFE_LITE_3_CSID_CLK_SRC 100
#define CAMCC_IPE_0_AHB_CLK 101
#define CAMCC_IPE_0_AREG_CLK 102
#define CAMCC_IPE_0_AXI_CLK 103
#define CAMCC_IPE_0_CLK 104
#define CAMCC_IPE_0_CLK_SRC 105
#define CAMCC_IPE_1_AHB_CLK 106
#define CAMCC_IPE_1_AREG_CLK 107
#define CAMCC_IPE_1_AXI_CLK 108
#define CAMCC_IPE_1_CLK 109
#define CAMCC_JPEG_CLK 110
#define CAMCC_JPEG_CLK_SRC 111
#define CAMCC_LRME_CLK 112
#define CAMCC_LRME_CLK_SRC 113
#define CAMCC_MCLK0_CLK 114
#define CAMCC_MCLK0_CLK_SRC 115
#define CAMCC_MCLK1_CLK 116
#define CAMCC_MCLK1_CLK_SRC 117
#define CAMCC_MCLK2_CLK 118
#define CAMCC_MCLK2_CLK_SRC 119
#define CAMCC_MCLK3_CLK 120
#define CAMCC_MCLK3_CLK_SRC 121
#define CAMCC_MCLK4_CLK 122
#define CAMCC_MCLK4_CLK_SRC 123
#define CAMCC_MCLK5_CLK 124
#define CAMCC_MCLK5_CLK_SRC 125
#define CAMCC_MCLK6_CLK 126
#define CAMCC_MCLK6_CLK_SRC 127
#define CAMCC_MCLK7_CLK 128
#define CAMCC_MCLK7_CLK_SRC 129
#define CAMCC_SLEEP_CLK 130
#define CAMCC_SLEEP_CLK_SRC 131
#define CAMCC_SLOW_AHB_CLK_SRC 132
#define CAMCC_XO_CLK_SRC 133
/* CAMCC resets */
#define CAMCC_BPS_BCR 0
#define CAMCC_CAMNOC_BCR 1
#define CAMCC_CCI_BCR 2
#define CAMCC_CPAS_BCR 3
#define CAMCC_CSI0PHY_BCR 4
#define CAMCC_CSI1PHY_BCR 5
#define CAMCC_CSI2PHY_BCR 6
#define CAMCC_CSI3PHY_BCR 7
#define CAMCC_ICP_BCR 8
#define CAMCC_IFE_0_BCR 9
#define CAMCC_IFE_1_BCR 10
#define CAMCC_IFE_2_BCR 11
#define CAMCC_IFE_3_BCR 12
#define CAMCC_IFE_LITE_0_BCR 13
#define CAMCC_IFE_LITE_1_BCR 14
#define CAMCC_IFE_LITE_2_BCR 15
#define CAMCC_IFE_LITE_3_BCR 16
#define CAMCC_IPE_0_BCR 17
#define CAMCC_IPE_1_BCR 18
#define CAMCC_JPEG_BCR 19
#define CAMCC_LRME_BCR 20
/* CAMCC GDSCRs */
#define BPS_GDSC 0
#define IFE_0_GDSC 1
#define IFE_1_GDSC 2
#define IFE_2_GDSC 3
#define IFE_3_GDSC 4
#define IPE_0_GDSC 5
#define IPE_1_GDSC 6
#define TITAN_TOP_GDSC 7
#endif /* __DT_BINDINGS_CLK_QCOM_CAMCC_SC8280XP_H__ */

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include/dt-bindings/clock/qcom,sm8650-dispcc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved
* Copyright (c) 2023, Linaro Ltd.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_SM8650_DISP_CC_H
#define _DT_BINDINGS_CLK_QCOM_SM8650_DISP_CC_H
/* DISP_CC clocks */
#define DISP_CC_MDSS_ACCU_CLK 0
#define DISP_CC_MDSS_AHB1_CLK 1
#define DISP_CC_MDSS_AHB_CLK 2
#define DISP_CC_MDSS_AHB_CLK_SRC 3
#define DISP_CC_MDSS_BYTE0_CLK 4
#define DISP_CC_MDSS_BYTE0_CLK_SRC 5
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6
#define DISP_CC_MDSS_BYTE0_INTF_CLK 7
#define DISP_CC_MDSS_BYTE1_CLK 8
#define DISP_CC_MDSS_BYTE1_CLK_SRC 9
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 10
#define DISP_CC_MDSS_BYTE1_INTF_CLK 11
#define DISP_CC_MDSS_DPTX0_AUX_CLK 12
#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 13
#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 14
#define DISP_CC_MDSS_DPTX0_LINK_CLK 15
#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 16
#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 17
#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 18
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 19
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 20
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 21
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 22
#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 23
#define DISP_CC_MDSS_DPTX1_AUX_CLK 24
#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 25
#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 26
#define DISP_CC_MDSS_DPTX1_LINK_CLK 27
#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 28
#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 29
#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 30
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 31
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 32
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 33
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 34
#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 35
#define DISP_CC_MDSS_DPTX2_AUX_CLK 36
#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 37
#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 38
#define DISP_CC_MDSS_DPTX2_LINK_CLK 39
#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 40
#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 41
#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 42
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 43
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 44
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 45
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 46
#define DISP_CC_MDSS_DPTX3_AUX_CLK 47
#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 48
#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 49
#define DISP_CC_MDSS_DPTX3_LINK_CLK 50
#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 51
#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 52
#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 53
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 54
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 55
#define DISP_CC_MDSS_ESC0_CLK 56
#define DISP_CC_MDSS_ESC0_CLK_SRC 57
#define DISP_CC_MDSS_ESC1_CLK 58
#define DISP_CC_MDSS_ESC1_CLK_SRC 59
#define DISP_CC_MDSS_MDP1_CLK 60
#define DISP_CC_MDSS_MDP_CLK 61
#define DISP_CC_MDSS_MDP_CLK_SRC 62
#define DISP_CC_MDSS_MDP_LUT1_CLK 63
#define DISP_CC_MDSS_MDP_LUT_CLK 64
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 65
#define DISP_CC_MDSS_PCLK0_CLK 66
#define DISP_CC_MDSS_PCLK0_CLK_SRC 67
#define DISP_CC_MDSS_PCLK1_CLK 68
#define DISP_CC_MDSS_PCLK1_CLK_SRC 69
#define DISP_CC_MDSS_RSCC_AHB_CLK 70
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 71
#define DISP_CC_MDSS_VSYNC1_CLK 72
#define DISP_CC_MDSS_VSYNC_CLK 73
#define DISP_CC_MDSS_VSYNC_CLK_SRC 74
#define DISP_CC_PLL0 75
#define DISP_CC_PLL1 76
#define DISP_CC_SLEEP_CLK 77
#define DISP_CC_SLEEP_CLK_SRC 78
#define DISP_CC_XO_CLK 79
#define DISP_CC_XO_CLK_SRC 80
/* DISP_CC resets */
#define DISP_CC_MDSS_CORE_BCR 0
#define DISP_CC_MDSS_CORE_INT2_BCR 1
#define DISP_CC_MDSS_RSCC_BCR 2
/* DISP_CC GDSCR */
#define MDSS_GDSC 0
#define MDSS_INT2_GDSC 1
#endif

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include/dt-bindings/clock/qcom,sm8650-gcc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8650_H
#define _DT_BINDINGS_CLK_QCOM_GCC_SM8650_H
/* GCC clocks */
#define GCC_AGGRE_NOC_PCIE_AXI_CLK 0
#define GCC_AGGRE_UFS_PHY_AXI_CLK 1
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 2
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3
#define GCC_BOOT_ROM_AHB_CLK 4
#define GCC_CAMERA_AHB_CLK 5
#define GCC_CAMERA_HF_AXI_CLK 6
#define GCC_CAMERA_SF_AXI_CLK 7
#define GCC_CAMERA_XO_CLK 8
#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 9
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 10
#define GCC_CNOC_PCIE_SF_AXI_CLK 11
#define GCC_DDRSS_GPU_AXI_CLK 12
#define GCC_DDRSS_PCIE_SF_QTB_CLK 13
#define GCC_DISP_AHB_CLK 14
#define GCC_DISP_HF_AXI_CLK 15
#define GCC_DISP_XO_CLK 16
#define GCC_GP1_CLK 17
#define GCC_GP1_CLK_SRC 18
#define GCC_GP2_CLK 19
#define GCC_GP2_CLK_SRC 20
#define GCC_GP3_CLK 21
#define GCC_GP3_CLK_SRC 22
#define GCC_GPLL0 23
#define GCC_GPLL0_OUT_EVEN 24
#define GCC_GPLL1 25
#define GCC_GPLL3 26
#define GCC_GPLL4 27
#define GCC_GPLL6 28
#define GCC_GPLL7 29
#define GCC_GPLL9 30
#define GCC_GPU_CFG_AHB_CLK 31
#define GCC_GPU_GPLL0_CLK_SRC 32
#define GCC_GPU_GPLL0_DIV_CLK_SRC 33
#define GCC_GPU_MEMNOC_GFX_CLK 34
#define GCC_GPU_SNOC_DVM_GFX_CLK 35
#define GCC_PCIE_0_AUX_CLK 36
#define GCC_PCIE_0_AUX_CLK_SRC 37
#define GCC_PCIE_0_CFG_AHB_CLK 38
#define GCC_PCIE_0_MSTR_AXI_CLK 39
#define GCC_PCIE_0_PHY_RCHNG_CLK 40
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 41
#define GCC_PCIE_0_PIPE_CLK 42
#define GCC_PCIE_0_PIPE_CLK_SRC 43
#define GCC_PCIE_0_SLV_AXI_CLK 44
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 45
#define GCC_PCIE_1_AUX_CLK 46
#define GCC_PCIE_1_AUX_CLK_SRC 47
#define GCC_PCIE_1_CFG_AHB_CLK 48
#define GCC_PCIE_1_MSTR_AXI_CLK 49
#define GCC_PCIE_1_PHY_AUX_CLK 50
#define GCC_PCIE_1_PHY_AUX_CLK_SRC 51
#define GCC_PCIE_1_PHY_RCHNG_CLK 52
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 53
#define GCC_PCIE_1_PIPE_CLK 54
#define GCC_PCIE_1_PIPE_CLK_SRC 55
#define GCC_PCIE_1_SLV_AXI_CLK 56
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 57
#define GCC_PDM2_CLK 58
#define GCC_PDM2_CLK_SRC 59
#define GCC_PDM_AHB_CLK 60
#define GCC_PDM_XO4_CLK 61
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 62
#define GCC_QMIP_CAMERA_RT_AHB_CLK 63
#define GCC_QMIP_DISP_AHB_CLK 64
#define GCC_QMIP_GPU_AHB_CLK 65
#define GCC_QMIP_PCIE_AHB_CLK 66
#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 67
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 68
#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 69
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 70
#define GCC_QUPV3_I2C_CORE_CLK 71
#define GCC_QUPV3_I2C_S0_CLK 72
#define GCC_QUPV3_I2C_S0_CLK_SRC 73
#define GCC_QUPV3_I2C_S1_CLK 74
#define GCC_QUPV3_I2C_S1_CLK_SRC 75
#define GCC_QUPV3_I2C_S2_CLK 76
#define GCC_QUPV3_I2C_S2_CLK_SRC 77
#define GCC_QUPV3_I2C_S3_CLK 78
#define GCC_QUPV3_I2C_S3_CLK_SRC 79
#define GCC_QUPV3_I2C_S4_CLK 80
#define GCC_QUPV3_I2C_S4_CLK_SRC 81
#define GCC_QUPV3_I2C_S5_CLK 82
#define GCC_QUPV3_I2C_S5_CLK_SRC 83
#define GCC_QUPV3_I2C_S6_CLK 84
#define GCC_QUPV3_I2C_S6_CLK_SRC 85
#define GCC_QUPV3_I2C_S7_CLK 86
#define GCC_QUPV3_I2C_S7_CLK_SRC 87
#define GCC_QUPV3_I2C_S8_CLK 88
#define GCC_QUPV3_I2C_S8_CLK_SRC 89
#define GCC_QUPV3_I2C_S9_CLK 90
#define GCC_QUPV3_I2C_S9_CLK_SRC 91
#define GCC_QUPV3_I2C_S_AHB_CLK 92
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 93
#define GCC_QUPV3_WRAP1_CORE_CLK 94
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK 95
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 96
#define GCC_QUPV3_WRAP1_S0_CLK 97
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 98
#define GCC_QUPV3_WRAP1_S1_CLK 99
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 100
#define GCC_QUPV3_WRAP1_S2_CLK 101
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 102
#define GCC_QUPV3_WRAP1_S3_CLK 103
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 104
#define GCC_QUPV3_WRAP1_S4_CLK 105
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 106
#define GCC_QUPV3_WRAP1_S5_CLK 107
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 108
#define GCC_QUPV3_WRAP1_S6_CLK 109
#define GCC_QUPV3_WRAP1_S6_CLK_SRC 110
#define GCC_QUPV3_WRAP1_S7_CLK 111
#define GCC_QUPV3_WRAP1_S7_CLK_SRC 112
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 113
#define GCC_QUPV3_WRAP2_CORE_CLK 114
#define GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC 115
#define GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK 116
#define GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK 117
#define GCC_QUPV3_WRAP2_S0_CLK 118
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 119
#define GCC_QUPV3_WRAP2_S1_CLK 120
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 121
#define GCC_QUPV3_WRAP2_S2_CLK 122
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 123
#define GCC_QUPV3_WRAP2_S3_CLK 124
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 125
#define GCC_QUPV3_WRAP2_S4_CLK 126
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 127
#define GCC_QUPV3_WRAP2_S5_CLK 128
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 129
#define GCC_QUPV3_WRAP2_S6_CLK 130
#define GCC_QUPV3_WRAP2_S6_CLK_SRC 131
#define GCC_QUPV3_WRAP2_S7_CLK 132
#define GCC_QUPV3_WRAP2_S7_CLK_SRC 133
#define GCC_QUPV3_WRAP3_CORE_2X_CLK 134
#define GCC_QUPV3_WRAP3_CORE_CLK 135
#define GCC_QUPV3_WRAP3_QSPI_REF_CLK 136
#define GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC 137
#define GCC_QUPV3_WRAP3_S0_CLK 138
#define GCC_QUPV3_WRAP3_S0_CLK_SRC 139
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 140
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 141
#define GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK 142
#define GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK 143
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 144
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 145
#define GCC_QUPV3_WRAP_3_M_AHB_CLK 146
#define GCC_QUPV3_WRAP_3_S_AHB_CLK 147
#define GCC_SDCC2_AHB_CLK 148
#define GCC_SDCC2_APPS_CLK 149
#define GCC_SDCC2_APPS_CLK_SRC 150
#define GCC_SDCC4_AHB_CLK 151
#define GCC_SDCC4_APPS_CLK 152
#define GCC_SDCC4_APPS_CLK_SRC 153
#define GCC_UFS_PHY_AHB_CLK 154
#define GCC_UFS_PHY_AXI_CLK 155
#define GCC_UFS_PHY_AXI_CLK_SRC 156
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 157
#define GCC_UFS_PHY_ICE_CORE_CLK 158
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 159
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 160
#define GCC_UFS_PHY_PHY_AUX_CLK 161
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 162
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 163
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 164
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 165
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 166
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 167
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 168
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 169
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 170
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 171
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 172
#define GCC_USB30_PRIM_MASTER_CLK 173
#define GCC_USB30_PRIM_MASTER_CLK_SRC 174
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 175
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 176
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 177
#define GCC_USB30_PRIM_SLEEP_CLK 178
#define GCC_USB3_PRIM_PHY_AUX_CLK 179
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 180
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 181
#define GCC_USB3_PRIM_PHY_PIPE_CLK 182
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 183
#define GCC_VIDEO_AHB_CLK 184
#define GCC_VIDEO_AXI0_CLK 185
#define GCC_VIDEO_AXI1_CLK 186
#define GCC_VIDEO_XO_CLK 187
#define GCC_GPLL0_AO 188
#define GCC_GPLL0_OUT_EVEN_AO 189
#define GCC_GPLL1_AO 190
#define GCC_GPLL3_AO 191
#define GCC_GPLL4_AO 192
#define GCC_GPLL6_AO 193
/* GCC resets */
#define GCC_CAMERA_BCR 0
#define GCC_DISPLAY_BCR 1
#define GCC_GPU_BCR 2
#define GCC_PCIE_0_BCR 3
#define GCC_PCIE_0_LINK_DOWN_BCR 4
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5
#define GCC_PCIE_0_PHY_BCR 6
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7
#define GCC_PCIE_1_BCR 8
#define GCC_PCIE_1_LINK_DOWN_BCR 9
#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10
#define GCC_PCIE_1_PHY_BCR 11
#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12
#define GCC_PCIE_PHY_BCR 13
#define GCC_PCIE_PHY_CFG_AHB_BCR 14
#define GCC_PCIE_PHY_COM_BCR 15
#define GCC_PDM_BCR 16
#define GCC_QUPV3_WRAPPER_1_BCR 17
#define GCC_QUPV3_WRAPPER_2_BCR 18
#define GCC_QUPV3_WRAPPER_3_BCR 19
#define GCC_QUPV3_WRAPPER_I2C_BCR 20
#define GCC_QUSB2PHY_PRIM_BCR 21
#define GCC_QUSB2PHY_SEC_BCR 22
#define GCC_SDCC2_BCR 23
#define GCC_SDCC4_BCR 24
#define GCC_UFS_PHY_BCR 25
#define GCC_USB30_PRIM_BCR 26
#define GCC_USB3_DP_PHY_PRIM_BCR 27
#define GCC_USB3_DP_PHY_SEC_BCR 28
#define GCC_USB3_PHY_PRIM_BCR 29
#define GCC_USB3_PHY_SEC_BCR 30
#define GCC_USB3PHY_PHY_PRIM_BCR 31
#define GCC_USB3PHY_PHY_SEC_BCR 32
#define GCC_VIDEO_AXI0_CLK_ARES 33
#define GCC_VIDEO_AXI1_CLK_ARES 34
#define GCC_VIDEO_BCR 35
/* GCC power domains */
#define PCIE_0_GDSC 0
#define PCIE_0_PHY_GDSC 1
#define PCIE_1_GDSC 2
#define PCIE_1_PHY_GDSC 3
#define UFS_PHY_GDSC 4
#define UFS_MEM_PHY_GDSC 5
#define USB30_PRIM_GDSC 6
#define USB3_PHY_GDSC 7
#endif

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include/dt-bindings/clock/qcom,sm8650-gpucc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved
* Copyright (c) 2023, Linaro Limited
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8650_H
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8650_H
/* GPU_CC clocks */
#define GPU_CC_AHB_CLK 0
#define GPU_CC_CRC_AHB_CLK 1
#define GPU_CC_CX_ACCU_SHIFT_CLK 2
#define GPU_CC_CX_FF_CLK 3
#define GPU_CC_CX_GMU_CLK 4
#define GPU_CC_CXO_AON_CLK 5
#define GPU_CC_CXO_CLK 6
#define GPU_CC_DEMET_CLK 7
#define GPU_CC_DPM_CLK 8
#define GPU_CC_FF_CLK_SRC 9
#define GPU_CC_FREQ_MEASURE_CLK 10
#define GPU_CC_GMU_CLK_SRC 11
#define GPU_CC_GX_ACCU_SHIFT_CLK 12
#define GPU_CC_GX_FF_CLK 13
#define GPU_CC_GX_GFX3D_CLK 14
#define GPU_CC_GX_GFX3D_RDVM_CLK 15
#define GPU_CC_GX_GMU_CLK 16
#define GPU_CC_GX_VSENSE_CLK 17
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 18
#define GPU_CC_HUB_AON_CLK 19
#define GPU_CC_HUB_CLK_SRC 20
#define GPU_CC_HUB_CX_INT_CLK 21
#define GPU_CC_HUB_DIV_CLK_SRC 22
#define GPU_CC_MEMNOC_GFX_CLK 23
#define GPU_CC_PLL0 24
#define GPU_CC_PLL1 25
#define GPU_CC_SLEEP_CLK 26
/* GDSCs */
#define GPU_GX_GDSC 0
#define GPU_CX_GDSC 1
#endif

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include/dt-bindings/clock/qcom,sm8650-tcsr.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8650_H
#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8650_H
/* TCSR CC clocks */
#define TCSR_PCIE_0_CLKREF_EN 0
#define TCSR_PCIE_1_CLKREF_EN 1
#define TCSR_UFS_CLKREF_EN 2
#define TCSR_UFS_PAD_CLKREF_EN 3
#define TCSR_USB2_CLKREF_EN 4
#define TCSR_USB3_CLKREF_EN 5
#endif

4
include/dt-bindings/clock/qcom,videocc-sm8150.h
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/* VIDEO_CC Resets */
#define VIDEO_CC_MVSC_CORE_CLK_BCR 0
#define VIDEO_CC_INTERFACE_BCR 1
#define VIDEO_CC_MVS0_BCR 2
#define VIDEO_CC_MVS1_BCR 3
#define VIDEO_CC_MVSC_BCR 4
/* VIDEO_CC GDSCRs */
#define VENUS_GDSC 0

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include/dt-bindings/clock/qcom,x1e80100-gcc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_X1E80100_H
#define _DT_BINDINGS_CLK_QCOM_GCC_X1E80100_H
/* GCC clocks */
#define GCC_AGGRE_NOC_USB_NORTH_AXI_CLK 0
#define GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK 1
#define GCC_AGGRE_UFS_PHY_AXI_CLK 2
#define GCC_AGGRE_USB2_PRIM_AXI_CLK 3
#define GCC_AGGRE_USB3_MP_AXI_CLK 4
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 5
#define GCC_AGGRE_USB3_SEC_AXI_CLK 6
#define GCC_AGGRE_USB3_TERT_AXI_CLK 7
#define GCC_AGGRE_USB4_0_AXI_CLK 8
#define GCC_AGGRE_USB4_1_AXI_CLK 9
#define GCC_AGGRE_USB4_2_AXI_CLK 10
#define GCC_AGGRE_USB_NOC_AXI_CLK 11
#define GCC_AV1E_AHB_CLK 12
#define GCC_AV1E_AXI_CLK 13
#define GCC_AV1E_XO_CLK 14
#define GCC_BOOT_ROM_AHB_CLK 15
#define GCC_CAMERA_AHB_CLK 16
#define GCC_CAMERA_HF_AXI_CLK 17
#define GCC_CAMERA_SF_AXI_CLK 18
#define GCC_CAMERA_XO_CLK 19
#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 20
#define GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK 21
#define GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK 22
#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 23
#define GCC_CFG_NOC_USB3_MP_AXI_CLK 24
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 25
#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 26
#define GCC_CFG_NOC_USB3_TERT_AXI_CLK 27
#define GCC_CFG_NOC_USB_ANOC_AHB_CLK 28
#define GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK 29
#define GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK 30
#define GCC_CNOC_PCIE1_TUNNEL_CLK 31
#define GCC_CNOC_PCIE2_TUNNEL_CLK 32
#define GCC_CNOC_PCIE_NORTH_SF_AXI_CLK 33
#define GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK 34
#define GCC_CNOC_PCIE_TUNNEL_CLK 35
#define GCC_DDRSS_GPU_AXI_CLK 36
#define GCC_DISP_AHB_CLK 37
#define GCC_DISP_HF_AXI_CLK 38
#define GCC_DISP_XO_CLK 39
#define GCC_GP1_CLK 40
#define GCC_GP1_CLK_SRC 41
#define GCC_GP2_CLK 42
#define GCC_GP2_CLK_SRC 43
#define GCC_GP3_CLK 44
#define GCC_GP3_CLK_SRC 45
#define GCC_GPLL0 46
#define GCC_GPLL0_OUT_EVEN 47
#define GCC_GPLL4 48
#define GCC_GPLL7 49
#define GCC_GPLL8 50
#define GCC_GPLL9 51
#define GCC_GPU_CFG_AHB_CLK 52
#define GCC_GPU_GPLL0_CPH_CLK_SRC 53
#define GCC_GPU_GPLL0_DIV_CPH_CLK_SRC 54
#define GCC_GPU_MEMNOC_GFX_CLK 55
#define GCC_GPU_SNOC_DVM_GFX_CLK 56
#define GCC_PCIE0_PHY_RCHNG_CLK 57
#define GCC_PCIE1_PHY_RCHNG_CLK 58
#define GCC_PCIE2_PHY_RCHNG_CLK 59
#define GCC_PCIE_0_AUX_CLK 60
#define GCC_PCIE_0_AUX_CLK_SRC 61
#define GCC_PCIE_0_CFG_AHB_CLK 62
#define GCC_PCIE_0_MSTR_AXI_CLK 63
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 64
#define GCC_PCIE_0_PIPE_CLK 65
#define GCC_PCIE_0_SLV_AXI_CLK 66
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 67
#define GCC_PCIE_1_AUX_CLK 68
#define GCC_PCIE_1_AUX_CLK_SRC 69
#define GCC_PCIE_1_CFG_AHB_CLK 70
#define GCC_PCIE_1_MSTR_AXI_CLK 71
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 72
#define GCC_PCIE_1_PIPE_CLK 73
#define GCC_PCIE_1_SLV_AXI_CLK 74
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 75
#define GCC_PCIE_2_AUX_CLK 76
#define GCC_PCIE_2_AUX_CLK_SRC 77
#define GCC_PCIE_2_CFG_AHB_CLK 78
#define GCC_PCIE_2_MSTR_AXI_CLK 79
#define GCC_PCIE_2_PHY_RCHNG_CLK_SRC 80
#define GCC_PCIE_2_PIPE_CLK 81
#define GCC_PCIE_2_SLV_AXI_CLK 82
#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 83
#define GCC_PCIE_3_AUX_CLK 84
#define GCC_PCIE_3_AUX_CLK_SRC 85
#define GCC_PCIE_3_CFG_AHB_CLK 86
#define GCC_PCIE_3_MSTR_AXI_CLK 87
#define GCC_PCIE_3_PHY_AUX_CLK 88
#define GCC_PCIE_3_PHY_RCHNG_CLK 89
#define GCC_PCIE_3_PHY_RCHNG_CLK_SRC 90
#define GCC_PCIE_3_PIPE_CLK 91
#define GCC_PCIE_3_PIPE_DIV_CLK_SRC 92
#define GCC_PCIE_3_PIPEDIV2_CLK 93
#define GCC_PCIE_3_SLV_AXI_CLK 94
#define GCC_PCIE_3_SLV_Q2A_AXI_CLK 95
#define GCC_PCIE_4_AUX_CLK 96
#define GCC_PCIE_4_AUX_CLK_SRC 97
#define GCC_PCIE_4_CFG_AHB_CLK 98
#define GCC_PCIE_4_MSTR_AXI_CLK 99
#define GCC_PCIE_4_PHY_RCHNG_CLK 100
#define GCC_PCIE_4_PHY_RCHNG_CLK_SRC 101
#define GCC_PCIE_4_PIPE_CLK 102
#define GCC_PCIE_4_PIPE_DIV_CLK_SRC 103
#define GCC_PCIE_4_PIPEDIV2_CLK 104
#define GCC_PCIE_4_SLV_AXI_CLK 105
#define GCC_PCIE_4_SLV_Q2A_AXI_CLK 106
#define GCC_PCIE_5_AUX_CLK 107
#define GCC_PCIE_5_AUX_CLK_SRC 108
#define GCC_PCIE_5_CFG_AHB_CLK 109
#define GCC_PCIE_5_MSTR_AXI_CLK 110
#define GCC_PCIE_5_PHY_RCHNG_CLK 111
#define GCC_PCIE_5_PHY_RCHNG_CLK_SRC 112
#define GCC_PCIE_5_PIPE_CLK 113
#define GCC_PCIE_5_PIPE_DIV_CLK_SRC 114
#define GCC_PCIE_5_PIPEDIV2_CLK 115
#define GCC_PCIE_5_SLV_AXI_CLK 116
#define GCC_PCIE_5_SLV_Q2A_AXI_CLK 117
#define GCC_PCIE_6A_AUX_CLK 118
#define GCC_PCIE_6A_AUX_CLK_SRC 119
#define GCC_PCIE_6A_CFG_AHB_CLK 120
#define GCC_PCIE_6A_MSTR_AXI_CLK 121
#define GCC_PCIE_6A_PHY_AUX_CLK 122
#define GCC_PCIE_6A_PHY_RCHNG_CLK 123
#define GCC_PCIE_6A_PHY_RCHNG_CLK_SRC 124
#define GCC_PCIE_6A_PIPE_CLK 125
#define GCC_PCIE_6A_PIPE_DIV_CLK_SRC 126
#define GCC_PCIE_6A_PIPEDIV2_CLK 127
#define GCC_PCIE_6A_SLV_AXI_CLK 128
#define GCC_PCIE_6A_SLV_Q2A_AXI_CLK 129
#define GCC_PCIE_6B_AUX_CLK 130
#define GCC_PCIE_6B_AUX_CLK_SRC 131
#define GCC_PCIE_6B_CFG_AHB_CLK 132
#define GCC_PCIE_6B_MSTR_AXI_CLK 133
#define GCC_PCIE_6B_PHY_AUX_CLK 134
#define GCC_PCIE_6B_PHY_RCHNG_CLK 135
#define GCC_PCIE_6B_PHY_RCHNG_CLK_SRC 136
#define GCC_PCIE_6B_PIPE_CLK 137
#define GCC_PCIE_6B_PIPE_DIV_CLK_SRC 138
#define GCC_PCIE_6B_PIPEDIV2_CLK 139
#define GCC_PCIE_6B_SLV_AXI_CLK 140
#define GCC_PCIE_6B_SLV_Q2A_AXI_CLK 141
#define GCC_PCIE_RSCC_AHB_CLK 142
#define GCC_PCIE_RSCC_XO_CLK 143
#define GCC_PCIE_RSCC_XO_CLK_SRC 144
#define GCC_PDM2_CLK 145
#define GCC_PDM2_CLK_SRC 146
#define GCC_PDM_AHB_CLK 147
#define GCC_PDM_XO4_CLK 148
#define GCC_QMIP_AV1E_AHB_CLK 149
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 150
#define GCC_QMIP_CAMERA_RT_AHB_CLK 151
#define GCC_QMIP_DISP_AHB_CLK 152
#define GCC_QMIP_GPU_AHB_CLK 153
#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 154
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 155
#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 156
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 157
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 158
#define GCC_QUPV3_WRAP0_CORE_CLK 159
#define GCC_QUPV3_WRAP0_QSPI_S2_CLK 160
#define GCC_QUPV3_WRAP0_QSPI_S3_CLK 161
#define GCC_QUPV3_WRAP0_S0_CLK 162
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 163
#define GCC_QUPV3_WRAP0_S1_CLK 164
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 165
#define GCC_QUPV3_WRAP0_S2_CLK 166
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 167
#define GCC_QUPV3_WRAP0_S2_DIV_CLK_SRC 168
#define GCC_QUPV3_WRAP0_S3_CLK 169
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 170
#define GCC_QUPV3_WRAP0_S3_DIV_CLK_SRC 171
#define GCC_QUPV3_WRAP0_S4_CLK 172
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 173
#define GCC_QUPV3_WRAP0_S5_CLK 174
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 175
#define GCC_QUPV3_WRAP0_S6_CLK 176
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 177
#define GCC_QUPV3_WRAP0_S7_CLK 178
#define GCC_QUPV3_WRAP0_S7_CLK_SRC 179
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 180
#define GCC_QUPV3_WRAP1_CORE_CLK 181
#define GCC_QUPV3_WRAP1_QSPI_S2_CLK 182
#define GCC_QUPV3_WRAP1_QSPI_S3_CLK 183
#define GCC_QUPV3_WRAP1_S0_CLK 184
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 185
#define GCC_QUPV3_WRAP1_S1_CLK 186
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 187
#define GCC_QUPV3_WRAP1_S2_CLK 188
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 189
#define GCC_QUPV3_WRAP1_S2_DIV_CLK_SRC 190
#define GCC_QUPV3_WRAP1_S3_CLK 191
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 192
#define GCC_QUPV3_WRAP1_S3_DIV_CLK_SRC 193
#define GCC_QUPV3_WRAP1_S4_CLK 194
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 195
#define GCC_QUPV3_WRAP1_S5_CLK 196
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 197
#define GCC_QUPV3_WRAP1_S6_CLK 198
#define GCC_QUPV3_WRAP1_S6_CLK_SRC 199
#define GCC_QUPV3_WRAP1_S7_CLK 200
#define GCC_QUPV3_WRAP1_S7_CLK_SRC 201
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 202
#define GCC_QUPV3_WRAP2_CORE_CLK 203
#define GCC_QUPV3_WRAP2_QSPI_S2_CLK 204
#define GCC_QUPV3_WRAP2_QSPI_S3_CLK 205
#define GCC_QUPV3_WRAP2_S0_CLK 206
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 207
#define GCC_QUPV3_WRAP2_S1_CLK 208
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 209
#define GCC_QUPV3_WRAP2_S2_CLK 210
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 211
#define GCC_QUPV3_WRAP2_S2_DIV_CLK_SRC 212
#define GCC_QUPV3_WRAP2_S3_CLK 213
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 214
#define GCC_QUPV3_WRAP2_S3_DIV_CLK_SRC 215
#define GCC_QUPV3_WRAP2_S4_CLK 216
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 217
#define GCC_QUPV3_WRAP2_S5_CLK 218
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 219
#define GCC_QUPV3_WRAP2_S6_CLK 220
#define GCC_QUPV3_WRAP2_S6_CLK_SRC 221
#define GCC_QUPV3_WRAP2_S7_CLK 222
#define GCC_QUPV3_WRAP2_S7_CLK_SRC 223
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 224
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 225
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 226
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 227
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 228
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 229
#define GCC_SDCC2_AHB_CLK 230
#define GCC_SDCC2_APPS_CLK 231
#define GCC_SDCC2_APPS_CLK_SRC 232
#define GCC_SDCC4_AHB_CLK 233
#define GCC_SDCC4_APPS_CLK 234
#define GCC_SDCC4_APPS_CLK_SRC 235
#define GCC_SYS_NOC_USB_AXI_CLK 236
#define GCC_UFS_PHY_AHB_CLK 237
#define GCC_UFS_PHY_AXI_CLK 238
#define GCC_UFS_PHY_AXI_CLK_SRC 239
#define GCC_UFS_PHY_ICE_CORE_CLK 240
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 241
#define GCC_UFS_PHY_PHY_AUX_CLK 242
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 243
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 244
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 245
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 246
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 247
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 248
#define GCC_USB20_MASTER_CLK 249
#define GCC_USB20_MASTER_CLK_SRC 250
#define GCC_USB20_MOCK_UTMI_CLK 251
#define GCC_USB20_MOCK_UTMI_CLK_SRC 252
#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 253
#define GCC_USB20_SLEEP_CLK 254
#define GCC_USB30_MP_MASTER_CLK 255
#define GCC_USB30_MP_MASTER_CLK_SRC 256
#define GCC_USB30_MP_MOCK_UTMI_CLK 257
#define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 258
#define GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC 259
#define GCC_USB30_MP_SLEEP_CLK 260
#define GCC_USB30_PRIM_MASTER_CLK 261
#define GCC_USB30_PRIM_MASTER_CLK_SRC 262
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 263
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 264
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 265
#define GCC_USB30_PRIM_SLEEP_CLK 266
#define GCC_USB30_SEC_MASTER_CLK 267
#define GCC_USB30_SEC_MASTER_CLK_SRC 268
#define GCC_USB30_SEC_MOCK_UTMI_CLK 269
#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 270
#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 271
#define GCC_USB30_SEC_SLEEP_CLK 272
#define GCC_USB30_TERT_MASTER_CLK 273
#define GCC_USB30_TERT_MASTER_CLK_SRC 274
#define GCC_USB30_TERT_MOCK_UTMI_CLK 275
#define GCC_USB30_TERT_MOCK_UTMI_CLK_SRC 276
#define GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC 277
#define GCC_USB30_TERT_SLEEP_CLK 278
#define GCC_USB3_MP_PHY_AUX_CLK 279
#define GCC_USB3_MP_PHY_AUX_CLK_SRC 280
#define GCC_USB3_MP_PHY_COM_AUX_CLK 281
#define GCC_USB3_MP_PHY_PIPE_0_CLK 282
#define GCC_USB3_MP_PHY_PIPE_1_CLK 283
#define GCC_USB3_PRIM_PHY_AUX_CLK 284
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 285
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 286
#define GCC_USB3_PRIM_PHY_PIPE_CLK 287
#define GCC_USB3_SEC_PHY_AUX_CLK 288
#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 289
#define GCC_USB3_SEC_PHY_COM_AUX_CLK 290
#define GCC_USB3_SEC_PHY_PIPE_CLK 291
#define GCC_USB3_TERT_PHY_AUX_CLK 292
#define GCC_USB3_TERT_PHY_AUX_CLK_SRC 293
#define GCC_USB3_TERT_PHY_COM_AUX_CLK 294
#define GCC_USB3_TERT_PHY_PIPE_CLK 295
#define GCC_USB4_0_CFG_AHB_CLK 296
#define GCC_USB4_0_DP0_CLK 297
#define GCC_USB4_0_DP1_CLK 298
#define GCC_USB4_0_MASTER_CLK 299
#define GCC_USB4_0_MASTER_CLK_SRC 300
#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK 301
#define GCC_USB4_0_PHY_PCIE_PIPE_CLK 302
#define GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC 303
#define GCC_USB4_0_PHY_RX0_CLK 304
#define GCC_USB4_0_PHY_RX1_CLK 305
#define GCC_USB4_0_PHY_USB_PIPE_CLK 306
#define GCC_USB4_0_SB_IF_CLK 307
#define GCC_USB4_0_SB_IF_CLK_SRC 308
#define GCC_USB4_0_SYS_CLK 309
#define GCC_USB4_0_TMU_CLK 310
#define GCC_USB4_0_TMU_CLK_SRC 311
#define GCC_USB4_1_CFG_AHB_CLK 312
#define GCC_USB4_1_DP0_CLK 313
#define GCC_USB4_1_DP1_CLK 314
#define GCC_USB4_1_MASTER_CLK 315
#define GCC_USB4_1_MASTER_CLK_SRC 316
#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK 317
#define GCC_USB4_1_PHY_PCIE_PIPE_CLK 318
#define GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC 319
#define GCC_USB4_1_PHY_RX0_CLK 320
#define GCC_USB4_1_PHY_RX1_CLK 321
#define GCC_USB4_1_PHY_USB_PIPE_CLK 322
#define GCC_USB4_1_SB_IF_CLK 323
#define GCC_USB4_1_SB_IF_CLK_SRC 324
#define GCC_USB4_1_SYS_CLK 325
#define GCC_USB4_1_TMU_CLK 326
#define GCC_USB4_1_TMU_CLK_SRC 327
#define GCC_USB4_2_CFG_AHB_CLK 328
#define GCC_USB4_2_DP0_CLK 329
#define GCC_USB4_2_DP1_CLK 330
#define GCC_USB4_2_MASTER_CLK 331
#define GCC_USB4_2_MASTER_CLK_SRC 332
#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK 333
#define GCC_USB4_2_PHY_PCIE_PIPE_CLK 334
#define GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC 335
#define GCC_USB4_2_PHY_RX0_CLK 336
#define GCC_USB4_2_PHY_RX1_CLK 337
#define GCC_USB4_2_PHY_USB_PIPE_CLK 338
#define GCC_USB4_2_SB_IF_CLK 339
#define GCC_USB4_2_SB_IF_CLK_SRC 340
#define GCC_USB4_2_SYS_CLK 341
#define GCC_USB4_2_TMU_CLK 342
#define GCC_USB4_2_TMU_CLK_SRC 343
#define GCC_VIDEO_AHB_CLK 344
#define GCC_VIDEO_AXI0_CLK 345
#define GCC_VIDEO_AXI1_CLK 346
#define GCC_VIDEO_XO_CLK 347
#define GCC_PCIE_3_PIPE_CLK_SRC 348
#define GCC_PCIE_4_PIPE_CLK_SRC 349
#define GCC_PCIE_5_PIPE_CLK_SRC 350
#define GCC_PCIE_6A_PIPE_CLK_SRC 351
#define GCC_PCIE_6B_PIPE_CLK_SRC 352
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 353
#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 354
#define GCC_USB3_TERT_PHY_PIPE_CLK_SRC 355
/* GCC power domains */
#define GCC_PCIE_0_TUNNEL_GDSC 0
#define GCC_PCIE_1_TUNNEL_GDSC 1
#define GCC_PCIE_2_TUNNEL_GDSC 2
#define GCC_PCIE_3_GDSC 3
#define GCC_PCIE_3_PHY_GDSC 4
#define GCC_PCIE_4_GDSC 5
#define GCC_PCIE_4_PHY_GDSC 6
#define GCC_PCIE_5_GDSC 7
#define GCC_PCIE_5_PHY_GDSC 8
#define GCC_PCIE_6_PHY_GDSC 9
#define GCC_PCIE_6A_GDSC 10
#define GCC_PCIE_6B_GDSC 11
#define GCC_UFS_MEM_PHY_GDSC 12
#define GCC_UFS_PHY_GDSC 13
#define GCC_USB20_PRIM_GDSC 14
#define GCC_USB30_MP_GDSC 15
#define GCC_USB30_PRIM_GDSC 16
#define GCC_USB30_SEC_GDSC 17
#define GCC_USB30_TERT_GDSC 18
#define GCC_USB3_MP_SS0_PHY_GDSC 19
#define GCC_USB3_MP_SS1_PHY_GDSC 20
#define GCC_USB4_0_GDSC 21
#define GCC_USB4_1_GDSC 22
#define GCC_USB4_2_GDSC 23
#define GCC_USB_0_PHY_GDSC 24
#define GCC_USB_1_PHY_GDSC 25
#define GCC_USB_2_PHY_GDSC 26
/* GCC resets */
#define GCC_AV1E_BCR 0
#define GCC_CAMERA_BCR 1
#define GCC_DISPLAY_BCR 2
#define GCC_GPU_BCR 3
#define GCC_PCIE_0_LINK_DOWN_BCR 4
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5
#define GCC_PCIE_0_PHY_BCR 6
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7
#define GCC_PCIE_0_TUNNEL_BCR 8
#define GCC_PCIE_1_LINK_DOWN_BCR 9
#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10
#define GCC_PCIE_1_PHY_BCR 11
#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12
#define GCC_PCIE_1_TUNNEL_BCR 13
#define GCC_PCIE_2_LINK_DOWN_BCR 14
#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 15
#define GCC_PCIE_2_PHY_BCR 16
#define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR 17
#define GCC_PCIE_2_TUNNEL_BCR 18
#define GCC_PCIE_3_BCR 19
#define GCC_PCIE_3_LINK_DOWN_BCR 20
#define GCC_PCIE_3_NOCSR_COM_PHY_BCR 21
#define GCC_PCIE_3_PHY_BCR 22
#define GCC_PCIE_3_PHY_NOCSR_COM_PHY_BCR 23
#define GCC_PCIE_4_BCR 24
#define GCC_PCIE_4_LINK_DOWN_BCR 25
#define GCC_PCIE_4_NOCSR_COM_PHY_BCR 26
#define GCC_PCIE_4_PHY_BCR 27
#define GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR 28
#define GCC_PCIE_5_BCR 29
#define GCC_PCIE_5_LINK_DOWN_BCR 30
#define GCC_PCIE_5_NOCSR_COM_PHY_BCR 31
#define GCC_PCIE_5_PHY_BCR 32
#define GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR 33
#define GCC_PCIE_6A_BCR 34
#define GCC_PCIE_6A_LINK_DOWN_BCR 35
#define GCC_PCIE_6A_NOCSR_COM_PHY_BCR 36
#define GCC_PCIE_6A_PHY_BCR 37
#define GCC_PCIE_6A_PHY_NOCSR_COM_PHY_BCR 38
#define GCC_PCIE_6B_BCR 39
#define GCC_PCIE_6B_LINK_DOWN_BCR 40
#define GCC_PCIE_6B_NOCSR_COM_PHY_BCR 41
#define GCC_PCIE_6B_PHY_BCR 42
#define GCC_PCIE_6B_PHY_NOCSR_COM_PHY_BCR 43
#define GCC_PCIE_PHY_BCR 44
#define GCC_PCIE_PHY_CFG_AHB_BCR 45
#define GCC_PCIE_PHY_COM_BCR 46
#define GCC_PCIE_RSCC_BCR 47
#define GCC_PDM_BCR 48
#define GCC_QUPV3_WRAPPER_0_BCR 49
#define GCC_QUPV3_WRAPPER_1_BCR 50
#define GCC_QUPV3_WRAPPER_2_BCR 51
#define GCC_QUSB2PHY_HS0_MP_BCR 52
#define GCC_QUSB2PHY_HS1_MP_BCR 53
#define GCC_QUSB2PHY_PRIM_BCR 54
#define GCC_QUSB2PHY_SEC_BCR 55
#define GCC_QUSB2PHY_TERT_BCR 56
#define GCC_QUSB2PHY_USB20_HS_BCR 57
#define GCC_SDCC2_BCR 58
#define GCC_SDCC4_BCR 59
#define GCC_UFS_PHY_BCR 60
#define GCC_USB20_PRIM_BCR 61
#define GCC_USB30_MP_BCR 62
#define GCC_USB30_PRIM_BCR 63
#define GCC_USB30_SEC_BCR 64
#define GCC_USB30_TERT_BCR 65
#define GCC_USB3_MP_SS0_PHY_BCR 66
#define GCC_USB3_MP_SS1_PHY_BCR 67
#define GCC_USB3_PHY_PRIM_BCR 68
#define GCC_USB3_PHY_SEC_BCR 69
#define GCC_USB3_PHY_TERT_BCR 70
#define GCC_USB3_UNIPHY_MP0_BCR 71
#define GCC_USB3_UNIPHY_MP1_BCR 72
#define GCC_USB3PHY_PHY_PRIM_BCR 73
#define GCC_USB3PHY_PHY_SEC_BCR 74
#define GCC_USB3PHY_PHY_TERT_BCR 75
#define GCC_USB3UNIPHY_PHY_MP0_BCR 76
#define GCC_USB3UNIPHY_PHY_MP1_BCR 77
#define GCC_USB4_0_BCR 78
#define GCC_USB4_0_DP0_PHY_PRIM_BCR 79
#define GCC_USB4_1_DP0_PHY_SEC_BCR 80
#define GCC_USB4_2_DP0_PHY_TERT_BCR 81
#define GCC_USB4_1_BCR 82
#define GCC_USB4_2_BCR 83
#define GCC_USB_0_PHY_BCR 84
#define GCC_USB_1_PHY_BCR 85
#define GCC_USB_2_PHY_BCR 86
#define GCC_VIDEO_BCR 87
#endif

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include/dt-bindings/reset/mediatek,mt7988-resets.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org>
* Author: Daniel Golle <daniel@makrotopia.org>
*/
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7988
#define _DT_BINDINGS_RESET_CONTROLLER_MT7988
/* ETHWARP resets */
#define MT7988_ETHWARP_RST_SWITCH 0
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */

20
include/dt-bindings/reset/qcom,sm8650-gpucc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#ifndef _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8650_H
#define _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8650_H
#define GPUCC_GPU_CC_ACD_BCR 0
#define GPUCC_GPU_CC_CX_BCR 1
#define GPUCC_GPU_CC_FAST_HUB_BCR 2
#define GPUCC_GPU_CC_FF_BCR 3
#define GPUCC_GPU_CC_GFX3D_AON_BCR 4
#define GPUCC_GPU_CC_GMU_BCR 5
#define GPUCC_GPU_CC_GX_BCR 6
#define GPUCC_GPU_CC_XO_BCR 7
#define GPUCC_GPU_CC_GX_ACD_IROOT_BCR 8
#endif