pinctrl: renesas: sh7757: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 115 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/05c69ca8710134bb96ec8f7d18bafe42418f3510.1649865241.git.geert+renesas@glider.be
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@ -1963,43 +1963,35 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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0, 0,
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0, 0, ))
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},
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{ PINMUX_CFG_REG("PSEL1", 0xffec0072, 16, 1, GROUP(
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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{ PINMUX_CFG_REG_VAR("PSEL1", 0xffec0072, 16,
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GROUP(-5, 1, 1, 1, -5, 1, -2),
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GROUP(
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/* RESERVED [5] */
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PS1_10_FN1, PS1_10_FN2,
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PS1_9_FN1, PS1_9_FN2,
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PS1_8_FN1, PS1_8_FN2,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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/* RESERVED [5] */
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PS1_2_FN1, PS1_2_FN2,
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0, 0,
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0, 0, ))
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/* RESERVED [2] */ ))
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},
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{ PINMUX_CFG_REG("PSEL2", 0xffec0074, 16, 1, GROUP(
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0, 0,
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0, 0,
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{ PINMUX_CFG_REG_VAR("PSEL2", 0xffec0074, 16,
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GROUP(-2, 1, 1, -4, 1, 1, 1, 1, -1, 1, -2),
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GROUP(
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/* RESERVED [2] */
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PS2_13_FN1, PS2_13_FN2,
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PS2_12_FN1, PS2_12_FN2,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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/* RESERVED [4] */
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PS2_7_FN1, PS2_7_FN2,
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PS2_6_FN1, PS2_6_FN2,
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PS2_5_FN1, PS2_5_FN2,
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PS2_4_FN1, PS2_4_FN2,
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0, 0,
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/* RESERVED [1] */
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PS2_2_FN1, PS2_2_FN2,
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0, 0,
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0, 0, ))
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/* RESERVED [2] */ ))
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},
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{ PINMUX_CFG_REG("PSEL3", 0xffec0076, 16, 1, GROUP(
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{ PINMUX_CFG_REG_VAR("PSEL3", 0xffec0076, 16,
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GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, -4, 1, 1, -1),
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GROUP(
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PS3_15_FN1, PS3_15_FN2,
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PS3_14_FN1, PS3_14_FN2,
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PS3_13_FN1, PS3_13_FN2,
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@ -2009,38 +2001,35 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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PS3_9_FN1, PS3_9_FN2,
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PS3_8_FN1, PS3_8_FN2,
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PS3_7_FN1, PS3_7_FN2,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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/* RESERVED [4] */
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PS3_2_FN1, PS3_2_FN2,
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PS3_1_FN1, PS3_1_FN2,
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0, 0, ))
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/* RESERVED [1] */ ))
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},
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{ PINMUX_CFG_REG("PSEL4", 0xffec0078, 16, 1, GROUP(
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0, 0,
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{ PINMUX_CFG_REG_VAR("PSEL4", 0xffec0078, 16,
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GROUP(-1, 1, 1, 1, -1, 1, 1, 1, -3, 1, 1, 1,
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1, 1),
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GROUP(
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/* RESERVED [1] */
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PS4_14_FN1, PS4_14_FN2,
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PS4_13_FN1, PS4_13_FN2,
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PS4_12_FN1, PS4_12_FN2,
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0, 0,
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/* RESERVED [1] */
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PS4_10_FN1, PS4_10_FN2,
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PS4_9_FN1, PS4_9_FN2,
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PS4_8_FN1, PS4_8_FN2,
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0, 0,
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0, 0,
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0, 0,
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/* RESERVED [3] */
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PS4_4_FN1, PS4_4_FN2,
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PS4_3_FN1, PS4_3_FN2,
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PS4_2_FN1, PS4_2_FN2,
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PS4_1_FN1, PS4_1_FN2,
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PS4_0_FN1, PS4_0_FN2, ))
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},
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{ PINMUX_CFG_REG("PSEL5", 0xffec007a, 16, 1, GROUP(
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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{ PINMUX_CFG_REG_VAR("PSEL5", 0xffec007a, 16,
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GROUP(-4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, -2),
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GROUP(
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/* RESERVED [4] */
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PS5_11_FN1, PS5_11_FN2,
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PS5_10_FN1, PS5_10_FN2,
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PS5_9_FN1, PS5_9_FN2,
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@ -2051,8 +2040,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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PS5_4_FN1, PS5_4_FN2,
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PS5_3_FN1, PS5_3_FN2,
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PS5_2_FN1, PS5_2_FN2,
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0, 0,
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0, 0, ))
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/* RESERVED [2] */ ))
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},
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{ PINMUX_CFG_REG("PSEL6", 0xffec007c, 16, 1, GROUP(
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PS6_15_FN1, PS6_15_FN2,
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@ -2072,7 +2060,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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PS6_1_FN1, PS6_1_FN2,
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PS6_0_FN1, PS6_0_FN2, ))
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},
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{ PINMUX_CFG_REG("PSEL7", 0xffec0082, 16, 1, GROUP(
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{ PINMUX_CFG_REG_VAR("PSEL7", 0xffec0082, 16,
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GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, -5),
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GROUP(
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PS7_15_FN1, PS7_15_FN2,
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PS7_14_FN1, PS7_14_FN2,
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PS7_13_FN1, PS7_13_FN2,
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@ -2084,13 +2074,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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PS7_7_FN1, PS7_7_FN2,
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PS7_6_FN1, PS7_6_FN2,
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PS7_5_FN1, PS7_5_FN2,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0, ))
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/* RESERVED [5] */ ))
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},
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{ PINMUX_CFG_REG("PSEL8", 0xffec0084, 16, 1, GROUP(
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{ PINMUX_CFG_REG_VAR("PSEL8", 0xffec0084, 16,
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GROUP(1, 1, 1, 1, 1, 1, 1, 1, -8),
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GROUP(
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PS8_15_FN1, PS8_15_FN2,
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PS8_14_FN1, PS8_14_FN2,
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PS8_13_FN1, PS8_13_FN2,
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@ -2099,14 +2087,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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PS8_10_FN1, PS8_10_FN2,
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PS8_9_FN1, PS8_9_FN2,
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PS8_8_FN1, PS8_8_FN2,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0, ))
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/* RESERVED [8] */ ))
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},
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{}
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};
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