clk: sifive: Add SoCs prefix in each SoCs-dependent data
This patch is prerequisite for moving SoCs C files into SoCs header files. Currently, fu540-prci.c and fu740-prci.c use same names for several macro definitions and variables, it would cause redefinition error when we trying to include all stuff in sifive-prci.c. In this patch, we also remove the temporary macro definitions which are added by previous patch. Signed-off-by: Zong Li <zong.li@sifive.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/7728ef662c59449ce954b1b62c6ad5241e07adfb.1646388139.git.zong.li@sifive.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Zong Li
Stephen Boyd
parent
990d627f80
commit
24a4a29f75
@ -1,9 +1,9 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018-2019 SiFive, Inc.
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* Copyright (C) 2018-2022 SiFive, Inc.
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* Copyright (C) 2018-2019 Wesley Terpstra
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* Copyright (C) 2018-2019 Paul Walmsley
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* Copyright (C) 2020 Zong Li
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* Copyright (C) 2020-2022 Zong Li
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*
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* The FU540 PRCI implements clock and reset control for the SiFive
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* FU540-C000 chip. This driver assumes that it has sole control
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@ -22,26 +22,21 @@
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#include "sifive-prci.h"
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#define PRCI_CLK_COREPLL 0
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#define PRCI_CLK_DDRPLL 1
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#define PRCI_CLK_GEMGXLPLL 2
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#define PRCI_CLK_TLCLK 3
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/* PRCI integration data for each WRPLL instance */
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static struct __prci_wrpll_data __prci_corepll_data = {
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static struct __prci_wrpll_data sifive_fu540_prci_corepll_data = {
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.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
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.enable_bypass = sifive_prci_coreclksel_use_hfclk,
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.disable_bypass = sifive_prci_coreclksel_use_corepll,
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};
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static struct __prci_wrpll_data __prci_ddrpll_data = {
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static struct __prci_wrpll_data sifive_fu540_prci_ddrpll_data = {
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.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
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};
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static struct __prci_wrpll_data __prci_gemgxlpll_data = {
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static struct __prci_wrpll_data sifive_fu540_prci_gemgxlpll_data = {
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.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
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};
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@ -67,25 +62,25 @@ static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops = {
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/* List of clock controls provided by the PRCI */
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struct __prci_clock __prci_init_clocks_fu540[] = {
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[PRCI_CLK_COREPLL] = {
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[FU540_PRCI_CLK_COREPLL] = {
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.name = "corepll",
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.parent_name = "hfclk",
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.ops = &sifive_fu540_prci_wrpll_clk_ops,
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.pwd = &__prci_corepll_data,
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.pwd = &sifive_fu540_prci_corepll_data,
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},
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[PRCI_CLK_DDRPLL] = {
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[FU540_PRCI_CLK_DDRPLL] = {
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.name = "ddrpll",
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.parent_name = "hfclk",
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.ops = &sifive_fu540_prci_wrpll_ro_clk_ops,
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.pwd = &__prci_ddrpll_data,
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.pwd = &sifive_fu540_prci_ddrpll_data,
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},
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[PRCI_CLK_GEMGXLPLL] = {
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[FU540_PRCI_CLK_GEMGXLPLL] = {
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.name = "gemgxlpll",
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.parent_name = "hfclk",
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.ops = &sifive_fu540_prci_wrpll_clk_ops,
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.pwd = &__prci_gemgxlpll_data,
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.pwd = &sifive_fu540_prci_gemgxlpll_data,
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},
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[PRCI_CLK_TLCLK] = {
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[FU540_PRCI_CLK_TLCLK] = {
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.name = "tlclk",
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.parent_name = "corepll",
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.ops = &sifive_fu540_prci_tlclksel_clk_ops,
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@ -1,7 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 SiFive, Inc.
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* Copyright (C) 2020 Zong Li
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* Copyright (C) 2020-2022 SiFive, Inc.
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* Copyright (C) 2020-2022 Zong Li
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*/
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#include <linux/module.h>
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@ -10,50 +10,40 @@
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#include "sifive-prci.h"
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#define PRCI_CLK_COREPLL 0
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#define PRCI_CLK_DDRPLL 1
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#define PRCI_CLK_GEMGXLPLL 2
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#define PRCI_CLK_DVFSCOREPLL 3
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#define PRCI_CLK_HFPCLKPLL 4
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#define PRCI_CLK_CLTXPLL 5
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#define PRCI_CLK_TLCLK 6
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#define PRCI_CLK_PCLK 7
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#define PRCI_CLK_PCIE_AUX 8
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/* PRCI integration data for each WRPLL instance */
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static struct __prci_wrpll_data __prci_corepll_data = {
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static struct __prci_wrpll_data sifive_fu740_prci_corepll_data = {
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.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
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.enable_bypass = sifive_prci_coreclksel_use_hfclk,
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.disable_bypass = sifive_prci_coreclksel_use_final_corepll,
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};
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static struct __prci_wrpll_data __prci_ddrpll_data = {
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static struct __prci_wrpll_data sifive_fu740_prci_ddrpll_data = {
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.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
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};
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static struct __prci_wrpll_data __prci_gemgxlpll_data = {
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static struct __prci_wrpll_data sifive_fu740_prci_gemgxlpll_data = {
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.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
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};
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static struct __prci_wrpll_data __prci_dvfscorepll_data = {
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static struct __prci_wrpll_data sifive_fu740_prci_dvfscorepll_data = {
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.cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_DVFSCOREPLLCFG1_OFFSET,
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.enable_bypass = sifive_prci_corepllsel_use_corepll,
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.disable_bypass = sifive_prci_corepllsel_use_dvfscorepll,
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};
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static struct __prci_wrpll_data __prci_hfpclkpll_data = {
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static struct __prci_wrpll_data sifive_fu740_prci_hfpclkpll_data = {
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.cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_HFPCLKPLLCFG1_OFFSET,
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.enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk,
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.disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll,
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};
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static struct __prci_wrpll_data __prci_cltxpll_data = {
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static struct __prci_wrpll_data sifive_fu740_prci_cltxpll_data = {
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.cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET,
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};
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@ -89,53 +79,53 @@ static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = {
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/* List of clock controls provided by the PRCI */
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struct __prci_clock __prci_init_clocks_fu740[] = {
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[PRCI_CLK_COREPLL] = {
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[FU740_PRCI_CLK_COREPLL] = {
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.name = "corepll",
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.parent_name = "hfclk",
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.ops = &sifive_fu740_prci_wrpll_clk_ops,
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.pwd = &__prci_corepll_data,
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.pwd = &sifive_fu740_prci_corepll_data,
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},
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[PRCI_CLK_DDRPLL] = {
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[FU740_PRCI_CLK_DDRPLL] = {
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.name = "ddrpll",
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.parent_name = "hfclk",
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.ops = &sifive_fu740_prci_wrpll_ro_clk_ops,
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.pwd = &__prci_ddrpll_data,
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.pwd = &sifive_fu740_prci_ddrpll_data,
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},
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[PRCI_CLK_GEMGXLPLL] = {
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[FU740_PRCI_CLK_GEMGXLPLL] = {
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.name = "gemgxlpll",
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.parent_name = "hfclk",
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.ops = &sifive_fu740_prci_wrpll_clk_ops,
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.pwd = &__prci_gemgxlpll_data,
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.pwd = &sifive_fu740_prci_gemgxlpll_data,
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},
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[PRCI_CLK_DVFSCOREPLL] = {
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[FU740_PRCI_CLK_DVFSCOREPLL] = {
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.name = "dvfscorepll",
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.parent_name = "hfclk",
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.ops = &sifive_fu740_prci_wrpll_clk_ops,
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.pwd = &__prci_dvfscorepll_data,
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.pwd = &sifive_fu740_prci_dvfscorepll_data,
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},
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[PRCI_CLK_HFPCLKPLL] = {
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[FU740_PRCI_CLK_HFPCLKPLL] = {
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.name = "hfpclkpll",
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.parent_name = "hfclk",
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.ops = &sifive_fu740_prci_wrpll_clk_ops,
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.pwd = &__prci_hfpclkpll_data,
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.pwd = &sifive_fu740_prci_hfpclkpll_data,
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},
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[PRCI_CLK_CLTXPLL] = {
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[FU740_PRCI_CLK_CLTXPLL] = {
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.name = "cltxpll",
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.parent_name = "hfclk",
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.ops = &sifive_fu740_prci_wrpll_clk_ops,
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.pwd = &__prci_cltxpll_data,
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.pwd = &sifive_fu740_prci_cltxpll_data,
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},
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[PRCI_CLK_TLCLK] = {
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[FU740_PRCI_CLK_TLCLK] = {
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.name = "tlclk",
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.parent_name = "corepll",
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.ops = &sifive_fu740_prci_tlclksel_clk_ops,
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},
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[PRCI_CLK_PCLK] = {
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[FU740_PRCI_CLK_PCLK] = {
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.name = "pclk",
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.parent_name = "hfpclkpll",
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.ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
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},
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[PRCI_CLK_PCIE_AUX] = {
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[FU740_PRCI_CLK_PCIE_AUX] = {
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.name = "pcie_aux",
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.parent_name = "hfclk",
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.ops = &sifive_fu740_prci_pcie_aux_clk_ops,
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