dt-bindings: PCI: layerscape-pci: Convert to YAML format
Convert layerscape PCIe bind document to the preferred YAML format. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/20240207231550.2663689-1-Frank.Li@nxp.com Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
This commit is contained in:
Frank Li
Krzysztof Wilczyński
parent
d3fa4be903
commit
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie-ep.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale Layerscape PCIe Endpoint(EP) controller
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maintainers:
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- Frank Li <Frank.Li@nxp.com>
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description:
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This PCIe EP controller is based on the Synopsys DesignWare PCIe IP.
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This controller derives its clocks from the Reset Configuration Word (RCW)
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which is used to describe the PLL settings at the time of chip-reset.
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Also as per the available Reference Manuals, there is no specific 'version'
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register available in the Freescale PCIe controller register set,
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which can allow determining the underlying DesignWare PCIe controller version
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information.
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properties:
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compatible:
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enum:
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- fsl,ls2088a-pcie-ep
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- fsl,ls1088a-pcie-ep
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- fsl,ls1046a-pcie-ep
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- fsl,ls1028a-pcie-ep
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- fsl,lx2160ar2-pcie-ep
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reg:
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maxItems: 2
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reg-names:
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items:
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- const: regs
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- const: addr_space
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fsl,pcie-scfg:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: A phandle to the SCFG device node. The second entry is the
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physical PCIe controller index starting from '0'. This is used to get
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SCFG PEXN registers.
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big-endian:
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$ref: /schemas/types.yaml#/definitions/flag
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description: If the PEX_LUT and PF register block is in big-endian, specify
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this property.
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dma-coherent: true
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interrupts:
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minItems: 1
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maxItems: 2
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interrupt-names:
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minItems: 1
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maxItems: 2
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required:
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- compatible
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- reg
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- reg-names
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allOf:
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- if:
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properties:
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compatible:
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enum:
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- fsl,ls1028a-pcie-ep
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- fsl,ls1046a-pcie-ep
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- fsl,ls1088a-pcie-ep
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then:
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properties:
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interrupt-names:
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items:
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- const: pme
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie_ep1: pcie-ep@3400000 {
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compatible = "fsl,ls1028a-pcie-ep";
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reg = <0x00 0x03400000 0x0 0x00100000
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0x80 0x00000000 0x8 0x00000000>;
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reg-names = "regs", "addr_space";
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
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interrupt-names = "pme";
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num-ib-windows = <6>;
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num-ob-windows = <8>;
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status = "disabled";
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};
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};
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...
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167
Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
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167
Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
Normal file
@ -0,0 +1,167 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale Layerscape PCIe Root Complex(RC) controller
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maintainers:
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- Frank Li <Frank.Li@nxp.com>
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description:
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This PCIe RC controller is based on the Synopsys DesignWare PCIe IP
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This controller derives its clocks from the Reset Configuration Word (RCW)
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which is used to describe the PLL settings at the time of chip-reset.
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Also as per the available Reference Manuals, there is no specific 'version'
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register available in the Freescale PCIe controller register set,
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which can allow determining the underlying DesignWare PCIe controller version
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information.
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properties:
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compatible:
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enum:
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- fsl,ls1021a-pcie
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- fsl,ls2080a-pcie
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- fsl,ls2085a-pcie
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- fsl,ls2088a-pcie
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- fsl,ls1088a-pcie
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- fsl,ls1046a-pcie
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- fsl,ls1043a-pcie
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- fsl,ls1012a-pcie
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- fsl,ls1028a-pcie
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- fsl,lx2160a-pcie
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reg:
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maxItems: 2
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reg-names:
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items:
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- const: regs
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- const: config
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fsl,pcie-scfg:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: A phandle to the SCFG device node. The second entry is the
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physical PCIe controller index starting from '0'. This is used to get
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SCFG PEXN registers.
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big-endian:
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$ref: /schemas/types.yaml#/definitions/flag
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description: If the PEX_LUT and PF register block is in big-endian, specify
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this property.
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dma-coherent: true
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msi-parent: true
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iommu-map: true
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interrupts:
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minItems: 1
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maxItems: 2
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interrupt-names:
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minItems: 1
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maxItems: 2
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required:
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- compatible
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- reg
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- reg-names
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- "#address-cells"
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- "#size-cells"
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- device_type
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- bus-range
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- ranges
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- interrupts
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- interrupt-names
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- "#interrupt-cells"
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- interrupt-map-mask
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- interrupt-map
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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- if:
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properties:
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compatible:
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enum:
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- fsl,ls1028a-pcie
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- fsl,ls1046a-pcie
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- fsl,ls1043a-pcie
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- fsl,ls1012a-pcie
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then:
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properties:
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interrupts:
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maxItems: 2
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interrupt-names:
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items:
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- const: pme
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- const: aer
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- if:
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properties:
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compatible:
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enum:
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- fsl,ls2080a-pcie
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- fsl,ls2085a-pcie
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- fsl,ls2088a-pcie
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then:
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properties:
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interrupts:
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maxItems: 1
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interrupt-names:
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items:
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- const: intr
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- if:
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properties:
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compatible:
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enum:
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- fsl,ls1088a-pcie
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then:
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properties:
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interrupts:
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maxItems: 1
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interrupt-names:
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items:
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- const: aer
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@3400000 {
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compatible = "fsl,ls1088a-pcie";
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reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
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<0x20 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
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interrupt-names = "aer";
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#address-cells = <3>;
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#size-cells = <2>;
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dma-coherent;
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device_type = "pci";
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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msi-parent = <&its>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
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iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
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};
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};
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...
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@ -1,79 +0,0 @@
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Freescale Layerscape PCIe controller
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This PCIe host controller is based on the Synopsys DesignWare PCIe IP
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and thus inherits all the common properties defined in snps,dw-pcie.yaml.
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This controller derives its clocks from the Reset Configuration Word (RCW)
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which is used to describe the PLL settings at the time of chip-reset.
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Also as per the available Reference Manuals, there is no specific 'version'
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register available in the Freescale PCIe controller register set,
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which can allow determining the underlying DesignWare PCIe controller version
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information.
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Required properties:
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- compatible: should contain the platform identifier such as:
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RC mode:
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"fsl,ls1021a-pcie"
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"fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
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"fsl,ls2088a-pcie"
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"fsl,ls1088a-pcie"
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"fsl,ls1046a-pcie"
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"fsl,ls1043a-pcie"
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"fsl,ls1012a-pcie"
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"fsl,ls1028a-pcie"
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EP mode:
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"fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep"
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"fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"
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"fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"
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"fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep"
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"fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep"
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- reg: base addresses and lengths of the PCIe controller register blocks.
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- interrupts: A list of interrupt outputs of the controller. Must contain an
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entry for each entry in the interrupt-names property.
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- interrupt-names: It could include the following entries:
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"aer": Used for interrupt line which reports AER events when
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non MSI/MSI-X/INTx mode is used
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"pme": Used for interrupt line which reports PME events when
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non MSI/MSI-X/INTx mode is used
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"intr": Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a)
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which has a single interrupt line for miscellaneous controller
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events(could include AER and PME events).
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- fsl,pcie-scfg: Must include two entries.
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The first entry must be a link to the SCFG device node
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The second entry is the physical PCIe controller index starting from '0'.
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This is used to get SCFG PEXN registers
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- dma-coherent: Indicates that the hardware IP block can ensure the coherency
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of the data transferred from/to the IP block. This can avoid the software
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cache flush/invalid actions, and improve the performance significantly.
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Optional properties:
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- big-endian: If the PEX_LUT and PF register block is in big-endian, specify
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this property.
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Example:
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pcie@3400000 {
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compatible = "fsl,ls1088a-pcie";
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reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
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<0x20 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
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interrupt-names = "aer";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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dma-coherent;
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num-viewport = <256>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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msi-parent = <&its>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
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iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
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};
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