Pin control fixes for v6.7:
- Ignore disabled device tree nodes in the Starfive 7100 and
7100 drivers.
- Mask non-wake source pins with interrupt enabled at suspend
in the AMD driver, this blocks unnecessary wakeups from misc
interrupts. This can be power consuming because in many cases
the system doesn't really suspend, it just wakes right back
up.
- Fix a typo breaking compilation of the cy8c95x0 driver, and
fix up bugs in the get/set config callbacks.
- Use a dedicated lock class for the PIO4 drivers IRQ.
This fixes a crash on suspend.
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Merge tag 'pinctrl-v6.7-4' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij:
"Some driver fixes for v6.7, all are in drivers, the most interesting
one is probably the AMD laptop suspend bug which really needs fixing.
Freedestop org has the bug description:
https://gitlab.freedesktop.org/drm/amd/-/issues/2812
Summary:
- Ignore disabled device tree nodes in the Starfive 7100 and 7100
drivers.
- Mask non-wake source pins with interrupt enabled at suspend in the
AMD driver, this blocks unnecessary wakeups from misc interrupts.
This can be power consuming because in many cases the system
doesn't really suspend, it just wakes right back up.
- Fix a typo breaking compilation of the cy8c95x0 driver, and fix up
bugs in the get/set config callbacks.
- Use a dedicated lock class for the PIO4 drivers IRQ. This fixes a
crash on suspend"
* tag 'pinctrl-v6.7-4' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinctrl: at91-pio4: use dedicated lock class for IRQ
pinctrl: cy8c95x0: Fix get_pincfg
pinctrl: cy8c95x0: Fix regression
pinctrl: cy8c95x0: Fix typo
pinctrl: amd: Mask non-wake source pins with interrupt enabled at suspend
pinctrl: starfive: jh7100: ignore disabled device tree nodes
pinctrl: starfive: jh7110: ignore disabled device tree nodes
This commit is contained in:
Linus Torvalds
commit
24e0d2e527
@ -923,6 +923,15 @@ static int amd_gpio_suspend(struct device *dev)
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raw_spin_lock_irqsave(&gpio_dev->lock, flags);
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gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING;
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/* mask any interrupts not intended to be a wake source */
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if (!(gpio_dev->saved_regs[i] & WAKE_SOURCE)) {
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writel(gpio_dev->saved_regs[i] & ~BIT(INTERRUPT_MASK_OFF),
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gpio_dev->base + pin * 4);
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pm_pr_dbg("Disabling GPIO #%d interrupt for suspend.\n",
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pin);
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}
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raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
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}
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@ -80,6 +80,11 @@
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#define FUNCTION_MASK GENMASK(1, 0)
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#define FUNCTION_INVALID GENMASK(7, 0)
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#define WAKE_SOURCE (BIT(WAKE_CNTRL_OFF_S0I3) | \
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BIT(WAKE_CNTRL_OFF_S3) | \
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BIT(WAKE_CNTRL_OFF_S4) | \
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BIT(WAKECNTRL_Z_OFF))
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struct amd_function {
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const char *name;
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const char * const groups[NSELECTS];
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@ -1068,6 +1068,13 @@ static const struct of_device_id atmel_pctrl_of_match[] = {
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}
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};
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/*
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* This lock class allows to tell lockdep that parent IRQ and children IRQ do
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* not share the same class so it does not raise false positive
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*/
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static struct lock_class_key atmel_lock_key;
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static struct lock_class_key atmel_request_key;
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static int atmel_pinctrl_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@ -1214,6 +1221,7 @@ static int atmel_pinctrl_probe(struct platform_device *pdev)
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irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip,
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handle_simple_irq);
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irq_set_chip_data(irq, atmel_pioctrl);
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irq_set_lockdep_class(irq, &atmel_lock_key, &atmel_request_key);
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dev_dbg(dev,
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"atmel gpio irq domain: hwirq: %d, linux irq: %d\n",
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i, irq);
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@ -308,6 +308,9 @@ static const char * const cy8c95x0_groups[] = {
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"gp77",
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};
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static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip,
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unsigned int pin, bool input);
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static inline u8 cypress_get_port(struct cy8c95x0_pinctrl *chip, unsigned int pin)
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{
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/* Account for GPORT2 which only has 4 bits */
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@ -712,6 +715,8 @@ static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip,
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ret = regmap_read(chip->regmap, reg, ®_val);
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if (reg_val & bit)
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arg = 1;
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if (param == PIN_CONFIG_OUTPUT_ENABLE)
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arg = !arg;
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*config = pinconf_to_config_packed(param, (u16)arg);
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out:
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@ -727,6 +732,7 @@ static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip,
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u8 port = cypress_get_port(chip, off);
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u8 bit = cypress_get_pin_mask(chip, off);
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unsigned long param = pinconf_to_config_param(config);
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unsigned long arg = pinconf_to_config_argument(config);
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unsigned int reg;
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int ret;
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@ -765,6 +771,12 @@ static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip,
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case PIN_CONFIG_MODE_PWM:
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reg = CY8C95X0_PWMSEL;
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break;
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case PIN_CONFIG_OUTPUT_ENABLE:
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ret = cy8c95x0_pinmux_direction(chip, off, !arg);
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goto out;
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case PIN_CONFIG_INPUT_ENABLE:
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ret = cy8c95x0_pinmux_direction(chip, off, arg);
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goto out;
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default:
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ret = -ENOTSUPP;
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goto out;
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@ -822,7 +834,7 @@ static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip)
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gc->get_direction = cy8c95x0_gpio_get_direction;
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gc->get_multiple = cy8c95x0_gpio_get_multiple;
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gc->set_multiple = cy8c95x0_gpio_set_multiple;
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gc->set_config = gpiochip_generic_config,
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gc->set_config = gpiochip_generic_config;
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gc->can_sleep = true;
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gc->add_pin_ranges = cy8c95x0_add_pin_ranges;
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@ -492,7 +492,7 @@ static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
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nmaps = 0;
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ngroups = 0;
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for_each_child_of_node(np, child) {
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for_each_available_child_of_node(np, child) {
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int npinmux = of_property_count_u32_elems(child, "pinmux");
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int npins = of_property_count_u32_elems(child, "pins");
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@ -527,7 +527,7 @@ static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
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nmaps = 0;
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ngroups = 0;
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mutex_lock(&sfp->mutex);
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for_each_child_of_node(np, child) {
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for_each_available_child_of_node(np, child) {
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int npins;
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int i;
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@ -135,7 +135,7 @@ static int jh7110_dt_node_to_map(struct pinctrl_dev *pctldev,
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int ret;
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ngroups = 0;
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for_each_child_of_node(np, child)
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for_each_available_child_of_node(np, child)
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ngroups += 1;
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nmaps = 2 * ngroups;
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@ -150,7 +150,7 @@ static int jh7110_dt_node_to_map(struct pinctrl_dev *pctldev,
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nmaps = 0;
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ngroups = 0;
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mutex_lock(&sfp->mutex);
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for_each_child_of_node(np, child) {
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for_each_available_child_of_node(np, child) {
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int npins = of_property_count_u32_elems(child, "pinmux");
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int *pins;
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u32 *pinmux;
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