dt-bindings: clk: Extend binding doc for Stingray SOC
Update iproc clock dt-binding documentation with Stingray pll and clock details. Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Sandeep Tripathy
Stephen Boyd
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567bf2ed86
commit
25146e1e8f
@ -219,3 +219,79 @@ BCM63138
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--------
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PLL and leaf clock compatible strings for BCM63138 are:
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"brcm,bcm63138-armpll"
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Stingray
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-----------
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PLL and leaf clock compatible strings for Stingray are:
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"brcm,sr-genpll0"
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"brcm,sr-genpll1"
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"brcm,sr-genpll2"
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"brcm,sr-genpll3"
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"brcm,sr-genpll4"
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"brcm,sr-genpll5"
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"brcm,sr-genpll6"
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"brcm,sr-lcpll0"
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"brcm,sr-lcpll1"
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"brcm,sr-lcpll-pcie"
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The following table defines the set of PLL/clock index and ID for Stingray.
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These clock IDs are defined in:
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"include/dt-bindings/clock/bcm-sr.h"
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Clock Source Index ID
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--- ----- ----- ---------
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crystal N/A N/A N/A
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crmu_ref25m crystal N/A N/A
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genpll0 crystal 0 BCM_SR_GENPLL0
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clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK
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clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK
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clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK
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clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK
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clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK
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clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK
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genpll1 crystal 0 BCM_SR_GENPLL1
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clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK
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clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK
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genpll2 crystal 0 BCM_SR_GENPLL2
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clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK
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clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK
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clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK
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clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK
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clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH
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genpll3 crystal 0 BCM_SR_GENPLL3
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clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK
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clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK
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genpll4 crystal 0 BCM_SR_GENPLL4
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ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK
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clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK
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noc_clk genpll4 3 BCM_SR_GENPLL4_NOC_CLK
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clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK
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clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
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genpll5 crystal 0 BCM_SR_GENPLL5
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fs4_hf_clk genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK
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crypto_ae_clk genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK
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raid_ae_clk genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK
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genpll6 crystal 0 BCM_SR_GENPLL6
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48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK
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lcpll0 crystal 0 BCM_SR_LCPLL0
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clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK
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clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK
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clk_usb_ref lcpll0 3 BCM_SR_LCPLL0_USB_REF_CLK
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sata_refpn lcpll0 3 BCM_SR_LCPLL0_SATA_REFPN_CLK
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lcpll1 crystal 0 BCM_SR_LCPLL1
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wan lcpll1 1 BCM_SR_LCPLL0_WAN_CLK
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lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE
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pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK
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101
include/dt-bindings/clock/bcm-sr.h
Normal file
101
include/dt-bindings/clock/bcm-sr.h
Normal file
@ -0,0 +1,101 @@
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/*
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* BSD LICENSE
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*
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* Copyright(c) 2017 Broadcom. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Broadcom Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _CLOCK_BCM_SR_H
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#define _CLOCK_BCM_SR_H
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/* GENPLL 0 clock channel ID SCR HSLS FS PCIE */
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#define BCM_SR_GENPLL0 0
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#define BCM_SR_GENPLL0_SATA_CLK 1
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#define BCM_SR_GENPLL0_SCR_CLK 2
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#define BCM_SR_GENPLL0_250M_CLK 3
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#define BCM_SR_GENPLL0_PCIE_AXI_CLK 4
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#define BCM_SR_GENPLL0_PAXC_AXI_X2_CLK 5
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#define BCM_SR_GENPLL0_PAXC_AXI_CLK 6
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/* GENPLL 1 clock channel ID MHB PCIE NITRO */
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#define BCM_SR_GENPLL1 0
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#define BCM_SR_GENPLL1_PCIE_TL_CLK 1
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#define BCM_SR_GENPLL1_MHB_APB_CLK 2
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/* GENPLL 2 clock channel ID NITRO MHB*/
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#define BCM_SR_GENPLL2 0
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#define BCM_SR_GENPLL2_NIC_CLK 1
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#define BCM_SR_GENPLL2_250_NITRO_CLK 2
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#define BCM_SR_GENPLL2_125_NITRO_CLK 3
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#define BCM_SR_GENPLL2_CHIMP_CLK 4
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/* GENPLL 3 HSLS clock channel ID */
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#define BCM_SR_GENPLL3 0
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#define BCM_SR_GENPLL3_HSLS_CLK 1
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#define BCM_SR_GENPLL3_SDIO_CLK 2
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/* GENPLL 4 SCR clock channel ID */
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#define BCM_SR_GENPLL4 0
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#define BCM_SR_GENPLL4_CCN_CLK 1
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/* GENPLL 5 FS4 clock channel ID */
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#define BCM_SR_GENPLL5 0
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#define BCM_SR_GENPLL5_FS_CLK 1
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#define BCM_SR_GENPLL5_SPU_CLK 2
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/* GENPLL 6 NITRO clock channel ID */
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#define BCM_SR_GENPLL6 0
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#define BCM_SR_GENPLL6_48_USB_CLK 1
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/* LCPLL0 clock channel ID */
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#define BCM_SR_LCPLL0 0
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#define BCM_SR_LCPLL0_SATA_REF_CLK 1
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#define BCM_SR_LCPLL0_USB_REF_CLK 2
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#define BCM_SR_LCPLL0_SATA_REFPN_CLK 3
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/* LCPLL1 clock channel ID */
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#define BCM_SR_LCPLL1 0
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#define BCM_SR_LCPLL1_WAN_CLK 1
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/* LCPLL PCIE clock channel ID */
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#define BCM_SR_LCPLL_PCIE 0
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#define BCM_SR_LCPLL_PCIE_PHY_REF_CLK 1
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/* GENPLL EMEM0 clock channel ID */
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#define BCM_SR_EMEMPLL0 0
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#define BCM_SR_EMEMPLL0_EMEM_CLK 1
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/* GENPLL EMEM0 clock channel ID */
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#define BCM_SR_EMEMPLL1 0
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#define BCM_SR_EMEMPLL1_EMEM_CLK 1
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/* GENPLL EMEM0 clock channel ID */
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#define BCM_SR_EMEMPLL2 0
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#define BCM_SR_EMEMPLL2_EMEM_CLK 1
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#endif /* _CLOCK_BCM_SR_H */
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