clk: qcom: gcc-msm8939: Add missing MDSS MDP clock frequencies
Again the msm8936/msm8939 supports a wider range of operating frequencies to the antecedent msm8916 from which the msm8939.c driver is derived. static struct clk_freq_tbl ftbl_gcc_mdss_mdp_clk[] = { F( 50000000, gpll0_out_aux, 16, 0, 0), F( 80000000, gpll0_out_aux, 10, 0, 0), F( 100000000, gpll0_out_aux, 8, 0, 0), F( 145500000, gpll0_out_aux, 5.5, 0, 0), F( 153600000, gpll1_out_main, 4, 0, 0), F( 160000000, gpll0_out_aux, 5, 0, 0), F( 177780000, gpll0_out_aux, 4.5, 0, 0), F( 200000000, gpll0_out_aux, 4, 0, 0), F( 266670000, gpll0_out_aux, 3, 0, 0), F( 307200000, gpll1_out_main, 2, 0, 0), F( 366670000, gpll3_out_aux, 3, 0, 0), F_END }; We are missing 145.5 MHz and 153.6 MHz. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220712125922.3461675-6-bryan.odonoghue@linaro.org
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@ -1306,6 +1306,8 @@ static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
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F(50000000, P_GPLL0_AUX, 16, 0, 0),
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F(80000000, P_GPLL0_AUX, 10, 0, 0),
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F(100000000, P_GPLL0_AUX, 8, 0, 0),
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F(145500000, P_GPLL0_AUX, 5.5, 0, 0),
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F(153600000, P_GPLL0, 4, 0, 0),
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F(160000000, P_GPLL0_AUX, 5, 0, 0),
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F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
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F(200000000, P_GPLL0_AUX, 4, 0, 0),
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