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Newly added boards are the PX30 SOM system from Engicam and Kobol Helios64.

Browse Source 
The Scarlet tablet finally gets support for its cameras, now that the
 the rk3399-isp moved out of staging.
 The Odroid-Go-Advance got its joystick support now that the adc-joystick
 driver was merged and misc omprovements to the RockPi4, rk3328-roc-cc
 and orange-pi.
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Merge tag 'v5.11-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt

Newly added boards are the PX30 SOM system from Engicam and Kobol Helios64.
The Scarlet tablet finally gets support for its cameras, now that the
the rk3399-isp moved out of staging.
The Odroid-Go-Advance got its joystick support now that the adc-joystick
driver was merged and misc omprovements to the RockPi4, rk3328-roc-cc
and orange-pi.

* tag 'v5.11-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (28 commits)
  arm64: dts: rockchip: use USB host by default on rk3399-rock-pi-4
  arm64: dts: rockchip: fix I2S conflict on rk3399-rock-pi-4
  arm64: dts: rockchip: fix supplies on rk3399-rock-pi-4
  arm64: dts: rockchip: Fix UART pull-ups on rk3328
  arm64: dts: rockchip: add isp and sensors for Scarlet
  arm64: dts: rockchip: add isp0 node for rk3399
  arm64: dts: rockchip: Properly define the type C connector on rk3399-orangepi
  arm64: dts: rockchip: Add BT support on px30-engicam
  arm64: dts: rockchip: Add WiFi support on px30-engicam
  arm64: dts: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OF
  dt-bindings: arm: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OF
  arm64: dts: rockchip: Enable LVDS panel on px30-engicam-edimm2.2
  arm64: dts: rockchip: Enable USB Host, OTG on px30-enagicam
  arm64: dts: rockchip: rename sdhci nodename to mmc on rk3399
  arm64: dts: rockchip: Enable analog audio on rk3328-roc-cc
  arm64: dts: rockchip: Enable HDMI audio on rk3328-roc-cc
  arm64: dts: rockchip: Set dr_mode to "host" for OTG on rk3328-roc-cc
  arm64: dts: rockchip: Add Engicam PX30.Core C.TOUCH 2.0
  arm64: dts: rockchip: Add Engicam C.TOUCH 2.0
  dt-bindings: arm: rockchip: Add Engicam PX30.Core C.TOUCH 2.0
  ...

Link: https://lore.kernel.org/r/4278011.LvFx2qVVIh@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2020-12-09 00:03:14 +01:00
commit 261078ab90
18 changed files with 1219 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
Documentation/devicetree/bindings/arm/rockchip.yaml
View File

@ -70,6 +70,24 @@ properties:
- const: elgin,rv1108-r1
- const: rockchip,rv1108
- description: Engicam PX30.Core C.TOUCH 2.0
items:
- const: engicam,px30-core-ctouch2
- const: engicam,px30-core
- const: rockchip,px30
- description: Engicam PX30.Core C.TOUCH 2.0 10.1" Open Frame
items:
- const: engicam,px30-core-ctouch2-of10
- const: engicam,px30-core
- const: rockchip,px30
- description: Engicam PX30.Core EDIMM2.2 Starter Kit
items:
- const: engicam,px30-core-edimm2.2
- const: engicam,px30-core
- const: rockchip,px30
- description: Firefly Firefly-RK3288
items:
- enum:
@ -381,6 +399,11 @@ properties:
- khadas,edge-v
- const: rockchip,rk3399
- description: Kobol Helios64
items:
- const: kobol,helios64
- const: rockchip,rk3399
- description: Mecer Xtreme Mini S6
items:
- const: mecer,xms6

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -563,6 +563,8 @@ patternProperties:
description: Kionix, Inc.
"^kobo,.*":
description: Rakuten Kobo Inc.
"^kobol,.*":
description: Kobol Innovations Pte. Ltd.
"^koe,.*":
description: Kaohsiung Opto-Electronics Inc.
"^kontron,.*":

4
arch/arm64/boot/dts/rockchip/Makefile
View File

@ -1,5 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2-of10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb
@ -26,6 +29,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-hugsun-x99.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-captain.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-v.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-kobol-helios64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-leez-p710.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb

124
arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi Normal file
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@ -0,0 +1,124 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Engicam srl
* Copyright (c) 2020 Amarula Solutions
* Copyright (c) 2020 Amarula Solutions(India)
*/
/ {
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys"; /* +5V */
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&xin32k>;
clock-names = "ext_clock";
post-power-on-delay-ms = <80>;
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
};
vcc3v3_btreg: vcc3v3-btreg {
compatible = "regulator-gpio";
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&bt_enable_h>;
regulator-name = "btreg-gpio-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
states = <3300000 0x0>;
};
vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_rf_aux_mod";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
};
xin32k: xin32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "xin32k";
};
};
&sdio {
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
clock-frequency = <50000000>;
cap-sdio-irq;
cap-sd-highspeed;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
sd-uhs-sdr104;
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
};
};
&gmac {
clock_in_out = "output";
phy-supply = <&vcc_3v3>; /* +3V3_SOM */
snps,reset-active-low;
snps,reset-delays-us = <0 50000 50000>;
snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&pwm0 {
status = "okay";
};
&sdmmc {
cap-sd-highspeed;
card-detect-delay = <800>;
vmmc-supply = <&vcc_3v3>; /* +3V3_SOM */
vqmmc-supply = <&vcc_3v3>;
status = "okay";
};
&u2phy {
status = "okay";
u2phy_host: host-port {
status = "okay";
};
u2phy_otg: otg-port {
status = "okay";
};
};
&uart2 {
pinctrl-0 = <&uart2m1_xfer>;
status = "okay";
};
&usb20_otg {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};

30
arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi Normal file
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@ -0,0 +1,30 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Engicam srl
* Copyright (c) 2020 Amarula Solutions
* Copyright (c) 2020 Amarula Solutions(India)
*/
#include "px30-engicam-common.dtsi"
&pinctrl {
bt {
bt_enable_h: bt-enable-h {
rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&sdio_pwrseq {
reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
};
&vcc3v3_btreg {
enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
};

66
arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi Normal file
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@ -0,0 +1,66 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Engicam srl
* Copyright (c) 2020 Amarula Solutions(India)
*/
#include "px30-engicam-common.dtsi"
/ {
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm0 0 25000 0>;
};
panel {
compatible = "yes-optoelectronics,ytc700tlag-05-201c";
backlight = <&backlight>;
data-mapping = "vesa-24";
power-supply = <&vcc3v3_lcd>;
port {
panel_in_lvds: endpoint {
remote-endpoint = <&lvds_out_panel>;
};
};
};
};
&display_subsystem {
status = "okay";
};
&dsi_dphy {
status = "okay";
};
/* LVDS_B(secondary) */
&lvds {
status = "okay";
ports {
port@1 {
reg = <1>;
lvds_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds>;
};
};
};
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};

77
arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts Normal file
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@ -0,0 +1,77 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
* Copyright (c) 2020 Engicam srl
* Copyright (c) 2020 Amarula Solutions(India)
*/
/dts-v1/;
#include "px30.dtsi"
#include "px30-engicam-ctouch2.dtsi"
#include "px30-engicam-px30-core.dtsi"
/ {
model = "Engicam PX30.Core C.TOUCH 2.0 10.1\" Open Frame";
compatible = "engicam,px30-core-ctouch2-of10", "engicam,px30-core",
"rockchip,px30";
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm0 0 25000 0>;
};
chosen {
stdout-path = "serial2:115200n8";
};
panel {
compatible = "ampire,am-1280800n3tzqw-t00h";
backlight = <&backlight>;
power-supply = <&vcc3v3_lcd>;
data-mapping = "vesa-24";
port {
panel_in_lvds: endpoint {
remote-endpoint = <&lvds_out_panel>;
};
};
};
};
&display_subsystem {
status = "okay";
};
&dsi_dphy {
status = "okay";
};
&lvds {
status = "okay";
ports {
port@1 {
reg = <1>;
lvds_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds>;
};
};
};
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};

22
arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2.dts Normal file
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@ -0,0 +1,22 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
* Copyright (c) 2020 Engicam srl
* Copyright (c) 2020 Amarula Solutions
* Copyright (c) 2020 Amarula Solutions(India)
*/
/dts-v1/;
#include "px30.dtsi"
#include "px30-engicam-ctouch2.dtsi"
#include "px30-engicam-px30-core.dtsi"
/ {
model = "Engicam PX30.Core C.TOUCH 2.0";
compatible = "engicam,px30-core-ctouch2", "engicam,px30-core",
"rockchip,px30";
chosen {
stdout-path = "serial2:115200n8";
};
};

43
arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts Normal file
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@ -0,0 +1,43 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
* Copyright (c) 2020 Engicam srl
* Copyright (c) 2020 Amarula Solutions(India)
*/
/dts-v1/;
#include "px30.dtsi"
#include "px30-engicam-edimm2.2.dtsi"
#include "px30-engicam-px30-core.dtsi"
/ {
model = "Engicam PX30.Core EDIMM2.2 Starter Kit";
compatible = "engicam,px30-core-edimm2.2", "engicam,px30-core",
"rockchip,px30";
chosen {
stdout-path = "serial2:115200n8";
};
};
&pinctrl {
bt {
bt_enable_h: bt-enable-h {
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&sdio_pwrseq {
reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>;
};
&vcc3v3_btreg {
enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
};

237
arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi Normal file
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@ -0,0 +1,237 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
* Copyright (c) 2020 Engicam srl
* Copyright (c) 2020 Amarula Solutons
* Copyright (c) 2020 Amarula Solutons(India)
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
/ {
compatible = "engicam,px30-core", "rockchip,px30";
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&cpu1 {
cpu-supply = <&vdd_arm>;
};
&cpu2 {
cpu-supply = <&vdd_arm>;
};
&cpu3 {
cpu-supply = <&vdd_arm>;
};
&emmc {
cap-mmc-highspeed;
mmc-hs200-1_8v;
non-removable;
status = "okay";
};
&i2c0 {
status = "okay";
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc5v0_sys>;
regulators {
vdd_log: DCDC_REG1 {
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vdd_arm: DCDC_REG2 {
regulator-name = "vdd_arm";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_3v3: DCDC_REG4 {
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc3v3_sys: DCDC_REG5 {
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_1v0: LDO_REG1 {
regulator-name = "vcc_1v0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc_1v8: LDO_REG2 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_1v0: LDO_REG3 {
regulator-name = "vdd_1v0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc3v0_pmu: LDO_REG4 {
regulator-name = "vcc3v0_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc3v3_lcd: SWITCH_REG1 {
regulator-boot-on;
regulator-name = "vcc3v3_lcd";
};
vcc5v0_host: SWITCH_REG2 {
regulator-name = "vcc5v0_host";
regulator-always-on;
regulator-boot-on;
};
};
};
};
&io_domains {
vccio1-supply = <&vcc_3v3>;
vccio2-supply = <&vcc_3v3>;
vccio3-supply = <&vcc_3v3>;
vccio4-supply = <&vcc_3v3>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_1v8>;
status = "okay";
};
&pinctrl {
pmic {
pmic_int: pmic_int {
rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&pmu_io_domains {
pmuio1-supply = <&vcc_3v3>;
pmuio2-supply = <&vcc_3v3>;
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <1>;
status = "okay";
};

24
arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
View File

@ -18,6 +18,30 @@
stdout-path = "serial2:115200n8";
};
adc-joystick {
compatible = "adc-joystick";
io-channels = <&saradc 1>,
<&saradc 2>;
#address-cells = <1>;
#size-cells = <0>;
axis@0 {
reg = <0>;
abs-flat = <10>;
abs-fuzz = <10>;
abs-range = <172 772>;
linux,code = <ABS_X>;
};
axis@1 {
reg = <1>;
abs-flat = <10>;
abs-fuzz = <10>;
abs-range = <278 815>;
linux,code = <ABS_Y>;
};
};
backlight: backlight {
compatible = "pwm-backlight";
power-supply = <&vcc_bl>;

21
arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
View File

@ -104,6 +104,14 @@
};
};
&analog_sound {
status = "okay";
};
&codec {
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
@ -161,6 +169,10 @@
status = "okay";
};
&hdmi_sound {
status = "okay";
};
&i2c1 {
status = "okay";
@ -270,6 +282,14 @@
};
};
&i2s0 {
status = "okay";
};
&i2s1 {
status = "okay";
};
&io_domains {
status = "okay";
@ -334,6 +354,7 @@
};
&usb20_otg {
dr_mode = "host";
status = "okay";
};

16
arch/arm64/boot/dts/rockchip/rk3328.dtsi
View File

@ -1237,8 +1237,8 @@
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
<1 RK_PB0 1 &pcfg_pull_none>;
rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
<1 RK_PB0 1 &pcfg_pull_up>;
};
uart0_cts: uart0-cts {
@ -1256,8 +1256,8 @@
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
<3 RK_PA6 4 &pcfg_pull_none>;
rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>,
<3 RK_PA6 4 &pcfg_pull_up>;
};
uart1_cts: uart1-cts {
@ -1275,15 +1275,15 @@
uart2-0 {
uart2m0_xfer: uart2m0-xfer {
rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
<1 RK_PA1 2 &pcfg_pull_none>;
rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>,
<1 RK_PA1 2 &pcfg_pull_up>;
};
};
uart2-1 {
uart2m1_xfer: uart2m1-xfer {
rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
<2 RK_PA1 1 &pcfg_pull_none>;
rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
<2 RK_PA1 1 &pcfg_pull_up>;
};
};

74
arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
View File

@ -296,6 +296,52 @@ camera: &i2c7 {
/* 24M mclk is shared between world and user cameras */
pinctrl-0 = <&i2c7_xfer &test_clkout1>;
/* Rear-facing camera */
wcam: camera@36 {
compatible = "ovti,ov5695";
reg = <0x36>;
pinctrl-names = "default";
pinctrl-0 = <&wcam_rst>;
clocks = <&cru SCLK_TESTCLKOUT1>;
clock-names = "xvclk";
avdd-supply = <&pp2800_cam>;
dvdd-supply = <&pp1250_cam>;
dovdd-supply = <&pp1800_s0>;
reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
port {
wcam_out: endpoint {
remote-endpoint = <&mipi_in_wcam>;
data-lanes = <1 2>;
};
};
};
/* Front-facing camera */
ucam: camera@3c {
compatible = "ovti,ov2685";
reg = <0x3c>;
pinctrl-names = "default";
pinctrl-0 = <&ucam_rst>;
clocks = <&cru SCLK_TESTCLKOUT1>;
clock-names = "xvclk";
avdd-supply = <&pp2800_cam>;
dovdd-supply = <&pp1800_s0>;
dvdd-supply = <&pp1800_s0>;
reset-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
port {
ucam_out: endpoint {
remote-endpoint = <&mipi_in_ucam>;
data-lanes = <1>;
};
};
};
};
&cdn_dp {
@ -353,10 +399,38 @@ camera: &i2c7 {
gpio1830-supply = <&pp1800_s0>; /* APIO4_VDD; 4c 4d */
};
&isp0 {
status = "okay";
ports {
port@0 {
mipi_in_wcam: endpoint@0 {
reg = <0>;
remote-endpoint = <&wcam_out>;
data-lanes = <1 2>;
};
mipi_in_ucam: endpoint@1 {
reg = <1>;
remote-endpoint = <&ucam_out>;
data-lanes = <1>;
};
};
};
};
&isp0_mmu {
status = "okay";
};
&max98357a {
sdmode-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
};
&mipi_dphy_rx0 {
status = "okay";
};
&mipi_dsi {
status = "okay";
clock-master;

372
arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts Normal file
View File

@ -0,0 +1,372 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Aditya Prayoga <aditya@kobol.io>
*/
/*
* The Kobol Helios64 is a board designed to operate as a NAS and optionally
* ships with an enclosing that can host five 2.5" hard disks.
*
* See https://wiki.kobol.io/helios64/intro/ for further details.
*/
/dts-v1/;
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
/ {
model = "Kobol Helios64";
compatible = "kobol,helios64", "rockchip,rk3399";
avdd_1v8_s0: avdd-1v8-s0 {
compatible = "regulator-fixed";
regulator-name = "avdd_1v8_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc3v3_sys_s3>;
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&sys_grn_led_on &sys_red_led_on>;
led-0 {
label = "helios64:green:status";
gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
led-1 {
label = "helios64:red:fault";
gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
};
vcc1v8_sys_s0: vcc1v8-sys-s0 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8_sys_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc1v8_sys_s3>;
};
vcc3v0_sd: vcc3v0-sd {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
regulator-name = "vcc3v0_sd";
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_pwr_h>;
vin-supply = <&vcc3v3_sys_s3>;
};
vcc3v3_sys_s3: vcc_lan: vcc3v3-sys-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin_bkup>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc12v_dcin: vcc12v-dcin {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc12v_dcin_bkup: vcc12v-dcin-bkup {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin_bkup";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
vin-supply = <&vcc12v_dcin>;
};
};
/*
* The system doesn't run stable with cpu freq enabled, so disallow the lower
* frequencies until this problem is properly understood and resolved.
*/
&cluster0_opp {
/delete-node/ opp00;
/delete-node/ opp01;
/delete-node/ opp02;
/delete-node/ opp03;
/delete-node/ opp04;
};
&cluster1_opp {
/delete-node/ opp00;
/delete-node/ opp01;
/delete-node/ opp02;
/delete-node/ opp03;
/delete-node/ opp04;
/delete-node/ opp05;
/delete-node/ opp06;
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_b>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_b>;
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_l>;
};
&emmc_phy {
status = "okay";
};
&gmac {
assigned-clock-parents = <&clkin_gmac>;
assigned-clocks = <&cru SCLK_RMII_SRC>;
clock_in_out = "input";
phy-mode = "rgmii";
phy-supply = <&vcc_lan>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins &gphy_reset>;
rx_delay = <0x20>;
tx_delay = <0x28>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <168>;
i2c-scl-falling-time-ns = <4>;
status = "okay";
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio0>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
clock-output-names = "xin32k", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc6-supply = <&vcc5v0_sys>;
vcc7-supply = <&vcc5v0_sys>;
vcc8-supply = <&vcc3v3_sys_s3>;
vcc9-supply = <&vcc5v0_sys>;
vcc10-supply = <&vcc5v0_sys>;
vcc11-supply = <&vcc5v0_sys>;
vcc12-supply = <&vcc3v3_sys_s3>;
vddio-supply = <&vcc3v0_s3>;
wakeup-source;
#clock-cells = <1>;
regulators {
vdd_cpu_l: DCDC_REG2 {
regulator-name = "vdd_cpu_l";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_sys_s3: DCDC_REG4 {
regulator-name = "vcc1v8_sys_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_sdio_s0: LDO_REG4 {
regulator-name = "vcc_sdio_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc3v0_s3: LDO_REG8 {
regulator-name = "vcc3v0_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
};
};
vdd_cpu_b: regulator@40 {
compatible = "silergy,syr827";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu_b";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c2 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <160>;
i2c-scl-falling-time-ns = <30>;
status = "okay";
temp@4c {
compatible = "national,lm75";
reg = <0x4c>;
};
};
&io_domains {
audio-supply = <&vcc1v8_sys_s0>;
bt656-supply = <&vcc1v8_sys_s0>;
gpio1830-supply = <&vcc3v0_s3>;
sdmmc-supply = <&vcc_sdio_s0>;
status = "okay";
};
&pinctrl {
gmac {
gphy_reset: gphy-reset {
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>;
};
};
leds {
sys_grn_led_on: sys-grn-led-on {
rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
};
sys_red_led_on: sys-red-led-on {
rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
vcc3v0-sd {
sdmmc0_pwr_h: sdmmc0-pwr-h {
rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&pmu_io_domains {
pmu1830-supply = <&vcc3v0_s3>;
status = "okay";
};
&sdhci {
bus-width = <8>;
mmc-hs200-1_8v;
non-removable;
vqmmc-supply = <&vcc1v8_sys_s0>;
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-sd-highspeed;
cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
vmmc-supply = <&vcc3v0_sd>;
vqmmc-supply = <&vcc_sdio_s0>;
status = "okay";
};
&uart2 {
status = "okay";
};

62
arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts
View File

@ -7,6 +7,7 @@
#include "dt-bindings/pwm/pwm.h"
#include "dt-bindings/input/input.h"
#include "dt-bindings/usb/pd.h"
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
@ -531,6 +532,43 @@
pinctrl-names = "default";
pinctrl-0 = <&chg_cc_int_l>;
vbus-supply = <&vbus_typec>;
typec_con: connector {
compatible = "usb-c-connector";
data-role = "host";
label = "USB-C";
op-sink-microwatt = <1000000>;
power-role = "dual";
sink-pdos =
<PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
source-pdos =
<PDO_FIXED(5000, 1400, PDO_FIXED_USB_COMM)>;
try-power-role = "sink";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec_hs: endpoint {
remote-endpoint = <&u2phy0_typec_hs>;
};
};
port@1 {
reg = <1>;
typec_ss: endpoint {
remote-endpoint = <&tcphy0_typec_ss>;
};
};
port@2 {
reg = <2>;
typec_dp: endpoint {
remote-endpoint = <&tcphy0_typec_dp>;
};
};
};
};
};
};
@ -717,6 +755,22 @@
status = "okay";
};
&tcphy0_dp {
port {
tcphy0_typec_dp: endpoint {
remote-endpoint = <&typec_dp>;
};
};
};
&tcphy0_usb3 {
port {
tcphy0_typec_ss: endpoint {
remote-endpoint = <&typec_ss>;
};
};
};
&tcphy1 {
status = "okay";
};
@ -739,6 +793,12 @@
phy-supply = <&vcc5v0_host>;
status = "okay";
};
port {
u2phy0_typec_hs: endpoint {
remote-endpoint = <&typec_hs>;
};
};
};
&u2phy1 {
@ -799,7 +859,7 @@
&usbdrd_dwc3_0 {
status = "okay";
dr_mode = "otg";
dr_mode = "host";
};
&usbdrd3_1 {

15
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
View File

@ -111,10 +111,6 @@
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_log: vdd-log {
@ -362,8 +358,6 @@
regulator-name = "vcc_cam";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
@ -373,8 +367,6 @@
regulator-name = "vcc_mipi";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
@ -440,8 +432,9 @@
};
&i2s0 {
rockchip,playback-channels = <8>;
rockchip,capture-channels = <8>;
pinctrl-0 = <&i2s0_2ch_bus>;
rockchip,capture-channels = <2>;
rockchip,playback-channels = <2>;
status = "okay";
};
@ -680,7 +673,7 @@
&usbdrd_dwc3_0 {
status = "okay";
dr_mode = "otg";
dr_mode = "host";
};
&usbdrd3_1 {

28
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View File

@ -328,7 +328,7 @@
status = "disabled";
};
sdhci: sdhci@fe330000 {
sdhci: mmc@fe330000 {
compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
reg = <0x0 0xfe330000 0x0 0x10000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
@ -1723,6 +1723,32 @@
status = "disabled";
};
isp0: isp0@ff910000 {
compatible = "rockchip,rk3399-cif-isp";
reg = <0x0 0xff910000 0x0 0x4000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru SCLK_ISP0>,
<&cru ACLK_ISP0_WRAPPER>,
<&cru HCLK_ISP0_WRAPPER>;
clock-names = "isp", "aclk", "hclk";
iommus = <&isp0_mmu>;
phys = <&mipi_dphy_rx0>;
phy-names = "dphy";
power-domains = <&power RK3399_PD_ISP0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
isp0_mmu: iommu@ff914000 {
compatible = "rockchip,iommu";
reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;