drm/i915/dpio: Give VLV DPIO group register a clearer name
Include _GRP in VLV DPIO PHY group access register define names. Makes it more obvious where the accesses will land. Also matches the naming used by BXT already. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240422083457.23815-11-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä
parent
b798431c04
commit
263ed34938
@ -1071,18 +1071,18 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
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vlv_dpio_get(dev_priv);
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vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), 0x00000000);
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vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch), demph_reg_value);
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vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(ch),
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vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), 0x00000000);
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vlv_dpio_write(dev_priv, phy, VLV_TX_DW4_GRP(ch), demph_reg_value);
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vlv_dpio_write(dev_priv, phy, VLV_TX_DW2_GRP(ch),
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uniqtranscale_reg_value);
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vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(ch), 0x0C782040);
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vlv_dpio_write(dev_priv, phy, VLV_TX_DW3_GRP(ch), 0x0C782040);
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if (tx3_demph)
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vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(ch), tx3_demph);
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vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(ch), 0x00030000);
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vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(ch), preemph_reg_value);
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vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), DPIO_TX_OCALINIT_EN);
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vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11_GRP(ch), 0x00030000);
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vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value);
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vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), DPIO_TX_OCALINIT_EN);
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vlv_dpio_put(dev_priv);
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}
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@ -1098,19 +1098,19 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
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/* Program Tx lane resets to default */
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vlv_dpio_get(dev_priv);
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vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch),
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vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch),
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DPIO_PCS_TX_LANE2_RESET |
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DPIO_PCS_TX_LANE1_RESET);
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vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch),
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vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch),
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DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
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DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
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(1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
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DPIO_PCS_CLK_SOFT_RESET);
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/* Fix up inter-pair skew failure */
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vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12(ch), 0x00750f00);
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vlv_dpio_write(dev_priv, phy, VLV_TX_DW11(ch), 0x00001500);
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vlv_dpio_write(dev_priv, phy, VLV_TX_DW14(ch), 0x40400000);
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vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12_GRP(ch), 0x00750f00);
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vlv_dpio_write(dev_priv, phy, VLV_TX_DW11_GRP(ch), 0x00001500);
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vlv_dpio_write(dev_priv, phy, VLV_TX_DW14_GRP(ch), 0x40400000);
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vlv_dpio_put(dev_priv);
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}
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@ -1136,11 +1136,11 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
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else
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val &= ~(1<<21);
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val |= 0x001000c4;
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vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8(ch), val);
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vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8_GRP(ch), val);
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/* Program lane clock */
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vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14(ch), 0x00760018);
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vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23(ch), 0x00400888);
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vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14_GRP(ch), 0x00760018);
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vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23_GRP(ch), 0x00400888);
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vlv_dpio_put(dev_priv);
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}
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@ -1154,7 +1154,7 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder,
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enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
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vlv_dpio_get(dev_priv);
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vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch), 0x00000000);
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vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch), 0x00e00060);
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vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch), 0x00000000);
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vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060);
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vlv_dpio_put(dev_priv);
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}
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@ -254,13 +254,13 @@
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* Per DDI channel DPIO regs
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*/
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#define _VLV_PCS_DW0_CH0 0x8200
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#define _VLV_PCS_DW0_CH1 0x8400
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#define _VLV_PCS_DW0_CH0_GRP 0x8200
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#define _VLV_PCS_DW0_CH1_GRP 0x8400
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#define DPIO_PCS_TX_LANE2_RESET (1 << 16)
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#define DPIO_PCS_TX_LANE1_RESET (1 << 7)
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#define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4)
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#define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3)
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#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
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#define VLV_PCS_DW0_GRP(ch) _PORT(ch, _VLV_PCS_DW0_CH0_GRP, _VLV_PCS_DW0_CH1_GRP)
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#define _VLV_PCS01_DW0_CH0 0x200
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#define _VLV_PCS23_DW0_CH0 0x400
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@ -269,14 +269,14 @@
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#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
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#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
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#define _VLV_PCS_DW1_CH0 0x8204
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#define _VLV_PCS_DW1_CH1 0x8404
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#define _VLV_PCS_DW1_CH0_GRP 0x8204
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#define _VLV_PCS_DW1_CH1_GRP 0x8404
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#define CHV_PCS_REQ_SOFTRESET_EN (1 << 23)
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#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22)
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#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
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#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
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#define DPIO_PCS_CLK_SOFT_RESET (1 << 5)
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#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
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#define VLV_PCS_DW1_GRP(ch) _PORT(ch, _VLV_PCS_DW1_CH0_GRP, _VLV_PCS_DW1_CH1_GRP)
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#define _VLV_PCS01_DW1_CH0 0x204
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#define _VLV_PCS23_DW1_CH0 0x404
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@ -285,11 +285,11 @@
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#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
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#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
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#define _VLV_PCS_DW8_CH0 0x8220
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#define _VLV_PCS_DW8_CH1 0x8420
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#define _VLV_PCS_DW8_CH0_GRP 0x8220
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#define _VLV_PCS_DW8_CH1_GRP 0x8420
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#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
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#define CHV_PCS_USEDCLKCHANNEL (1 << 21)
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#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
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#define VLV_PCS_DW8_GRP(ch) _PORT(ch, _VLV_PCS_DW8_CH0_GRP, _VLV_PCS_DW8_CH1_GRP)
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#define _VLV_PCS01_DW8_CH0 0x0220
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#define _VLV_PCS23_DW8_CH0 0x0420
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@ -298,15 +298,15 @@
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#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
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#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
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#define _VLV_PCS_DW9_CH0 0x8224
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#define _VLV_PCS_DW9_CH1 0x8424
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#define _VLV_PCS_DW9_CH0_GRP 0x8224
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#define _VLV_PCS_DW9_CH1_GRP 0x8424
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#define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13)
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#define DPIO_PCS_TX2MARGIN_000 (0 << 13)
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#define DPIO_PCS_TX2MARGIN_101 (1 << 13)
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#define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10)
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#define DPIO_PCS_TX1MARGIN_000 (0 << 10)
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#define DPIO_PCS_TX1MARGIN_101 (1 << 10)
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#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
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#define VLV_PCS_DW9_GRP(ch) _PORT(ch, _VLV_PCS_DW9_CH0_GRP, _VLV_PCS_DW9_CH1_GRP)
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#define _VLV_PCS01_DW9_CH0 0x224
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#define _VLV_PCS23_DW9_CH0 0x424
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@ -315,8 +315,8 @@
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#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
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#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
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#define _CHV_PCS_DW10_CH0 0x8228
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#define _CHV_PCS_DW10_CH1 0x8428
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#define _CHV_PCS_DW10_CH0_GRP 0x8228
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#define _CHV_PCS_DW10_CH1_GRP 0x8428
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#define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30)
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#define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31)
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#define DPIO_PCS_TX2DEEMP_MASK (0xf << 24)
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@ -325,7 +325,7 @@
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#define DPIO_PCS_TX1DEEMP_MASK (0xf << 16)
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#define DPIO_PCS_TX1DEEMP_9P5 (0 << 16)
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#define DPIO_PCS_TX1DEEMP_6P0 (2 << 16)
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#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
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#define CHV_PCS_DW10_GRP(ch) _PORT(ch, _CHV_PCS_DW10_CH0_GRP, _CHV_PCS_DW10_CH1_GRP)
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#define _VLV_PCS01_DW10_CH0 0x0228
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#define _VLV_PCS23_DW10_CH0 0x0428
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@ -334,13 +334,13 @@
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#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
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#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
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#define _VLV_PCS_DW11_CH0 0x822c
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#define _VLV_PCS_DW11_CH1 0x842c
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#define _VLV_PCS_DW11_CH0_GRP 0x822c
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#define _VLV_PCS_DW11_CH1_GRP 0x842c
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#define DPIO_TX2_STAGGER_MASK(x) ((x) << 24)
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#define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3)
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#define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1)
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#define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0)
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#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
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#define VLV_PCS_DW11_GRP(ch) _PORT(ch, _VLV_PCS_DW11_CH0_GRP, _VLV_PCS_DW11_CH1_GRP)
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#define _VLV_PCS01_DW11_CH0 0x022c
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#define _VLV_PCS23_DW11_CH0 0x042c
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@ -356,64 +356,64 @@
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#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
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#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
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#define _VLV_PCS_DW12_CH0 0x8230
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#define _VLV_PCS_DW12_CH1 0x8430
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#define _VLV_PCS_DW12_CH0_GRP 0x8230
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#define _VLV_PCS_DW12_CH1_GRP 0x8430
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#define DPIO_TX2_STAGGER_MULT(x) ((x) << 20)
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#define DPIO_TX1_STAGGER_MULT(x) ((x) << 16)
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#define DPIO_TX1_STAGGER_MASK(x) ((x) << 8)
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#define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6)
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#define DPIO_LANESTAGGER_STRAP(x) ((x) << 0)
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#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
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#define VLV_PCS_DW12_GRP(ch) _PORT(ch, _VLV_PCS_DW12_CH0_GRP, _VLV_PCS_DW12_CH1_GRP)
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#define _VLV_PCS_DW14_CH0 0x8238
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#define _VLV_PCS_DW14_CH1 0x8438
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#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
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#define _VLV_PCS_DW14_CH0_GRP 0x8238
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#define _VLV_PCS_DW14_CH1_GRP 0x8438
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#define VLV_PCS_DW14_GRP(ch) _PORT(ch, _VLV_PCS_DW14_CH0_GRP, _VLV_PCS_DW14_CH1_GRP)
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#define VLV_PCS_DW17_BCAST 0xc044
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#define _VLV_PCS_DW23_CH0 0x825c
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#define _VLV_PCS_DW23_CH1 0x845c
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#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
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#define _VLV_PCS_DW23_CH0_GRP 0x825c
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#define _VLV_PCS_DW23_CH1_GRP 0x845c
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#define VLV_PCS_DW23_GRP(ch) _PORT(ch, _VLV_PCS_DW23_CH0_GRP, _VLV_PCS_DW23_CH1_GRP)
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#define _VLV_TX_DW2_CH0 0x8288
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#define _VLV_TX_DW2_CH1 0x8488
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#define _VLV_TX_DW2_CH0_GRP 0x8288
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#define _VLV_TX_DW2_CH1_GRP 0x8488
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#define DPIO_SWING_MARGIN000_SHIFT 16
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#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
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#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
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#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
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#define VLV_TX_DW2_GRP(ch) _PORT(ch, _VLV_TX_DW2_CH0_GRP, _VLV_TX_DW2_CH1_GRP)
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#define _VLV_TX_DW3_CH0 0x828c
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#define _VLV_TX_DW3_CH1 0x848c
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#define _VLV_TX_DW3_CH0_GRP 0x828c
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#define _VLV_TX_DW3_CH1_GRP 0x848c
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/* The following bit for CHV phy */
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#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27)
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#define DPIO_SWING_MARGIN101_SHIFT 16
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#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
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#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
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#define VLV_TX_DW3_GRP(ch) _PORT(ch, _VLV_TX_DW3_CH0_GRP, _VLV_TX_DW3_CH1_GRP)
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#define _VLV_TX_DW4_CH0 0x8290
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#define _VLV_TX_DW4_CH1 0x8490
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#define _VLV_TX_DW4_CH0_GRP 0x8290
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#define _VLV_TX_DW4_CH1_GRP 0x8490
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#define DPIO_SWING_DEEMPH9P5_SHIFT 24
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#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
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#define DPIO_SWING_DEEMPH6P0_SHIFT 16
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#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
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#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
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#define VLV_TX_DW4_GRP(ch) _PORT(ch, _VLV_TX_DW4_CH0_GRP, _VLV_TX_DW4_CH1_GRP)
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#define _VLV_TX3_DW4_CH0 0x690
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#define _VLV_TX3_DW4_CH1 0x2a90
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#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
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#define _VLV_TX_DW5_CH0 0x8294
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#define _VLV_TX_DW5_CH1 0x8494
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#define _VLV_TX_DW5_CH0_GRP 0x8294
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#define _VLV_TX_DW5_CH1_GRP 0x8494
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#define DPIO_TX_OCALINIT_EN (1 << 31)
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#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
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#define VLV_TX_DW5_GRP(ch) _PORT(ch, _VLV_TX_DW5_CH0_GRP, _VLV_TX_DW5_CH1_GRP)
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#define _VLV_TX_DW11_CH0 0x82ac
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#define _VLV_TX_DW11_CH1 0x84ac
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#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
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#define _VLV_TX_DW11_CH0_GRP 0x82ac
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#define _VLV_TX_DW11_CH1_GRP 0x84ac
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#define VLV_TX_DW11_GRP(ch) _PORT(ch, _VLV_TX_DW11_CH0_GRP, _VLV_TX_DW11_CH1_GRP)
|
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|
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#define _VLV_TX_DW14_CH0 0x82b8
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#define _VLV_TX_DW14_CH1 0x84b8
|
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#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
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#define _VLV_TX_DW14_CH0_GRP 0x82b8
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#define _VLV_TX_DW14_CH1_GRP 0x84b8
|
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#define VLV_TX_DW14_GRP(ch) _PORT(ch, _VLV_TX_DW14_CH0_GRP, _VLV_TX_DW14_CH1_GRP)
|
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|
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/* CHV dpPhy registers */
|
||||
#define _CHV_PLL_DW0_CH0 0x8000
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user