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drm/amdgpu: apply gc v9_4_2 golden settings for aldebaran

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Those registers should be programmed as one-time initialization

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang 2020-10-19 20:54:25 +08:00 committed by Alex Deucher
parent 16171a25d8
commit 264aef8b3b
3 changed files with 57 additions and 1 deletions
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4
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
View File

@ -984,6 +984,10 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_gc_9_1_rn,
ARRAY_SIZE(golden_settings_gc_9_1_rn));
return; /* for renoir, don't need common goldensetting */
case CHIP_ALDEBARAN:
gfx_v9_4_2_init_golden_registers(adev,
adev->smuio.funcs->get_die_id(adev));
break;
default:
break;
}

51
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
View File

@ -26,6 +26,57 @@
#include "gc/gc_9_4_2_offset.h"
#include "gc/gc_9_4_2_sh_mask.h"
static const struct soc15_reg_golden golden_settings_gc_9_4_2_alde_die_0[] = {
SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_0, 0x3fffffff, 0x141dc920),
SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_1, 0x3fffffff, 0x3b458b93),
SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_2, 0x3fffffff, 0x1a4f5583),
SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_3, 0x3fffffff, 0x317717f6),
SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_4, 0x3fffffff, 0x107cc1e6),
SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_5, 0x3ff, 0x351),
};
static const struct soc15_reg_golden golden_settings_gc_9_4_2_alde_die_1[] = {
SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_0, 0x3fffffff, 0x2591aa38),
SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_1, 0x3fffffff, 0xac9688B),
SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_2, 0x3fffffff, 0x2bc3369B),
SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_3, 0x3fffffff, 0xfb74ee),
SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_4, 0x3fffffff, 0x21f0a2fe),
SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_5, 0x3ff, 0x49),
};
static const struct soc15_reg_golden golden_settings_gc_9_4_2_alde[] = {
SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_UTCL1_CNTL1, 0x30000000, 0x30000000),
};
void gfx_v9_4_2_init_golden_registers(struct amdgpu_device *adev,
uint32_t die_id)
{
soc15_program_register_sequence(adev,
golden_settings_gc_9_4_2_alde,
ARRAY_SIZE(golden_settings_gc_9_4_2_alde));
/* apply golden settings per die */
switch (die_id) {
case 0:
soc15_program_register_sequence(adev,
golden_settings_gc_9_4_2_alde_die_0,
ARRAY_SIZE(golden_settings_gc_9_4_2_alde_die_0));
break;
case 1:
soc15_program_register_sequence(adev,
golden_settings_gc_9_4_2_alde_die_1,
ARRAY_SIZE(golden_settings_gc_9_4_2_alde_die_1));
break;
default:
dev_warn(adev->dev,
"invalid die id %d, ignore channel fabricid remap settings\n",
die_id);
break;
}
return;
}
void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev,
uint32_t first_vmid,
uint32_t last_vmid)

3
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h
View File

@ -26,5 +26,6 @@
void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev,
uint32_t first_vmid, uint32_t last_vmid);
void gfx_v9_4_2_init_golden_registers(struct amdgpu_device *adev,
uint32_t die_id);
#endif /* __GFX_V9_4_2_H__ */