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ARM: dts: pfla02: PHY reset is active-low

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Note that the fec driver code currently hard-codes an active-low
reset, regardless of the flags in the device tree.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This commit is contained in:
Philipp Zabel 2014-04-14 17:37:26 +02:00 committed by Shawn Guo
parent 94a1bbf85a
commit 26888190cb
1 changed files with 3 additions and 1 deletions
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4
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
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@ -9,6 +9,8 @@
* http://www.gnu.org/copyleft/gpl.html
*/
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Phytec phyFLEX-i.MX6 Ouad";
compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
@ -289,7 +291,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 0>;
phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
status = "disabled";
};