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clk: qcom: flag for 64 bit CONFIG_CTL

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Some of the Alpha PLLs (like Spark and Brammo) don't have a
CONFIG_CTL_U register. Add logic to detect when PLLs don't have
this second config register and skip programming it during PLL
initialization.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Abhishek Sahu 2017-09-28 23:20:43 +05:30 committed by Stephen Boyd
parent 1e859d3e03
commit 26945e0a23
1 changed files with 6 additions and 1 deletions
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7
drivers/clk/qcom/clk-alpha-pll.c
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@ -82,6 +82,8 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
#define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
#define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
struct clk_alpha_pll, clkr)
@ -136,7 +138,10 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
regmap_write(regmap, PLL_L_VAL(pll), config->l);
regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
regmap_write(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
if (pll_has_64bit_config(pll))
regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
config->config_ctl_hi_val);
val = config->main_output_mask;
val |= config->aux_output_mask;