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MIPS: Octeon: Update feature test functions for new chips and features.

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cvmx.h was rearranged to fix include file ordering problems, but there
is no change other than moving some definitions around.

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2984/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney 2011-11-22 14:47:04 +00:00 committed by Ralf Baechle
parent 412394d104
commit 26afc5e399
2 changed files with 126 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

42
arch/mips/include/asm/octeon/cvmx.h
View File

@ -31,6 +31,27 @@
#include <linux/kernel.h>
#include <linux/string.h>
enum cvmx_mips_space {
CVMX_MIPS_SPACE_XKSEG = 3LL,
CVMX_MIPS_SPACE_XKPHYS = 2LL,
CVMX_MIPS_SPACE_XSSEG = 1LL,
CVMX_MIPS_SPACE_XUSEG = 0LL
};
/* These macros for use when using 32 bit pointers. */
#define CVMX_MIPS32_SPACE_KSEG0 1l
#define CVMX_ADD_SEG32(segment, add) \
(((int32_t)segment << 31) | (int32_t)(add))
#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
/* These macros simplify the process of creating common IO addresses */
#define CVMX_ADD_SEG(segment, add) \
((((uint64_t)segment) << 62) | (add))
#ifndef CVMX_ADD_IO_SEG
#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
#endif
#include "cvmx-asm.h"
#include "cvmx-packet.h"
#include "cvmx-sysinfo.h"
@ -129,27 +150,6 @@ static inline uint64_t cvmx_build_bits(uint64_t high_bit,
return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit;
}
enum cvmx_mips_space {
CVMX_MIPS_SPACE_XKSEG = 3LL,
CVMX_MIPS_SPACE_XKPHYS = 2LL,
CVMX_MIPS_SPACE_XSSEG = 1LL,
CVMX_MIPS_SPACE_XUSEG = 0LL
};
/* These macros for use when using 32 bit pointers. */
#define CVMX_MIPS32_SPACE_KSEG0 1l
#define CVMX_ADD_SEG32(segment, add) \
(((int32_t)segment << 31) | (int32_t)(add))
#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
/* These macros simplify the process of creating common IO addresses */
#define CVMX_ADD_SEG(segment, add) \
((((uint64_t)segment) << 62) | (add))
#ifndef CVMX_ADD_IO_SEG
#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
#endif
/**
* Convert a memory pointer (void*) into a hardware compatible
* memory address (uint64_t). Octeon hardware widgets don't

114
arch/mips/include/asm/octeon/octeon-feature.h
View File

@ -31,8 +31,14 @@
#ifndef __OCTEON_FEATURE_H__
#define __OCTEON_FEATURE_H__
#include <asm/octeon/cvmx-mio-defs.h>
#include <asm/octeon/cvmx-rnm-defs.h>
enum octeon_feature {
/* CN68XX uses port kinds for packet interface */
OCTEON_FEATURE_PKND,
/* CN68XX has different fields in word0 - word2 */
OCTEON_FEATURE_CN68XX_WQE,
/*
* Octeon models in the CN5XXX family and higher support
* atomic add instructions to memory (saa/saad).
@ -42,8 +48,13 @@ enum octeon_feature {
OCTEON_FEATURE_ZIP,
/* Does this Octeon support crypto acceleration using COP2? */
OCTEON_FEATURE_CRYPTO,
OCTEON_FEATURE_DORM_CRYPTO,
/* Does this Octeon support PCI express? */
OCTEON_FEATURE_PCIE,
/* Does this Octeon support SRIOs */
OCTEON_FEATURE_SRIO,
/* Does this Octeon support Interlaken */
OCTEON_FEATURE_ILK,
/* Some Octeon models support internal memory for storing
* cryptographic keys */
OCTEON_FEATURE_KEY_MEMORY,
@ -64,6 +75,15 @@ enum octeon_feature {
/* Octeon MDIO block supports clause 45 transactions for 10
* Gig support */
OCTEON_FEATURE_MDIO_CLAUSE_45,
/*
* CN52XX and CN56XX used a block named NPEI for PCIe
* access. Newer chips replaced this with SLI+DPI.
*/
OCTEON_FEATURE_NPEI,
OCTEON_FEATURE_HFA,
OCTEON_FEATURE_DFM,
OCTEON_FEATURE_CIU2,
OCTEON_MAX_FEATURE
};
static inline int cvmx_fuse_read(int fuse);
@ -96,30 +116,78 @@ static inline int octeon_has_feature(enum octeon_feature feature)
return !cvmx_fuse_read(121);
case OCTEON_FEATURE_CRYPTO:
return !cvmx_fuse_read(90);
if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
union cvmx_mio_fus_dat2 fus_2;
fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
if (fus_2.s.nocrypto || fus_2.s.nomul) {
return 0;
} else if (!fus_2.s.dorm_crypto) {
return 1;
} else {
union cvmx_rnm_ctl_status st;
st.u64 = cvmx_read_csr(CVMX_RNM_CTL_STATUS);
return st.s.eer_val;
}
} else {
return !cvmx_fuse_read(90);
}
case OCTEON_FEATURE_DORM_CRYPTO:
if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
union cvmx_mio_fus_dat2 fus_2;
fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
return !fus_2.s.nocrypto && !fus_2.s.nomul && fus_2.s.dorm_crypto;
} else {
return 0;
}
case OCTEON_FEATURE_PCIE:
case OCTEON_FEATURE_MGMT_PORT:
case OCTEON_FEATURE_RAID:
return OCTEON_IS_MODEL(OCTEON_CN56XX)
|| OCTEON_IS_MODEL(OCTEON_CN52XX);
|| OCTEON_IS_MODEL(OCTEON_CN52XX)
|| OCTEON_IS_MODEL(OCTEON_CN6XXX);
case OCTEON_FEATURE_SRIO:
return OCTEON_IS_MODEL(OCTEON_CN63XX)
|| OCTEON_IS_MODEL(OCTEON_CN66XX);
case OCTEON_FEATURE_ILK:
return (OCTEON_IS_MODEL(OCTEON_CN68XX));
case OCTEON_FEATURE_KEY_MEMORY:
return OCTEON_IS_MODEL(OCTEON_CN38XX)
|| OCTEON_IS_MODEL(OCTEON_CN58XX)
|| OCTEON_IS_MODEL(OCTEON_CN56XX)
|| OCTEON_IS_MODEL(OCTEON_CN6XXX);
case OCTEON_FEATURE_LED_CONTROLLER:
return OCTEON_IS_MODEL(OCTEON_CN38XX)
|| OCTEON_IS_MODEL(OCTEON_CN58XX)
|| OCTEON_IS_MODEL(OCTEON_CN56XX);
case OCTEON_FEATURE_TRA:
return !(OCTEON_IS_MODEL(OCTEON_CN30XX)
|| OCTEON_IS_MODEL(OCTEON_CN50XX));
case OCTEON_FEATURE_MGMT_PORT:
return OCTEON_IS_MODEL(OCTEON_CN56XX)
|| OCTEON_IS_MODEL(OCTEON_CN52XX)
|| OCTEON_IS_MODEL(OCTEON_CN6XXX);
case OCTEON_FEATURE_RAID:
return OCTEON_IS_MODEL(OCTEON_CN56XX)
|| OCTEON_IS_MODEL(OCTEON_CN52XX)
|| OCTEON_IS_MODEL(OCTEON_CN6XXX);
case OCTEON_FEATURE_USB:
return !(OCTEON_IS_MODEL(OCTEON_CN38XX)
|| OCTEON_IS_MODEL(OCTEON_CN58XX));
case OCTEON_FEATURE_NO_WPTR:
return (OCTEON_IS_MODEL(OCTEON_CN56XX)
|| OCTEON_IS_MODEL(OCTEON_CN52XX))
&& !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
&& !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X);
|| OCTEON_IS_MODEL(OCTEON_CN52XX)
|| OCTEON_IS_MODEL(OCTEON_CN6XXX))
&& !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
&& !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X);
case OCTEON_FEATURE_DFA:
if (!OCTEON_IS_MODEL(OCTEON_CN38XX)
&& !OCTEON_IS_MODEL(OCTEON_CN31XX)
@ -127,14 +195,42 @@ static inline int octeon_has_feature(enum octeon_feature feature)
return 0;
else if (OCTEON_IS_MODEL(OCTEON_CN3020))
return 0;
else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
return 1;
else
return !cvmx_fuse_read(120);
case OCTEON_FEATURE_HFA:
if (!OCTEON_IS_MODEL(OCTEON_CN6XXX))
return 0;
else
return !cvmx_fuse_read(90);
case OCTEON_FEATURE_DFM:
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)
|| OCTEON_IS_MODEL(OCTEON_CN66XX)))
return 0;
else
return !cvmx_fuse_read(90);
case OCTEON_FEATURE_MDIO_CLAUSE_45:
return !(OCTEON_IS_MODEL(OCTEON_CN3XXX)
|| OCTEON_IS_MODEL(OCTEON_CN58XX)
|| OCTEON_IS_MODEL(OCTEON_CN50XX));
case OCTEON_FEATURE_NPEI:
return OCTEON_IS_MODEL(OCTEON_CN56XX)
|| OCTEON_IS_MODEL(OCTEON_CN52XX);
case OCTEON_FEATURE_PKND:
return OCTEON_IS_MODEL(OCTEON_CN68XX);
case OCTEON_FEATURE_CN68XX_WQE:
return OCTEON_IS_MODEL(OCTEON_CN68XX);
case OCTEON_FEATURE_CIU2:
return OCTEON_IS_MODEL(OCTEON_CN68XX);
default:
break;
}
return 0;
}