Merge branch 'pci/controller/microchip'
- Fix DED and SEC interrupt bit offsets so interrupt handlers work correctly (Daire McNamara) - Make driver buildable as a module (Daire McNamara) - Reorganize register #defines to align with hardware docs (Daire McNamara) - Tweak register accessors to simplify callers (Daire McNamara) - Refactor interrupt initialisation (Daire McNamara) - Read FPGA MSI configuration parameters from hardware instead of hard-coding them (Daire McNamara) - Re-partition code between probe() and init() (Daire McNamara) * pci/controller/microchip: PCI: microchip: Re-partition code between probe() and init() PCI: microchip: Gather MSI information from hardware config registers PCI: microchip: Clean up initialisation of interrupts PCI: microchip: Enable event handlers to access bridge and control pointers PCI: microchip: Align register, offset, and mask names with HW docs PCI: microchip: Enable building driver as a module PCI: microchip: Correct the DED and SEC interrupt bit offsets
This commit is contained in:
Bjorn Helgaas
commit
26d7492618
@ -217,7 +217,7 @@ config PCIE_MT7621
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This selects a driver for the MediaTek MT7621 PCIe Controller.
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config PCIE_MICROCHIP_HOST
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bool "Microchip AXI PCIe controller"
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tristate "Microchip AXI PCIe controller"
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depends on PCI_MSI && OF
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select PCI_HOST_COMMON
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help
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@ -7,6 +7,7 @@
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* Author: Daire McNamara <daire.mcnamara@microchip.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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@ -20,8 +21,7 @@
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#include "../pci.h"
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/* Number of MSI IRQs */
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#define MC_NUM_MSI_IRQS 32
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#define MC_NUM_MSI_IRQS_CODED 5
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#define MC_MAX_NUM_MSI_IRQS 32
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/* PCIe Bridge Phy and Controller Phy offsets */
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#define MC_PCIE1_BRIDGE_ADDR 0x00008000u
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@ -30,65 +30,11 @@
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#define MC_PCIE_BRIDGE_ADDR (MC_PCIE1_BRIDGE_ADDR)
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#define MC_PCIE_CTRL_ADDR (MC_PCIE1_CTRL_ADDR)
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/* PCIe Controller Phy Regs */
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#define SEC_ERROR_CNT 0x20
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#define DED_ERROR_CNT 0x24
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#define SEC_ERROR_INT 0x28
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#define SEC_ERROR_INT_TX_RAM_SEC_ERR_INT GENMASK(3, 0)
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#define SEC_ERROR_INT_RX_RAM_SEC_ERR_INT GENMASK(7, 4)
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#define SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT GENMASK(11, 8)
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#define SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT GENMASK(15, 12)
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#define NUM_SEC_ERROR_INTS (4)
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#define SEC_ERROR_INT_MASK 0x2c
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#define DED_ERROR_INT 0x30
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#define DED_ERROR_INT_TX_RAM_DED_ERR_INT GENMASK(3, 0)
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#define DED_ERROR_INT_RX_RAM_DED_ERR_INT GENMASK(7, 4)
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#define DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT GENMASK(11, 8)
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#define DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT GENMASK(15, 12)
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#define NUM_DED_ERROR_INTS (4)
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#define DED_ERROR_INT_MASK 0x34
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#define ECC_CONTROL 0x38
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#define ECC_CONTROL_TX_RAM_INJ_ERROR_0 BIT(0)
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#define ECC_CONTROL_TX_RAM_INJ_ERROR_1 BIT(1)
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#define ECC_CONTROL_TX_RAM_INJ_ERROR_2 BIT(2)
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#define ECC_CONTROL_TX_RAM_INJ_ERROR_3 BIT(3)
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#define ECC_CONTROL_RX_RAM_INJ_ERROR_0 BIT(4)
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#define ECC_CONTROL_RX_RAM_INJ_ERROR_1 BIT(5)
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#define ECC_CONTROL_RX_RAM_INJ_ERROR_2 BIT(6)
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#define ECC_CONTROL_RX_RAM_INJ_ERROR_3 BIT(7)
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#define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_0 BIT(8)
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#define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_1 BIT(9)
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#define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_2 BIT(10)
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#define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_3 BIT(11)
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#define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_0 BIT(12)
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#define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_1 BIT(13)
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#define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_2 BIT(14)
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#define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_3 BIT(15)
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#define ECC_CONTROL_TX_RAM_ECC_BYPASS BIT(24)
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#define ECC_CONTROL_RX_RAM_ECC_BYPASS BIT(25)
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#define ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS BIT(26)
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#define ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS BIT(27)
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#define LTSSM_STATE 0x5c
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#define LTSSM_L0_STATE 0x10
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#define PCIE_EVENT_INT 0x14c
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#define PCIE_EVENT_INT_L2_EXIT_INT BIT(0)
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#define PCIE_EVENT_INT_HOTRST_EXIT_INT BIT(1)
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#define PCIE_EVENT_INT_DLUP_EXIT_INT BIT(2)
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#define PCIE_EVENT_INT_MASK GENMASK(2, 0)
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#define PCIE_EVENT_INT_L2_EXIT_INT_MASK BIT(16)
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#define PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK BIT(17)
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#define PCIE_EVENT_INT_DLUP_EXIT_INT_MASK BIT(18)
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#define PCIE_EVENT_INT_ENB_MASK GENMASK(18, 16)
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#define PCIE_EVENT_INT_ENB_SHIFT 16
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#define NUM_PCIE_EVENTS (3)
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/* PCIe Bridge Phy Regs */
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#define PCIE_PCI_IDS_DW1 0x9c
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/* PCIe Config space MSI capability structure */
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#define MC_MSI_CAP_CTRL_OFFSET 0xe0u
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#define MC_MSI_MAX_Q_AVAIL (MC_NUM_MSI_IRQS_CODED << 1)
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#define MC_MSI_Q_SIZE (MC_NUM_MSI_IRQS_CODED << 4)
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#define PCIE_PCI_IRQ_DW0 0xa8
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#define MSIX_CAP_MASK BIT(31)
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#define NUM_MSI_MSGS_MASK GENMASK(6, 4)
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#define NUM_MSI_MSGS_SHIFT 4
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#define IMASK_LOCAL 0x180
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#define DMA_END_ENGINE_0_MASK 0x00000000u
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@ -137,7 +83,7 @@
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#define ISTATUS_LOCAL 0x184
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#define IMASK_HOST 0x188
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#define ISTATUS_HOST 0x18c
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#define MSI_ADDR 0x190
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#define IMSI_ADDR 0x190
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#define ISTATUS_MSI 0x194
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/* PCIe Master table init defines */
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@ -162,17 +108,73 @@
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#define ATR_ENTRY_SIZE 32
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/* PCIe Controller Phy Regs */
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#define SEC_ERROR_EVENT_CNT 0x20
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#define DED_ERROR_EVENT_CNT 0x24
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#define SEC_ERROR_INT 0x28
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#define SEC_ERROR_INT_TX_RAM_SEC_ERR_INT GENMASK(3, 0)
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#define SEC_ERROR_INT_RX_RAM_SEC_ERR_INT GENMASK(7, 4)
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#define SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT GENMASK(11, 8)
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#define SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT GENMASK(15, 12)
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#define SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT GENMASK(15, 0)
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#define NUM_SEC_ERROR_INTS (4)
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#define SEC_ERROR_INT_MASK 0x2c
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#define DED_ERROR_INT 0x30
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#define DED_ERROR_INT_TX_RAM_DED_ERR_INT GENMASK(3, 0)
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#define DED_ERROR_INT_RX_RAM_DED_ERR_INT GENMASK(7, 4)
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#define DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT GENMASK(11, 8)
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#define DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT GENMASK(15, 12)
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#define DED_ERROR_INT_ALL_RAM_DED_ERR_INT GENMASK(15, 0)
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#define NUM_DED_ERROR_INTS (4)
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#define DED_ERROR_INT_MASK 0x34
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#define ECC_CONTROL 0x38
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#define ECC_CONTROL_TX_RAM_INJ_ERROR_0 BIT(0)
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#define ECC_CONTROL_TX_RAM_INJ_ERROR_1 BIT(1)
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#define ECC_CONTROL_TX_RAM_INJ_ERROR_2 BIT(2)
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#define ECC_CONTROL_TX_RAM_INJ_ERROR_3 BIT(3)
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#define ECC_CONTROL_RX_RAM_INJ_ERROR_0 BIT(4)
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#define ECC_CONTROL_RX_RAM_INJ_ERROR_1 BIT(5)
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#define ECC_CONTROL_RX_RAM_INJ_ERROR_2 BIT(6)
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#define ECC_CONTROL_RX_RAM_INJ_ERROR_3 BIT(7)
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#define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_0 BIT(8)
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#define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_1 BIT(9)
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#define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_2 BIT(10)
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#define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_3 BIT(11)
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#define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_0 BIT(12)
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#define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_1 BIT(13)
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#define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_2 BIT(14)
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#define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_3 BIT(15)
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#define ECC_CONTROL_TX_RAM_ECC_BYPASS BIT(24)
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#define ECC_CONTROL_RX_RAM_ECC_BYPASS BIT(25)
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#define ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS BIT(26)
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#define ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS BIT(27)
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#define PCIE_EVENT_INT 0x14c
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#define PCIE_EVENT_INT_L2_EXIT_INT BIT(0)
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#define PCIE_EVENT_INT_HOTRST_EXIT_INT BIT(1)
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#define PCIE_EVENT_INT_DLUP_EXIT_INT BIT(2)
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#define PCIE_EVENT_INT_MASK GENMASK(2, 0)
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#define PCIE_EVENT_INT_L2_EXIT_INT_MASK BIT(16)
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#define PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK BIT(17)
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#define PCIE_EVENT_INT_DLUP_EXIT_INT_MASK BIT(18)
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#define PCIE_EVENT_INT_ENB_MASK GENMASK(18, 16)
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#define PCIE_EVENT_INT_ENB_SHIFT 16
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#define NUM_PCIE_EVENTS (3)
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/* PCIe Config space MSI capability structure */
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#define MC_MSI_CAP_CTRL_OFFSET 0xe0u
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/* Events */
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#define EVENT_PCIE_L2_EXIT 0
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#define EVENT_PCIE_HOTRST_EXIT 1
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#define EVENT_PCIE_DLUP_EXIT 2
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#define EVENT_SEC_TX_RAM_SEC_ERR 3
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#define EVENT_SEC_RX_RAM_SEC_ERR 4
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#define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR 5
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#define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR 6
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#define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR 5
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#define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR 6
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#define EVENT_DED_TX_RAM_DED_ERR 7
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#define EVENT_DED_RX_RAM_DED_ERR 8
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#define EVENT_DED_AXI2PCIE_RAM_DED_ERR 9
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#define EVENT_DED_PCIE2AXI_RAM_DED_ERR 10
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#define EVENT_DED_PCIE2AXI_RAM_DED_ERR 9
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#define EVENT_DED_AXI2PCIE_RAM_DED_ERR 10
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#define EVENT_LOCAL_DMA_END_ENGINE_0 11
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#define EVENT_LOCAL_DMA_END_ENGINE_1 12
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#define EVENT_LOCAL_DMA_ERROR_ENGINE_0 13
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@ -259,7 +261,7 @@ struct mc_msi {
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struct irq_domain *dev_domain;
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u32 num_vectors;
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u64 vector_phy;
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DECLARE_BITMAP(used, MC_NUM_MSI_IRQS);
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DECLARE_BITMAP(used, MC_MAX_NUM_MSI_IRQS);
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};
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struct mc_pcie {
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@ -382,25 +384,29 @@ static struct {
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static char poss_clks[][5] = { "fic0", "fic1", "fic2", "fic3" };
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static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *base)
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static struct mc_pcie *port;
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static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *ecam)
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{
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struct mc_msi *msi = &port->msi;
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u32 cap_offset = MC_MSI_CAP_CTRL_OFFSET;
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u16 msg_ctrl = readw_relaxed(base + cap_offset + PCI_MSI_FLAGS);
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u16 reg;
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u8 queue_size;
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msg_ctrl |= PCI_MSI_FLAGS_ENABLE;
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msg_ctrl &= ~PCI_MSI_FLAGS_QMASK;
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msg_ctrl |= MC_MSI_MAX_Q_AVAIL;
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msg_ctrl &= ~PCI_MSI_FLAGS_QSIZE;
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msg_ctrl |= MC_MSI_Q_SIZE;
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msg_ctrl |= PCI_MSI_FLAGS_64BIT;
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/* Fixup MSI enable flag */
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reg = readw_relaxed(ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS);
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reg |= PCI_MSI_FLAGS_ENABLE;
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writew_relaxed(reg, ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS);
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writew_relaxed(msg_ctrl, base + cap_offset + PCI_MSI_FLAGS);
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/* Fixup PCI MSI queue flags */
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queue_size = FIELD_GET(PCI_MSI_FLAGS_QMASK, reg);
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reg |= FIELD_PREP(PCI_MSI_FLAGS_QSIZE, queue_size);
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writew_relaxed(reg, ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS);
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/* Fixup MSI addr fields */
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writel_relaxed(lower_32_bits(msi->vector_phy),
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base + cap_offset + PCI_MSI_ADDRESS_LO);
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ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_ADDRESS_LO);
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writel_relaxed(upper_32_bits(msi->vector_phy),
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base + cap_offset + PCI_MSI_ADDRESS_HI);
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ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_ADDRESS_HI);
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}
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static void mc_handle_msi(struct irq_desc *desc)
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@ -473,10 +479,7 @@ static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
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{
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struct mc_pcie *port = domain->host_data;
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struct mc_msi *msi = &port->msi;
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void __iomem *bridge_base_addr =
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port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
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unsigned long bit;
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u32 val;
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mutex_lock(&msi->lock);
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bit = find_first_zero_bit(msi->used, msi->num_vectors);
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@ -490,11 +493,6 @@ static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
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irq_domain_set_info(domain, virq, bit, &mc_msi_bottom_irq_chip,
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domain->host_data, handle_edge_irq, NULL, NULL);
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/* Enable MSI interrupts */
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val = readl_relaxed(bridge_base_addr + IMASK_LOCAL);
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val |= PM_MSI_INT_MSI_MASK;
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writel_relaxed(val, bridge_base_addr + IMASK_LOCAL);
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mutex_unlock(&msi->lock);
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return 0;
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@ -656,9 +654,10 @@ static inline u32 reg_to_event(u32 reg, struct event_map field)
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return (reg & field.reg_mask) ? BIT(field.event_bit) : 0;
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}
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static u32 pcie_events(void __iomem *addr)
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static u32 pcie_events(struct mc_pcie *port)
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{
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u32 reg = readl_relaxed(addr);
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void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
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u32 reg = readl_relaxed(ctrl_base_addr + PCIE_EVENT_INT);
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u32 val = 0;
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int i;
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@ -668,9 +667,10 @@ static u32 pcie_events(void __iomem *addr)
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return val;
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}
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static u32 sec_errors(void __iomem *addr)
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static u32 sec_errors(struct mc_pcie *port)
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{
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u32 reg = readl_relaxed(addr);
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void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
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u32 reg = readl_relaxed(ctrl_base_addr + SEC_ERROR_INT);
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u32 val = 0;
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int i;
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@ -680,9 +680,10 @@ static u32 sec_errors(void __iomem *addr)
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return val;
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}
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static u32 ded_errors(void __iomem *addr)
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static u32 ded_errors(struct mc_pcie *port)
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{
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u32 reg = readl_relaxed(addr);
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void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
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u32 reg = readl_relaxed(ctrl_base_addr + DED_ERROR_INT);
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u32 val = 0;
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int i;
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@ -692,9 +693,10 @@ static u32 ded_errors(void __iomem *addr)
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return val;
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}
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static u32 local_events(void __iomem *addr)
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static u32 local_events(struct mc_pcie *port)
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{
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u32 reg = readl_relaxed(addr);
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void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
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u32 reg = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL);
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u32 val = 0;
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int i;
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@ -706,15 +708,12 @@ static u32 local_events(void __iomem *addr)
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static u32 get_events(struct mc_pcie *port)
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{
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void __iomem *bridge_base_addr =
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port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
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void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
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u32 events = 0;
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events |= pcie_events(ctrl_base_addr + PCIE_EVENT_INT);
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events |= sec_errors(ctrl_base_addr + SEC_ERROR_INT);
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events |= ded_errors(ctrl_base_addr + DED_ERROR_INT);
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events |= local_events(bridge_base_addr + ISTATUS_LOCAL);
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events |= pcie_events(port);
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events |= sec_errors(port);
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events |= ded_errors(port);
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events |= local_events(port);
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return events;
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}
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@ -987,39 +986,73 @@ static int mc_pcie_setup_windows(struct platform_device *pdev,
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return 0;
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}
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static int mc_platform_init(struct pci_config_window *cfg)
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static inline void mc_clear_secs(struct mc_pcie *port)
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{
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struct device *dev = cfg->parent;
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struct platform_device *pdev = to_platform_device(dev);
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struct mc_pcie *port;
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void __iomem *bridge_base_addr;
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void __iomem *ctrl_base_addr;
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int ret;
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void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
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|
||||
writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT, ctrl_base_addr +
|
||||
SEC_ERROR_INT);
|
||||
writel_relaxed(0, ctrl_base_addr + SEC_ERROR_EVENT_CNT);
|
||||
}
|
||||
|
||||
static inline void mc_clear_deds(struct mc_pcie *port)
|
||||
{
|
||||
void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
|
||||
|
||||
writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT, ctrl_base_addr +
|
||||
DED_ERROR_INT);
|
||||
writel_relaxed(0, ctrl_base_addr + DED_ERROR_EVENT_CNT);
|
||||
}
|
||||
|
||||
static void mc_disable_interrupts(struct mc_pcie *port)
|
||||
{
|
||||
void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
|
||||
void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
|
||||
u32 val;
|
||||
|
||||
/* Ensure ECC bypass is enabled */
|
||||
val = ECC_CONTROL_TX_RAM_ECC_BYPASS |
|
||||
ECC_CONTROL_RX_RAM_ECC_BYPASS |
|
||||
ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS |
|
||||
ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS;
|
||||
writel_relaxed(val, ctrl_base_addr + ECC_CONTROL);
|
||||
|
||||
/* Disable SEC errors and clear any outstanding */
|
||||
writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT, ctrl_base_addr +
|
||||
SEC_ERROR_INT_MASK);
|
||||
mc_clear_secs(port);
|
||||
|
||||
/* Disable DED errors and clear any outstanding */
|
||||
writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT, ctrl_base_addr +
|
||||
DED_ERROR_INT_MASK);
|
||||
mc_clear_deds(port);
|
||||
|
||||
/* Disable local interrupts and clear any outstanding */
|
||||
writel_relaxed(0, bridge_base_addr + IMASK_LOCAL);
|
||||
writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_LOCAL);
|
||||
writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_MSI);
|
||||
|
||||
/* Disable PCIe events and clear any outstanding */
|
||||
val = PCIE_EVENT_INT_L2_EXIT_INT |
|
||||
PCIE_EVENT_INT_HOTRST_EXIT_INT |
|
||||
PCIE_EVENT_INT_DLUP_EXIT_INT |
|
||||
PCIE_EVENT_INT_L2_EXIT_INT_MASK |
|
||||
PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK |
|
||||
PCIE_EVENT_INT_DLUP_EXIT_INT_MASK;
|
||||
writel_relaxed(val, ctrl_base_addr + PCIE_EVENT_INT);
|
||||
|
||||
/* Disable host interrupts and clear any outstanding */
|
||||
writel_relaxed(0, bridge_base_addr + IMASK_HOST);
|
||||
writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST);
|
||||
}
|
||||
|
||||
static int mc_init_interrupts(struct platform_device *pdev, struct mc_pcie *port)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
int irq;
|
||||
int i, intx_irq, msi_irq, event_irq;
|
||||
u32 val;
|
||||
int err;
|
||||
int ret;
|
||||
|
||||
port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
|
||||
if (!port)
|
||||
return -ENOMEM;
|
||||
port->dev = dev;
|
||||
|
||||
ret = mc_pcie_init_clks(dev);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to get clock resources, error %d\n", ret);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
port->axi_base_addr = devm_platform_ioremap_resource(pdev, 1);
|
||||
if (IS_ERR(port->axi_base_addr))
|
||||
return PTR_ERR(port->axi_base_addr);
|
||||
|
||||
bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
|
||||
ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
|
||||
|
||||
port->msi.vector_phy = MSI_ADDR;
|
||||
port->msi.num_vectors = MC_NUM_MSI_IRQS;
|
||||
ret = mc_pcie_init_irq_domains(port);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed creating IRQ domains\n");
|
||||
@ -1037,11 +1070,11 @@ static int mc_platform_init(struct pci_config_window *cfg)
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
err = devm_request_irq(dev, event_irq, mc_event_handler,
|
||||
ret = devm_request_irq(dev, event_irq, mc_event_handler,
|
||||
0, event_cause[i].sym, port);
|
||||
if (err) {
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to request IRQ %d\n", event_irq);
|
||||
return err;
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
@ -1066,44 +1099,81 @@ static int mc_platform_init(struct pci_config_window *cfg)
|
||||
/* Plug the main event chained handler */
|
||||
irq_set_chained_handler_and_data(irq, mc_handle_event, port);
|
||||
|
||||
/* Hardware doesn't setup MSI by default */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mc_platform_init(struct pci_config_window *cfg)
|
||||
{
|
||||
struct device *dev = cfg->parent;
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
void __iomem *bridge_base_addr =
|
||||
port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
|
||||
int ret;
|
||||
|
||||
/* Configure address translation table 0 for PCIe config space */
|
||||
mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start,
|
||||
cfg->res.start,
|
||||
resource_size(&cfg->res));
|
||||
|
||||
/* Need some fixups in config space */
|
||||
mc_pcie_enable_msi(port, cfg->win);
|
||||
|
||||
val = readl_relaxed(bridge_base_addr + IMASK_LOCAL);
|
||||
val |= PM_MSI_INT_INTX_MASK;
|
||||
writel_relaxed(val, bridge_base_addr + IMASK_LOCAL);
|
||||
/* Configure non-config space outbound ranges */
|
||||
ret = mc_pcie_setup_windows(pdev, port);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
writel_relaxed(val, ctrl_base_addr + ECC_CONTROL);
|
||||
/* Address translation is up; safe to enable interrupts */
|
||||
ret = mc_init_interrupts(pdev, port);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
val = PCIE_EVENT_INT_L2_EXIT_INT |
|
||||
PCIE_EVENT_INT_HOTRST_EXIT_INT |
|
||||
PCIE_EVENT_INT_DLUP_EXIT_INT;
|
||||
writel_relaxed(val, ctrl_base_addr + PCIE_EVENT_INT);
|
||||
return 0;
|
||||
}
|
||||
|
||||
val = SEC_ERROR_INT_TX_RAM_SEC_ERR_INT |
|
||||
SEC_ERROR_INT_RX_RAM_SEC_ERR_INT |
|
||||
SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT |
|
||||
SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT;
|
||||
writel_relaxed(val, ctrl_base_addr + SEC_ERROR_INT);
|
||||
writel_relaxed(0, ctrl_base_addr + SEC_ERROR_INT_MASK);
|
||||
writel_relaxed(0, ctrl_base_addr + SEC_ERROR_CNT);
|
||||
static int mc_host_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
void __iomem *bridge_base_addr;
|
||||
int ret;
|
||||
u32 val;
|
||||
|
||||
val = DED_ERROR_INT_TX_RAM_DED_ERR_INT |
|
||||
DED_ERROR_INT_RX_RAM_DED_ERR_INT |
|
||||
DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT |
|
||||
DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT;
|
||||
writel_relaxed(val, ctrl_base_addr + DED_ERROR_INT);
|
||||
writel_relaxed(0, ctrl_base_addr + DED_ERROR_INT_MASK);
|
||||
writel_relaxed(0, ctrl_base_addr + DED_ERROR_CNT);
|
||||
port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
|
||||
if (!port)
|
||||
return -ENOMEM;
|
||||
|
||||
writel_relaxed(0, bridge_base_addr + IMASK_HOST);
|
||||
writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST);
|
||||
port->dev = dev;
|
||||
|
||||
/* Configure Address Translation Table 0 for PCIe config space */
|
||||
mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & 0xffffffff,
|
||||
cfg->res.start, resource_size(&cfg->res));
|
||||
port->axi_base_addr = devm_platform_ioremap_resource(pdev, 1);
|
||||
if (IS_ERR(port->axi_base_addr))
|
||||
return PTR_ERR(port->axi_base_addr);
|
||||
|
||||
return mc_pcie_setup_windows(pdev, port);
|
||||
mc_disable_interrupts(port);
|
||||
|
||||
bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
|
||||
|
||||
/* Allow enabling MSI by disabling MSI-X */
|
||||
val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0);
|
||||
val &= ~MSIX_CAP_MASK;
|
||||
writel(val, bridge_base_addr + PCIE_PCI_IRQ_DW0);
|
||||
|
||||
/* Pick num vectors from bitfile programmed onto FPGA fabric */
|
||||
val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0);
|
||||
val &= NUM_MSI_MSGS_MASK;
|
||||
val >>= NUM_MSI_MSGS_SHIFT;
|
||||
|
||||
port->msi.num_vectors = 1 << val;
|
||||
|
||||
/* Pick vector address from design */
|
||||
port->msi.vector_phy = readl_relaxed(bridge_base_addr + IMSI_ADDR);
|
||||
|
||||
ret = mc_pcie_init_clks(dev);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to get clock resources, error %d\n", ret);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
return pci_host_common_probe(pdev);
|
||||
}
|
||||
|
||||
static const struct pci_ecam_ops mc_ecam_ops = {
|
||||
@ -1126,7 +1196,7 @@ static const struct of_device_id mc_pcie_of_match[] = {
|
||||
MODULE_DEVICE_TABLE(of, mc_pcie_of_match);
|
||||
|
||||
static struct platform_driver mc_pcie_driver = {
|
||||
.probe = pci_host_common_probe,
|
||||
.probe = mc_host_probe,
|
||||
.driver = {
|
||||
.name = "microchip-pcie",
|
||||
.of_match_table = mc_pcie_of_match,
|
||||
@ -1135,5 +1205,6 @@ static struct platform_driver mc_pcie_driver = {
|
||||
};
|
||||
|
||||
builtin_platform_driver(mc_pcie_driver);
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DESCRIPTION("Microchip PCIe host controller driver");
|
||||
MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user