drm/msm: Add proper checks for GPU LLCC support
Domain attribute setting for LLCC is guarded by !IS_ERR check which works fine only when CONFIG_QCOM_LLCC=y but when it is disabled, the LLCC apis return NULL and that is not handled by IS_ERR check. Due to this, domain attribute for LLCC will be set even on GPUs which do not support it and cause issues, so correct this by using IS_ERR_OR_NULL checks appropriately. Meanwhile also cleanup comment block and remove unwanted blank line. Fixes: 00fd44a1a470 ("drm/msm: Only enable A6xx LLCC code on A6xx") Fixes: 474dadb8b0d5 ("drm/msm/a6xx: Add support for using system cache(LLC)") Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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@ -1118,7 +1118,7 @@ static void a6xx_llc_slices_init(struct platform_device *pdev,
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a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU);
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a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW);
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if (IS_ERR(a6xx_gpu->llc_slice) && IS_ERR(a6xx_gpu->htw_llc_slice))
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if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
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a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
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}
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@ -200,15 +200,15 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu,
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if (!iommu)
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return NULL;
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if (adreno_is_a6xx(adreno_gpu)) {
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struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
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struct io_pgtable_domain_attr pgtbl_cfg;
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/*
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* This allows GPU to set the bus attributes required to use system
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* cache on behalf of the iommu page table walker.
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*/
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if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
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* This allows GPU to set the bus attributes required to use system
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* cache on behalf of the iommu page table walker.
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*/
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if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) {
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pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
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iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG, &pgtbl_cfg);
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}
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