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Linux 3.15-rc1

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Merge tag 'v3.15-rc1' into patchwork

Linux 3.15-rc1

* tag 'v3.15-rc1': (12180 commits)
  Linux 3.15-rc1
  mm: Initialize error in shmem_file_aio_read()
  cifs: Use min_t() when comparing "size_t" and "unsigned long"
  sym53c8xx_2: Set DID_REQUEUE return code when aborting squeue
  powerpc: Don't try to set LPCR unless we're in hypervisor mode
  futex: update documentation for ordering guarantees
  ceph: fix pr_fmt() redefinition
  vti: don't allow to add the same tunnel twice
  gre: don't allow to add the same tunnel twice
  drivers: net: xen-netfront: fix array initialization bug
  missing bits of "splice: fix racy pipe->buffers uses"
  cifs: fix the race in cifs_writev()
  ceph_sync_{,direct_}write: fix an oops on ceph_osdc_new_request() failure
  pktgen: be friendly to LLTX devices
  r8152: check RTL8152_UNPLUG
  net: sun4i-emac: add promiscuous support
  net/apne: replace IS_ERR and PTR_ERR with PTR_ERR_OR_ZERO
  blackfin: cleanup board files
  bf609: clock: drop unused clock bit set/clear functions
  Blackfin: bf537: rename "CONFIG_ADT75"
  ...
This commit is contained in:
Mauro Carvalho Chehab 2014-04-14 12:00:36 -03:00
commit 277a163c83
9634 changed files with 558606 additions and 220526 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
CREDITS
View File

@ -1236,7 +1236,7 @@ E: philip@gladstonefamily.net
D: Kernel / timekeeping stuff
S: Carlisle, MA 01741
S: USA
N: Jan-Benedict Glaw
E: jbglaw@lug-owl.de
D: SRM environment driver (for Alpha systems)
@ -2567,10 +2567,14 @@ S: 22 Seaview St
S: Fullarton 5063
S: South Australia
N. Wolfgang Muees
N: Wolfgang Muees
E: wolfgang@iksw-muees.de
D: Auerswald USB driver
N: Paul Mundt
E: paul.mundt@gmail.com
D: SuperH maintainer
N: Ian A. Murdock
E: imurdock@gnu.ai.mit.edu
D: Creator of Debian distribution
@ -2714,6 +2718,9 @@ N: Greg Page
E: gpage@sovereign.org
D: IPX development and support
N: Venkatesh Pallipadi (Venki)
D: x86/HPET
N: David Parsons
E: orc@pell.chi.il.us
D: improved memory detection code.

2
Documentation/00-INDEX
View File

@ -413,8 +413,6 @@ serial-console.txt
- how to set up Linux with a serial line console as the default.
sgi-ioc4.txt
- description of the SGI IOC4 PCI (multi function) device.
sgi-visws.txt
- short blurb on the SGI Visual Workstations.
sh/
- directory with info on porting Linux to a new architecture.
smsc_ece1099.txt

41
Documentation/ABI/stable/sysfs-firmware-opal-dump Normal file
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@ -0,0 +1,41 @@
What: /sys/firmware/opal/dump
Date: Feb 2014
Contact: Stewart Smith <stewart@linux.vnet.ibm.com>
Description:
This directory exposes interfaces for interacting with
the FSP and platform dumps through OPAL firmware interface.
This is only for the powerpc/powernv platform.
initiate_dump: When '1' is written to it,
we will initiate a dump.
Read this file for supported commands.
0xXX-0xYYYY: A directory for dump of type 0xXX and
id 0xYYYY (in hex). The name of this
directory should not be relied upon to
be in this format, only that it's unique
among all dumps. For determining the type
and ID of the dump, use the id and type files.
Do not rely on any particular size of dump
type or dump id.
Each dump has the following files:
id: An ASCII representation of the dump ID
in hex (e.g. '0x01')
type: An ASCII representation of the type of
dump in the format "0x%x %s" with the ID
in hex and a description of the dump type
(or 'unknown').
Type '0xffffffff unknown' is used when
we could not get the type from firmware.
e.g. '0x02 System/Platform Dump'
dump: A binary file containing the dump.
The size of the dump is the size of this file.
acknowledge: When 'ack' is written to this, we will
acknowledge that we've retrieved the
dump to the service processor. It will
then remove it, making the dump
inaccessible.
Reading this file will get a list of
supported actions.

60
Documentation/ABI/stable/sysfs-firmware-opal-elog Normal file
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@ -0,0 +1,60 @@
What: /sys/firmware/opal/elog
Date: Feb 2014
Contact: Stewart Smith <stewart@linux.vnet.ibm.com>
Description:
This directory exposes error log entries retrieved
through the OPAL firmware interface.
Each error log is identified by a unique ID and will
exist until explicitly acknowledged to firmware.
Each log entry has a directory in /sys/firmware/opal/elog.
Log entries may be purged by the service processor
before retrieved by firmware or retrieved/acknowledged by
Linux if there is no room for more log entries.
In the event that Linux has retrieved the log entries
but not explicitly acknowledged them to firmware and
the service processor needs more room for log entries,
the only remaining copy of a log message may be in
Linux.
Typically, a user space daemon will monitor for new
entries, read them out and acknowledge them.
The service processor may be able to store more log
entries than firmware can, so after you acknowledge
an event from Linux you may instantly get another one
from the queue that was generated some time in the past.
The raw log format is a binary format. We currently
do not parse this at all in kernel, leaving it up to
user space to solve the problem. In future, we may
do more parsing in kernel and add more files to make
it easier for simple user space processes to extract
more information.
For each log entry (directory), there are the following
files:
id: An ASCII representation of the ID of the
error log, in hex - e.g. "0x01".
type: An ASCII representation of the type id and
description of the type of error log.
Currently just "0x00 PEL" - platform error log.
In the future there may be additional types.
raw: A read-only binary file that can be read
to get the raw log entry. These are
<16kb, often just hundreds of bytes and
"average" 2kb.
acknowledge: Writing 'ack' to this file will acknowledge
the error log to firmware (and in turn
the service processor, if applicable).
Shortly after acknowledging it, the log
entry will be removed from sysfs.
Reading this file will list the supported
operations (curently just acknowledge).

39
Documentation/ABI/testing/sysfs-block-zram
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@ -43,6 +43,36 @@ Description:
The invalid_io file is read-only and specifies the number of
non-page-size-aligned I/O requests issued to this device.
What: /sys/block/zram<id>/failed_reads
Date: February 2014
Contact: Sergey Senozhatsky <sergey.senozhatsky@gmail.com>
Description:
The failed_reads file is read-only and specifies the number of
failed reads happened on this device.
What: /sys/block/zram<id>/failed_writes
Date: February 2014
Contact: Sergey Senozhatsky <sergey.senozhatsky@gmail.com>
Description:
The failed_writes file is read-only and specifies the number of
failed writes happened on this device.
What: /sys/block/zram<id>/max_comp_streams
Date: February 2014
Contact: Sergey Senozhatsky <sergey.senozhatsky@gmail.com>
Description:
The max_comp_streams file is read-write and specifies the
number of backend's zcomp_strm compression streams (number of
concurrent compress operations).
What: /sys/block/zram<id>/comp_algorithm
Date: February 2014
Contact: Sergey Senozhatsky <sergey.senozhatsky@gmail.com>
Description:
The comp_algorithm file is read-write and lets to show
available and selected compression algorithms, change
compression algorithm selection.
What: /sys/block/zram<id>/notify_free
Date: August 2010
Contact: Nitin Gupta <ngupta@vflare.org>
@ -53,15 +83,6 @@ Description:
is freed. This statistic is applicable only when this disk is
being used as a swap disk.
What: /sys/block/zram<id>/discard
Date: August 2010
Contact: Nitin Gupta <ngupta@vflare.org>
Description:
The discard file is read-only and specifies the number of
discard requests received by this device. These requests
provide information to block device regarding blocks which are
no longer used by filesystem.
What: /sys/block/zram<id>/zero_pages
Date: August 2010
Contact: Nitin Gupta <ngupta@vflare.org>

517
Documentation/ABI/testing/sysfs-bus-event_source-devices-events
View File

@ -57,6 +57,523 @@ What: /sys/devices/cpu/events/PM_1PLUS_PPC_CMPL
/sys/devices/cpu/events/PM_LD_REF_L1
/sys/devices/cpu/events/PM_RUN_CYC
/sys/devices/cpu/events/PM_RUN_INST_CMPL
/sys/devices/cpu/events/PM_IC_DEMAND_L2_BR_ALL
/sys/devices/cpu/events/PM_GCT_UTIL_7_TO_10_SLOTS
/sys/devices/cpu/events/PM_PMC2_SAVED
/sys/devices/cpu/events/PM_VSU0_16FLOP
/sys/devices/cpu/events/PM_MRK_LSU_DERAT_MISS
/sys/devices/cpu/events/PM_MRK_ST_CMPL
/sys/devices/cpu/events/PM_NEST_PAIR3_ADD
/sys/devices/cpu/events/PM_L2_ST_DISP
/sys/devices/cpu/events/PM_L2_CASTOUT_MOD
/sys/devices/cpu/events/PM_ISEG
/sys/devices/cpu/events/PM_MRK_INST_TIMEO
/sys/devices/cpu/events/PM_L2_RCST_DISP_FAIL_ADDR
/sys/devices/cpu/events/PM_LSU1_DC_PREF_STREAM_CONFIRM
/sys/devices/cpu/events/PM_IERAT_WR_64K
/sys/devices/cpu/events/PM_MRK_DTLB_MISS_16M
/sys/devices/cpu/events/PM_IERAT_MISS
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_LMEM
/sys/devices/cpu/events/PM_FLOP
/sys/devices/cpu/events/PM_THRD_PRIO_4_5_CYC
/sys/devices/cpu/events/PM_BR_PRED_TA
/sys/devices/cpu/events/PM_EXT_INT
/sys/devices/cpu/events/PM_VSU_FSQRT_FDIV
/sys/devices/cpu/events/PM_MRK_LD_MISS_EXPOSED_CYC
/sys/devices/cpu/events/PM_LSU1_LDF
/sys/devices/cpu/events/PM_IC_WRITE_ALL
/sys/devices/cpu/events/PM_LSU0_SRQ_STFWD
/sys/devices/cpu/events/PM_PTEG_FROM_RL2L3_MOD
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L31_SHR
/sys/devices/cpu/events/PM_DATA_FROM_L21_MOD
/sys/devices/cpu/events/PM_VSU1_SCAL_DOUBLE_ISSUED
/sys/devices/cpu/events/PM_VSU0_8FLOP
/sys/devices/cpu/events/PM_POWER_EVENT1
/sys/devices/cpu/events/PM_DISP_CLB_HELD_BAL
/sys/devices/cpu/events/PM_VSU1_2FLOP
/sys/devices/cpu/events/PM_LWSYNC_HELD
/sys/devices/cpu/events/PM_PTEG_FROM_DL2L3_SHR
/sys/devices/cpu/events/PM_INST_FROM_L21_MOD
/sys/devices/cpu/events/PM_IERAT_XLATE_WR_16MPLUS
/sys/devices/cpu/events/PM_IC_REQ_ALL
/sys/devices/cpu/events/PM_DSLB_MISS
/sys/devices/cpu/events/PM_L3_MISS
/sys/devices/cpu/events/PM_LSU0_L1_PREF
/sys/devices/cpu/events/PM_VSU_SCALAR_SINGLE_ISSUED
/sys/devices/cpu/events/PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE
/sys/devices/cpu/events/PM_L2_INST
/sys/devices/cpu/events/PM_VSU0_FRSP
/sys/devices/cpu/events/PM_FLUSH_DISP
/sys/devices/cpu/events/PM_PTEG_FROM_L2MISS
/sys/devices/cpu/events/PM_VSU1_DQ_ISSUED
/sys/devices/cpu/events/PM_MRK_DATA_FROM_DMEM
/sys/devices/cpu/events/PM_LSU_FLUSH_ULD
/sys/devices/cpu/events/PM_PTEG_FROM_LMEM
/sys/devices/cpu/events/PM_MRK_DERAT_MISS_16M
/sys/devices/cpu/events/PM_THRD_ALL_RUN_CYC
/sys/devices/cpu/events/PM_MEM0_PREFETCH_DISP
/sys/devices/cpu/events/PM_MRK_STALL_CMPLU_CYC_COUNT
/sys/devices/cpu/events/PM_DATA_FROM_DL2L3_MOD
/sys/devices/cpu/events/PM_VSU_FRSP
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L21_MOD
/sys/devices/cpu/events/PM_PMC1_OVERFLOW
/sys/devices/cpu/events/PM_VSU0_SINGLE
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_L3MISS
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_L31_SHR
/sys/devices/cpu/events/PM_VSU0_VECTOR_SP_ISSUED
/sys/devices/cpu/events/PM_VSU1_FEST
/sys/devices/cpu/events/PM_MRK_INST_DISP
/sys/devices/cpu/events/PM_VSU0_COMPLEX_ISSUED
/sys/devices/cpu/events/PM_LSU1_FLUSH_UST
/sys/devices/cpu/events/PM_FXU_IDLE
/sys/devices/cpu/events/PM_LSU0_FLUSH_ULD
/sys/devices/cpu/events/PM_MRK_DATA_FROM_DL2L3_MOD
/sys/devices/cpu/events/PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC
/sys/devices/cpu/events/PM_LSU1_REJECT_LMQ_FULL
/sys/devices/cpu/events/PM_INST_PTEG_FROM_L21_MOD
/sys/devices/cpu/events/PM_INST_FROM_RL2L3_MOD
/sys/devices/cpu/events/PM_SHL_CREATED
/sys/devices/cpu/events/PM_L2_ST_HIT
/sys/devices/cpu/events/PM_DATA_FROM_DMEM
/sys/devices/cpu/events/PM_L3_LD_MISS
/sys/devices/cpu/events/PM_FXU1_BUSY_FXU0_IDLE
/sys/devices/cpu/events/PM_DISP_CLB_HELD_RES
/sys/devices/cpu/events/PM_L2_SN_SX_I_DONE
/sys/devices/cpu/events/PM_STCX_CMPL
/sys/devices/cpu/events/PM_VSU0_2FLOP
/sys/devices/cpu/events/PM_L3_PREF_MISS
/sys/devices/cpu/events/PM_LSU_SRQ_SYNC_CYC
/sys/devices/cpu/events/PM_LSU_REJECT_ERAT_MISS
/sys/devices/cpu/events/PM_L1_ICACHE_MISS
/sys/devices/cpu/events/PM_LSU1_FLUSH_SRQ
/sys/devices/cpu/events/PM_LD_REF_L1_LSU0
/sys/devices/cpu/events/PM_VSU0_FEST
/sys/devices/cpu/events/PM_VSU_VECTOR_SINGLE_ISSUED
/sys/devices/cpu/events/PM_FREQ_UP
/sys/devices/cpu/events/PM_DATA_FROM_LMEM
/sys/devices/cpu/events/PM_LSU1_LDX
/sys/devices/cpu/events/PM_PMC3_OVERFLOW
/sys/devices/cpu/events/PM_MRK_BR_MPRED
/sys/devices/cpu/events/PM_SHL_MATCH
/sys/devices/cpu/events/PM_MRK_BR_TAKEN
/sys/devices/cpu/events/PM_ISLB_MISS
/sys/devices/cpu/events/PM_DISP_HELD_THERMAL
/sys/devices/cpu/events/PM_INST_PTEG_FROM_RL2L3_SHR
/sys/devices/cpu/events/PM_LSU1_SRQ_STFWD
/sys/devices/cpu/events/PM_PTEG_FROM_DMEM
/sys/devices/cpu/events/PM_VSU_2FLOP
/sys/devices/cpu/events/PM_GCT_FULL_CYC
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L3_CYC
/sys/devices/cpu/events/PM_LSU_SRQ_S0_ALLOC
/sys/devices/cpu/events/PM_MRK_DERAT_MISS_4K
/sys/devices/cpu/events/PM_BR_MPRED_TA
/sys/devices/cpu/events/PM_INST_PTEG_FROM_L2MISS
/sys/devices/cpu/events/PM_DPU_HELD_POWER
/sys/devices/cpu/events/PM_MRK_VSU_FIN
/sys/devices/cpu/events/PM_LSU_SRQ_S0_VALID
/sys/devices/cpu/events/PM_GCT_EMPTY_CYC
/sys/devices/cpu/events/PM_IOPS_DISP
/sys/devices/cpu/events/PM_RUN_SPURR
/sys/devices/cpu/events/PM_PTEG_FROM_L21_MOD
/sys/devices/cpu/events/PM_VSU0_1FLOP
/sys/devices/cpu/events/PM_SNOOP_TLBIE
/sys/devices/cpu/events/PM_DATA_FROM_L3MISS
/sys/devices/cpu/events/PM_VSU_SINGLE
/sys/devices/cpu/events/PM_DTLB_MISS_16G
/sys/devices/cpu/events/PM_FLUSH
/sys/devices/cpu/events/PM_L2_LD_HIT
/sys/devices/cpu/events/PM_NEST_PAIR2_AND
/sys/devices/cpu/events/PM_VSU1_1FLOP
/sys/devices/cpu/events/PM_IC_PREF_REQ
/sys/devices/cpu/events/PM_L3_LD_HIT
/sys/devices/cpu/events/PM_DISP_HELD
/sys/devices/cpu/events/PM_L2_LD
/sys/devices/cpu/events/PM_LSU_FLUSH_SRQ
/sys/devices/cpu/events/PM_BC_PLUS_8_CONV
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L31_MOD_CYC
/sys/devices/cpu/events/PM_L2_RCST_BUSY_RC_FULL
/sys/devices/cpu/events/PM_TB_BIT_TRANS
/sys/devices/cpu/events/PM_THERMAL_MAX
/sys/devices/cpu/events/PM_LSU1_FLUSH_ULD
/sys/devices/cpu/events/PM_LSU1_REJECT_LHS
/sys/devices/cpu/events/PM_LSU_LRQ_S0_ALLOC
/sys/devices/cpu/events/PM_L3_CO_L31
/sys/devices/cpu/events/PM_POWER_EVENT4
/sys/devices/cpu/events/PM_DATA_FROM_L31_SHR
/sys/devices/cpu/events/PM_BR_UNCOND
/sys/devices/cpu/events/PM_LSU1_DC_PREF_STREAM_ALLOC
/sys/devices/cpu/events/PM_PMC4_REWIND
/sys/devices/cpu/events/PM_L2_RCLD_DISP
/sys/devices/cpu/events/PM_THRD_PRIO_2_3_CYC
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_L2MISS
/sys/devices/cpu/events/PM_IC_DEMAND_L2_BHT_REDIRECT
/sys/devices/cpu/events/PM_DATA_FROM_L31_SHR
/sys/devices/cpu/events/PM_IC_PREF_CANCEL_L2
/sys/devices/cpu/events/PM_MRK_FIN_STALL_CYC_COUNT
/sys/devices/cpu/events/PM_BR_PRED_CCACHE
/sys/devices/cpu/events/PM_GCT_UTIL_1_TO_2_SLOTS
/sys/devices/cpu/events/PM_MRK_ST_CMPL_INT
/sys/devices/cpu/events/PM_LSU_TWO_TABLEWALK_CYC
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L3MISS
/sys/devices/cpu/events/PM_LSU_SET_MPRED
/sys/devices/cpu/events/PM_FLUSH_DISP_TLBIE
/sys/devices/cpu/events/PM_VSU1_FCONV
/sys/devices/cpu/events/PM_DERAT_MISS_16G
/sys/devices/cpu/events/PM_INST_FROM_LMEM
/sys/devices/cpu/events/PM_IC_DEMAND_L2_BR_REDIRECT
/sys/devices/cpu/events/PM_INST_PTEG_FROM_L2
/sys/devices/cpu/events/PM_PTEG_FROM_L2
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L21_SHR_CYC
/sys/devices/cpu/events/PM_MRK_DTLB_MISS_4K
/sys/devices/cpu/events/PM_VSU0_FPSCR
/sys/devices/cpu/events/PM_VSU1_VECT_DOUBLE_ISSUED
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_RL2L3_MOD
/sys/devices/cpu/events/PM_MEM0_RQ_DISP
/sys/devices/cpu/events/PM_L2_LD_MISS
/sys/devices/cpu/events/PM_VMX_RESULT_SAT_1
/sys/devices/cpu/events/PM_L1_PREF
/sys/devices/cpu/events/PM_MRK_DATA_FROM_LMEM_CYC
/sys/devices/cpu/events/PM_GRP_IC_MISS_NONSPEC
/sys/devices/cpu/events/PM_PB_NODE_PUMP
/sys/devices/cpu/events/PM_SHL_MERGED
/sys/devices/cpu/events/PM_NEST_PAIR1_ADD
/sys/devices/cpu/events/PM_DATA_FROM_L3
/sys/devices/cpu/events/PM_LSU_FLUSH
/sys/devices/cpu/events/PM_LSU_SRQ_SYNC_COUNT
/sys/devices/cpu/events/PM_PMC2_OVERFLOW
/sys/devices/cpu/events/PM_LSU_LDF
/sys/devices/cpu/events/PM_POWER_EVENT3
/sys/devices/cpu/events/PM_DISP_WT
/sys/devices/cpu/events/PM_IC_BANK_CONFLICT
/sys/devices/cpu/events/PM_BR_MPRED_CR_TA
/sys/devices/cpu/events/PM_L2_INST_MISS
/sys/devices/cpu/events/PM_NEST_PAIR2_ADD
/sys/devices/cpu/events/PM_MRK_LSU_FLUSH
/sys/devices/cpu/events/PM_L2_LDST
/sys/devices/cpu/events/PM_INST_FROM_L31_SHR
/sys/devices/cpu/events/PM_VSU0_FIN
/sys/devices/cpu/events/PM_VSU1_FCONV
/sys/devices/cpu/events/PM_INST_FROM_RMEM
/sys/devices/cpu/events/PM_DISP_CLB_HELD_TLBIE
/sys/devices/cpu/events/PM_MRK_DATA_FROM_DMEM_CYC
/sys/devices/cpu/events/PM_BR_PRED_CR
/sys/devices/cpu/events/PM_LSU_REJECT
/sys/devices/cpu/events/PM_GCT_UTIL_3_TO_6_SLOTS
/sys/devices/cpu/events/PM_CMPLU_STALL_END_GCT_NOSLOT
/sys/devices/cpu/events/PM_LSU0_REJECT_LMQ_FULL
/sys/devices/cpu/events/PM_VSU_FEST
/sys/devices/cpu/events/PM_NEST_PAIR0_AND
/sys/devices/cpu/events/PM_PTEG_FROM_L3
/sys/devices/cpu/events/PM_POWER_EVENT2
/sys/devices/cpu/events/PM_IC_PREF_CANCEL_PAGE
/sys/devices/cpu/events/PM_VSU0_FSQRT_FDIV
/sys/devices/cpu/events/PM_MRK_GRP_CMPL
/sys/devices/cpu/events/PM_VSU0_SCAL_DOUBLE_ISSUED
/sys/devices/cpu/events/PM_GRP_DISP
/sys/devices/cpu/events/PM_LSU0_LDX
/sys/devices/cpu/events/PM_DATA_FROM_L2
/sys/devices/cpu/events/PM_MRK_DATA_FROM_RL2L3_MOD
/sys/devices/cpu/events/PM_VSU0_VECT_DOUBLE_ISSUED
/sys/devices/cpu/events/PM_VSU1_2FLOP_DOUBLE
/sys/devices/cpu/events/PM_THRD_PRIO_6_7_CYC
/sys/devices/cpu/events/PM_BC_PLUS_8_RSLV_TAKEN
/sys/devices/cpu/events/PM_BR_MPRED_CR
/sys/devices/cpu/events/PM_L3_CO_MEM
/sys/devices/cpu/events/PM_DATA_FROM_RL2L3_MOD
/sys/devices/cpu/events/PM_LSU_SRQ_FULL_CYC
/sys/devices/cpu/events/PM_TABLEWALK_CYC
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_RMEM
/sys/devices/cpu/events/PM_LSU_SRQ_STFWD
/sys/devices/cpu/events/PM_INST_PTEG_FROM_RMEM
/sys/devices/cpu/events/PM_FXU0_FIN
/sys/devices/cpu/events/PM_LSU1_L1_SW_PREF
/sys/devices/cpu/events/PM_PTEG_FROM_L31_MOD
/sys/devices/cpu/events/PM_PMC5_OVERFLOW
/sys/devices/cpu/events/PM_LD_REF_L1_LSU1
/sys/devices/cpu/events/PM_INST_PTEG_FROM_L21_SHR
/sys/devices/cpu/events/PM_DATA_FROM_RMEM
/sys/devices/cpu/events/PM_VSU0_SCAL_SINGLE_ISSUED
/sys/devices/cpu/events/PM_BR_MPRED_LSTACK
/sys/devices/cpu/events/PM_MRK_DATA_FROM_RL2L3_MOD_CYC
/sys/devices/cpu/events/PM_LSU0_FLUSH_UST
/sys/devices/cpu/events/PM_LSU_NCST
/sys/devices/cpu/events/PM_BR_TAKEN
/sys/devices/cpu/events/PM_INST_PTEG_FROM_LMEM
/sys/devices/cpu/events/PM_DTLB_MISS_4K
/sys/devices/cpu/events/PM_PMC4_SAVED
/sys/devices/cpu/events/PM_VSU1_PERMUTE_ISSUED
/sys/devices/cpu/events/PM_SLB_MISS
/sys/devices/cpu/events/PM_LSU1_FLUSH_LRQ
/sys/devices/cpu/events/PM_DTLB_MISS
/sys/devices/cpu/events/PM_VSU1_FRSP
/sys/devices/cpu/events/PM_VSU_VECTOR_DOUBLE_ISSUED
/sys/devices/cpu/events/PM_L2_CASTOUT_SHR
/sys/devices/cpu/events/PM_DATA_FROM_DL2L3_SHR
/sys/devices/cpu/events/PM_VSU1_STF
/sys/devices/cpu/events/PM_ST_FIN
/sys/devices/cpu/events/PM_PTEG_FROM_L21_SHR
/sys/devices/cpu/events/PM_L2_LOC_GUESS_WRONG
/sys/devices/cpu/events/PM_MRK_STCX_FAIL
/sys/devices/cpu/events/PM_LSU0_REJECT_LHS
/sys/devices/cpu/events/PM_IC_PREF_CANCEL_HIT
/sys/devices/cpu/events/PM_L3_PREF_BUSY
/sys/devices/cpu/events/PM_MRK_BRU_FIN
/sys/devices/cpu/events/PM_LSU1_NCLD
/sys/devices/cpu/events/PM_INST_PTEG_FROM_L31_MOD
/sys/devices/cpu/events/PM_LSU_NCLD
/sys/devices/cpu/events/PM_LSU_LDX
/sys/devices/cpu/events/PM_L2_LOC_GUESS_CORRECT
/sys/devices/cpu/events/PM_THRESH_TIMEO
/sys/devices/cpu/events/PM_L3_PREF_ST
/sys/devices/cpu/events/PM_DISP_CLB_HELD_SYNC
/sys/devices/cpu/events/PM_VSU_SIMPLE_ISSUED
/sys/devices/cpu/events/PM_VSU1_SINGLE
/sys/devices/cpu/events/PM_DATA_TABLEWALK_CYC
/sys/devices/cpu/events/PM_L2_RC_ST_DONE
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_L21_MOD
/sys/devices/cpu/events/PM_LARX_LSU1
/sys/devices/cpu/events/PM_MRK_DATA_FROM_RMEM
/sys/devices/cpu/events/PM_DISP_CLB_HELD
/sys/devices/cpu/events/PM_DERAT_MISS_4K
/sys/devices/cpu/events/PM_L2_RCLD_DISP_FAIL_ADDR
/sys/devices/cpu/events/PM_SEG_EXCEPTION
/sys/devices/cpu/events/PM_FLUSH_DISP_SB
/sys/devices/cpu/events/PM_L2_DC_INV
/sys/devices/cpu/events/PM_PTEG_FROM_DL2L3_MOD
/sys/devices/cpu/events/PM_DSEG
/sys/devices/cpu/events/PM_BR_PRED_LSTACK
/sys/devices/cpu/events/PM_VSU0_STF
/sys/devices/cpu/events/PM_LSU_FX_FIN
/sys/devices/cpu/events/PM_DERAT_MISS_16M
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_DL2L3_MOD
/sys/devices/cpu/events/PM_GCT_UTIL_11_PLUS_SLOTS
/sys/devices/cpu/events/PM_INST_FROM_L3
/sys/devices/cpu/events/PM_MRK_IFU_FIN
/sys/devices/cpu/events/PM_ITLB_MISS
/sys/devices/cpu/events/PM_VSU_STF
/sys/devices/cpu/events/PM_LSU_FLUSH_UST
/sys/devices/cpu/events/PM_L2_LDST_MISS
/sys/devices/cpu/events/PM_FXU1_FIN
/sys/devices/cpu/events/PM_SHL_DEALLOCATED
/sys/devices/cpu/events/PM_L2_SN_M_WR_DONE
/sys/devices/cpu/events/PM_LSU_REJECT_SET_MPRED
/sys/devices/cpu/events/PM_L3_PREF_LD
/sys/devices/cpu/events/PM_L2_SN_M_RD_DONE
/sys/devices/cpu/events/PM_MRK_DERAT_MISS_16G
/sys/devices/cpu/events/PM_VSU_FCONV
/sys/devices/cpu/events/PM_ANY_THRD_RUN_CYC
/sys/devices/cpu/events/PM_LSU_LMQ_FULL_CYC
/sys/devices/cpu/events/PM_MRK_LSU_REJECT_LHS
/sys/devices/cpu/events/PM_MRK_LD_MISS_L1_CYC
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L2_CYC
/sys/devices/cpu/events/PM_INST_IMC_MATCH_DISP
/sys/devices/cpu/events/PM_MRK_DATA_FROM_RMEM_CYC
/sys/devices/cpu/events/PM_VSU0_SIMPLE_ISSUED
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_RL2L3_SHR
/sys/devices/cpu/events/PM_VSU_FMA_DOUBLE
/sys/devices/cpu/events/PM_VSU_4FLOP
/sys/devices/cpu/events/PM_VSU1_FIN
/sys/devices/cpu/events/PM_NEST_PAIR1_AND
/sys/devices/cpu/events/PM_INST_PTEG_FROM_RL2L3_MOD
/sys/devices/cpu/events/PM_PTEG_FROM_RMEM
/sys/devices/cpu/events/PM_LSU_LRQ_S0_VALID
/sys/devices/cpu/events/PM_LSU0_LDF
/sys/devices/cpu/events/PM_FLUSH_COMPLETION
/sys/devices/cpu/events/PM_ST_MISS_L1
/sys/devices/cpu/events/PM_L2_NODE_PUMP
/sys/devices/cpu/events/PM_INST_FROM_DL2L3_SHR
/sys/devices/cpu/events/PM_MRK_STALL_CMPLU_CYC
/sys/devices/cpu/events/PM_VSU1_DENORM
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L31_SHR_CYC
/sys/devices/cpu/events/PM_NEST_PAIR0_ADD
/sys/devices/cpu/events/PM_INST_FROM_L3MISS
/sys/devices/cpu/events/PM_EE_OFF_EXT_INT
/sys/devices/cpu/events/PM_INST_PTEG_FROM_DMEM
/sys/devices/cpu/events/PM_INST_FROM_DL2L3_MOD
/sys/devices/cpu/events/PM_PMC6_OVERFLOW
/sys/devices/cpu/events/PM_VSU_2FLOP_DOUBLE
/sys/devices/cpu/events/PM_TLB_MISS
/sys/devices/cpu/events/PM_FXU_BUSY
/sys/devices/cpu/events/PM_L2_RCLD_DISP_FAIL_OTHER
/sys/devices/cpu/events/PM_LSU_REJECT_LMQ_FULL
/sys/devices/cpu/events/PM_IC_RELOAD_SHR
/sys/devices/cpu/events/PM_GRP_MRK
/sys/devices/cpu/events/PM_MRK_ST_NEST
/sys/devices/cpu/events/PM_VSU1_FSQRT_FDIV
/sys/devices/cpu/events/PM_LSU0_FLUSH_LRQ
/sys/devices/cpu/events/PM_LARX_LSU0
/sys/devices/cpu/events/PM_IBUF_FULL_CYC
/sys/devices/cpu/events/PM_MRK_DATA_FROM_DL2L3_SHR_CYC
/sys/devices/cpu/events/PM_LSU_DC_PREF_STREAM_ALLOC
/sys/devices/cpu/events/PM_GRP_MRK_CYC
/sys/devices/cpu/events/PM_MRK_DATA_FROM_RL2L3_SHR_CYC
/sys/devices/cpu/events/PM_L2_GLOB_GUESS_CORRECT
/sys/devices/cpu/events/PM_LSU_REJECT_LHS
/sys/devices/cpu/events/PM_MRK_DATA_FROM_LMEM
/sys/devices/cpu/events/PM_INST_PTEG_FROM_L3
/sys/devices/cpu/events/PM_FREQ_DOWN
/sys/devices/cpu/events/PM_PB_RETRY_NODE_PUMP
/sys/devices/cpu/events/PM_INST_FROM_RL2L3_SHR
/sys/devices/cpu/events/PM_MRK_INST_ISSUED
/sys/devices/cpu/events/PM_PTEG_FROM_L3MISS
/sys/devices/cpu/events/PM_RUN_PURR
/sys/devices/cpu/events/PM_MRK_GRP_IC_MISS
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L3
/sys/devices/cpu/events/PM_PTEG_FROM_RL2L3_SHR
/sys/devices/cpu/events/PM_LSU_FLUSH_LRQ
/sys/devices/cpu/events/PM_MRK_DERAT_MISS_64K
/sys/devices/cpu/events/PM_INST_PTEG_FROM_DL2L3_MOD
/sys/devices/cpu/events/PM_L2_ST_MISS
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_L21_SHR
/sys/devices/cpu/events/PM_LWSYNC
/sys/devices/cpu/events/PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE
/sys/devices/cpu/events/PM_MRK_LSU_FLUSH_LRQ
/sys/devices/cpu/events/PM_INST_IMC_MATCH_CMPL
/sys/devices/cpu/events/PM_NEST_PAIR3_AND
/sys/devices/cpu/events/PM_PB_RETRY_SYS_PUMP
/sys/devices/cpu/events/PM_MRK_INST_FIN
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_DL2L3_SHR
/sys/devices/cpu/events/PM_INST_FROM_L31_MOD
/sys/devices/cpu/events/PM_MRK_DTLB_MISS_64K
/sys/devices/cpu/events/PM_LSU_FIN
/sys/devices/cpu/events/PM_MRK_LSU_REJECT
/sys/devices/cpu/events/PM_L2_CO_FAIL_BUSY
/sys/devices/cpu/events/PM_MEM0_WQ_DISP
/sys/devices/cpu/events/PM_DATA_FROM_L31_MOD
/sys/devices/cpu/events/PM_THERMAL_WARN
/sys/devices/cpu/events/PM_VSU0_4FLOP
/sys/devices/cpu/events/PM_BR_MPRED_CCACHE
/sys/devices/cpu/events/PM_L1_DEMAND_WRITE
/sys/devices/cpu/events/PM_FLUSH_BR_MPRED
/sys/devices/cpu/events/PM_MRK_DTLB_MISS_16G
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_DMEM
/sys/devices/cpu/events/PM_L2_RCST_DISP
/sys/devices/cpu/events/PM_LSU_PARTIAL_CDF
/sys/devices/cpu/events/PM_DISP_CLB_HELD_SB
/sys/devices/cpu/events/PM_VSU0_FMA_DOUBLE
/sys/devices/cpu/events/PM_FXU0_BUSY_FXU1_IDLE
/sys/devices/cpu/events/PM_IC_DEMAND_CYC
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L21_SHR
/sys/devices/cpu/events/PM_MRK_LSU_FLUSH_UST
/sys/devices/cpu/events/PM_INST_PTEG_FROM_L3MISS
/sys/devices/cpu/events/PM_VSU_DENORM
/sys/devices/cpu/events/PM_MRK_LSU_PARTIAL_CDF
/sys/devices/cpu/events/PM_INST_FROM_L21_SHR
/sys/devices/cpu/events/PM_IC_PREF_WRITE
/sys/devices/cpu/events/PM_BR_PRED
/sys/devices/cpu/events/PM_INST_FROM_DMEM
/sys/devices/cpu/events/PM_IC_PREF_CANCEL_ALL
/sys/devices/cpu/events/PM_LSU_DC_PREF_STREAM_CONFIRM
/sys/devices/cpu/events/PM_MRK_LSU_FLUSH_SRQ
/sys/devices/cpu/events/PM_MRK_FIN_STALL_CYC
/sys/devices/cpu/events/PM_L2_RCST_DISP_FAIL_OTHER
/sys/devices/cpu/events/PM_VSU1_DD_ISSUED
/sys/devices/cpu/events/PM_PTEG_FROM_L31_SHR
/sys/devices/cpu/events/PM_DATA_FROM_L21_SHR
/sys/devices/cpu/events/PM_LSU0_NCLD
/sys/devices/cpu/events/PM_VSU1_4FLOP
/sys/devices/cpu/events/PM_VSU1_8FLOP
/sys/devices/cpu/events/PM_VSU_8FLOP
/sys/devices/cpu/events/PM_LSU_LMQ_SRQ_EMPTY_CYC
/sys/devices/cpu/events/PM_DTLB_MISS_64K
/sys/devices/cpu/events/PM_THRD_CONC_RUN_INST
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_L2
/sys/devices/cpu/events/PM_PB_SYS_PUMP
/sys/devices/cpu/events/PM_VSU_FIN
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L31_MOD
/sys/devices/cpu/events/PM_THRD_PRIO_0_1_CYC
/sys/devices/cpu/events/PM_DERAT_MISS_64K
/sys/devices/cpu/events/PM_PMC2_REWIND
/sys/devices/cpu/events/PM_INST_FROM_L2
/sys/devices/cpu/events/PM_GRP_BR_MPRED_NONSPEC
/sys/devices/cpu/events/PM_INST_DISP
/sys/devices/cpu/events/PM_MEM0_RD_CANCEL_TOTAL
/sys/devices/cpu/events/PM_LSU0_DC_PREF_STREAM_CONFIRM
/sys/devices/cpu/events/PM_L1_DCACHE_RELOAD_VALID
/sys/devices/cpu/events/PM_VSU_SCALAR_DOUBLE_ISSUED
/sys/devices/cpu/events/PM_L3_PREF_HIT
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_L31_MOD
/sys/devices/cpu/events/PM_MRK_FXU_FIN
/sys/devices/cpu/events/PM_PMC4_OVERFLOW
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_L3
/sys/devices/cpu/events/PM_LSU0_LMQ_LHR_MERGE
/sys/devices/cpu/events/PM_BTAC_HIT
/sys/devices/cpu/events/PM_L3_RD_BUSY
/sys/devices/cpu/events/PM_LSU0_L1_SW_PREF
/sys/devices/cpu/events/PM_INST_FROM_L2MISS
/sys/devices/cpu/events/PM_LSU0_DC_PREF_STREAM_ALLOC
/sys/devices/cpu/events/PM_L2_ST
/sys/devices/cpu/events/PM_VSU0_DENORM
/sys/devices/cpu/events/PM_MRK_DATA_FROM_DL2L3_SHR
/sys/devices/cpu/events/PM_BR_PRED_CR_TA
/sys/devices/cpu/events/PM_VSU0_FCONV
/sys/devices/cpu/events/PM_MRK_LSU_FLUSH_ULD
/sys/devices/cpu/events/PM_BTAC_MISS
/sys/devices/cpu/events/PM_MRK_LD_MISS_EXPOSED_CYC_COUNT
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L2
/sys/devices/cpu/events/PM_LSU_DCACHE_RELOAD_VALID
/sys/devices/cpu/events/PM_VSU_FMA
/sys/devices/cpu/events/PM_LSU0_FLUSH_SRQ
/sys/devices/cpu/events/PM_LSU1_L1_PREF
/sys/devices/cpu/events/PM_IOPS_CMPL
/sys/devices/cpu/events/PM_L2_SYS_PUMP
/sys/devices/cpu/events/PM_L2_RCLD_BUSY_RC_FULL
/sys/devices/cpu/events/PM_LSU_LMQ_S0_ALLOC
/sys/devices/cpu/events/PM_FLUSH_DISP_SYNC
/sys/devices/cpu/events/PM_MRK_DATA_FROM_DL2L3_MOD_CYC
/sys/devices/cpu/events/PM_L2_IC_INV
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L21_MOD_CYC
/sys/devices/cpu/events/PM_L3_PREF_LDST
/sys/devices/cpu/events/PM_LSU_SRQ_EMPTY_CYC
/sys/devices/cpu/events/PM_LSU_LMQ_S0_VALID
/sys/devices/cpu/events/PM_FLUSH_PARTIAL
/sys/devices/cpu/events/PM_VSU1_FMA_DOUBLE
/sys/devices/cpu/events/PM_1PLUS_PPC_DISP
/sys/devices/cpu/events/PM_DATA_FROM_L2MISS
/sys/devices/cpu/events/PM_SUSPENDED
/sys/devices/cpu/events/PM_VSU0_FMA
/sys/devices/cpu/events/PM_STCX_FAIL
/sys/devices/cpu/events/PM_VSU0_FSQRT_FDIV_DOUBLE
/sys/devices/cpu/events/PM_DC_PREF_DST
/sys/devices/cpu/events/PM_VSU1_SCAL_SINGLE_ISSUED
/sys/devices/cpu/events/PM_L3_HIT
/sys/devices/cpu/events/PM_L2_GLOB_GUESS_WRONG
/sys/devices/cpu/events/PM_MRK_DFU_FIN
/sys/devices/cpu/events/PM_INST_FROM_L1
/sys/devices/cpu/events/PM_IC_DEMAND_REQ
/sys/devices/cpu/events/PM_VSU1_FSQRT_FDIV_DOUBLE
/sys/devices/cpu/events/PM_VSU1_FMA
/sys/devices/cpu/events/PM_MRK_LD_MISS_L1
/sys/devices/cpu/events/PM_VSU0_2FLOP_DOUBLE
/sys/devices/cpu/events/PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM
/sys/devices/cpu/events/PM_INST_PTEG_FROM_L31_SHR
/sys/devices/cpu/events/PM_MRK_LSU_REJECT_ERAT_MISS
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L2MISS
/sys/devices/cpu/events/PM_DATA_FROM_RL2L3_SHR
/sys/devices/cpu/events/PM_INST_FROM_PREF
/sys/devices/cpu/events/PM_VSU1_SQ
/sys/devices/cpu/events/PM_L2_LD_DISP
/sys/devices/cpu/events/PM_L2_DISP_ALL
/sys/devices/cpu/events/PM_THRD_GRP_CMPL_BOTH_CYC
/sys/devices/cpu/events/PM_VSU_FSQRT_FDIV_DOUBLE
/sys/devices/cpu/events/PM_INST_PTEG_FROM_DL2L3_SHR
/sys/devices/cpu/events/PM_VSU_1FLOP
/sys/devices/cpu/events/PM_HV_CYC
/sys/devices/cpu/events/PM_MRK_LSU_FIN
/sys/devices/cpu/events/PM_MRK_DATA_FROM_RL2L3_SHR
/sys/devices/cpu/events/PM_DTLB_MISS_16M
/sys/devices/cpu/events/PM_LSU1_LMQ_LHR_MERGE
/sys/devices/cpu/events/PM_IFU_FIN
/sys/devices/cpu/events/PM_1THRD_CON_RUN_INSTR
/sys/devices/cpu/events/PM_CMPLU_STALL_COUNT
/sys/devices/cpu/events/PM_MEM0_PB_RD_CL
/sys/devices/cpu/events/PM_THRD_1_RUN_CYC
/sys/devices/cpu/events/PM_THRD_2_CONC_RUN_INSTR
/sys/devices/cpu/events/PM_THRD_2_RUN_CYC
/sys/devices/cpu/events/PM_THRD_3_CONC_RUN_INST
/sys/devices/cpu/events/PM_THRD_3_RUN_CYC
/sys/devices/cpu/events/PM_THRD_4_CONC_RUN_INST
/sys/devices/cpu/events/PM_THRD_4_RUN_CYC
Date: 2013/01/08

23
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@ -0,0 +1,23 @@
What: /sys/bus/event_source/devices/hv_24x7/interface/catalog
Date: February 2014
Contact: Cody P Schafer <cody@linux.vnet.ibm.com>
Description:
Provides access to the binary "24x7 catalog" provided by the
hypervisor on POWER7 and 8 systems. This catalog lists events
avaliable from the powerpc "hv_24x7" pmu. Its format is
documented here:
https://raw.githubusercontent.com/jmesmon/catalog-24x7/master/hv-24x7-catalog.h
What: /sys/bus/event_source/devices/hv_24x7/interface/catalog_length
Date: February 2014
Contact: Cody P Schafer <cody@linux.vnet.ibm.com>
Description:
A number equal to the length in bytes of the catalog. This is
also extractable from the provided binary "catalog" sysfs entry.
What: /sys/bus/event_source/devices/hv_24x7/interface/catalog_version
Date: February 2014
Contact: Cody P Schafer <cody@linux.vnet.ibm.com>
Description:
Exposes the "version" field of the 24x7 catalog. This is also
extractable from the provided binary "catalog" sysfs entry.

43
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What: /sys/bus/event_source/devices/hv_gpci/interface/collect_privileged
Date: February 2014
Contact: Cody P Schafer <cody@linux.vnet.ibm.com>
Description:
'0' if the hypervisor is configured to forbid access to event
counters being accumulated by other guests and to physical
domain event counters.
'1' if that access is allowed.
What: /sys/bus/event_source/devices/hv_gpci/interface/ga
Date: February 2014
Contact: Cody P Schafer <cody@linux.vnet.ibm.com>
Description:
0 or 1. Indicates whether we have access to "GA" events (listed
in arch/powerpc/perf/hv-gpci.h).
What: /sys/bus/event_source/devices/hv_gpci/interface/expanded
Date: February 2014
Contact: Cody P Schafer <cody@linux.vnet.ibm.com>
Description:
0 or 1. Indicates whether we have access to "EXPANDED" events (listed
in arch/powerpc/perf/hv-gpci.h).
What: /sys/bus/event_source/devices/hv_gpci/interface/lab
Date: February 2014
Contact: Cody P Schafer <cody@linux.vnet.ibm.com>
Description:
0 or 1. Indicates whether we have access to "LAB" events (listed
in arch/powerpc/perf/hv-gpci.h).
What: /sys/bus/event_source/devices/hv_gpci/interface/version
Date: February 2014
Contact: Cody P Schafer <cody@linux.vnet.ibm.com>
Description:
A number indicating the version of the gpci interface that the
hypervisor reports supporting.
What: /sys/bus/event_source/devices/hv_gpci/interface/kernel_version
Date: February 2014
Contact: Cody P Schafer <cody@linux.vnet.ibm.com>
Description:
A number indicating the latest version of the gpci interface
that the kernel is aware of.

20
Documentation/ABI/testing/sysfs-bus-mdio
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@ -7,3 +7,23 @@ Description:
by the device during bus enumeration, encoded in hexadecimal.
This ID is used to match the device with the appropriate
driver.
What: /sys/bus/mdio_bus/devices/.../phy_interface
Date: February 2014
KernelVersion: 3.15
Contact: netdev@vger.kernel.org
Description:
This attribute contains the PHY interface as configured by the
Ethernet driver during bus enumeration, encoded in string.
This interface mode is used to configure the Ethernet MAC with the
appropriate mode for its data lines to the PHY hardware.
What: /sys/bus/mdio_bus/devices/.../phy_has_fixups
Date: February 2014
KernelVersion: 3.15
Contact: netdev@vger.kernel.org
Description:
This attribute contains the boolean value whether a given PHY
device has had any "fixup" workaround running on it, encoded as
a boolean. This information is provided to help troubleshooting
PHY configurations.

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What: /sys/class/net/<iface>/addr_assign_type
Date: July 2010
KernelVersion: 3.2
Contact: netdev@vger.kernel.org
Description:
Indicates the address assignment type. Possible values are:
0: permanent address
1: randomly generated
2: stolen from another device
3: set using dev_set_mac_address
What: /sys/class/net/<iface>/addr_len
Date: April 2005
KernelVersion: 2.6.12
Contact: netdev@vger.kernel.org
Description:
Indicates the hardware address size in bytes.
Values vary based on the lower-level protocol used by the
interface (Ethernet, FDDI, ATM, IEEE 802.15.4...). See
include/uapi/linux/if_*.h for actual values.
What: /sys/class/net/<iface>/address
Date: April 2005
KernelVersion: 2.6.12
Contact: netdev@vger.kernel.org
Description:
Hardware address currently assigned to this interface.
Format is a string, e.g: 00:11:22:33:44:55 for an Ethernet MAC
address.
What: /sys/class/net/<iface>/broadcast
Date: April 2005
KernelVersion: 2.6.12
Contact: netdev@vger.kernel.org
Description:
Hardware broadcast address for this interface. Format is a
string, e.g: ff:ff:ff:ff:ff:ff for an Ethernet broadcast MAC
address.
What: /sys/class/net/<iface>/carrier
Date: April 2005
KernelVersion: 2.6.12
Contact: netdev@vger.kernel.org
Description:
Indicates the current physical link state of the interface.
Posssible values are:
0: physical link is down
1: physical link is up
Note: some special devices, e.g: bonding and team drivers will
allow this attribute to be written to force a link state for
operating correctly and designating another fallback interface.
What: /sys/class/net/<iface>/dev_id
Date: April 2008
KernelVersion: 2.6.26
Contact: netdev@vger.kernel.org
Description:
Indicates the device unique identifier. Format is an hexadecimal
value. This is used to disambiguate interfaces which might be
stacked (e.g: VLAN interfaces) but still have the same MAC
address as their parent device.
What: /sys/class/net/<iface>/dormant
Date: March 2006
KernelVersion: 2.6.17
Contact: netdev@vger.kernel.org
Description:
Indicates whether the interface is in dormant state. Possible
values are:
0: interface is not dormant
1: interface is dormant
This attribute can be used by supplicant software to signal that
the device is not usable unless some supplicant-based
authentication is performed (e.g: 802.1x). 'link_mode' attribute
will also reflect the dormant state.
What: /sys/clas/net/<iface>/duplex
Date: October 2009
KernelVersion: 2.6.33
Contact: netdev@vger.kernel.org
Description:
Indicates the interface latest or current duplex value. Possible
values are:
half: half duplex
full: full duplex
Note: This attribute is only valid for interfaces that implement
the ethtool get_settings method (mostly Ethernet).
What: /sys/class/net/<iface>/flags
Date: April 2005
KernelVersion: 2.6.12
Contact: netdev@vger.kernel.org
Description:
Indicates the interface flags as a bitmask in hexadecimal. See
include/uapi/linux/if.h for a list of all possible values and
the flags semantics.
What: /sys/class/net/<iface>/ifalias
Date: September 2008
KernelVersion: 2.6.28
Contact: netdev@vger.kernel.org
Description:
Indicates/stores an interface alias name as a string. This can
be used for system management purposes.
What: /sys/class/net/<iface>/ifindex
Date: April 2005
KernelVersion: 2.6.12
Contact: netdev@vger.kernel.org
Description:
Indicates the system-wide interface unique index identifier as a
decimal number. This attribute is used for mapping an interface
identifier to an interface name. It is used throughout the
networking stack for specifying the interface specific
requests/events.
What: /sys/class/net/<iface>/iflink
Date: April 2005
KernelVersion: 2.6.12
Contact: netdev@vger.kernel.org
Description:
Indicates the system-wide interface unique index identifier a
the interface is linked to. Format is decimal. This attribute is
used to resolve interfaces chaining, linking and stacking.
Physical interfaces have the same 'ifindex' and 'iflink' values.
What: /sys/class/net/<iface>/link_mode
Date: March 2006
KernelVersion: 2.6.17
Contact: netdev@vger.kernel.org
Description:
Indicates the interface link mode, as a decimal number. This
attribute should be used in conjunction with 'dormant' attribute
to determine the interface usability. Possible values:
0: default link mode
1: dormant link mode
What: /sys/class/net/<iface>/mtu
Date: April 2005
KernelVersion: 2.6.12
Contact: netdev@vger.kernel.org
Description:
Indicates the interface currently configured MTU value, in
bytes, and in decimal format. Specific values depends on the
lower-level interface protocol used. Ethernet devices will show
a 'mtu' attribute value of 1500 unless changed.
What: /sys/calss/net/<iface>/netdev_group
Date: January 2011
KernelVersion: 2.6.39
Contact: netdev@vger.kernel.org
Description:
Indicates the interface network device group, as a decimal
integer. Default value is 0 which corresponds to the initial
network devices group. The group can be changed to affect
routing decisions (see: net/ipv4/fib_rules and
net/ipv6/fib6_rules.c).
What: /sys/class/net/<iface>/operstate
Date: March 2006
KernelVersion: 2.6.17
Contact: netdev@vger.kernel.org
Description:
Indicates the interface RFC2863 operational state as a string.
Possible values are:
"unknown", "notpresent", "down", "lowerlayerdown", "testing",
"dormant", "up".
What: /sys/class/net/<iface>/speed
Date: October 2009
KernelVersion: 2.6.33
Contact: netdev@vger.kernel.org
Description:
Indicates the interface latest or current speed value. Value is
an integer representing the link speed in Mbits/sec.
Note: this attribute is only valid for interfaces that implement
the ethtool get_settings method (mostly Ethernet ).
What: /sys/class/net/<iface>/tx_queue_len
Date: April 2005
KernelVersion: 2.6.12
Contact: netdev@vger.kernel.org
Description:
Indicates the interface transmit queue len in number of packets,
as an integer value. Value depend on the type of interface,
Ethernet network adapters have a default value of 1000 unless
configured otherwise
What: /sys/class/net/<iface>/type
Date: April 2005
KernelVersion: 2.6.12
Contact: netdev@vger.kernel.org
Description:
Indicates the interface protocol type as a decimal value. See
include/uapi/linux/if_arp.h for all possible values.

9
Documentation/ABI/testing/sysfs-class-net-mesh
View File

@ -76,6 +76,15 @@ Description:
is used to classify clients as "isolated" by the
Extended Isolation feature.
What: /sys/class/net/<mesh_iface>/mesh/multicast_mode
Date: Feb 2014
Contact: Linus Lüssing <linus.luessing@web.de>
Description:
Indicates whether multicast optimizations are enabled
or disabled. If set to zero then all nodes in the
mesh are going to use classic flooding for any
multicast packet with no optimizations.
What: /sys/class/net/<mesh_iface>/mesh/network_coding
Date: Nov 2012
Contact: Martin Hundeboll <martin@hundeboll.net>

16
Documentation/ABI/testing/sysfs-class-scsi_host
View File

@ -11,3 +11,19 @@ Description:
guaranteed. The 'isci_id' attribute unambiguously identifies
the controller index: '0' for the first controller,
'1' for the second.
What: /sys/class/scsi_host/hostX/acciopath_status
Date: November 2013
Contact: Stephen M. Cameron <scameron@beardog.cce.hp.com>
Description: This file contains the current status of the "SSD Smart Path"
feature of HP Smart Array RAID controllers using the hpsa
driver. SSD Smart Path, when enabled permits the driver to
send i/o requests directly to physical devices that are part
of a logical drive, bypassing the controllers firmware RAID
stack for a performance advantage when possible. A value of
'1' indicates the feature is enabled, and the controller may
use the direct i/o path to physical devices. A value of zero
means the feature is disabled and the controller may not use
the direct i/o path to physical devices. This setting is
controller wide, affecting all configured logical drives on the
controller. This file is readable and writable.

73
Documentation/ABI/testing/sysfs-devices-power
View File

@ -83,8 +83,10 @@ Contact: Rafael J. Wysocki <rjw@rjwysocki.net>
Description:
The /sys/devices/.../wakeup_count attribute contains the number
of signaled wakeup events associated with the device. This
attribute is read-only. If the device is not enabled to wake up
attribute is read-only. If the device is not capable to wake up
the system from sleep states, this attribute is not present.
If the device is not enabled to wake up the system from sleep
states, this attribute is empty.
What: /sys/devices/.../power/wakeup_active_count
Date: September 2010
@ -93,8 +95,10 @@ Description:
The /sys/devices/.../wakeup_active_count attribute contains the
number of times the processing of wakeup events associated with
the device was completed (at the kernel level). This attribute
is read-only. If the device is not enabled to wake up the
system from sleep states, this attribute is not present.
is read-only. If the device is not capable to wake up the
system from sleep states, this attribute is not present. If
the device is not enabled to wake up the system from sleep
states, this attribute is empty.
What: /sys/devices/.../power/wakeup_abort_count
Date: February 2012
@ -104,8 +108,9 @@ Description:
number of times the processing of a wakeup event associated with
the device might have aborted system transition into a sleep
state in progress. This attribute is read-only. If the device
is not enabled to wake up the system from sleep states, this
attribute is not present.
is not capable to wake up the system from sleep states, this
attribute is not present. If the device is not enabled to wake
up the system from sleep states, this attribute is empty.
What: /sys/devices/.../power/wakeup_expire_count
Date: February 2012
@ -114,8 +119,10 @@ Description:
The /sys/devices/.../wakeup_expire_count attribute contains the
number of times a wakeup event associated with the device has
been reported with a timeout that expired. This attribute is
read-only. If the device is not enabled to wake up the system
from sleep states, this attribute is not present.
read-only. If the device is not capable to wake up the system
from sleep states, this attribute is not present. If the
device is not enabled to wake up the system from sleep states,
this attribute is empty.
What: /sys/devices/.../power/wakeup_active
Date: September 2010
@ -124,8 +131,10 @@ Description:
The /sys/devices/.../wakeup_active attribute contains either 1,
or 0, depending on whether or not a wakeup event associated with
the device is being processed (1). This attribute is read-only.
If the device is not enabled to wake up the system from sleep
states, this attribute is not present.
If the device is not capable to wake up the system from sleep
states, this attribute is not present. If the device is not
enabled to wake up the system from sleep states, this attribute
is empty.
What: /sys/devices/.../power/wakeup_total_time_ms
Date: September 2010
@ -134,8 +143,9 @@ Description:
The /sys/devices/.../wakeup_total_time_ms attribute contains
the total time of processing wakeup events associated with the
device, in milliseconds. This attribute is read-only. If the
device is not enabled to wake up the system from sleep states,
this attribute is not present.
device is not capable to wake up the system from sleep states,
this attribute is not present. If the device is not enabled to
wake up the system from sleep states, this attribute is empty.
What: /sys/devices/.../power/wakeup_max_time_ms
Date: September 2010
@ -144,8 +154,10 @@ Description:
The /sys/devices/.../wakeup_max_time_ms attribute contains
the maximum time of processing a single wakeup event associated
with the device, in milliseconds. This attribute is read-only.
If the device is not enabled to wake up the system from sleep
states, this attribute is not present.
If the device is not capable to wake up the system from sleep
states, this attribute is not present. If the device is not
enabled to wake up the system from sleep states, this attribute
is empty.
What: /sys/devices/.../power/wakeup_last_time_ms
Date: September 2010
@ -156,7 +168,8 @@ Description:
signaling the last wakeup event associated with the device, in
milliseconds. This attribute is read-only. If the device is
not enabled to wake up the system from sleep states, this
attribute is not present.
attribute is not present. If the device is not enabled to wake
up the system from sleep states, this attribute is empty.
What: /sys/devices/.../power/wakeup_prevent_sleep_time_ms
Date: February 2012
@ -165,9 +178,10 @@ Description:
The /sys/devices/.../wakeup_prevent_sleep_time_ms attribute
contains the total time the device has been preventing
opportunistic transitions to sleep states from occurring.
This attribute is read-only. If the device is not enabled to
This attribute is read-only. If the device is not capable to
wake up the system from sleep states, this attribute is not
present.
present. If the device is not enabled to wake up the system
from sleep states, this attribute is empty.
What: /sys/devices/.../power/autosuspend_delay_ms
Date: September 2010
@ -187,7 +201,7 @@ Description:
Not all drivers support this attribute. If it isn't supported,
attempts to read or write it will yield I/O errors.
What: /sys/devices/.../power/pm_qos_latency_us
What: /sys/devices/.../power/pm_qos_resume_latency_us
Date: March 2012
Contact: Rafael J. Wysocki <rjw@rjwysocki.net>
Description:
@ -205,6 +219,31 @@ Description:
This attribute has no effect on system-wide suspend/resume and
hibernation.
What: /sys/devices/.../power/pm_qos_latency_tolerance_us
Date: January 2014
Contact: Rafael J. Wysocki <rjw@rjwysocki.net>
Description:
The /sys/devices/.../power/pm_qos_latency_tolerance_us attribute
contains the PM QoS active state latency tolerance limit for the
given device in microseconds. That is the maximum memory access
latency the device can suffer without any visible adverse
effects on user space functionality. If that value is the
string "any", the latency does not matter to user space at all,
but hardware should not be allowed to set the latency tolerance
for the device automatically.
Reading "auto" from this file means that the maximum memory
access latency for the device may be determined automatically
by the hardware as needed. Writing "auto" to it allows the
hardware to be switched to this mode if there are no other
latency tolerance requirements from the kernel side.
This attribute is only present if the feature controlled by it
is supported by the hardware.
This attribute has no effect on runtime suspend and resume of
devices and on system-wide suspend/resume and hibernation.
What: /sys/devices/.../power/pm_qos_no_power_off
Date: September 2012
Contact: Rafael J. Wysocki <rjw@rjwysocki.net>

28
Documentation/ABI/testing/sysfs-firmware-ofw Normal file
View File

@ -0,0 +1,28 @@
What: /sys/firmware/devicetree/*
Date: November 2013
Contact: Grant Likely <grant.likely@linaro.org>
Description:
When using OpenFirmware or a Flattened Device Tree to enumerate
hardware, the device tree structure will be exposed in this
directory.
It is possible for multiple device-tree directories to exist.
Some device drivers use a separate detached device tree which
have no attachment to the system tree and will appear in a
different subdirectory under /sys/firmware/devicetree.
Userspace must not use the /sys/firmware/devicetree/base
path directly, but instead should follow /proc/device-tree
symlink. It is possible that the absolute path will change
in the future, but the symlink is the stable ABI.
The /proc/device-tree symlink replaces the devicetree /proc
filesystem support, and has largely the same semantics and
should be compatible with existing userspace.
The contents of /sys/firmware/devicetree/ is a
hierarchy of directories, one per device tree node. The
directory name is the resolved path component name (node
name plus address). Properties are represented as files
in the directory. The contents of each file is the exact
binary data from the device tree.

12
Documentation/ABI/testing/sysfs-fs-f2fs
View File

@ -55,3 +55,15 @@ Date: January 2014
Contact: "Jaegeuk Kim" <jaegeuk.kim@samsung.com>
Description:
Controls the number of trials to find a victim segment.
What: /sys/fs/f2fs/<disk>/dir_level
Date: March 2014
Contact: "Jaegeuk Kim" <jaegeuk.kim@samsung.com>
Description:
Controls the directory level for large directory.
What: /sys/fs/f2fs/<disk>/ram_thresh
Date: March 2014
Contact: "Jaegeuk Kim" <jaegeuk.kim@samsung.com>
Description:
Controls the memory footprint used by f2fs.

1
Documentation/ABI/testing/sysfs-module
View File

@ -49,3 +49,4 @@ Description: Module taint flags:
O - out-of-tree module
F - force-loaded module
C - staging driver module
E - unsigned module

5
Documentation/ABI/testing/sysfs-power
View File

@ -12,8 +12,9 @@ Contact: Rafael J. Wysocki <rjw@rjwysocki.net>
Description:
The /sys/power/state file controls the system power state.
Reading from this file returns what states are supported,
which is hard-coded to 'standby' (Power-On Suspend), 'mem'
(Suspend-to-RAM), and 'disk' (Suspend-to-Disk).
which is hard-coded to 'freeze' (Low-Power Idle), 'standby'
(Power-On Suspend), 'mem' (Suspend-to-RAM), and 'disk'
(Suspend-to-Disk).
Writing to this file one of these strings causes the system to
transition into that state. Please see the file

20
Documentation/ABI/testing/sysfs-ptp
View File

@ -54,6 +54,26 @@ Description:
This file contains the number of programmable periodic
output channels offered by the PTP hardware clock.
What: /sys/class/ptp/ptpN/n_pins
Date: March 2014
Contact: Richard Cochran <richardcochran@gmail.com>
Description:
This file contains the number of programmable pins
offered by the PTP hardware clock.
What: /sys/class/ptp/ptpN/pins
Date: March 2014
Contact: Richard Cochran <richardcochran@gmail.com>
Description:
This directory contains one file for each programmable
pin offered by the PTP hardware clock. The file name
is the hardware dependent pin name. Reading from this
file produces two numbers, the assigned function (see
the PTP_PF_ enumeration values in linux/ptp_clock.h)
and the channel number. The function and channel
assignment may be changed by two writing numbers into
the file.
What: /sys/class/ptp/ptpN/pps_avaiable
Date: September 2010
Contact: Richard Cochran <richardcochran@gmail.com>

2
Documentation/DocBook/80211.tmpl
View File

@ -98,6 +98,8 @@
!Finclude/net/cfg80211.h priv_to_wiphy
!Finclude/net/cfg80211.h set_wiphy_dev
!Finclude/net/cfg80211.h wdev_priv
!Finclude/net/cfg80211.h ieee80211_iface_limit
!Finclude/net/cfg80211.h ieee80211_iface_combination
</chapter>
<chapter>
<title>Actions and configuration</title>

27
Documentation/DocBook/Makefile
View File

@ -14,9 +14,9 @@ DOCBOOKS := z8530book.xml device-drivers.xml \
genericirq.xml s390-drivers.xml uio-howto.xml scsi.xml \
80211.xml debugobjects.xml sh.xml regulator.xml \
alsa-driver-api.xml writing-an-alsa-driver.xml \
tracepoint.xml drm.xml media_api.xml
tracepoint.xml drm.xml media_api.xml w1.xml
include $(srctree)/Documentation/DocBook/media/Makefile
include Documentation/DocBook/media/Makefile
###
# The build process is as follows (targets):
@ -36,6 +36,7 @@ PS_METHOD = $(prefer-db2x)
# The targets that may be used.
PHONY += xmldocs sgmldocs psdocs pdfdocs htmldocs mandocs installmandocs cleandocs
targets += $(DOCBOOKS)
BOOKS := $(addprefix $(obj)/,$(DOCBOOKS))
xmldocs: $(BOOKS)
sgmldocs: xmldocs
@ -58,14 +59,14 @@ mandocs: $(MAN)
installmandocs: mandocs
mkdir -p /usr/local/man/man9/
install Documentation/DocBook/man/*.9.gz /usr/local/man/man9/
install $(obj)/man/*.9.gz /usr/local/man/man9/
###
#External programs used
KERNELDOC = $(srctree)/scripts/kernel-doc
DOCPROC = $(objtree)/scripts/docproc
XMLTOFLAGS = -m $(srctree)/Documentation/DocBook/stylesheet.xsl
XMLTOFLAGS = -m $(srctree)/$(src)/stylesheet.xsl
XMLTOFLAGS += --skip-validation
###
@ -87,21 +88,9 @@ define rule_docproc
) > $(dir $@).$(notdir $@).cmd
endef
%.xml: %.tmpl FORCE
%.xml: %.tmpl $(KERNELDOC) $(DOCPROC) FORCE
$(call if_changed_rule,docproc)
###
#Read in all saved dependency files
cmd_files := $(wildcard $(foreach f,$(BOOKS),$(dir $(f)).$(notdir $(f)).cmd))
ifneq ($(cmd_files),)
include $(cmd_files)
endif
###
# Changes in kernel-doc force a rebuild of all documentation
$(BOOKS): $(KERNELDOC)
# Tell kbuild to always build the programs
always := $(hostprogs-y)
@ -139,7 +128,7 @@ quiet_cmd_db2pdf = PDF $@
index = index.html
main_idx = Documentation/DocBook/$(index)
main_idx = $(obj)/$(index)
build_main_index = rm -rf $(main_idx); \
echo '<h1>Linux Kernel HTML Documentation</h1>' >> $(main_idx) && \
echo '<h2>Kernel Version: $(KERNELVERSION)</h2>' >> $(main_idx) && \
@ -148,7 +137,7 @@ build_main_index = rm -rf $(main_idx); \
quiet_cmd_db2html = HTML $@
cmd_db2html = xmlto html $(XMLTOFLAGS) -o $(patsubst %.html,%,$@) $< && \
echo '<a HREF="$(patsubst %.html,%,$(notdir $@))/index.html"> \
$(patsubst %.html,%,$(notdir $@))</a><p>' > $@
$(patsubst %.html,%,$(notdir $@))</a><p>' > $@
%.html: %.xml
@(which xmlto > /dev/null 2>&1) || \

552
Documentation/DocBook/drm.tmpl
View File

@ -29,12 +29,26 @@
</address>
</affiliation>
</author>
<author>
<firstname>Daniel</firstname>
<surname>Vetter</surname>
<contrib>Contributions all over the place</contrib>
<affiliation>
<orgname>Intel Corporation</orgname>
<address>
<email>daniel.vetter@ffwll.ch</email>
</address>
</affiliation>
</author>
</authorgroup>
<copyright>
<year>2008-2009</year>
<year>2012</year>
<year>2013-2014</year>
<holder>Intel Corporation</holder>
</copyright>
<copyright>
<year>2012</year>
<holder>Laurent Pinchart</holder>
</copyright>
@ -60,7 +74,15 @@
<toc></toc>
<!-- Introduction -->
<part id="drmCore">
<title>DRM Core</title>
<partintro>
<para>
This first part of the DRM Developer's Guide documents core DRM code,
helper libraries for writting drivers and generic userspace interfaces
exposed by DRM drivers.
</para>
</partintro>
<chapter id="drmIntroduction">
<title>Introduction</title>
@ -264,8 +286,8 @@ char *date;</synopsis>
<para>
The <methodname>load</methodname> method is the driver and device
initialization entry point. The method is responsible for allocating and
initializing driver private data, specifying supported performance
counters, performing resource allocation and mapping (e.g. acquiring
initializing driver private data, performing resource allocation and
mapping (e.g. acquiring
clocks, mapping registers or allocating command buffers), initializing
the memory manager (<xref linkend="drm-memory-management"/>), installing
the IRQ handler (<xref linkend="drm-irq-registration"/>), setting up
@ -295,7 +317,7 @@ char *date;</synopsis>
their <methodname>load</methodname> method called with flags to 0.
</para>
<sect3>
<title>Driver Private &amp; Performance Counters</title>
<title>Driver Private Data</title>
<para>
The driver private hangs off the main
<structname>drm_device</structname> structure and can be used for
@ -307,14 +329,6 @@ char *date;</synopsis>
<structname>drm_device</structname>.<structfield>dev_priv</structfield>
set to NULL when the driver is unloaded.
</para>
<para>
DRM supports several counters which were used for rough performance
characterization. This stat counter system is deprecated and should not
be used. If performance monitoring is desired, the developer should
investigate and potentially enhance the kernel perf and tracing
infrastructure to export GPU related performance information for
consumption by performance monitoring tools and applications.
</para>
</sect3>
<sect3 id="drm-irq-registration">
<title>IRQ Registration</title>
@ -697,55 +711,16 @@ char *date;</synopsis>
respectively. The conversion is handled by the DRM core without any
driver-specific support.
</para>
<para>
Similar to global names, GEM file descriptors are also used to share GEM
objects across processes. They offer additional security: as file
descriptors must be explicitly sent over UNIX domain sockets to be shared
between applications, they can't be guessed like the globally unique GEM
names.
</para>
<para>
Drivers that support GEM file descriptors, also known as the DRM PRIME
API, must set the DRIVER_PRIME bit in the struct
<structname>drm_driver</structname>
<structfield>driver_features</structfield> field, and implement the
<methodname>prime_handle_to_fd</methodname> and
<methodname>prime_fd_to_handle</methodname> operations.
</para>
<para>
<synopsis>int (*prime_handle_to_fd)(struct drm_device *dev,
struct drm_file *file_priv, uint32_t handle,
uint32_t flags, int *prime_fd);
int (*prime_fd_to_handle)(struct drm_device *dev,
struct drm_file *file_priv, int prime_fd,
uint32_t *handle);</synopsis>
Those two operations convert a handle to a PRIME file descriptor and
vice versa. Drivers must use the kernel dma-buf buffer sharing framework
to manage the PRIME file descriptors.
</para>
<para>
While non-GEM drivers must implement the operations themselves, GEM
drivers must use the <function>drm_gem_prime_handle_to_fd</function>
and <function>drm_gem_prime_fd_to_handle</function> helper functions.
Those helpers rely on the driver
<methodname>gem_prime_export</methodname> and
<methodname>gem_prime_import</methodname> operations to create a dma-buf
instance from a GEM object (dma-buf exporter role) and to create a GEM
object from a dma-buf instance (dma-buf importer role).
</para>
<para>
<synopsis>struct dma_buf * (*gem_prime_export)(struct drm_device *dev,
struct drm_gem_object *obj,
int flags);
struct drm_gem_object * (*gem_prime_import)(struct drm_device *dev,
struct dma_buf *dma_buf);</synopsis>
These two operations are mandatory for GEM drivers that support DRM
PRIME.
</para>
<sect4>
<title>DRM PRIME Helper Functions Reference</title>
!Pdrivers/gpu/drm/drm_prime.c PRIME Helpers
</sect4>
<para>
GEM also supports buffer sharing with dma-buf file descriptors through
PRIME. GEM-based drivers must use the provided helpers functions to
implement the exporting and importing correctly. See <xref linkend="drm-prime-support" />.
Since sharing file descriptors is inherently more secure than the
easily guessable and global GEM names it is the preferred buffer
sharing mechanism. Sharing buffers through GEM names is only supported
for legacy userspace. Furthermore PRIME also allows cross-device
buffer sharing since it is based on dma-bufs.
</para>
</sect3>
<sect3 id="drm-gem-objects-mapping">
<title>GEM Objects Mapping</title>
@ -829,62 +804,6 @@ char *date;</synopsis>
faults can implement their own mmap file operation handler.
</para>
</sect3>
<sect3>
<title>Dumb GEM Objects</title>
<para>
The GEM API doesn't standardize GEM objects creation and leaves it to
driver-specific ioctls. While not an issue for full-fledged graphics
stacks that include device-specific userspace components (in libdrm for
instance), this limit makes DRM-based early boot graphics unnecessarily
complex.
</para>
<para>
Dumb GEM objects partly alleviate the problem by providing a standard
API to create dumb buffers suitable for scanout, which can then be used
to create KMS frame buffers.
</para>
<para>
To support dumb GEM objects drivers must implement the
<methodname>dumb_create</methodname>,
<methodname>dumb_destroy</methodname> and
<methodname>dumb_map_offset</methodname> operations.
</para>
<itemizedlist>
<listitem>
<synopsis>int (*dumb_create)(struct drm_file *file_priv, struct drm_device *dev,
struct drm_mode_create_dumb *args);</synopsis>
<para>
The <methodname>dumb_create</methodname> operation creates a GEM
object suitable for scanout based on the width, height and depth
from the struct <structname>drm_mode_create_dumb</structname>
argument. It fills the argument's <structfield>handle</structfield>,
<structfield>pitch</structfield> and <structfield>size</structfield>
fields with a handle for the newly created GEM object and its line
pitch and size in bytes.
</para>
</listitem>
<listitem>
<synopsis>int (*dumb_destroy)(struct drm_file *file_priv, struct drm_device *dev,
uint32_t handle);</synopsis>
<para>
The <methodname>dumb_destroy</methodname> operation destroys a dumb
GEM object created by <methodname>dumb_create</methodname>.
</para>
</listitem>
<listitem>
<synopsis>int (*dumb_map_offset)(struct drm_file *file_priv, struct drm_device *dev,
uint32_t handle, uint64_t *offset);</synopsis>
<para>
The <methodname>dumb_map_offset</methodname> operation associates an
mmap fake offset with the GEM object given by the handle and returns
it. Drivers must use the
<function>drm_gem_create_mmap_offset</function> function to
associate the fake offset as described in
<xref linkend="drm-gem-objects-mapping"/>.
</para>
</listitem>
</itemizedlist>
</sect3>
<sect3>
<title>Memory Coherency</title>
<para>
@ -924,7 +843,99 @@ char *date;</synopsis>
abstracted from the client in libdrm.
</para>
</sect3>
</sect2>
<sect3>
<title>GEM Function Reference</title>
!Edrivers/gpu/drm/drm_gem.c
</sect3>
</sect2>
<sect2>
<title>VMA Offset Manager</title>
!Pdrivers/gpu/drm/drm_vma_manager.c vma offset manager
!Edrivers/gpu/drm/drm_vma_manager.c
!Iinclude/drm/drm_vma_manager.h
</sect2>
<sect2 id="drm-prime-support">
<title>PRIME Buffer Sharing</title>
<para>
PRIME is the cross device buffer sharing framework in drm, originally
created for the OPTIMUS range of multi-gpu platforms. To userspace
PRIME buffers are dma-buf based file descriptors.
</para>
<sect3>
<title>Overview and Driver Interface</title>
<para>
Similar to GEM global names, PRIME file descriptors are
also used to share buffer objects across processes. They offer
additional security: as file descriptors must be explicitly sent over
UNIX domain sockets to be shared between applications, they can't be
guessed like the globally unique GEM names.
</para>
<para>
Drivers that support the PRIME
API must set the DRIVER_PRIME bit in the struct
<structname>drm_driver</structname>
<structfield>driver_features</structfield> field, and implement the
<methodname>prime_handle_to_fd</methodname> and
<methodname>prime_fd_to_handle</methodname> operations.
</para>
<para>
<synopsis>int (*prime_handle_to_fd)(struct drm_device *dev,
struct drm_file *file_priv, uint32_t handle,
uint32_t flags, int *prime_fd);
int (*prime_fd_to_handle)(struct drm_device *dev,
struct drm_file *file_priv, int prime_fd,
uint32_t *handle);</synopsis>
Those two operations convert a handle to a PRIME file descriptor and
vice versa. Drivers must use the kernel dma-buf buffer sharing framework
to manage the PRIME file descriptors. Similar to the mode setting
API PRIME is agnostic to the underlying buffer object manager, as
long as handles are 32bit unsinged integers.
</para>
<para>
While non-GEM drivers must implement the operations themselves, GEM
drivers must use the <function>drm_gem_prime_handle_to_fd</function>
and <function>drm_gem_prime_fd_to_handle</function> helper functions.
Those helpers rely on the driver
<methodname>gem_prime_export</methodname> and
<methodname>gem_prime_import</methodname> operations to create a dma-buf
instance from a GEM object (dma-buf exporter role) and to create a GEM
object from a dma-buf instance (dma-buf importer role).
</para>
<para>
<synopsis>struct dma_buf * (*gem_prime_export)(struct drm_device *dev,
struct drm_gem_object *obj,
int flags);
struct drm_gem_object * (*gem_prime_import)(struct drm_device *dev,
struct dma_buf *dma_buf);</synopsis>
These two operations are mandatory for GEM drivers that support
PRIME.
</para>
</sect3>
<sect3>
<title>PRIME Helper Functions</title>
!Pdrivers/gpu/drm/drm_prime.c PRIME Helpers
</sect3>
</sect2>
<sect2>
<title>PRIME Function References</title>
!Edrivers/gpu/drm/drm_prime.c
</sect2>
<sect2>
<title>DRM MM Range Allocator</title>
<sect3>
<title>Overview</title>
!Pdrivers/gpu/drm/drm_mm.c Overview
</sect3>
<sect3>
<title>LRU Scan/Eviction Support</title>
!Pdrivers/gpu/drm/drm_mm.c lru scan roaster
</sect3>
</sect2>
<sect2>
<title>DRM MM Range Allocator Function References</title>
!Edrivers/gpu/drm/drm_mm.c
!Iinclude/drm/drm_mm.h
</sect2>
</sect1>
<!-- Internals: mode setting -->
@ -952,6 +963,11 @@ int max_width, max_height;</synopsis>
<para>Mode setting functions.</para>
</listitem>
</itemizedlist>
<sect2>
<title>Display Modes Function Reference</title>
!Iinclude/drm/drm_modes.h
!Edrivers/gpu/drm/drm_modes.c
</sect2>
<sect2>
<title>Frame Buffer Creation</title>
<synopsis>struct drm_framebuffer *(*fb_create)(struct drm_device *dev,
@ -968,9 +984,11 @@ int max_width, max_height;</synopsis>
Frame buffers rely on the underneath memory manager for low-level memory
operations. When creating a frame buffer applications pass a memory
handle (or a list of memory handles for multi-planar formats) through
the <parameter>drm_mode_fb_cmd2</parameter> argument. This document
assumes that the driver uses GEM, those handles thus reference GEM
objects.
the <parameter>drm_mode_fb_cmd2</parameter> argument. For drivers using
GEM as their userspace buffer management interface this would be a GEM
handle. Drivers are however free to use their own backing storage object
handles, e.g. vmwgfx directly exposes special TTM handles to userspace
and so expects TTM handles in the create ioctl and not GEM handles.
</para>
<para>
Drivers must first validate the requested frame buffer parameters passed
@ -992,7 +1010,7 @@ int max_width, max_height;</synopsis>
</para>
<para>
The initailization of the new framebuffer instance is finalized with a
The initialization of the new framebuffer instance is finalized with a
call to <function>drm_framebuffer_init</function> which takes a pointer
to DRM frame buffer operations (struct
<structname>drm_framebuffer_funcs</structname>). Note that this function
@ -1042,7 +1060,7 @@ int max_width, max_height;</synopsis>
<para>
The lifetime of a drm framebuffer is controlled with a reference count,
drivers can grab additional references with
<function>drm_framebuffer_reference</function> </para> and drop them
<function>drm_framebuffer_reference</function>and drop them
again with <function>drm_framebuffer_unreference</function>. For
driver-private framebuffers for which the last reference is never
dropped (e.g. for the fbdev framebuffer when the struct
@ -1050,6 +1068,72 @@ int max_width, max_height;</synopsis>
helper struct) drivers can manually clean up a framebuffer at module
unload time with
<function>drm_framebuffer_unregister_private</function>.
</para>
</sect2>
<sect2>
<title>Dumb Buffer Objects</title>
<para>
The KMS API doesn't standardize backing storage object creation and
leaves it to driver-specific ioctls. Furthermore actually creating a
buffer object even for GEM-based drivers is done through a
driver-specific ioctl - GEM only has a common userspace interface for
sharing and destroying objects. While not an issue for full-fledged
graphics stacks that include device-specific userspace components (in
libdrm for instance), this limit makes DRM-based early boot graphics
unnecessarily complex.
</para>
<para>
Dumb objects partly alleviate the problem by providing a standard
API to create dumb buffers suitable for scanout, which can then be used
to create KMS frame buffers.
</para>
<para>
To support dumb objects drivers must implement the
<methodname>dumb_create</methodname>,
<methodname>dumb_destroy</methodname> and
<methodname>dumb_map_offset</methodname> operations.
</para>
<itemizedlist>
<listitem>
<synopsis>int (*dumb_create)(struct drm_file *file_priv, struct drm_device *dev,
struct drm_mode_create_dumb *args);</synopsis>
<para>
The <methodname>dumb_create</methodname> operation creates a driver
object (GEM or TTM handle) suitable for scanout based on the
width, height and depth from the struct
<structname>drm_mode_create_dumb</structname> argument. It fills the
argument's <structfield>handle</structfield>,
<structfield>pitch</structfield> and <structfield>size</structfield>
fields with a handle for the newly created object and its line
pitch and size in bytes.
</para>
</listitem>
<listitem>
<synopsis>int (*dumb_destroy)(struct drm_file *file_priv, struct drm_device *dev,
uint32_t handle);</synopsis>
<para>
The <methodname>dumb_destroy</methodname> operation destroys a dumb
object created by <methodname>dumb_create</methodname>.
</para>
</listitem>
<listitem>
<synopsis>int (*dumb_map_offset)(struct drm_file *file_priv, struct drm_device *dev,
uint32_t handle, uint64_t *offset);</synopsis>
<para>
The <methodname>dumb_map_offset</methodname> operation associates an
mmap fake offset with the object given by the handle and returns
it. Drivers must use the
<function>drm_gem_create_mmap_offset</function> function to
associate the fake offset as described in
<xref linkend="drm-gem-objects-mapping"/>.
</para>
</listitem>
</itemizedlist>
<para>
Note that dumb objects may not be used for gpu acceleration, as has been
attempted on some ARM embedded platforms. Such drivers really must have
a hardware-specific ioctl to allocate suitable buffer objects.
</para>
</sect2>
<sect2>
<title>Output Polling</title>
@ -1110,7 +1194,7 @@ int max_width, max_height;</synopsis>
pointer to CRTC functions.
</para>
</sect3>
<sect3>
<sect3 id="drm-kms-crtcops">
<title>CRTC Operations</title>
<sect4>
<title>Set Configuration</title>
@ -1130,8 +1214,11 @@ int max_width, max_height;</synopsis>
This operation is called with the mode config lock held.
</para>
<note><para>
FIXME: How should set_config interact with DPMS? If the CRTC is
suspended, should it be resumed?
Note that the drm core has no notion of restoring the mode setting
state after resume, since all resume handling is in the full
responsibility of the driver. The common mode setting helper library
though provides a helper which can be used for this:
<function>drm_helper_resume_force_mode</function>.
</para></note>
</sect4>
<sect4>
@ -1248,15 +1335,47 @@ int max_width, max_height;</synopsis>
optionally scale it to a destination size. The result is then blended
with or overlayed on top of a CRTC.
</para>
<para>
The DRM core recognizes three types of planes:
<itemizedlist>
<listitem>
DRM_PLANE_TYPE_PRIMARY represents a "main" plane for a CRTC. Primary
planes are the planes operated upon by by CRTC modesetting and flipping
operations described in <xref linkend="drm-kms-crtcops"/>.
</listitem>
<listitem>
DRM_PLANE_TYPE_CURSOR represents a "cursor" plane for a CRTC. Cursor
planes are the planes operated upon by the DRM_IOCTL_MODE_CURSOR and
DRM_IOCTL_MODE_CURSOR2 ioctls.
</listitem>
<listitem>
DRM_PLANE_TYPE_OVERLAY represents all non-primary, non-cursor planes.
Some drivers refer to these types of planes as "sprites" internally.
</listitem>
</itemizedlist>
For compatibility with legacy userspace, only overlay planes are made
available to userspace by default. Userspace clients may set the
DRM_CLIENT_CAP_UNIVERSAL_PLANES client capability bit to indicate that
they wish to receive a universal plane list containing all plane types.
</para>
<sect3>
<title>Plane Initialization</title>
<para>
Planes are optional. To create a plane, a KMS drivers allocates and
To create a plane, a KMS drivers allocates and
zeroes an instances of struct <structname>drm_plane</structname>
(possibly as part of a larger structure) and registers it with a call
to <function>drm_plane_init</function>. The function takes a bitmask
to <function>drm_universal_plane_init</function>. The function takes a bitmask
of the CRTCs that can be associated with the plane, a pointer to the
plane functions and a list of format supported formats.
plane functions, a list of format supported formats, and the type of
plane (primary, cursor, or overlay) being initialized.
</para>
<para>
Cursor and overlay planes are optional. All drivers should provide
one primary plane per CRTC (although this requirement may change in
the future); drivers that do not wish to provide special handling for
primary planes may make use of the helper functions described in
<xref linkend="drm-kms-planehelpers"/> to create and register a
primary plane with standard capabilities.
</para>
</sect3>
<sect3>
@ -1687,7 +1806,7 @@ void intel_crt_init(struct drm_device *dev)
<sect1>
<title>Mode Setting Helper Functions</title>
<para>
The CRTC, encoder and connector functions provided by the drivers
The plane, CRTC, encoder and connector functions provided by the drivers
implement the DRM API. They're called by the DRM core and ioctl handlers
to handle device state changes and configuration request. As implementing
those functions often requires logic not specific to drivers, mid-layer
@ -1695,8 +1814,8 @@ void intel_crt_init(struct drm_device *dev)
</para>
<para>
The DRM core contains one mid-layer implementation. The mid-layer provides
implementations of several CRTC, encoder and connector functions (called
from the top of the mid-layer) that pre-process requests and call
implementations of several plane, CRTC, encoder and connector functions
(called from the top of the mid-layer) that pre-process requests and call
lower-level functions provided by the driver (at the bottom of the
mid-layer). For instance, the
<function>drm_crtc_helper_set_config</function> function can be used to
@ -2134,7 +2253,7 @@ void intel_crt_init(struct drm_device *dev)
set the <structfield>display_info</structfield>
<structfield>width_mm</structfield> and
<structfield>height_mm</structfield> fields if they haven't been set
already (for instance at initilization time when a fixed-size panel is
already (for instance at initialization time when a fixed-size panel is
attached to the connector). The mode <structfield>width_mm</structfield>
and <structfield>height_mm</structfield> fields are only used internally
during EDID parsing and should not be set when creating modes manually.
@ -2196,10 +2315,19 @@ void intel_crt_init(struct drm_device *dev)
!Edrivers/gpu/drm/drm_flip_work.c
</sect2>
<sect2>
<title>VMA Offset Manager</title>
!Pdrivers/gpu/drm/drm_vma_manager.c vma offset manager
!Edrivers/gpu/drm/drm_vma_manager.c
!Iinclude/drm/drm_vma_manager.h
<title>HDMI Infoframes Helper Reference</title>
<para>
Strictly speaking this is not a DRM helper library but generally useable
by any driver interfacing with HDMI outputs like v4l or alsa drivers.
But it nicely fits into the overall topic of mode setting helper
libraries and hence is also included here.
</para>
!Iinclude/linux/hdmi.h
!Edrivers/video/hdmi.c
</sect2>
<sect2>
<title id="drm-kms-planehelpers">Plane Helper Reference</title>
!Edrivers/gpu/drm/drm_plane_helper.c Plane Helpers
</sect2>
</sect1>
@ -2561,42 +2689,44 @@ int num_ioctls;</synopsis>
</para>
</sect2>
</sect1>
<sect1>
<title>Command submission &amp; fencing</title>
<title>Legacy Support Code</title>
<para>
This should cover a few device-specific command submission
implementations.
The section very brievely covers some of the old legacy support code which
is only used by old DRM drivers which have done a so-called shadow-attach
to the underlying device instead of registering as a real driver. This
also includes some of the old generic buffer mangement and command
submission code. Do not use any of this in new and modern drivers.
</para>
</sect1>
<!-- Internals: suspend/resume -->
<sect2>
<title>Legacy Suspend/Resume</title>
<para>
The DRM core provides some suspend/resume code, but drivers wanting full
suspend/resume support should provide save() and restore() functions.
These are called at suspend, hibernate, or resume time, and should perform
any state save or restore required by your device across suspend or
hibernate states.
</para>
<synopsis>int (*suspend) (struct drm_device *, pm_message_t state);
int (*resume) (struct drm_device *);</synopsis>
<para>
Those are legacy suspend and resume methods which
<emphasis>only</emphasis> work with the legacy shadow-attach driver
registration functions. New driver should use the power management
interface provided by their bus type (usually through
the struct <structname>device_driver</structname> dev_pm_ops) and set
these methods to NULL.
</para>
</sect2>
<sect1>
<title>Suspend/Resume</title>
<para>
The DRM core provides some suspend/resume code, but drivers wanting full
suspend/resume support should provide save() and restore() functions.
These are called at suspend, hibernate, or resume time, and should perform
any state save or restore required by your device across suspend or
hibernate states.
</para>
<synopsis>int (*suspend) (struct drm_device *, pm_message_t state);
int (*resume) (struct drm_device *);</synopsis>
<para>
Those are legacy suspend and resume methods. New driver should use the
power management interface provided by their bus type (usually through
the struct <structname>device_driver</structname> dev_pm_ops) and set
these methods to NULL.
</para>
</sect1>
<sect1>
<title>DMA services</title>
<para>
This should cover how DMA mapping etc. is supported by the core.
These functions are deprecated and should not be used.
</para>
<sect2>
<title>Legacy DMA Services</title>
<para>
This should cover how DMA mapping etc. is supported by the core.
These functions are deprecated and should not be used.
</para>
</sect2>
</sect1>
</chapter>
@ -2658,8 +2788,8 @@ int (*resume) (struct drm_device *);</synopsis>
DRM core provides multiple character-devices for user-space to use.
Depending on which device is opened, user-space can perform a different
set of operations (mainly ioctls). The primary node is always created
and called <term>card&lt;num&gt;</term>. Additionally, a currently
unused control node, called <term>controlD&lt;num&gt;</term> is also
and called card&lt;num&gt;. Additionally, a currently
unused control node, called controlD&lt;num&gt; is also
created. The primary node provides all legacy operations and
historically was the only interface used by userspace. With KMS, the
control node was introduced. However, the planned KMS control interface
@ -2674,21 +2804,21 @@ int (*resume) (struct drm_device *);</synopsis>
nodes were introduced. Render nodes solely serve render clients, that
is, no modesetting or privileged ioctls can be issued on render nodes.
Only non-global rendering commands are allowed. If a driver supports
render nodes, it must advertise it via the <term>DRIVER_RENDER</term>
render nodes, it must advertise it via the DRIVER_RENDER
DRM driver capability. If not supported, the primary node must be used
for render clients together with the legacy drmAuth authentication
procedure.
</para>
<para>
If a driver advertises render node support, DRM core will create a
separate render node called <term>renderD&lt;num&gt;</term>. There will
separate render node called renderD&lt;num&gt;. There will
be one render node per device. No ioctls except PRIME-related ioctls
will be allowed on this node. Especially <term>GEM_OPEN</term> will be
will be allowed on this node. Especially GEM_OPEN will be
explicitly prohibited. Render nodes are designed to avoid the
buffer-leaks, which occur if clients guess the flink names or mmap
offsets on the legacy interface. Additionally to this basic interface,
drivers must mark their driver-dependent render-only ioctls as
<term>DRM_RENDER_ALLOW</term> so render clients can use them. Driver
DRM_RENDER_ALLOW so render clients can use them. Driver
authors must be careful not to allow any privileged ioctls on render
nodes.
</para>
@ -2749,15 +2879,73 @@ int (*resume) (struct drm_device *);</synopsis>
</sect1>
</chapter>
</part>
<part id="drmDrivers">
<title>DRM Drivers</title>
<!-- API reference -->
<appendix id="drmDriverApi">
<title>DRM Driver API</title>
<partintro>
<para>
Include auto-generated API reference here (need to reference it
from paragraphs above too).
This second part of the DRM Developer's Guide documents driver code,
implementation details and also all the driver-specific userspace
interfaces. Especially since all hardware-acceleration interfaces to
userspace are driver specific for efficiency and other reasons these
interfaces can be rather substantial. Hence every driver has its own
chapter.
</para>
</appendix>
</partintro>
<chapter id="drmI915">
<title>drm/i915 Intel GFX Driver</title>
<para>
The drm/i915 driver supports all (with the exception of some very early
models) integrated GFX chipsets with both Intel display and rendering
blocks. This excludes a set of SoC platforms with an SGX rendering unit,
those have basic support through the gma500 drm driver.
</para>
<sect1>
<title>Display Hardware Handling</title>
<para>
This section covers everything related to the display hardware including
the mode setting infrastructure, plane, sprite and cursor handling and
display, output probing and related topics.
</para>
<sect2>
<title>Mode Setting Infrastructure</title>
<para>
The i915 driver is thus far the only DRM driver which doesn't use the
common DRM helper code to implement mode setting sequences. Thus it
has its own tailor-made infrastructure for executing a display
configuration change.
</para>
</sect2>
<sect2>
<title>Plane Configuration</title>
<para>
This section covers plane configuration and composition with the
primary plane, sprites, cursors and overlays. This includes the
infrastructure to do atomic vsync'ed updates of all this state and
also tightly coupled topics like watermark setup and computation,
framebuffer compression and panel self refresh.
</para>
</sect2>
<sect2>
<title>Output Probing</title>
<para>
This section covers output probing and related infrastructure like the
hotplug interrupt storm detection and mitigation code. Note that the
i915 driver still uses most of the common DRM helper code for output
probing, so those sections fully apply.
</para>
</sect2>
</sect1>
<sect1>
<title>Memory Management and Command Submission</title>
<para>
This sections covers all things related to the GEM implementation in the
i915 driver.
</para>
</sect1>
</chapter>
</part>
</book>

12
Documentation/DocBook/kernel-hacking.tmpl
View File

@ -671,7 +671,7 @@ printk(KERN_INFO "my ip: %pI4\n", &amp;ipaddress);
<sect1 id="routines-local-irqs">
<title><function>local_irq_save()</function>/<function>local_irq_restore()</function>
<filename class="headerfile">include/asm/system.h</filename>
<filename class="headerfile">include/linux/irqflags.h</filename>
</title>
<para>
@ -850,16 +850,6 @@ printk(KERN_INFO "my ip: %pI4\n", &amp;ipaddress);
<returnvalue>-ERESTARTSYS</returnvalue> if a signal is received.
The <function>wait_event()</function> version ignores signals.
</para>
<para>
Do not use the <function>sleep_on()</function> function family -
it is very easy to accidentally introduce races; almost certainly
one of the <function>wait_event()</function> family will do, or a
loop around <function>schedule_timeout()</function>. If you choose
to loop around <function>schedule_timeout()</function> remember
you must set the task state (with
<function>set_current_state()</function>) on each iteration to avoid
busy-looping.
</para>
</sect1>

101
Documentation/DocBook/w1.tmpl Normal file
View File

@ -0,0 +1,101 @@
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE book PUBLIC "-//OASIS//DTD DocBook XML V4.1.2//EN"
"http://www.oasis-open.org/docbook/xml/4.1.2/docbookx.dtd" []>
<book id="w1id">
<bookinfo>
<title>W1: Dallas' 1-wire bus</title>
<authorgroup>
<author>
<firstname>David</firstname>
<surname>Fries</surname>
<affiliation>
<address>
<email>David@Fries.net</email>
</address>
</affiliation>
</author>
</authorgroup>
<copyright>
<year>2013</year>
<!--
<holder></holder>
-->
</copyright>
<legalnotice>
<para>
This documentation is free software; you can redistribute
it and/or modify it under the terms of the GNU General Public
License version 2.
</para>
<para>
This program is distributed in the hope that it will be
useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
For more details see the file COPYING in the source
distribution of Linux.
</para>
</legalnotice>
</bookinfo>
<toc></toc>
<chapter id="w1_internal">
<title>W1 API internal to the kernel</title>
<sect1 id="w1_internal_api">
<title>W1 API internal to the kernel</title>
<sect2 id="w1.h">
<title>drivers/w1/w1.h</title>
<para>W1 core functions.</para>
!Idrivers/w1/w1.h
</sect2>
<sect2 id="w1.c">
<title>drivers/w1/w1.c</title>
<para>W1 core functions.</para>
!Idrivers/w1/w1.c
</sect2>
<sect2 id="w1_family.h">
<title>drivers/w1/w1_family.h</title>
<para>Allows registering device family operations.</para>
!Idrivers/w1/w1_family.h
</sect2>
<sect2 id="w1_family.c">
<title>drivers/w1/w1_family.c</title>
<para>Allows registering device family operations.</para>
!Edrivers/w1/w1_family.c
</sect2>
<sect2 id="w1_int.c">
<title>drivers/w1/w1_int.c</title>
<para>W1 internal initialization for master devices.</para>
!Edrivers/w1/w1_int.c
</sect2>
<sect2 id="w1_netlink.h">
<title>drivers/w1/w1_netlink.h</title>
<para>W1 external netlink API structures and commands.</para>
!Idrivers/w1/w1_netlink.h
</sect2>
<sect2 id="w1_io.c">
<title>drivers/w1/w1_io.c</title>
<para>W1 input/output.</para>
!Edrivers/w1/w1_io.c
!Idrivers/w1/w1_io.c
</sect2>
</sect1>
</chapter>
</book>

72
Documentation/DocBook/writing-an-alsa-driver.tmpl
View File

@ -468,8 +468,6 @@
return err;
}
snd_card_set_dev(card, &pci->dev);
*rchip = chip;
return 0;
}
@ -492,7 +490,8 @@
}
/* (2) */
err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
0, &card);
if (err < 0)
return err;
@ -591,7 +590,8 @@
struct snd_card *card;
int err;
....
err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
0, &card);
]]>
</programlisting>
</informalexample>
@ -809,28 +809,34 @@
<para>
As mentioned above, to create a card instance, call
<function>snd_card_create()</function>.
<function>snd_card_new()</function>.
<informalexample>
<programlisting>
<![CDATA[
struct snd_card *card;
int err;
err = snd_card_create(index, id, module, extra_size, &card);
err = snd_card_new(&pci->dev, index, id, module, extra_size, &card);
]]>
</programlisting>
</informalexample>
</para>
<para>
The function takes five arguments, the card-index number, the
id string, the module pointer (usually
The function takes six arguments: the parent device pointer,
the card-index number, the id string, the module pointer (usually
<constant>THIS_MODULE</constant>),
the size of extra-data space, and the pointer to return the
card instance. The extra_size argument is used to
allocate card-&gt;private_data for the
chip-specific data. Note that these data
are allocated by <function>snd_card_create()</function>.
are allocated by <function>snd_card_new()</function>.
</para>
<para>
The first argument, the pointer of struct
<structname>device</structname>, specifies the parent device.
For PCI devices, typically &amp;pci-&gt; is passed there.
</para>
</section>
@ -916,16 +922,16 @@
</para>
<section id="card-management-chip-specific-snd-card-new">
<title>1. Allocating via <function>snd_card_create()</function>.</title>
<title>1. Allocating via <function>snd_card_new()</function>.</title>
<para>
As mentioned above, you can pass the extra-data-length
to the 4th argument of <function>snd_card_create()</function>, i.e.
to the 5th argument of <function>snd_card_new()</function>, i.e.
<informalexample>
<programlisting>
<![CDATA[
err = snd_card_create(index[dev], id[dev], THIS_MODULE,
sizeof(struct mychip), &card);
err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
sizeof(struct mychip), &card);
]]>
</programlisting>
</informalexample>
@ -954,7 +960,7 @@
<para>
After allocating a card instance via
<function>snd_card_create()</function> (with
<function>snd_card_new()</function> (with
<constant>0</constant> on the 4th arg), call
<function>kzalloc()</function>.
@ -963,7 +969,8 @@
<![CDATA[
struct snd_card *card;
struct mychip *chip;
err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
0, &card);
.....
chip = kzalloc(sizeof(*chip), GFP_KERNEL);
]]>
@ -1170,8 +1177,6 @@
return err;
}
snd_card_set_dev(card, &pci->dev);
*rchip = chip;
return 0;
}
@ -1526,30 +1531,6 @@
</section>
<section id="pci-resource-device-struct">
<title>Registration of Device Struct</title>
<para>
At some point, typically after calling <function>snd_device_new()</function>,
you need to register the struct <structname>device</structname> of the chip
you're handling for udev and co. ALSA provides a macro for compatibility with
older kernels. Simply call like the following:
<informalexample>
<programlisting>
<![CDATA[
snd_card_set_dev(card, &pci->dev);
]]>
</programlisting>
</informalexample>
so that it stores the PCI's device pointer to the card. This will be
referred by ALSA core functions later when the devices are registered.
</para>
<para>
In the case of non-PCI, pass the proper device struct pointer of the BUS
instead. (In the case of legacy ISA without PnP, you don't have to do
anything.)
</para>
</section>
<section id="pci-resource-entries">
<title>PCI Entries</title>
<para>
@ -5740,7 +5721,8 @@ struct _snd_pcm_runtime {
struct mychip *chip;
int err;
....
err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
0, &card);
....
chip = kzalloc(sizeof(*chip), GFP_KERNEL);
....
@ -5752,7 +5734,7 @@ struct _snd_pcm_runtime {
</informalexample>
When you created the chip data with
<function>snd_card_create()</function>, it's anyway accessible
<function>snd_card_new()</function>, it's anyway accessible
via <structfield>private_data</structfield> field.
<informalexample>
@ -5766,8 +5748,8 @@ struct _snd_pcm_runtime {
struct mychip *chip;
int err;
....
err = snd_card_create(index[dev], id[dev], THIS_MODULE,
sizeof(struct mychip), &card);
err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
sizeof(struct mychip), &card);
....
chip = card->private_data;
....

4
Documentation/PCI/pci-iov-howto.txt
View File

@ -68,10 +68,6 @@ To disable SR-IOV capability:
echo 0 > \
/sys/bus/pci/devices/<DOMAIN:BUS:DEVICE.FUNCTION>/sriov_numvfs
To notify SR-IOV core of Virtual Function Migration:
(a) In the driver:
irqreturn_t pci_sriov_migration(struct pci_dev *dev);
3.2 Usage example
Following piece of code illustrates the usage of the SR-IOV API.

149
Documentation/RCU/RTFP.txt
View File

@ -31,6 +31,14 @@ has lapsed, so this approach may be used in non-GPL software, if desired.
(In contrast, implementation of RCU is permitted only in software licensed
under either GPL or LGPL. Sorry!!!)
In 1987, Rashid et al. described lazy TLB-flush [RichardRashid87a].
At first glance, this has nothing to do with RCU, but nevertheless
this paper helped inspire the update-side batching used in the later
RCU implementation in DYNIX/ptx. In 1988, Barbara Liskov published
a description of Argus that noted that use of out-of-date values can
be tolerated in some situations. Thus, this paper provides some early
theoretical justification for use of stale data.
In 1990, Pugh [Pugh90] noted that explicitly tracking which threads
were reading a given data structure permitted deferred free to operate
in the presence of non-terminating threads. However, this explicit
@ -41,11 +49,11 @@ providing a fine-grained locking design, however, it would be interesting
to see how much of the performance advantage reported in 1990 remains
today.
At about this same time, Adams [Adams91] described ``chaotic relaxation'',
where the normal barriers between successive iterations of convergent
numerical algorithms are relaxed, so that iteration $n$ might use
data from iteration $n-1$ or even $n-2$. This introduces error,
which typically slows convergence and thus increases the number of
At about this same time, Andrews [Andrews91textbook] described ``chaotic
relaxation'', where the normal barriers between successive iterations
of convergent numerical algorithms are relaxed, so that iteration $n$
might use data from iteration $n-1$ or even $n-2$. This introduces
error, which typically slows convergence and thus increases the number of
iterations required. However, this increase is sometimes more than made
up for by a reduction in the number of expensive barrier operations,
which are otherwise required to synchronize the threads at the end
@ -55,7 +63,8 @@ is thus inapplicable to most data structures in operating-system kernels.
In 1992, Henry (now Alexia) Massalin completed a dissertation advising
parallel programmers to defer processing when feasible to simplify
synchronization. RCU makes extremely heavy use of this advice.
synchronization [HMassalinPhD]. RCU makes extremely heavy use of
this advice.
In 1993, Jacobson [Jacobson93] verbally described what is perhaps the
simplest deferred-free technique: simply waiting a fixed amount of time
@ -90,27 +99,29 @@ mechanism, which is quite similar to RCU [Gamsa99]. These operating
systems made pervasive use of RCU in place of "existence locks", which
greatly simplifies locking hierarchies and helps avoid deadlocks.
2001 saw the first RCU presentation involving Linux [McKenney01a]
at OLS. The resulting abundance of RCU patches was presented the
following year [McKenney02a], and use of RCU in dcache was first
described that same year [Linder02a].
The year 2000 saw an email exchange that would likely have
led to yet another independent invention of something like RCU
[RustyRussell2000a,RustyRussell2000b]. Instead, 2001 saw the first
RCU presentation involving Linux [McKenney01a] at OLS. The resulting
abundance of RCU patches was presented the following year [McKenney02a],
and use of RCU in dcache was first described that same year [Linder02a].
Also in 2002, Michael [Michael02b,Michael02a] presented "hazard-pointer"
techniques that defer the destruction of data structures to simplify
non-blocking synchronization (wait-free synchronization, lock-free
synchronization, and obstruction-free synchronization are all examples of
non-blocking synchronization). In particular, this technique eliminates
locking, reduces contention, reduces memory latency for readers, and
parallelizes pipeline stalls and memory latency for writers. However,
these techniques still impose significant read-side overhead in the
form of memory barriers. Researchers at Sun worked along similar lines
in the same timeframe [HerlihyLM02]. These techniques can be thought
of as inside-out reference counts, where the count is represented by the
number of hazard pointers referencing a given data structure rather than
the more conventional counter field within the data structure itself.
The key advantage of inside-out reference counts is that they can be
stored in immortal variables, thus allowing races between access and
deletion to be avoided.
non-blocking synchronization). The corresponding journal article appeared
in 2004 [MagedMichael04a]. This technique eliminates locking, reduces
contention, reduces memory latency for readers, and parallelizes pipeline
stalls and memory latency for writers. However, these techniques still
impose significant read-side overhead in the form of memory barriers.
Researchers at Sun worked along similar lines in the same timeframe
[HerlihyLM02]. These techniques can be thought of as inside-out reference
counts, where the count is represented by the number of hazard pointers
referencing a given data structure rather than the more conventional
counter field within the data structure itself. The key advantage
of inside-out reference counts is that they can be stored in immortal
variables, thus allowing races between access and deletion to be avoided.
By the same token, RCU can be thought of as a "bulk reference count",
where some form of reference counter covers all reference by a given CPU
@ -123,8 +134,10 @@ can be thought of in other terms as well.
In 2003, the K42 group described how RCU could be used to create
hot-pluggable implementations of operating-system functions [Appavoo03a].
Later that year saw a paper describing an RCU implementation of System
V IPC [Arcangeli03], and an introduction to RCU in Linux Journal
Later that year saw a paper describing an RCU implementation
of System V IPC [Arcangeli03] (following up on a suggestion by
Hugh Dickins [Dickins02a] and an implementation by Mingming Cao
[MingmingCao2002IPCRCU]), and an introduction to RCU in Linux Journal
[McKenney03a].
2004 has seen a Linux-Journal article on use of RCU in dcache
@ -383,6 +396,21 @@ for Programming Languages and Operating Systems}"
}
}
@phdthesis{HMassalinPhD
,author="H. Massalin"
,title="Synthesis: An Efficient Implementation of Fundamental Operating
System Services"
,school="Columbia University"
,address="New York, NY"
,year="1992"
,annotation={
Mondo optimizing compiler.
Wait-free stuff.
Good advice: defer work to avoid synchronization. See page 90
(PDF page 106), Section 5.4, fourth bullet point.
}
}
@unpublished{Jacobson93
,author="Van Jacobson"
,title="Avoid Read-Side Locking Via Delayed Free"
@ -671,6 +699,20 @@ Orran Krieger and Rusty Russell and Dipankar Sarma and Maneesh Soni"
[Viewed October 18, 2004]"
}
@conference{Michael02b
,author="Maged M. Michael"
,title="High Performance Dynamic Lock-Free Hash Tables and List-Based Sets"
,Year="2002"
,Month="August"
,booktitle="{Proceedings of the 14\textsuperscript{th} Annual ACM
Symposium on Parallel
Algorithms and Architecture}"
,pages="73-82"
,annotation={
Like the title says...
}
}
@Conference{Linder02a
,Author="Hanna Linder and Dipankar Sarma and Maneesh Soni"
,Title="Scalability of the Directory Entry Cache"
@ -727,6 +769,24 @@ Andrea Arcangeli and Andi Kleen and Orran Krieger and Rusty Russell"
}
}
@conference{Michael02a
,author="Maged M. Michael"
,title="Safe Memory Reclamation for Dynamic Lock-Free Objects Using Atomic
Reads and Writes"
,Year="2002"
,Month="August"
,booktitle="{Proceedings of the 21\textsuperscript{st} Annual ACM
Symposium on Principles of Distributed Computing}"
,pages="21-30"
,annotation={
Each thread keeps an array of pointers to items that it is
currently referencing. Sort of an inside-out garbage collection
mechanism, but one that requires the accessing code to explicitly
state its needs. Also requires read-side memory barriers on
most architectures.
}
}
@unpublished{Dickins02a
,author="Hugh Dickins"
,title="Use RCU for System-V IPC"
@ -735,6 +795,17 @@ Andrea Arcangeli and Andi Kleen and Orran Krieger and Rusty Russell"
,note="private communication"
}
@InProceedings{HerlihyLM02
,author={Maurice Herlihy and Victor Luchangco and Mark Moir}
,title="The Repeat Offender Problem: A Mechanism for Supporting Dynamic-Sized,
Lock-Free Data Structures"
,booktitle={Proceedings of 16\textsuperscript{th} International
Symposium on Distributed Computing}
,year=2002
,month="October"
,pages="339-353"
}
@unpublished{Sarma02b
,Author="Dipankar Sarma"
,Title="Some dcache\_rcu benchmark numbers"
@ -749,6 +820,19 @@ Andrea Arcangeli and Andi Kleen and Orran Krieger and Rusty Russell"
}
}
@unpublished{MingmingCao2002IPCRCU
,Author="Mingming Cao"
,Title="[PATCH]updated ipc lock patch"
,month="October"
,year="2002"
,note="Available:
\url{https://lkml.org/lkml/2002/10/24/262}
[Viewed February 15, 2014]"
,annotation={
Mingming Cao's patch to introduce RCU to SysV IPC.
}
}
@unpublished{LinusTorvalds2003a
,Author="Linus Torvalds"
,Title="Re: {[PATCH]} small fixes in brlock.h"
@ -982,6 +1066,23 @@ Realtime Applications"
}
}
@article{MagedMichael04a
,author="Maged M. Michael"
,title="Hazard Pointers: Safe Memory Reclamation for Lock-Free Objects"
,Year="2004"
,Month="June"
,journal="IEEE Transactions on Parallel and Distributed Systems"
,volume="15"
,number="6"
,pages="491-504"
,url="Available:
\url{http://www.research.ibm.com/people/m/michael/ieeetpds-2004.pdf}
[Viewed March 1, 2005]"
,annotation={
New canonical hazard-pointer citation.
}
}
@phdthesis{PaulEdwardMcKenneyPhD
,author="Paul E. McKenney"
,title="Exploiting Deferred Destruction:

18
Documentation/RCU/checklist.txt
View File

@ -256,10 +256,10 @@ over a rather long period of time, but improvements are always welcome!
variations on this theme.
b. Limiting update rate. For example, if updates occur only
once per hour, then no explicit rate limiting is required,
unless your system is already badly broken. The dcache
subsystem takes this approach -- updates are guarded
by a global lock, limiting their rate.
once per hour, then no explicit rate limiting is
required, unless your system is already badly broken.
Older versions of the dcache subsystem take this approach,
guarding updates with a global lock, limiting their rate.
c. Trusted update -- if updates can only be done manually by
superuser or some other trusted user, then it might not
@ -268,7 +268,8 @@ over a rather long period of time, but improvements are always welcome!
the machine.
d. Use call_rcu_bh() rather than call_rcu(), in order to take
advantage of call_rcu_bh()'s faster grace periods.
advantage of call_rcu_bh()'s faster grace periods. (This
is only a partial solution, though.)
e. Periodically invoke synchronize_rcu(), permitting a limited
number of updates per grace period.
@ -276,6 +277,13 @@ over a rather long period of time, but improvements are always welcome!
The same cautions apply to call_rcu_bh(), call_rcu_sched(),
call_srcu(), and kfree_rcu().
Note that although these primitives do take action to avoid memory
exhaustion when any given CPU has too many callbacks, a determined
user could still exhaust memory. This is especially the case
if a system with a large number of CPUs has been configured to
offload all of its RCU callbacks onto a single CPU, or if the
system has relatively little free memory.
9. All RCU list-traversal primitives, which include
rcu_dereference(), list_for_each_entry_rcu(), and
list_for_each_safe_rcu(), must be either within an RCU read-side

50
Documentation/SubmittingPatches
View File

@ -14,7 +14,10 @@ Read Documentation/SubmitChecklist for a list of items to check
before submitting code. If you are submitting a driver, also read
Documentation/SubmittingDrivers.
Many of these steps describe the default behavior of the git version
control system; if you use git to prepare your patches, you'll find much
of the mechanical work done for you, though you'll still need to prepare
and document a sensible set of patches.
--------------------------------------------
SECTION 1 - CREATING AND SENDING YOUR CHANGE
@ -25,7 +28,9 @@ SECTION 1 - CREATING AND SENDING YOUR CHANGE
1) "diff -up"
------------
Use "diff -up" or "diff -uprN" to create patches.
Use "diff -up" or "diff -uprN" to create patches. git generates patches
in this form by default; if you're using git, you can skip this section
entirely.
All changes to the Linux kernel occur in the form of patches, as
generated by diff(1). When creating your patch, make sure to create it
@ -66,19 +71,14 @@ Make sure your patch does not include any extra files which do not
belong in a patch submission. Make sure to review your patch -after-
generated it with diff(1), to ensure accuracy.
If your changes produce a lot of deltas, you may want to look into
splitting them into individual patches which modify things in
logical stages. This will facilitate easier reviewing by other
kernel developers, very important if you want your patch accepted.
There are a number of scripts which can aid in this:
If your changes produce a lot of deltas, you need to split them into
individual patches which modify things in logical stages; see section
#3. This will facilitate easier reviewing by other kernel developers,
very important if you want your patch accepted.
Quilt:
http://savannah.nongnu.org/projects/quilt
Andrew Morton's patch scripts:
http://userweb.kernel.org/~akpm/stuff/patch-scripts.tar.gz
Instead of these scripts, quilt is the recommended patch management
tool (see above).
If you're using git, "git rebase -i" can help you with this process. If
you're not using git, quilt <http://savannah.nongnu.org/projects/quilt>
is another popular alternative.
@ -106,8 +106,21 @@ I.e., the patch (series) and its description should be self-contained.
This benefits both the patch merger(s) and reviewers. Some reviewers
probably didn't even receive earlier versions of the patch.
Describe your changes in imperative mood, e.g. "make xyzzy do frotz"
instead of "[This patch] makes xyzzy do frotz" or "[I] changed xyzzy
to do frotz", as if you are giving orders to the codebase to change
its behaviour.
If the patch fixes a logged bug entry, refer to that bug entry by
number and URL.
number and URL. If the patch follows from a mailing list discussion,
give a URL to the mailing list archive; use the https://lkml.kernel.org/
redirector with a Message-Id, to ensure that the links cannot become
stale.
However, try to make your explanation understandable without external
resources. In addition to giving a URL to a mailing list archive or
bug, summarize the relevant points of the discussion that led to the
patch as submitted.
If you want to refer to a specific commit, don't just refer to the
SHA-1 ID of the commit. Please also include the oneline summary of
@ -594,7 +607,8 @@ patch.
If you are going to include a diffstat after the "---" marker, please
use diffstat options "-p 1 -w 70" so that filenames are listed from
the top of the kernel source tree and don't use too much horizontal
space (easily fit in 80 columns, maybe with some indentation).
space (easily fit in 80 columns, maybe with some indentation). (git
generates appropriate diffstats by default.)
See more details on the proper patch format in the following
references.
@ -725,7 +739,7 @@ SECTION 3 - REFERENCES
----------------------
Andrew Morton, "The perfect patch" (tpp).
<http://userweb.kernel.org/~akpm/stuff/tpp.txt>
<http://www.ozlabs.org/~akpm/stuff/tpp.txt>
Jeff Garzik, "Linux kernel patch submission format".
<http://linux.yyz.us/patch-format.html>
@ -738,7 +752,7 @@ Greg Kroah-Hartman, "How to piss off a kernel subsystem maintainer".
<http://www.kroah.com/log/linux/maintainer-05.html>
NO!!!! No more huge patch bombs to linux-kernel@vger.kernel.org people!
<http://marc.theaimsgroup.com/?l=linux-kernel&m=112112749912944&w=2>
<https://lkml.org/lkml/2005/7/11/336>
Kernel Documentation/CodingStyle:
<http://users.sosdg.org/~qiyong/lxr/source/Documentation/CodingStyle>

12
Documentation/arm/Marvell/README
View File

@ -83,14 +83,24 @@ EBU Armada family
88F6710
88F6707
88F6W11
Product Brief: http://www.marvell.com/embedded-processors/armada-300/assets/Marvell_ARMADA_370_SoC.pdf
Armada 375 Flavors:
88F6720
Product Brief: http://www.marvell.com/embedded-processors/armada-300/assets/ARMADA_375_SoC-01_product_brief.pdf
Armada 380/385 Flavors:
88F6810
88F6820
88F6828
Armada XP Flavors:
MV78230
MV78260
MV78460
NOTE: not to be confused with the non-SMP 78xx0 SoCs
Product Brief: http://www.marvell.com/embedded-processors/armada-xp/assets/Marvell-ArmadaXP-SoC-product%20brief.pdf
Product Brief: http://www.marvell.com/embedded-processors/armada-xp/assets/Marvell-ArmadaXP-SoC-product%20brief.pdf
No public datasheet available.
Core: Sheeva ARMv7 compatible

10
Documentation/arm64/booting.txt
View File

@ -111,8 +111,14 @@ Before jumping into the kernel, the following conditions must be met:
- Caches, MMUs
The MMU must be off.
Instruction cache may be on or off.
Data cache must be off and invalidated.
External caches (if present) must be configured and disabled.
The address range corresponding to the loaded kernel image must be
cleaned to the PoC. In the presence of a system cache or other
coherent masters with caches enabled, this will typically require
cache maintenance by VA rather than set/way operations.
System caches which respect the architected cache maintenance by VA
operations must be configured and may be enabled.
System caches which do not respect architected cache maintenance by VA
operations (not recommended) must be configured and disabled.
- Architected timers
CNTFRQ must be programmed with the timer frequency and CNTVOFF must

16
Documentation/arm64/memory.txt
View File

@ -35,11 +35,13 @@ ffffffbc00000000 ffffffbdffffffff 8GB vmemmap
ffffffbe00000000 ffffffbffbbfffff ~8GB [guard, future vmmemap]
ffffffbffbc00000 ffffffbffbdfffff 2MB earlyprintk device
ffffffbffa000000 ffffffbffaffffff 16MB PCI I/O space
ffffffbffbe00000 ffffffbffbe0ffff 64KB PCI I/O space
ffffffbffb000000 ffffffbffbbfffff 12MB [guard]
ffffffbffbe10000 ffffffbcffffffff ~2MB [guard]
ffffffbffbc00000 ffffffbffbdfffff 2MB fixed mappings
ffffffbffbe00000 ffffffbffbffffff 2MB [guard]
ffffffbffc000000 ffffffbfffffffff 64MB modules
@ -60,11 +62,13 @@ fffffdfc00000000 fffffdfdffffffff 8GB vmemmap
fffffdfe00000000 fffffdfffbbfffff ~8GB [guard, future vmmemap]
fffffdfffbc00000 fffffdfffbdfffff 2MB earlyprintk device
fffffdfffa000000 fffffdfffaffffff 16MB PCI I/O space
fffffdfffbe00000 fffffdfffbe0ffff 64KB PCI I/O space
fffffdfffb000000 fffffdfffbbfffff 12MB [guard]
fffffdfffbe10000 fffffdfffbffffff ~2MB [guard]
fffffdfffbc00000 fffffdfffbdfffff 2MB fixed mappings
fffffdfffbe00000 fffffdfffbffffff 2MB [guard]
fffffdfffc000000 fffffdffffffffff 64MB modules

38
Documentation/blockdev/drbd/data-structure-v9.txt Normal file
View File

@ -0,0 +1,38 @@
This describes the in kernel data structure for DRBD-9. Starting with
Linux v3.14 we are reorganizing DRBD to use this data structure.
Basic Data Structure
====================
A node has a number of DRBD resources. Each such resource has a number of
devices (aka volumes) and connections to other nodes ("peer nodes"). Each DRBD
device is represented by a block device locally.
The DRBD objects are interconnected to form a matrix as depicted below; a
drbd_peer_device object sits at each intersection between a drbd_device and a
drbd_connection:
/--------------+---------------+.....+---------------\
| resource | device | | device |
+--------------+---------------+.....+---------------+
| connection | peer_device | | peer_device |
+--------------+---------------+.....+---------------+
: : : : :
: : : : :
+--------------+---------------+.....+---------------+
| connection | peer_device | | peer_device |
\--------------+---------------+.....+---------------/
In this table, horizontally, devices can be accessed from resources by their
volume number. Likewise, peer_devices can be accessed from connections by
their volume number. Objects in the vertical direction are connected by double
linked lists. There are back pointers from peer_devices to their connections a
devices, and from connections and devices to their resource.
All resources are in the drbd_resources double-linked list. In addition, all
devices can be accessed by their minor device number via the drbd_devices idr.
The drbd_resource, drbd_connection, and drbd_device objects are reference
counted. The peer_device objects only serve to establish the links between
devices and connections; their lifetime is determined by the lifetime of the
device and connection which they reference.

54
Documentation/blockdev/zram.txt
View File

@ -21,7 +21,43 @@ Following shows a typical sequence of steps for using zram.
This creates 4 devices: /dev/zram{0,1,2,3}
(num_devices parameter is optional. Default: 1)
2) Set Disksize
2) Set max number of compression streams
Compression backend may use up to max_comp_streams compression streams,
thus allowing up to max_comp_streams concurrent compression operations.
By default, compression backend uses single compression stream.
Examples:
#show max compression streams number
cat /sys/block/zram0/max_comp_streams
#set max compression streams number to 3
echo 3 > /sys/block/zram0/max_comp_streams
Note:
In order to enable compression backend's multi stream support max_comp_streams
must be initially set to desired concurrency level before ZRAM device
initialisation. Once the device initialised as a single stream compression
backend (max_comp_streams equals to 1), you will see error if you try to change
the value of max_comp_streams because single stream compression backend
implemented as a special case by lock overhead issue and does not support
dynamic max_comp_streams. Only multi stream backend supports dynamic
max_comp_streams adjustment.
3) Select compression algorithm
Using comp_algorithm device attribute one can see available and
currently selected (shown in square brackets) compression algortithms,
change selected compression algorithm (once the device is initialised
there is no way to change compression algorithm).
Examples:
#show supported compression algorithms
cat /sys/block/zram0/comp_algorithm
lzo [lz4]
#select lzo compression algorithm
echo lzo > /sys/block/zram0/comp_algorithm
4) Set Disksize
Set disk size by writing the value to sysfs node 'disksize'.
The value can be either in bytes or you can use mem suffixes.
Examples:
@ -33,32 +69,38 @@ Following shows a typical sequence of steps for using zram.
echo 512M > /sys/block/zram0/disksize
echo 1G > /sys/block/zram0/disksize
3) Activate:
Note:
There is little point creating a zram of greater than twice the size of memory
since we expect a 2:1 compression ratio. Note that zram uses about 0.1% of the
size of the disk when not in use so a huge zram is wasteful.
5) Activate:
mkswap /dev/zram0
swapon /dev/zram0
mkfs.ext4 /dev/zram1
mount /dev/zram1 /tmp
4) Stats:
6) Stats:
Per-device statistics are exported as various nodes under
/sys/block/zram<id>/
disksize
num_reads
num_writes
failed_reads
failed_writes
invalid_io
notify_free
discard
zero_pages
orig_data_size
compr_data_size
mem_used_total
5) Deactivate:
7) Deactivate:
swapoff /dev/zram0
umount /dev/zram1
6) Reset:
8) Reset:
Write any positive value to 'reset' sysfs node
echo 1 > /sys/block/zram0/reset
echo 1 > /sys/block/zram1/reset

4
Documentation/cgroups/memcg_test.txt
View File

@ -24,7 +24,7 @@ Please note that implementation details can be changed.
a page/swp_entry may be charged (usage += PAGE_SIZE) at
mem_cgroup_newpage_charge()
mem_cgroup_charge_anon()
Called at new page fault and Copy-On-Write.
mem_cgroup_try_charge_swapin()
@ -32,7 +32,7 @@ Please note that implementation details can be changed.
Followed by charge-commit-cancel protocol. (With swap accounting)
At commit, a charge recorded in swap_cgroup is removed.
mem_cgroup_cache_charge()
mem_cgroup_charge_file()
Called at add_to_page_cache()
mem_cgroup_cache_charge_swapin()

12
Documentation/cgroups/resource_counter.txt
View File

@ -76,15 +76,7 @@ to work with it.
limit_fail_at parameter is set to the particular res_counter element
where the charging failed.
d. int res_counter_charge_locked
(struct res_counter *rc, unsigned long val, bool force)
The same as res_counter_charge(), but it must not acquire/release the
res_counter->lock internally (it must be called with res_counter->lock
held). The force parameter indicates whether we can bypass the limit.
e. u64 res_counter_uncharge[_locked]
(struct res_counter *rc, unsigned long val)
d. u64 res_counter_uncharge(struct res_counter *rc, unsigned long val)
When a resource is released (freed) it should be de-accounted
from the resource counter it was accounted to. This is called
@ -93,7 +85,7 @@ to work with it.
The _locked routines imply that the res_counter->lock is taken.
f. u64 res_counter_uncharge_until
e. u64 res_counter_uncharge_until
(struct res_counter *rc, struct res_counter *top,
unsigned long val)

34
Documentation/clk.txt
View File

@ -255,3 +255,37 @@ are sorted out.
To bypass this disabling, include "clk_ignore_unused" in the bootargs to the
kernel.
Part 7 - Locking
The common clock framework uses two global locks, the prepare lock and the
enable lock.
The enable lock is a spinlock and is held across calls to the .enable,
.disable and .is_enabled operations. Those operations are thus not allowed to
sleep, and calls to the clk_enable(), clk_disable() and clk_is_enabled() API
functions are allowed in atomic context.
The prepare lock is a mutex and is held across calls to all other operations.
All those operations are allowed to sleep, and calls to the corresponding API
functions are not allowed in atomic context.
This effectively divides operations in two groups from a locking perspective.
Drivers don't need to manually protect resources shared between the operations
of one group, regardless of whether those resources are shared by multiple
clocks or not. However, access to resources that are shared between operations
of the two groups needs to be protected by the drivers. An example of such a
resource would be a register that controls both the clock rate and the clock
enable/disable state.
The clock framework is reentrant, in that a driver is allowed to call clock
framework functions from within its implementation of clock operations. This
can for instance cause a .set_rate operation of one clock being called from
within the .set_rate operation of another clock. This case must be considered
in the driver implementations, but the code flow is usually controlled by the
driver in that case.
Note that locking must also be considered when code outside of the common
clock framework needs to access resources used by the clock operations. This
is considered out of scope of this document.

2
Documentation/connector/cn_test.c
View File

@ -145,7 +145,7 @@ static void cn_test_timer_func(unsigned long __data)
memcpy(m + 1, data, m->len);
cn_netlink_send(m, 0, GFP_ATOMIC);
cn_netlink_send(m, 0, 0, GFP_ATOMIC);
kfree(m);
}

4
Documentation/cpu-freq/core.txt
View File

@ -92,7 +92,3 @@ values:
cpu - number of the affected CPU
old - old frequency
new - new frequency
If the cpufreq core detects the frequency has changed while the system
was suspended, these notifiers are called with CPUFREQ_RESUMECHANGE as
second argument.

8
Documentation/cpu-freq/cpu-drivers.txt
View File

@ -61,7 +61,13 @@ target_index - See below on the differences.
And optionally
cpufreq_driver.exit - A pointer to a per-CPU cleanup function.
cpufreq_driver.exit - A pointer to a per-CPU cleanup
function called during CPU_POST_DEAD
phase of cpu hotplug process.
cpufreq_driver.stop_cpu - A pointer to a per-CPU stop function
called during CPU_DOWN_PREPARE phase of
cpu hotplug process.
cpufreq_driver.resume - A pointer to a per-CPU resume function
which is called with interrupts disabled

45
Documentation/cpu-hotplug.txt
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@ -312,12 +312,57 @@ things will happen if a notifier in path sent a BAD notify code.
Q: I don't see my action being called for all CPUs already up and running?
A: Yes, CPU notifiers are called only when new CPUs are on-lined or offlined.
If you need to perform some action for each cpu already in the system, then
do this:
for_each_online_cpu(i) {
foobar_cpu_callback(&foobar_cpu_notifier, CPU_UP_PREPARE, i);
foobar_cpu_callback(&foobar_cpu_notifier, CPU_ONLINE, i);
}
However, if you want to register a hotplug callback, as well as perform
some initialization for CPUs that are already online, then do this:
Version 1: (Correct)
---------
cpu_notifier_register_begin();
for_each_online_cpu(i) {
foobar_cpu_callback(&foobar_cpu_notifier,
CPU_UP_PREPARE, i);
foobar_cpu_callback(&foobar_cpu_notifier,
CPU_ONLINE, i);
}
/* Note the use of the double underscored version of the API */
__register_cpu_notifier(&foobar_cpu_notifier);
cpu_notifier_register_done();
Note that the following code is *NOT* the right way to achieve this,
because it is prone to an ABBA deadlock between the cpu_add_remove_lock
and the cpu_hotplug.lock.
Version 2: (Wrong!)
---------
get_online_cpus();
for_each_online_cpu(i) {
foobar_cpu_callback(&foobar_cpu_notifier,
CPU_UP_PREPARE, i);
foobar_cpu_callback(&foobar_cpu_notifier,
CPU_ONLINE, i);
}
register_cpu_notifier(&foobar_cpu_notifier);
put_online_cpus();
So always use the first version shown above when you want to register
callbacks as well as initialize the already online CPUs.
Q: If i would like to develop cpu hotplug support for a new architecture,
what do i need at a minimum?
A: The following are what is required for CPU hotplug infrastructure to work

11
Documentation/device-mapper/cache.txt
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@ -124,12 +124,11 @@ the default being 204800 sectors (or 100MB).
Updating on-disk metadata
-------------------------
On-disk metadata is committed every time a REQ_SYNC or REQ_FUA bio is
written. If no such requests are made then commits will occur every
second. This means the cache behaves like a physical disk that has a
write cache (the same is true of the thin-provisioning target). If
power is lost you may lose some recent writes. The metadata should
always be consistent in spite of any crash.
On-disk metadata is committed every time a FLUSH or FUA bio is written.
If no such requests are made then commits will occur every second. This
means the cache behaves like a physical disk that has a volatile write
cache. If power is lost you may lose some recent writes. The metadata
should always be consistent in spite of any crash.
The 'dirty' state for a cache block changes far too frequently for us
to keep updating it on the fly. So we treat it as a hint. In normal

108
Documentation/device-mapper/era.txt Normal file
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@ -0,0 +1,108 @@
Introduction
============
dm-era is a target that behaves similar to the linear target. In
addition it keeps track of which blocks were written within a user
defined period of time called an 'era'. Each era target instance
maintains the current era as a monotonically increasing 32-bit
counter.
Use cases include tracking changed blocks for backup software, and
partially invalidating the contents of a cache to restore cache
coherency after rolling back a vendor snapshot.
Constructor
===========
era <metadata dev> <origin dev> <block size>
metadata dev : fast device holding the persistent metadata
origin dev : device holding data blocks that may change
block size : block size of origin data device, granularity that is
tracked by the target
Messages
========
None of the dm messages take any arguments.
checkpoint
----------
Possibly move to a new era. You shouldn't assume the era has
incremented. After sending this message, you should check the
current era via the status line.
take_metadata_snap
------------------
Create a clone of the metadata, to allow a userland process to read it.
drop_metadata_snap
------------------
Drop the metadata snapshot.
Status
======
<metadata block size> <#used metadata blocks>/<#total metadata blocks>
<current era> <held metadata root | '-'>
metadata block size : Fixed block size for each metadata block in
sectors
#used metadata blocks : Number of metadata blocks used
#total metadata blocks : Total number of metadata blocks
current era : The current era
held metadata root : The location, in blocks, of the metadata root
that has been 'held' for userspace read
access. '-' indicates there is no held root
Detailed use case
=================
The scenario of invalidating a cache when rolling back a vendor
snapshot was the primary use case when developing this target:
Taking a vendor snapshot
------------------------
- Send a checkpoint message to the era target
- Make a note of the current era in its status line
- Take vendor snapshot (the era and snapshot should be forever
associated now).
Rolling back to an vendor snapshot
----------------------------------
- Cache enters passthrough mode (see: dm-cache's docs in cache.txt)
- Rollback vendor storage
- Take metadata snapshot
- Ascertain which blocks have been written since the snapshot was taken
by checking each block's era
- Invalidate those blocks in the caching software
- Cache returns to writeback/writethrough mode
Memory usage
============
The target uses a bitset to record writes in the current era. It also
has a spare bitset ready for switching over to a new era. Other than
that it uses a few 4k blocks for updating metadata.
(4 * nr_blocks) bytes + buffers
Resilience
==========
Metadata is updated on disk before a write to a previously unwritten
block is performed. As such dm-era should not be effected by a hard
crash such as power failure.
Userland tools
==============
Userland tools are found in the increasingly poorly named
thin-provisioning-tools project:
https://github.com/jthornber/thin-provisioning-tools

34
Documentation/device-mapper/thin-provisioning.txt
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@ -116,6 +116,35 @@ Resuming a device with a new table itself triggers an event so the
userspace daemon can use this to detect a situation where a new table
already exceeds the threshold.
A low water mark for the metadata device is maintained in the kernel and
will trigger a dm event if free space on the metadata device drops below
it.
Updating on-disk metadata
-------------------------
On-disk metadata is committed every time a FLUSH or FUA bio is written.
If no such requests are made then commits will occur every second. This
means the thin-provisioning target behaves like a physical disk that has
a volatile write cache. If power is lost you may lose some recent
writes. The metadata should always be consistent in spite of any crash.
If data space is exhausted the pool will either error or queue IO
according to the configuration (see: error_if_no_space). If metadata
space is exhausted or a metadata operation fails: the pool will error IO
until the pool is taken offline and repair is performed to 1) fix any
potential inconsistencies and 2) clear the flag that imposes repair.
Once the pool's metadata device is repaired it may be resized, which
will allow the pool to return to normal operation. Note that if a pool
is flagged as needing repair, the pool's data and metadata devices
cannot be resized until repair is performed. It should also be noted
that when the pool's metadata space is exhausted the current metadata
transaction is aborted. Given that the pool will cache IO whose
completion may have already been acknowledged to upper IO layers
(e.g. filesystem) it is strongly suggested that consistency checks
(e.g. fsck) be performed on those layers when repair of the pool is
required.
Thin provisioning
-----------------
@ -258,10 +287,9 @@ ii) Status
should register for the event and then check the target's status.
held metadata root:
The location, in sectors, of the metadata root that has been
The location, in blocks, of the metadata root that has been
'held' for userspace read access. '-' indicates there is no
held root. This feature is not yet implemented so '-' is
always returned.
held root.
discard_passdown|no_discard_passdown
Whether or not discards are actually being passed down to the

3
Documentation/devices.txt
View File

@ -353,6 +353,7 @@ Your cooperation is appreciated.
133 = /dev/exttrp External device trap
134 = /dev/apm_bios Advanced Power Management BIOS
135 = /dev/rtc Real Time Clock
137 = /dev/vhci Bluetooth virtual HCI driver
139 = /dev/openprom SPARC OpenBoot PROM
140 = /dev/relay8 Berkshire Products Octal relay card
141 = /dev/relay16 Berkshire Products ISO-16 relay card
@ -410,6 +411,7 @@ Your cooperation is appreciated.
194 = /dev/zkshim Zero-Knowledge network shim control
195 = /dev/elographics/e2201 Elographics touchscreen E271-2201
196 = /dev/vfio/vfio VFIO userspace driver interface
197 = /dev/pxa3xx-gcu PXA3xx graphics controller unit driver
198 = /dev/sexec Signed executable interface
199 = /dev/scanners/cuecat :CueCat barcode scanner
200 = /dev/net/tun TAP/TUN network device
@ -451,6 +453,7 @@ Your cooperation is appreciated.
236 = /dev/mapper/control Device-Mapper control device
237 = /dev/loop-control Loopback control device
238 = /dev/vhost-net Host kernel accelerator for virtio net
239 = /dev/uhid User-space I/O driver support for HID subsystem
240-254 Reserved for local use
255 Reserved for MISC_DYNAMIC_MINOR

8
Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
View File

@ -1,4 +1,4 @@
Marvell Armada 370 and Armada XP Interrupt Controller
Marvell Armada 370, 375, 38x, XP Interrupt Controller
-----------------------------------------------------
Required properties:
@ -16,7 +16,13 @@ Required properties:
automatically map to the interrupt controller registers of the
current CPU)
Optional properties:
- interrupts: If defined, then it indicates that this MPIC is
connected as a slave to another interrupt controller. This is
typically the case on Armada 375 and Armada 38x, where the MPIC is
connected as a slave to the Cortex-A9 GIC. The provided interrupt
indicate to which GIC interrupt the MPIC output is connected.
Example:

9
Documentation/devicetree/bindings/arm/armada-375.txt Normal file
View File

@ -0,0 +1,9 @@
Marvell Armada 375 Platforms Device Tree Bindings
-------------------------------------------------
Boards with a SoC of the Marvell Armada 375 family shall have the
following property:
Required root node property:
compatible: must contain "marvell,armada375"

10
Documentation/devicetree/bindings/arm/armada-38x.txt Normal file
View File

@ -0,0 +1,10 @@
Marvell Armada 38x Platforms Device Tree Bindings
-------------------------------------------------
Boards with a SoC of the Marvell Armada 38x family shall have the
following property:
Required root node property:
- compatible: must contain either "marvell,armada380" or
"marvell,armada385" depending on the variant of the SoC being used.

15
Documentation/devicetree/bindings/arm/bcm/bcm21664.txt Normal file
View File

@ -0,0 +1,15 @@
Broadcom BCM21664 device tree bindings
--------------------------------------
This document describes the device tree bindings for boards with the BCM21664
SoC.
Required root node property:
- compatible: brcm,bcm21664
Example:
/ {
model = "BCM21664 SoC";
compatible = "brcm,bcm21664";
[...]
}

14
Documentation/devicetree/bindings/arm/bcm/kona-resetmgr.txt Normal file
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@ -0,0 +1,14 @@
Broadcom Kona Family Reset Manager
----------------------------------
The reset manager is used on the Broadcom BCM21664 SoC.
Required properties:
- compatible: brcm,bcm21664-resetmgr
- reg: memory address & range
Example:
brcm,resetmgr@35001f00 {
compatible = "brcm,bcm21664-resetmgr";
reg = <0x35001f00 0x24>;
};

8
Documentation/devicetree/bindings/arm/bcm4708.txt Normal file
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@ -0,0 +1,8 @@
Broadcom BCM4708 device tree bindings
-------------------------------------------
Boards with the BCM4708 SoC shall have the following properties:
Required root node property:
compatible = "brcm,bcm4708";

25
Documentation/devicetree/bindings/arm/cpus.txt
View File

@ -180,7 +180,11 @@ nodes to be present and contain the properties described below.
be one of:
"spin-table"
"psci"
# On ARM 32-bit systems this property is optional.
# On ARM 32-bit systems this property is optional and
can be one of:
"qcom,gcc-msm8660"
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
- cpu-release-addr
Usage: required for systems that have an "enable-method"
@ -191,6 +195,21 @@ nodes to be present and contain the properties described below.
property identifying a 64-bit zero-initialised
memory location.
- qcom,saw
Usage: required for systems that have an "enable-method"
property value of "qcom,kpss-acc-v1" or
"qcom,kpss-acc-v2"
Value type: <phandle>
Definition: Specifies the SAW[1] node associated with this CPU.
- qcom,acc
Usage: required for systems that have an "enable-method"
property value of "qcom,kpss-acc-v1" or
"qcom,kpss-acc-v2"
Value type: <phandle>
Definition: Specifies the ACC[2] node associated with this CPU.
Example 1 (dual-cluster big.LITTLE system 32-bit):
cpus {
@ -382,3 +401,7 @@ cpus {
cpu-release-addr = <0 0x20000000>;
};
};
--
[1] arm/msm/qcom,saw2.txt
[2] arm/msm/qcom,kpss-acc.txt

6
Documentation/devicetree/bindings/arm/gic.txt
View File

@ -50,6 +50,11 @@ Optional
regions, used when the GIC doesn't have banked registers. The offset is
cpu-offset * cpu-nr.
- arm,routable-irqs : Total number of gic irq inputs which are not directly
connected from the peripherals, but are routed dynamically
by a crossbar/multiplexer preceding the GIC. The GIC irq
input line is assigned dynamically when the corresponding
peripheral's crossbar line is mapped.
Example:
intc: interrupt-controller@fff11000 {
@ -57,6 +62,7 @@ Example:
#interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller;
arm,routable-irqs = <160>;
reg = <0xfff11000 0x1000>,
<0xfff10100 0x100>;
};

14
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
View File

@ -30,3 +30,17 @@ Example:
resume-offset = <0x308>;
reboot-offset = <0x4>;
};
PCTRL: Peripheral misc control register
Required Properties:
- compatible: "hisilicon,pctrl"
- reg: Address and size of pctrl.
Example:
/* for Hi3620 */
pctrl: pctrl@fca09000 {
compatible = "hisilicon,pctrl";
reg = <0xfca09000 0x1000>;
};

10
Documentation/devicetree/bindings/arm/keystone/keystone.txt
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@ -8,3 +8,13 @@ Required properties:
- compatible: All TI specific devices present in Keystone SOC should be in
the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550
type UART should use the specified compatible for those devices.
Boards:
- Keystone 2 Hawking/Kepler EVM
compatible = "ti,k2hk-evm","ti,keystone"
- Keystone 2 Lamarr EVM
compatible = "ti,k2l-evm","ti,keystone"
- Keystone 2 Edison EVM
compatible = "ti,k2e-evm","ti,keystone"

22
Documentation/devicetree/bindings/arm/marvell,dove.txt Normal file
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@ -0,0 +1,22 @@
Marvell Dove Platforms Device Tree Bindings
-----------------------------------------------
Boards with a Marvell Dove SoC shall have the following properties:
Required root node property:
- compatible: must contain "marvell,dove";
* Global Configuration registers
Global Configuration registers of Dove SoC are shared by a syscon node.
Required properties:
- compatible: must contain "marvell,dove-global-config" and "syscon".
- reg: base address and size of the Global Configuration registers.
Example:
gconf: global-config@e802c {
compatible = "marvell,dove-global-config", "syscon";
reg = <0xe802c 0x14>;
};

16
Documentation/devicetree/bindings/arm/mrvl/feroceon.txt Normal file
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@ -0,0 +1,16 @@
* Marvell Feroceon Cache
Required properties:
- compatible : Should be either "marvell,feroceon-cache" or
"marvell,kirkwood-cache".
Optional properties:
- reg : Address of the L2 cache control register. Mandatory for
"marvell,kirkwood-cache", not used by "marvell,feroceon-cache"
Example:
l2: l2-cache@20128 {
compatible = "marvell,kirkwood-cache";
reg = <0x20128 0x4>;
};

30
Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt Normal file
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@ -0,0 +1,30 @@
Krait Processor Sub-system (KPSS) Application Clock Controller (ACC)
The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
There is one ACC register region per CPU within the KPSS remapped region as
well as an alias register region that remaps accesses to the ACC associated
with the CPU accessing the region.
PROPERTIES
- compatible:
Usage: required
Value type: <string>
Definition: should be one of:
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the first element specifies the base address and size of
the register region. An optional second element specifies
the base address and size of the alias register region.
Example:
clock-controller@2088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x02088000 0x1000>,
<0x02008000 0x1000>;
};

35
Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt Normal file
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@ -0,0 +1,35 @@
SPM AVS Wrapper 2 (SAW2)
The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
micro-controller that transitions a piece of hardware (like a processor or
subsystem) into and out of low power modes via a direct connection to
the PMIC. It can also be wired up to interact with other processors in the
system, notifying them when a low power state is entered or exited.
PROPERTIES
- compatible:
Usage: required
Value type: <string>
Definition: shall contain "qcom,saw2". A more specific value should be
one of:
"qcom,saw2-v1"
"qcom,saw2-v1.1"
"qcom,saw2-v2"
"qcom,saw2-v2.1"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the first element specifies the base address and size of
the register region. An optional second element specifies
the base address and size of the alias register region.
Example:
regulator@2099000 {
compatible = "qcom,saw2";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
};

3
Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
View File

@ -1,12 +1,13 @@
MVEBU System Controller
-----------------------
MVEBU (Marvell SOCs: Armada 370/XP, Dove, mv78xx0, Kirkwood, Orion5x)
MVEBU (Marvell SOCs: Armada 370/375/XP, Dove, mv78xx0, Kirkwood, Orion5x)
Required properties:
- compatible: one of:
- "marvell,orion-system-controller"
- "marvell,armada-370-xp-system-controller"
- "marvell,armada-375-system-controller"
- reg: Should contain system controller registers location and length.
Example:

27
Documentation/devicetree/bindings/arm/omap/crossbar.txt Normal file
View File

@ -0,0 +1,27 @@
Some socs have a large number of interrupts requests to service
the needs of its many peripherals and subsystems. All of the
interrupt lines from the subsystems are not needed at the same
time, so they have to be muxed to the irq-controller appropriately.
In such places a interrupt controllers are preceded by an CROSSBAR
that provides flexibility in muxing the device requests to the controller
inputs.
Required properties:
- compatible : Should be "ti,irq-crossbar"
- reg: Base address and the size of the crossbar registers.
- ti,max-irqs: Total number of irqs available at the interrupt controller.
- ti,reg-size: Size of a individual register in bytes. Every individual
register is assumed to be of same size. Valid sizes are 1, 2, 4.
- ti,irqs-reserved: List of the reserved irq lines that are not muxed using
crossbar. These interrupt lines are reserved in the soc,
so crossbar bar driver should not consider them as free
lines.
Examples:
crossbar_mpu: @4a020000 {
compatible = "ti,irq-crossbar";
reg = <0x4a002a48 0x130>;
ti,max-irqs = <160>;
ti,reg-size = <2>;
ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
};

22
Documentation/devicetree/bindings/arm/omap/dmm.txt Normal file
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@ -0,0 +1,22 @@
OMAP Dynamic Memory Manager (DMM) bindings
The dynamic memory manager (DMM) is a module located immediately in front of the
SDRAM controllers (called EMIFs on OMAP). DMM manages various aspects of memory
accesses such as priority generation amongst initiators, configuration of SDRAM
interleaving, optimizing transfer of 2D block objects, and provide MMU-like page
translation for initiators which need contiguous dma bus addresses.
Required properties:
- compatible: Should contain "ti,omap4-dmm" for OMAP4 family
Should contain "ti,omap5-dmm" for OMAP5 and DRA7x family
- reg: Contains DMM register address range (base address and length)
- interrupts: Should contain an interrupt-specifier for DMM_IRQ.
- ti,hwmods: Name of the hwmod associated to DMM, which is typically "dmm"
Example:
dmm@4e000000 {
compatible = "ti,omap4-dmm";
reg = <0x4e000000 0x800>;
ti,hwmods = "dmm";
};

6
Documentation/devicetree/bindings/arm/omap/omap.txt
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@ -99,6 +99,9 @@ Boards:
- OMAP4 PandaBoard : Low cost community board
compatible = "ti,omap4-panda", "ti,omap4430"
- OMAP4 DuoVero with Parlor : Commercial expansion board with daughter board
compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4";
- OMAP3 EVM : Software Development Board for OMAP35x, AM/DM37x
compatible = "ti,omap3-evm", "ti,omap3"
@ -114,5 +117,8 @@ Boards:
- AM43x EPOS EVM
compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43"
- AM437x GP EVM
compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43"
- DRA7 EVM: Software Developement Board for DRA7XX
compatible = "ti,dra7-evm", "ti,dra7"

10
Documentation/devicetree/bindings/arm/pmu.txt
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@ -9,6 +9,7 @@ Required properties:
- compatible : should be one of
"arm,armv8-pmuv3"
"arm,cortex-a15-pmu"
"arm,cortex-a12-pmu"
"arm,cortex-a9-pmu"
"arm,cortex-a8-pmu"
"arm,cortex-a7-pmu"
@ -16,7 +17,14 @@ Required properties:
"arm,arm11mpcore-pmu"
"arm,arm1176-pmu"
"arm,arm1136-pmu"
- interrupts : 1 combined interrupt or 1 per core.
"qcom,krait-pmu"
- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
interrupt (PPI) then 1 interrupt should be specified.
Optional properties:
- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
events.
Example:

16
Documentation/devicetree/bindings/arm/rockchip/pmu.txt Normal file
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@ -0,0 +1,16 @@
Rockchip power-management-unit:
-------------------------------
The pmu is used to turn off and on different power domains of the SoCs
This includes the power to the CPU cores.
Required node properties:
- compatible value : = "rockchip,rk3066-pmu";
- reg : physical base address and the size of the registers window
Example:
pmu@20004000 {
compatible = "rockchip,rk3066-pmu";
reg = <0x20004000 0x100>;
};

30
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@ -0,0 +1,30 @@
Rockchip SRAM for smp bringup:
------------------------------
Rockchip's smp-capable SoCs use the first part of the sram for the bringup
of the cores. Once the core gets powered up it executes the code that is
residing at the very beginning of the sram.
Therefore a reserved section sub-node has to be added to the mmio-sram
declaration.
Required sub-node properties:
- compatible : should be "rockchip,rk3066-smp-sram"
The rest of the properties should follow the generic mmio-sram discription
found in ../../misc/sram.txt
Example:
sram: sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
smp-sram@10080000 {
compatible = "rockchip,rk3066-smp-sram";
reg = <0x10080000 0x50>;
};
};

15
Documentation/devicetree/bindings/arm/samsung/pmu.txt Normal file
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@ -0,0 +1,15 @@
SAMSUNG Exynos SoC series PMU Registers
Properties:
- compatible : should contain two values. First value must be one from following list:
- "samsung,exynos5250-pmu" - for Exynos5250 SoC,
- "samsung,exynos5420-pmu" - for Exynos5420 SoC.
second value must be always "syscon".
- reg : offset and length of the register set.
Example :
pmu_system_controller: system-controller@10040000 {
compatible = "samsung,exynos5250-pmu", "syscon";
reg = <0x10040000 0x5000>;
};

7
Documentation/devicetree/bindings/arm/topology.txt
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@ -75,9 +75,10 @@ The cpu-map node can only contain three types of child nodes:
whose bindings are described in paragraph 3.
The nodes describing the CPU topology (cluster/core/thread) can only be
defined within the cpu-map node.
Any other configuration is consider invalid and therefore must be ignored.
The nodes describing the CPU topology (cluster/core/thread) can only
be defined within the cpu-map node and every core/thread in the system
must be defined within the topology. Any other configuration is
invalid and therefore must be ignored.
===========================================
2.1 - cpu-map child nodes naming convention

22
Documentation/devicetree/bindings/ata/ahci-platform.txt
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@ -4,17 +4,33 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA controller should have its own node.
Required properties:
- compatible : compatible list, contains "snps,spear-ahci"
- compatible : compatible list, one of "snps,spear-ahci",
"snps,exynos5440-ahci", "ibm,476gtr-ahci",
"allwinner,sun4i-a10-ahci", "fsl,imx53-ahci"
"fsl,imx6q-ahci" or "snps,dwc-ahci"
- interrupts : <interrupt mapping for SATA IRQ>
- reg : <registers mapping>
Optional properties:
- dma-coherent : Present if dma operations are coherent
- clocks : a list of phandle + clock specifier pairs
- target-supply : regulator for SATA target power
Example:
"fsl,imx53-ahci", "fsl,imx6q-ahci" required properties:
- clocks : must contain the sata, sata_ref and ahb clocks
- clock-names : must contain "ahb" for the ahb clock
Examples:
sata@ffe08000 {
compatible = "snps,spear-ahci";
reg = <0xffe08000 0x1000>;
interrupts = <115>;
};
ahci: sata@01c18000 {
compatible = "allwinner,sun4i-a10-ahci";
reg = <0x01c18000 0x1000>;
interrupts = <56>;
clocks = <&pll6 0>, <&ahb_gates 25>;
target-supply = <&reg_ahci_5v>;
};

76
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@ -0,0 +1,76 @@
* APM X-Gene 6.0 Gb/s SATA host controller nodes
SATA host controller nodes are defined to describe on-chip Serial ATA
controllers. Each SATA controller (pair of ports) have its own node.
Required properties:
- compatible : Shall contain:
* "apm,xgene-ahci"
- reg : First memory resource shall be the AHCI memory
resource.
Second memory resource shall be the host controller
core memory resource.
Third memory resource shall be the host controller
diagnostic memory resource.
4th memory resource shall be the host controller
AXI memory resource.
5th optional memory resource shall be the host
controller MUX memory resource if required.
- interrupts : Interrupt-specifier for SATA host controller IRQ.
- clocks : Reference to the clock entry.
- phys : A list of phandles + phy-specifiers, one for each
entry in phy-names.
- phy-names : Should contain:
* "sata-phy" for the SATA 6.0Gbps PHY
Optional properties:
- status : Shall be "ok" if enabled or "disabled" if disabled.
Default is "ok".
Example:
sataclk: sataclk {
compatible = "fixed-clock";
#clock-cells = <1>;
clock-frequency = <100000000>;
clock-output-names = "sataclk";
};
phy2: phy@1f22a000 {
compatible = "apm,xgene-phy";
reg = <0x0 0x1f22a000 0x0 0x100>;
#phy-cells = <1>;
};
phy3: phy@1f23a000 {
compatible = "apm,xgene-phy";
reg = <0x0 0x1f23a000 0x0 0x100>;
#phy-cells = <1>;
};
sata2: sata@1a400000 {
compatible = "apm,xgene-ahci";
reg = <0x0 0x1a400000 0x0 0x1000>,
<0x0 0x1f220000 0x0 0x1000>,
<0x0 0x1f22d000 0x0 0x1000>,
<0x0 0x1f22e000 0x0 0x1000>,
<0x0 0x1f227000 0x0 0x1000>;
interrupts = <0x0 0x87 0x4>;
status = "ok";
clocks = <&sataclk 0>;
phys = <&phy2 0>;
phy-names = "sata-phy";
};
sata3: sata@1a800000 {
compatible = "apm,xgene-ahci-pcie";
reg = <0x0 0x1a800000 0x0 0x1000>,
<0x0 0x1f230000 0x0 0x1000>,
<0x0 0x1f23d000 0x0 0x1000>,
<0x0 0x1f23e000 0x0 0x1000>,
<0x0 0x1f237000 0x0 0x1000>;
interrupts = <0x0 0x88 0x4>;
status = "ok";
clocks = <&sataclk 0>;
phys = <&phy3 0>;
phy-names = "sata-phy";
};

14
Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
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@ -1,14 +0,0 @@
* Samsung SATA PHY Controller
SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
Each SATA PHY controller should have its own node.
Required properties:
- compatible : compatible list, contains "samsung,exynos5-sata-phy"
- reg : <registers mapping>
Example:
sata@ffe07000 {
compatible = "samsung,exynos5-sata-phy";
reg = <0xffe07000 0x1000>;
};

31
Documentation/devicetree/bindings/ata/exynos-sata.txt
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@ -4,14 +4,27 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA controller should have its own node.
Required properties:
- compatible : compatible list, contains "samsung,exynos5-sata"
- interrupts : <interrupt mapping for SATA IRQ>
- reg : <registers mapping>
- samsung,sata-freq : <frequency in MHz>
- compatible : compatible list, contains "samsung,exynos5-sata"
- interrupts : <interrupt mapping for SATA IRQ>
- reg : <registers mapping>
- samsung,sata-freq : <frequency in MHz>
- phys : Must contain exactly one entry as specified
in phy-bindings.txt
- phy-names : Must be "sata-phy"
Optional properties:
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Shall be "sata" for the external SATA bus clock,
and "sclk_sata" for the internal controller clock.
Example:
sata@ffe08000 {
compatible = "samsung,exynos5-sata";
reg = <0xffe08000 0x1000>;
interrupts = <115>;
};
sata@122f0000 {
compatible = "snps,dwc-ahci";
samsung,sata-freq = <66>;
reg = <0x122f0000 0x1ff>;
interrupts = <0 115 0>;
clocks = <&clock 277>, <&clock 143>;
clock-names = "sata", "sclk_sata";
phys = <&sata_phy>;
phy-names = "sata-phy";
};

28
Documentation/devicetree/bindings/bus/imx-weim.txt
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@ -8,7 +8,12 @@ The actual devices are instantiated from the child nodes of a WEIM node.
Required properties:
- compatible: Should be set to "fsl,<soc>-weim"
- compatible: Should contain one of the following:
"fsl,imx1-weim"
"fsl,imx27-weim"
"fsl,imx51-weim"
"fsl,imx50-weim"
"fsl,imx6q-weim"
- reg: A resource specifier for the register space
(see the example below)
- clocks: the clock, see the example below.
@ -19,6 +24,26 @@ Required properties:
<cs-number> 0 <physical address of mapping> <size>
Optional properties:
- fsl,weim-cs-gpr: For "fsl,imx50-weim" and "fsl,imx6q-weim" type of
devices, it should be the phandle to the system General
Purpose Register controller that contains WEIM CS GPR
register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]
should be set up as one of the following 4 possible
values depending on the CS space configuration.
IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3
---------------------------------------------
05 128M 0M 0M 0M
033 64M 64M 0M 0M
0113 64M 32M 32M 0M
01111 32M 32M 32M 32M
In case that the property is absent, the reset value or
what bootloader sets up in IOMUXC_GPR1[11:0] will be
used.
Timing property for child nodes. It is mandatory, not optional.
- fsl,weim-cs-timing: The timing array, contains timing values for the
@ -43,6 +68,7 @@ Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x08000000 0x08000000>;
fsl,weim-cs-gpr = <&gpr>;
nor@0,0 {
compatible = "cfi-flash";

5
Documentation/devicetree/bindings/clock/altr_socfpga.txt
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@ -23,3 +23,8 @@ Optional properties:
and the bit index.
- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
and width.
- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
hold/delay times that is needed for the SD/MMC CIU clock. The values of both
can be 0-315 degrees, in 45 degree increments.

34
Documentation/devicetree/bindings/clock/arm-integrator.txt Normal file
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@ -0,0 +1,34 @@
Clock bindings for ARM Integrator Core Module clocks
Auxilary Oscillator Clock
This is a configurable clock fed from a 24 MHz chrystal,
used for generating e.g. video clocks. It is located on the
core module and there is only one of these.
This clock node *must* be a subnode of the core module, since
it obtains the base address for it's address range from its
parent node.
Required properties:
- compatible: must be "arm,integrator-cm-auxosc"
- #clock-cells: must be <0>
Optional properties:
- clocks: parent clock(s)
Example:
core-module@10000000 {
xtal24mhz: xtal24mhz@24M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
auxosc: cm_aux_osc@25M {
#clock-cells = <0>;
compatible = "arm,integrator-cm-auxosc";
clocks = <&xtal24mhz>;
};
};

2
Documentation/devicetree/bindings/clock/axi-clkgen.txt
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@ -5,7 +5,7 @@ This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be "adi,axi-clkgen".
- compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a".
- #clock-cells : from common clock binding; Should always be set to 0.
- reg : Address and length of the axi-clkgen register set.
- clocks : Phandle and clock specifier for the parent clock.

17
Documentation/devicetree/bindings/clock/clock-bindings.txt
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@ -44,6 +44,23 @@ For example:
clocks by index. The names should reflect the clock output signal
names for the device.
clock-indices: If the identifyng number for the clocks in the node
is not linear from zero, then the this mapping allows
the mapping of identifiers into the clock-output-names
array.
For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
oscillator {
compatible = "myclocktype";
#clock-cells = <1>;
clock-indices = <1>, <3>;
clock-output-names = "clka", "clkb";
}
This ensures we do not have any empty nodes in clock-output-names
==Clock consumers==
Required properties:

259
Documentation/devicetree/bindings/clock/exynos4-clock.txt
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@ -15,259 +15,12 @@ Required Properties:
- #clock-cells: should be 1.
The following is the list of clocks generated by the controller. Each clock is
assigned an identifier and client nodes use this identifier to specify the
clock which they consume. Some of the clocks are available only on a particular
Exynos4 SoC and this is specified where applicable.
[Core Clocks]
Clock ID SoC (if specific)
-----------------------------------------------
xxti 1
xusbxti 2
fin_pll 3
fout_apll 4
fout_mpll 5
fout_epll 6
fout_vpll 7
sclk_apll 8
sclk_mpll 9
sclk_epll 10
sclk_vpll 11
arm_clk 12
aclk200 13
aclk100 14
aclk160 15
aclk133 16
mout_mpll_user_t 17 Exynos4x12
mout_mpll_user_c 18 Exynos4x12
mout_core 19
mout_apll 20
[Clock Gate for Special Clocks]
Clock ID SoC (if specific)
-----------------------------------------------
sclk_fimc0 128
sclk_fimc1 129
sclk_fimc2 130
sclk_fimc3 131
sclk_cam0 132
sclk_cam1 133
sclk_csis0 134
sclk_csis1 135
sclk_hdmi 136
sclk_mixer 137
sclk_dac 138
sclk_pixel 139
sclk_fimd0 140
sclk_mdnie0 141 Exynos4412
sclk_mdnie_pwm0 12 142 Exynos4412
sclk_mipi0 143
sclk_audio0 144
sclk_mmc0 145
sclk_mmc1 146
sclk_mmc2 147
sclk_mmc3 148
sclk_mmc4 149
sclk_sata 150 Exynos4210
sclk_uart0 151
sclk_uart1 152
sclk_uart2 153
sclk_uart3 154
sclk_uart4 155
sclk_audio1 156
sclk_audio2 157
sclk_spdif 158
sclk_spi0 159
sclk_spi1 160
sclk_spi2 161
sclk_slimbus 162
sclk_fimd1 163 Exynos4210
sclk_mipi1 164 Exynos4210
sclk_pcm1 165
sclk_pcm2 166
sclk_i2s1 167
sclk_i2s2 168
sclk_mipihsi 169 Exynos4412
sclk_mfc 170
sclk_pcm0 171
sclk_g3d 172
sclk_pwm_isp 173 Exynos4x12
sclk_spi0_isp 174 Exynos4x12
sclk_spi1_isp 175 Exynos4x12
sclk_uart_isp 176 Exynos4x12
sclk_fimg2d 177
[Peripheral Clock Gates]
Clock ID SoC (if specific)
-----------------------------------------------
fimc0 256
fimc1 257
fimc2 258
fimc3 259
csis0 260
csis1 261
jpeg 262
smmu_fimc0 263
smmu_fimc1 264
smmu_fimc2 265
smmu_fimc3 266
smmu_jpeg 267
vp 268
mixer 269
tvenc 270 Exynos4210
hdmi 271
smmu_tv 272
mfc 273
smmu_mfcl 274
smmu_mfcr 275
g3d 276
g2d 277
rotator 278 Exynos4210
mdma 279 Exynos4210
smmu_g2d 280 Exynos4210
smmu_rotator 281 Exynos4210
smmu_mdma 282 Exynos4210
fimd0 283
mie0 284
mdnie0 285 Exynos4412
dsim0 286
smmu_fimd0 287
fimd1 288 Exynos4210
mie1 289 Exynos4210
dsim1 290 Exynos4210
smmu_fimd1 291 Exynos4210
pdma0 292
pdma1 293
pcie_phy 294
sata_phy 295 Exynos4210
tsi 296
sdmmc0 297
sdmmc1 298
sdmmc2 299
sdmmc3 300
sdmmc4 301
sata 302 Exynos4210
sromc 303
usb_host 304
usb_device 305
pcie 306
onenand 307
nfcon 308
smmu_pcie 309
gps 310
smmu_gps 311
uart0 312
uart1 313
uart2 314
uart3 315
uart4 316
i2c0 317
i2c1 318
i2c2 319
i2c3 320
i2c4 321
i2c5 322
i2c6 323
i2c7 324
i2c_hdmi 325
tsadc 326
spi0 327
spi1 328
spi2 329
i2s1 330
i2s2 331
pcm0 332
i2s0 333
pcm1 334
pcm2 335
pwm 336
slimbus 337
spdif 338
ac97 339
modemif 340
chipid 341
sysreg 342
hdmi_cec 343
mct 344
wdt 345
rtc 346
keyif 347
audss 348
mipi_hsi 349 Exynos4210
mdma2 350 Exynos4210
pixelasyncm0 351
pixelasyncm1 352
fimc_lite0 353 Exynos4x12
fimc_lite1 354 Exynos4x12
ppmuispx 355 Exynos4x12
ppmuispmx 356 Exynos4x12
fimc_isp 357 Exynos4x12
fimc_drc 358 Exynos4x12
fimc_fd 359 Exynos4x12
mcuisp 360 Exynos4x12
gicisp 361 Exynos4x12
smmu_isp 362 Exynos4x12
smmu_drc 363 Exynos4x12
smmu_fd 364 Exynos4x12
smmu_lite0 365 Exynos4x12
smmu_lite1 366 Exynos4x12
mcuctl_isp 367 Exynos4x12
mpwm_isp 368 Exynos4x12
i2c0_isp 369 Exynos4x12
i2c1_isp 370 Exynos4x12
mtcadc_isp 371 Exynos4x12
pwm_isp 372 Exynos4x12
wdt_isp 373 Exynos4x12
uart_isp 374 Exynos4x12
asyncaxim 375 Exynos4x12
smmu_ispcx 376 Exynos4x12
spi0_isp 377 Exynos4x12
spi1_isp 378 Exynos4x12
pwm_isp_sclk 379 Exynos4x12
spi0_isp_sclk 380 Exynos4x12
spi1_isp_sclk 381 Exynos4x12
uart_isp_sclk 382 Exynos4x12
tmu_apbif 383
[Mux Clocks]
Clock ID SoC (if specific)
-----------------------------------------------
mout_fimc0 384
mout_fimc1 385
mout_fimc2 386
mout_fimc3 387
mout_cam0 388
mout_cam1 389
mout_csis0 390
mout_csis1 391
mout_g3d0 392
mout_g3d1 393
mout_g3d 394
aclk400_mcuisp 395 Exynos4x12
[Div Clocks]
Clock ID SoC (if specific)
-----------------------------------------------
div_isp0 450 Exynos4x12
div_isp1 451 Exynos4x12
div_mcuisp0 452 Exynos4x12
div_mcuisp1 453 Exynos4x12
div_aclk200 454 Exynos4x12
div_aclk400_mcuisp 455 Exynos4x12
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos4.h header and can be used in device
tree sources.
Example 1: An example of a clock controller node is listed below.
@ -285,6 +38,6 @@ Example 2: UART controller node that consumes the clock generated by the clock
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>;
interrupts = <0 54 0>;
clocks = <&clock 314>, <&clock 153>;
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
};

163
Documentation/devicetree/bindings/clock/exynos5250-clock.txt
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@ -13,163 +13,12 @@ Required Properties:
- #clock-cells: should be 1.
The following is the list of clocks generated by the controller. Each clock is
assigned an identifier and client nodes use this identifier to specify the
clock which they consume.
[Core Clocks]
Clock ID
----------------------------
fin_pll 1
[Clock Gate for Special Clocks]
Clock ID
----------------------------
sclk_cam_bayer 128
sclk_cam0 129
sclk_cam1 130
sclk_gscl_wa 131
sclk_gscl_wb 132
sclk_fimd1 133
sclk_mipi1 134
sclk_dp 135
sclk_hdmi 136
sclk_pixel 137
sclk_audio0 138
sclk_mmc0 139
sclk_mmc1 140
sclk_mmc2 141
sclk_mmc3 142
sclk_sata 143
sclk_usb3 144
sclk_jpeg 145
sclk_uart0 146
sclk_uart1 147
sclk_uart2 148
sclk_uart3 149
sclk_pwm 150
sclk_audio1 151
sclk_audio2 152
sclk_spdif 153
sclk_spi0 154
sclk_spi1 155
sclk_spi2 156
div_i2s1 157
div_i2s2 158
sclk_hdmiphy 159
div_pcm0 160
[Peripheral Clock Gates]
Clock ID
----------------------------
gscl0 256
gscl1 257
gscl2 258
gscl3 259
gscl_wa 260
gscl_wb 261
smmu_gscl0 262
smmu_gscl1 263
smmu_gscl2 264
smmu_gscl3 265
mfc 266
smmu_mfcl 267
smmu_mfcr 268
rotator 269
jpeg 270
mdma1 271
smmu_rotator 272
smmu_jpeg 273
smmu_mdma1 274
pdma0 275
pdma1 276
sata 277
usbotg 278
mipi_hsi 279
sdmmc0 280
sdmmc1 281
sdmmc2 282
sdmmc3 283
sromc 284
usb2 285
usb3 286
sata_phyctrl 287
sata_phyi2c 288
uart0 289
uart1 290
uart2 291
uart3 292
uart4 293
i2c0 294
i2c1 295
i2c2 296
i2c3 297
i2c4 298
i2c5 299
i2c6 300
i2c7 301
i2c_hdmi 302
adc 303
spi0 304
spi1 305
spi2 306
i2s1 307
i2s2 308
pcm1 309
pcm2 310
pwm 311
spdif 312
ac97 313
hsi2c0 314
hsi2c1 315
hs12c2 316
hs12c3 317
chipid 318
sysreg 319
pmu 320
cmu_top 321
cmu_core 322
cmu_mem 323
tzpc0 324
tzpc1 325
tzpc2 326
tzpc3 327
tzpc4 328
tzpc5 329
tzpc6 330
tzpc7 331
tzpc8 332
tzpc9 333
hdmi_cec 334
mct 335
wdt 336
rtc 337
tmu 338
fimd1 339
mie1 340
dsim0 341
dp 342
mixer 343
hdmi 344
g2d 345
mdma0 346
smmu_mdma0 347
[Clock Muxes]
Clock ID
----------------------------
mout_hdmi 1024
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos5250.h header and can be used in device
tree sources.
Example 1: An example of a clock controller node is listed below.
@ -187,6 +36,6 @@ Example 2: UART controller node that consumes the clock generated by the clock
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>;
interrupts = <0 54 0>;
clocks = <&clock 314>, <&clock 153>;
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
};

184
Documentation/devicetree/bindings/clock/exynos5420-clock.txt
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@ -13,184 +13,12 @@ Required Properties:
- #clock-cells: should be 1.
The following is the list of clocks generated by the controller. Each clock is
assigned an identifier and client nodes use this identifier to specify the
clock which they consume.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume.
[Core Clocks]
Clock ID
----------------------------
fin_pll 1
[Clock Gate for Special Clocks]
Clock ID
----------------------------
sclk_uart0 128
sclk_uart1 129
sclk_uart2 130
sclk_uart3 131
sclk_mmc0 132
sclk_mmc1 133
sclk_mmc2 134
sclk_spi0 135
sclk_spi1 136
sclk_spi2 137
sclk_i2s1 138
sclk_i2s2 139
sclk_pcm1 140
sclk_pcm2 141
sclk_spdif 142
sclk_hdmi 143
sclk_pixel 144
sclk_dp1 145
sclk_mipi1 146
sclk_fimd1 147
sclk_maudio0 148
sclk_maupcm0 149
sclk_usbd300 150
sclk_usbd301 151
sclk_usbphy300 152
sclk_usbphy301 153
sclk_unipro 154
sclk_pwm 155
sclk_gscl_wa 156
sclk_gscl_wb 157
sclk_hdmiphy 158
[Peripheral Clock Gates]
Clock ID
----------------------------
aclk66_peric 256
uart0 257
uart1 258
uart2 259
uart3 260
i2c0 261
i2c1 262
i2c2 263
i2c3 264
i2c4 265
i2c5 266
i2c6 267
i2c7 268
i2c_hdmi 269
tsadc 270
spi0 271
spi1 272
spi2 273
keyif 274
i2s1 275
i2s2 276
pcm1 277
pcm2 278
pwm 279
spdif 280
i2c8 281
i2c9 282
i2c10 283
aclk66_psgen 300
chipid 301
sysreg 302
tzpc0 303
tzpc1 304
tzpc2 305
tzpc3 306
tzpc4 307
tzpc5 308
tzpc6 309
tzpc7 310
tzpc8 311
tzpc9 312
hdmi_cec 313
seckey 314
mct 315
wdt 316
rtc 317
tmu 318
tmu_gpu 319
pclk66_gpio 330
aclk200_fsys2 350
mmc0 351
mmc1 352
mmc2 353
sromc 354
ufs 355
aclk200_fsys 360
tsi 361
pdma0 362
pdma1 363
rtic 364
usbh20 365
usbd300 366
usbd301 377
aclk400_mscl 380
mscl0 381
mscl1 382
mscl2 383
smmu_mscl0 384
smmu_mscl1 385
smmu_mscl2 386
aclk333 400
mfc 401
smmu_mfcl 402
smmu_mfcr 403
aclk200_disp1 410
dsim1 411
dp1 412
hdmi 413
aclk300_disp1 420
fimd1 421
smmu_fimd1 422
aclk166 430
mixer 431
aclk266 440
rotator 441
mdma1 442
smmu_rotator 443
smmu_mdma1 444
aclk300_jpeg 450
jpeg 451
jpeg2 452
smmu_jpeg 453
aclk300_gscl 460
smmu_gscl0 461
smmu_gscl1 462
gscl_wa 463
gscl_wb 464
gscl0 465
gscl1 466
clk_3aa 467
aclk266_g2d 470
sss 471
slim_sss 472
mdma0 473
aclk333_g2d 480
g2d 481
aclk333_432_gscl 490
smmu_3aa 491
smmu_fimcl0 492
smmu_fimcl1 493
smmu_fimcl3 494
fimc_lite3 495
aclk_g3d 500
g3d 501
smmu_mixer 502
Mux ID
----------------------------
mout_hdmi 640
Divider ID
----------------------------
dout_pixel 768
All available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos5420.h header and can be used in device
tree sources.
Example 1: An example of a clock controller node is listed below.
@ -208,6 +36,6 @@ Example 2: UART controller node that consumes the clock generated by the clock
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>;
interrupts = <0 54 0>;
clocks = <&clock 259>, <&clock 130>;
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
};

43
Documentation/devicetree/bindings/clock/exynos5440-clock.txt
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@ -12,45 +12,12 @@ Required Properties:
- #clock-cells: should be 1.
The following is the list of clocks generated by the controller. Each clock is
assigned an identifier and client nodes use this identifier to specify the
clock which they consume.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume.
[Core Clocks]
Clock ID
----------------------------
xtal 1
arm_clk 2
[Peripheral Clock Gates]
Clock ID
----------------------------
spi_baud 16
pb0_250 17
pr0_250 18
pr1_250 19
b_250 20
b_125 21
b_200 22
sata 23
usb 24
gmac0 25
cs250 26
pb0_250_o 27
pr0_250_o 28
pr1_250_o 29
b_250_o 30
b_125_o 31
b_200_o 32
sata_o 33
usb_o 34
gmac0_o 35
cs250_o 36
All available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos5440.h header and can be used in device
tree sources.
Example: An example of a clock controller node is listed below.

1
Documentation/devicetree/bindings/clock/hi3620-clock.txt
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@ -7,6 +7,7 @@ Required Properties:
- compatible: should be one of the following.
- "hisilicon,hi3620-clock" - controller compatible with Hi3620 SoC.
- "hisilicon,hi3620-mmc-clock" - controller specific for Hi3620 mmc.
- reg: physical base address of the controller and length of memory mapped
region.

48
Documentation/devicetree/bindings/clock/moxa,moxart-clock.txt Normal file
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@ -0,0 +1,48 @@
Device Tree Clock bindings for arch-moxart
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
MOXA ART SoCs allow to determine PLL output and APB frequencies
by reading registers holding multiplier and divisor information.
PLL:
Required properties:
- compatible : Must be "moxa,moxart-pll-clock"
- #clock-cells : Should be 0
- reg : Should contain registers location and length
- clocks : Should contain phandle + clock-specifier for the parent clock
Optional properties:
- clock-output-names : Should contain clock name
APB:
Required properties:
- compatible : Must be "moxa,moxart-apb-clock"
- #clock-cells : Should be 0
- reg : Should contain registers location and length
- clocks : Should contain phandle + clock-specifier for the parent clock
Optional properties:
- clock-output-names : Should contain clock name
For example:
clk_pll: clk_pll@98100000 {
compatible = "moxa,moxart-pll-clock";
#clock-cells = <0>;
reg = <0x98100000 0x34>;
};
clk_apb: clk_apb@98100000 {
compatible = "moxa,moxart-apb-clock";
#clock-cells = <0>;
reg = <0x98100000 0x34>;
clocks = <&clk_pll>;
};

14
Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
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@ -11,6 +11,18 @@ The following is a list of provided IDs and clock names on Armada 370/XP:
3 = hclk (DRAM control clock)
4 = dramclk (DDR clock)
The following is a list of provided IDs and clock names on Armada 375:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU clock)
2 = l2clk (L2 Cache clock)
3 = ddrclk (DDR clock)
The following is a list of provided IDs and clock names on Armada 380/385:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU clock)
2 = l2clk (L2 Cache clock)
3 = ddrclk (DDR clock)
The following is a list of provided IDs and clock names on Kirkwood and Dove:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU0 clock)
@ -20,6 +32,8 @@ The following is a list of provided IDs and clock names on Kirkwood and Dove:
Required properties:
- compatible : shall be one of the following:
"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
"marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
"marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
"marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
"marvell,dove-core-clock" - for Dove SoC core clocks
"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)

5
Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
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@ -4,7 +4,10 @@ The following is a list of provided IDs and clock names on Armada 370/XP:
0 = nand (NAND clock)
Required properties:
- compatible : must be "marvell,armada-370-corediv-clock"
- compatible : must be "marvell,armada-370-corediv-clock",
"marvell,armada-375-corediv-clock",
"marvell,armada-380-corediv-clock",
- reg : must be the register address of Core Divider control register
- #clock-cells : from common clock binding; shall be set to 1
- clocks : must be set to the parent's phandle

65
Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
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@ -1,9 +1,10 @@
* Gated Clock bindings for Marvell EBU SoCs
Marvell Armada 370/XP, Dove and Kirkwood allow some peripheral clocks to be
gated to save some power. The clock consumer should specify the desired clock
by having the clock ID in its "clocks" phandle cell. The clock ID is directly
mapped to the corresponding clock gating control bit in HW to ease manual clock
Marvell Armada 370/375/380/385/XP, Dove and Kirkwood allow some
peripheral clocks to be gated to save some power. The clock consumer
should specify the desired clock by having the clock ID in its
"clocks" phandle cell. The clock ID is directly mapped to the
corresponding clock gating control bit in HW to ease manual clock
lookup in datasheet.
The following is a list of provided IDs for Armada 370:
@ -22,6 +23,60 @@ ID Clock Peripheral
28 ddr DDR Cntrl
30 sata1 SATA Host 0
The following is a list of provided IDs for Armada 375:
ID Clock Peripheral
-----------------------------------
2 mu Management Unit
3 pp Packet Processor
4 ptp PTP
5 pex0 PCIe 0 Clock out
6 pex1 PCIe 1 Clock out
8 audio Audio Cntrl
11 nd_clk Nand Flash Cntrl
14 sata0_link SATA 0 Link
15 sata0_core SATA 0 Core
16 usb3 USB3 Host
17 sdio SDHCI Host
18 usb USB Host
19 gop Gigabit Ethernet MAC
20 sata1_link SATA 1 Link
21 sata1_core SATA 1 Core
22 xor0 XOR DMA 0
23 xor1 XOR DMA 0
24 copro Coprocessor
25 tdm Time Division Mplx
28 crypto0_enc Cryptographic Unit Port 0 Encryption
29 crypto0_core Cryptographic Unit Port 0 Core
30 crypto1_enc Cryptographic Unit Port 1 Encryption
31 crypto1_core Cryptographic Unit Port 1 Core
The following is a list of provided IDs for Armada 380/385:
ID Clock Peripheral
-----------------------------------
0 audio Audio
2 ge2 Gigabit Ethernet 2
3 ge1 Gigabit Ethernet 1
4 ge0 Gigabit Ethernet 0
5 pex1 PCIe 1
6 pex2 PCIe 2
7 pex3 PCIe 3
8 pex0 PCIe 0
9 usb3h0 USB3 Host 0
10 usb3h1 USB3 Host 1
11 usb3d USB3 Device
13 bm Buffer Management
14 crypto0z Cryptographic 0 Z
15 sata0 SATA 0
16 crypto1z Cryptographic 1 Z
17 sdio SDIO
18 usb2 USB 2
21 crypto1 Cryptographic 1
22 xor0 XOR 0
23 crypto0 Cryptographic 0
25 tdm Time Division Multiplexing
28 xor1 XOR 1
30 sata1 SATA 1
The following is a list of provided IDs for Armada XP:
ID Clock Peripheral
-----------------------------------
@ -95,6 +150,8 @@ ID Clock Peripheral
Required properties:
- compatible : shall be one of the following:
"marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
"marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
"marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
"marvell,dove-gating-clock" - for Dove SoC clock gating
"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating

4
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
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@ -21,9 +21,9 @@ Required Properties:
must appear in the same order as the output clocks.
- #clock-cells: Must be 1
- clock-output-names: The name of the clocks as free-form strings
- renesas,indices: Indices of the gate clocks into the group (0 to 31)
- renesas,clock-indices: Indices of the gate clocks into the group (0 to 31)
The clocks, clock-output-names and renesas,indices properties contain one
The clocks, clock-output-names and renesas,clock-indices properties contain one
entry per gate clock. The MSTP groups are sparsely populated. Unimplemented
gate clocks must not be declared.

29
Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt Normal file
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@ -0,0 +1,29 @@
* Renesas RZ Clock Pulse Generator (CPG)
The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
CPU and GPU clocks, and several fixed ratio dividers.
Required Properties:
- compatible: Must be one of
- "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG
- "renesas,rz-cpg-clocks" for the generic RZ CPG
- reg: Base address and length of the memory resource used by the CPG
- clocks: References to possible parent clocks. Order must match clock modes
in the datasheet. For the r7s72100, this is extal, usb_x1.
- #clock-cells: Must be 1
- clock-output-names: The names of the clocks. Supported clocks are "pll",
"i", and "g"
Example
-------
cpg_clocks: cpg_clocks@fcfe0000 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-cpg-clocks",
"renesas,rz-cpg-clocks";
reg = <0xfcfe0000 0x18>;
clocks = <&extal_clk>, <&usb_x1_clk>;
clock-output-names = "pll", "i", "g";
};

49
Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt Normal file
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@ -0,0 +1,49 @@
Binding for a ST divider and multiplexer clock driver.
This binding uses the common clock binding[1].
Base address is located to the parent node. See clock binding[2]
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
Required properties:
- compatible : shall be:
"st,clkgena-divmux-c65-hs", "st,clkgena-divmux"
"st,clkgena-divmux-c65-ls", "st,clkgena-divmux"
"st,clkgena-divmux-c32-odf0", "st,clkgena-divmux"
"st,clkgena-divmux-c32-odf1", "st,clkgena-divmux"
"st,clkgena-divmux-c32-odf2", "st,clkgena-divmux"
"st,clkgena-divmux-c32-odf3", "st,clkgena-divmux"
- #clock-cells : From common clock binding; shall be set to 1.
- clocks : From common clock binding
- clock-output-names : From common clock binding.
Example:
clockgenA@fd345000 {
reg = <0xfd345000 0xb50>;
CLK_M_A1_DIV1: CLK_M_A1_DIV1 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf1",
"st,clkgena-divmux";
clocks = <&CLK_M_A1_OSC_PREDIV>,
<&CLK_M_A1_PLL0 1>, /* PLL0 PHI1 */
<&CLK_M_A1_PLL1 1>; /* PLL1 PHI1 */
clock-output-names = "CLK_M_RX_ICN_TS",
"CLK_M_RX_ICN_VDP_0",
"", /* Unused */
"CLK_M_PRV_T1_BUS",
"CLK_M_ICN_REG_12",
"CLK_M_ICN_REG_10",
"", /* Unused */
"CLK_M_ICN_ST231";
};
};

36
Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt Normal file
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@ -0,0 +1,36 @@
Binding for a ST multiplexed clock driver.
This binding supports only simple indexed multiplexers, it does not
support table based parent index to hardware value translations.
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be:
"st,stih416-clkgenc-vcc-hd", "st,clkgen-mux"
"st,stih416-clkgenf-vcc-fvdp", "st,clkgen-mux"
"st,stih416-clkgenf-vcc-hva", "st,clkgen-mux"
"st,stih416-clkgenf-vcc-hd", "st,clkgen-mux"
"st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"
"st,stih415-clkgen-a9-mux", "st,clkgen-mux"
"st,stih416-clkgen-a9-mux", "st,clkgen-mux"
- #clock-cells : from common clock binding; shall be set to 0.
- reg : A Base address and length of the register set.
- clocks : from common clock binding
Example:
CLK_M_HVA: CLK_M_HVA {
#clock-cells = <0>;
compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
reg = <0xfd690868 4>;
clocks = <&CLOCKGEN_F 1>, <&CLK_M_A1_DIV0 3>;
};

48
Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt Normal file
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@ -0,0 +1,48 @@
Binding for a ST pll clock driver.
This binding uses the common clock binding[1].
Base address is located to the parent node. See clock binding[2]
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
Required properties:
- compatible : shall be:
"st,clkgena-prediv-c65", "st,clkgena-prediv"
"st,clkgena-prediv-c32", "st,clkgena-prediv"
"st,clkgena-plls-c65"
"st,plls-c32-a1x-0", "st,clkgen-plls-c32"
"st,plls-c32-a1x-1", "st,clkgen-plls-c32"
"st,stih415-plls-c32-a9", "st,clkgen-plls-c32"
"st,stih415-plls-c32-ddr", "st,clkgen-plls-c32"
"st,stih416-plls-c32-a9", "st,clkgen-plls-c32"
"st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
- #clock-cells : From common clock binding; shall be set to 1.
- clocks : From common clock binding
- clock-output-names : From common clock binding.
Example:
clockgenA@fee62000 {
reg = <0xfee62000 0xb48>;
CLK_S_A0_PLL: CLK_S_A0_PLL {
#clock-cells = <1>;
compatible = "st,clkgena-plls-c65";
clocks = <&CLK_SYSIN>;
clock-output-names = "CLK_S_A0_PLL0_HS",
"CLK_S_A0_PLL0_LS",
"CLK_S_A0_PLL1";
};
};

36
Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt Normal file
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@ -0,0 +1,36 @@
Binding for a ST pre-divider clock driver.
This binding uses the common clock binding[1].
Base address is located to the parent node. See clock binding[2]
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
Required properties:
- compatible : shall be:
"st,clkgena-prediv-c65", "st,clkgena-prediv"
"st,clkgena-prediv-c32", "st,clkgena-prediv"
- #clock-cells : From common clock binding; shall be set to 0.
- clocks : From common clock binding
- clock-output-names : From common clock binding.
Example:
clockgenA@fd345000 {
reg = <0xfd345000 0xb50>;
CLK_M_A2_OSC_PREDIV: CLK_M_A2_OSC_PREDIV {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c32",
"st,clkgena-prediv";
clocks = <&CLK_SYSIN>;
clock-output-names = "CLK_M_A2_OSC_PREDIV";
};
};

53
Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt Normal file
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@ -0,0 +1,53 @@
Binding for a type of STMicroelectronics clock crossbar (VCC).
The crossbar can take up to 4 input clocks and control up to 16
output clocks. Not all inputs or outputs have to be in use in a
particular instantiation. Each output can be individually enabled,
select any of the input clocks and apply a divide (by 1,2,4 or 8) to
that selected clock.
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be:
"st,stih416-clkgenc", "st,vcc"
"st,stih416-clkgenf", "st,vcc"
- #clock-cells : from common clock binding; shall be set to 1.
- reg : A Base address and length of the register set.
- clocks : from common clock binding
- clock-output-names : From common clock binding. The block has 16
clock outputs but not all of them in a specific instance
have to be used in the SoC. If a clock name is left as
an empty string then no clock will be created for the
output associated with that string index. If fewer than
16 strings are provided then no clocks will be created
for the remaining outputs.
Example:
CLOCKGEN_C_VCC: CLOCKGEN_C_VCC {
#clock-cells = <1>;
compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
reg = <0xfe8308ac 12>;
clocks = <&CLK_S_VCC_HD>, <&CLOCKGEN_C 1>,
<&CLK_S_TMDS_FROMPHY>, <&CLOCKGEN_C 2>;
clock-output-names =
"CLK_S_PIX_HDMI", "CLK_S_PIX_DVO",
"CLK_S_OUT_DVO", "CLK_S_PIX_HD",
"CLK_S_HDDAC", "CLK_S_DENC",
"CLK_S_SDDAC", "CLK_S_PIX_MAIN",
"CLK_S_PIX_AUX", "CLK_S_STFE_FRC_0",
"CLK_S_REF_MCRU", "CLK_S_SLAVE_MCRU",
"CLK_S_TMDS_HDMI", "CLK_S_HDMI_REJECT_PLL",
"CLK_S_THSENS";
};

83
Documentation/devicetree/bindings/clock/st/st,clkgen.txt Normal file
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@ -0,0 +1,83 @@
Binding for a Clockgen hardware block found on
certain STMicroelectronics consumer electronics SoC devices.
A Clockgen node can contain pll, diviser or multiplexer nodes.
We will find only the base address of the Clockgen, this base
address is common of all subnode.
clockgen_node {
reg = <>;
pll_node {
...
};
prediv_node {
...
};
divmux_node {
...
};
quadfs_node {
...
};
...
};
This binding uses the common clock binding[1].
Each subnode should use the binding discribe in [2]..[4]
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/st,quadfs.txt
[3] Documentation/devicetree/bindings/clock/st,quadfs.txt
[4] Documentation/devicetree/bindings/clock/st,quadfs.txt
Required properties:
- reg : A Base address and length of the register set.
Example:
clockgenA@fee62000 {
reg = <0xfee62000 0xb48>;
CLK_S_A0_PLL: CLK_S_A0_PLL {
#clock-cells = <1>;
compatible = "st,clkgena-plls-c65";
clocks = <&CLK_SYSIN>;
clock-output-names = "CLK_S_A0_PLL0_HS",
"CLK_S_A0_PLL0_LS",
"CLK_S_A0_PLL1";
};
CLK_S_A0_OSC_PREDIV: CLK_S_A0_OSC_PREDIV {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c65",
"st,clkgena-prediv";
clocks = <&CLK_SYSIN>;
clock-output-names = "CLK_S_A0_OSC_PREDIV";
};
CLK_S_A0_HS: CLK_S_A0_HS {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c65-hs",
"st,clkgena-divmux";
clocks = <&CLK_S_A0_OSC_PREDIV>,
<&CLK_S_A0_PLL 0>, /* PLL0 HS */
<&CLK_S_A0_PLL 2>; /* PLL1 */
clock-output-names = "CLK_S_FDMA_0",
"CLK_S_FDMA_1",
""; /* CLK_S_JIT_SENSE */
/* Fourth output unused */
};
};

45
Documentation/devicetree/bindings/clock/st/st,quadfs.txt Normal file
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@ -0,0 +1,45 @@
Binding for a type of quad channel digital frequency synthesizer found on
certain STMicroelectronics consumer electronics SoC devices.
This version contains a programmable PLL which can generate up to 216, 432
or 660MHz (from a 30MHz oscillator input) as the input to the digital
synthesizers.
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be:
"st,stih416-quadfs216", "st,quadfs"
"st,stih416-quadfs432", "st,quadfs"
"st,stih416-quadfs660-E", "st,quadfs"
"st,stih416-quadfs660-F", "st,quadfs"
- #clock-cells : from common clock binding; shall be set to 1.
- reg : A Base address and length of the register set.
- clocks : from common clock binding
- clock-output-names : From common clock binding. The block has 4
clock outputs but not all of them in a specific instance
have to be used in the SoC. If a clock name is left as
an empty string then no clock will be created for the
output associated with that string index. If fewer than
4 strings are provided then no clocks will be created
for the remaining outputs.
Example:
CLOCKGEN_E: CLOCKGEN_E {
#clock-cells = <1>;
compatible = "st,stih416-quadfs660-E", "st,quadfs";
reg = <0xfd3208bc 0xB0>;
clocks = <&CLK_SYSIN>;
clock-output-names = "CLK_M_PIX_MDTP_0",
"CLK_M_PIX_MDTP_1",
"CLK_M_PIX_MDTP_2",
"CLK_M_MPELPC";
};

102
Documentation/devicetree/bindings/clock/sunxi.txt
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@ -6,37 +6,41 @@ This binding uses the common clock binding[1].
Required properties:
- compatible : shall be one of the following:
"allwinner,sun4i-osc-clk" - for a gatable oscillator
"allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4
"allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
"allwinner,sun4i-pll5-clk" - for the PLL5 clock
"allwinner,sun4i-pll6-clk" - for the PLL6 clock
"allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
"allwinner,sun4i-axi-clk" - for the AXI clock
"allwinner,sun4i-axi-gates-clk" - for the AXI gates
"allwinner,sun4i-ahb-clk" - for the AHB clock
"allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
"allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
"allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
"allwinner,sun4i-a10-axi-clk" - for the AXI clock
"allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
"allwinner,sun4i-a10-ahb-clk" - for the AHB clock
"allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
"allwinner,sun4i-apb0-clk" - for the APB0 clock
"allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
"allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
"allwinner,sun4i-apb1-clk" - for the APB1 clock
"allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
"allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
"allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
"allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
"allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
"allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
"allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
"allwinner,sun7i-a20-out-clk" - for the external output clocks
"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
Required properties for all clocks:
- reg : shall be the control register address for the clock.
@ -44,10 +48,17 @@ Required properties for all clocks:
multiplexed clocks, the list order must match the hardware
programming order.
- #clock-cells : from common clock binding; shall be set to 0 except for
"allwinner,*-gates-clk" where it shall be set to 1
"allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and
"allwinner,sun4i-pll6-clk" where it shall be set to 1
- clock-output-names : shall be the corresponding names of the outputs.
If the clock module only has one output, the name shall be the
module name.
Additionally, "allwinner,*-gates-clk" clocks require:
- clock-output-names : the corresponding gate names that the clock controls
And "allwinner,*-usb-clk" clocks also require:
- reset-cells : shall be set to 1
For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
dummy clocks at 25 MHz and 125 MHz, respectively. See example.
Clock consumers should specify the desired clocks they use with a
"clocks" phandle cell. Consumers that are using a gated clock should
@ -56,23 +67,68 @@ offset of the bit controlling this particular gate in the register.
For example:
osc24M: osc24M@01c20050 {
osc24M: clk@01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-osc-clk";
compatible = "allwinner,sun4i-a10-osc-clk";
reg = <0x01c20050 0x4>;
clocks = <&osc24M_fixed>;
clock-output-names = "osc24M";
};
pll1: pll1@01c20000 {
pll1: clk@01c20000 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-pll1-clk";
compatible = "allwinner,sun4i-a10-pll1-clk";
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll1";
};
pll5: clk@01c20020 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-pll5-clk";
reg = <0x01c20020 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll5_ddr", "pll5_other";
};
cpu: cpu@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-cpu-clk";
compatible = "allwinner,sun4i-a10-cpu-clk";
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll1>;
clock-output-names = "cpu";
};
mmc0_clk: clk@01c20088 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
reg = <0x01c20088 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc0";
};
mii_phy_tx_clk: clk@2 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
clock-output-names = "mii_phy_tx";
};
gmac_int_tx_clk: clk@3 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac_int_tx";
};
gmac_clk: clk@01c20164 {
#clock-cells = <0>;
compatible = "allwinner,sun7i-a20-gmac-clk";
reg = <0x01c20164 0x4>;
/*
* The first clock must be fixed at 25MHz;
* the second clock must be fixed at 125MHz
*/
clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
clock-output-names = "gmac";
};

4
Documentation/devicetree/bindings/clock/zynq-7000.txt
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@ -14,6 +14,7 @@ for all clock consumers of PS clocks.
Required properties:
- #clock-cells : Must be 1
- compatible : "xlnx,ps7-clkc"
- reg : SLCR offset and size taken via syscon < 0x100 0x100 >
- ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
(usually 33 MHz oscillators are used for Zynq platforms)
- clock-output-names : List of strings used to name the clock outputs. Shall be
@ -87,10 +88,11 @@ Clock outputs:
47: dbg_apb
Example:
clkc: clkc {
clkc: clkc@100 {
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
ps-clk-frequency = <33333333>;
reg = <0x100 0x100>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
"dci", "lqspi", "smc", "pcap", "gem0", "gem1",

76
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@ -0,0 +1,76 @@
* Freescale enhanced Direct Memory Access(eDMA) Controller
The eDMA channels have multiplex capability by programmble memory-mapped
registers. channels are split into two groups, called DMAMUX0 and DMAMUX1,
specific DMA request source can only be multiplexed by any channel of certain
group, DMAMUX0 or DMAMUX1, but not both.
* eDMA Controller
Required properties:
- compatible :
- "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC
- reg : Specifies base physical address(s) and size of the eDMA registers.
The 1st region is eDMA control register's address and size.
The 2nd and the 3rd regions are programmable channel multiplexing
control register's address and size.
- interrupts : A list of interrupt-specifiers, one for each entry in
interrupt-names.
- interrupt-names : Should contain:
"edma-tx" - the transmission interrupt
"edma-err" - the error interrupt
- #dma-cells : Must be <2>.
The 1st cell specifies the DMAMUX(0 for DMAMUX0 and 1 for DMAMUX1).
Specific request source can only be multiplexed by specific channels
group called DMAMUX.
The 2nd cell specifies the request source(slot) ID.
See the SoC's reference manual for all the supported request sources.
- dma-channels : Number of channels supported by the controller
- clock-names : A list of channel group clock names. Should contain:
"dmamux0" - clock name of mux0 group
"dmamux1" - clock name of mux1 group
- clocks : A list of phandle and clock-specifier pairs, one for each entry in
clock-names.
Optional properties:
- big-endian: If present registers and hardware scatter/gather descriptors
of the eDMA are implemented in big endian mode, otherwise in little
mode.
Examples:
edma0: dma-controller@40018000 {
#dma-cells = <2>;
compatible = "fsl,vf610-edma";
reg = <0x40018000 0x2000>,
<0x40024000 0x1000>,
<0x40025000 0x1000>;
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
<0 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma-tx", "edma-err";
dma-channels = <32>;
clock-names = "dmamux0", "dmamux1";
clocks = <&clks VF610_CLK_DMAMUX0>,
<&clks VF610_CLK_DMAMUX1>;
};
* DMA clients
DMA client drivers that uses the DMA function must use the format described
in the dma.txt file, using a two-cell specifier for each channel: the 1st
specifies the channel group(DMAMUX) in which this request can be multiplexed,
and the 2nd specifies the request source.
Examples:
sai2: sai@40031000 {
compatible = "fsl,vf610-sai";
reg = <0x40031000 0x1000>;
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sai";
clocks = <&clks VF610_CLK_SAI2>;
dma-names = "tx", "rx";
dmas = <&edma0 0 21>,
<&edma0 0 20>;
status = "disabled";
};

41
Documentation/devicetree/bindings/dma/qcom_bam_dma.txt Normal file
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@ -0,0 +1,41 @@
QCOM BAM DMA controller
Required properties:
- compatible: must contain "qcom,bam-v1.4.0" for MSM8974
- reg: Address range for DMA registers
- interrupts: Should contain the one interrupt shared by all channels
- #dma-cells: must be <1>, the cell in the dmas property of the client device
represents the channel number
- clocks: required clock
- clock-names: must contain "bam_clk" entry
- qcom,ee : indicates the active Execution Environment identifier (0-7) used in
the secure world.
Example:
uart-bam: dma@f9984000 = {
compatible = "qcom,bam-v1.4.0";
reg = <0xf9984000 0x15000>;
interrupts = <0 94 0>;
clocks = <&gcc GCC_BAM_DMA_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
};
DMA clients must use the format described in the dma.txt file, using a two cell
specifier for each channel.
Example:
serial@f991e000 {
compatible = "qcom,msm-uart";
reg = <0xf991e000 0x1000>
<0xf9944000 0x19000>;
interrupts = <0 108 0>;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&uart-bam 0>, <&uart-bam 1>;
dma-names = "rx", "tx";
};

43
Documentation/devicetree/bindings/dma/sirfsoc-dma.txt Normal file
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@ -0,0 +1,43 @@
* CSR SiRFSoC DMA controller
See dma.txt first
Required properties:
- compatible: Should be "sirf,prima2-dmac" or "sirf,marco-dmac"
- reg: Should contain DMA registers location and length.
- interrupts: Should contain one interrupt shared by all channel
- #dma-cells: must be <1>. used to represent the number of integer
cells in the dmas property of client device.
- clocks: clock required
Example:
Controller:
dmac0: dma-controller@b00b0000 {
compatible = "sirf,prima2-dmac";
reg = <0xb00b0000 0x10000>;
interrupts = <12>;
clocks = <&clks 24>;
#dma-cells = <1>;
};
Client:
Fill the specific dma request line in dmas. In the below example, spi0 read
channel request line is 9 of the 2nd dma controller, while write channel uses
4 of the 2nd dma controller; spi1 read channel request line is 12 of the 1st
dma controller, while write channel uses 13 of the 1st dma controller:
spi0: spi@b00d0000 {
compatible = "sirf,prima2-spi";
dmas = <&dmac1 9>,
<&dmac1 4>;
dma-names = "rx", "tx";
};
spi1: spi@b0170000 {
compatible = "sirf,prima2-spi";
dmas = <&dmac0 12>,
<&dmac0 13>;
dma-names = "rx", "tx";
};

27
Documentation/devicetree/bindings/drm/bridge/ptn3460.txt Normal file
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@ -0,0 +1,27 @@
ptn3460 bridge bindings
Required properties:
- compatible: "nxp,ptn3460"
- reg: i2c address of the bridge
- powerdown-gpio: OF device-tree gpio specification
- reset-gpio: OF device-tree gpio specification
- edid-emulation: The EDID emulation entry to use
+-------+------------+------------------+
| Value | Resolution | Description |
| 0 | 1024x768 | NXP Generic |
| 1 | 1920x1080 | NXP Generic |
| 2 | 1920x1080 | NXP Generic |
| 3 | 1600x900 | Samsung LTM200KT |
| 4 | 1920x1080 | Samsung LTM230HT |
| 5 | 1366x768 | NXP Generic |
| 6 | 1600x900 | ChiMei M215HGE |
+-------+------------+------------------+
Example:
lvds-bridge@20 {
compatible = "nxp,ptn3460";
reg = <0x20>;
powerdown-gpio = <&gpy2 5 1 0 0>;
reset-gpio = <&gpx1 5 1 0 0>;
edid-emulation = <5>;
};

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