drm/msm/a6xx: Add a helper for software-resetting the GPU
Introduce a6xx_gpu_sw_reset() in preparation for adding GMU wrapper GPUs and reuse it in a6xx_gmu_force_off(). This helper, contrary to the original usage in GMU code paths, adds a readback+delay sequence to ensure that the reset is never deasserted too quickly due to e.g. OoO execution going crazy. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/542758/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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@ -899,8 +899,7 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
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a6xx_bus_clear_pending_transactions(adreno_gpu, true);
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/* Reset GPU core blocks */
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gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, 1);
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udelay(100);
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a6xx_gpu_sw_reset(gpu, true);
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}
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static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
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@ -1742,6 +1742,18 @@ void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_
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gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
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}
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void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert)
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{
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gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, assert);
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/* Perform a bogus read and add a brief delay to ensure ordering. */
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gpu_read(gpu, REG_A6XX_RBBM_SW_RESET_CMD);
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udelay(1);
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/* The reset line needs to be asserted for at least 100 us */
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if (assert)
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udelay(100);
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}
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static int a6xx_pm_resume(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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@ -89,5 +89,6 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu);
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int a6xx_gpu_state_put(struct msm_gpu_state *state);
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void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off);
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void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert);
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#endif /* __A6XX_GPU_H__ */
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