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drm/amd/display: fix input states translation error for dcn35 & dcn351

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[Why]
Currently there is an error while translating input clock sates into
output clock states. The highest fclk setting from output sates is
being dropped because of this error.

[How]
For dcn35 and dcn351, make output_states equal to input states.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Swapnil Patel <swapnil.patel@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Swapnil Patel 2024-02-06 11:40:20 -05:00 committed by Alex Deucher
parent d2b48f340d
commit 27a6c49394
1 changed files with 8 additions and 1 deletions
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9
drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
View File

@ -398,7 +398,6 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,
/* Copy clocks tables entries, if available */
if (dml2->config.bbox_overrides.clks_table.num_states) {
p->in_states->num_states = dml2->config.bbox_overrides.clks_table.num_states;
for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels; i++) {
p->in_states->state_array[i].dcfclk_mhz = dml2->config.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz;
}
@ -437,6 +436,14 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,
}
dml2_policy_build_synthetic_soc_states(s, p);
if (dml2->v20.dml_core_ctx.project == dml_project_dcn35 ||
dml2->v20.dml_core_ctx.project == dml_project_dcn351) {
// Override last out_state with data from last in_state
// This will ensure that out_state contains max fclk
memcpy(&p->out_states->state_array[p->out_states->num_states - 1],
&p->in_states->state_array[p->in_states->num_states - 1],
sizeof(struct soc_state_bounding_box_st));
}
}
void dml2_translate_ip_params(const struct dc *in, struct ip_params_st *out)