ARM: Orion: PCIE: Add support for clk
Prepare and enable the clocks when the board indicates the pcie buses will be used. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jamie Lentin <jm@lentin.co.uk> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -87,7 +87,7 @@ static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx)
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void __init kirkwood_clk_init(void)
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{
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struct clk *runit, *ge0, *ge1, *sata0, *sata1, *usb0, *sdio;
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struct clk *crypto, *xor0, *xor1;
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struct clk *crypto, *xor0, *xor1, *pex0, *pex1;
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tclk = clk_register_fixed_rate(NULL, "tclk", NULL,
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CLK_IS_ROOT, kirkwood_tclk);
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@ -102,8 +102,8 @@ void __init kirkwood_clk_init(void)
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crypto = kirkwood_register_gate("crypto", CGC_BIT_CRYPTO);
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xor0 = kirkwood_register_gate("xor0", CGC_BIT_XOR0);
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xor1 = kirkwood_register_gate("xor1", CGC_BIT_XOR1);
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kirkwood_register_gate("pex0", CGC_BIT_PEX0);
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kirkwood_register_gate("pex1", CGC_BIT_PEX1);
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pex0 = kirkwood_register_gate("pex0", CGC_BIT_PEX0);
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pex1 = kirkwood_register_gate("pex1", CGC_BIT_PEX1);
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kirkwood_register_gate("audio", CGC_BIT_AUDIO);
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kirkwood_register_gate("tdm", CGC_BIT_TDM);
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kirkwood_register_gate("tsu", CGC_BIT_TSU);
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@ -122,6 +122,8 @@ void __init kirkwood_clk_init(void)
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orion_clkdev_add(NULL, "mv_crypto", crypto);
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orion_clkdev_add(NULL, MV_XOR_SHARED_NAME ".0", xor0);
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orion_clkdev_add(NULL, MV_XOR_SHARED_NAME ".1", xor1);
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orion_clkdev_add("0", "pcie", pex0);
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orion_clkdev_add("1", "pcie", pex1);
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}
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/*****************************************************************************
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@ -11,6 +11,7 @@
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <video/vga.h>
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#include <asm/irq.h>
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#include <asm/mach/pci.h>
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@ -19,6 +20,23 @@
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#include <plat/addr-map.h>
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#include "common.h"
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static void kirkwood_enable_pcie_clk(const char *port)
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{
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struct clk *clk;
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clk = clk_get_sys("pcie", port);
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if (IS_ERR(clk)) {
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printk(KERN_ERR "PCIE clock %s missing\n", port);
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return;
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}
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clk_prepare_enable(clk);
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clk_put(clk);
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}
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/* This function is called very early in the boot when probing the
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hardware to determine what we actually are, and what rate tclk is
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ticking at. Hence calling kirkwood_enable_pcie_clk() is not
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possible since the clk tree has not been created yet. */
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void kirkwood_enable_pcie(void)
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{
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u32 curr = readl(CLOCK_GATING_CTRL);
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@ -183,10 +201,12 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
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switch (index) {
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case 0:
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kirkwood_clk_ctrl |= CGC_PEX0;
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kirkwood_enable_pcie_clk("0");
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pcie0_ioresources_init(pp);
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break;
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case 1:
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kirkwood_clk_ctrl |= CGC_PEX1;
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kirkwood_enable_pcie_clk("1");
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pcie1_ioresources_init(pp);
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break;
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default:
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