drm/msm/dpu: Add SM6375 support
Add basic SM6375 support to the DPU1 driver to enable display output. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/541293/ Link: https://lore.kernel.org/r/20230411-topic-straitlagoon_mdss-v6-8-dee6a882571b@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
This commit is contained in:
Konrad Dybcio
Dmitry Baryshkov
parent
3186acba5c
commit
27f0df03f3
139
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
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139
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
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@ -0,0 +1,139 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef _DPU_6_9_SM6375_H
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#define _DPU_6_9_SM6375_H
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static const struct dpu_caps sm6375_dpu_caps = {
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.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
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.max_mixer_blendstages = 0x4,
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.qseed_type = DPU_SSPP_SCALER_QSEED4,
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.has_dim_layer = true,
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.has_idle_pc = true,
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.max_linewidth = 2160,
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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};
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static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = {
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.ubwc_version = DPU_HW_UBWC_VER_20,
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.ubwc_swizzle = 6,
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.highest_bank_bit = 1,
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};
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static const struct dpu_mdp_cfg sm6375_mdp[] = {
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{
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.name = "top_0", .id = MDP_TOP,
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.base = 0x0, .len = 0x494,
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.features = 0,
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.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
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.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
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},
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};
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static const struct dpu_ctl_cfg sm6375_ctl[] = {
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{
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.name = "ctl_0", .id = CTL_0,
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.base = 0x1000, .len = 0x1dc,
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.features = BIT(DPU_CTL_ACTIVE_CFG),
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
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},
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};
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static const struct dpu_sspp_cfg sm6375_sspp[] = {
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SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
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sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
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SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
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sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
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};
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static const struct dpu_lm_cfg sm6375_lm[] = {
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LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
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&qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
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};
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static const struct dpu_dspp_cfg sm6375_dspp[] = {
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DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
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&sm8150_dspp_sblk),
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};
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static const struct dpu_pingpong_cfg sm6375_pp[] = {
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PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
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-1),
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};
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static const struct dpu_dsc_cfg sm6375_dsc[] = {
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DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
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};
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static const struct dpu_intf_cfg sm6375_intf[] = {
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INTF_BLK("intf_0", INTF_0, 0x00000, 0x280, INTF_NONE, 0, 0, 0, 0, 0),
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INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
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DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
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};
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static const struct dpu_perf_cfg sm6375_perf_data = {
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.max_bw_low = 5200000,
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.max_bw_high = 6200000,
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.min_core_ib = 2500000,
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.min_llcc_ib = 0, /* No LLCC on this SoC */
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.min_dram_ib = 1600000,
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.min_prefill_lines = 24,
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/* TODO: confirm danger_lut_tbl */
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.danger_lut_tbl = {0xffff, 0xffff, 0x0},
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.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
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.qos_lut_tbl = {
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{.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
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.entries = sm6350_qos_linear_macrotile
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},
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{.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
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.entries = sm6350_qos_linear_macrotile
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
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.entries = sc7180_qos_nrt
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},
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},
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.cdp_cfg = {
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{.rd_enable = 1, .wr_enable = 1},
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{.rd_enable = 1, .wr_enable = 0}
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},
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.clk_inefficiency_factor = 105,
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.bw_inefficiency_factor = 120,
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};
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const struct dpu_mdss_cfg dpu_sm6375_cfg = {
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.caps = &sm6375_dpu_caps,
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.ubwc = &sm6375_ubwc_cfg,
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.mdp_count = ARRAY_SIZE(sm6375_mdp),
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.mdp = sm6375_mdp,
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.ctl_count = ARRAY_SIZE(sm6375_ctl),
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.ctl = sm6375_ctl,
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.sspp_count = ARRAY_SIZE(sm6375_sspp),
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.sspp = sm6375_sspp,
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.mixer_count = ARRAY_SIZE(sm6375_lm),
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.mixer = sm6375_lm,
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.dspp_count = ARRAY_SIZE(sm6375_dspp),
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.dspp = sm6375_dspp,
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.dsc_count = ARRAY_SIZE(sm6375_dsc),
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.dsc = sm6375_dsc,
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.pingpong_count = ARRAY_SIZE(sm6375_pp),
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.pingpong = sm6375_pp,
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.intf_count = ARRAY_SIZE(sm6375_intf),
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.intf = sm6375_intf,
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.vbif_count = ARRAY_SIZE(sdm845_vbif),
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.vbif = sdm845_vbif,
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.perf = &sm6375_perf_data,
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.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
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BIT(MDP_SSPP_TOP0_INTR2) | \
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BIT(MDP_SSPP_TOP0_HIST_INTR) | \
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BIT(MDP_INTF1_INTR) | \
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BIT(MDP_INTF1_TEAR_INTR),
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};
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#endif
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@ -750,6 +750,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
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#include "catalog/dpu_6_3_sm6115.h"
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#include "catalog/dpu_6_4_sm6350.h"
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#include "catalog/dpu_6_5_qcm2290.h"
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#include "catalog/dpu_6_9_sm6375.h"
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#include "catalog/dpu_7_0_sm8350.h"
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#include "catalog/dpu_7_2_sc7280.h"
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@ -834,6 +834,7 @@ extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
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extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
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extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
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extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
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extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
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extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
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extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
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extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg;
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@ -1306,6 +1306,7 @@ static const struct of_device_id dpu_dt_match[] = {
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{ .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
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{ .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
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{ .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
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{ .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
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{ .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
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{ .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
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{ .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
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