[PATCH] m68k: move cache functions into separate file
Move a few cache functions into its own file and fix flush_icache_range() so it can handle both kernel and user addresses correctly (assuming context is set correctly). Turn copy_to_user_page/copy_from_user_page into inline functions and add a missing cache flush. Signed-off-by: Roman Zippel <zippel@linux-m68k.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Roman Zippel
Linus Torvalds
parent
69f447cffb
commit
2855b97020
@ -2,7 +2,7 @@
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# Makefile for the linux m68k-specific parts of the memory manager.
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# Makefile for the linux m68k-specific parts of the memory manager.
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#
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#
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obj-y := init.o fault.o hwtest.o
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obj-y := cache.o init.o fault.o hwtest.o
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obj-$(CONFIG_MMU_MOTOROLA) += kmap.o memory.o motorola.o
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obj-$(CONFIG_MMU_MOTOROLA) += kmap.o memory.o motorola.o
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obj-$(CONFIG_MMU_SUN3) += sun3kmap.o sun3mmu.o
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obj-$(CONFIG_MMU_SUN3) += sun3kmap.o sun3mmu.o
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118
arch/m68k/mm/cache.c
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118
arch/m68k/mm/cache.c
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@ -0,0 +1,118 @@
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/*
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* linux/arch/m68k/mm/cache.c
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*
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* Instruction cache handling
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*
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* Copyright (C) 1995 Hamish Macdonald
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*/
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#include <linux/module.h>
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#include <asm/pgalloc.h>
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#include <asm/traps.h>
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static unsigned long virt_to_phys_slow(unsigned long vaddr)
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{
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if (CPU_IS_060) {
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unsigned long paddr;
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/* The PLPAR instruction causes an access error if the translation
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* is not possible. To catch this we use the same exception mechanism
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* as for user space accesses in <asm/uaccess.h>. */
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asm volatile (".chip 68060\n"
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"1: plpar (%0)\n"
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".chip 68k\n"
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"2:\n"
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".section .fixup,\"ax\"\n"
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" .even\n"
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"3: sub.l %0,%0\n"
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" jra 2b\n"
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".previous\n"
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".section __ex_table,\"a\"\n"
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" .align 4\n"
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" .long 1b,3b\n"
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".previous"
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: "=a" (paddr)
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: "0" (vaddr));
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return paddr;
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} else if (CPU_IS_040) {
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unsigned long mmusr;
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asm volatile (".chip 68040\n\t"
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"ptestr (%1)\n\t"
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"movec %%mmusr, %0\n\t"
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".chip 68k"
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: "=r" (mmusr)
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: "a" (vaddr));
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if (mmusr & MMU_R_040)
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return (mmusr & PAGE_MASK) | (vaddr & ~PAGE_MASK);
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} else {
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unsigned short mmusr;
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unsigned long *descaddr;
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asm volatile ("ptestr %3,%2@,#7,%0\n\t"
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"pmove %%psr,%1@"
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: "=a&" (descaddr)
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: "a" (&mmusr), "a" (vaddr), "d" (get_fs().seg));
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if (mmusr & (MMU_I|MMU_B|MMU_L))
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return 0;
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descaddr = phys_to_virt((unsigned long)descaddr);
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switch (mmusr & MMU_NUM) {
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case 1:
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return (*descaddr & 0xfe000000) | (vaddr & 0x01ffffff);
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case 2:
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return (*descaddr & 0xfffc0000) | (vaddr & 0x0003ffff);
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case 3:
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return (*descaddr & PAGE_MASK) | (vaddr & ~PAGE_MASK);
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}
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}
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return 0;
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}
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/* Push n pages at kernel virtual address and clear the icache */
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/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
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void flush_icache_range(unsigned long address, unsigned long endaddr)
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{
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if (CPU_IS_040_OR_060) {
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address &= PAGE_MASK;
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do {
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asm volatile ("nop\n\t"
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".chip 68040\n\t"
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"cpushp %%bc,(%0)\n\t"
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".chip 68k"
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: : "a" (virt_to_phys_slow(address)));
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address += PAGE_SIZE;
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} while (address < endaddr);
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} else {
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unsigned long tmp;
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asm volatile ("movec %%cacr,%0\n\t"
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"orw %1,%0\n\t"
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"movec %0,%%cacr"
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: "=&d" (tmp)
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: "di" (FLUSH_I));
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}
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}
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EXPORT_SYMBOL(flush_icache_range);
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void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
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unsigned long addr, int len)
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{
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if (CPU_IS_040_OR_060) {
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asm volatile ("nop\n\t"
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".chip 68040\n\t"
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"cpushp %%bc,(%0)\n\t"
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".chip 68k"
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: : "a" (page_to_phys(page)));
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} else {
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unsigned long tmp;
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asm volatile ("movec %%cacr,%0\n\t"
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"orw %1,%0\n\t"
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"movec %0,%%cacr"
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: "=&d" (tmp)
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: "di" (FLUSH_I));
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}
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}
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@ -354,110 +354,6 @@ void cache_push (unsigned long paddr, int len)
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#endif
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#endif
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}
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}
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static unsigned long virt_to_phys_slow(unsigned long vaddr)
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{
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if (CPU_IS_060) {
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mm_segment_t fs = get_fs();
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unsigned long paddr;
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set_fs(get_ds());
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/* The PLPAR instruction causes an access error if the translation
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* is not possible. To catch this we use the same exception mechanism
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* as for user space accesses in <asm/uaccess.h>. */
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asm volatile (".chip 68060\n"
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"1: plpar (%0)\n"
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".chip 68k\n"
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"2:\n"
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".section .fixup,\"ax\"\n"
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" .even\n"
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"3: sub.l %0,%0\n"
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" jra 2b\n"
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".previous\n"
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".section __ex_table,\"a\"\n"
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" .align 4\n"
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" .long 1b,3b\n"
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".previous"
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: "=a" (paddr)
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: "0" (vaddr));
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set_fs(fs);
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return paddr;
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} else if (CPU_IS_040) {
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mm_segment_t fs = get_fs();
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unsigned long mmusr;
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set_fs(get_ds());
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asm volatile (".chip 68040\n\t"
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"ptestr (%1)\n\t"
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"movec %%mmusr, %0\n\t"
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".chip 68k"
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: "=r" (mmusr)
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: "a" (vaddr));
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set_fs(fs);
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if (mmusr & MMU_R_040)
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return (mmusr & PAGE_MASK) | (vaddr & ~PAGE_MASK);
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} else {
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unsigned short mmusr;
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unsigned long *descaddr;
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asm volatile ("ptestr #5,%2@,#7,%0\n\t"
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"pmove %%psr,%1@"
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: "=a&" (descaddr)
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: "a" (&mmusr), "a" (vaddr));
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if (mmusr & (MMU_I|MMU_B|MMU_L))
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return 0;
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descaddr = phys_to_virt((unsigned long)descaddr);
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switch (mmusr & MMU_NUM) {
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case 1:
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return (*descaddr & 0xfe000000) | (vaddr & 0x01ffffff);
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case 2:
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return (*descaddr & 0xfffc0000) | (vaddr & 0x0003ffff);
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case 3:
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return (*descaddr & PAGE_MASK) | (vaddr & ~PAGE_MASK);
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}
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}
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return 0;
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}
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/* Push n pages at kernel virtual address and clear the icache */
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/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
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void flush_icache_range(unsigned long address, unsigned long endaddr)
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{
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if (CPU_IS_040_OR_060) {
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address &= PAGE_MASK;
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if (address >= PAGE_OFFSET && address < (unsigned long)high_memory) {
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do {
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asm volatile ("nop\n\t"
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".chip 68040\n\t"
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"cpushp %%bc,(%0)\n\t"
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".chip 68k"
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: : "a" (virt_to_phys((void *)address)));
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address += PAGE_SIZE;
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} while (address < endaddr);
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} else {
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do {
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asm volatile ("nop\n\t"
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".chip 68040\n\t"
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"cpushp %%bc,(%0)\n\t"
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".chip 68k"
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: : "a" (virt_to_phys_slow(address)));
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address += PAGE_SIZE;
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} while (address < endaddr);
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}
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} else {
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unsigned long tmp;
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asm volatile ("movec %%cacr,%0\n\t"
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"orw %1,%0\n\t"
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"movec %0,%%cacr"
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: "=&d" (tmp)
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: "di" (FLUSH_I));
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}
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}
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#ifndef CONFIG_SINGLE_MEMORY_CHUNK
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#ifndef CONFIG_SINGLE_MEMORY_CHUNK
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int mm_end_of_chunk (unsigned long addr, int len)
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int mm_end_of_chunk (unsigned long addr, int len)
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{
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{
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@ -130,20 +130,25 @@ static inline void __flush_page_to_ram(void *vaddr)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#define flush_icache_page(vma, page) __flush_page_to_ram(page_address(page))
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#define flush_icache_page(vma, page) __flush_page_to_ram(page_address(page))
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#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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flush_cache_page(vma, vaddr, page_to_pfn(page));\
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memcpy(dst, src, len); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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flush_cache_page(vma, vaddr, page_to_pfn(page));\
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memcpy(dst, src, len); \
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} while (0)
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extern void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
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unsigned long addr, int len);
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extern void flush_icache_range(unsigned long address, unsigned long endaddr);
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extern void flush_icache_range(unsigned long address, unsigned long endaddr);
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static inline void copy_to_user_page(struct vm_area_struct *vma,
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struct page *page, unsigned long vaddr,
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void *dst, void *src, int len)
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{
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flush_cache_page(vma, vaddr, page_to_pfn(page));
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memcpy(dst, src, len);
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flush_icache_user_range(vma, page, vaddr, len);
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}
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static inline void copy_from_user_page(struct vm_area_struct *vma,
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struct page *page, unsigned long vaddr,
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void *dst, void *src, int len)
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{
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flush_cache_page(vma, vaddr, page_to_pfn(page));
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memcpy(dst, src, len);
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}
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#endif /* _M68K_CACHEFLUSH_H */
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#endif /* _M68K_CACHEFLUSH_H */
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