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drm/tegra: Fix planar formats on Tegra186 and later

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Use the correct pitch when programming the DC_WIN_PLANAR_STORAGE_UV
register's PITCH_U field to ensure the correct value is used in all
cases. This isn't currently causing any problems because the pitch
for both U and V planes is always the same.

Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding
2022-01-12 09:40:34 +01:00
parent 025c6643a8
commit 28aa30b08d
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/tegra/hub.c
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@ -673,7 +673,7 @@ static void tegra_shared_plane_atomic_update(struct drm_plane *plane,
tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_V); tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_V);
tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_V); tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_V);
value = PITCH_U(fb->pitches[2]) | PITCH_V(fb->pitches[2]); value = PITCH_U(fb->pitches[1]) | PITCH_V(fb->pitches[2]);
tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE_UV); tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE_UV);
} else { } else {
tegra_plane_writel(p, 0, DC_WINBUF_START_ADDR_U); tegra_plane_writel(p, 0, DC_WINBUF_START_ADDR_U);