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drm/amd/powerplay: correct Vega20 gfxclk readout under DS

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Current implementation cannot report the correct gfxclk under DS.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan 2019-01-24 17:50:39 +08:00 committed by Alex Deucher
parent d2c460e753
commit 28e732dcd4
1 changed files with 9 additions and 5 deletions
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14
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
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@ -2013,16 +2013,20 @@ static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
{
struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
struct amdgpu_device *adev = hwmgr->adev;
SmuMetrics_t metrics_table;
uint32_t val_vid;
int ret = 0;
switch (idx) {
case AMDGPU_PP_SENSOR_GFX_SCLK:
ret = vega20_get_current_clk_freq(hwmgr,
PPCLK_GFXCLK,
(uint32_t *)value);
if (!ret)
*size = 4;
ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table,
TABLE_SMU_METRICS, true);
PP_ASSERT_WITH_CODE(!ret,
"Failed to export SMU METRICS table!",
return ret);
*((uint32_t *)value) = metrics_table.AverageGfxclkFrequency * 100;
*size = 4;
break;
case AMDGPU_PP_SENSOR_GFX_MCLK:
ret = vega20_get_current_clk_freq(hwmgr,