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cxl/region: Fix decoder interleave programming

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Jonathan notes:

"Curiously interleave ways = 1 for the EPs which is obviously wrong"

...while testing the latest CXL development branch on QEMU.

It turns out the region creation process failed to program the endpoint
decoders. This was missed because the default settings of x1 at 4K
intereleave still results in the region appearing to function. Jonathan
caught the bug by reverse mapping the translations that need to happen
for the QEMU support.

Link: https://lore.kernel.org/r/62e95fdf9f6e2_30440294e4@dwillia2-xfh.jf.intel.com.notmuch
Fixes: 384e624bb211 ("cxl/region: Attach endpoint decoders")
Reported-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165951146336.967013.11160153960900111443.stgit@dwillia2-xfh.jf.intel.com
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Dan Williams 2022-08-02 10:34:35 -07:00
parent 8732947b75
commit 2901c8bded
1 changed files with 3 additions and 0 deletions
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3
drivers/cxl/core/region.c
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@ -1255,6 +1255,9 @@ static int cxl_region_attach(struct cxl_region *cxlr,
p->state = CXL_CONFIG_ACTIVE;
}
cxled->cxld.interleave_ways = p->interleave_ways;
cxled->cxld.interleave_granularity = p->interleave_granularity;
return 0;
err_decrement: