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SoC changes for omap variants for v5.2 merge window

Browse Source 
This series of changes mostly consists of ti-sysc interconnect driver
 related preparation work. With these changes and the related ti-sysc
 driver changes, we can start dropping legacy omap_hwmod_*data.c platform
 data for many devices.
 
 There are also two am335x and am437x related PM changes for secure
 devices that have ROM handling some parts and needs EFUSE power domain
 active.
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Merge tag 'omap-for-v5.2/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/soc

SoC changes for omap variants for v5.2 merge window

This series of changes mostly consists of ti-sysc interconnect driver
related preparation work. With these changes and the related ti-sysc
driver changes, we can start dropping legacy omap_hwmod_*data.c platform
data for many devices.

There are also two am335x and am437x related PM changes for secure
devices that have ROM handling some parts and needs EFUSE power domain
active.

* tag 'omap-for-v5.2/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2+: pm33xx-core: Do not Turn OFF CEFUSE as PPA may be using it
  ARM: OMAP2+: Wakeupgen: AM43xx HS devices should save context like non-HS
  ARM: OMAP2+: Handle reset quirks for dynamically allocated modules
  ARM: OMAP2+: Remove hwmod .rev data and use local SoC checks instead
  ARM: OMAP2+: Allocate struct omap_hwmod based on dts data
  ARM: OMAP2+: Define _HWMOD_STATE_DEFAULT and use it
  ARM: OMAP2+: Prepare class allocation for dynamically allocated modules
  ARM: OMAP2+: Make interconnect target module allocation functions static
  ARM: OMAP2+: Fix potentially uninitialized return value for _setup_reset()
  ARM: dts: Fix dcan clkctrl clock for am3

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-04-28 23:02:56 -07:00
commit 29104e0149
19 changed files with 215 additions and 71 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/boot/dts/am33xx-l4.dtsi
View File

@ -1762,7 +1762,7 @@
reg = <0xcc000 0x4>;
reg-names = "rev";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM3_D_CAN0_CLKCTRL 0>;
clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
@ -1785,7 +1785,7 @@
reg = <0xd0000 0x4>;
reg-names = "rev";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM3_D_CAN1_CLKCTRL 0>;
clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;

9
arch/arm/mach-omap2/common.h
View File

@ -336,6 +336,15 @@ static inline void omap5_secondary_hyp_startup(void)
}
#endif
#ifdef CONFIG_SOC_DRA7XX
extern int dra7xx_pciess_reset(struct omap_hwmod *oh);
#else
static inline int dra7xx_pciess_reset(struct omap_hwmod *oh)
{
return 0;
}
#endif
void pdata_quirks_init(const struct of_device_id *);
void omap_auxdata_legacy_init(struct device *dev);
void omap_pcs_legacy_init(int irq, void (*rearm)(void));

11
arch/arm/mach-omap2/i2c.c
View File

@ -53,15 +53,10 @@ int omap_i2c_reset(struct omap_hwmod *oh)
u16 i2c_con;
int c = 0;
if (oh->class->rev == OMAP_I2C_IP_VERSION_2) {
i2c_con = OMAP4_I2C_CON_OFFSET;
} else if (oh->class->rev == OMAP_I2C_IP_VERSION_1) {
if (soc_is_omap24xx() || soc_is_omap34xx() || soc_is_am35xx())
i2c_con = OMAP2_I2C_CON_OFFSET;
} else {
WARN(1, "Cannot reset I2C block %s: unsupported revision\n",
oh->name);
return -EINVAL;
}
else
i2c_con = OMAP4_I2C_CON_OFFSET;
/* Disable I2C */
v = omap_hwmod_read(oh, i2c_con);

7
arch/arm/mach-omap2/io.c
View File

@ -411,14 +411,9 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
static void __init __maybe_unused omap_hwmod_init_postsetup(void)
{
u8 postsetup_state;
u8 postsetup_state = _HWMOD_STATE_DEFAULT;
/* Set the default postsetup state for all hwmods */
#ifdef CONFIG_PM
postsetup_state = _HWMOD_STATE_IDLE;
#else
postsetup_state = _HWMOD_STATE_ENABLED;
#endif
omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
}

8
arch/arm/mach-omap2/mmc.h
View File

@ -7,7 +7,15 @@
#define OMAP4_MMC_REG_OFFSET 0x100
struct omap_hwmod;
#ifdef CONFIG_SOC_OMAP2420
int omap_msdi_reset(struct omap_hwmod *oh);
#else
static inline int omap_msdi_reset(struct omap_hwmod *oh)
{
return 0;
}
#endif
/* called from board-specific card detection service routine */
extern void omap_mmc_notify_cover_event(struct device *dev, int slot,

4
arch/arm/mach-omap2/omap-wakeupgen.c
View File

@ -436,13 +436,13 @@ static int irq_notifier(struct notifier_block *self, unsigned long cmd, void *v)
{
switch (cmd) {
case CPU_CLUSTER_PM_ENTER:
if (omap_type() == OMAP2_DEVICE_TYPE_GP)
if (omap_type() == OMAP2_DEVICE_TYPE_GP || soc_is_am43xx())
irq_save_context();
else
irq_save_secure_context();
break;
case CPU_CLUSTER_PM_EXIT:
if (omap_type() == OMAP2_DEVICE_TYPE_GP)
if (omap_type() == OMAP2_DEVICE_TYPE_GP || soc_is_am43xx())
irq_restore_context();
break;
}

200
arch/arm/mach-omap2/omap_hwmod.c
View File

@ -155,6 +155,8 @@
#include "soc.h"
#include "common.h"
#include "clockdomain.h"
#include "hdq1w.h"
#include "mmc.h"
#include "powerdomain.h"
#include "cm2xxx.h"
#include "cm3xxx.h"
@ -165,6 +167,7 @@
#include "prm33xx.h"
#include "prminst44xx.h"
#include "pm.h"
#include "wd_timer.h"
/* Name of the OMAP hwmod for the MPU */
#define MPU_INITIATOR_NAME "mpu"
@ -204,6 +207,20 @@ struct clkctrl_provider {
static LIST_HEAD(clkctrl_providers);
/**
* struct omap_hwmod_reset - IP specific reset functions
* @match: string to match against the module name
* @len: number of characters to match
* @reset: IP specific reset function
*
* Used only in cases where struct omap_hwmod is dynamically allocated.
*/
struct omap_hwmod_reset {
const char *match;
int len;
int (*reset)(struct omap_hwmod *oh);
};
/**
* struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations
* @enable_module: function to enable a module (via MODULEMODE)
@ -235,6 +252,7 @@ static struct omap_hwmod_soc_ops soc_ops;
/* omap_hwmod_list contains all registered struct omap_hwmods */
static LIST_HEAD(omap_hwmod_list);
static DEFINE_MUTEX(list_lock);
/* mpu_oh: used to add/remove MPU initiator from sleepdep list */
static struct omap_hwmod *mpu_oh;
@ -2465,7 +2483,7 @@ static void _setup_iclk_autoidle(struct omap_hwmod *oh)
*/
static int _setup_reset(struct omap_hwmod *oh)
{
int r;
int r = 0;
if (oh->_state != _HWMOD_STATE_INITIALIZED)
return -EINVAL;
@ -2624,7 +2642,7 @@ static int _setup(struct omap_hwmod *oh, void *data)
* that the copy process would be relatively complex due to the large number
* of substructures.
*/
static int __init _register(struct omap_hwmod *oh)
static int _register(struct omap_hwmod *oh)
{
if (!oh || !oh->name || !oh->class || !oh->class->name ||
(oh->_state != _HWMOD_STATE_UNKNOWN))
@ -2663,7 +2681,7 @@ static int __init _register(struct omap_hwmod *oh)
* locking in this code. Changes to this assumption will require
* additional locking. Returns 0.
*/
static int __init _add_link(struct omap_hwmod_ocp_if *oi)
static int _add_link(struct omap_hwmod_ocp_if *oi)
{
pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name,
oi->slave->name);
@ -3241,9 +3259,10 @@ static int omap_hwmod_init_regbits(struct device *dev,
* @sysc_offs: sysc register offset
* @syss_offs: syss register offset
*/
int omap_hwmod_init_reg_offs(struct device *dev,
const struct ti_sysc_module_data *data,
s32 *rev_offs, s32 *sysc_offs, s32 *syss_offs)
static int omap_hwmod_init_reg_offs(struct device *dev,
const struct ti_sysc_module_data *data,
s32 *rev_offs, s32 *sysc_offs,
s32 *syss_offs)
{
*rev_offs = -ENODEV;
*sysc_offs = 0;
@ -3267,9 +3286,9 @@ int omap_hwmod_init_reg_offs(struct device *dev,
* @data: module data
* @sysc_flags: module configuration
*/
int omap_hwmod_init_sysc_flags(struct device *dev,
const struct ti_sysc_module_data *data,
u32 *sysc_flags)
static int omap_hwmod_init_sysc_flags(struct device *dev,
const struct ti_sysc_module_data *data,
u32 *sysc_flags)
{
*sysc_flags = 0;
@ -3341,9 +3360,9 @@ int omap_hwmod_init_sysc_flags(struct device *dev,
* @data: module data
* @idlemodes: module supported idle modes
*/
int omap_hwmod_init_idlemodes(struct device *dev,
const struct ti_sysc_module_data *data,
u32 *idlemodes)
static int omap_hwmod_init_idlemodes(struct device *dev,
const struct ti_sysc_module_data *data,
u32 *idlemodes)
{
*idlemodes = 0;
@ -3434,14 +3453,18 @@ static int omap_hwmod_check_module(struct device *dev,
*
* Note that the allocations here cannot use devm as ti-sysc can rebind.
*/
int omap_hwmod_allocate_module(struct device *dev, struct omap_hwmod *oh,
const struct ti_sysc_module_data *data,
struct sysc_regbits *sysc_fields,
s32 rev_offs, s32 sysc_offs, s32 syss_offs,
u32 sysc_flags, u32 idlemodes)
static int omap_hwmod_allocate_module(struct device *dev, struct omap_hwmod *oh,
const struct ti_sysc_module_data *data,
struct sysc_regbits *sysc_fields,
s32 rev_offs, s32 sysc_offs,
s32 syss_offs, u32 sysc_flags,
u32 idlemodes)
{
struct omap_hwmod_class_sysconfig *sysc;
struct omap_hwmod_class *class;
struct omap_hwmod_class *class = NULL;
struct omap_hwmod_ocp_if *oi = NULL;
struct clockdomain *clkdm = NULL;
struct clk *clk = NULL;
void __iomem *regs = NULL;
unsigned long flags;
@ -3465,26 +3488,128 @@ int omap_hwmod_allocate_module(struct device *dev, struct omap_hwmod *oh,
}
/*
* We need new oh->class as the other devices in the same class
* We may need a new oh->class as the other devices in the same class
* may not yet have ioremapped their registers.
*/
class = kmemdup(oh->class, sizeof(*oh->class), GFP_KERNEL);
if (!class)
return -ENOMEM;
if (oh->class->name && strcmp(oh->class->name, data->name)) {
class = kmemdup(oh->class, sizeof(*oh->class), GFP_KERNEL);
if (!class)
return -ENOMEM;
}
class->sysc = sysc;
if (list_empty(&oh->slave_ports)) {
oi = kcalloc(1, sizeof(*oi), GFP_KERNEL);
if (!oi)
return -ENOMEM;
/*
* Note that we assume interconnect interface clocks will be
* managed by the interconnect driver for OCPIF_SWSUP_IDLE case
* on omap24xx and omap3.
*/
oi->slave = oh;
oi->user = OCP_USER_MPU | OCP_USER_SDMA;
}
if (!oh->_clk) {
struct clk_hw_omap *hwclk;
clk = of_clk_get_by_name(dev->of_node, "fck");
if (!IS_ERR(clk))
clk_prepare(clk);
else
clk = NULL;
/*
* Populate clockdomain based on dts clock. It is needed for
* clkdm_deny_idle() and clkdm_allow_idle() until we have have
* interconnect driver and reset driver capable of blocking
* clockdomain idle during reset, enable and idle.
*/
if (clk) {
hwclk = to_clk_hw_omap(__clk_get_hw(clk));
if (hwclk && hwclk->clkdm_name)
clkdm = clkdm_lookup(hwclk->clkdm_name);
}
/*
* Note that we assume interconnect driver manages the clocks
* and do not need to populate oh->_clk for dynamically
* allocated modules.
*/
clk_unprepare(clk);
clk_put(clk);
}
spin_lock_irqsave(&oh->_lock, flags);
if (regs)
oh->_mpu_rt_va = regs;
oh->class = class;
if (class)
oh->class = class;
oh->class->sysc = sysc;
if (oi)
_add_link(oi);
if (clkdm)
oh->clkdm = clkdm;
oh->_state = _HWMOD_STATE_INITIALIZED;
oh->_postsetup_state = _HWMOD_STATE_DEFAULT;
_setup(oh, NULL);
spin_unlock_irqrestore(&oh->_lock, flags);
return 0;
}
static const struct omap_hwmod_reset omap24xx_reset_quirks[] = {
{ .match = "msdi", .len = 4, .reset = omap_msdi_reset, },
};
static const struct omap_hwmod_reset dra7_reset_quirks[] = {
{ .match = "pcie", .len = 4, .reset = dra7xx_pciess_reset, },
};
static const struct omap_hwmod_reset omap_reset_quirks[] = {
{ .match = "dss", .len = 3, .reset = omap_dss_reset, },
{ .match = "hdq1w", .len = 5, .reset = omap_hdq1w_reset, },
{ .match = "i2c", .len = 3, .reset = omap_i2c_reset, },
{ .match = "wd_timer", .len = 8, .reset = omap2_wd_timer_reset, },
};
static void
omap_hwmod_init_reset_quirk(struct device *dev, struct omap_hwmod *oh,
const struct ti_sysc_module_data *data,
const struct omap_hwmod_reset *quirks,
int quirks_sz)
{
const struct omap_hwmod_reset *quirk;
int i;
for (i = 0; i < quirks_sz; i++) {
quirk = &quirks[i];
if (!strncmp(data->name, quirk->match, quirk->len)) {
oh->class->reset = quirk->reset;
return;
}
}
}
static void
omap_hwmod_init_reset_quirks(struct device *dev, struct omap_hwmod *oh,
const struct ti_sysc_module_data *data)
{
if (soc_is_omap24xx())
omap_hwmod_init_reset_quirk(dev, oh, data,
omap24xx_reset_quirks,
ARRAY_SIZE(omap24xx_reset_quirks));
if (soc_is_dra7xx())
omap_hwmod_init_reset_quirk(dev, oh, data, dra7_reset_quirks,
ARRAY_SIZE(dra7_reset_quirks));
omap_hwmod_init_reset_quirk(dev, oh, data, omap_reset_quirks,
ARRAY_SIZE(omap_reset_quirks));
}
/**
* omap_hwmod_init_module - initialize new module
* @dev: struct device
@ -3505,8 +3630,31 @@ int omap_hwmod_init_module(struct device *dev,
return -EINVAL;
oh = _lookup(data->name);
if (!oh)
return -ENODEV;
if (!oh) {
oh = kzalloc(sizeof(*oh), GFP_KERNEL);
if (!oh)
return -ENOMEM;
oh->name = data->name;
oh->_state = _HWMOD_STATE_UNKNOWN;
lockdep_register_key(&oh->hwmod_key);
/* Unused, can be handled by PRM driver handling resets */
oh->prcm.omap4.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT;
oh->class = kzalloc(sizeof(*oh->class), GFP_KERNEL);
if (!oh->class) {
kfree(oh);
return -ENOMEM;
}
omap_hwmod_init_reset_quirks(dev, oh, data);
oh->class->name = data->name;
mutex_lock(&list_lock);
error = _register(oh);
mutex_unlock(&list_lock);
}
cookie->data = oh;

8
arch/arm/mach-omap2/omap_hwmod.h
View File

@ -493,11 +493,16 @@ struct omap_hwmod_omap4_prcm {
#define _HWMOD_STATE_IDLE 5
#define _HWMOD_STATE_DISABLED 6
#ifdef CONFIG_PM
#define _HWMOD_STATE_DEFAULT _HWMOD_STATE_IDLE
#else
#define _HWMOD_STATE_DEFAULT _HWMOD_STATE_ENABLED
#endif
/**
* struct omap_hwmod_class - the type of an IP block
* @name: name of the hwmod_class
* @sysc: device SYSCONFIG/SYSSTATUS register data
* @rev: revision of the IP class
* @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown
* @reset: ptr to fn to be executed in place of the standard hwmod reset fn
* @enable_preprogram: ptr to fn to be executed during device enable
@ -523,7 +528,6 @@ struct omap_hwmod_omap4_prcm {
struct omap_hwmod_class {
const char *name;
struct omap_hwmod_class_sysconfig *sysc;
u32 rev;
int (*pre_shutdown)(struct omap_hwmod *oh);
int (*reset)(struct omap_hwmod *oh);
int (*enable_preprogram)(struct omap_hwmod *oh);

1
arch/arm/mach-omap2/omap_hwmod_2420_data.c
View File

@ -91,7 +91,6 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
static struct omap_hwmod_class i2c_class = {
.name = "i2c",
.sysc = &i2c_sysc,
.rev = OMAP_I2C_IP_VERSION_1,
.reset = &omap_i2c_reset,
};

1
arch/arm/mach-omap2/omap_hwmod_2430_data.c
View File

@ -68,7 +68,6 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
static struct omap_hwmod_class i2c_class = {
.name = "i2c",
.sysc = &i2c_sysc,
.rev = OMAP_I2C_IP_VERSION_1,
.reset = &omap_i2c_reset,
};

1
arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
View File

@ -96,7 +96,6 @@ static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
.name = "gpio",
.sysc = &omap2xxx_gpio_sysc,
.rev = 0,
};
/* system dma */

2
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
View File

@ -534,7 +534,6 @@ static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
struct omap_hwmod_class am33xx_gpio_hwmod_class = {
.name = "gpio",
.sysc = &am33xx_gpio_sysc,
.rev = 2,
};
/* gpio1 */
@ -643,7 +642,6 @@ static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
static struct omap_hwmod_class i2c_class = {
.name = "i2c",
.sysc = &am33xx_i2c_sysc,
.rev = OMAP_I2C_IP_VERSION_2,
.reset = &omap_i2c_reset,
};

4
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
View File

@ -484,7 +484,6 @@ static struct omap_hwmod am35xx_uart4_hwmod = {
static struct omap_hwmod_class i2c_class = {
.name = "i2c",
.sysc = &i2c_sysc,
.rev = OMAP_I2C_IP_VERSION_1,
.reset = &omap_i2c_reset,
};
@ -707,7 +706,6 @@ static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
.name = "gpio",
.sysc = &omap3xxx_gpio_sysc,
.rev = 1,
};
/* gpio1 */
@ -1029,7 +1027,6 @@ static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
.name = "smartreflex",
.sysc = &omap34xx_sr_sysc,
.rev = 1,
};
static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
@ -1044,7 +1041,6 @@ static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
.name = "smartreflex",
.sysc = &omap36xx_sr_sysc,
.rev = 2,
};
/* SR1 */

3
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View File

@ -1075,7 +1075,6 @@ static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
.name = "gpio",
.sysc = &omap44xx_gpio_sysc,
.rev = 2,
};
/* gpio1 */
@ -1374,7 +1373,6 @@ static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
.name = "i2c",
.sysc = &omap44xx_i2c_sysc,
.rev = OMAP_I2C_IP_VERSION_2,
.reset = &omap_i2c_reset,
};
@ -2367,7 +2365,6 @@ static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
.name = "smartreflex",
.sysc = &omap44xx_smartreflex_sysc,
.rev = 2,
};
/* smartreflex_core */

2
arch/arm/mach-omap2/omap_hwmod_54xx_data.c
View File

@ -620,7 +620,6 @@ static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
.name = "gpio",
.sysc = &omap54xx_gpio_sysc,
.rev = 2,
};
/* gpio1 */
@ -819,7 +818,6 @@ static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
.name = "i2c",
.sysc = &omap54xx_i2c_sysc,
.reset = &omap_i2c_reset,
.rev = OMAP_I2C_IP_VERSION_2,
};
/* i2c1 */

7
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
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@ -693,7 +693,6 @@ static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
.name = "aes",
.sysc = &dra7xx_aes_sysc,
.rev = 2,
};
/* AES1 */
@ -737,7 +736,6 @@ static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
.name = "sham",
.sysc = &dra7xx_sha0_sysc,
.rev = 2,
};
struct omap_hwmod dra7xx_sha0_hwmod = {
@ -811,7 +809,6 @@ static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
.name = "gpio",
.sysc = &dra7xx_gpio_sysc,
.rev = 2,
};
/* gpio1 */
@ -1085,7 +1082,6 @@ static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
.name = "i2c",
.sysc = &dra7xx_i2c_sysc,
.reset = &omap_i2c_reset,
.rev = OMAP_I2C_IP_VERSION_2,
};
/* i2c1 */
@ -1832,7 +1828,7 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
* We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
* lines after asserting them.
*/
static int dra7xx_pciess_reset(struct omap_hwmod *oh)
int dra7xx_pciess_reset(struct omap_hwmod *oh)
{
int i;
@ -2019,7 +2015,6 @@ static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
.name = "smartreflex",
.sysc = &dra7xx_smartreflex_sysc,
.rev = 2,
};
/* smartreflex_core */

1
arch/arm/mach-omap2/omap_hwmod_81xx_data.c
View File

@ -484,7 +484,6 @@ static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = {
static struct omap_hwmod_class dm81xx_gpio_hwmod_class = {
.name = "gpio",
.sysc = &dm81xx_gpio_sysc,
.rev = 2,
};
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {

8
arch/arm/mach-omap2/pm33xx-core.c
View File

@ -51,10 +51,12 @@ static int amx3_common_init(void)
/* CEFUSE domain can be turned off post bootup */
cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm");
if (cefuse_pwrdm)
omap_set_pwrdm_state(cefuse_pwrdm, PWRDM_POWER_OFF);
else
if (!cefuse_pwrdm)
pr_err("PM: Failed to get cefuse_pwrdm\n");
else if (omap_type() != OMAP2_DEVICE_TYPE_GP)
pr_info("PM: Leaving EFUSE power domain active\n");
else
omap_set_pwrdm_state(cefuse_pwrdm, PWRDM_POWER_OFF);
return 0;
}

5
arch/arm/mach-omap2/sr_device.c
View File

@ -119,7 +119,10 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
}
sr_data->name = oh->name;
sr_data->ip_type = oh->class->rev;
if (cpu_is_omap343x())
sr_data->ip_type = 1;
else
sr_data->ip_type = 2;
sr_data->senn_mod = 0x1;
sr_data->senp_mod = 0x1;