wifi: rtw89: switch BANDEDGE and TX_SHAPE based on OFDMA trigger frame
There are some registers for transmit waveform control, two of them used in this change are for BANDEDGE and TX_SHAPE control. BANDEDGE controls whether to apply band edge filter to transmit waveform. TX_SHAPE controls whether to apply triangular mask to transmit waveform. It is found for some chip, these two should be turned off during OFDMA UL traffic for better performance. Signed-off-by: Eric Huang <echuang@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20221117063001.42967-3-pkshih@realtek.com
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@ -2237,6 +2237,7 @@ static void rtw89_track_work(struct work_struct *work)
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rtw89_phy_ra_update(rtwdev);
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rtw89_phy_cfo_track(rtwdev);
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rtw89_phy_tx_path_div_track(rtwdev);
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rtw89_phy_ul_tb_ctrl_track(rtwdev);
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if (rtwdev->lps_enabled && !rtwdev->btc.lps)
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rtw89_enter_lps_track(rtwdev);
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@ -2560,6 +2561,7 @@ int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev,
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rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta,
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BTC_ROLE_MSTS_STA_CONN_END);
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rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta->htc_template);
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rtw89_phy_ul_tb_assoc(rtwdev, rtwvif);
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}
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return ret;
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@ -2261,6 +2261,8 @@ struct rtw89_vif {
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bool wowlan_magic;
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bool is_hesta;
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bool last_a_ctrl;
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bool dyn_tb_bedge_en;
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u8 def_tri_idx;
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struct work_struct update_beacon_work;
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struct rtw89_addr_cam_entry addr_cam;
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struct rtw89_bssid_cam_entry bssid_cam;
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@ -2646,6 +2648,11 @@ struct rtw89_dig_regs {
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struct rtw89_reg_def p1_s20_pagcugc_en;
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};
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struct rtw89_phy_ul_tb_info {
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bool dyn_tb_tri_en;
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u8 def_if_bandedge;
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};
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struct rtw89_chip_info {
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enum rtw89_core_chip_id chip_id;
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const struct rtw89_chip_ops *ops;
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@ -2663,6 +2670,7 @@ struct rtw89_chip_info {
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u8 support_chanctx_num;
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u8 support_bands;
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bool support_bw160;
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bool support_ul_tb_ctrl;
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bool hw_sec_hdr;
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u8 rf_path_num;
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u8 tx_nss;
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@ -3585,6 +3593,7 @@ struct rtw89_dev {
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struct rtw89_phy_ch_info ch_info;
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struct rtw89_phy_bb_gain_info bb_gain;
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struct rtw89_phy_efuse_gain efuse_gain;
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struct rtw89_phy_ul_tb_info ul_tb_info;
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struct delayed_work track_work;
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struct delayed_work coex_act1_work;
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@ -27,6 +27,7 @@ enum rtw89_debug_mask {
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RTW89_DBG_SAR = BIT(16),
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RTW89_DBG_STATE = BIT(17),
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RTW89_DBG_WOW = BIT(18),
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RTW89_DBG_UL_TB = BIT(19),
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RTW89_DBG_UNEXP = BIT(31),
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};
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@ -2,6 +2,7 @@
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/* Copyright(c) 2019-2020 Realtek Corporation
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*/
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#include "coex.h"
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#include "debug.h"
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#include "fw.h"
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#include "mac.h"
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@ -9,7 +10,7 @@
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#include "ps.h"
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#include "reg.h"
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#include "sar.h"
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#include "coex.h"
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#include "util.h"
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static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev,
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const struct rtw89_ra_report *report)
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@ -2794,6 +2795,129 @@ void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val,
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cfo->packet_count++;
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}
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void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
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{
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const struct rtw89_chip_info *chip = rtwdev->chip;
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const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
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struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
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if (!chip->support_ul_tb_ctrl)
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return;
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rtwvif->def_tri_idx =
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rtw89_phy_read32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG);
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if (chip->chip_id == RTL8852B && rtwdev->hal.cv > CHIP_CBV)
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rtwvif->dyn_tb_bedge_en = false;
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else if (chan->band_type >= RTW89_BAND_5G &&
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chan->band_width >= RTW89_CHANNEL_WIDTH_40)
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rtwvif->dyn_tb_bedge_en = true;
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else
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rtwvif->dyn_tb_bedge_en = false;
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rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
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"[ULTB] def_if_bandedge=%d, def_tri_idx=%d\n",
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ul_tb_info->def_if_bandedge, rtwvif->def_tri_idx);
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rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
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"[ULTB] dyn_tb_begde_en=%d, dyn_tb_tri_en=%d\n",
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rtwvif->dyn_tb_bedge_en, ul_tb_info->dyn_tb_tri_en);
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}
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struct rtw89_phy_ul_tb_check_data {
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bool valid;
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bool high_tf_client;
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bool low_tf_client;
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bool dyn_tb_bedge_en;
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u8 def_tri_idx;
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};
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static
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void rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev *rtwdev,
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struct rtw89_vif *rtwvif,
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struct rtw89_phy_ul_tb_check_data *ul_tb_data)
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{
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struct rtw89_traffic_stats *stats = &rtwdev->stats;
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struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
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if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION)
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return;
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if (!vif->cfg.assoc)
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return;
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if (stats->rx_tf_periodic > UL_TB_TF_CNT_L2H_TH)
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ul_tb_data->high_tf_client = true;
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else if (stats->rx_tf_periodic < UL_TB_TF_CNT_H2L_TH)
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ul_tb_data->low_tf_client = true;
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ul_tb_data->valid = true;
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ul_tb_data->def_tri_idx = rtwvif->def_tri_idx;
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ul_tb_data->dyn_tb_bedge_en = rtwvif->dyn_tb_bedge_en;
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}
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void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev)
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{
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const struct rtw89_chip_info *chip = rtwdev->chip;
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struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
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struct rtw89_phy_ul_tb_check_data ul_tb_data = {};
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struct rtw89_vif *rtwvif;
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if (!chip->support_ul_tb_ctrl)
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return;
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if (rtwdev->total_sta_assoc != 1)
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return;
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rtw89_for_each_rtwvif(rtwdev, rtwvif)
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rtw89_phy_ul_tb_ctrl_check(rtwdev, rtwvif, &ul_tb_data);
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if (!ul_tb_data.valid)
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return;
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if (ul_tb_data.dyn_tb_bedge_en) {
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if (ul_tb_data.high_tf_client) {
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rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0);
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rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
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"[ULTB] Turn off if_bandedge\n");
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} else if (ul_tb_data.low_tf_client) {
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rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN,
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ul_tb_info->def_if_bandedge);
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rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
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"[ULTB] Set to default if_bandedge = %d\n",
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ul_tb_info->def_if_bandedge);
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}
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}
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if (ul_tb_info->dyn_tb_tri_en) {
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if (ul_tb_data.high_tf_client) {
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rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT,
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B_TXSHAPE_TRIANGULAR_CFG, 0);
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rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
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"[ULTB] Turn off Tx triangle\n");
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} else if (ul_tb_data.low_tf_client) {
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rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT,
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B_TXSHAPE_TRIANGULAR_CFG,
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ul_tb_data.def_tri_idx);
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rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
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"[ULTB] Set to default tx_shap_idx = %d\n",
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ul_tb_data.def_tri_idx);
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}
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}
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}
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static void rtw89_phy_ul_tb_info_init(struct rtw89_dev *rtwdev)
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{
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const struct rtw89_chip_info *chip = rtwdev->chip;
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struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
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if (!chip->support_ul_tb_ctrl)
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return;
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ul_tb_info->dyn_tb_tri_en = true;
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ul_tb_info->def_if_bandedge =
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rtw89_phy_read32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN);
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}
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static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev)
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{
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struct rtw89_phy_stat *phystat = &rtwdev->phystat;
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@ -3980,6 +4104,7 @@ void rtw89_phy_dm_init(struct rtw89_dev *rtwdev)
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rtw89_physts_parsing_init(rtwdev);
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rtw89_phy_dig_init(rtwdev);
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rtw89_phy_cfo_init(rtwdev);
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rtw89_phy_ul_tb_info_init(rtwdev);
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rtw89_phy_init_rf_nctl(rtwdev);
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rtw89_chip_rfk_init(rtwdev);
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@ -64,6 +64,9 @@
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#define MAX_CFO_TOLERANCE 30
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#define CFO_TF_CNT_TH 300
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#define UL_TB_TF_CNT_L2H_TH 100
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#define UL_TB_TF_CNT_H2L_TH 70
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#define CCX_MAX_PERIOD 2097
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#define CCX_MAX_PERIOD_UNIT 32
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#define MS_TO_4US_RATIO 250
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@ -550,5 +553,7 @@ void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif
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void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev,
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enum rtw89_mac_idx mac_idx,
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enum rtw89_tssi_bandedge_cfg bandedge_cfg);
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void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
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void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev);
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#endif
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@ -2082,6 +2082,7 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
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.support_bands = BIT(NL80211_BAND_2GHZ) |
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BIT(NL80211_BAND_5GHZ),
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.support_bw160 = false,
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.support_ul_tb_ctrl = false,
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.hw_sec_hdr = false,
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.rf_path_num = 2,
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.tx_nss = 2,
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@ -2452,6 +2452,7 @@ const struct rtw89_chip_info rtw8852b_chip_info = {
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.support_bands = BIT(NL80211_BAND_2GHZ) |
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BIT(NL80211_BAND_5GHZ),
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.support_bw160 = false,
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.support_ul_tb_ctrl = true,
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.hw_sec_hdr = false,
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.rf_path_num = 2,
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.tx_nss = 2,
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@ -2891,6 +2891,7 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
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BIT(NL80211_BAND_5GHZ) |
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BIT(NL80211_BAND_6GHZ),
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.support_bw160 = true,
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.support_ul_tb_ctrl = false,
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.hw_sec_hdr = true,
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.rf_path_num = 2,
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.tx_nss = 2,
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