ARM: dts: Group omap3 CM_CLKSEL1_EMU clocks
The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren <tony@atomide.com>
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c22a3d8cad
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@ -254,14 +254,87 @@
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reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>;
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};
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dpll3_m3_ck: dpll3_m3_ck@1140 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll3_ck>;
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ti,bit-shift = <16>;
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ti,max-div = <31>;
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/* CM_CLKSEL1_EMU */
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clock@1140 {
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compatible = "ti,clksel";
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reg = <0x1140>;
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ti,index-starts-at-one;
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#clock-cells = <2>;
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#address-cells = <0>;
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dpll3_m3_ck: clock-dpll3-m3 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clock-output-names = "dpll3_m3_ck";
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clocks = <&dpll3_ck>;
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ti,bit-shift = <16>;
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ti,max-div = <31>;
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ti,index-starts-at-one;
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};
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dpll4_m6_ck: clock-dpll4-m6 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clock-output-names = "dpll4_m6_ck";
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clocks = <&dpll4_ck>;
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ti,bit-shift = <24>;
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ti,max-div = <63>;
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ti,index-starts-at-one;
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};
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emu_src_mux_ck: clock-emu-src-mux {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clock-output-names = "emu_src_mux_ck";
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clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
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};
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pclk_fck: clock-pclk-fck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clock-output-names = "pclk_fck";
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clocks = <&emu_src_ck>;
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ti,bit-shift = <8>;
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ti,max-div = <7>;
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ti,index-starts-at-one;
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};
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pclkx2_fck: clock-pclkx2-fck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clock-output-names = "pclkx2_fck";
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clocks = <&emu_src_ck>;
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ti,bit-shift = <6>;
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ti,max-div = <3>;
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ti,index-starts-at-one;
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};
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atclk_fck: clock-atclk-fck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clock-output-names = "atclk_fck";
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clocks = <&emu_src_ck>;
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ti,bit-shift = <4>;
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ti,max-div = <3>;
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ti,index-starts-at-one;
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};
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traceclk_src_fck: clock-traceclk-src-fck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clock-output-names = "traceclk_src_fck";
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clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
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ti,bit-shift = <2>;
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};
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traceclk_fck: clock-traceclk-fck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clock-output-names = "traceclk_fck";
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clocks = <&traceclk_src_fck>;
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ti,bit-shift = <11>;
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ti,max-div = <7>;
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ti,index-starts-at-one;
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};
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};
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dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
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@ -500,16 +573,6 @@
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ti,set-rate-parent;
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};
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dpll4_m6_ck: dpll4_m6_ck@1140 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll4_ck>;
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ti,bit-shift = <24>;
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ti,max-div = <63>;
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reg = <0x1140>;
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ti,index-starts-at-one;
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};
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dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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@ -1633,67 +1696,12 @@
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};
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};
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emu_src_mux_ck: emu_src_mux_ck@1140 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
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reg = <0x1140>;
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};
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emu_src_ck: emu_src_ck {
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#clock-cells = <0>;
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compatible = "ti,clkdm-gate-clock";
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clocks = <&emu_src_mux_ck>;
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};
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pclk_fck: pclk_fck@1140 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&emu_src_ck>;
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ti,bit-shift = <8>;
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ti,max-div = <7>;
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reg = <0x1140>;
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ti,index-starts-at-one;
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};
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pclkx2_fck: pclkx2_fck@1140 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&emu_src_ck>;
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ti,bit-shift = <6>;
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ti,max-div = <3>;
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reg = <0x1140>;
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ti,index-starts-at-one;
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};
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atclk_fck: atclk_fck@1140 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&emu_src_ck>;
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ti,bit-shift = <4>;
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ti,max-div = <3>;
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reg = <0x1140>;
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ti,index-starts-at-one;
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};
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traceclk_src_fck: traceclk_src_fck@1140 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
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ti,bit-shift = <2>;
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reg = <0x1140>;
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};
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traceclk_fck: traceclk_fck@1140 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&traceclk_src_fck>;
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ti,bit-shift = <11>;
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ti,max-div = <7>;
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reg = <0x1140>;
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ti,index-starts-at-one;
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};
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secure_32k_fck: secure_32k_fck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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