Merge tag 'sunxi-clk-for-6.5-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Pull an Allwinner clk driver update from Jernej Skrabec: - Preselect PLL MIPI as TCON0 parent for A64 SoC * tag 'sunxi-clk-for-6.5-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux
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@ -528,11 +528,18 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
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0x104, 0, 4, 24, 3, BIT(31),
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0x104, 0, 4, 24, 3, BIT(31),
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CLK_SET_RATE_PARENT);
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CLK_SET_RATE_PARENT);
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/*
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* DSI output seems to work only when PLL_MIPI selected. Set it and prevent
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* the mux from reparenting.
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*/
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#define SUN50I_A64_TCON0_CLK_REG 0x118
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static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
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static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
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static const u8 tcon0_table[] = { 0, 2, };
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static const u8 tcon0_table[] = { 0, 2, };
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static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
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static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
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tcon0_table, 0x118, 24, 3, BIT(31),
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tcon0_table, 0x118, 24, 3, BIT(31),
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CLK_SET_RATE_PARENT);
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CLK_SET_RATE_PARENT |
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CLK_SET_RATE_NO_REPARENT);
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static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
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static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
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static const u8 tcon1_table[] = { 0, 2, };
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static const u8 tcon1_table[] = { 0, 2, };
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@ -953,6 +960,11 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
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writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
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writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
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/* Set PLL MIPI as parent for TCON0 */
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val = readl(reg + SUN50I_A64_TCON0_CLK_REG);
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val &= ~GENMASK(26, 24);
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writel(val | (0 << 24), reg + SUN50I_A64_TCON0_CLK_REG);
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ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc);
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ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc);
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if (ret)
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if (ret)
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return ret;
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return ret;
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