clk: rs9: Fix DIF OEn bit placement on 9FGV0241
On 9FGV0241, the DIF OE0 is BIT(1) and DIF OE1 is BIT(2), on the other chips like 9FGV0441 and 9FGV0841 DIF OE0 is BIT(0) and so on. Increment the index in BIT() macro instead of the result of BIT() macro to shift the bit correctly on 9FGV0241. Fixes: 603df193ec51 ("clk: rs9: Support device specific dif bit calculation") Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://lore.kernel.org/r/20231105200642.62792-1-marek.vasut+renesas@mailbox.org Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -163,7 +163,7 @@ static u8 rs9_calc_dif(const struct rs9_driver_data *rs9, int idx)
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enum rs9_model model = rs9->chip_info->model;
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if (model == RENESAS_9FGV0241)
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return BIT(idx) + 1;
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return BIT(idx + 1);
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else if (model == RENESAS_9FGV0441)
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return BIT(idx);
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