perf vendor events intel: Add alderlake metric constraints
Previously these constraints were disabled as they contained topdown events. Since: https://lore.kernel.org/all/20230312021543.3060328-9-irogers@google.com/ the topdown events are correctly grouped even if no group exists. This change was created by PR: https://github.com/intel/perfmon/pull/71 Signed-off-by: Ian Rogers <irogers@google.com> Tested-by: Kan Liang <kan.liang@linux.intel.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Ahmad Yasin <ahmad.yasin@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Cc: Caleb Biggers <caleb.biggers@intel.com> Cc: Edward Baker <edward.baker@intel.com> Cc: Florian Fischer <florian.fischer@muhq.space> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.g.garry@oracle.com> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Kang Minchul <tegongkang@gmail.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Perry Taylor <perry.taylor@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ravi Bangoria <ravi.bangoria@amd.com> Cc: Rob Herring <robh@kernel.org> Cc: Samantha Alt <samantha.alt@intel.com> Cc: Stephane Eranian <eranian@google.com> Cc: Sumanth Korikkar <sumanthk@linux.ibm.com> Cc: Suzuki Poulouse <suzuki.poulose@arm.com> Cc: Thomas Richter <tmricht@linux.ibm.com> Cc: Tiezhu Yang <yangtiezhu@loongson.cn> Cc: Weilin Wang <weilin.wang@intel.com> Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com> Cc: Yang Jihong <yangjihong1@huawei.com> Link: https://lore.kernel.org/r/20230502223851.2234828-6-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ian Rogers
Arnaldo Carvalho de Melo
parent
d3b52f71d1
commit
2a61d97fb0
@ -1077,6 +1077,7 @@
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},
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{
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"BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)",
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"MetricConstraint": "NO_GROUP_EVENTS",
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"MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector",
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"MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group",
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"MetricName": "tma_fp_arith",
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@ -1203,6 +1204,7 @@
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},
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{
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"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
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"MetricConstraint": "NO_GROUP_EVENTS",
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"MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_slots / BR_MISP_RETIRED.ALL_BRANCHES",
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"MetricGroup": "Bad;BrMispredicts;tma_issueBM",
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"MetricName": "tma_info_branch_misprediction_cost",
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@ -1255,6 +1257,7 @@
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},
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{
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"BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
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"MetricConstraint": "NO_GROUP_EVENTS",
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"MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if tma_info_smt_2t_utilization > 0.5 else 0)",
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"MetricGroup": "Cor;SMT",
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"MetricName": "tma_info_core_bound_likely",
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@ -1315,6 +1318,7 @@
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},
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{
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"BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck",
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"MetricConstraint": "NO_GROUP_EVENTS",
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"MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_lsd + tma_mite))",
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"MetricGroup": "DSBmiss;Fed;tma_issueFB",
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"MetricName": "tma_info_dsb_misses",
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@ -1408,6 +1412,7 @@
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},
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{
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"BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks",
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"MetricConstraint": "NO_GROUP_EVENTS",
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"MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_big_code",
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"MetricGroup": "Fed;FetchBW;Frontend",
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"MetricName": "tma_info_instruction_fetch_bw",
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@ -1827,6 +1832,7 @@
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},
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{
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"BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
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"MetricConstraint": "NO_GROUP_EVENTS",
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"MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))",
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"MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB",
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"MetricName": "tma_info_memory_data_tlbs",
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@ -1836,6 +1842,7 @@
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},
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{
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"BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
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"MetricConstraint": "NO_GROUP_EVENTS",
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"MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound))",
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"MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat",
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"MetricName": "tma_info_memory_latency",
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@ -1845,6 +1852,7 @@
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},
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{
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"BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
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"MetricConstraint": "NO_GROUP_EVENTS",
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"MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
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"MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM",
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"MetricName": "tma_info_mispredictions",
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@ -1877,6 +1885,7 @@
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},
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{
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"BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
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"MetricConstraint": "NO_GROUP_EVENTS",
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"MetricExpr": "tma_retiring * tma_info_slots / cpu_core@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
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"MetricGroup": "Pipeline;Ret",
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"MetricName": "tma_info_retire",
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@ -2152,6 +2161,7 @@
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},
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{
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"BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.",
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"MetricConstraint": "NO_GROUP_EVENTS",
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"MetricExpr": "tma_light_operations * MEM_UOP_RETIRED.ANY / (tma_retiring * tma_info_slots)",
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"MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
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"MetricName": "tma_memory_operations",
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@ -2231,6 +2241,7 @@
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},
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{
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"BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes",
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"MetricConstraint": "NO_GROUP_EVENTS",
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"MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_int_operations + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions))",
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"MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
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"MetricName": "tma_other_light_ops",
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