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drm/amd/powerplay/smu11: disable PLL shutdown when gfxoff enabled

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MP1 cannot access clock IP during MP1 FW reload, disable PLL
shutdown as a workaround.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jack Xiao 2019-05-06 16:28:22 +08:00 committed by Alex Deucher
parent 8c3b2d1bc0
commit 2a8bfa139a
1 changed files with 5 additions and 1 deletions
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6
drivers/gpu/drm/amd/powerplay/navi10_ppt.c
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@ -383,10 +383,14 @@ static int navi10_append_powerplay_table(struct smu_context *smu)
/* Mvdd Svi2 Div Ratio Setting */
smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
if (adev->pm.pp_feature & PP_GFXOFF_MASK)
if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
*(uint64_t *)smc_pptable->FeaturesToRun |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
| FEATURE_MASK(FEATURE_GFXOFF_BIT);
/* TODO: remove it once SMU fw fix it */
smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
}
return 0;
}