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drm/amd/display: Add NBIO reg offsets to DC

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[Why&How]
Add a field to store the NBIO IP offset for use with runtime offset
calculation

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Aurabindo Pillai 2022-04-04 13:38:57 -04:00 committed by Alex Deucher
parent e5028e9fd3
commit 2a93292fb7
4 changed files with 6 additions and 0 deletions
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1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
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@ -1565,6 +1565,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
init_data.flags.enable_mipi_converter_optimization = true;
init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
INIT_LIST_HEAD(&adev->dm.da_list);

2
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@ -863,6 +863,7 @@ static bool dc_construct_ctx(struct dc *dc,
dc_ctx->dc_stream_id_count = 0;
dc_ctx->dce_environment = init_params->dce_environment;
dc_ctx->dcn_reg_offsets = init_params->dcn_reg_offsets;
dc_ctx->nbio_reg_offsets = init_params->nbio_reg_offsets;
/* Create logger */
@ -1243,6 +1244,7 @@ struct dc *dc_create(const struct dc_init_data *init_params)
}
dc->dcn_reg_offsets = init_params->dcn_reg_offsets;
dc->nbio_reg_offsets = init_params->nbio_reg_offsets;
/* Populate versioning information */
dc->versions.dc_ver = DC_VER;

2
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -810,6 +810,7 @@ struct dc {
struct vm_helper *vm_helper;
uint32_t *dcn_reg_offsets;
uint32_t *nbio_reg_offsets;
};
enum frame_buffer_mode {
@ -857,6 +858,7 @@ struct dc_init_data {
* before them.
*/
uint32_t *dcn_reg_offsets;
uint32_t *nbio_reg_offsets;
};
struct dc_callback_init {

1
drivers/gpu/drm/amd/display/dc/dc_types.h
View File

@ -877,6 +877,7 @@ struct dc_context {
struct cp_psp cp_psp;
#endif
uint32_t *dcn_reg_offsets;
uint32_t *nbio_reg_offsets;
};
/* DSC DPCD capabilities */