mt76: mt76x02: use napi polling for tx cleanup
This allows tx scheduling and tx cleanup to run concurrently Signed-off-by: Felix Fietkau <nbd@nbd.name>
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091a79fd42
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2ac515a5d7
@ -89,7 +89,7 @@ struct mt76x02_dev {
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struct sk_buff *rx_head;
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struct tasklet_struct tx_tasklet;
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struct napi_struct tx_napi;
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struct tasklet_struct pre_tbtt_tasklet;
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struct delayed_work cal_work;
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struct delayed_work wdt_work;
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@ -154,18 +154,32 @@ static void mt76x02_process_tx_status_fifo(struct mt76x02_dev *dev)
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static void mt76x02_tx_tasklet(unsigned long data)
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{
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struct mt76x02_dev *dev = (struct mt76x02_dev *)data;
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mt76x02_mac_poll_tx_status(dev, false);
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mt76x02_process_tx_status_fifo(dev);
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mt76_txq_schedule_all(&dev->mt76);
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}
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int mt76x02_poll_tx(struct napi_struct *napi, int budget)
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{
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struct mt76x02_dev *dev = container_of(napi, struct mt76x02_dev, tx_napi);
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int i;
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mt76x02_process_tx_status_fifo(dev);
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mt76x02_mac_poll_tx_status(dev, false);
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for (i = MT_TXQ_MCU; i >= 0; i--)
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mt76_queue_tx_cleanup(dev, i, false);
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mt76x02_mac_poll_tx_status(dev, false);
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if (napi_complete_done(napi, 0))
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mt76x02_irq_enable(dev, MT_INT_TX_DONE_ALL);
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mt76_txq_schedule_all(&dev->mt76);
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for (i = MT_TXQ_MCU; i >= 0; i--)
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mt76_queue_tx_cleanup(dev, i, false);
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mt76x02_irq_enable(dev, MT_INT_TX_DONE_ALL);
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tasklet_schedule(&dev->mt76.tx_tasklet);
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return 0;
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}
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int mt76x02_dma_init(struct mt76x02_dev *dev)
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@ -223,7 +237,15 @@ int mt76x02_dma_init(struct mt76x02_dev *dev)
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if (ret)
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return ret;
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return mt76_init_queues(dev);
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ret = mt76_init_queues(dev);
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if (ret)
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return ret;
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netif_tx_napi_add(&dev->mt76.napi_dev, &dev->tx_napi, mt76x02_poll_tx,
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NAPI_POLL_WEIGHT);
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napi_enable(&dev->tx_napi);
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return 0;
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}
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EXPORT_SYMBOL_GPL(mt76x02_dma_init);
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@ -251,11 +273,6 @@ irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance)
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intr &= dev->mt76.mmio.irqmask;
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if (intr & MT_INT_TX_DONE_ALL) {
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mt76x02_irq_disable(dev, MT_INT_TX_DONE_ALL);
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tasklet_schedule(&dev->mt76.tx_tasklet);
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}
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if (intr & MT_INT_RX_DONE(0)) {
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mt76x02_irq_disable(dev, MT_INT_RX_DONE(0));
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napi_schedule(&dev->mt76.napi[0]);
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@ -277,9 +294,12 @@ irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance)
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mt76_queue_kick(dev, dev->mt76.q_tx[MT_TXQ_PSD].q);
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}
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if (intr & MT_INT_TX_STAT) {
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if (intr & MT_INT_TX_STAT)
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mt76x02_mac_poll_tx_status(dev, true);
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tasklet_schedule(&dev->mt76.tx_tasklet);
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if (intr & (MT_INT_TX_STAT | MT_INT_TX_DONE_ALL)) {
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mt76x02_irq_disable(dev, MT_INT_TX_DONE_ALL);
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napi_schedule(&dev->tx_napi);
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}
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if (intr & MT_INT_GPTIMER) {
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@ -310,6 +330,7 @@ static void mt76x02_dma_enable(struct mt76x02_dev *dev)
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void mt76x02_dma_cleanup(struct mt76x02_dev *dev)
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{
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tasklet_kill(&dev->mt76.tx_tasklet);
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netif_napi_del(&dev->tx_napi);
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mt76_dma_cleanup(&dev->mt76);
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}
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EXPORT_SYMBOL_GPL(mt76x02_dma_cleanup);
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@ -429,6 +450,7 @@ static void mt76x02_watchdog_reset(struct mt76x02_dev *dev)
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tasklet_disable(&dev->pre_tbtt_tasklet);
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tasklet_disable(&dev->mt76.tx_tasklet);
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napi_disable(&dev->tx_napi);
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for (i = 0; i < ARRAY_SIZE(dev->mt76.napi); i++)
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napi_disable(&dev->mt76.napi[i]);
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@ -482,7 +504,8 @@ static void mt76x02_watchdog_reset(struct mt76x02_dev *dev)
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clear_bit(MT76_RESET, &dev->mt76.state);
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tasklet_enable(&dev->mt76.tx_tasklet);
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tasklet_schedule(&dev->mt76.tx_tasklet);
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napi_enable(&dev->tx_napi);
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napi_schedule(&dev->tx_napi);
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tasklet_enable(&dev->pre_tbtt_tasklet);
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