arm64: kvm: mte: Hide the MTE CPUID information from the guests
KVM does not support MTE in guests yet, so clear the corresponding field in the ID_AA64PFR1_EL1 register. In addition, inject an undefined exception in the guest if it accesses one of the GCR_EL1, RGSR_EL1, TFSR_EL1 or TFSRE0_EL1 registers. While the emulate_sys_reg() function already injects an undefined exception, this patch prevents the unnecessary printk. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Steven Price <steven.price@arm.com> Acked-by: Marc Zyngier <maz@kernel.org>
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@ -1131,6 +1131,8 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
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if (!vcpu_has_sve(vcpu))
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val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
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val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT);
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} else if (id == SYS_ID_AA64PFR1_EL1) {
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val &= ~(0xfUL << ID_AA64PFR1_MTE_SHIFT);
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} else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) {
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val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) |
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(0xfUL << ID_AA64ISAR1_API_SHIFT) |
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@ -1382,6 +1384,13 @@ static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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return true;
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}
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static bool access_mte_regs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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const struct sys_reg_desc *r)
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{
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kvm_inject_undefined(vcpu);
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return false;
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}
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/* sys_reg_desc initialiser for known cpufeature ID registers */
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#define ID_SANITISED(name) { \
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SYS_DESC(SYS_##name), \
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@ -1547,6 +1556,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
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{ SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
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{ SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },
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{ SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
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{ SYS_DESC(SYS_RGSR_EL1), access_mte_regs },
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{ SYS_DESC(SYS_GCR_EL1), access_mte_regs },
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{ SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
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{ SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
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{ SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
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@ -1571,6 +1584,9 @@ static const struct sys_reg_desc sys_reg_descs[] = {
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{ SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
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{ SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
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{ SYS_DESC(SYS_TFSR_EL1), access_mte_regs },
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{ SYS_DESC(SYS_TFSRE0_EL1), access_mte_regs },
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{ SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
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{ SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
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